diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2015-10-29 10:37:28 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-02-22 09:16:34 -0800 |
| commit | e10842167b5529a45433ba9e33097dc853065aba (patch) | |
| tree | 1d91738b1599b172ed6e7372070bcd8616cd957f /docs | |
| parent | e0d4158c71c4fd9fdde8875f71043a9c152bddfb (diff) | |
Tegra: init normal/crash console for platforms
The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.
This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.
Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/plat/nvidia-tegra.md | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index e6ec4622..f82085b1 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -65,14 +65,17 @@ to the build command line. The Tegra platform code expects a pointer to the following platform specific structure via 'x1' register from the BL2 layer which is used by the bl31_early_platform_setup() handler to extract the TZDRAM carveout base and -size for loading the Trusted OS. The Tegra memory controller driver programs -this base/size in order to restrict NS accesses. +size for loading the Trusted OS and the UART port ID to be used. The Tegra +memory controller driver programs this base/size in order to restrict NS +accesses. typedef struct plat_params_from_bl2 { /* TZ memory size */ uint64_t tzdram_size; /* TZ memory base */ uint64_t tzdram_base; + /* UART port ID */ + int uart_id; } plat_params_from_bl2_t; Power Management |