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| author | dp-arm <dimitris.papastamos@arm.com> | 2017-05-23 09:32:49 +0100 |
|---|---|---|
| committer | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2017-06-22 10:33:19 +0100 |
| commit | d832aee900a92d14a08a6a2a552894188404b6a4 (patch) | |
| tree | f1e12914f0bc1f687509f1b7fbbaf172a335acfd /docs | |
| parent | 18f2efd67d881fe0a9a535ce9e801e60d746e024 (diff) | |
aarch64: Enable Statistical Profiling Extensions for lower ELs
SPE is only supported in non-secure state. Accesses to SPE specific
registers from SEL1 will trap to EL3. During a world switch, before
`TTBR` is modified the SPE profiling buffers are drained. This is to
avoid a potential invalid memory access in SEL1.
SPE is architecturally specified only for AArch64.
Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/user-guide.md | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/docs/user-guide.md b/docs/user-guide.md index 0065ac01..d5423ca3 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -542,6 +542,11 @@ performed. cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0. +* `ENABLE_SPE_FOR_LOWER_ELS` : Boolean option to enable Statistical Profiling + extensions. This is an optional architectural feature available only for + AArch64 8.2 onwards. This option defaults to 1 but is automatically + disabled when the target architecture is AArch32 or AArch64 8.0/8.1. + #### ARM development platform specific build options * `ARM_BL31_IN_DRAM`: Boolean option to select loading of BL31 in TZC secured |