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| author | David Cunado <david.cunado@arm.com> | 2017-04-13 22:38:29 +0100 |
|---|---|---|
| committer | David Cunado <david.cunado@arm.com> | 2017-06-21 17:57:54 +0100 |
| commit | 18f2efd67d881fe0a9a535ce9e801e60d746e024 (patch) | |
| tree | 5c02488f3d5e7c29035e51f65fbe8b83fad74026 /docs | |
| parent | b1187232fdf819586ba8c8ece4a27a7515cbdc6d (diff) | |
Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully
initialises essential control registers rather then relying on hardware
to set the reset values.
The context management functions are also updated to fully initialise
the appropriate control registers when initialising the non-secure and
secure context structures and when preparing to leave EL3 for a lower
EL.
This gives better alignement with the ARM ARM which states that software
must initialise RES0 and RES1 fields with 0 / 1.
This patch also corrects the following typos:
"NASCR definitions" -> "NSACR definitions"
Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc
Signed-off-by: David Cunado <david.cunado@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/firmware-design.md | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/docs/firmware-design.md b/docs/firmware-design.md index 358292ab..746e4131 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -220,6 +220,12 @@ BL1 performs minimal architectural initialization as follows. - `DAIF`. The SError interrupt is enabled by clearing the SError interrupt mask bit. + - `MDCR_EL3`. The trap controls, `MDCR_EL3.TDOSA`, `MDCR_EL3.TDA` and + `MDCR_EL3.TPM`, are set so that accesses to the registers they control + do not trap to EL3. AArch64 Secure self-hosted debug is disabled by + setting the `MDCR_EL3.SDD` bit. Also `MDCR_EL3.SPD32` is set to + disable AArch32 Secure self-hosted privileged debug from S-EL1. + * Control register setup (for AArch32) - `SCTLR`. Instruction cache is enabled by setting the `SCTLR.I` bit. Alignment checking is enabled by setting the `SCTLR.A` bit. @@ -243,6 +249,9 @@ BL1 performs minimal architectural initialization as follows. - `CPSR.A`. The Asynchronous data abort interrupt is enabled by clearing the Asynchronous data abort interrupt mask bit. + - `SDCR`. The `SDCR.SPD` field is set to disable AArch32 Secure + self-hosted privileged debug. + #### Platform initialization On ARM platforms, BL1 performs the following platform initializations: |