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| author | Paul Beesley <paul.beesley@arm.com> | 2019-10-04 16:17:46 +0000 |
|---|---|---|
| committer | Paul Beesley <paul.beesley@arm.com> | 2019-10-11 12:39:06 +0000 |
| commit | be653a6940b6c7bf3c0c6b7049ae829fa70863c1 (patch) | |
| tree | e0f14828750f595ee14a7ad836b8a56deea252f4 /docs/security_advisories | |
| parent | 6f0c77f0c7c224b0e4be2aaf3cfedcbdcba9a144 (diff) | |
doc: Misc syntax and spelling fixes
Tidying up a few Sphinx warnings that had built-up over time.
None of these are critical but it cleans up the Sphinx output.
At the same time, fixing some spelling errors that were detected.
Change-Id: I38209e235481eed287f8008c6de9dedd6b12ab2e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Diffstat (limited to 'docs/security_advisories')
| -rw-r--r-- | docs/security_advisories/security-advisory-tfv-6.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/security_advisories/security-advisory-tfv-6.rst b/docs/security_advisories/security-advisory-tfv-6.rst index 495eddda..9eeaeec5 100644 --- a/docs/security_advisories/security-advisory-tfv-6.rst +++ b/docs/security_advisories/security-advisory-tfv-6.rst @@ -51,7 +51,7 @@ the MMU. For Cortex-A73 and Cortex-A75 CPUs, the PRs in this advisory invalidate the branch predictor when entering EL3 by temporarily dropping into AArch32 Secure-EL1 and executing the ``BPIALL`` instruction. This workaround is -signifiantly more complex than the "MMU disable/enable" workaround. The latter +significantly more complex than the "MMU disable/enable" workaround. The latter is not effective at invalidating the branch predictor on Cortex-A73/Cortex-A75. Note that if other privileged software, for example a Rich OS kernel, implements |