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| author | Harvey Hsieh <hhsieh@nvidia.com> | 2016-11-23 19:13:08 +0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-01-16 10:10:52 -0800 |
| commit | b495791ba28ae36078e09d32877fca8e97088410 (patch) | |
| tree | 7c8d1f779947b6b7dc33dcd6220ed43f4f30e11a /docs/plat | |
| parent | 322e7c3e003cdcf954fb1e82cb9184405e053d03 (diff) | |
Tegra: support to set the L2 ECC and Parity enable bit
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.
* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4
Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'docs/plat')
| -rw-r--r-- | docs/plat/nvidia-tegra.rst | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst index 56dfacfc..e244c1c9 100644 --- a/docs/plat/nvidia-tegra.rst +++ b/docs/plat/nvidia-tegra.rst @@ -80,6 +80,8 @@ uint64\_t tzdram\_size; uint64\_t tzdram\_base; /* UART port ID \*/ int uart\_id; +/* L2 ECC parity protection disable flag \*/ +int l2\_ecc\_parity\_prot\_dis; } plat\_params\_from\_bl2\_t; Power Management |