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| author | Varun Wadekar <vwadekar@nvidia.com> | 2015-07-31 10:15:41 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2015-07-31 10:26:22 +0530 |
| commit | 2ee2c4f0bb5f764cba9f306d1ccd6ef536dd1d59 (patch) | |
| tree | 13e08e84202a59d36aa67921a62257c968750b9a /docs/plat | |
| parent | 0bf1b022f29147bdbab825947c07ed4509eac7fc (diff) | |
Tegra132: set TZDRAM_BASE to 0xF5C00000
The TZDRAM base on the reference platform has been bumped up due to
some BL2 memory cleanup. Platforms can also use a different TZDRAM
base by setting TZDRAM_BASE=<value> in the build command line.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'docs/plat')
| -rw-r--r-- | docs/plat/nvidia-tegra.md | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index 6c76dd10..d8e8ec63 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -59,6 +59,9 @@ Preparing the BL31 image to run on Tegra SoCs 'CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> all' +Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>' +to the build command line. + Power Management ================ The PSCI implementation expects each platform to expose the 'power state' |