diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2015-05-19 16:48:04 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2015-05-29 16:43:25 +0530 |
| commit | 08438e24e10504642634da9ee3dde794ac6fa8f0 (patch) | |
| tree | b089a797094d671c9bbc43bf30f42f2e33625b21 /docs/plat | |
| parent | c13b2e32f1391a1678c258a01286f100df67cd33 (diff) | |
Support for NVIDIA's Tegra T210 SoCs
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.
This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'docs/plat')
| -rw-r--r-- | docs/plat/nvidia-tegra.md | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md new file mode 100644 index 00000000..242e8db6 --- /dev/null +++ b/docs/plat/nvidia-tegra.md @@ -0,0 +1,21 @@ +Tegra-T210 Overview +==================== + +T210 has Quad ARM® Cortex®-A57 cores in a switched configuration with a +companion set of quad ARM Cortex-A53 cores. The Cortex-A57 and A53 cores +support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code +including legacy ARMv7 applications. The Cortex-A57 processors each have +48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared +Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction +and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache. + +Directory structure +==================== + +* plat/nvidia/tegra/common - Common code for all Tegra SoCs +* plat/nvidia/tegra/soc/txxx - Chip specific code + +Preparing the BL31 image to run on Tegra SoCs +=================================================== +CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ +TARGET_SOC=<target-soc e.g. t210> all |