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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2019-07-04 06:58:51 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-07-04 06:58:51 +0000 |
| commit | bb2d778c749ed772be8a2eb6f08356d2d03d9b1a (patch) | |
| tree | ccbf67ba40831b10dbc279d8f3f4464838eeb1c2 /docs/design | |
| parent | b01e0ad5cd0e6a752ef6b3481b0040d7ecd780e1 (diff) | |
| parent | 7d6f751867a6c778280d931857663a3218251609 (diff) | |
Merge changes from topic "lw/n1_errata_fixes" into integration
* changes:
Removing redundant ISB instructions
Workaround for Neoverse N1 erratum 1275112
Workaround for Neoverse N1 erratum 1262888
Workaround for Neoverse N1 erratum 1262606
Workaround for Neoverse N1 erratum 1257314
Workaround for Neoverse N1 erratum 1220197
Workaround for Neoverse N1 erratum 1207823
Workaround for Neoverse N1 erratum 1165347
Workaround for Neoverse N1 erratum 1130799
Workaround for Neoverse N1 erratum 1073348
Diffstat (limited to 'docs/design')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 6b524c24..d3fe89d6 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -226,6 +226,35 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +For Neoverse N1, the following errata build flags are defined : + +- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. + +- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + +- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + +- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + +- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r2p0 of the CPU. + +- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + +- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + +- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + +- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. |