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| author | lauwal01 <lauren.wehrmeister@arm.com> | 2019-06-24 11:44:58 -0500 |
|---|---|---|
| committer | lauwal01 <lauren.wehrmeister@arm.com> | 2019-07-02 09:16:54 -0500 |
| commit | 411f4959b45b7a072b567dadf33b110936f14f32 (patch) | |
| tree | 1ed19f9f44816e4c7fdaafb00457b5d51361e0d3 /docs/design | |
| parent | 335b3c79c79dcfc04e9776ce2e21c3b16aa6febf (diff) | |
Workaround for Neoverse N1 erratum 1262606
Neoverse N1 erratum 1262606 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Diffstat (limited to 'docs/design')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 14dfe958..1ed7cebe 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -246,6 +246,9 @@ For Neoverse N1, the following errata build flags are defined : - ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revision <= r3p0 of the CPU. + - ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. |