diff options
| author | Gerald Lejeune <gerald.lejeune@st.com> | 2016-03-22 09:29:23 +0100 |
|---|---|---|
| committer | Gerald Lejeune <gerald.lejeune@st.com> | 2016-03-30 17:26:23 +0200 |
| commit | adb4fcfb4c515a9b9af68d386ed1350505480655 (patch) | |
| tree | 9087d2aa75bc34f41290504025576434a1947786 /common | |
| parent | 6b1ca8f35802fddc530e1a5f2be7b82ddbab6917 (diff) | |
Enable asynchronous abort exceptions during boot
Asynchronous abort exceptions generated by the platform during cold boot are
not taken in EL3 unless SCR_EL3.EA is set.
Therefore EA bit is set along with RES1 bits in early BL1 and BL31 architecture
initialisation. Further write accesses to SCR_EL3 preserve these bits during
cold boot.
A build flag controls SCR_EL3.EA value to keep asynchronous abort exceptions
being trapped by EL3 after cold boot or not.
For further reference SError Interrupts are also known as asynchronous external
aborts.
On Cortex-A53 revisions below r0p2, asynchronous abort exceptions are taken in
EL3 whatever the SCR_EL3.EA value is.
Fixes arm-software/tf-issues#368
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Diffstat (limited to 'common')
| -rw-r--r-- | common/context_mgmt.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/common/context_mgmt.c b/common/context_mgmt.c index 68ec8945..586d42a4 100644 --- a/common/context_mgmt.c +++ b/common/context_mgmt.c @@ -111,6 +111,11 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t if (EP_GET_ST(ep->h.attr)) scr_el3 |= SCR_ST_BIT; +#ifndef HANDLE_EA_EL3_FIRST + /* Explicitly stop to trap aborts from lower exception levels. */ + scr_el3 &= ~SCR_EA_BIT; +#endif + #if IMAGE_BL31 /* * IRQ/FIQ bits only need setting if interrupt routing |