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authorJeenu Viswambharan <jeenu.viswambharan@arm.com>2016-11-30 15:21:11 +0000
committerJeenu Viswambharan <jeenu.viswambharan@arm.com>2016-12-05 14:55:35 +0000
commita806dad58c4cf752238d7bbffbc9a1ce17f63cea (patch)
tree9981b72bc40a9169972103ca315549d8a35bb052 /common
parentc59428b1502f37c9b2f551613da1b491c4226d10 (diff)
Define and use no_ret macro where no return is expected
There are many instances in ARM Trusted Firmware where control is transferred to functions from which return isn't expected. Such jumps are made using 'bl' instruction to provide the callee with the location from which it was jumped to. Additionally, debuggers infer the caller by examining where 'lr' register points to. If a 'bl' of the nature described above falls at the end of an assembly function, 'lr' will be left pointing to a location outside of the function range. This misleads the debugger back trace. This patch defines a 'no_ret' macro to be used when jumping to functions from which return isn't expected. The macro ensures to use 'bl' instruction for the jump, and also, for debug builds, places a 'nop' instruction immediately thereafter (unless instructed otherwise) so as to leave 'lr' pointing within the function range. Change-Id: Ib34c69fc09197cfd57bc06e147cc8252910e01b0 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'common')
-rw-r--r--common/aarch32/debug.S4
-rw-r--r--common/aarch64/debug.S2
-rw-r--r--common/aarch64/early_exceptions.S32
3 files changed, 19 insertions, 19 deletions
diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S
index 6be69512..cfce7ed9 100644
--- a/common/aarch32/debug.S
+++ b/common/aarch32/debug.S
@@ -38,7 +38,7 @@
* The common implementation of do_panic for all BL stages
***********************************************************/
func do_panic
- b plat_panic_handler
+ no_ret plat_panic_handler
endfunc do_panic
/***********************************************************
@@ -50,5 +50,5 @@ func report_exception
mrs r0, cpsr
and r0, #MODE32_MASK
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
endfunc report_exception
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index d3538792..9dd53ca9 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -191,5 +191,5 @@ _panic_handler:
/* Pass to plat_panic_handler the address from where el3_panic was
* called, not the address of the call from el3_panic. */
mov x30,x6
- b plat_panic_handler
+ no_ret plat_panic_handler
endfunc do_panic
diff --git a/common/aarch64/early_exceptions.S b/common/aarch64/early_exceptions.S
index ad5b4d86..be214596 100644
--- a/common/aarch64/early_exceptions.S
+++ b/common/aarch64/early_exceptions.S
@@ -47,25 +47,25 @@ vector_base early_exceptions
vector_entry SynchronousExceptionSP0
mov x0, #SYNC_EXCEPTION_SP_EL0
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size SynchronousExceptionSP0
vector_entry IrqSP0
mov x0, #IRQ_SP_EL0
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size IrqSP0
vector_entry FiqSP0
mov x0, #FIQ_SP_EL0
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size FiqSP0
vector_entry SErrorSP0
mov x0, #SERROR_SP_EL0
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size SErrorSP0
/* -----------------------------------------------------
@@ -75,25 +75,25 @@ vector_entry SErrorSP0
vector_entry SynchronousExceptionSPx
mov x0, #SYNC_EXCEPTION_SP_ELX
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size SynchronousExceptionSPx
vector_entry IrqSPx
mov x0, #IRQ_SP_ELX
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size IrqSPx
vector_entry FiqSPx
mov x0, #FIQ_SP_ELX
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size FiqSPx
vector_entry SErrorSPx
mov x0, #SERROR_SP_ELX
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size SErrorSPx
/* -----------------------------------------------------
@@ -103,25 +103,25 @@ vector_entry SErrorSPx
vector_entry SynchronousExceptionA64
mov x0, #SYNC_EXCEPTION_AARCH64
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size SynchronousExceptionA64
vector_entry IrqA64
mov x0, #IRQ_AARCH64
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size IrqA64
vector_entry FiqA64
mov x0, #FIQ_AARCH64
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size FiqA64
vector_entry SErrorA64
mov x0, #SERROR_AARCH64
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size SErrorA64
/* -----------------------------------------------------
@@ -131,23 +131,23 @@ vector_entry SErrorA64
vector_entry SynchronousExceptionA32
mov x0, #SYNC_EXCEPTION_AARCH32
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size SynchronousExceptionA32
vector_entry IrqA32
mov x0, #IRQ_AARCH32
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size IrqA32
vector_entry FiqA32
mov x0, #FIQ_AARCH32
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size FiqA32
vector_entry SErrorA32
mov x0, #SERROR_AARCH32
bl plat_report_exception
- bl plat_panic_handler
+ no_ret plat_panic_handler
check_vector_size SErrorA32