diff options
| author | danh-arm <dan.handley@arm.com> | 2016-06-03 15:12:37 +0100 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2016-06-03 15:12:37 +0100 |
| commit | 8d8c61ea75d668ce4f13e5f7ebc5e56741b3f1bd (patch) | |
| tree | 939fed21a2d2ddbb5dfec8234f5dff27e601078a /common | |
| parent | a7e530331d7cf4b58618f0715e61b5a872176f07 (diff) | |
| parent | 8cd16e6b5b4a83a2cf704362b9acb1c2eea1417e (diff) | |
Merge pull request #636 from soby-mathew/sm/cpu_ctx_rem_aarch32_regs
Build option to include AArch32 registers in cpu context
Diffstat (limited to 'common')
| -rw-r--r-- | common/aarch64/context.S | 66 |
1 files changed, 35 insertions, 31 deletions
diff --git a/common/aarch64/context.S b/common/aarch64/context.S index 0baa9b2f..d51daa78 100644 --- a/common/aarch64/context.S +++ b/common/aarch64/context.S @@ -57,14 +57,6 @@ func el1_sysregs_context_save mrs x10, elr_el1 stp x9, x10, [x0, #CTX_SPSR_EL1] - mrs x11, spsr_abt - mrs x12, spsr_und - stp x11, x12, [x0, #CTX_SPSR_ABT] - - mrs x13, spsr_irq - mrs x14, spsr_fiq - stp x13, x14, [x0, #CTX_SPSR_IRQ] - mrs x15, sctlr_el1 mrs x16, actlr_el1 stp x15, x16, [x0, #CTX_SCTLR_EL1] @@ -93,10 +85,6 @@ func el1_sysregs_context_save mrs x10, tpidrro_el0 stp x9, x10, [x0, #CTX_TPIDR_EL0] - mrs x11, dacr32_el2 - mrs x12, ifsr32_el2 - stp x11, x12, [x0, #CTX_DACR32_EL2] - mrs x13, par_el1 mrs x14, far_el1 stp x13, x14, [x0, #CTX_PAR_EL1] @@ -109,6 +97,24 @@ func el1_sysregs_context_save mrs x9, vbar_el1 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] + /* Save AArch32 system registers if the build has instructed so */ +#if CTX_INCLUDE_AARCH32_REGS + mrs x11, spsr_abt + mrs x12, spsr_und + stp x11, x12, [x0, #CTX_SPSR_ABT] + + mrs x13, spsr_irq + mrs x14, spsr_fiq + stp x13, x14, [x0, #CTX_SPSR_IRQ] + + mrs x15, dacr32_el2 + mrs x16, ifsr32_el2 + stp x15, x16, [x0, #CTX_DACR32_EL2] + + mrs x17, fpexc32_el2 + str x17, [x0, #CTX_FP_FPEXC32_EL2] +#endif + /* Save NS timer registers if the build has instructed so */ #if NS_TIMER_SWITCH mrs x10, cntp_ctl_el0 @@ -123,9 +129,6 @@ func el1_sysregs_context_save str x14, [x0, #CTX_CNTKCTL_EL1] #endif - mrs x15, fpexc32_el2 - str x15, [x0, #CTX_FP_FPEXC32_EL2] - ret endfunc el1_sysregs_context_save @@ -143,14 +146,6 @@ func el1_sysregs_context_restore msr spsr_el1, x9 msr elr_el1, x10 - ldp x11, x12, [x0, #CTX_SPSR_ABT] - msr spsr_abt, x11 - msr spsr_und, x12 - - ldp x13, x14, [x0, #CTX_SPSR_IRQ] - msr spsr_irq, x13 - msr spsr_fiq, x14 - ldp x15, x16, [x0, #CTX_SCTLR_EL1] msr sctlr_el1, x15 msr actlr_el1, x16 @@ -179,10 +174,6 @@ func el1_sysregs_context_restore msr tpidr_el0, x9 msr tpidrro_el0, x10 - ldp x11, x12, [x0, #CTX_DACR32_EL2] - msr dacr32_el2, x11 - msr ifsr32_el2, x12 - ldp x13, x14, [x0, #CTX_PAR_EL1] msr par_el1, x13 msr far_el1, x14 @@ -195,6 +186,23 @@ func el1_sysregs_context_restore msr contextidr_el1, x17 msr vbar_el1, x9 + /* Restore AArch32 system registers if the build has instructed so */ +#if CTX_INCLUDE_AARCH32_REGS + ldp x11, x12, [x0, #CTX_SPSR_ABT] + msr spsr_abt, x11 + msr spsr_und, x12 + + ldp x13, x14, [x0, #CTX_SPSR_IRQ] + msr spsr_irq, x13 + msr spsr_fiq, x14 + + ldp x15, x16, [x0, #CTX_DACR32_EL2] + msr dacr32_el2, x15 + msr ifsr32_el2, x16 + + ldr x17, [x0, #CTX_FP_FPEXC32_EL2] + msr fpexc32_el2, x17 +#endif /* Restore NS timer registers if the build has instructed so */ #if NS_TIMER_SWITCH ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] @@ -209,11 +217,7 @@ func el1_sysregs_context_restore msr cntkctl_el1, x14 #endif - ldr x15, [x0, #CTX_FP_FPEXC32_EL2] - msr fpexc32_el2, x15 - /* No explict ISB required here as ERET covers it */ - ret endfunc el1_sysregs_context_restore |