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| author | danh-arm <dan.handley@arm.com> | 2016-06-15 15:57:02 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-06-15 15:57:02 +0100 |
| commit | 50f7101a49d39243cca5942e3a2eb92ab460bd14 (patch) | |
| tree | 5f435f90c53dd23ee58bef44846b3aec284e9584 /common | |
| parent | f9455cea8c38f36f12c524226ccfae2ed2dabf87 (diff) | |
| parent | 2ba6895919546c5b346e49b1390e64b76100e85c (diff) | |
Merge pull request #650 from Xilinx/zynqmp-updates
Zynqmp updates
Diffstat (limited to 'common')
| -rw-r--r-- | common/context_mgmt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/common/context_mgmt.c b/common/context_mgmt.c index 586d42a4..3ccbd030 100644 --- a/common/context_mgmt.c +++ b/common/context_mgmt.c @@ -126,7 +126,7 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t /* * Set up SCTLR_ELx for the target exception level: - * EE bit is taken from the entrpoint attributes + * EE bit is taken from the entrypoint attributes * M, C and I bits must be zero (as required by PSCI specification) * * The target exception level is based on the spsr mode requested. |