diff options
| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2018-04-27 15:17:03 +0100 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2018-06-27 11:31:30 +0100 |
| commit | 64ee263e20611fae9ddf0ee4a8fcfeb6fbc724ae (patch) | |
| tree | f3207482f0c5ca18743a73d2568b81d4505722ff /bl32 | |
| parent | 92bec97f5c39b16b1599d41337ae4556b6da6c72 (diff) | |
DynamIQ: Enable MMU without using stack
Having an active stack while enabling MMU has shown coherency problems.
This patch builds on top of translation library changes that introduces
MMU-enabling without using stacks.
Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while
enabling MMU only because of active stack. Now that we can enable MMU
without using stack, we can enable both MMU and data caches at the same
time.
NOTE: Since this feature depends on using translation table library v2,
disallow using translation table library v1 with HW_ASSISTED_COHERENCY.
Fixes ARM-software/tf-issues#566
Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'bl32')
| -rw-r--r-- | bl32/sp_min/aarch32/entrypoint.S | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 87ef3f36..d6853cc4 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -298,20 +298,17 @@ func sp_min_warm_entrypoint * enter coherency (as CPUs already are); and there's no reason to have * caches disabled either. */ +#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY + mov r0, #0 +#else mov r0, #DISABLE_DCACHE +#endif bl bl32_plat_enable_mmu #if SP_MIN_WITH_SECURE_FIQ route_fiq_to_sp_min r0 #endif -#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY - ldcopr r0, SCTLR - orr r0, r0, #SCTLR_C_BIT - stcopr r0, SCTLR - isb -#endif - bl sp_min_warm_boot bl smc_get_next_ctx /* r0 points to `smc_ctx_t` */ |