diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2015-01-08 18:02:44 +0000 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2015-01-22 10:57:44 +0000 |
| commit | ab8707e6875a9fe447ff04fad9053d7d719f89e6 (patch) | |
| tree | 376a47144a8349f7ce3cdf21a1a12694e7f6bba6 /bl32 | |
| parent | 8c5fe0b5b9f1666b4ddd8f5849de80249cdebe40 (diff) | |
Remove coherent memory from the BL memory maps
This patch extends the build option `USE_COHERENT_MEMORY` to
conditionally remove coherent memory from the memory maps of
all boot loader stages. The patch also adds necessary
documentation for coherent memory removal in firmware-design,
porting and user guides.
Fixes ARM-Software/tf-issues#106
Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
Diffstat (limited to 'bl32')
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 2 | ||||
| -rw-r--r-- | bl32/tsp/tsp.ld.S | 4 | ||||
| -rw-r--r-- | bl32/tsp/tsp_main.c | 6 |
3 files changed, 9 insertions, 3 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 1cda1653..2714282b 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -108,9 +108,11 @@ func tsp_entrypoint ldr x1, =__BSS_SIZE__ bl zeromem16 +#if USE_COHERENT_MEM ldr x0, =__COHERENT_RAM_START__ ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ bl zeromem16 +#endif /* -------------------------------------------- * Allocate a stack whose memory will be marked diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index 5d7ffa11..d411ad02 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -98,6 +98,7 @@ SECTIONS *(xlat_table) } >RAM +#if USE_COHERENT_MEM /* * The base address of the coherent memory section must be page-aligned (4K) * to guarantee that the coherent data are stored on their own pages and @@ -116,12 +117,15 @@ SECTIONS . = NEXT(4096); __COHERENT_RAM_END__ = .; } >RAM +#endif __BL32_END__ = .; __BSS_SIZE__ = SIZEOF(.bss); +#if USE_COHERENT_MEM __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif ASSERT(. <= BL32_LIMIT, "BL3-2 image has exceeded its limit.") } diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index 193ba29b..2eaca7c9 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -43,7 +43,7 @@ * of trusted SRAM ******************************************************************************/ extern unsigned long __RO_START__; -extern unsigned long __COHERENT_RAM_END__; +extern unsigned long __BL32_END__; /******************************************************************************* * Lock to control access to the console @@ -63,11 +63,11 @@ work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; /******************************************************************************* * The BL32 memory footprint starts with an RO sections and ends - * with a section for coherent RAM. Use it to find the memory size + * with the linker symbol __BL32_END__. Use it to find the memory size ******************************************************************************/ #define BL32_TOTAL_BASE (unsigned long)(&__RO_START__) -#define BL32_TOTAL_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__) static tsp_args_t *set_smc_args(uint64_t arg0, uint64_t arg1, |