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| author | Dan Handley <dan.handley@arm.com> | 2014-08-19 11:04:21 +0100 |
|---|---|---|
| committer | Dan Handley <dan.handley@arm.com> | 2014-08-19 11:04:21 +0100 |
| commit | a1d80440c44ce70e5fec4d8c60b5f6688b6cf8ff (patch) | |
| tree | 27877c106f03eed314f529ee05e66cb747e1914b /bl32 | |
| parent | 57a18ff489fcfba38f26845eafacd90479c0be81 (diff) | |
| parent | 0c8d4fef28768233f1f46b4d085f904293dffd2c (diff) | |
Merge pull request #189 from achingupta/ag/tf-issues#153
Unmask SError interrupt and clear SCR_EL3.EA bit
Diffstat (limited to 'bl32')
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 12 | ||||
| -rw-r--r-- | bl32/tsp/aarch64/tsp_exceptions.S | 6 |
2 files changed, 18 insertions, 0 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 1838d5a8..8fae1b2b 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -78,6 +78,14 @@ func tsp_entrypoint */ adr x0, tsp_exceptions msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer @@ -187,6 +195,10 @@ func tsp_cpu_on_entry */ adr x0, tsp_exceptions msr vbar_el1, x0 + isb + + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index f84b5e09..4c0d4361 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -120,6 +120,9 @@ sync_exception_sp_elx: .align 7 irq_sp_elx: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + save_caller_regs_and_lr /* We just update some statistics in the handler */ bl tsp_irq_received @@ -132,6 +135,9 @@ irq_sp_elx: .align 7 fiq_sp_elx: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + save_caller_regs_and_lr bl tsp_fiq_handler cbz x0, fiq_sp_elx_done |