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| author | danh-arm <dan.handley@arm.com> | 2014-07-28 14:27:25 +0100 |
|---|---|---|
| committer | danh-arm <dan.handley@arm.com> | 2014-07-28 14:27:25 +0100 |
| commit | 9fd412770f1a7d9c68731a21f157a326db3c5725 (patch) | |
| tree | 745886c81021ef1cd3bffa5ef131b7564812d179 /bl32 | |
| parent | d9b1128b438748ce7ccfd33804321da2eed6fcfd (diff) | |
| parent | ec3c10039bdc2c1468a8ba95fbbe9de78628eea5 (diff) | |
Merge pull request #170 from achingupta/ag/tf-issues#226
Simplify management of SCTLR_EL3 and SCTLR_EL1
Diffstat (limited to 'bl32')
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 7a1797ee..91b6128c 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -89,11 +89,13 @@ func tsp_entrypoint msr vbar_el1, x0 /* --------------------------------------------- - * Enable the instruction cache. + * Enable the instruction cache, stack pointer + * and data access alignment checks * --------------------------------------------- */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el1 - orr x0, x0, #SCTLR_I_BIT + orr x0, x0, x1 msr sctlr_el1, x0 isb @@ -196,11 +198,13 @@ func tsp_cpu_on_entry msr vbar_el1, x0 /* --------------------------------------------- - * Enable the instruction cache. + * Enable the instruction cache, stack pointer + * and data access alignment checks * --------------------------------------------- */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el1 - orr x0, x0, #SCTLR_I_BIT + orr x0, x0, x1 msr sctlr_el1, x0 isb |