diff options
| author | Juan Castillo <juan.castillo@arm.com> | 2014-06-13 17:05:10 +0100 |
|---|---|---|
| committer | Juan Castillo <juan.castillo@arm.com> | 2014-06-24 12:50:00 +0100 |
| commit | 4f2104ff20753d78af0058e3ca5e9e042cd707af (patch) | |
| tree | 82c3050940f816e3de424958d23bfa691b44b152 /bl32 | |
| parent | 41cf7bdfd7114ee437d165974367a483636df76d (diff) | |
Remove all checkpatch errors from codebase
Exclude stdlib files because they do not follow kernel code style.
Fixes ARM-software/tf-issues#73
Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab
Diffstat (limited to 'bl32')
| -rw-r--r-- | bl32/tsp/tsp_interrupt.c | 4 | ||||
| -rw-r--r-- | bl32/tsp/tsp_timer.c | 10 |
2 files changed, 7 insertions, 7 deletions
diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c index 4a4b877e..ff6bdc5c 100644 --- a/bl32/tsp/tsp_interrupt.c +++ b/bl32/tsp/tsp_interrupt.c @@ -72,7 +72,7 @@ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3) * architecture version in v2.0 and the secure physical timer interrupt is the * only S-EL1 interrupt that it needs to handle. ******************************************************************************/ -int32_t tsp_fiq_handler() +int32_t tsp_fiq_handler(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr), id; @@ -109,7 +109,7 @@ int32_t tsp_fiq_handler() return 0; } -int32_t tsp_irq_received() +int32_t tsp_irq_received(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c index 366640f4..a7fdfdaf 100644 --- a/bl32/tsp/tsp_timer.c +++ b/bl32/tsp/tsp_timer.c @@ -46,7 +46,7 @@ static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT]; /******************************************************************************* * This function initializes the generic timer to fire every 0.5 second ******************************************************************************/ -void tsp_generic_timer_start() +void tsp_generic_timer_start(void) { uint64_t cval; uint32_t ctl = 0; @@ -63,7 +63,7 @@ void tsp_generic_timer_start() /******************************************************************************* * This function deasserts the timer interrupt and sets it up again ******************************************************************************/ -void tsp_generic_timer_handler() +void tsp_generic_timer_handler(void) { /* Ensure that the timer did assert the interrupt */ assert(get_cntp_ctl_istatus(read_cntps_ctl_el1())); @@ -76,7 +76,7 @@ void tsp_generic_timer_handler() /******************************************************************************* * This function deasserts the timer interrupt prior to cpu power down ******************************************************************************/ -void tsp_generic_timer_stop() +void tsp_generic_timer_stop(void) { /* Disable the timer */ write_cntps_ctl_el1(0); @@ -85,7 +85,7 @@ void tsp_generic_timer_stop() /******************************************************************************* * This function saves the timer context prior to cpu suspension ******************************************************************************/ -void tsp_generic_timer_save() +void tsp_generic_timer_save(void) { uint32_t linear_id = platform_get_core_pos(read_mpidr()); @@ -98,7 +98,7 @@ void tsp_generic_timer_save() /******************************************************************************* * This function restores the timer context post cpu resummption ******************************************************************************/ -void tsp_generic_timer_restore() +void tsp_generic_timer_restore(void) { uint32_t linear_id = platform_get_core_pos(read_mpidr()); |