diff options
| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-05-29 09:28:05 +0100 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2018-06-21 13:29:21 +0800 |
| commit | 770f853dcb47ad856c060ffc6fefd626ae40e52c (patch) | |
| tree | 89e973cc90a4341ebdec51f4e26805fa1a81319e /bl32 | |
| parent | 959392911781f3bd4263a01d703097998d0aaa0f (diff) | |
Merge pull request #1392 from dp-arm/dp/cve_2018_3639
Implement workaround for CVE-2018-3639 on Cortex A57/A72/A73 and A75
Conflicts:
services/arm_arch_svc/arm_arch_svc_setup.c
Diffstat (limited to 'bl32')
| -rw-r--r-- | bl32/sp_min/sp_min.mk | 4 | ||||
| -rw-r--r-- | bl32/sp_min/wa_cve_2017_5715_bpiall.S (renamed from bl32/sp_min/workaround_cve_2017_5715_bpiall.S) | 4 | ||||
| -rw-r--r-- | bl32/sp_min/wa_cve_2017_5715_icache_inv.S (renamed from bl32/sp_min/workaround_cve_2017_5715_icache_inv.S) | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk index 193b1d5e..6233299d 100644 --- a/bl32/sp_min/sp_min.mk +++ b/bl32/sp_min/sp_min.mk @@ -29,8 +29,8 @@ BL32_SOURCES += lib/extensions/amu/aarch32/amu.c\ endif ifeq (${WORKAROUND_CVE_2017_5715},1) -BL32_SOURCES += bl32/sp_min/workaround_cve_2017_5715_bpiall.S \ - bl32/sp_min/workaround_cve_2017_5715_icache_inv.S +BL32_SOURCES += bl32/sp_min/wa_cve_2017_5715_bpiall.S \ + bl32/sp_min/wa_cve_2017_5715_icache_inv.S endif BL32_LINKERFILE := bl32/sp_min/sp_min.ld.S diff --git a/bl32/sp_min/workaround_cve_2017_5715_bpiall.S b/bl32/sp_min/wa_cve_2017_5715_bpiall.S index 5387cefc..385f3d4b 100644 --- a/bl32/sp_min/workaround_cve_2017_5715_bpiall.S +++ b/bl32/sp_min/wa_cve_2017_5715_bpiall.S @@ -6,9 +6,9 @@ #include <asm_macros.S> - .globl workaround_bpiall_runtime_exceptions + .globl wa_cve_2017_5715_bpiall_vbar -vector_base workaround_bpiall_runtime_exceptions +vector_base wa_cve_2017_5715_bpiall_vbar /* We encode the exception entry in the bottom 3 bits of SP */ add sp, sp, #1 /* Reset: 0b111 */ add sp, sp, #1 /* Undef: 0b110 */ diff --git a/bl32/sp_min/workaround_cve_2017_5715_icache_inv.S b/bl32/sp_min/wa_cve_2017_5715_icache_inv.S index 9102b02f..d0a46250 100644 --- a/bl32/sp_min/workaround_cve_2017_5715_icache_inv.S +++ b/bl32/sp_min/wa_cve_2017_5715_icache_inv.S @@ -6,9 +6,9 @@ #include <asm_macros.S> - .globl workaround_icache_inv_runtime_exceptions + .globl wa_cve_2017_5715_icache_inv_vbar -vector_base workaround_icache_inv_runtime_exceptions +vector_base wa_cve_2017_5715_icache_inv_vbar /* We encode the exception entry in the bottom 3 bits of SP */ add sp, sp, #1 /* Reset: 0b111 */ add sp, sp, #1 /* Undef: 0b110 */ |