diff options
author | danh-arm <dan.handley@arm.com> | 2014-07-28 14:24:52 +0100 |
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committer | danh-arm <dan.handley@arm.com> | 2014-07-28 14:24:52 +0100 |
commit | d9b1128b438748ce7ccfd33804321da2eed6fcfd (patch) | |
tree | 838d8022c6db8516721432ec43bd64f7614516a9 /bl32/tsp | |
parent | 592dd7cbe658cc33ae2818c9ed543ac57e97f784 (diff) | |
parent | 539a7b383d52493a94df4f5da8f74aa102429fa0 (diff) |
Merge pull request #169 from achingupta/ag/tf-issues#198
Ag/tf issues#198
Diffstat (limited to 'bl32/tsp')
-rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 60 |
1 files changed, 39 insertions, 21 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 479ca59b..7a1797ee 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -31,6 +31,7 @@ #include <arch.h> #include <asm_macros.S> #include <tsp.h> +#include <xlat_tables.h> .globl tsp_entrypoint @@ -111,12 +112,15 @@ func tsp_entrypoint bl zeromem16 /* -------------------------------------------- - * Give ourselves a small coherent stack to - * ease the pain of initializing the MMU + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. * -------------------------------------------- */ mrs x0, mpidr_el1 - bl platform_set_coherent_stack + bl platform_set_stack /* --------------------------------------------- * Perform early platform setup & platform @@ -127,14 +131,6 @@ func tsp_entrypoint bl bl32_plat_arch_setup /* --------------------------------------------- - * Give ourselves a stack allocated in Normal - * -IS-WBWA memory - * --------------------------------------------- - */ - mrs x0, mpidr_el1 - bl platform_set_stack - - /* --------------------------------------------- * Jump to main function. * --------------------------------------------- */ @@ -209,26 +205,48 @@ func tsp_cpu_on_entry isb /* -------------------------------------------- - * Give ourselves a small coherent stack to - * ease the pain of initializing the MMU + * Give ourselves a stack whose memory will be + * marked as Normal-IS-WBWA when the MMU is + * enabled. * -------------------------------------------- */ mrs x0, mpidr_el1 - bl platform_set_coherent_stack + bl platform_set_stack - /* --------------------------------------------- - * Initialise the MMU - * --------------------------------------------- + /* -------------------------------------------- + * Enable the MMU with the DCache disabled. It + * is safe to use stacks allocated in normal + * memory as a result. All memory accesses are + * marked nGnRnE when the MMU is disabled. So + * all the stack writes will make it to memory. + * All memory accesses are marked Non-cacheable + * when the MMU is enabled but D$ is disabled. + * So used stack memory is guaranteed to be + * visible immediately after the MMU is enabled + * Enabling the DCache at the same time as the + * MMU can lead to speculatively fetched and + * possibly stale stack memory being read from + * other caches. This can lead to coherency + * issues. + * -------------------------------------------- */ + mov x0, #DISABLE_DCACHE bl bl32_plat_enable_mmu /* --------------------------------------------- - * Give ourselves a stack allocated in Normal - * -IS-WBWA memory + * Enable the Data cache now that the MMU has + * been enabled. The stack has been unwound. It + * will be written first before being read. This + * will invalidate any stale cache lines resi- + * -dent in other caches. We assume that + * interconnect coherency has been enabled for + * this cluster by EL3 firmware. * --------------------------------------------- */ - mrs x0, mpidr_el1 - bl platform_set_stack + mrs x0, sctlr_el1 + orr x0, x0, #SCTLR_C_BIT + msr sctlr_el1, x0 + isb /* --------------------------------------------- * Enter C runtime to perform any remaining |