diff options
| author | Paul Beesley <paul.beesley@arm.com> | 2019-08-23 11:26:57 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-08-23 11:26:57 +0000 |
| commit | 30560911ddd08880f8a2c8142ce8c69975976adc (patch) | |
| tree | 62907e026519c717e5a8476d79aa3da47bda15ef /bl31 | |
| parent | 44e8d5ebc36950943d70f3517d7756e210fc42ab (diff) | |
| parent | e290a8fcbc836d51566da1607add8a320d0f1a20 (diff) | |
Merge "AArch64: Disable Secure Cycle Counter" into integration
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/ea_delegate.S | 14 | ||||
| -rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 22 |
2 files changed, 36 insertions, 0 deletions
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index 40c3191a..8dca10cf 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -68,6 +68,13 @@ func enter_lower_el_sync_ea /* Save GP registers */ bl save_gp_registers + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + /* Save ARMv8.3-PAuth registers and load firmware key */ #if CTX_INCLUDE_PAUTH_REGS bl pauth_context_save @@ -106,6 +113,13 @@ func enter_lower_el_async_ea /* Save GP registers */ bl save_gp_registers + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + /* Save ARMv8.3-PAuth registers and load firmware key */ #if CTX_INCLUDE_PAUTH_REGS bl pauth_context_save diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 6ffd9955..fd7656e2 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -67,6 +67,14 @@ /* Save GP registers and restore them afterwards */ bl save_gp_registers + + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + bl handle_lower_el_ea_esb bl restore_gp_registers @@ -123,6 +131,13 @@ bl save_gp_registers + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + /* Save ARMv8.3-PAuth registers and load firmware key */ #if CTX_INCLUDE_PAUTH_REGS bl pauth_context_save @@ -335,6 +350,13 @@ smc_handler64: /* Save general purpose registers */ bl save_gp_registers + /* + * If Secure Cycle Counter is not disabled in MDCR_EL3 + * when ARMv8.5-PMU is implemented, save PMCR_EL0 and + * disable all event counters and cycle counter. + */ + bl save_pmcr_disable_pmu + /* Save ARMv8.3-PAuth registers and load firmware key */ #if CTX_INCLUDE_PAUTH_REGS bl pauth_context_save |