diff options
| author | David Cunado <david.cunado@arm.com> | 2017-10-20 11:30:57 +0100 |
|---|---|---|
| committer | David Cunado <david.cunado@arm.com> | 2017-11-15 22:42:05 +0000 |
| commit | 91089f360aaa38408d96a02136456dbde4f34eaf (patch) | |
| tree | 33301c2c73797b1f5ae3582070e314895d2319e1 /bl31 | |
| parent | e83769c07bb09b7727a36389c9dd92096860637e (diff) | |
Move FPEXC32_EL2 to FP Context
The FPEXC32_EL2 register controls SIMD and FP functionality when the
lower ELs are executing in AArch32 mode. It is architecturally mapped
to AArch32 system register FPEXC.
This patch removes FPEXC32_EL2 register from the System Register context
and adds it to the floating-point context. EL3 only saves / restores the
floating-point context if the build option CTX_INCLUDE_FPREGS is set to 1.
The rationale for this change is that if the Secure world is using FP
functionality and EL3 is not managing the FP context, then the Secure
world will save / restore the appropriate FP registers.
NOTE - this is a break in behaviour in the unlikely case that
CTX_INCLUDE_FPREGS is set to 0 and the platform contains an AArch32
Secure Payload that modifies FPEXC, but does not save and restore
this register
Change-Id: Iab80abcbfe302752d52b323b4abcc334b585c184
Signed-off-by: David Cunado <david.cunado@arm.com>
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/crash_reporting.S | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S index 34e4dcdd..cf32b31d 100644 --- a/bl31/aarch64/crash_reporting.S +++ b/bl31/aarch64/crash_reporting.S @@ -46,8 +46,7 @@ non_el3_sys_regs: "tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\ "mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\ "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\ - "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0",\ - "isr_el1", "" + "cntv_cval_el0", "cntkctl_el1", "sp_el0", "isr_el1", "" panic_msg: .asciz "PANIC in EL3 at x30 = 0x" @@ -313,9 +312,8 @@ func do_crash_reporting mrs x15, cntv_cval_el0 bl str_in_crash_buf_print mrs x8, cntkctl_el1 - mrs x9, fpexc32_el2 - mrs x10, sp_el0 - mrs x11, isr_el1 + mrs x9, sp_el0 + mrs x10, isr_el1 bl str_in_crash_buf_print /* Get the cpu specific registers to report */ |