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| author | davidcunado-arm <david.cunado@arm.com> | 2018-02-07 11:57:19 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-02-07 11:57:19 +0800 |
| commit | 5b75b4a725d062bd593856a665bfda0e1b23a04b (patch) | |
| tree | afc86aa95f7073042803ed9f5938020d19ecb369 /bl1 | |
| parent | 9fd2f13bd608832260300640970f73c62357c684 (diff) | |
| parent | 95ae5b00447da02695a653004b86e6b805e058a9 (diff) | |
Merge pull request #1173 from etienne-lms/armv7-qemu
support to boot OP-TEE on AArch32/Armv7+example with Cortex-A15/Qemu
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch32/bl1_exceptions.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S index f73db402..a1e32f06 100644 --- a/bl1/aarch32/bl1_exceptions.S +++ b/bl1/aarch32/bl1_exceptions.S @@ -73,6 +73,11 @@ debug_loop: ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] msr spsr, r1 + /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ + cps #MODE32_svc + ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET] + cps #MODE32_mon + add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET ldm r8, {r0, r1, r2, r3} eret |