Factor out translation table setup in ARM FVP port

This patch factors out the ARM FVP specific code to create MMU
translation tables so that it is possible for a boot loader stage to
create a different set of tables instead of using the default ones.
The default translation tables are created with the assumption that
the calling boot loader stage executes out of secure SRAM. This might
not be true for the BL3_2 stage in the future.

A boot loader stage can define the `fill_xlation_tables()` function as
per its requirements. It returns a reference to the level 1
translation table which is used by the common platform code to setup
the TTBR_EL3.

This patch is a temporary solution before a larger rework of
translation table creation logic is introduced.

Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6

1 files changed, 1 insertions, 0 deletions

diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index 50a245b4..8e86af47 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -33,6 +33,7 @@ vpath			%.c	plat/${PLAT}		\
 				common			\
 				lib			\
 				arch/${ARCH}		\
+				lib/arch/${ARCH}	\
 				${PLAT_BL1_C_VPATH}
 
 vpath			%.S	arch/${ARCH}/cpu	\