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| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-03-31 10:44:09 +0100 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-04-08 15:22:56 +0100 |
| commit | 65a9c0e96a9fe033936f40b7603e0ae267b97d96 (patch) | |
| tree | 2317b487f3fd5895d0af80a354a3365150904c47 /bl1/aarch64 | |
| parent | e6e54a18f80318e2fcf98f4f8810705618cdea79 (diff) | |
Revert "Move architecture timer setup to platform-specific code"
This reverts commit 1c297bf015226c182b66498d5a64b8b51c7624f5
because it introduced a bug: the CNTFRQ_EL0 register was no
longer programmed by all CPUs. bl31_platform_setup() function
is invoked only in the cold boot path and consequently only
on the primary cpu.
A subsequent commit will correctly implement the necessary changes
to the counter frequency setup code.
Fixes ARM-software/tf-issues#125
Conflicts:
docs/firmware-design.md
plat/fvp/bl31_plat_setup.c
Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
Diffstat (limited to 'bl1/aarch64')
| -rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index f9443aa1..4191937e 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -39,6 +39,7 @@ void bl1_arch_setup(void) { unsigned long tmp_reg = 0; + unsigned int counter_base_frequency; /* Enable alignment checks and set the exception endianess to LE */ tmp_reg = read_sctlr_el3(); @@ -60,6 +61,13 @@ void bl1_arch_setup(void) enable_serror(); enable_debug_exceptions(); + /* Read the frequency from Frequency modes table */ + counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); + /* The first entry of the frequency modes table must not be 0 */ + assert(counter_base_frequency != 0); + + /* Program the counter frequency */ + write_cntfrq_el0(counter_base_frequency); return; } |