diff options
| author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-08-20 15:33:27 +0800 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2019-09-12 12:36:31 +0000 |
| commit | b90f207a1d386ec391bd3ea9eb403c4ad7b7551b (patch) | |
| tree | e7e7acdda3c1a7823b8ba8d7f14fe3f27bc1d64f /Makefile | |
| parent | 2fc6ffc451c9af16e03eff51e779c33828e9ab07 (diff) | |
Invalidate dcache build option for bl2 entry at EL3
Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cache beforehand will crash the platform. Hence, this will provide an
option to skip the data cache invalidation upon bl2 entry at EL3
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -689,6 +689,7 @@ $(eval $(call assert_boolean,USE_TBBR_DEFS)) $(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call assert_boolean,BL2_AT_EL3)) $(eval $(call assert_boolean,BL2_IN_XIP_MEM)) +$(eval $(call assert_boolean,BL2_INV_DCACHE)) $(eval $(call assert_numeric,ARM_ARCH_MAJOR)) $(eval $(call assert_numeric,ARM_ARCH_MINOR)) @@ -749,6 +750,7 @@ $(eval $(call add_define,USE_TBBR_DEFS)) $(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call add_define,BL2_AT_EL3)) $(eval $(call add_define,BL2_IN_XIP_MEM)) +$(eval $(call add_define,BL2_INV_DCACHE)) ifeq (${SANITIZE_UB},trap) $(eval $(call add_define,MONITOR_TRAPS)) |