diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-05-06 13:11:04 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-05-09 15:25:12 +0800 |
| commit | e9dfde639db8593aa12d779f1990c8bb276e711c (patch) | |
| tree | ce1f9b042dcf042ee83811eda9fcc18c989c17dd | |
| parent | 57bf8a00a74f12671cb38863bbc3606b3834f195 (diff) | |
MLK-23821-03 plat: imx8m: Fix the dfiphymaster setting after dvfs
the dfiphymaster setting need to be save/restore to make sure
it aligned with the initial config.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/ddr/lpddr4_dvfs.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/plat/imx/imx8m/ddr/lpddr4_dvfs.c b/plat/imx/imx8m/ddr/lpddr4_dvfs.c index 0458574e..489ad6a8 100644 --- a/plat/imx/imx8m/ddr/lpddr4_dvfs.c +++ b/plat/imx/imx8m/ddr/lpddr4_dvfs.c @@ -36,6 +36,7 @@ void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, uint32_t val; uint32_t derate_backup[3]; uint32_t (*mr_data)[8]; + uint32_t phy_master; /* 1. program targetd UMCTL2_REGS_FREQ1/2/3,already done, skip it. */ @@ -56,6 +57,8 @@ void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, /* 12. set PWRCTL.selfref_en=0 */ mmio_clrbits_32(DDRC_PWRCTL(0), 0xf); + phy_master = mmio_read_32(DDRC_DFIPHYMSTR(0)); + /* It is more safe to config it here */ mmio_clrbits_32(DDRC_DFIPHYMSTR(0), 0x1); @@ -224,8 +227,8 @@ void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, emr3 = (emr3 & 0x00f7) | 0x0d00; lpddr4_mr_write(3, 13, emr3); - /* enable PHY master */ - mmio_write_32(DDRC_DFIPHYMSTR(0), 0x1); + /* restore the PHY master */ + mmio_write_32(DDRC_DFIPHYMSTR(0), phy_master); /* 32. issue ZQ if required: zq_calib_short, bit 4 */ /* polling zq_calib_short_busy */ |