diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2021-05-03 21:28:55 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2021-05-03 21:30:40 +0200 |
| commit | 835a8f67b2ca7aa3f2d05d6e6a1a51f7e1147266 (patch) | |
| tree | 229385550c80485b4f31cdad8a78eda7d5fac26e | |
| parent | 7f1187ba31cc1624f7dadd98998e010cb229926a (diff) | |
| parent | 2a26786460edd4f0ec3111e7027c93c57fc572c1 (diff) | |
Merge remote-tracking branch 'nxp/imx_5.4.70_2.3.0' into toradex_imx_5.4.70_2.3.0
Updates to 5.4.70_2.3.2
Related-to: ELB-3957
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | plat/imx/imx8m/ddr/clock.c | 3 | ||||
| -rw-r--r-- | plat/imx/imx8m/ddr/ddr4_dvfs.c | 18 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8m_csu.c | 4 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c | 5 |
4 files changed, 25 insertions, 5 deletions
diff --git a/plat/imx/imx8m/ddr/clock.c b/plat/imx/imx8m/ddr/clock.c index 7ddc25cc..7eb989f9 100644 --- a/plat/imx/imx8m/ddr/clock.c +++ b/plat/imx/imx8m/ddr/clock.c @@ -84,6 +84,9 @@ void dram_pll_init(unsigned int drate) mmio_clrbits_32(DRAM_PLL_CTRL, (1 << 9)); switch (drate) { + case 4000: + mmio_write_32(DRAM_PLL_CTRL + 0x4, (250 << 12) | (3 << 4) | 1); + break; case 3200: mmio_write_32(DRAM_PLL_CTRL + 0x4, (200 << 12) | (3 << 4) | 1); break; diff --git a/plat/imx/imx8m/ddr/ddr4_dvfs.c b/plat/imx/imx8m/ddr/ddr4_dvfs.c index 52dd2066..d1c0d750 100644 --- a/plat/imx/imx8m/ddr/ddr4_dvfs.c +++ b/plat/imx/imx8m/ddr/ddr4_dvfs.c @@ -18,8 +18,22 @@ void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, * 1. Poll MRSTAT.mr_wr_busy until it is 0 to make sure * that there is no outstanding MR transAction. */ - while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) - ; + + /* + * ERR050712: + * When performing a software driven MR access, the following sequence + * must be done automatically before performing other APB register accesses. + * 1. Set MRCTRL0.mr_wr=1 + * 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) + * 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2) + */ + mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); + + do { + while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) + ; + + } while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1); /* * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank diff --git a/plat/imx/imx8m/imx8m_csu.c b/plat/imx/imx8m/imx8m_csu.c index 3405fa59..b1f6886e 100644 --- a/plat/imx/imx8m/imx8m_csu.c +++ b/plat/imx/imx8m/imx8m_csu.c @@ -34,14 +34,14 @@ void imx_csu_init(const struct imx_csu_cfg *csu_cfg) if (val & CSU_SA_LOCK(csu->idx)) break; mmio_clrsetbits_32(CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx), - CSU_SA_CFG(csu->hp | (csu->lock << 0x1), csu->idx)); + CSU_SA_CFG(csu->sa | (csu->lock << 0x1), csu->idx)); break; case CSU_HPCONTROL: val = mmio_read_32(CSU_HPCONTROL_REG(csu->idx)); if (val & CSU_HPCONTROL_LOCK(csu->idx)) break; mmio_clrsetbits_32(CSU_HPCONTROL_REG(csu->idx), CSU_HPCONTROL_CFG(0x1, csu->idx), - CSU_HPCONTROL_CFG(csu->hp | (csu->lock << 0x1), csu->idx)); + CSU_HPCONTROL_CFG(csu->hpctrl | (csu->lock << 0x1), csu->idx)); break; default: break; diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index f4c45895..7b320f0e 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -94,7 +94,10 @@ static void imx8mq_soc_info_init(void) ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1); if (ocotp_val == 0xff0055aa) { imx_soc_revision &= ~0xff; - imx_soc_revision |= 0x21; + if (rom_version == 0x22) + imx_soc_revision |= 0x22; + else + imx_soc_revision |= 0x21; return; } } |