diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2021-03-16 16:42:54 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2021-03-26 14:45:24 +0800 |
| commit | 768e16f784bd7462d7df684e24deb0b777bdfc28 (patch) | |
| tree | 02ee828fa6bd797f2656ed02cf9c4cc0443ac392 | |
| parent | ed66400156db65fca3f69aae2536282555b63798 (diff) | |
MLK-25345 plat: imx8m: Add ddr4 dvfs sw workaround for ERR050712
APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring
When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:
1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2)
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1eb7ad6c5ea2c47952ab5e083df9802e27c165f5)
| -rw-r--r-- | plat/imx/imx8m/ddr/ddr4_dvfs.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/plat/imx/imx8m/ddr/ddr4_dvfs.c b/plat/imx/imx8m/ddr/ddr4_dvfs.c index 52dd2066..d1c0d750 100644 --- a/plat/imx/imx8m/ddr/ddr4_dvfs.c +++ b/plat/imx/imx8m/ddr/ddr4_dvfs.c @@ -18,8 +18,22 @@ void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, * 1. Poll MRSTAT.mr_wr_busy until it is 0 to make sure * that there is no outstanding MR transAction. */ - while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) - ; + + /* + * ERR050712: + * When performing a software driven MR access, the following sequence + * must be done automatically before performing other APB register accesses. + * 1. Set MRCTRL0.mr_wr=1 + * 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) + * 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2) + */ + mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); + + do { + while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) + ; + + } while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1); /* * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank |