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authorJacky Bai <ping.bai@nxp.com>2020-03-27 20:50:44 +0800
committerJacky Bai <ping.bai@nxp.com>2020-03-27 20:52:50 +0800
commitac5f80377ff574d721a9f966cecd0f1f63c22e94 (patch)
treecaa0726b86e10c54509981499a92ed0a090bb0cb
parented6eee177da175128578a7ae21b3bf5f66d9c7e1 (diff)
plat: imx8mm: Update the cpu core power up timing
Updating the CPU CORE power up timing to make sure the RDC reload is done before CPU start to run code in OCRAM space. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
-rw-r--r--plat/imx/imx8m/imx8mm/gpc.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c
index 75e103d7..b18071a0 100644
--- a/plat/imx/imx8m/imx8mm/gpc.c
+++ b/plat/imx/imx8m/imx8mm/gpc.c
@@ -423,16 +423,16 @@ void imx_gpc_init(void)
/*
* Set the CORE & SCU power up timing:
- * SW = 0x1, SW2ISO = 0x1;
+ * SW = 0x1, SW2ISO = 0x8;
* the CPU CORE and SCU power up timming counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
- mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81);
- mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81);
- mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81);
- mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81);
- mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81);
+ mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401);
mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
(0x59 << 10) | 0x5B | (0x2 << 20));