diff options
| author | Silvano di Ninno <silvano.dininno@nxp.com> | 2020-03-25 09:28:22 +0100 |
|---|---|---|
| committer | Silvano di Ninno <silvano.dininno@nxp.com> | 2020-03-27 12:22:09 +0100 |
| commit | 572dafcd0f92b61909e25f4326befbdea8eaeca9 (patch) | |
| tree | cc7ac51be628a5783c030e4dc09bb2b36f4e891b | |
| parent | 8091a6c56a568b09935fd1279ed562de4327cdb3 (diff) | |
TEE-532-3: plat: imx8mn: add optee support
Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c | 13 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/include/platform_def.h | 2 |
2 files changed, 11 insertions, 4 deletions
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c index c3868c0a..eaa4492a 100644 --- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c +++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c @@ -167,14 +167,19 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl32_image_ep_info.pc = BL32_BASE; bl32_image_ep_info.spsr = 0; + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; + #ifdef SPD_trusty bl32_image_ep_info.args.arg0 = BL32_SIZE; bl32_image_ep_info.args.arg1 = BL32_BASE; +#else + /* Make sure memory is clean */ + mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); + bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; + bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; #endif - - /* Pass TEE base and size to bl33 */ - bl33_image_ep_info.args.arg1 = BL32_BASE; - bl33_image_ep_info.args.arg2 = BL32_SIZE; #endif bl31_tzc380_setup(); diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h index 32fb3cc5..36535542 100644 --- a/plat/imx/imx8m/imx8mn/include/platform_def.h +++ b/plat/imx/imx8m/imx8mn/include/platform_def.h @@ -37,6 +37,8 @@ /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) +#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) + /* GICv3 base address */ #define PLAT_GICD_BASE U(0x38800000) #define PLAT_GICR_BASE U(0x38880000) |