diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-03-31 16:42:50 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-03-31 17:47:27 +0800 |
| commit | 25ce865155010545fa70256bbc2089b464c79f87 (patch) | |
| tree | 6a834cdefa9aca5f2cb24a42523cde2b81e4d207 | |
| parent | 2704540b4a7952d73e702a3e079c13c6af5ef03a (diff) | |
plat: imx8m: Fix the m4 enabled check for imx8m
On i.MX8MN & i.MX8MP, the M core enabled check should
relay on the IOMUX GPR CPU_WAIT bit, when this bit is
cleared, it means M core is active & running, so refine
the m4 enabled check method.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/gpc_common.c | 2 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/platform_def.h | 2 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mn/include/platform_def.h | 2 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mp/include/platform_def.h | 2 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mq/include/platform_def.h | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index c6d9ffe3..af1e33b3 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -45,7 +45,7 @@ bool imx_m4_lpa_active(void) bool imx_is_m4_enabled(void) { - return mmio_read_32(IMX_M4_STATUS) & IMX_M4_ENABLED; + return !(mmio_read_32(IMX_M4_STATUS) & IMX_M4_ENABLED_MASK); } void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint) diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index bcd84ba5..61ccbed0 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -121,7 +121,7 @@ #define SRC_SCR_M4_ENABLE_MASK BIT(3) #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) #define IMX_M4_STATUS (IMX_SRC_BASE + SRC_M4RCR) -#define IMX_M4_ENABLED SRC_SCR_M4C_NON_SCLR_RST_MASK +#define IMX_M4_ENABLED_MASK SRC_SCR_M4C_NON_SCLR_RST_MASK #define SNVS_LPCR U(0x38) #define SNVS_LPCR_SRTC_ENV BIT(0) diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h index 36535542..2e3e0b69 100644 --- a/plat/imx/imx8m/imx8mn/include/platform_def.h +++ b/plat/imx/imx8m/imx8mn/include/platform_def.h @@ -127,7 +127,7 @@ #define IOMUXC_GPR22 U(0x58) #define GPR_CM7_CPUWAIT BIT(0) #define IMX_M4_STATUS (IMX_IOMUX_GPR_BASE + IOMUXC_GPR22) -#define IMX_M4_ENABLED GPR_CM7_CPUWAIT +#define IMX_M4_ENABLED_MASK GPR_CM7_CPUWAIT #define ANAMIX_MISC_CTL U(0x124) diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h index bcd45343..ecbe0c5f 100644 --- a/plat/imx/imx8m/imx8mp/include/platform_def.h +++ b/plat/imx/imx8m/imx8mp/include/platform_def.h @@ -129,7 +129,7 @@ #define IOMUXC_GPR22 U(0x58) #define GPR_CM7_CPUWAIT BIT(0) #define IMX_M4_STATUS (IMX_IOMUX_GPR_BASE + IOMUXC_GPR22) -#define IMX_M4_ENABLED GPR_CM7_CPUWAIT +#define IMX_M4_ENABLED_MASK GPR_CM7_CPUWAIT #define ANAMIX_MISC_CTL U(0x124) diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h index fea4f04e..e0ae541b 100644 --- a/plat/imx/imx8m/imx8mq/include/platform_def.h +++ b/plat/imx/imx8m/imx8mq/include/platform_def.h @@ -122,7 +122,7 @@ #define SRC_SCR_M4_ENABLE_MASK BIT(3) #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) #define IMX_M4_STATUS (IMX_SRC_BASE + SRC_M4RCR) -#define IMX_M4_ENABLED SRC_SCR_M4C_NON_SCLR_RST_MASK +#define IMX_M4_ENABLED_MASK SRC_SCR_M4C_NON_SCLR_RST_MASK #define SNVS_LPCR U(0x38) #define SNVS_LPCR_SRTC_ENV BIT(0) |