diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-04-13 11:07:40 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-04-13 16:55:49 +0800 |
| commit | 25687f9ad5b9e4c1458776b06601a09ba4d1013d (patch) | |
| tree | 8894117603dea951c8b37d823b68b8d72c5212d8 | |
| parent | cc58d01e8ca73f90150e21024cbeaedb96726359 (diff) | |
MLK-23775 plat: imx8m: Fix the ddr4 dvfs random hang on imx8m
In step12, remove the while loop waiting to align
with the ddr4 dvfs flow on imx_2.0.y.
Tested-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/ddr/ddr4_dvfs.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/imx/imx8m/ddr/ddr4_dvfs.c b/plat/imx/imx8m/ddr/ddr4_dvfs.c index 4f55d2fe..86347928 100644 --- a/plat/imx/imx8m/ddr/ddr4_dvfs.c +++ b/plat/imx/imx8m/ddr/ddr4_dvfs.c @@ -180,8 +180,8 @@ void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate) * 12. Wait until STAT.operating_mode[1:0]!=11 indicating that the * controller is not in self-refresh mode. */ - while ((mmio_read_32(DDRC_STAT(0)) & 0x3) == 0x3) - ; + if ((mmio_read_32(DDRC_STAT(0)) & 0x3) == 0x3) + printf("C: Error DRAM should not in Self Refresh\n"); /* * 13. Assert PWRCTL.selfref_sw for the DWC_ddr_umctl2 core to enter |