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authorNitin Garg <nitin.garg@nxp.com>2017-05-11 16:28:55 -0500
committerAnson Huang <Anson.Huang@nxp.com>2017-07-12 23:28:20 +0800
commitde3efc86fcbcdf90e44a3f389db23d24fda8adda (patch)
tree2fa00bc21a4078b9b1f7ca7bf937327adeffbb08
parent992a0b82e9fd6dc3a4e1a99291c27a4b0c74e054 (diff)
Fix A72 L2 DATA latency and support booting CA72 as primary
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
-rw-r--r--plat/freescale/common/imx8_helpers.S30
-rw-r--r--plat/freescale/imx8qm/include/platform_def.h5
2 files changed, 35 insertions, 0 deletions
diff --git a/plat/freescale/common/imx8_helpers.S b/plat/freescale/common/imx8_helpers.S
index 6f677ca9..091d60a5 100644
--- a/plat/freescale/common/imx8_helpers.S
+++ b/plat/freescale/common/imx8_helpers.S
@@ -30,6 +30,7 @@
#include <asm_macros.S>
#include <platform_def.h>
+#include <cortex_a72.h>
.globl plat_is_my_cpu_primary
.globl plat_my_core_pos
@@ -42,6 +43,20 @@
.globl platform_mem_init
.globl imx_mailbox_init
+ /* --------------------------------------------------------------------
+ * Helper macro that reads the part number of the current CPU and jumps
+ * to the given label if it matches the CPU MIDR provided.
+ *
+ * Clobbers x0.
+ * --------------------------------------------------------------------
+ */
+ .macro jump_if_cpu_midr _cpu_midr, _label
+ mrs x0, midr_el1
+ ubfx x0, x0, MIDR_PN_SHIFT, #12
+ cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+ b.eq \_label
+ .endm
+
/* ----------------------------------------------
* The mailbox_base is used to distinguish warm/cold
* reset. The mailbox_base is in the data section, not
@@ -102,6 +117,21 @@ func plat_reset_handler
msr actlr_el3, x0
msr actlr_el2, x0
isb
+ /* --------------------------------------------------------------------
+ * Nothing to do on Cortex-A53.
+ * --------------------------------------------------------------------
+ */
+ jump_if_cpu_midr CORTEX_A72_MIDR, A72
+ ret
+
+A72:
+ /* --------------------------------------------------------------------
+ * Cortex-A72 specific settings
+ * --------------------------------------------------------------------
+ */
+ mov x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+ msr CORTEX_A72_L2CTLR_EL1, x0
+ isb
ret
endfunc plat_reset_handler
diff --git a/plat/freescale/imx8qm/include/platform_def.h b/plat/freescale/imx8qm/include/platform_def.h
index 5579ee06..76aa228a 100644
--- a/plat/freescale/imx8qm/include/platform_def.h
+++ b/plat/freescale/imx8qm/include/platform_def.h
@@ -35,7 +35,12 @@
#define PLATFORM_STACK_SIZE 0X400
#define CACHE_WRITEBACK_GRANULE 64
+/*#define CA72_ONLY*/
+#ifdef CA72_ONLY
+#define PLAT_PRIMARY_CPU 0x100
+#else
#define PLAT_PRIMARY_CPU 0x0
+#endif
#define PLATFORM_MAX_CPU_PER_CLUSTER 4
#define PLATFORM_CLUSTER_COUNT 2
#define PLATFORM_CLUSTER0_CORE_COUNT 4