diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2017-09-02 00:54:06 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2017-09-02 00:54:06 +0800 |
| commit | d52b12729a6c7c54cdd213203742b0e5dea0ae27 (patch) | |
| tree | b114c3d140f7f57ea0a83f7fda3f404dad5a6940 | |
| parent | a8c35fafe0af0bda340592373d446d93cc1ec75a (diff) | |
imx8mq: gpc: correct ARM power down request register offset
The GPC_CPU_PGC_SW_PDN_REQ offset should be 0xfc, previous
offset is incorrect, so actually ARM core is NOT powered
down and the power leakage is very high.
With this fix, each ARM core's leakage is about 25mA@0.9V.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | plat/freescale/imx8mq/gpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/freescale/imx8mq/gpc.c b/plat/freescale/imx8mq/gpc.c index c1836d93..ed40873f 100644 --- a/plat/freescale/imx8mq/gpc.c +++ b/plat/freescale/imx8mq/gpc.c @@ -93,7 +93,7 @@ #define SLPCR_A53_FASTWUP_WAIT (1 << 16) #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 -#define GPC_CPU_PGC_SW_PDN_REQ 0xf4 +#define GPC_CPU_PGC_SW_PDN_REQ 0xfc #define BM_CPU_PGC_SW_PDN_PUP_REQ 0x1 #define GPC_ARM_PGC 0x800 |