diff options
| author | Peng Fan <peng.fan@nxp.com> | 2017-07-05 16:39:02 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2017-07-12 23:33:10 +0800 |
| commit | 0e1d8df8ca232f69e277ce6894f06aadba7b8129 (patch) | |
| tree | 0222873a9aa9dcc63fcdf5efd12d0d97e5c2397f | |
| parent | 4d88656ba40c3f170d05fabcd393da4aa32967cc (diff) | |
imx8mq: enable tzc380
enable tzc380 for i.mx8mq
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | plat/freescale/imx8mq/imx8m_bl31_setup.c | 34 | ||||
| -rw-r--r-- | plat/freescale/imx8mq/include/platform_def.h | 2 | ||||
| -rw-r--r-- | plat/freescale/imx8mq/platform.mk | 1 |
3 files changed, 37 insertions, 0 deletions
diff --git a/plat/freescale/imx8mq/imx8m_bl31_setup.c b/plat/freescale/imx8mq/imx8m_bl31_setup.c index 129c2e89..2e307970 100644 --- a/plat/freescale/imx8mq/imx8m_bl31_setup.c +++ b/plat/freescale/imx8mq/imx8m_bl31_setup.c @@ -42,6 +42,7 @@ #include <plat_imx8.h> #include <xlat_tables.h> #include <soc.h> +#include <tzc380.h> /* linker defined symbols */ extern unsigned long __RO_START__; @@ -89,6 +90,8 @@ static uint32_t get_spsr_for_bl33_entry(void) #define SC_CNTCR_FREQ0 (1 << 8) #define SC_CNTCR_FREQ1 (1 << 9) +#define GPR_TZASC_EN (1 << 0) +#define GPR_TZASC_EN_LOCK (1 << 16) unsigned int freq; void system_counter_init(void) @@ -104,6 +107,34 @@ void system_counter_init(void) mmio_write_32(SCTR_BASE_ADDR + CNTCR_OFF, val); } +void bl31_tzc380_setup(void) +{ + unsigned int val; + + NOTICE("Configureing TZASC380\n"); + + /* Enable TZASC and lock setting */ + val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); + val |= GPR_TZASC_EN; + mmio_write_32(IMX_IOMUX_GPR_BASE + 0x28, val); + val |= GPR_TZASC_EN_LOCK; + mmio_write_32(IMX_IOMUX_GPR_BASE + 0x28, val); + + tzc380_init(IMX_TZASC_BASE); + + /* + * Need to substact offset 0x40000000 from CPU address when + * programming tzasc region for i.mx8mq. + */ + + /* Enable 1G-5G S/NS RW */ + tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); + /* Enable 0x40000000 - 0x40020000 S RW */ + tzc380_configure_region(1, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_128K) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW); + + tzc380_dump_state(); +} + void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { @@ -158,6 +189,8 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + + bl31_tzc380_setup(); } void bl31_plat_arch_setup(void) @@ -173,6 +206,7 @@ void bl31_plat_arch_setup(void) 0x1000, MT_DEVICE | MT_RW); mmap_add_region(IMX_GPC_BASE, IMX_GPC_BASE, 0x1000, MT_DEVICE | MT_RW); mmap_add_region(IMX_WDOG_BASE, IMX_WDOG_BASE, 0x1000, MT_DEVICE | MT_RW); + mmap_add_region(IMX_IOMUX_GPR_BASE, IMX_IOMUX_GPR_BASE, 0x1000, MT_DEVICE | MT_RW); mmap_add_region(IMX_ANAMIX_BASE, IMX_ANAMIX_BASE, 0x1000, MT_DEVICE | MT_RW); mmap_add_region(PLAT_GICD_BASE, PLAT_GICD_BASE, 0x80000, MT_DEVICE | MT_RW); diff --git a/plat/freescale/imx8mq/include/platform_def.h b/plat/freescale/imx8mq/include/platform_def.h index 960c1b15..670f0abf 100644 --- a/plat/freescale/imx8mq/include/platform_def.h +++ b/plat/freescale/imx8mq/include/platform_def.h @@ -47,6 +47,8 @@ #define IMX_GPC_BASE 0x303a0000 #define IMX_WDOG_BASE 0x30280000 #define IMX_SNVS_BASE 0x30370000 +#define IMX_TZASC_BASE 0x32F80000 +#define IMX_IOMUX_GPR_BASE 0x30340000 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ diff --git a/plat/freescale/imx8mq/platform.mk b/plat/freescale/imx8mq/platform.mk index ec51a899..424ccc83 100644 --- a/plat/freescale/imx8mq/platform.mk +++ b/plat/freescale/imx8mq/platform.mk @@ -20,6 +20,7 @@ BL31_SOURCES += plat/freescale/common/imx8_helpers.S \ lib/cpus/aarch64/cortex_a53.S \ drivers/console/aarch64/console.S \ ${PLAT_GIC_SOURCES} \ + drivers/arm/tzc/tzc380.c ENABLE_PLAT_COMPAT := 0 USE_COHERENT_MEM := 0 |