diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-02-12 12:37:35 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:33:02 +0300 |
| commit | f94206b9be9cbbcaf03ec59af50fb2be879787bb (patch) | |
| tree | c467deb2722bbe5b6f29b49caceee22d35d00756 | |
| parent | 0ad3ae282a59466ea08783aeefcb39a762f453ba (diff) | |
plat: imx8mq: update the lpddr4 dvfs and retention flow
Update the ddr retenton flow and dvfs flow used on imx8mq lpddr4 board.
1. DVFS flow is changed from hwffc to swffc.
2. frequency setpoint is change from 100mts to 667mts.
3. ddr retention flow is updated to compatible with the new lpddr4 training fw.
4. fix the retention failure issue caused by incorrect reset flow in retention exit.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
| -rw-r--r-- | plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c | 147 | ||||
| -rw-r--r-- | plat/imx/imx8mq/ddr/lpddr4_dvfs.c | 105 | ||||
| -rw-r--r-- | plat/imx/imx8mq/ddr/lpddr4_dvfs.h | 16 | ||||
| -rw-r--r-- | plat/imx/imx8mq/ddr/lpddr4_hwffc.c | 144 | ||||
| -rw-r--r-- | plat/imx/imx8mq/ddr/lpddr4_phy_cfg.c | 1602 | ||||
| -rw-r--r-- | plat/imx/imx8mq/ddr/lpddr4_retention.c | 247 | ||||
| -rw-r--r-- | plat/imx/imx8mq/ddr/lpddr4_swffc.c | 417 | ||||
| -rw-r--r-- | plat/imx/imx8mq/ddrc.c | 2989 | ||||
| -rw-r--r-- | plat/imx/imx8mq/imx8m_bl31_setup.c | 3 | ||||
| -rw-r--r-- | plat/imx/imx8mq/include/ddrc.h | 427 | ||||
| -rw-r--r-- | plat/imx/imx8mq/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/imx/imx8mq/include/soc.h | 4 | ||||
| -rw-r--r-- | plat/imx/imx8mq/platform.mk | 8 |
13 files changed, 2982 insertions, 3128 deletions
diff --git a/plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c b/plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c new file mode 100644 index 00000000..dba387b0 --- /dev/null +++ b/plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright 2017-2018 NXP. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <debug.h> +#include <stdbool.h> +#include <ddrc.h> +#include <mmio.h> +#include <platform_def.h> +#include <spinlock.h> +#include <soc.h> + +#define WR_POST_EXT_3200 + +static inline void umctl2_addrmap(void) +{ + /* Address mapping */ + /* need be refined for DDR vender */ + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + mmio_write_32(DDRC_ADDRMAP0(0), 0x00000015); + mmio_write_32(DDRC_ADDRMAP3(0), 0x00000000); + mmio_write_32(DDRC_ADDRMAP4(0), 0x00001F1F); + /* bank interleave */ + mmio_write_32(DDRC_ADDRMAP1(0), 0x00080808); + mmio_write_32(DDRC_ADDRMAP5(0), 0x07070707); + mmio_write_32(DDRC_ADDRMAP6(0), 0x08080707); +} + +static inline void umctl2_perf(void) +{ + mmio_write_32(DDRC_ODTCFG(0), 0x0b060908); + mmio_write_32(DDRC_ODTMAP(0), 0x00000000); + mmio_write_32(DDRC_SCHED(0), 0x29511505); + mmio_write_32(DDRC_SCHED1(0), 0x0000002c); + mmio_write_32(DDRC_PERFHPR1(0), 0x5900575b); + mmio_write_32(DDRC_PERFLPR1(0), 0x00000009); + mmio_write_32(DDRC_PERFWR1(0), 0x02005574); + mmio_write_32(DDRC_DBG0(0), 0x00000016); + mmio_write_32(DDRC_DBG1(0), 0x00000000); + mmio_write_32(DDRC_DBGCMD(0), 0x00000000); + mmio_write_32(DDRC_SWCTL(0), 0x00000001); + mmio_write_32(DDRC_POISONCFG(0), 0x00000011); + mmio_write_32(DDRC_PCCFG(0), 0x00000111); + mmio_write_32(DDRC_PCFGR_0(0), 0x000010f3); + mmio_write_32(DDRC_PCFGW_0(0), 0x000072ff); + mmio_write_32(DDRC_PCTRL_0(0), 0x00000001); + mmio_write_32(DDRC_PCFGQOS0_0(0), 0x01110d00); + mmio_write_32(DDRC_PCFGQOS1_0(0), 0x00620790); + mmio_write_32(DDRC_PCFGWQOS0_0(0), 0x00100001); + mmio_write_32(DDRC_PCFGWQOS1_0(0), 0x0000041f); + mmio_write_32(DDRC_FREQ1_DERATEEN(0), 0x00000202); + mmio_write_32(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5); + mmio_write_32(DDRC_FREQ1_RFSHCTL0(0), 0x00618040); + mmio_write_32(DDRC_FREQ1_RFSHTMG(0), 0x00610090); +} + +static inline void umctl2_freq1(void) +{ + mmio_write_32(DDRC_FREQ1_DERATEEN(0), 0x0000000); + mmio_write_32(DDRC_FREQ1_DERATEINT(0), 0x0800000); + mmio_write_32(DDRC_FREQ1_RFSHCTL0(0), 0x0210000); + mmio_write_32(DDRC_FREQ1_RFSHTMG(0), 0x014001E); + mmio_write_32(DDRC_FREQ1_INIT3(0), 0x0140009); + mmio_write_32(DDRC_FREQ1_INIT4(0), 0x00310008); + mmio_write_32(DDRC_FREQ1_INIT6(0), 0x0066004a); + mmio_write_32(DDRC_FREQ1_INIT7(0), 0x0006004a); + mmio_write_32(DDRC_FREQ1_DRAMTMG0(0), 0xB070A07); + mmio_write_32(DDRC_FREQ1_DRAMTMG1(0), 0x003040A); + mmio_write_32(DDRC_FREQ1_DRAMTMG2(0), 0x305080C); + mmio_write_32(DDRC_FREQ1_DRAMTMG3(0), 0x0505000); + mmio_write_32(DDRC_FREQ1_DRAMTMG4(0), 0x3040203); + mmio_write_32(DDRC_FREQ1_DRAMTMG5(0), 0x2030303); + mmio_write_32(DDRC_FREQ1_DRAMTMG6(0), 0x2020004); + mmio_write_32(DDRC_FREQ1_DRAMTMG7(0), 0x0000302); + mmio_write_32(DDRC_FREQ1_DRAMTMG12(0), 0x0020310); + mmio_write_32(DDRC_FREQ1_DRAMTMG13(0), 0xA100002); + mmio_write_32(DDRC_FREQ1_DRAMTMG14(0), 0x0000020); + mmio_write_32(DDRC_FREQ1_DRAMTMG17(0), 0x0220011); + mmio_write_32(DDRC_FREQ1_ZQCTL0(0), 0x0A70005); + mmio_write_32(DDRC_FREQ1_DFITMG0(0), 0x3858202); + mmio_write_32(DDRC_FREQ1_DFITMG1(0), 0x0000404); + mmio_write_32(DDRC_FREQ1_DFITMG2(0), 0x0000502); +} + +void lpddr4_cfg_umctl2(void) +{ + /* Start to config, default 3200mbps */ + mmio_write_32(DDRC_DBG1(0), 0x00000001); + mmio_write_32(DDRC_PWRCTL(0), 0x00000001); + mmio_write_32(DDRC_MSTR(0), 0xa3080020); + mmio_write_32(DDRC_MSTR2(0), 0x00000000); + mmio_write_32(DDRC_RFSHTMG(0), 0x006100E0); + mmio_write_32(DDRC_INIT0(0), 0xC003061B); + mmio_write_32(DDRC_INIT1(0), 0x009D0000); + mmio_write_32(DDRC_INIT3(0), 0x00D4002D); +#ifdef WR_POST_EXT_3200 /* recommened to define */ + mmio_write_32(DDRC_INIT4(0), 0x00330008); +#else + mmio_write_32(DDRC_INIT4(0), 0x00310008); +#endif + mmio_write_32(DDRC_INIT6(0), 0x0066004a); + mmio_write_32(DDRC_INIT7(0), 0x0006004a); + + mmio_write_32(DDRC_DRAMTMG0(0), 0x1A201B22); + mmio_write_32(DDRC_DRAMTMG1(0), 0x00060633); + mmio_write_32(DDRC_DRAMTMG3(0), 0x00C0C000); + mmio_write_32(DDRC_DRAMTMG4(0), 0x0F04080F); + mmio_write_32(DDRC_DRAMTMG5(0), 0x02040C0C); + mmio_write_32(DDRC_DRAMTMG6(0), 0x01010007); + mmio_write_32(DDRC_DRAMTMG7(0), 0x00000401); + mmio_write_32(DDRC_DRAMTMG12(0), 0x00020600); + mmio_write_32(DDRC_DRAMTMG13(0), 0x0C100002); + mmio_write_32(DDRC_DRAMTMG14(0), 0x000000E6); + mmio_write_32(DDRC_DRAMTMG17(0), 0x00A00050); + + mmio_write_32(DDRC_ZQCTL0(0), 0x03200018); + mmio_write_32(DDRC_ZQCTL1(0), 0x028061A8); + mmio_write_32(DDRC_ZQCTL2(0), 0x00000000); + + mmio_write_32(DDRC_DFITMG0(0), 0x0497820A); + mmio_write_32(DDRC_DFITMG1(0), 0x00080303); + mmio_write_32(DDRC_DFIUPD0(0), 0xE0400018); + mmio_write_32(DDRC_DFIUPD1(0), 0x00DF00E4); + mmio_write_32(DDRC_DFIUPD2(0), 0x80000000); + mmio_write_32(DDRC_DFIMISC(0), 0x00000011); + mmio_write_32(DDRC_DFITMG2(0), 0x0000170A); + + mmio_write_32(DDRC_DBICTL(0), 0x00000001); + mmio_write_32(DDRC_DFIPHYMSTR(0), 0x00000001); + + mmio_write_32(DDRC_RANKCTL(0), 0x00000c99); + mmio_write_32(DDRC_DRAMTMG2(0), 0x070E171a); + + /* address mapping */ + umctl2_addrmap(); + + /* performance setting */ + umctl2_perf(); + + /* freq set point 1 setting */ + umctl2_freq1(); +} diff --git a/plat/imx/imx8mq/ddr/lpddr4_dvfs.c b/plat/imx/imx8mq/ddr/lpddr4_dvfs.c new file mode 100644 index 00000000..8f37fc7d --- /dev/null +++ b/plat/imx/imx8mq/ddr/lpddr4_dvfs.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright 2017-2018 NXP. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <debug.h> +#include <stdbool.h> +#include <ddrc.h> +#include <mmio.h> +#include <platform_def.h> +#include <spinlock.h> +#include <soc.h> + +#include "lpddr4_dvfs.h" + +/* lock used for DDR DVFS */ +spinlock_t dfs_lock; +/* IRQ used for DDR DVFS */ +static uint32_t irqs_used [] = {102, 109, 110, 111}; +static volatile uint32_t wfe_done; +static volatile bool wait_ddrc_hwffc_done = true; + +static unsigned int init_fsp = 0x1; + +void lpddr4_switch_to_3200(void) +{ + lpddr4_dvfs_swffc(init_fsp, 0x0); +} + +/* + * x1: for DDR frequency target info + * x2: for online cpu info. + */ +int lpddr4_dvfs_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + unsigned int target_freq = x1; + uint32_t online_cores = x2; + + if (target_freq == 0xf) { + /* set the WFE done status */ + spin_lock(&dfs_lock); + wfe_done |= (1 << cpu_id * 8); + spin_unlock(&dfs_lock); + + while (1) { + /* ddr frequency change done */ + wfe(); + if (!wait_ddrc_hwffc_done) { + break; + } + } + } else { + wait_ddrc_hwffc_done = true; + /* trigger the IRQ */ + for (int i = 0; i < 4; i++) { + int irq = irqs_used[i] % 32; + if (cpu_id != i && (online_cores & (0x1 << (i * 8)))) { + mmio_write_32(0x38800204 + (irqs_used[i] / 32) * 4, (1 << irq)); + } + } + + /* make sure all the core in WFE */ + online_cores &= ~(0x1 << (cpu_id * 8)); + while (1) { + mmio_write_32(0x30340004, mmio_read_32(0x30340004) | (1 << 12)); + if (online_cores == wfe_done) + break; + } + + mmio_write_32(0x30340004, mmio_read_32(0x30340004) & ~(1 << 12)); + + /* flush the L1/L2 cache */ + dcsw_op_all(DCCSW); + + /* + * for DDR dvfs, we have two method: hwffc or swffc, + * the default method we used on i.MX8MQ is swffc. + */ +#if LPDDR4_DVFS_HWFFC + lpddr4_dvfs_hwffc(init_vrcg, init_fsp, target_freq, discamdrain); + init_fsp = (~init_fsp) & 0x1; +#else + lpddr4_dvfs_swffc(init_fsp, target_freq); +#endif + wait_ddrc_hwffc_done = false; + wfe_done = 0; + dsb(); + sev(); + isb(); + } + + return 0; +} + + + diff --git a/plat/imx/imx8mq/ddr/lpddr4_dvfs.h b/plat/imx/imx8mq/ddr/lpddr4_dvfs.h new file mode 100644 index 00000000..ba6351c1 --- /dev/null +++ b/plat/imx/imx8mq/ddr/lpddr4_dvfs.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright 2017-2018 NXP. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __LPDDR4_DVFS_H +#define __LPDDR4_DVFS_H + + +void lpddr4_dvfs_swffc(unsigned int init_fsp, unsigned int target_freq); +void lpddr4_dvfs_hwffc(int init_vrcg, int init_fsp, int target_freq, + int discamdrain); + +#endif /* __LPDDR4_DVFS_H */ diff --git a/plat/imx/imx8mq/ddr/lpddr4_hwffc.c b/plat/imx/imx8mq/ddr/lpddr4_hwffc.c new file mode 100644 index 00000000..cf46b7f9 --- /dev/null +++ b/plat/imx/imx8mq/ddr/lpddr4_hwffc.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright 2017-2018 NXP. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +void lpddr4_dvfs_hwffc(int init_vrcg, int init_fsp, int target_freq, + int discamdrain) +{ + uint32_t tmp, tmp_t; + + INFO("hwffc enter\n"); + + /* step 1: hwffc flow enter, set the HWFCCCTL */ + tmp = ((init_fsp << 4) & 0x10) | ((init_vrcg << 5) & 0x20) | 0x40; + tmp |= 0x3; + mmio_write_32(IMX_DDRC_BASE + DDRC_HWFFCCTL, tmp); + + /* + * set SWCTL.sw_done to disable quasi-dynamic register programming + * outside reset + */ + mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x0); + + mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x11); + + /* + * set SWCTL.sw_done to enable quasi-dynamic register programming + * outside reset. + */ + mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x1); + /*wait SWSTAT.sw_done_ack to 1 */ + while (!(mmio_read_32(IMX_DDRC_BASE + DDRC_SWSTAT) & 0x1)) + ; + + /* wait for DBGCAM is empty */ + if (discamdrain) + while ((mmio_read_32(IMX_DDRC_BASE + DDRC_DBGCAM) & + 0x30000000) != 0x30000000) + ; + + /* set HWFFC requirements, ddrc_csysfreqency_ddrc[1:0] = 2b'10; + * [15]: ccmsrcgpcmix_ddrc_csysdisdrain_ddrc; + * [14:13]: ccmsrcgpcmix_ddrc_csysfrequency_ddrc[1:0]; + * [12]: ccmsrcgpcmix_ddrc_csysmode_ddrc; + */ + tmp = mmio_read_32(0x303a0164); + tmp &= 0xFFFF0FFF; + tmp |= ((discamdrain << 15) & 0x8000); + tmp |= ((target_freq << 13) & 0x6000); + tmp |= 0x1000; + mmio_write_32(0x303a0164, tmp); + + /* set the gpc_ddr1_core_csysreq to active low */ + tmp = mmio_read_32(0x303a01fc); + tmp &= 0xfffffffe; + mmio_write_32(0x303a01fc, tmp); + + /* wait gpc_ddr1_core_csysack to active low */ + while ((mmio_read_32(0x303a01fc) & 0x10000)) + ; + + /* step B: switch the clock */ + if (target_freq == 0x1) { + /* change the clock source of dram_alt_clk_root to source 5 --400MHz */ + mmio_write_32(0x3038a008, (0x7 << 24) | (0x7 << 16)); + mmio_write_32(0x303aa004, (0x5 << 24)); + + /* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */ + mmio_write_32(0x3038a088, (0x7 << 24) | (0x7 << 16)); + mmio_write_32(0x3038a084, (0x2 << 24) | (0x1 << 16));; + + /* bypass the DRAM PLL */ + mmio_write_32(0x30389804, 1 << 24); + + } else if (target_freq == 0x2) { + /* change the clock source of dram_alt_clk_root to source 2 --100MHz */ + mmio_write_32(0x3038a008, (0x7 << 24) | (0x7 << 16)); + mmio_write_32(0x3038a004, (0x2 << 24)); + + /* change the clock source of dram_apb_clk_root to source 2 --40Mhz/2 */ + mmio_write_32(0x3038a088, (0x7 << 24) | (0x7 << 16)); + mmio_write_32(0x3038a084, (0x2 << 24) | (0x1 << 16));; + + /* bypass the DRAM PLL */ + mmio_write_32(0x30389804, 1 << 24); + } else { + /* switch to the default freq fsp = 0x1 3200mts */ + mmio_write_32(0x3038a088,(0x7<<24)|(0x7<<16)); + /* to source 4 --800MHz/ 4 */ + mmio_write_32(0x3038a084,(0x4<<24)|(0x3<<16)); + mmio_write_32(0x30389808, 1<<24); + } + + /* step C: exit hwffc flow */ + tmp = mmio_read_32(0x303a01fc); + tmp |= 0x1; + mmio_write_32(0x303a01fc, tmp); + /* wait gpc_ddr1_core_csysack to high */ + while (!(mmio_read_32(0x303a01fc) & 0x10000)) + ; + + /* [1:0]-->2b'10, to disable HWFFC */ + mmio_write_32(IMX_DDRC_BASE + DDRC_HWFFCCTL, 0x72); + + /*wait until hwffc_in_progress = 0 */ + while(mmio_read_32(IMX_DDRC_BASE + DDRC_HWFFCSTAT) & 0x1) + ; + + mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x0); + /* set MSTR.frequency_mode MSTR.[29], MSTR2.target_frequency[1:0] */ + tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_MSTR); + tmp |= 0x20000000; + mmio_write_32(IMX_DDRC_BASE + DDRC_MSTR, tmp); + + tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_HWFFCSTAT); + tmp_t = (tmp >> 4) & 0x3; + tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_MSTR2); + tmp = (tmp & 0xfffffffc) | tmp_t; + mmio_write_32(IMX_DDRC_BASE + DDRC_MSTR2, tmp); + + mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x1); + mmio_write_32(IMX_DDRC_BASE + DDRC_HWFFCCTL, 0x70); + + /* why we need below flow */ + mmio_write_32(IMX_DDRC_BASE + DDRC_PWRCTL, 0x1a8); + while ((mmio_read_32(IMX_DDRC_BASE + DDRC_STAT) & 0x3) != 0x3) + ; + /* wait SDRAM into self refresh state */ + while(!(mmio_read_32(IMX_DDRC_BASE + DDRC_STAT) & 0x30)) + ; + + tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_CRCPARSTAT); + tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_CRCPARSTAT); + + mmio_write_32(IMX_DDRC_BASE + DDRC_PWRCTL, 0x188); + + /* wait STAT to normal mode */ + while ((mmio_read_32(IMX_DDRC_BASE + DDRC_STAT) & 0x3) != 0x1) + ; + + INFO("hwffc exit\n"); +} diff --git a/plat/imx/imx8mq/ddr/lpddr4_phy_cfg.c b/plat/imx/imx8mq/ddr/lpddr4_phy_cfg.c new file mode 100644 index 00000000..765bcaf7 --- /dev/null +++ b/plat/imx/imx8mq/ddr/lpddr4_phy_cfg.c @@ -0,0 +1,1602 @@ +/* + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright 2017-2018 NXP. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <debug.h> +#include <stdbool.h> +#include <ddrc.h> +#include <mmio.h> +#include <platform_def.h> +#include <spinlock.h> +#include <soc.h> + +struct ddrphy_cfg_param { + uint32_t offset; /*reg offset */ + uint32_t val; /* config param */ +}; + +/* lpddr4 phy init config parameters */ +static const struct ddrphy_cfg_param phy_init_cfg[] = { + { .offset = 0x20110, .val = 0x02 }, /* MapCAB0toDFI */ + { .offset = 0x20111, .val = 0x03 }, /* MapCAB1toDFI */ + { .offset = 0x20112, .val = 0x04 }, /* MapCAB2toDFI */ + { .offset = 0x20113, .val = 0x05 }, /* MapCAB3toDFI */ + { .offset = 0x20114, .val = 0x00 }, /* MapCAB4toDFI */ + { .offset = 0x20115, .val = 0x01 }, /* MapCAB5toDFI */ + + /* Initialize PHY Configuration */ + { .offset = 0x1005f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 + { .offset = 0x1015f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 + { .offset = 0x1105f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 + { .offset = 0x1115f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 + { .offset = 0x1205f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 + { .offset = 0x1215f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 + { .offset = 0x1305f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 + { .offset = 0x1315f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 + + { .offset = 0x11005f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 + { .offset = 0x11015f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 + { .offset = 0x11105f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 + { .offset = 0x11115f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 + { .offset = 0x11205f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 + { .offset = 0x11215f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 + { .offset = 0x11305f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 + { .offset = 0x11315f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 + + { .offset = 0x21005f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 + { .offset = 0x21015f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 + { .offset = 0x21105f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 + { .offset = 0x21115f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 + { .offset = 0x21205f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 + { .offset = 0x21215f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 + { .offset = 0x21305f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 + { .offset = 0x21315f, .val = 0x1ff }, // DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 + + { .offset = 0x55, .val = 0x1ff }, // DWC_DDRPHYA_ANIB0_ATxSlewRate + { .offset = 0x1055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB1_ATxSlewRate + { .offset = 0x2055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB2_ATxSlewRate + { .offset = 0x3055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB3_ATxSlewRate + { .offset = 0x4055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB4_ATxSlewRate + { .offset = 0x5055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB5_ATxSlewRate + { .offset = 0x6055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB6_ATxSlewRate + { .offset = 0x7055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB7_ATxSlewRate + { .offset = 0x8055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB8_ATxSlewRate + { .offset = 0x9055, .val = 0x1ff }, // DWC_DDRPHYA_ANIB9_ATxSlewRate + { .offset = 0x200c5, .val = 0x19 }, // DWC_DDRPHYA_MASTER0_PllCtrl2_p0 + { .offset = 0x1200c5, .val = 0x7 }, // DWC_DDRPHYA_MASTER0_PllCtrl2_p1 + { .offset = 0x2200c5, .val = 0x7 }, // DWC_DDRPHYA_MASTER0_PllCtrl2_p2 + { .offset = 0x2002e, .val = 0x2 }, // DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 + { .offset = 0x12002e, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 + { .offset = 0x22002e, .val = 0x2 }, // DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 + { .offset = 0x90204, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_Seq0BGPR4_p0 + { .offset = 0x190204, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_Seq0BGPR4_p1 + { .offset = 0x290204, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_Seq0BGPR4_p2 + + { .offset = 0x20024, .val = 0xe3 }, // DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 + { .offset = 0x2003a, .val = 0x2 }, // DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl + { .offset = 0x120024, .val = 0xa3 }, // DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 + { .offset = 0x2003a, .val = 0x2 }, // DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl + { .offset = 0x220024, .val = 0xa3 }, // DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 + { .offset = 0x2003a, .val = 0x2 }, // DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl + + { .offset = 0x20056, .val = 0x3 }, // DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 + { .offset = 0x120056, .val = 0xa }, // DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 + { .offset = 0x220056, .val = 0xa }, // DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 + + { .offset = 0x1004d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 + { .offset = 0x1014d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 + { .offset = 0x1104d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 + { .offset = 0x1114d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 + { .offset = 0x1204d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 + { .offset = 0x1214d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 + { .offset = 0x1304d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 + { .offset = 0x1314d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 + { .offset = 0x11004d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 + { .offset = 0x11014d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 + { .offset = 0x11104d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 + { .offset = 0x11114d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 + { .offset = 0x11204d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 + { .offset = 0x11214d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 + { .offset = 0x11304d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 + { .offset = 0x11314d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 + { .offset = 0x21004d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 + { .offset = 0x21014d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 + { .offset = 0x21104d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 + { .offset = 0x21114d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 + { .offset = 0x21204d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 + { .offset = 0x21214d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 + { .offset = 0x21304d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 + { .offset = 0x21314d, .val = 0xe00 }, // DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 + + { .offset = 0x10049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 + { .offset = 0x10149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 + { .offset = 0x11049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 + { .offset = 0x11149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 + { .offset = 0x12049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 + { .offset = 0x12149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 + { .offset = 0x13049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 + { .offset = 0x13149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 + + { .offset = 0x110049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 + { .offset = 0x110149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 + { .offset = 0x111049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 + { .offset = 0x111149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 + { .offset = 0x112049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 + { .offset = 0x112149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 + { .offset = 0x113049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 + { .offset = 0x113149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 + + { .offset = 0x210049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 + { .offset = 0x210149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 + { .offset = 0x211049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 + { .offset = 0x211149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 + { .offset = 0x212049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 + { .offset = 0x212149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 + { .offset = 0x213049, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 + { .offset = 0x213149, .val = 0xfbe }, // DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 + + { .offset = 0x43, .val = 0x63 }, // DWC_DDRPHYA_ANIB0_ATxImpedance + { .offset = 0x1043, .val = 0x63 }, // DWC_DDRPHYA_ANIB1_ATxImpedance + { .offset = 0x2043, .val = 0x63 }, // DWC_DDRPHYA_ANIB2_ATxImpedance + { .offset = 0x3043, .val = 0x63 }, // DWC_DDRPHYA_ANIB3_ATxImpedance + { .offset = 0x4043, .val = 0x63 }, // DWC_DDRPHYA_ANIB4_ATxImpedance + { .offset = 0x5043, .val = 0x63 }, // DWC_DDRPHYA_ANIB5_ATxImpedance + { .offset = 0x6043, .val = 0x63 }, // DWC_DDRPHYA_ANIB6_ATxImpedance + { .offset = 0x7043, .val = 0x63 }, // DWC_DDRPHYA_ANIB7_ATxImpedance + { .offset = 0x8043, .val = 0x63 }, // DWC_DDRPHYA_ANIB8_ATxImpedance + { .offset = 0x9043, .val = 0x63 }, // DWC_DDRPHYA_ANIB9_ATxImpedance + + { .offset = 0x20018, .val = 0x3 }, // DWC_DDRPHYA_MASTER0_DfiMode + { .offset = 0x20075, .val = 0x4 }, // DWC_DDRPHYA_MASTER0_DfiCAMode + { .offset = 0x20050, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_CalDrvStr0 + { .offset = 0x20008, .val = 0x320 }, // DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 + { .offset = 0x120008, .val = 0xa7 }, // DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 + { .offset = 0x220008, .val = 0x19 }, // DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 + { .offset = 0x20088, .val = 0x9 }, // DWC_DDRPHYA_MASTER0_CalRate + { .offset = 0x200b2, .val = 0x104 }, // DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 + { .offset = 0x10043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 + { .offset = 0x10143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 + { .offset = 0x11043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 + { .offset = 0x11143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 + { .offset = 0x12043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 + { .offset = 0x12143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 + { .offset = 0x13043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 + { .offset = 0x13143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 + { .offset = 0x1200b2, .val = 0x104 }, // DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 + { .offset = 0x110043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 + { .offset = 0x110143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 + { .offset = 0x111043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 + { .offset = 0x111143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 + { .offset = 0x112043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 + { .offset = 0x112143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 + { .offset = 0x113043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 + { .offset = 0x113143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 + { .offset = 0x2200b2, .val = 0x104 }, // DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 + { .offset = 0x210043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 + { .offset = 0x210143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 + { .offset = 0x211043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 + { .offset = 0x211143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 + { .offset = 0x212043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 + { .offset = 0x212143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 + { .offset = 0x213043, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 + { .offset = 0x213143, .val = 0x5a1 }, // DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 + { .offset = 0x200fa, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 + { .offset = 0x1200fa, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 + { .offset = 0x2200fa, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 + { .offset = 0x20019, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_TristateModeCA_p0 + { .offset = 0x120019, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_TristateModeCA_p1 + { .offset = 0x220019, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_TristateModeCA_p2 + { .offset = 0x200f0, .val = 0x600 }, // DWC_DDRPHYA_MASTER0_DfiFreqXlat0 + { .offset = 0x200f1, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DfiFreqXlat1 + { .offset = 0x200f2, .val = 0x4444 }, // DWC_DDRPHYA_MASTER0_DfiFreqXlat2 + { .offset = 0x200f3, .val = 0x8888 }, // DWC_DDRPHYA_MASTER0_DfiFreqXlat3 + { .offset = 0x200f4, .val = 0x5655 }, // DWC_DDRPHYA_MASTER0_DfiFreqXlat4 + { .offset = 0x200f5, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DfiFreqXlat5 + { .offset = 0x200f6, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DfiFreqXlat6 + { .offset = 0x200f7, .val = 0xf000 }, // DWC_DDRPHYA_MASTER0_DfiFreqXlat7 + { .offset = 0x20025, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_MasterX4Config + { .offset = 0x2002d, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 + { .offset = 0x12002d, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 + { .offset = 0x22002d, .val = 0x0 }, // DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 +}; + +/* lpddr4 phy trained CSR registers */ +static struct ddrphy_cfg_param phy_trained_csr[] = { + { .offset = 0x200b2, .val = 0 }, + { .offset = 0x1200b2, .val = 0 }, + { .offset = 0x2200b2, .val = 0 }, + { .offset = 0x200cb, .val = 0 }, + { .offset = 0x10043, .val = 0 }, + { .offset = 0x110043, .val = 0 }, + { .offset = 0x210043, .val = 0 }, + { .offset = 0x10143, .val = 0 }, + { .offset = 0x110143, .val = 0 }, + { .offset = 0x210143, .val = 0 }, + { .offset = 0x11043, .val = 0 }, + { .offset = 0x111043, .val = 0 }, + { .offset = 0x211043, .val = 0 }, + { .offset = 0x11143, .val = 0 }, + { .offset = 0x111143, .val = 0 }, + { .offset = 0x211143, .val = 0 }, + { .offset = 0x12043, .val = 0 }, + { .offset = 0x112043, .val = 0 }, + { .offset = 0x212043, .val = 0 }, + { .offset = 0x12143, .val = 0 }, + { .offset = 0x112143, .val = 0 }, + { .offset = 0x212143, .val = 0 }, + { .offset = 0x13043, .val = 0 }, + { .offset = 0x113043, .val = 0 }, + { .offset = 0x213043, .val = 0 }, + { .offset = 0x13143, .val = 0 }, + { .offset = 0x113143, .val = 0 }, + { .offset = 0x213143, .val = 0 }, + { .offset = 0x80, .val = 0 }, + { .offset = 0x100080, .val = 0 }, + { .offset = 0x200080, .val = 0 }, + { .offset = 0x1080, .val = 0 }, + { .offset = 0x101080, .val = 0 }, + { .offset = 0x201080, .val = 0 }, + { .offset = 0x2080, .val = 0 }, + { .offset = 0x102080, .val = 0 }, + { .offset = 0x202080, .val = 0 }, + { .offset = 0x3080, .val = 0 }, + { .offset = 0x103080, .val = 0 }, + { .offset = 0x203080, .val = 0 }, + { .offset = 0x4080, .val = 0 }, + { .offset = 0x104080, .val = 0 }, + { .offset = 0x204080, .val = 0 }, + { .offset = 0x5080, .val = 0 }, + { .offset = 0x105080, .val = 0 }, + { .offset = 0x205080, .val = 0 }, + { .offset = 0x6080, .val = 0 }, + { .offset = 0x106080, .val = 0 }, + { .offset = 0x206080, .val = 0 }, + { .offset = 0x7080, .val = 0 }, + { .offset = 0x107080, .val = 0 }, + { .offset = 0x207080, .val = 0 }, + { .offset = 0x8080, .val = 0 }, + { .offset = 0x108080, .val = 0 }, + { .offset = 0x208080, .val = 0 }, + { .offset = 0x9080, .val = 0 }, + { .offset = 0x109080, .val = 0 }, + { .offset = 0x209080, .val = 0 }, + { .offset = 0x10080, .val = 0 }, + { .offset = 0x110080, .val = 0 }, + { .offset = 0x210080, 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.offset = 0x126c1, .val = 0 }, + { .offset = 0x1126c1, .val = 0 }, + { .offset = 0x2126c1, .val = 0 }, + { .offset = 0x127c1, .val = 0 }, + { .offset = 0x1127c1, .val = 0 }, + { .offset = 0x2127c1, .val = 0 }, + { .offset = 0x128c1, .val = 0 }, + { .offset = 0x1128c1, .val = 0 }, + { .offset = 0x2128c1, .val = 0 }, + { .offset = 0x130c1, .val = 0 }, + { .offset = 0x1130c1, .val = 0 }, + { .offset = 0x2130c1, .val = 0 }, + { .offset = 0x131c1, .val = 0 }, + { .offset = 0x1131c1, .val = 0 }, + { .offset = 0x2131c1, .val = 0 }, + { .offset = 0x132c1, .val = 0 }, + { .offset = 0x1132c1, .val = 0 }, + { .offset = 0x2132c1, .val = 0 }, + { .offset = 0x133c1, .val = 0 }, + { .offset = 0x1133c1, .val = 0 }, + { .offset = 0x2133c1, .val = 0 }, + { .offset = 0x134c1, .val = 0 }, + { .offset = 0x1134c1, .val = 0 }, + { .offset = 0x2134c1, .val = 0 }, + { .offset = 0x135c1, .val = 0 }, + { .offset = 0x1135c1, .val = 0 }, + { .offset = 0x2135c1, .val = 0 }, + { .offset = 0x136c1, .val = 0 }, + { .offset = 0x1136c1, .val = 0 }, + { .offset = 0x2136c1, .val = 0 }, + { .offset = 0x137c1, .val = 0 }, + { .offset = 0x1137c1, .val = 0 }, + { .offset = 0x2137c1, .val = 0 }, + { .offset = 0x138c1, .val = 0 }, + { .offset = 0x1138c1, .val = 0 }, + { .offset = 0x2138c1, .val = 0 }, + { .offset = 0x10020, .val = 0 }, + { .offset = 0x110020, .val = 0 }, + { .offset = 0x210020, .val = 0 }, + { .offset = 0x11020, .val = 0 }, + { .offset = 0x111020, .val = 0 }, + { .offset = 0x211020, .val = 0 }, + { .offset = 0x12020, .val = 0 }, + { .offset = 0x112020, .val = 0 }, + { .offset = 0x212020, .val = 0 }, + { .offset = 0x13020, .val = 0 }, + { .offset = 0x113020, .val = 0 }, + { .offset = 0x213020, .val = 0 }, + { .offset = 0x20072, .val = 0 }, + { .offset = 0x20073, .val = 0 }, + { .offset = 0x20074, .val = 0 }, + { .offset = 0x100aa, .val = 0 }, + { .offset = 0x110aa, .val = 0 }, + { .offset = 0x120aa, .val = 0 }, + { .offset = 0x130aa, .val = 0 }, + { .offset = 0x20010, .val = 0 }, + { .offset = 0x120010, .val = 0 }, + { .offset = 0x220010, .val = 0 }, + { .offset = 0x20011, .val = 0 }, + { .offset = 0x120011, .val = 0 }, + { .offset = 0x220011, .val = 0 }, + { .offset = 0x100ae, .val = 0 }, + { .offset = 0x1100ae, .val = 0 }, + { .offset = 0x2100ae, .val = 0 }, + { .offset = 0x100af, .val = 0 }, + { .offset = 0x1100af, .val = 0 }, + { .offset = 0x2100af, .val = 0 }, + { .offset = 0x110ae, .val = 0 }, + { .offset = 0x1110ae, .val = 0 }, + { .offset = 0x2110ae, .val = 0 }, + { .offset = 0x110af, .val = 0 }, + { .offset = 0x1110af, .val = 0 }, + { .offset = 0x2110af, .val = 0 }, + { .offset = 0x120ae, .val = 0 }, + { .offset = 0x1120ae, .val = 0 }, + { .offset = 0x2120ae, .val = 0 }, + { .offset = 0x120af, .val = 0 }, + { .offset = 0x1120af, .val = 0 }, + { .offset = 0x2120af, .val = 0 }, + { .offset = 0x130ae, .val = 0 }, + { .offset = 0x1130ae, .val = 0 }, + { .offset = 0x2130ae, .val = 0 }, + { .offset = 0x130af, .val = 0 }, + { .offset = 0x1130af, .val = 0 }, + { .offset = 0x2130af, .val = 0 }, + { .offset = 0x20020, .val = 0 }, + { .offset = 0x120020, .val = 0 }, + { .offset = 0x220020, .val = 0 }, + { .offset = 0x100a0, .val = 0 }, + { .offset = 0x100a1, .val = 0 }, + { .offset = 0x100a2, .val = 0 }, + { .offset = 0x100a3, .val = 0 }, + { .offset = 0x100a4, .val = 0 }, + { .offset = 0x100a5, .val = 0 }, + { .offset = 0x100a6, .val = 0 }, + { .offset = 0x100a7, .val = 0 }, + { .offset = 0x110a0, .val = 0 }, + { .offset = 0x110a1, .val = 0 }, + { .offset = 0x110a2, .val = 0 }, + { .offset = 0x110a3, .val = 0 }, + { .offset = 0x110a4, .val = 0 }, + { .offset = 0x110a5, .val = 0 }, + { .offset = 0x110a6, .val = 0 }, + { .offset = 0x110a7, .val = 0 }, + { .offset = 0x120a0, .val = 0 }, + { .offset = 0x120a1, .val = 0 }, + { .offset = 0x120a2, .val = 0 }, + { .offset = 0x120a3, .val = 0 }, + { .offset = 0x120a4, .val = 0 }, + { .offset = 0x120a5, .val = 0 }, + { .offset = 0x120a6, .val = 0 }, + { .offset = 0x120a7, .val = 0 }, + { .offset = 0x130a0, .val = 0 }, + { .offset = 0x130a1, .val = 0 }, + { .offset = 0x130a2, .val = 0 }, + { .offset = 0x130a3, .val = 0 }, + { .offset = 0x130a4, .val = 0 }, + { .offset = 0x130a5, .val = 0 }, + { .offset = 0x130a6, .val = 0 }, + { .offset = 0x130a7, .val = 0 }, + { .offset = 0x2007c, .val = 0 }, + { .offset = 0x12007c, .val = 0 }, + { .offset = 0x22007c, .val = 0 }, + { .offset = 0x2007d, .val = 0 }, + { .offset = 0x12007d, .val = 0 }, + { .offset = 0x22007d, .val = 0 }, + { .offset = 0x400fd, .val = 0 }, + { .offset = 0x400c0, .val = 0 }, + { .offset = 0x90201, .val = 0 }, + { .offset = 0x190201, .val = 0 }, + { .offset = 0x290201, .val = 0 }, + { .offset = 0x90202, .val = 0 }, + { .offset = 0x190202, .val = 0 }, + { .offset = 0x290202, .val = 0 }, + { .offset = 0x90203, .val = 0 }, + { .offset = 0x190203, .val = 0 }, + { .offset = 0x290203, .val = 0 }, + { .offset = 0x90204, .val = 0 }, + { .offset = 0x190204, .val = 0 }, + { .offset = 0x290204, .val = 0 }, + { .offset = 0x90205, .val = 0 }, + { .offset = 0x190205, .val = 0 }, + { .offset = 0x290205, .val = 0 }, + { .offset = 0x90206, .val = 0 }, + { .offset = 0x190206, .val = 0 }, + { .offset = 0x290206, .val = 0 }, + { .offset = 0x90207, .val = 0 }, + { .offset = 0x190207, .val = 0 }, + { .offset = 0x290207, .val = 0 }, + { .offset = 0x90208, .val = 0 }, + { .offset = 0x190208, .val = 0 }, + { .offset = 0x290208, .val = 0 }, + { .offset = 0x10062, .val = 0 }, + { .offset = 0x10162, .val = 0 }, + { .offset = 0x10262, .val = 0 }, + { .offset = 0x10362, .val = 0 }, + { .offset = 0x10462, .val = 0 }, + { .offset = 0x10562, .val = 0 }, + { .offset = 0x10662, .val = 0 }, + { .offset = 0x10762, .val = 0 }, + { .offset = 0x10862, .val = 0 }, + { .offset = 0x11062, .val = 0 }, + { .offset = 0x11162, .val = 0 }, + { .offset = 0x11262, .val = 0 }, + { .offset = 0x11362, .val = 0 }, + { .offset = 0x11462, .val = 0 }, + { .offset = 0x11562, .val = 0 }, + { .offset = 0x11662, .val = 0 }, + { .offset = 0x11762, .val = 0 }, + { .offset = 0x11862, .val = 0 }, + { .offset = 0x12062, .val = 0 }, + { .offset = 0x12162, .val = 0 }, + { .offset = 0x12262, .val = 0 }, + { .offset = 0x12362, .val = 0 }, + { .offset = 0x12462, .val = 0 }, + { .offset = 0x12562, .val = 0 }, + { .offset = 0x12662, .val = 0 }, + { .offset = 0x12762, .val = 0 }, + { .offset = 0x12862, .val = 0 }, + { .offset = 0x13062, .val = 0 }, + { .offset = 0x13162, .val = 0 }, + { .offset = 0x13262, .val = 0 }, + { .offset = 0x13362, .val = 0 }, + { .offset = 0x13462, .val = 0 }, + { .offset = 0x13562, .val = 0 }, + { .offset = 0x13662, .val = 0 }, + { .offset = 0x13762, .val = 0 }, + { .offset = 0x13862, .val = 0 }, + { .offset = 0x20077, .val = 0 }, + { .offset = 0x10001, .val = 0 }, + { .offset = 0x11001, .val = 0 }, + { .offset = 0x12001, .val = 0 }, + { .offset = 0x13001, .val = 0 }, + { .offset = 0x10040, .val = 0 }, + { .offset = 0x10140, .val = 0 }, + { .offset = 0x10240, .val = 0 }, + { .offset = 0x10340, .val = 0 }, + { .offset = 0x10440, .val = 0 }, + { .offset = 0x10540, .val = 0 }, + { .offset = 0x10640, .val = 0 }, + { .offset = 0x10740, .val = 0 }, + { .offset = 0x10840, .val = 0 }, + { .offset = 0x10030, .val = 0 }, + { .offset = 0x10130, .val = 0 }, + { .offset = 0x10230, .val = 0 }, + { .offset = 0x10330, .val = 0 }, + { .offset = 0x10430, .val = 0 }, + { .offset = 0x10530, .val = 0 }, + { .offset = 0x10630, .val = 0 }, + { .offset = 0x10730, .val = 0 }, + { .offset = 0x10830, .val = 0 }, + { .offset = 0x11040, .val = 0 }, + { .offset = 0x11140, .val = 0 }, + { .offset = 0x11240, .val = 0 }, + { .offset = 0x11340, .val = 0 }, + { .offset = 0x11440, .val = 0 }, + { .offset = 0x11540, .val = 0 }, + { .offset = 0x11640, .val = 0 }, + { .offset = 0x11740, .val = 0 }, + { .offset = 0x11840, .val = 0 }, + { .offset = 0x11030, .val = 0 }, + { .offset = 0x11130, .val = 0 }, + { .offset = 0x11230, .val = 0 }, + { .offset = 0x11330, .val = 0 }, + { .offset = 0x11430, .val = 0 }, + { .offset = 0x11530, .val = 0 }, + { .offset = 0x11630, .val = 0 }, + { .offset = 0x11730, .val = 0 }, + { .offset = 0x11830, .val = 0 }, + { .offset = 0x12040, .val = 0 }, + { .offset = 0x12140, .val = 0 }, + { .offset = 0x12240, .val = 0 }, + { .offset = 0x12340, .val = 0 }, + { .offset = 0x12440, .val = 0 }, + { .offset = 0x12540, .val = 0 }, + { .offset = 0x12640, .val = 0 }, + { .offset = 0x12740, .val = 0 }, + { .offset = 0x12840, .val = 0 }, + { .offset = 0x12030, .val = 0 }, + { .offset = 0x12130, .val = 0 }, + { .offset = 0x12230, .val = 0 }, + { .offset = 0x12330, .val = 0 }, + { .offset = 0x12430, .val = 0 }, + { .offset = 0x12530, .val = 0 }, + { .offset = 0x12630, .val = 0 }, + { .offset = 0x12730, .val = 0 }, + { .offset = 0x12830, .val = 0 }, + { .offset = 0x13040, .val = 0 }, + { .offset = 0x13140, .val = 0 }, + { .offset = 0x13240, .val = 0 }, + { .offset = 0x13340, .val = 0 }, + { .offset = 0x13440, .val = 0 }, + { .offset = 0x13540, .val = 0 }, + { .offset = 0x13640, .val = 0 }, + { .offset = 0x13740, .val = 0 }, + { .offset = 0x13840, .val = 0 }, + { .offset = 0x13030, .val = 0 }, + { .offset = 0x13130, .val = 0 }, + { .offset = 0x13230, .val = 0 }, + { .offset = 0x13330, .val = 0 }, + { .offset = 0x13430, .val = 0 }, + { .offset = 0x13530, .val = 0 }, + { .offset = 0x13630, .val = 0 }, + { .offset = 0x13730, .val = 0 }, + { .offset = 0x13830, .val = 0 }, +}; + +/* lpddr4 phy PIE image */ +static const struct ddrphy_cfg_param phy_pie[] = { + { .offset = 0xd0000, .val = 0x0 }, // DWC_DDRPHYA_APBONLY0_MicroContMuxSel + { .offset = 0x90000, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 + { .offset = 0x90001, .val = 0x400 }, // DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 + { .offset = 0x90002, .val = 0x10e }, // DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 + { .offset = 0x90003, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 + { .offset = 0x90004, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 + { .offset = 0x90005, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 + { .offset = 0x90029, .val = 0xb }, // DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 + { .offset = 0x9002a, .val = 0x480 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 + { .offset = 0x9002b, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 + { .offset = 0x9002c, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 + { .offset = 0x9002d, .val = 0x448 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 + { .offset = 0x9002e, .val = 0x139 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 + { .offset = 0x9002f, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 + { .offset = 0x90030, .val = 0x478 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 + { .offset = 0x90031, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 + { .offset = 0x90032, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 + { .offset = 0x90033, .val = 0xe8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 + { .offset = 0x90034, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 + { .offset = 0x90035, .val = 0x2 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 + { .offset = 0x90036, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 + { .offset = 0x90037, .val = 0x139 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 + { .offset = 0x90038, .val = 0xb }, // DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 + { .offset = 0x90039, .val = 0x7c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 + { .offset = 0x9003a, .val = 0x139 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 + { .offset = 0x9003b, .val = 0x44 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 + { .offset = 0x9003c, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 + { .offset = 0x9003d, .val = 0x159 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 + { .offset = 0x9003e, .val = 0x14f }, // DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 + { .offset = 0x9003f, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 + { .offset = 0x90040, .val = 0x159 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 + { .offset = 0x90041, .val = 0x47 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 + { .offset = 0x90042, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 + { .offset = 0x90043, .val = 0x149 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 + { .offset = 0x90044, .val = 0x4f }, // DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 + { .offset = 0x90045, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 + { .offset = 0x90046, .val = 0x179 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 + { .offset = 0x90047, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 + { .offset = 0x90048, .val = 0xe0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 + { .offset = 0x90049, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 + { .offset = 0x9004a, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 + { .offset = 0x9004b, .val = 0x7c8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 + { .offset = 0x9004c, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 + { .offset = 0x9004d, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 + { .offset = 0x9004e, .val = 0x1 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 + { .offset = 0x9004f, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 + { .offset = 0x90050, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 + { .offset = 0x90051, .val = 0x45a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 + { .offset = 0x90052, .val = 0x9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 + { .offset = 0x90053, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 + { .offset = 0x90054, .val = 0x448 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 + { .offset = 0x90055, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 + { .offset = 0x90056, .val = 0x40 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 + { .offset = 0x90057, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 + { .offset = 0x90058, .val = 0x179 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 + { .offset = 0x90059, .val = 0x1 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 + { .offset = 0x9005a, .val = 0x618 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 + { .offset = 0x9005b, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 + { .offset = 0x9005c, .val = 0x40c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 + { .offset = 0x9005d, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 + { .offset = 0x9005e, .val = 0x149 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 + { .offset = 0x9005f, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 + { .offset = 0x90060, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 + { .offset = 0x90061, .val = 0x48 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 + { .offset = 0x90062, .val = 0x4040 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 + { .offset = 0x90063, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 + { .offset = 0x90064, .val = 0x149 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 + { .offset = 0x90065, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 + { .offset = 0x90066, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 + { .offset = 0x90067, .val = 0x48 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 + { .offset = 0x90068, .val = 0x40 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 + { .offset = 0x90069, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 + { .offset = 0x9006a, .val = 0x149 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 + { .offset = 0x9006b, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 + { .offset = 0x9006c, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 + { .offset = 0x9006d, .val = 0x18 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 + { .offset = 0x9006e, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 + { .offset = 0x9006f, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 + { .offset = 0x90070, .val = 0x78 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 + { .offset = 0x90071, .val = 0x549 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 + { .offset = 0x90072, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 + { .offset = 0x90073, .val = 0x159 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 + { .offset = 0x90074, .val = 0xd49 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 + { .offset = 0x90075, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 + { .offset = 0x90076, .val = 0x159 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 + { .offset = 0x90077, .val = 0x94a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 + { .offset = 0x90078, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 + { .offset = 0x90079, .val = 0x159 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 + { .offset = 0x9007a, .val = 0x441 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 + { .offset = 0x9007b, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 + { .offset = 0x9007c, .val = 0x149 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 + { .offset = 0x9007d, .val = 0x42 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 + { .offset = 0x9007e, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 + { .offset = 0x9007f, .val = 0x149 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 + { .offset = 0x90080, .val = 0x1 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 + { .offset = 0x90081, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 + { .offset = 0x90082, .val = 0x149 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 + { .offset = 0x90083, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 + { .offset = 0x90084, .val = 0xe0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 + { .offset = 0x90085, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 + { .offset = 0x90086, .val = 0xa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 + { .offset = 0x90087, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 + { .offset = 0x90088, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 + { .offset = 0x90089, .val = 0x9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 + { .offset = 0x9008a, .val = 0x3c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 + { .offset = 0x9008b, .val = 0x149 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 + { .offset = 0x9008c, .val = 0x9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 + { .offset = 0x9008d, .val = 0x3c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 + { .offset = 0x9008e, .val = 0x159 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 + { .offset = 0x9008f, .val = 0x18 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 + { .offset = 0x90090, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 + { .offset = 0x90091, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 + { .offset = 0x90092, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 + { .offset = 0x90093, .val = 0x3c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 + { .offset = 0x90094, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 + { .offset = 0x90095, .val = 0x18 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 + { .offset = 0x90096, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 + { .offset = 0x90097, .val = 0x48 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 + { .offset = 0x90098, .val = 0x18 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 + { .offset = 0x90099, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 + { .offset = 0x9009a, .val = 0x58 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 + { .offset = 0x9009b, .val = 0xa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 + { .offset = 0x9009c, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 + { .offset = 0x9009d, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 + { .offset = 0x9009e, .val = 0x2 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 + { .offset = 0x9009f, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 + { .offset = 0x900a0, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 + { .offset = 0x900a1, .val = 0x5 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 + { .offset = 0x900a2, .val = 0x7c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 + { .offset = 0x900a3, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 + { .offset = 0x900a4, .val = 0xd }, // DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 + { .offset = 0x900a5, .val = 0x7c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 + { .offset = 0x900a6, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 + { .offset = 0x900a7, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 + { .offset = 0x900a8, .val = 0x7c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 + { .offset = 0x900a9, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 + { .offset = 0x40000, .val = 0x811 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x0 + { .offset = 0x40020, .val = 0x880 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x0 + { .offset = 0x40040, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x0 + { .offset = 0x40060, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x0 + { .offset = 0x40001, .val = 0x4008 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x1 + { .offset = 0x40021, .val = 0x83 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x1 + { .offset = 0x40041, .val = 0x4f }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x1 + { .offset = 0x40061, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x1 + { .offset = 0x40002, .val = 0x4040 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x2 + { .offset = 0x40022, .val = 0x83 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x2 + { .offset = 0x40042, .val = 0x51 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x2 + { .offset = 0x40062, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x2 + { .offset = 0x40003, .val = 0x811 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x3 + { .offset = 0x40023, .val = 0x880 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x3 + { .offset = 0x40043, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x3 + { .offset = 0x40063, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x3 + { .offset = 0x40004, .val = 0x720 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x4 + { .offset = 0x40024, .val = 0xf }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x4 + { .offset = 0x40044, .val = 0x1740 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x4 + { .offset = 0x40064, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x4 + { .offset = 0x40005, .val = 0x16 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x5 + { .offset = 0x40025, .val = 0x83 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x5 + { .offset = 0x40045, .val = 0x4b }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x5 + { .offset = 0x40065, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x5 + { .offset = 0x40006, .val = 0x716 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x6 + { .offset = 0x40026, .val = 0xf }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x6 + { .offset = 0x40046, .val = 0x2001 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x6 + { .offset = 0x40066, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x6 + { .offset = 0x40007, .val = 0x716 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x7 + { .offset = 0x40027, .val = 0xf }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x7 + { .offset = 0x40047, .val = 0x2800 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x7 + { .offset = 0x40067, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x7 + { .offset = 0x40008, .val = 0x716 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x8 + { .offset = 0x40028, .val = 0xf }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x8 + { .offset = 0x40048, .val = 0xf00 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x8 + { .offset = 0x40068, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x8 + { .offset = 0x40009, .val = 0x720 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x9 + { .offset = 0x40029, .val = 0xf }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x9 + { .offset = 0x40049, .val = 0x1400 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x9 + { .offset = 0x40069, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x9 + { .offset = 0x4000a, .val = 0xe08 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x10 + { .offset = 0x4002a, .val = 0xc15 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x10 + { .offset = 0x4004a, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x10 + { .offset = 0x4006a, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x10 + { .offset = 0x4000b, .val = 0x623 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x11 + { .offset = 0x4002b, .val = 0x15 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x11 + { .offset = 0x4004b, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x11 + { .offset = 0x4006b, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x11 + { .offset = 0x4000c, .val = 0x4028 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x12 + { .offset = 0x4002c, .val = 0x80 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x12 + { .offset = 0x4004c, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x12 + { .offset = 0x4006c, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x12 + { .offset = 0x4000d, .val = 0xe08 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x13 + { .offset = 0x4002d, .val = 0xc1a }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x13 + { .offset = 0x4004d, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x13 + { .offset = 0x4006d, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x13 + { .offset = 0x4000e, .val = 0x623 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x14 + { .offset = 0x4002e, .val = 0x1a }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x14 + { .offset = 0x4004e, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x14 + { .offset = 0x4006e, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x14 + { .offset = 0x4000f, .val = 0x4040 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x15 + { .offset = 0x4002f, .val = 0x80 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x15 + { .offset = 0x4004f, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x15 + { .offset = 0x4006f, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x15 + { .offset = 0x40010, .val = 0x2604 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x16 + { .offset = 0x40030, .val = 0x15 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x16 + { .offset = 0x40050, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x16 + { .offset = 0x40070, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x16 + { .offset = 0x40011, .val = 0x708 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x17 + { .offset = 0x40031, .val = 0x5 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x17 + { .offset = 0x40051, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x17 + { .offset = 0x40071, .val = 0x2002 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x17 + { .offset = 0x40012, .val = 0x8 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x18 + { .offset = 0x40032, .val = 0x80 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x18 + { .offset = 0x40052, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x18 + { .offset = 0x40072, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x18 + { .offset = 0x40013, .val = 0x2604 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x19 + { .offset = 0x40033, .val = 0x1a }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x19 + { .offset = 0x40053, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x19 + { .offset = 0x40073, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x19 + { .offset = 0x40014, .val = 0x708 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x20 + { .offset = 0x40034, .val = 0xa }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x20 + { .offset = 0x40054, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x20 + { .offset = 0x40074, .val = 0x2002 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x20 + { .offset = 0x40015, .val = 0x4040 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x21 + { .offset = 0x40035, .val = 0x80 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x21 + { .offset = 0x40055, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x21 + { .offset = 0x40075, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x21 + { .offset = 0x40016, .val = 0x60a }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x22 + { .offset = 0x40036, .val = 0x15 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x22 + { .offset = 0x40056, .val = 0x1200 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x22 + { .offset = 0x40076, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x22 + { .offset = 0x40017, .val = 0x61a }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x23 + { .offset = 0x40037, .val = 0x15 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x23 + { .offset = 0x40057, .val = 0x1300 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x23 + { .offset = 0x40077, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x23 + { .offset = 0x40018, .val = 0x60a }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x24 + { .offset = 0x40038, .val = 0x1a }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x24 + { .offset = 0x40058, .val = 0x1200 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x24 + { .offset = 0x40078, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x24 + { .offset = 0x40019, .val = 0x642 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x25 + { .offset = 0x40039, .val = 0x1a }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x25 + { .offset = 0x40059, .val = 0x1300 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x25 + { .offset = 0x40079, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x25 + { .offset = 0x4001a, .val = 0x4808 }, // DWC_DDRPHYA_ACSM0_AcsmSeq0x26 + { .offset = 0x4003a, .val = 0x880 }, // DWC_DDRPHYA_ACSM0_AcsmSeq1x26 + { .offset = 0x4005a, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq2x26 + { .offset = 0x4007a, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmSeq3x26 + { .offset = 0x900aa, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 + { .offset = 0x900ab, .val = 0x790 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 + { .offset = 0x900ac, .val = 0x11a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 + { .offset = 0x900ad, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 + { .offset = 0x900ae, .val = 0x7aa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 + { .offset = 0x900af, .val = 0x2a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 + { .offset = 0x900b0, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 + { .offset = 0x900b1, .val = 0x7b2 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 + { .offset = 0x900b2, .val = 0x2a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 + { .offset = 0x900b3, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 + { .offset = 0x900b4, .val = 0x7c8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 + { .offset = 0x900b5, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 + { .offset = 0x900b6, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 + { .offset = 0x900b7, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 + { .offset = 0x900b8, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 + { .offset = 0x900b9, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 + { .offset = 0x900ba, .val = 0x2a8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 + { .offset = 0x900bb, .val = 0x129 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 + { .offset = 0x900bc, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 + { .offset = 0x900bd, .val = 0x370 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 + { .offset = 0x900be, .val = 0x129 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 + { .offset = 0x900bf, .val = 0xa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 + { .offset = 0x900c0, .val = 0x3c8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 + { .offset = 0x900c1, .val = 0x1a9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 + { .offset = 0x900c2, .val = 0xc }, // DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 + { .offset = 0x900c3, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 + { .offset = 0x900c4, .val = 0x199 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 + { .offset = 0x900c5, .val = 0x14 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 + { .offset = 0x900c6, .val = 0x790 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 + { .offset = 0x900c7, .val = 0x11a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 + { .offset = 0x900c8, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 + { .offset = 0x900c9, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 + { .offset = 0x900ca, .val = 0x18 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 + { .offset = 0x900cb, .val = 0xe }, // DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 + { .offset = 0x900cc, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 + { .offset = 0x900cd, .val = 0x199 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 + { .offset = 0x900ce, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b55s0 + { .offset = 0x900cf, .val = 0x8568 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b55s1 + { .offset = 0x900d0, .val = 0x108 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b55s2 + { .offset = 0x900d1, .val = 0x18 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b56s0 + { .offset = 0x900d2, .val = 0x790 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b56s1 + { .offset = 0x900d3, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b56s2 + { .offset = 0x900d4, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b57s0 + { .offset = 0x900d5, .val = 0x1d8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b57s1 + { .offset = 0x900d6, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b57s2 + { .offset = 0x900d7, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b58s0 + { .offset = 0x900d8, .val = 0x8558 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b58s1 + { .offset = 0x900d9, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b58s2 + { .offset = 0x900da, .val = 0x70 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b59s0 + { .offset = 0x900db, .val = 0x788 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b59s1 + { .offset = 0x900dc, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b59s2 + { .offset = 0x900dd, .val = 0x1ff8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b60s0 + { .offset = 0x900de, .val = 0x85a8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b60s1 + { .offset = 0x900df, .val = 0x1e8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b60s2 + { .offset = 0x900e0, .val = 0x50 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b61s0 + { .offset = 0x900e1, .val = 0x798 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b61s1 + { .offset = 0x900e2, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b61s2 + { .offset = 0x900e3, .val = 0x60 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b62s0 + { .offset = 0x900e4, .val = 0x7a0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b62s1 + { .offset = 0x900e5, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b62s2 + { .offset = 0x900e6, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b63s0 + { .offset = 0x900e7, .val = 0x8310 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b63s1 + { .offset = 0x900e8, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b63s2 + { .offset = 0x900e9, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b64s0 + { .offset = 0x900ea, .val = 0xa310 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b64s1 + { .offset = 0x900eb, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b64s2 + { .offset = 0x900ec, .val = 0xa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b65s0 + { .offset = 0x900ed, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b65s1 + { .offset = 0x900ee, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b65s2 + { .offset = 0x900ef, .val = 0x6e }, // DWC_DDRPHYA_INITENG0_SequenceReg0b66s0 + { .offset = 0x900f0, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b66s1 + { .offset = 0x900f1, .val = 0x68 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b66s2 + { .offset = 0x900f2, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b67s0 + { .offset = 0x900f3, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b67s1 + { .offset = 0x900f4, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b67s2 + { .offset = 0x900f5, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b68s0 + { .offset = 0x900f6, .val = 0x8310 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b68s1 + { .offset = 0x900f7, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b68s2 + { .offset = 0x900f8, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b69s0 + { .offset = 0x900f9, .val = 0xa310 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b69s1 + { .offset = 0x900fa, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b69s2 + { .offset = 0x900fb, .val = 0x1ff8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b70s0 + { .offset = 0x900fc, .val = 0x85a8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b70s1 + { .offset = 0x900fd, .val = 0x1e8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b70s2 + { .offset = 0x900fe, .val = 0x68 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b71s0 + { .offset = 0x900ff, .val = 0x798 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b71s1 + { .offset = 0x90100, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b71s2 + { .offset = 0x90101, .val = 0x78 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b72s0 + { .offset = 0x90102, .val = 0x7a0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b72s1 + { .offset = 0x90103, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b72s2 + { .offset = 0x90104, .val = 0x68 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b73s0 + { .offset = 0x90105, .val = 0x790 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b73s1 + { .offset = 0x90106, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b73s2 + { .offset = 0x90107, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b74s0 + { .offset = 0x90108, .val = 0x8b10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b74s1 + { .offset = 0x90109, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b74s2 + { .offset = 0x9010a, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b75s0 + { .offset = 0x9010b, .val = 0xab10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b75s1 + { .offset = 0x9010c, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b75s2 + { .offset = 0x9010d, .val = 0xa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b76s0 + { .offset = 0x9010e, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b76s1 + { .offset = 0x9010f, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b76s2 + { .offset = 0x90110, .val = 0x58 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b77s0 + { .offset = 0x90111, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b77s1 + { .offset = 0x90112, .val = 0x68 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b77s2 + { .offset = 0x90113, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b78s0 + { .offset = 0x90114, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b78s1 + { .offset = 0x90115, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b78s2 + { .offset = 0x90116, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b79s0 + { .offset = 0x90117, .val = 0x8b10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b79s1 + { .offset = 0x90118, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b79s2 + { .offset = 0x90119, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b80s0 + { .offset = 0x9011a, .val = 0xab10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b80s1 + { .offset = 0x9011b, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b80s2 + { .offset = 0x9011c, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b81s0 + { .offset = 0x9011d, .val = 0x1d8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b81s1 + { .offset = 0x9011e, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b81s2 + { .offset = 0x9011f, .val = 0x80 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b82s0 + { .offset = 0x90120, .val = 0x790 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b82s1 + { .offset = 0x90121, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b82s2 + { .offset = 0x90122, .val = 0x18 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b83s0 + { .offset = 0x90123, .val = 0x7aa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b83s1 + { .offset = 0x90124, .val = 0x6a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b83s2 + { .offset = 0x90125, .val = 0xa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b84s0 + { .offset = 0x90126, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b84s1 + { .offset = 0x90127, .val = 0x1e9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b84s2 + { .offset = 0x90128, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b85s0 + { .offset = 0x90129, .val = 0x8080 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b85s1 + { .offset = 0x9012a, .val = 0x108 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b85s2 + { .offset = 0x9012b, .val = 0xf }, // DWC_DDRPHYA_INITENG0_SequenceReg0b86s0 + { .offset = 0x9012c, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b86s1 + { .offset = 0x9012d, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b86s2 + { .offset = 0x9012e, .val = 0xc }, // DWC_DDRPHYA_INITENG0_SequenceReg0b87s0 + { .offset = 0x9012f, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b87s1 + { .offset = 0x90130, .val = 0x68 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b87s2 + { .offset = 0x90131, .val = 0x9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b88s0 + { .offset = 0x90132, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b88s1 + { .offset = 0x90133, .val = 0x1a9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b88s2 + { .offset = 0x90134, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b89s0 + { .offset = 0x90135, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b89s1 + { .offset = 0x90136, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b89s2 + { .offset = 0x90137, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b90s0 + { .offset = 0x90138, .val = 0x8080 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b90s1 + { .offset = 0x90139, .val = 0x108 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b90s2 + { .offset = 0x9013a, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b91s0 + { .offset = 0x9013b, .val = 0x7aa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b91s1 + { .offset = 0x9013c, .val = 0x6a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b91s2 + { .offset = 0x9013d, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b92s0 + { .offset = 0x9013e, .val = 0x8568 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b92s1 + { .offset = 0x9013f, .val = 0x108 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b92s2 + { .offset = 0x90140, .val = 0xb7 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b93s0 + { .offset = 0x90141, .val = 0x790 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b93s1 + { .offset = 0x90142, .val = 0x16a }, // DWC_DDRPHYA_INITENG0_SequenceReg0b93s2 + { .offset = 0x90143, .val = 0x1f }, // DWC_DDRPHYA_INITENG0_SequenceReg0b94s0 + { .offset = 0x90144, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b94s1 + { .offset = 0x90145, .val = 0x68 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b94s2 + { .offset = 0x90146, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b95s0 + { .offset = 0x90147, .val = 0x8558 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b95s1 + { .offset = 0x90148, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b95s2 + { .offset = 0x90149, .val = 0xf }, // DWC_DDRPHYA_INITENG0_SequenceReg0b96s0 + { .offset = 0x9014a, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b96s1 + { .offset = 0x9014b, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b96s2 + { .offset = 0x9014c, .val = 0xc }, // DWC_DDRPHYA_INITENG0_SequenceReg0b97s0 + { .offset = 0x9014d, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b97s1 + { .offset = 0x9014e, .val = 0x68 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b97s2 + { .offset = 0x9014f, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b98s0 + { .offset = 0x90150, .val = 0x408 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b98s1 + { .offset = 0x90151, .val = 0x169 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b98s2 + { .offset = 0x90152, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b99s0 + { .offset = 0x90153, .val = 0x8558 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b99s1 + { .offset = 0x90154, .val = 0x168 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b99s2 + { .offset = 0x90155, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b100s0 + { .offset = 0x90156, .val = 0x3c8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b100s1 + { .offset = 0x90157, .val = 0x1a9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b100s2 + { .offset = 0x90158, .val = 0x3 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b101s0 + { .offset = 0x90159, .val = 0x370 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b101s1 + { .offset = 0x9015a, .val = 0x129 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b101s2 + { .offset = 0x9015b, .val = 0x20 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b102s0 + { .offset = 0x9015c, .val = 0x2aa }, // DWC_DDRPHYA_INITENG0_SequenceReg0b102s1 + { .offset = 0x9015d, .val = 0x9 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b102s2 + { .offset = 0x9015e, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b103s0 + { .offset = 0x9015f, .val = 0x400 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b103s1 + { .offset = 0x90160, .val = 0x10e }, // DWC_DDRPHYA_INITENG0_SequenceReg0b103s2 + { .offset = 0x90161, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b104s0 + { .offset = 0x90162, .val = 0xe8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b104s1 + { .offset = 0x90163, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b104s2 + { .offset = 0x90164, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b105s0 + { .offset = 0x90165, .val = 0x8140 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b105s1 + { .offset = 0x90166, .val = 0x10c }, // DWC_DDRPHYA_INITENG0_SequenceReg0b105s2 + { .offset = 0x90167, .val = 0x10 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b106s0 + { .offset = 0x90168, .val = 0x8138 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b106s1 + { .offset = 0x90169, .val = 0x10c }, // DWC_DDRPHYA_INITENG0_SequenceReg0b106s2 + { .offset = 0x9016a, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b107s0 + { .offset = 0x9016b, .val = 0x7c8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b107s1 + { .offset = 0x9016c, .val = 0x101 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b107s2 + { .offset = 0x9016d, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b108s0 + { .offset = 0x9016e, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b108s1 + { .offset = 0x9016f, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b108s2 + { .offset = 0x90170, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b109s0 + { .offset = 0x90171, .val = 0x448 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b109s1 + { .offset = 0x90172, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b109s2 + { .offset = 0x90173, .val = 0xf }, // DWC_DDRPHYA_INITENG0_SequenceReg0b110s0 + { .offset = 0x90174, .val = 0x7c0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b110s1 + { .offset = 0x90175, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b110s2 + { .offset = 0x90176, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b111s0 + { .offset = 0x90177, .val = 0xe8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b111s1 + { .offset = 0x90178, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b111s2 + { .offset = 0x90179, .val = 0x47 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b112s0 + { .offset = 0x9017a, .val = 0x630 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b112s1 + { .offset = 0x9017b, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b112s2 + { .offset = 0x9017c, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b113s0 + { .offset = 0x9017d, .val = 0x618 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b113s1 + { .offset = 0x9017e, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b113s2 + { .offset = 0x9017f, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b114s0 + { .offset = 0x90180, .val = 0xe0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b114s1 + { .offset = 0x90181, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b114s2 + { .offset = 0x90182, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b115s0 + { .offset = 0x90183, .val = 0x7c8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b115s1 + { .offset = 0x90184, .val = 0x109 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b115s2 + { .offset = 0x90185, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b116s0 + { .offset = 0x90186, .val = 0x8140 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b116s1 + { .offset = 0x90187, .val = 0x10c }, // DWC_DDRPHYA_INITENG0_SequenceReg0b116s2 + { .offset = 0x90188, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b117s0 + { .offset = 0x90189, .val = 0x1 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b117s1 + { .offset = 0x9018a, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b117s2 + { .offset = 0x9018b, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b118s0 + { .offset = 0x9018c, .val = 0x4 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b118s1 + { .offset = 0x9018d, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b118s2 + { .offset = 0x9018e, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b119s0 + { .offset = 0x9018f, .val = 0x7c8 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b119s1 + { .offset = 0x90190, .val = 0x101 }, // DWC_DDRPHYA_INITENG0_SequenceReg0b119s2 + { .offset = 0x90006, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 + { .offset = 0x90007, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 + { .offset = 0x90008, .val = 0x8 }, // DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 + { .offset = 0x90009, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 + { .offset = 0x9000a, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 + { .offset = 0x9000b, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 + { .offset = 0xd00e7, .val = 0x400 }, // DWC_DDRPHYA_APBONLY0_SequencerOverride + { .offset = 0x90017, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_StartVector0b0 + { .offset = 0x9001f, .val = 0x2b }, // DWC_DDRPHYA_INITENG0_StartVector0b8 + { .offset = 0x90026, .val = 0x6c }, // DWC_DDRPHYA_INITENG0_StartVector0b15 + { .offset = 0x400d0, .val = 0x0 }, // DWC_DDRPHYA_ACSM0_AcsmCsMapCtrl0 + { .offset = 0x400d1, .val = 0x101 }, // DWC_DDRPHYA_ACSM0_AcsmCsMapCtrl1 + { .offset = 0x400d2, .val = 0x105 }, // DWC_DDRPHYA_ACSM0_AcsmCsMapCtrl2 + { .offset = 0x400d3, .val = 0x107 }, // DWC_DDRPHYA_ACSM0_AcsmCsMapCtrl3 + { .offset = 0x400d4, .val = 0x10f }, // DWC_DDRPHYA_ACSM0_AcsmCsMapCtrl4 + { .offset = 0x400d5, .val = 0x202 }, // DWC_DDRPHYA_ACSM0_AcsmCsMapCtrl5 + { .offset = 0x400d6, .val = 0x20a }, // DWC_DDRPHYA_ACSM0_AcsmCsMapCtrl6 + { .offset = 0x400d7, .val = 0x20b }, // DWC_DDRPHYA_ACSM0_AcsmCsMapCtrl7 + { .offset = 0x2003a, .val = 0x2 }, // DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl + { .offset = 0x2000b, .val = 0x64 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 + { .offset = 0x2000c, .val = 0xc8 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 + { .offset = 0x2000d, .val = 0x7d0 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 + { .offset = 0x2000e, .val = 0x2c }, // DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 + { .offset = 0x12000b, .val = 0x14 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 + { .offset = 0x12000c, .val = 0x29 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 + { .offset = 0x12000d, .val = 0x1a1 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 + { .offset = 0x12000e, .val = 0x10 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 + { .offset = 0x22000b, .val = 0x3 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 + { .offset = 0x22000c, .val = 0x6 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 + { .offset = 0x22000d, .val = 0x3e }, // DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 + { .offset = 0x22000e, .val = 0x10 }, // DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 + { .offset = 0x9000c, .val = 0x0 }, // DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 + { .offset = 0x9000d, .val = 0x173 }, // DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 + { .offset = 0x9000e, .val = 0x60 }, // DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 + { .offset = 0x9000f, .val = 0x6110 }, // DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 + { .offset = 0x90010, .val = 0x2152 }, // DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 + { .offset = 0x90011, .val = 0xdfbd }, // DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 + { .offset = 0x90012, .val = 0x60 }, // DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 + { .offset = 0x90013, .val = 0x6152 }, // DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 + { .offset = 0x20010, .val = 0x5a }, // DWC_DDRPHYA_MASTER0_PPTTrainSetup_p0 + { .offset = 0x20011, .val = 0x3 }, // DWC_DDRPHYA_MASTER0_PPTTrainSetup2_p0 + { .offset = 0x40080, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x0_p0 + { .offset = 0x40081, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x0_p0 + { .offset = 0x40082, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x1_p0 + { .offset = 0x40083, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x1_p0 + { .offset = 0x40084, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x2_p0 + { .offset = 0x40085, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x2_p0 + { .offset = 0x140080, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x0_p1 + { .offset = 0x140081, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x0_p1 + { .offset = 0x140082, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x1_p1 + { .offset = 0x140083, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x1_p1 + { .offset = 0x140084, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x2_p1 + { .offset = 0x140085, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x2_p1 + { .offset = 0x240080, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x0_p2 + { .offset = 0x240081, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x0_p2 + { .offset = 0x240082, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x1_p2 + { .offset = 0x240083, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x1_p2 + { .offset = 0x240084, .val = 0xe0 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback0x2_p2 + { .offset = 0x240085, .val = 0x12 }, // DWC_DDRPHYA_ACSM0_AcsmPlayback1x2_p2 + { .offset = 0x400fd, .val = 0xf }, // DWC_DDRPHYA_ACSM0_AcsmCtrl13 + { .offset = 0x10011, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_TsmByte1 + { .offset = 0x10012, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_TsmByte2 + { .offset = 0x10013, .val = 0x180 }, // DWC_DDRPHYA_DBYTE0_TsmByte3 + { .offset = 0x10018, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_TsmByte5 + { .offset = 0x10002, .val = 0x6209 }, // DWC_DDRPHYA_DBYTE0_TrainingParam + { .offset = 0x100b2, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm0_i0 + { .offset = 0x101b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm2_i1 + { .offset = 0x102b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm2_i2 + { .offset = 0x103b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm2_i3 + { .offset = 0x104b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm2_i4 + { .offset = 0x105b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm2_i5 + { .offset = 0x106b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm2_i6 + { .offset = 0x107b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm2_i7 + { .offset = 0x108b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE0_Tsm2_i8 + { .offset = 0x11011, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_TsmByte1 + { .offset = 0x11012, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_TsmByte2 + { .offset = 0x11013, .val = 0x180 }, // DWC_DDRPHYA_DBYTE1_TsmByte3 + { .offset = 0x11018, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_TsmByte5 + { .offset = 0x11002, .val = 0x6209 }, // DWC_DDRPHYA_DBYTE1_TrainingParam + { .offset = 0x110b2, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm0_i0 + { .offset = 0x111b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm2_i1 + { .offset = 0x112b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm2_i2 + { .offset = 0x113b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm2_i3 + { .offset = 0x114b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm2_i4 + { .offset = 0x115b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm2_i5 + { .offset = 0x116b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm2_i6 + { .offset = 0x117b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm2_i7 + { .offset = 0x118b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE1_Tsm2_i8 + { .offset = 0x12011, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_TsmByte1 + { .offset = 0x12012, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_TsmByte2 + { .offset = 0x12013, .val = 0x180 }, // DWC_DDRPHYA_DBYTE2_TsmByte3 + { .offset = 0x12018, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_TsmByte5 + { .offset = 0x12002, .val = 0x6209 }, // DWC_DDRPHYA_DBYTE2_TrainingParam + { .offset = 0x120b2, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm0_i0 + { .offset = 0x121b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm2_i1 + { .offset = 0x122b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm2_i2 + { .offset = 0x123b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm2_i3 + { .offset = 0x124b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm2_i4 + { .offset = 0x125b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm2_i5 + { .offset = 0x126b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm2_i6 + { .offset = 0x127b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm2_i7 + { .offset = 0x128b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE2_Tsm2_i8 + { .offset = 0x13011, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_TsmByte1 + { .offset = 0x13012, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_TsmByte2 + { .offset = 0x13013, .val = 0x180 }, // DWC_DDRPHYA_DBYTE3_TsmByte3 + { .offset = 0x13018, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_TsmByte5 + { .offset = 0x13002, .val = 0x6209 }, // DWC_DDRPHYA_DBYTE3_TrainingParam + { .offset = 0x130b2, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm0_i0 + { .offset = 0x131b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm2_i1 + { .offset = 0x132b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm2_i2 + { .offset = 0x133b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm2_i3 + { .offset = 0x134b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm2_i4 + { .offset = 0x135b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm2_i5 + { .offset = 0x136b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm2_i6 + { .offset = 0x137b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm2_i7 + { .offset = 0x138b4, .val = 0x1 }, // DWC_DDRPHYA_DBYTE3_Tsm2_i8 + { .offset = 0x20089, .val = 0x1 }, // DWC_DDRPHYA_MASTER0_CalZap + { .offset = 0x20088, .val = 0x19 }, // DWC_DDRPHYA_MASTER0_CalRate + { .offset = 0xc0080, .val = 0x2 }, // DWC_DDRPHYA_DRTUB0_UcclkHclkEnables + { .offset = 0xd0000, .val = 0x1 }, // DWC_DDRPHYA_APBONLY0_MicroContMuxSel +}; + +static void lpddr4_phy_init_cfg(void) +{ + int index, offset, val, size; + + size = sizeof(phy_init_cfg) / 8; + + for (index = 0; index < size; index++) { + val = phy_init_cfg[index].val; + offset = phy_init_cfg[index].offset; + dwc_ddrphy_apb_wr(offset, val); + } +} + +static void lpddr4_phy_restore_trained_csr(void) +{ + int index, offset, val, size; + + dwc_ddrphy_apb_wr(0xd0000,0x0); + size = sizeof(phy_trained_csr) / 8; + + for(index = 0; index < size; index++) { + val = phy_trained_csr[index].val; + offset = phy_trained_csr[index].offset; + + dwc_ddrphy_apb_wr(offset, val); + } + dwc_ddrphy_apb_wr(0xd0000,0x1); +} + +static void lpddr4_phy_load_pie(void) +{ + int index, offset, val, size; + + size = sizeof(phy_pie) / 8; + + for(index = 0; index < size; index++) { + val = phy_pie[index].val; + offset = phy_pie[index].offset; + + dwc_ddrphy_apb_wr(offset, val); + } +} + +void lpddr4_phy_save_trained_csr(void) +{ + int index, offset, size; + + size = sizeof(phy_trained_csr) / 8; + + dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_wr(0xc0080, 0x3); + + + for (index = 0; index < size; index++) { + offset = phy_trained_csr[index].offset; + phy_trained_csr[index].val = dwc_ddrphy_apb_rd(offset); + } + + dwc_ddrphy_apb_wr(0xc0080, 0x0); + dwc_ddrphy_apb_wr(0xd0000, 0x1); +} + +void lpddr4_phy_cfg(void) +{ + /* load the init config */ + lpddr4_phy_init_cfg(); + + /* restore the trained csr */ + lpddr4_phy_restore_trained_csr(); + + /* load the phy PIE image */ + lpddr4_phy_load_pie(); +} diff --git a/plat/imx/imx8mq/ddr/lpddr4_retention.c b/plat/imx/imx8mq/ddr/lpddr4_retention.c new file mode 100644 index 00000000..f98c079a --- /dev/null +++ b/plat/imx/imx8mq/ddr/lpddr4_retention.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <debug.h> +#include <stdbool.h> +#include <ddrc.h> +#include <mmio.h> +#include <platform_def.h> +#include <spinlock.h> +#include <soc.h> + +#include "lpddr4_dvfs.h" + +#define SRC_IPS_BASE_ADDR 0x30390000 +#define SRC_DDRC_RCR_ADDR (SRC_IPS_BASE_ADDR + 0x1000) + +#define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC) //added by baoxye +#define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800) +#define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000) +#define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * n) +#define CCM_CCGR(n) (CCM_CCGR_OFFSET + 0x10 * n) + +static bool trained_csr_saved = false; + +void ddrc_enter_retention(void) +{ + unsigned int tmp, tmp_t, i; + + /* only need be save once */ + if (!trained_csr_saved) { + lpddr4_phy_save_trained_csr(); + trained_csr_saved = true; + } + + INFO("enter lpddr4_retention\n"); + /* wait DBGCAM to be empty */ + do{ + tmp = mmio_read_32(DDRC_DBGCAM(0)); + } while (tmp != 0x36000000); + + /* Blocks AXI ports from taking anymore transactions */ + mmio_write_32(DDRC_PCTRL_0(0), 0x00000000); + + /* Waits unit all AXI ports are idle */ + do { + tmp = mmio_read_32(DDRC_PSTAT(0)); + } while (tmp & 0x10001); + + /* enters self refresh */ + mmio_write_32(DDRC_PWRCTL(0), 0x000000aa); + + tmp=0; + while (tmp!=0x223) { + tmp = 0x33f & (mmio_read_32((DDRC_STAT(0)))); + } + + mmio_write_32(DDRC_DFIMISC(0), 0x00000000); + + /* set SWCTL.sw_done to disable quasi-dynamic register programming outside reset. */ + mmio_write_32(DDRC_SWCTL(0), 0x00000000); + + mmio_write_32(DDRC_DFIMISC(0), 0x00001f00); + mmio_write_32(DDRC_DFIMISC(0), 0x00001f20); + + /* wait DFISTAT.dfi_init_complete to 0 */ + tmp_t = 0; + while (tmp_t==1) { + tmp = mmio_read_32(DDRC_DFISTAT(0)); + tmp_t = tmp & 0x01; + } + + mmio_write_32(DDRC_DFIMISC(0), 0x00001f00); + + /* wait DFISTAT.dfi_init_complete to 1 */ + tmp_t = 0; + while (tmp_t==0) { + tmp = mmio_read_32(DDRC_DFISTAT(0)); + tmp_t = tmp & 0x01; + } + + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */ + mmio_write_32(DDRC_SWCTL(0), 0x00000001); + + /* should check PhyInLP3 pub reg */ + dwc_ddrphy_apb_wr(0xd0000,0x0); + tmp = dwc_ddrphy_apb_rd(0x90028); + tmp = tmp & 0x1; + if (tmp) + INFO("C: PhyInLP3 = 1\n"); + else + INFO("FAILED\n"); + + dwc_ddrphy_apb_wr(0xd0000,0x1); + + for (i=0; i<20; i++); + + /* pwrdnreqn_async adbm/adbs of ddr */ + mmio_clrbits_32(GPC_PU_PWRHSK, (1 << 1)); + do { + tmp = mmio_read_32(GPC_PU_PWRHSK); + INFO("C: wait pwrdnackn_async clr\n"); + } while (tmp & (0x1<<18));/* wait untill pwrdnackn_async=0 */ + mmio_setbits_32(GPC_PU_PWRHSK, (1 << 1)); + + /* remove PowerOk */ + mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000008); + + for (i=0; i<20; i++); + + mmio_write_32(CCM_CCGR(5),0); + mmio_write_32(CCM_SRC_CTRL(15),2); + + for (i=0; i<20; i++); + + /* enable the phy iso */ + mmio_setbits_32(0x303a0d40, 0x1); + mmio_setbits_32(0x303a0104, (1 << 5)); +} + +void ddrc_exit_retention(void) +{ + volatile unsigned int tmp, tmp_t, i; + INFO("exit lpddr4_retention\n"); + + for (i=0; i<50; i++); + + for (i=0; i<50; i++); + + /* assert all reset */ + /* assert [0]src_system_rst_b! */ + mmio_write_32(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000001); + mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F00000F); + /* release [0]src_system_rst_b! */ + mmio_write_32(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + + mmio_write_32(CCM_CCGR(5),2); + mmio_write_32(CCM_SRC_CTRL(15),2); + INFO("C: enable all DRAM clocks \n"); + + /* change the clock source of dram_apb_clk_root */ + mmio_write_32(0x3038a088, (0x7<<24)|(0x7<<16)); + mmio_write_32(0x3038a084, (0x4<<24)|(0x3<<16)); + + /* disable iso */ + /* mmio_write_32(0x303A00EC,0x0000ffff); //PGC_CPU_MAPPING */ + /* reg32setbit(0x303A00F8,5);//PU_PGC_SW_PUP_REQ */ + mmio_setbits_32(0x303a00f8, (1 << 5)); + + /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ + mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000006); + + lpddr4_cfg_umctl2(); + /* Skips the DRAM init routine and starts up in selfrefresh mode */ + /* Program INIT0.skip_dram_init = 2'b11 */ + mmio_write_32(DDRC_INIT0(0), 0xc0000000 | (mmio_read_32(DDRC_INIT0(0)))); + /* Keeps the controller in self-refresh mode */ + mmio_write_32(DDRC_PWRCTL(0), 0x000000aa); + mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000000); /* release all reset */ + mmio_write_32(DDRC_DBG1(0), 0x00000000); + + /* before write Dynamic reg, sw_done should be 0 */ + mmio_write_32(DDRC_SWCTL(0), 0x00000000); + mmio_write_32(DDRC_DDR_SS_GPR0, 0x01);//LPDDR4 mode + mmio_write_32(DDRC_DFIMISC(0), 0x00000000); + + lpddr4_phy_cfg(); + + dwc_ddrphy_apb_wr(0xd0000,0x0); + do { + tmp_t = dwc_ddrphy_apb_rd(0x20097); + INFO("C: Waiting for CalBusy = 0\n"); + } while(tmp_t != 0); + dwc_ddrphy_apb_wr(0xd0000,0x1); + + /* before write Dynamic reg, sw_done should be 0 */ + mmio_write_32(DDRC_SWCTL(0), 0x00000000); + mmio_write_32(DDRC_DFIMISC(0), 0x00000020); + + /* wait DFISTAT.dfi_init_complete to 1 */ + tmp_t = 0; + while(tmp_t==0){ + tmp = mmio_read_32(DDRC_DFISTAT(0)); + tmp_t = tmp & 0x01; + INFO("wait DFISTAT.dfi_init_complete to 1\n"); + } + + /* clear DFIMISC.dfi_init_start */ + mmio_write_32(DDRC_DFIMISC(0), 0x00000000); + /* set DFIMISC.dfi_init_complete_en */ + mmio_write_32(DDRC_DFIMISC(0), 0x00000001); + /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */ + mmio_write_32(DDRC_SWCTL(0), 0x00000001); + + /* wait SWSTAT.sw_done_ack to 1 */ + tmp_t = 0; + while (tmp_t!=0x1) { + tmp = mmio_read_32(DDRC_SWSTAT(0)); + tmp_t = tmp & 0x1; + INFO("1wait SWSTAT.sw_done_ack to 1\n"); + } + + mmio_write_32(DDRC_PWRCTL(0), 0x000000aa); + mmio_write_32(DDRC_SWCTL(0), 0x00000000); + mmio_write_32(DDRC_DFIMISC(0), 0x00000001); + mmio_write_32(DDRC_SWCTL(0), 0x00000001); + + /* wait SWSTAT.sw_done_ack to 1 */ + tmp_t = 0; + while (tmp_t!=0x1) { + tmp = mmio_read_32(DDRC_SWSTAT(0)); + tmp_t = tmp & 0x1; + INFO("2wait SWSTAT.sw_done_ack to 1\n"); + } + + /* mmio_write_32(DDRC_PWRCTL(0), 0x0000008a); */ + mmio_write_32(DDRC_PWRCTL(0), 0x00000088); + + /* wait STAT to normal state */ + tmp_t = 0; + while(tmp_t!=0x1){ + tmp = mmio_read_32(DDRC_STAT(0)); + tmp_t = tmp & 0x7; + INFO("wait STAT to normal state\n"); + } + + mmio_write_32(DDRC_DERATEEN(0), 0x00000302); + + mmio_write_32(DDRC_PCTRL_0(0), 0x00000001); + /* dis_auto-refresh is set to 0 */ + mmio_write_32(DDRC_RFSHCTL3(0), 0x00000000); + + /* should check PhyInLP3 pub reg */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_rd(0x90028); + tmp = tmp & 0x1; + if(!tmp) + INFO("C: PhyInLP3 = 0\n"); + else + INFO("FAILED\n"); + dwc_ddrphy_apb_wr(0xd0000, 0x1); +} diff --git a/plat/imx/imx8mq/ddr/lpddr4_swffc.c b/plat/imx/imx8mq/ddr/lpddr4_swffc.c new file mode 100644 index 00000000..6db6f4de --- /dev/null +++ b/plat/imx/imx8mq/ddr/lpddr4_swffc.c @@ -0,0 +1,417 @@ +/* + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright 2017-2018 NXP. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <ddrc.h> +#include <debug.h> +#include <mmio.h> + +#include "lpddr4_dvfs.h" + +#define P0_INIT3 0x00D4002D +#define P0_INIT4 0x00310008 +#define P0_INIT6 0x0066004a +#define P0_INIT7 0x0006004a + +#define P1_INIT3 0x0140009 +#define P1_INIT4 0x00310008 +#define P1_INIT6 0x0066004a +#define P1_INIT7 0x0006004a + +#define HW_DRAM_PLL_CFG0_ADDR (0x30360000 + 0x60) +#define HW_DRAM_PLL_CFG1_ADDR (0x30360000 + 0x64) +#define HW_DRAM_PLL_CFG2_ADDR (0x30360000 + 0x68) + +#define DFILP_SPT + +void sscgpll_bypass_enable(unsigned int reg_addr) +{ + unsigned int read_data; + read_data = mmio_read_32(reg_addr); + mmio_write_32(reg_addr, read_data | 0x00000010); + read_data = mmio_read_32(reg_addr); + mmio_write_32(reg_addr, read_data | 0x00000020); +} + +void sscgpll_bypass_disable(unsigned int reg_addr) +{ + unsigned int read_data; + read_data = mmio_read_32(reg_addr); + mmio_write_32(reg_addr, read_data & 0xffffffdf); + read_data = mmio_read_32(reg_addr); + mmio_write_32(reg_addr, read_data & 0xffffffef); +} + +unsigned int wait_pll_lock(unsigned int reg_addr) +{ + unsigned int pll_lock; + pll_lock = mmio_read_32(reg_addr) >> 31; + return pll_lock; +} + +void DDR_PLL_CONFIG_FREQ(unsigned int freq) +{ + unsigned int ddr_pll_lock = 0x0; + sscgpll_bypass_enable(HW_DRAM_PLL_CFG0_ADDR); + switch(freq) + { + case 800: + mmio_write_32(HW_DRAM_PLL_CFG2_ADDR, 0x00ece580); + break; + case 700: + mmio_write_32(HW_DRAM_PLL_CFG2_ADDR, 0x00ec4580); + break; + case 667: + mmio_write_32(HW_DRAM_PLL_CFG2_ADDR, 0x00ece480); + break; + case 400: + mmio_write_32(HW_DRAM_PLL_CFG2_ADDR, 0x00ec6984); + break; + case 167: + mmio_write_32(HW_DRAM_PLL_CFG2_ADDR, 0x00f5a406); + break; + case 100: + mmio_write_32(HW_DRAM_PLL_CFG2_ADDR, 0x015dea96); + break; + + default: + printf("Input freq=%d error.\n",freq); + } + + sscgpll_bypass_disable(HW_DRAM_PLL_CFG0_ADDR); + while (ddr_pll_lock != 0x1) + { + ddr_pll_lock = wait_pll_lock(HW_DRAM_PLL_CFG0_ADDR); + } +} + +void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr, unsigned int mr_data) +{ + unsigned int tmp; + /*1. Poll MRSTAT.mr_wr_busy until it is 0. This checks + * that there is no outstanding MR transaction. No writes + * should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. + */ + do{ + tmp = mmio_read_32(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + /* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank + * and (for MRWs) MRCTRL1.mr_data to define the MR transaction. + */ + mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4)); + mmio_write_32(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); + mmio_setbits_32(DDRC_MRCTRL0(0), (1 << 31)); +} + +void lpddr4_dvfs_swffc(unsigned int init_fsp, unsigned int target_freq) +{ + unsigned int mr, emr, emr2, emr3;//, mr4; + unsigned int mr11, mr12, mr22, mr14; + unsigned int tmp, tmp_t, tmp2, i; + + tf_printf("lpddr4 swffc start\n"); + + /* MR13.FSP-WR=1, MRW to update the MR registers */ + + /* setting for 3200 mts */ + if(target_freq==0) { + mr = P0_INIT3 >> 16; + emr = P0_INIT3 & 0xFFFF; + emr2 = P0_INIT4 >> 16; + emr3 = P0_INIT4 & 0xFFFF; + mr11 = P0_INIT6 >> 16; + mr12 = P0_INIT6 & 0xFFFF; + mr22 = P0_INIT7 >> 16; + mr14 = P0_INIT7 & 0xFFFF; + } else { + /* setting for 667 mts */ + mr = P1_INIT3 >> 16; + emr = P1_INIT3 & 0xFFFF; + emr2 = P1_INIT4 >> 16; + emr3 = P1_INIT4 & 0xFFFF; + mr11 = P1_INIT6 >> 16; + mr12 = P1_INIT6 & 0xFFFF; + mr22 = P1_INIT7 >> 16; + mr14 = P1_INIT7 & 0xFFFF; + } + + tmp = (init_fsp== 1) ? 0x2 <<6 : 0x1 <<6; + emr3 = (emr3 & 0x003f) | tmp | 0x0d00; + + /* set PWRCTL.selfref_en=0 */ + tmp= mmio_read_32(DDRC_PWRCTL(0)); + tmp &= ~0xf; + mmio_write_32(DDRC_PWRCTL(0),tmp); + + lpddr4_mr_write(3, 13, emr3); + lpddr4_mr_write(3, 1, mr); + lpddr4_mr_write(3, 2, emr); + lpddr4_mr_write(3, 3, emr2); + lpddr4_mr_write(3, 11, mr11); + lpddr4_mr_write(3, 12, mr12); + lpddr4_mr_write(3, 14, mr14); + lpddr4_mr_write(3, 22, mr22); + + /* polling mr done */ + do { + tmp = mmio_read_32(DDRC_MRSTAT(0)); + } while(tmp & 0x1); + + /* disable AXI ports */ + mmio_write_32(DDRC_PCTRL_0(0), 0x0); + + /* Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. */ + i=0; + do { + tmp = mmio_read_32(DDRC_PSTAT(0)); + i++; + } while ((tmp != 0) && (i < 100)); + + /* Disable phy master */ + mmio_write_32(DDRC_DFIPHYMSTR(0),0x00000000); + + +#ifdef DFILP_SPT + /* 8. disable DFI LP */ + /* DFILPCFG0.dfi_lp_en_sr */ + tmp = mmio_read_32(DDRC_DFILPCFG0(0)); + if (tmp & 0x100) { + tmp &= 0x0; + mmio_write_32(DDRC_DFILPCFG0(0),tmp); + do { + tmp = mmio_read_32(DDRC_DFISTAT(0)); /* dfi_lp_ack */ + tmp2= mmio_read_32(DDRC_STAT(0)); /* operating_mode */ + } while (((tmp & 0x2) == 0x2) && ((tmp2 & 0x7) == 3)); + } +#endif + + /* 9. wait until in normal or power down states */ + do { + tmp= mmio_read_32(DDRC_STAT(0)); /* operating_mode */ + } while (((tmp & 0x7) != 1) && ((tmp & 0x7) != 2)); + + /* 10. Disable automatic derating: derate_enable */ + tmp= mmio_read_32(DDRC_DERATEEN(0)); + tmp &= ~0x1; + mmio_write_32(DDRC_DERATEEN(0), tmp); /* ddrc_derate_enable, bit 0 */ + + tmp= mmio_read_32(DDRC_FREQ1_DERATEEN(0)); + tmp &= ~0x1; + mmio_write_32(DDRC_FREQ1_DERATEEN(0), tmp); /* ddrc_derate_enable, bit 0 */ + tmp= mmio_read_32(DDRC_ZQCTL0(0)); + tmp |= 0x80000000; + mmio_write_32(DDRC_ZQCTL0(0), tmp); /* ddrc_derate_enable, bit 0 */ + tmp= mmio_read_32(DDRC_FREQ1_ZQCTL0(0)); + tmp |= 0x80000000; + mmio_write_32(DDRC_FREQ1_ZQCTL0(0), tmp); /* ddrc_derate_enable, bit 0 */ + + /* 12. set PWRCTL.selfref_en=0 */ + tmp= mmio_read_32(DDRC_PWRCTL(0)); + tmp &= ~0x1; + mmio_write_32(DDRC_PWRCTL(0),tmp); + + /* 13.Poll STAT.operating_mode is in "Normal" (001) or "Power-down" (010) */ + do { + tmp= mmio_read_32(DDRC_STAT(0)); /* operating_mode */ + } while (((tmp & 0x7) != 1) && ((tmp & 0x7) != 2)); + + /* 14/15. trigger SW SR */ + tmp= mmio_read_32(DDRC_PWRCTL(0)); + tmp |= 0x60; + mmio_write_32(DDRC_PWRCTL(0),tmp); + + /* 16. Poll STAT.selfref_state in "Self Refresh 1" */ + do { + tmp= mmio_read_32(DDRC_STAT(0)); // operating_mode + } while ((tmp & 0x300) != 0x100); + + /* 17. disable dq */ + tmp= mmio_read_32(DDRC_DBG1(0)); + tmp |= 0x1; + mmio_write_32(DDRC_DBG1(0), tmp); + + /* 18. Poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty */ + do { + tmp = mmio_read_32(DDRC_DBGCAM(0)); + tmp_t = tmp & 0x30000000; + } while(tmp_t!=0x30000000); + + /* 19. change MR13.FSP-OP to new FSP and MR13.VRCG to high current */ + emr3 = (((~init_fsp) & 0x1) << 7) | (0x1 << 3) | (emr3 & 0x0077) | 0x0d00; + lpddr4_mr_write(3, 13, emr3); + + /* 20. enter SR Power Down */ + tmp= mmio_read_32(DDRC_PWRCTL(0)); + tmp &= ~0x60; + tmp |= 0x20; + mmio_write_32(DDRC_PWRCTL(0),tmp); + + /* 21. Poll STAT.selfref_state is in "SR Power down" */ + do { + tmp= mmio_read_32(DDRC_STAT(0)); + } while ((tmp & 0x300) != 0x200); + + /* 22. set dfi_init_complete_en = 0 */ + /* 23. switch clock */ + /* set SWCTL.dw_done to 0 */ + mmio_write_32(DDRC_SWCTL(0), 0x0000); + + /* 24. program frequency mode=1(bit 29), target_frequency=target_freq (bit 29) */ + + mmio_write_32(DDRC_MSTR2(0),target_freq); + + /* 25. DBICTL for FSP-OP[1], skip it if never enable it */ + + /* 26.trigger initialization in the PHY */ + + /* Q3: if refresh level is updated, then should program */ + tmp= mmio_read_32(DDRC_RFSHCTL3(0)); + tmp = tmp ^ 0x2; + mmio_write_32(DDRC_RFSHCTL3(0),tmp); + + /* Q4: only for legacy PHY, so here can skipped */ + tmp= mmio_read_32(DDRC_DFIMISC(0)); + tmp &= 0xFF; + tmp |= (target_freq << 8); /* should be 0 */ + mmio_write_32(DDRC_DFIMISC(0),tmp); + tmp |= 0x20; + mmio_write_32(DDRC_DFIMISC(0),tmp); + + /* polling dfi_init_complete de-assert */ + do { + tmp = mmio_read_32(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x1); + + /* switch_clocks for target frequency */ + if(target_freq==0x1) { + /* mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); */ + mmio_write_32(0x3038a088, (0x7 << 24) | (0x7 << 16)); + /* mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x4<<16)); */ + mmio_write_32(0x3038a084, (0x4 << 24) | (0x4 << 16)); //to source 4 --800MHz/5 + DDR_PLL_CONFIG_FREQ(167); + } else { + DDR_PLL_CONFIG_FREQ(800); + /* mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16)); */ + mmio_write_32(0x3038a088, (0x7 << 24) | (0x7 << 16)); + /* mmio_write_32(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16)); */ + mmio_write_32(0x3038a084, (0x4 << 24) | (0x3 << 16)); //to source 4 --800MHz/4*/ + } + + /* dfi_init_start de-assert */ + tmp= mmio_read_32(DDRC_DFIMISC(0)); + tmp &= ~0x20; + mmio_write_32(DDRC_DFIMISC(0),tmp); + + /* polling dfi_init_complete re-assert */ + do { + tmp = mmio_read_32(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* 27. set ZQCTL0.dis_srx_zqcl = 1 */ + if (target_freq ==0) { + tmp = mmio_read_32(DDRC_ZQCTL0(0)); + tmp |= 0x40000000; + mmio_write_32(DDRC_ZQCTL0(0), tmp); + } else { + tmp = mmio_read_32(DDRC_FREQ1_ZQCTL0(0)); + tmp |= 0x40000000; + mmio_write_32(DDRC_FREQ1_ZQCTL0(0), tmp); + } + + /* 28,29. exit "self refresh power down" to stay "self refresh 2" */ + tmp= mmio_read_32(DDRC_PWRCTL(0)); + tmp &= ~(0x60); + tmp |= 0x40; + mmio_write_32(DDRC_PWRCTL(0),tmp); + /* 30. Poll STAT.selfref_state in "Self refresh 2" */ + do { + tmp= mmio_read_32(DDRC_STAT(0)); // operating_mode + } while ((tmp & 0x300)!=0x300); + + /* 31. change MR13.VRCG to normal */ + emr3 = (emr3 & 0x00f7) | 0x0d00; + lpddr4_mr_write(3, 13, emr3); + + /* enable PHY master */ + mmio_write_32(DDRC_DFIPHYMSTR(0), 0x1); + + /* 32. issue ZQ if required: zq_calib_short, bit 4 */ + /* polling zq_calib_short_busy */ + tmp= mmio_read_32(DDRC_DBGCMD(0)); + tmp |= 0x10; + mmio_write_32(DDRC_DBGCMD(0),tmp); + do { + tmp= mmio_read_32(DDRC_DBGSTAT(0)); + } while ((tmp & 0x10 ) != 0x0); + + /* 33. Reset ZQCTL0.dis_srx_zqcl=0 */ + if (target_freq > 0) { + tmp = mmio_read_32(DDRC_FREQ1_ZQCTL0(0)); + tmp &= ~0x40000000; + mmio_write_32(DDRC_FREQ1_ZQCTL0(0), tmp); + } else { + tmp = mmio_read_32(DDRC_ZQCTL0(0)); + tmp &= ~0x40000000; + mmio_write_32(DDRC_ZQCTL0(0), tmp); + } + + /* set SWCTL.dw_done to 1 and poll SWSTAT.sw_done_ack=1 */ + mmio_write_32(DDRC_SWCTL(0), 0x0001); + + /* wait SWSTAT.sw_done_ack to 1 */ + tmp_t = 0; + while(tmp_t==0) { + tmp = mmio_read_32(DDRC_SWSTAT(0)); + tmp_t = tmp & 0x01; + } + + /* 34. set PWRCTL.stay_in_selfreh=0, exit SR */ + tmp= mmio_read_32(DDRC_PWRCTL(0)); + tmp &= ~(0x40); + mmio_write_32(DDRC_PWRCTL(0),tmp); + + /* 35. Poll STAT.selfref_state in "Idle" */ + do { + tmp= mmio_read_32(DDRC_STAT(0)); // operating_mode + } while ((tmp & 0x300)!=0x0); + +#ifdef DFILP_SPT + /* 36. restore dfi_lp.dfi_lp_en_sr */ + tmp = mmio_read_32(DDRC_DFILPCFG0(0)); + tmp |= 0x100; + mmio_write_32(DDRC_DFILPCFG0(0),tmp); +#endif + + /* 37. re-enable CAM: dis_dq */ + tmp= mmio_read_32(DDRC_DBG1(0)); + tmp &= 0xFFFFFFFE; + mmio_write_32(DDRC_DBG1(0), tmp); + + /* 38. re-enable automatic SR: selfref_en */ + tmp= mmio_read_32(DDRC_PWRCTL(0)); + tmp |= 0x1; + mmio_write_32(DDRC_PWRCTL(0), tmp); + + /* 39. re-enable automatic ZQ: dis_auto_zq=0 */ + /* disable automatic ZQ calibration */ + if (target_freq == 1) { + tmp = mmio_read_32(DDRC_FREQ1_ZQCTL0(0)); + tmp &= ~0x80000000; + mmio_write_32(DDRC_FREQ1_ZQCTL0(0), tmp); + } else { + tmp = mmio_read_32(DDRC_ZQCTL0(0)); + tmp &= ~0x80000000; + mmio_write_32(DDRC_ZQCTL0(0), tmp); + } + + /* 40. re-emable automatic derating: derate_enable */ + tmp= mmio_read_32(DDRC_DERATEEN(0)); + tmp &= 0xFFFFFFFE; + mmio_write_32(DDRC_DERATEEN(0), tmp); + + /* 41. write 1 to PCTRL.port_en */ + mmio_write_32(DDRC_PCTRL_0(0), 0x1); +} diff --git a/plat/imx/imx8mq/ddrc.c b/plat/imx/imx8mq/ddrc.c deleted file mode 100644 index ec8cc07d..00000000 --- a/plat/imx/imx8mq/ddrc.c +++ /dev/null @@ -1,2989 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * Copyright 2017 NXP - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch.h> -#include <arch_helpers.h> -#include <debug.h> -#include <ddrc.h> -#include <mmio.h> -#include <platform_def.h> -#include <spinlock.h> -#include <soc.h> - -struct ddrphy_trained_csr { - uint32_t offset; - uint32_t val; -}; -static struct ddrphy_trained_csr lpddr4_saved_trained_csr[] = { - { .offset = 0x200b2, .val = 0 }, - { .offset = 0x1200b2, .val = 0 }, - { .offset = 0x2200b2, .val = 0 }, - { .offset = 0x3200b2, .val = 0 }, - { .offset = 0x200cb, .val = 0 }, - { .offset = 0x1004a, .val = 0 }, - { .offset = 0x1004c, .val = 0 }, - { .offset = 0x11004c, .val = 0 }, - { .offset = 0x21004c, .val = 0 }, - { .offset = 0x31004c, .val = 0 }, - { .offset = 0x10043, .val = 0 }, - { .offset = 0x110043, .val = 0 }, - { .offset = 0x210043, .val = 0 }, - { .offset = 0x310043, .val = 0 }, - { .offset = 0x10143, .val = 0 }, - { .offset = 0x110143, .val = 0 }, - { .offset = 0x210143, .val = 0 }, - { .offset = 0x310143, .val = 0 }, - { .offset = 0x1104a, .val = 0 }, - { .offset = 0x1104c, .val = 0 }, - { .offset = 0x11104c, .val = 0 }, - { .offset = 0x21104c, .val = 0 }, - { .offset = 0x31104c, .val = 0 }, - { .offset = 0x11043, .val = 0 }, - { .offset = 0x111043, .val = 0 }, - { .offset = 0x211043, .val = 0 }, - { .offset = 0x311043, .val = 0 }, - { .offset = 0x11143, .val = 0 }, - { .offset = 0x111143, .val = 0 }, - { .offset = 0x211143, .val = 0 }, - { .offset = 0x311143, .val = 0 }, - { .offset = 0x1204a, .val = 0 }, - { .offset = 0x1204c, .val = 0 }, - { .offset = 0x11204c, .val = 0 }, - { .offset = 0x21204c, .val = 0 }, - { .offset = 0x31204c, .val = 0 }, - { .offset = 0x12043, .val = 0 }, - { .offset = 0x112043, .val = 0 }, - { .offset = 0x212043, .val = 0 }, - { .offset = 0x312043, .val = 0 }, - { .offset = 0x12143, .val = 0 }, - { .offset = 0x112143, .val = 0 }, - { .offset = 0x212143, .val = 0 }, - { .offset = 0x312143, .val = 0 }, - { .offset = 0x1304a, .val = 0 }, - { .offset = 0x1304c, .val = 0 }, - { .offset = 0x11304c, .val = 0 }, - { .offset = 0x21304c, .val = 0 }, - { .offset = 0x31304c, .val = 0 }, - { .offset = 0x13043, .val = 0 }, - { .offset = 0x113043, .val = 0 }, - { .offset = 0x213043, .val = 0 }, - { .offset = 0x313043, .val = 0 }, - { .offset = 0x13143, .val = 0 }, - { .offset = 0x113143, .val = 0 }, - { .offset = 0x213143, .val = 0 }, - { .offset = 0x313143, .val = 0 }, - { .offset = 0x80, .val = 0 }, - { .offset = 0x100080, .val = 0 }, - { .offset = 0x200080, .val = 0 }, - { .offset = 0x300080, .val = 0 }, - { .offset = 0x1080, .val = 0 }, - { .offset = 0x101080, .val = 0 }, - { .offset = 0x201080, .val = 0 }, - { .offset = 0x301080, .val = 0 }, - { .offset = 0x2080, .val = 0 }, - { .offset = 0x102080, .val = 0 }, - { .offset = 0x202080, .val = 0 }, - { .offset = 0x302080, .val = 0 }, - { .offset = 0x3080, .val = 0 }, - { .offset = 0x103080, .val = 0 }, - { .offset = 0x203080, .val = 0 }, - { .offset = 0x303080, .val = 0 }, - { .offset = 0x4080, .val = 0 }, - { .offset = 0x104080, .val = 0 }, - { .offset = 0x204080, .val = 0 }, - { .offset = 0x304080, .val = 0 }, - { .offset = 0x5080, .val = 0 }, - { .offset = 0x105080, .val = 0 }, - { .offset = 0x205080, .val = 0 }, - { .offset = 0x305080, .val = 0 }, - { .offset = 0x6080, .val = 0 }, - { .offset = 0x106080, .val = 0 }, - { .offset = 0x206080, .val = 0 }, - { .offset = 0x306080, .val = 0 }, - { .offset = 0x7080, .val = 0 }, - { .offset = 0x107080, .val = 0 }, - { .offset = 0x207080, .val = 0 }, - { .offset = 0x307080, .val = 0 }, - { .offset = 0x8080, .val = 0 }, - { .offset = 0x108080, .val = 0 }, - { .offset = 0x208080, .val = 0 }, - { .offset = 0x308080, .val = 0 }, - { .offset = 0x9080, .val = 0 }, - { .offset = 0x109080, .val = 0 }, - { .offset = 0x209080, .val = 0 }, - { .offset = 0x309080, .val = 0 }, - { .offset = 0x10080, .val = 0 }, - { .offset = 0x110080, .val = 0 }, - { .offset = 0x210080, .val = 0 }, - { .offset = 0x310080, .val = 0 }, - { .offset = 0x10180, .val = 0 }, - { .offset = 0x110180, .val = 0 }, - { .offset = 0x210180, .val = 0 }, - { .offset = 0x310180, .val = 0 }, - { .offset = 0x10081, .val = 0 }, - { .offset = 0x110081, .val = 0 }, - { .offset = 0x210081, .val = 0 }, - { .offset = 0x310081, .val = 0 }, - { .offset = 0x10181, .val = 0 }, - { .offset = 0x110181, .val = 0 }, - { .offset = 0x210181, .val = 0 }, - { .offset = 0x310181, .val = 0 }, - { .offset = 0x10082, .val = 0 }, - { .offset = 0x110082, .val = 0 }, - { .offset = 0x210082, .val = 0 }, - { .offset = 0x310082, .val = 0 }, - { .offset = 0x10182, .val = 0 }, - { .offset = 0x110182, .val = 0 }, - { .offset = 0x210182, .val = 0 }, - { .offset = 0x310182, .val = 0 }, - { .offset = 0x10083, .val = 0 }, - { .offset = 0x110083, .val = 0 }, - { .offset = 0x210083, .val = 0 }, - { .offset = 0x310083, .val = 0 }, - { .offset = 0x10183, .val = 0 }, - { .offset = 0x110183, .val = 0 }, - { .offset = 0x210183, .val = 0 }, - { .offset = 0x310183, .val = 0 }, - { .offset = 0x11080, .val = 0 }, - { .offset = 0x111080, .val = 0 }, - { .offset = 0x211080, .val = 0 }, - { .offset = 0x311080, .val = 0 }, - { .offset = 0x11180, .val = 0 }, - { .offset = 0x111180, .val = 0 }, - { .offset = 0x211180, .val = 0 }, - { .offset = 0x311180, .val = 0 }, - { .offset = 0x11081, .val = 0 }, - { .offset = 0x111081, .val = 0 }, - { .offset = 0x211081, .val = 0 }, - { .offset = 0x311081, .val = 0 }, - { .offset = 0x11181, .val = 0 }, - { .offset = 0x111181, .val = 0 }, - { .offset = 0x211181, .val = 0 }, - { .offset = 0x311181, .val = 0 }, - { .offset = 0x11082, .val = 0 }, - { .offset = 0x111082, .val = 0 }, - { .offset = 0x211082, .val = 0 }, - { .offset = 0x311082, .val = 0 }, - { .offset = 0x11182, .val = 0 }, - { .offset = 0x111182, .val = 0 }, - { .offset = 0x211182, .val = 0 }, - { .offset = 0x311182, .val = 0 }, - { .offset = 0x11083, .val = 0 }, - { .offset = 0x111083, .val = 0 }, - { .offset = 0x211083, .val = 0 }, - { .offset = 0x311083, .val = 0 }, - { .offset = 0x11183, .val = 0 }, - { .offset = 0x111183, .val = 0 }, - { .offset = 0x211183, .val = 0 }, - { .offset = 0x311183, .val = 0 }, - { .offset = 0x12080, .val = 0 }, - { .offset = 0x112080, .val = 0 }, - { .offset = 0x212080, .val = 0 }, - { .offset = 0x312080, .val = 0 }, - { .offset = 0x12180, .val = 0 }, - { .offset = 0x112180, .val = 0 }, - { .offset = 0x212180, .val = 0 }, - { .offset = 0x312180, .val = 0 }, - { .offset = 0x12081, .val = 0 }, - { .offset = 0x112081, .val = 0 }, - { .offset = 0x212081, .val = 0 }, - { .offset = 0x312081, .val = 0 }, - { .offset = 0x12181, .val = 0 }, - { .offset = 0x112181, .val = 0 }, - { .offset = 0x212181, .val = 0 }, - { .offset = 0x312181, .val = 0 }, - { .offset = 0x12082, .val = 0 }, - { .offset = 0x112082, .val = 0 }, - { .offset = 0x212082, .val = 0 }, - { .offset = 0x312082, .val = 0 }, - { .offset = 0x12182, .val = 0 }, - { .offset = 0x112182, .val = 0 }, - { .offset = 0x212182, .val = 0 }, - { .offset = 0x312182, .val = 0 }, - { .offset = 0x12083, .val = 0 }, - { .offset = 0x112083, .val = 0 }, - { .offset = 0x212083, .val = 0 }, - { .offset = 0x312083, .val = 0 }, - { .offset = 0x12183, .val = 0 }, - { .offset = 0x112183, .val = 0 }, - { .offset = 0x212183, .val = 0 }, - { .offset = 0x312183, .val = 0 }, - { .offset = 0x13080, .val = 0 }, - { .offset = 0x113080, .val = 0 }, - { .offset = 0x213080, .val = 0 }, - { .offset = 0x313080, .val = 0 }, - { .offset = 0x13180, .val = 0 }, - { .offset = 0x113180, .val = 0 }, - { .offset = 0x213180, .val = 0 }, - { .offset = 0x313180, .val = 0 }, - { .offset = 0x13081, .val = 0 }, - { .offset = 0x113081, .val = 0 }, - { .offset = 0x213081, .val = 0 }, - { .offset = 0x313081, .val = 0 }, - { .offset = 0x13181, .val = 0 }, - { .offset = 0x113181, .val = 0 }, - { .offset = 0x213181, .val = 0 }, - { .offset = 0x313181, .val = 0 }, - { .offset = 0x13082, .val = 0 }, - { .offset = 0x113082, .val = 0 }, - { .offset = 0x213082, .val = 0 }, - { .offset = 0x313082, .val = 0 }, - { .offset = 0x13182, .val = 0 }, - { .offset = 0x113182, .val = 0 }, - { .offset = 0x213182, .val = 0 }, - { .offset = 0x313182, .val = 0 }, - { .offset = 0x13083, .val = 0 }, - { .offset = 0x113083, .val = 0 }, - { .offset = 0x213083, .val = 0 }, - { .offset = 0x313083, .val = 0 }, - { .offset = 0x13183, .val = 0 }, - { .offset = 0x113183, .val = 0 }, - { .offset = 0x213183, .val = 0 }, - { .offset = 0x313183, .val = 0 }, - { .offset = 0x100d0, .val = 0 }, - { .offset = 0x1100d0, .val = 0 }, - { .offset = 0x2100d0, .val = 0 }, - { .offset = 0x3100d0, .val = 0 }, - { .offset = 0x101d0, .val = 0 }, - { .offset = 0x1101d0, .val = 0 }, - { .offset = 0x2101d0, .val = 0 }, - { .offset = 0x3101d0, .val = 0 }, - { .offset = 0x100d1, .val = 0 }, - { .offset = 0x1100d1, .val = 0 }, - { .offset = 0x2100d1, .val = 0 }, - { .offset = 0x3100d1, .val = 0 }, - { .offset = 0x101d1, .val = 0 }, - { .offset = 0x1101d1, .val = 0 }, - { .offset = 0x2101d1, .val = 0 }, - { .offset = 0x3101d1, .val = 0 }, - { .offset = 0x100d2, .val = 0 }, - { .offset = 0x1100d2, .val = 0 }, - { .offset = 0x2100d2, .val = 0 }, - { .offset = 0x3100d2, .val = 0 }, - { .offset = 0x101d2, .val = 0 }, - { .offset = 0x1101d2, .val = 0 }, - { .offset = 0x2101d2, .val = 0 }, - { .offset = 0x3101d2, .val = 0 }, - { .offset = 0x100d3, .val = 0 }, - { .offset = 0x1100d3, .val = 0 }, - { .offset = 0x2100d3, .val = 0 }, - { .offset = 0x3100d3, .val = 0 }, - { .offset = 0x101d3, .val = 0 }, - { .offset = 0x1101d3, .val = 0 }, - { .offset = 0x2101d3, .val = 0 }, - { .offset = 0x3101d3, .val = 0 }, - { .offset = 0x110d0, .val = 0 }, - { .offset = 0x1110d0, .val = 0 }, - { .offset = 0x2110d0, .val = 0 }, - { .offset = 0x3110d0, .val = 0 }, - { .offset = 0x111d0, .val = 0 }, - { .offset = 0x1111d0, .val = 0 }, - { .offset = 0x2111d0, .val = 0 }, - { .offset = 0x3111d0, .val = 0 }, - { .offset = 0x110d1, .val = 0 }, - { .offset = 0x1110d1, .val = 0 }, - { .offset = 0x2110d1, .val = 0 }, - { .offset = 0x3110d1, .val = 0 }, - { .offset = 0x111d1, .val = 0 }, - { .offset = 0x1111d1, .val = 0 }, - { .offset = 0x2111d1, .val = 0 }, - { .offset = 0x3111d1, .val = 0 }, - { .offset = 0x110d2, .val = 0 }, - { .offset = 0x1110d2, .val = 0 }, - { .offset = 0x2110d2, .val = 0 }, - { .offset = 0x3110d2, .val = 0 }, - { .offset = 0x111d2, .val = 0 }, - { .offset = 0x1111d2, .val = 0 }, - { .offset = 0x2111d2, .val = 0 }, - { .offset = 0x3111d2, .val = 0 }, - { .offset = 0x110d3, .val = 0 }, - { .offset = 0x1110d3, .val = 0 }, - { .offset = 0x2110d3, .val = 0 }, - { .offset = 0x3110d3, .val = 0 }, - { .offset = 0x111d3, .val = 0 }, - { .offset = 0x1111d3, .val = 0 }, - { .offset = 0x2111d3, .val = 0 }, - { .offset = 0x3111d3, .val = 0 }, - { .offset = 0x120d0, .val = 0 }, - { .offset = 0x1120d0, .val = 0 }, - { .offset = 0x2120d0, .val = 0 }, - { .offset = 0x3120d0, .val = 0 }, - { .offset = 0x121d0, .val = 0 }, - { .offset = 0x1121d0, .val = 0 }, - { .offset = 0x2121d0, .val = 0 }, - { .offset = 0x3121d0, .val = 0 }, - { .offset = 0x120d1, .val = 0 }, - { .offset = 0x1120d1, .val = 0 }, - { .offset = 0x2120d1, .val = 0 }, - { .offset = 0x3120d1, .val = 0 }, - { .offset = 0x121d1, .val = 0 }, - { .offset = 0x1121d1, .val = 0 }, - { .offset = 0x2121d1, .val = 0 }, - { .offset = 0x3121d1, .val = 0 }, - { .offset = 0x120d2, .val = 0 }, - { .offset = 0x1120d2, .val = 0 }, - { .offset = 0x2120d2, .val = 0 }, - { .offset = 0x3120d2, .val = 0 }, - { .offset = 0x121d2, .val = 0 }, - { .offset = 0x1121d2, .val = 0 }, - { .offset = 0x2121d2, .val = 0 }, - { .offset = 0x3121d2, .val = 0 }, - { .offset = 0x120d3, .val = 0 }, - { .offset = 0x1120d3, .val = 0 }, - { .offset = 0x2120d3, .val = 0 }, - { .offset = 0x3120d3, .val = 0 }, - { .offset = 0x121d3, .val = 0 }, - { .offset = 0x1121d3, .val = 0 }, - { .offset = 0x2121d3, .val = 0 }, - { .offset = 0x3121d3, .val = 0 }, - { .offset = 0x130d0, .val = 0 }, - { .offset = 0x1130d0, .val = 0 }, - { .offset = 0x2130d0, .val = 0 }, - { .offset = 0x3130d0, .val = 0 }, - { .offset = 0x131d0, .val = 0 }, - { .offset = 0x1131d0, .val = 0 }, - { .offset = 0x2131d0, .val = 0 }, - { .offset = 0x3131d0, .val = 0 }, - { .offset = 0x130d1, .val = 0 }, - { .offset = 0x1130d1, .val = 0 }, - { .offset = 0x2130d1, .val = 0 }, - { .offset = 0x3130d1, .val = 0 }, - { .offset = 0x131d1, .val = 0 }, - { .offset = 0x1131d1, .val = 0 }, - { .offset = 0x2131d1, .val = 0 }, - { .offset = 0x3131d1, .val = 0 }, - { .offset = 0x130d2, .val = 0 }, - { .offset = 0x1130d2, .val = 0 }, - { .offset = 0x2130d2, .val = 0 }, - { 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.val = 0 }, - { .offset = 0x2138c1, .val = 0 }, - { .offset = 0x3138c1, .val = 0 }, - { .offset = 0x130c2, .val = 0 }, - { .offset = 0x1130c2, .val = 0 }, - { .offset = 0x2130c2, .val = 0 }, - { .offset = 0x3130c2, .val = 0 }, - { .offset = 0x131c2, .val = 0 }, - { .offset = 0x1131c2, .val = 0 }, - { .offset = 0x2131c2, .val = 0 }, - { .offset = 0x3131c2, .val = 0 }, - { .offset = 0x132c2, .val = 0 }, - { .offset = 0x1132c2, .val = 0 }, - { .offset = 0x2132c2, .val = 0 }, - { .offset = 0x3132c2, .val = 0 }, - { .offset = 0x133c2, .val = 0 }, - { .offset = 0x1133c2, .val = 0 }, - { .offset = 0x2133c2, .val = 0 }, - { .offset = 0x3133c2, .val = 0 }, - { .offset = 0x134c2, .val = 0 }, - { .offset = 0x1134c2, .val = 0 }, - { .offset = 0x2134c2, .val = 0 }, - { .offset = 0x3134c2, .val = 0 }, - { .offset = 0x135c2, .val = 0 }, - { .offset = 0x1135c2, .val = 0 }, - { .offset = 0x2135c2, .val = 0 }, - { .offset = 0x3135c2, .val = 0 }, - { .offset = 0x136c2, .val = 0 }, - { .offset = 0x1136c2, .val = 0 }, - { .offset = 0x2136c2, .val = 0 }, - { .offset = 0x3136c2, .val = 0 }, - { .offset = 0x137c2, .val = 0 }, - { .offset = 0x1137c2, .val = 0 }, - { .offset = 0x2137c2, .val = 0 }, - { .offset = 0x3137c2, .val = 0 }, - { .offset = 0x138c2, .val = 0 }, - { .offset = 0x1138c2, .val = 0 }, - { .offset = 0x2138c2, .val = 0 }, - { .offset = 0x3138c2, .val = 0 }, - { .offset = 0x130c3, .val = 0 }, - { .offset = 0x1130c3, .val = 0 }, - { .offset = 0x2130c3, .val = 0 }, - { .offset = 0x3130c3, .val = 0 }, - { .offset = 0x131c3, .val = 0 }, - { .offset = 0x1131c3, .val = 0 }, - { .offset = 0x2131c3, .val = 0 }, - { .offset = 0x3131c3, .val = 0 }, - { .offset = 0x132c3, .val = 0 }, - { .offset = 0x1132c3, .val = 0 }, - { .offset = 0x2132c3, .val = 0 }, - { .offset = 0x3132c3, .val = 0 }, - { .offset = 0x133c3, .val = 0 }, - { .offset = 0x1133c3, .val = 0 }, - { .offset = 0x2133c3, .val = 0 }, - { .offset = 0x3133c3, .val = 0 }, - { .offset = 0x134c3, .val = 0 }, - { .offset = 0x1134c3, .val = 0 }, - { .offset = 0x2134c3, .val = 0 }, - { .offset = 0x3134c3, .val = 0 }, - { .offset = 0x135c3, .val = 0 }, - { .offset = 0x1135c3, .val = 0 }, - { .offset = 0x2135c3, .val = 0 }, - { .offset = 0x3135c3, .val = 0 }, - { .offset = 0x136c3, .val = 0 }, - { .offset = 0x1136c3, .val = 0 }, - { .offset = 0x2136c3, .val = 0 }, - { .offset = 0x3136c3, .val = 0 }, - { .offset = 0x137c3, .val = 0 }, - { .offset = 0x1137c3, .val = 0 }, - { .offset = 0x2137c3, .val = 0 }, - { .offset = 0x3137c3, .val = 0 }, - { .offset = 0x138c3, .val = 0 }, - { .offset = 0x1138c3, .val = 0 }, - { .offset = 0x2138c3, .val = 0 }, - { .offset = 0x3138c3, .val = 0 }, - { .offset = 0x10020, .val = 0 }, - { .offset = 0x110020, .val = 0 }, - { .offset = 0x210020, .val = 0 }, - { .offset = 0x310020, .val = 0 }, - { .offset = 0x11020, .val = 0 }, - { .offset = 0x111020, .val = 0 }, - { .offset = 0x211020, .val = 0 }, - { .offset = 0x311020, .val = 0 }, - { .offset = 0x12020, .val = 0 }, - { .offset = 0x112020, .val = 0 }, - { .offset = 0x212020, .val = 0 }, - { .offset = 0x312020, .val = 0 }, - { .offset = 0x13020, .val = 0 }, - { .offset = 0x113020, .val = 0 }, - { .offset = 0x213020, .val = 0 }, - { .offset = 0x313020, .val = 0 }, - { .offset = 0x20072, .val = 0 }, - { .offset = 0x20073, .val = 0 }, - { .offset = 0x20074, .val = 0 }, - { .offset = 0x100aa, .val = 0 }, - { .offset = 0x110aa, .val = 0 }, - { .offset = 0x120aa, .val = 0 }, - { .offset = 0x130aa, .val = 0 }, - { .offset = 0x100ae, .val = 0 }, - { .offset = 0x1100ae, .val = 0 }, - { .offset = 0x2100ae, .val = 0 }, - { .offset = 0x3100ae, .val = 0 }, - { .offset = 0x100af, .val = 0 }, - { .offset = 0x1100af, .val = 0 }, - { .offset = 0x2100af, .val = 0 }, - { .offset = 0x3100af, .val = 0 }, - { .offset = 0x110ae, .val = 0 }, - { .offset = 0x1110ae, .val = 0 }, - { .offset = 0x2110ae, .val = 0 }, - { .offset = 0x3110ae, .val = 0 }, - { .offset = 0x110af, .val = 0 }, - { .offset = 0x1110af, .val = 0 }, - { .offset = 0x2110af, .val = 0 }, - { .offset = 0x3110af, .val = 0 }, - { .offset = 0x120ae, .val = 0 }, - { .offset = 0x1120ae, .val = 0 }, - { .offset = 0x2120ae, .val = 0 }, - { .offset = 0x3120ae, .val = 0 }, - { .offset = 0x120af, .val = 0 }, - { .offset = 0x1120af, .val = 0 }, - { .offset = 0x2120af, .val = 0 }, - { .offset = 0x3120af, .val = 0 }, - { .offset = 0x130ae, .val = 0 }, - { .offset = 0x1130ae, .val = 0 }, - { .offset = 0x2130ae, .val = 0 }, - { .offset = 0x3130ae, .val = 0 }, - { .offset = 0x130af, .val = 0 }, - { .offset = 0x1130af, .val = 0 }, - { .offset = 0x2130af, .val = 0 }, - { .offset = 0x3130af, .val = 0 }, - { .offset = 0x20020, .val = 0 }, - { .offset = 0x120020, .val = 0 }, - { .offset = 0x220020, .val = 0 }, - { .offset = 0x320020, .val = 0 }, - { .offset = 0x100a0, .val = 0 }, - { .offset = 0x100a1, .val = 0 }, - { .offset = 0x100a2, .val = 0 }, - { .offset = 0x100a3, .val = 0 }, - { .offset = 0x100a4, .val = 0 }, - { .offset = 0x100a5, .val = 0 }, - { .offset = 0x100a6, .val = 0 }, - { .offset = 0x100a7, .val = 0 }, - { .offset = 0x110a0, .val = 0 }, - { .offset = 0x110a1, .val = 0 }, - { .offset = 0x110a2, .val = 0 }, - { .offset = 0x110a3, .val = 0 }, - { .offset = 0x110a4, .val = 0 }, - { .offset = 0x110a5, .val = 0 }, - { .offset = 0x110a6, .val = 0 }, - { .offset = 0x110a7, .val = 0 }, - { .offset = 0x120a0, .val = 0 }, - { .offset = 0x120a1, .val = 0 }, - { .offset = 0x120a2, .val = 0 }, - { .offset = 0x120a3, .val = 0 }, - { .offset = 0x120a4, .val = 0 }, - { .offset = 0x120a5, .val = 0 }, - { .offset = 0x120a6, .val = 0 }, - { .offset = 0x120a7, .val = 0 }, - { .offset = 0x130a0, .val = 0 }, - { .offset = 0x130a1, .val = 0 }, - { .offset = 0x130a2, .val = 0 }, - { .offset = 0x130a3, .val = 0 }, - { .offset = 0x130a4, .val = 0 }, - { .offset = 0x130a5, .val = 0 }, - { .offset = 0x130a6, .val = 0 }, - { .offset = 0x130a7, .val = 0 }, - { .offset = 0x2007c, .val = 0 }, - { .offset = 0x12007c, .val = 0 }, - { .offset = 0x22007c, .val = 0 }, - { .offset = 0x32007c, .val = 0 }, - { .offset = 0x2007d, .val = 0 }, - { .offset = 0x12007d, .val = 0 }, - { .offset = 0x22007d, .val = 0 }, - { .offset = 0x32007d, .val = 0 }, - { .offset = 0x400fd, .val = 0 }, - { .offset = 0x400c0, .val = 0 }, - { .offset = 0x90201, .val = 0 }, - { .offset = 0x190201, .val = 0 }, - { .offset = 0x290201, .val = 0 }, - { .offset = 0x390201, .val = 0 }, - { .offset = 0x90202, .val = 0 }, - { .offset = 0x190202, .val = 0 }, - { .offset = 0x290202, .val = 0 }, - { .offset = 0x390202, .val = 0 }, - { .offset = 0x90203, .val = 0 }, - { .offset = 0x190203, .val = 0 }, - { .offset = 0x290203, .val = 0 }, - { .offset = 0x390203, .val = 0 }, - { .offset = 0x90204, .val = 0 }, - { .offset = 0x190204, .val = 0 }, - { .offset = 0x290204, .val = 0 }, - { .offset = 0x390204, .val = 0 }, - { .offset = 0x90205, .val = 0 }, - { .offset = 0x190205, .val = 0 }, - { .offset = 0x290205, .val = 0 }, - { .offset = 0x390205, .val = 0 }, - { .offset = 0x90206, .val = 0 }, - { .offset = 0x190206, .val = 0 }, - { .offset = 0x290206, .val = 0 }, - { .offset = 0x390206, .val = 0 }, - { .offset = 0x90207, .val = 0 }, - { .offset = 0x190207, .val = 0 }, - { .offset = 0x290207, .val = 0 }, - { .offset = 0x390207, .val = 0 }, - { .offset = 0x90208, .val = 0 }, - { .offset = 0x190208, .val = 0 }, - { .offset = 0x290208, .val = 0 }, - { .offset = 0x390208, .val = 0 }, - { .offset = 0x10062, .val = 0 }, - { .offset = 0x10162, .val = 0 }, - { .offset = 0x10262, .val = 0 }, - { .offset = 0x10362, .val = 0 }, - { .offset = 0x10462, .val = 0 }, - { .offset = 0x10562, .val = 0 }, - { .offset = 0x10662, .val = 0 }, - { .offset = 0x10762, .val = 0 }, - { .offset = 0x10862, .val = 0 }, - { .offset = 0x11062, .val = 0 }, - { .offset = 0x11162, .val = 0 }, - { .offset = 0x11262, .val = 0 }, - { .offset = 0x11362, .val = 0 }, - { .offset = 0x11462, .val = 0 }, - { .offset = 0x11562, .val = 0 }, - { .offset = 0x11662, .val = 0 }, - { .offset = 0x11762, .val = 0 }, - { .offset = 0x11862, .val = 0 }, - { .offset = 0x12062, .val = 0 }, - { .offset = 0x12162, .val = 0 }, - { .offset = 0x12262, .val = 0 }, - { .offset = 0x12362, .val = 0 }, - { .offset = 0x12462, .val = 0 }, - { .offset = 0x12562, .val = 0 }, - { .offset = 0x12662, .val = 0 }, - { .offset = 0x12762, .val = 0 }, - { .offset = 0x12862, .val = 0 }, - { .offset = 0x13062, .val = 0 }, - { .offset = 0x13162, .val = 0 }, - { .offset = 0x13262, .val = 0 }, - { .offset = 0x13362, .val = 0 }, - { .offset = 0x13462, .val = 0 }, - { .offset = 0x13562, .val = 0 }, - { .offset = 0x13662, .val = 0 }, - { .offset = 0x13762, .val = 0 }, - { .offset = 0x13862, .val = 0 }, - { .offset = 0x20077, .val = 0 }, - { .offset = 0x10001, .val = 0 }, - { .offset = 0x10011, .val = 0 }, - { .offset = 0x10012, .val = 0 }, - { .offset = 0x10013, .val = 0 }, - { .offset = 0x10014, .val = 0 }, - { .offset = 0x10018, .val = 0 }, - { .offset = 0x11001, .val = 0 }, - { .offset = 0x11011, .val = 0 }, - { .offset = 0x11012, .val = 0 }, - { .offset = 0x11013, .val = 0 }, - { .offset = 0x11014, .val = 0 }, - { .offset = 0x11018, .val = 0 }, - { .offset = 0x12001, .val = 0 }, - { .offset = 0x12011, .val = 0 }, - { .offset = 0x12012, .val = 0 }, - { .offset = 0x12013, .val = 0 }, - { .offset = 0x12014, .val = 0 }, - { .offset = 0x12018, .val = 0 }, - { .offset = 0x13001, .val = 0 }, - { .offset = 0x13011, .val = 0 }, - { .offset = 0x13012, .val = 0 }, - { .offset = 0x13013, .val = 0 }, - { .offset = 0x13014, .val = 0 }, - { .offset = 0x13018, .val = 0 }, - { .offset = 0x1008c, .val = 0 }, - { .offset = 0x11008c, .val = 0 }, - { .offset = 0x21008c, .val = 0 }, - { .offset = 0x31008c, .val = 0 }, - { .offset = 0x1018c, .val = 0 }, - { .offset = 0x11018c, .val = 0 }, - { .offset = 0x21018c, .val = 0 }, - { .offset = 0x31018c, .val = 0 }, - { .offset = 0x1008d, .val = 0 }, - { .offset = 0x11008d, .val = 0 }, - { .offset = 0x21008d, .val = 0 }, - { .offset = 0x31008d, .val = 0 }, - { .offset = 0x1018d, .val = 0 }, - { .offset = 0x11018d, .val = 0 }, - { .offset = 0x21018d, .val = 0 }, - { .offset = 0x31018d, .val = 0 }, - { .offset = 0x1008e, .val = 0 }, - { .offset = 0x11008e, .val = 0 }, - { .offset = 0x21008e, .val = 0 }, - { .offset = 0x31008e, .val = 0 }, - { .offset = 0x1018e, .val = 0 }, - { .offset = 0x11018e, .val = 0 }, - { .offset = 0x21018e, .val = 0 }, - { .offset = 0x31018e, .val = 0 }, - { .offset = 0x1008f, .val = 0 }, - { .offset = 0x11008f, .val = 0 }, - { .offset = 0x21008f, .val = 0 }, - { .offset = 0x31008f, .val = 0 }, - { .offset = 0x1018f, .val = 0 }, - { .offset = 0x11018f, .val = 0 }, - { .offset = 0x21018f, .val = 0 }, - { .offset = 0x31018f, .val = 0 }, - { .offset = 0x1108c, .val = 0 }, - { .offset = 0x11108c, .val = 0 }, - { .offset = 0x21108c, .val = 0 }, - { .offset = 0x31108c, .val = 0 }, - { .offset = 0x1118c, .val = 0 }, - { .offset = 0x11118c, .val = 0 }, - { .offset = 0x21118c, .val = 0 }, - { .offset = 0x31118c, .val = 0 }, - { .offset = 0x1108d, .val = 0 }, - { .offset = 0x11108d, .val = 0 }, - { .offset = 0x21108d, .val = 0 }, - { .offset = 0x31108d, .val = 0 }, - { .offset = 0x1118d, .val = 0 }, - { .offset = 0x11118d, .val = 0 }, - { .offset = 0x21118d, .val = 0 }, - { .offset = 0x31118d, .val = 0 }, - { .offset = 0x1108e, .val = 0 }, - { .offset = 0x11108e, .val = 0 }, - { .offset = 0x21108e, .val = 0 }, - { .offset = 0x31108e, .val = 0 }, - { .offset = 0x1118e, .val = 0 }, - { .offset = 0x11118e, .val = 0 }, - { .offset = 0x21118e, .val = 0 }, - { .offset = 0x31118e, .val = 0 }, - { .offset = 0x1108f, .val = 0 }, - { .offset = 0x11108f, .val = 0 }, - { .offset = 0x21108f, .val = 0 }, - { .offset = 0x31108f, .val = 0 }, - { .offset = 0x1118f, .val = 0 }, - { .offset = 0x11118f, .val = 0 }, - { .offset = 0x21118f, .val = 0 }, - { .offset = 0x31118f, .val = 0 }, - { .offset = 0x1208c, .val = 0 }, - { .offset = 0x11208c, .val = 0 }, - { .offset = 0x21208c, .val = 0 }, - { .offset = 0x31208c, .val = 0 }, - { .offset = 0x1218c, .val = 0 }, - { .offset = 0x11218c, .val = 0 }, - { .offset = 0x21218c, .val = 0 }, - { .offset = 0x31218c, .val = 0 }, - { .offset = 0x1208d, .val = 0 }, - { .offset = 0x11208d, .val = 0 }, - { .offset = 0x21208d, .val = 0 }, - { .offset = 0x31208d, .val = 0 }, - { .offset = 0x1218d, .val = 0 }, - { .offset = 0x11218d, .val = 0 }, - { .offset = 0x21218d, .val = 0 }, - { .offset = 0x31218d, .val = 0 }, - { .offset = 0x1208e, .val = 0 }, - { .offset = 0x11208e, .val = 0 }, - { .offset = 0x21208e, .val = 0 }, - { .offset = 0x31208e, .val = 0 }, - { .offset = 0x1218e, .val = 0 }, - { .offset = 0x11218e, .val = 0 }, - { .offset = 0x21218e, .val = 0 }, - { .offset = 0x31218e, .val = 0 }, - { .offset = 0x1208f, .val = 0 }, - { .offset = 0x11208f, .val = 0 }, - { .offset = 0x21208f, .val = 0 }, - { .offset = 0x31208f, .val = 0 }, - { .offset = 0x1218f, .val = 0 }, - { .offset = 0x11218f, .val = 0 }, - { .offset = 0x21218f, .val = 0 }, - { .offset = 0x31218f, .val = 0 }, - { .offset = 0x1308c, .val = 0 }, - { .offset = 0x11308c, .val = 0 }, - { .offset = 0x21308c, .val = 0 }, - { .offset = 0x31308c, .val = 0 }, - { .offset = 0x1318c, .val = 0 }, - { .offset = 0x11318c, .val = 0 }, - { .offset = 0x21318c, .val = 0 }, - { .offset = 0x31318c, .val = 0 }, - { .offset = 0x1308d, .val = 0 }, - { .offset = 0x11308d, .val = 0 }, - { .offset = 0x21308d, .val = 0 }, - { .offset = 0x31308d, .val = 0 }, - { .offset = 0x1318d, .val = 0 }, - { .offset = 0x11318d, .val = 0 }, - { .offset = 0x21318d, .val = 0 }, - { .offset = 0x31318d, .val = 0 }, - { .offset = 0x1308e, .val = 0 }, - { .offset = 0x11308e, .val = 0 }, - { .offset = 0x21308e, .val = 0 }, - { .offset = 0x31308e, .val = 0 }, - { .offset = 0x1318e, .val = 0 }, - { .offset = 0x11318e, .val = 0 }, - { .offset = 0x21318e, .val = 0 }, - { .offset = 0x31318e, .val = 0 }, - { .offset = 0x1308f, .val = 0 }, - { .offset = 0x11308f, .val = 0 }, - { .offset = 0x21308f, .val = 0 }, - { .offset = 0x31308f, .val = 0 }, - { .offset = 0x1318f, .val = 0 }, - { .offset = 0x11318f, .val = 0 }, - { .offset = 0x21318f, .val = 0 }, - { .offset = 0x31318f, .val = 0 }, - { .offset = 0x10040, .val = 0 }, - { .offset = 0x10140, .val = 0 }, - { .offset = 0x10240, .val = 0 }, - { .offset = 0x10340, .val = 0 }, - { .offset = 0x10440, .val = 0 }, - { .offset = 0x10540, .val = 0 }, - { .offset = 0x10640, .val = 0 }, - { .offset = 0x10740, .val = 0 }, - { .offset = 0x10840, .val = 0 }, - { .offset = 0x10030, .val = 0 }, - { .offset = 0x10130, .val = 0 }, - { .offset = 0x10230, .val = 0 }, - { .offset = 0x10330, .val = 0 }, - { .offset = 0x10430, .val = 0 }, - { .offset = 0x10530, .val = 0 }, - { .offset = 0x10630, .val = 0 }, - { .offset = 0x10730, .val = 0 }, - { .offset = 0x10830, .val = 0 }, - { .offset = 0x11040, .val = 0 }, - { .offset = 0x11140, .val = 0 }, - { .offset = 0x11240, .val = 0 }, - { .offset = 0x11340, .val = 0 }, - { .offset = 0x11440, .val = 0 }, - { .offset = 0x11540, .val = 0 }, - { .offset = 0x11640, .val = 0 }, - { .offset = 0x11740, .val = 0 }, - { .offset = 0x11840, .val = 0 }, - { .offset = 0x11030, .val = 0 }, - { .offset = 0x11130, .val = 0 }, - { .offset = 0x11230, .val = 0 }, - { .offset = 0x11330, .val = 0 }, - { .offset = 0x11430, .val = 0 }, - { .offset = 0x11530, .val = 0 }, - { .offset = 0x11630, .val = 0 }, - { .offset = 0x11730, .val = 0 }, - { .offset = 0x11830, .val = 0 }, - { .offset = 0x12040, .val = 0 }, - { .offset = 0x12140, .val = 0 }, - { .offset = 0x12240, .val = 0 }, - { .offset = 0x12340, .val = 0 }, - { .offset = 0x12440, .val = 0 }, - { .offset = 0x12540, .val = 0 }, - { .offset = 0x12640, .val = 0 }, - { .offset = 0x12740, .val = 0 }, - { .offset = 0x12840, .val = 0 }, - { .offset = 0x12030, .val = 0 }, - { .offset = 0x12130, .val = 0 }, - { .offset = 0x12230, .val = 0 }, - { .offset = 0x12330, .val = 0 }, - { .offset = 0x12430, .val = 0 }, - { .offset = 0x12530, .val = 0 }, - { .offset = 0x12630, .val = 0 }, - { .offset = 0x12730, .val = 0 }, - { .offset = 0x12830, .val = 0 }, - { .offset = 0x13040, .val = 0 }, - { .offset = 0x13140, .val = 0 }, - { .offset = 0x13240, .val = 0 }, - { .offset = 0x13340, .val = 0 }, - { .offset = 0x13440, .val = 0 }, - { .offset = 0x13540, .val = 0 }, - { .offset = 0x13640, .val = 0 }, - { .offset = 0x13740, .val = 0 }, - { .offset = 0x13840, .val = 0 }, - { .offset = 0x13030, .val = 0 }, - { .offset = 0x13130, .val = 0 }, - { .offset = 0x13230, .val = 0 }, - { .offset = 0x13330, .val = 0 }, - { .offset = 0x13430, .val = 0 }, - { .offset = 0x13530, .val = 0 }, - { .offset = 0x13630, .val = 0 }, - { .offset = 0x13730, .val = 0 }, - { .offset = 0x13830, .val = 0 }, -}; - -static struct ddrphy_trained_csr data_before_restore[] = { - { .offset = 0xd0000, .val = 0x0 }, - { .offset = 0x20110, .val = 0x02 }, - { .offset = 0x20111, .val = 0x03 }, - { .offset = 0x20112, .val = 0x04 }, - { .offset = 0x20113, .val = 0x05 }, - { .offset = 0x20114, .val = 0x00 }, - { .offset = 0x20115, .val = 0x01 }, - { .offset = 0x1005f, .val = 0x1ff }, - { .offset = 0x1015f, .val = 0x1ff }, - { .offset = 0x1105f, .val = 0x1ff }, - { .offset = 0x1115f, .val = 0x1ff }, - { .offset = 0x1205f, .val = 0x1ff }, - { .offset = 0x1215f, .val = 0x1ff }, - { .offset = 0x1305f, .val = 0x1ff }, - { .offset = 0x1315f, .val = 0x1ff }, - { .offset = 0x11005f, .val = 0x1ff }, - { .offset = 0x11015f, .val = 0x1ff }, - { .offset = 0x11105f, .val = 0x1ff }, - { .offset = 0x11115f, .val = 0x1ff }, - { .offset = 0x11205f, .val = 0x1ff }, - { .offset = 0x11215f, .val = 0x1ff }, - { .offset = 0x11305f, .val = 0x1ff }, - { .offset = 0x11315f, .val = 0x1ff }, - { .offset = 0x21005f, .val = 0x1ff }, - { .offset = 0x21015f, .val = 0x1ff }, - { .offset = 0x21105f, .val = 0x1ff }, - { .offset = 0x21115f, .val = 0x1ff }, - { .offset = 0x21205f, .val = 0x1ff }, - { .offset = 0x21215f, .val = 0x1ff }, - { .offset = 0x21305f, .val = 0x1ff }, - { .offset = 0x21315f, .val = 0x1ff }, - { .offset = 0x55, .val=0x1ff }, - { .offset = 0x1055, .val=0x1ff }, - { .offset = 0x2055, .val=0x1ff }, - { .offset = 0x3055, .val=0x1ff }, - { .offset = 0x4055, .val=0x1ff }, - { .offset = 0x5055, .val=0x1ff }, - { .offset = 0x6055, .val=0x1ff }, - { .offset = 0x7055, .val=0x1ff }, - { .offset = 0x8055, .val=0x1ff }, - { .offset = 0x9055, .val=0x1ff }, - { .offset = 0x200c5, .val=0x19 }, - { .offset = 0x1200c5, .val=0x7 }, - { .offset = 0x2200c5, .val=0x7 }, - { .offset = 0x2002e, .val=0x2 }, - { .offset = 0x12002e, .val=0x2 }, - { .offset = 0x22002e, .val=0x2 }, - { .offset = 0x90204, .val=0x0 }, - { .offset = 0x190204, .val=0x0 }, - { .offset = 0x290204, .val=0x0 }, - { .offset = 0x20024, .val=0xab }, - { .offset = 0x2003a, .val=0x0 }, - { .offset = 0x120024, .val = 0xab }, - { .offset = 0x2003a, .val = 0x0 }, - { .offset = 0x120024, .val = 0xab }, - { .offset = 0x2003a, .val = 0x0 }, - { .offset = 0x20056, .val = 0x3 }, - { .offset = 0x120056, .val = 0xa }, - { .offset = 0x220056, .val = 0xa }, - { .offset = 0x1004d, .val = 0xe00 }, - { .offset = 0x1014d, .val = 0xe00 }, - { .offset = 0x1104d, .val = 0xe00 }, - { .offset = 0x1114d, .val = 0xe00 }, - { .offset = 0x1204d, .val = 0xe00 }, - { .offset = 0x1214d, .val = 0xe00 }, - { .offset = 0x1304d, .val = 0xe00 }, - { .offset = 0x1314d, .val = 0xe00 }, - { .offset = 0x11004d, .val = 0xe00 }, - { .offset = 0x11014d, .val = 0xe00 }, - { .offset = 0x11104d, .val = 0xe00 }, - { .offset = 0x11114d, .val = 0xe00 }, - { .offset = 0x11204d, .val = 0xe00 }, - { .offset = 0x11214d, .val = 0xe00 }, - { .offset = 0x11304d, .val = 0xe00 }, - { .offset = 0x11314d, .val = 0xe00 }, - { .offset = 0x21004d, .val = 0xe00 }, - { .offset = 0x21014d, .val = 0xe00 }, - { .offset = 0x21104d, .val = 0xe00 }, - { .offset = 0x21114d, .val = 0xe00 }, - { .offset = 0x21204d, .val = 0xe00 }, - { .offset = 0x21214d, .val = 0xe00 }, - { .offset = 0x21304d, .val = 0xe00 }, - { .offset = 0x21314d, .val = 0xe00 }, - { .offset = 0x10049, .val = 0xe38 }, - { .offset = 0x10149, .val = 0xe38 }, - { .offset = 0x11049, .val = 0xe38 }, - { .offset = 0x11149, .val = 0xe38 }, - { .offset = 0x12049, .val = 0xe38 }, - { .offset = 0x12149, .val = 0xe38 }, - { .offset = 0x13049, .val = 0xe38 }, - { .offset = 0x13149, .val = 0xe38 }, - { .offset = 0x110049, .val = 0xe38 }, - { .offset = 0x110149, .val = 0xe38 }, - { .offset = 0x111049, .val = 0xe38 }, - { .offset = 0x111149, .val = 0xe38 }, - { .offset = 0x112049, .val = 0xe38 }, - { .offset = 0x112149, .val = 0xe38 }, - { .offset = 0x113049, .val = 0xe38 }, - { .offset = 0x113149, .val = 0xe38 }, - { .offset = 0x210049, .val = 0xe38 }, - { .offset = 0x210149, .val = 0xe38 }, - { .offset = 0x211049, .val = 0xe38 }, - { .offset = 0x211149, .val = 0xe38 }, - { .offset = 0x212049, .val = 0xe38 }, - { .offset = 0x212149, .val = 0xe38 }, - { .offset = 0x213049, .val = 0xe38 }, - { .offset = 0x213149, .val = 0xe38 }, - { .offset = 0x43, .val = 0x21 }, - { .offset = 0x1043, .val = 0x21 }, - { .offset = 0x2043, .val = 0x21 }, - { .offset = 0x3043, .val = 0x21 }, - { .offset = 0x4043, .val = 0x21 }, - { .offset = 0x5043, .val = 0x21 }, - { .offset = 0x6043, .val = 0x21 }, - { .offset = 0x7043, .val = 0x21 }, - { .offset = 0x8043, .val = 0x21 }, - { .offset = 0x9043, .val = 0x21 }, - { .offset = 0x20018, .val = 0x3 }, - { .offset = 0x20075, .val = 0x4 }, - { .offset = 0x20050, .val = 0x0 }, - { .offset = 0x20008, .val = 0x320 }, - { .offset = 0x120008, .val = 0x64 }, - { .offset = 0x220008, .val = 0x19 }, - { .offset = 0x20088, .val = 0x9 }, - { .offset = 0x200b2, .val = 0x19c }, - { .offset = 0x10043, .val = 0x5a1 }, - { .offset = 0x10143, .val = 0x5a1 }, - { .offset = 0x11043, .val = 0x5a1 }, - { .offset = 0x11143, .val = 0x5a1 }, - { .offset = 0x12043, .val = 0x5a1 }, - { .offset = 0x12143, .val = 0x5a1 }, - { .offset = 0x13043, .val = 0x5a1 }, - { .offset = 0x13143, .val = 0x5a1 }, - { .offset = 0x1200b2, .val = 0x19c }, - { .offset = 0x110043, .val = 0x5a1 }, - { .offset = 0x110143, .val = 0x5a1 }, - { .offset = 0x111043, .val = 0x5a1 }, - { .offset = 0x111143, .val = 0x5a1 }, - { .offset = 0x112043, .val = 0x5a1 }, - { .offset = 0x112143, .val = 0x5a1 }, - { .offset = 0x113043, .val = 0x5a1 }, - { .offset = 0x113143, .val = 0x5a1 }, - { .offset = 0x2200b2, .val = 0x19c }, - { .offset = 0x210043, .val = 0x5a1 }, - { .offset = 0x210143, .val = 0x5a1 }, - { .offset = 0x211043, .val = 0x5a1 }, - { .offset = 0x211143, .val = 0x5a1 }, - { .offset = 0x212043, .val = 0x5a1 }, - { .offset = 0x212143, .val = 0x5a1 }, - { .offset = 0x213043, .val = 0x5a1 }, - { .offset = 0x213143, .val = 0x5a1 }, - { .offset = 0x200fa, .val = 0x1 }, - { .offset = 0x1200fa, .val = 0x1 }, - { .offset = 0x2200fa, .val = 0x1 }, - { .offset = 0x20019, .val = 0x1 }, - { .offset = 0x120019, .val = 0x1 }, - { .offset = 0x220019, .val = 0x1 }, - { .offset = 0x200f0, .val = 0x660 }, - { .offset = 0x200f1, .val = 0x0 }, - { .offset = 0x200f2, .val = 0x4444 }, - { .offset = 0x200f3, .val = 0x8888 }, - { .offset = 0x200f4, .val = 0x5555 }, - { .offset = 0x200f5, .val = 0x0 }, - { .offset = 0x200f6, .val = 0x0 }, - { .offset = 0x200f7, .val = 0xf000 }, - { .offset = 0x2000b, .val = 0x65 }, - { .offset = 0x2000c, .val = 0xc9 }, - { .offset = 0x2000d, .val = 0x7d1 }, - { .offset = 0x2000e, .val = 0x2c }, - { .offset = 0x12000b, .val = 0xd }, - { .offset = 0x12000c, .val = 0x1a }, - { .offset = 0x12000d, .val = 0xfb }, - { .offset = 0x12000e, .val = 0x10 }, - { .offset = 0x22000b, .val = 0x4 }, - { .offset = 0x22000c, .val = 0x7 }, - { .offset = 0x22000d, .val = 0x3f }, - { .offset = 0x22000e, .val = 0x10 }, - { .offset = 0x20025, .val = 0x0 }, - { .offset = 0x2002d, .val = 0x0 }, - { .offset = 0x12002d, .val = 0x0 }, - { .offset = 0x22002d, .val = 0x0 }, -}; - -static struct ddrphy_trained_csr data_after_restore[] = { - { .offset = 0xd0000, .val = 0x0 }, - { .offset = 0x90000, .val = 0x10 }, - { .offset = 0x90001, .val = 0x400 }, - { .offset = 0x90002, .val = 0x10e }, - { .offset = 0x90003, .val = 0x0 }, - { .offset = 0x90004, .val = 0x0 }, - { .offset = 0x90005, .val = 0x8 }, - { .offset = 0x90029, .val = 0xb }, - { .offset = 0x9002a, .val = 0x480 }, - { .offset = 0x9002b, .val = 0x109 }, - { .offset = 0x9002c, .val = 0x8 }, - { .offset = 0x9002d, .val = 0x448 }, - { .offset = 0x9002e, .val = 0x139 }, - { .offset = 0x9002f, .val = 0x8 }, - { .offset = 0x90030, .val = 0x478 }, - { .offset = 0x90031, .val = 0x109 }, - { .offset = 0x90032, .val = 0x0 }, - { .offset = 0x90033, .val = 0xe8 }, - { .offset = 0x90034, .val = 0x109 }, - { .offset = 0x90035, .val = 0x2 }, - { .offset = 0x90036, .val = 0x10 }, - { .offset = 0x90037, .val = 0x139 }, - { .offset = 0x90038, .val = 0xf }, - { .offset = 0x90039, .val = 0x7c0 }, - { .offset = 0x9003a, .val = 0x139 }, - { .offset = 0x9003b, .val = 0x44 }, - { .offset = 0x9003c, .val = 0x630 }, - { .offset = 0x9003d, .val = 0x159 }, - { .offset = 0x9003e, .val = 0x14f }, - { .offset = 0x9003f, .val = 0x630 }, - { .offset = 0x90040, .val = 0x159 }, - { .offset = 0x90041, .val = 0x47 }, - { .offset = 0x90042, .val = 0x630 }, - { .offset = 0x90043, .val = 0x149 }, - { .offset = 0x90044, .val = 0x4f }, - { .offset = 0x90045, .val = 0x630 }, - { .offset = 0x90046, .val = 0x179 }, - { .offset = 0x90047, .val = 0x8 }, - { .offset = 0x90048, .val = 0xe0 }, - { .offset = 0x90049, .val = 0x109 }, - { .offset = 0x9004a, .val = 0x0 }, - { .offset = 0x9004b, .val = 0x7c8 }, - { .offset = 0x9004c, .val = 0x109 }, - { .offset = 0x9004d, .val = 0x0 }, - { .offset = 0x9004e, .val = 0x1 }, - { .offset = 0x9004f, .val = 0x8 }, - { .offset = 0x90050, .val = 0x0 }, - { .offset = 0x90051, .val = 0x45a }, - { .offset = 0x90052, .val = 0x9 }, - { .offset = 0x90053, .val = 0x0 }, - { .offset = 0x90054, .val = 0x448 }, - { .offset = 0x90055, .val = 0x109 }, - { .offset = 0x90056, .val = 0x40 }, - { .offset = 0x90057, .val = 0x630 }, - { .offset = 0x90058, .val = 0x179 }, - { .offset = 0x90059, .val = 0x1 }, - { .offset = 0x9005a, .val = 0x618 }, - { .offset = 0x9005b, .val = 0x109 }, - { .offset = 0x9005c, .val = 0x40c0 }, - { .offset = 0x9005d, .val = 0x630 }, - { .offset = 0x9005e, .val = 0x149 }, - { .offset = 0x9005f, .val = 0x8 }, - { .offset = 0x90060, .val = 0x4 }, - { .offset = 0x90061, .val = 0x48 }, - { .offset = 0x90062, .val = 0x4040 }, - { .offset = 0x90063, .val = 0x630 }, - { .offset = 0x90064, .val = 0x149 }, - { .offset = 0x90065, .val = 0x0 }, - { .offset = 0x90066, .val = 0x4 }, - { .offset = 0x90067, .val = 0x48 }, - { .offset = 0x90068, .val = 0x40 }, - { .offset = 0x90069, .val = 0x630 }, - { .offset = 0x9006a, .val = 0x149 }, - { .offset = 0x9006b, .val = 0x10 }, - { .offset = 0x9006c, .val = 0x4 }, - { .offset = 0x9006d, .val = 0x18 }, - { .offset = 0x9006e, .val = 0x0 }, - { .offset = 0x9006f, .val = 0x4 }, - { .offset = 0x90070, .val = 0x78 }, - { .offset = 0x90071, .val = 0x549 }, - { .offset = 0x90072, .val = 0x630 }, - { .offset = 0x90073, .val = 0x159 }, - { .offset = 0x90074, .val = 0xd49 }, - { .offset = 0x90075, .val = 0x630 }, - { .offset = 0x90076, .val = 0x159 }, - { .offset = 0x90077, .val = 0x94a }, - { .offset = 0x90078, .val = 0x630 }, - { .offset = 0x90079, .val = 0x159 }, - { .offset = 0x9007a, .val = 0x441 }, - { .offset = 0x9007b, .val = 0x630 }, - { .offset = 0x9007c, .val = 0x149 }, - { .offset = 0x9007d, .val = 0x42 }, - { .offset = 0x9007e, .val = 0x630 }, - { .offset = 0x9007f, .val = 0x149 }, - { .offset = 0x90080, .val = 0x1 }, - { .offset = 0x90081, .val = 0x630 }, - { .offset = 0x90082, .val = 0x149 }, - { .offset = 0x90083, .val = 0x0 }, - { .offset = 0x90084, .val = 0xe0 }, - { .offset = 0x90085, .val = 0x109 }, - { .offset = 0x90086, .val = 0xa }, - { .offset = 0x90087, .val = 0x10 }, - { .offset = 0x90088, .val = 0x109 }, - { .offset = 0x90089, .val = 0x9 }, - { .offset = 0x9008a, .val = 0x3c0 }, - { .offset = 0x9008b, .val = 0x149 }, - { .offset = 0x9008c, .val = 0x9 }, - { .offset = 0x9008d, .val = 0x3c0 }, - { .offset = 0x9008e, .val = 0x159 }, - { .offset = 0x9008f, .val = 0x18 }, - { .offset = 0x90090, .val = 0x10 }, - { .offset = 0x90091, .val = 0x109 }, - { .offset = 0x90092, .val = 0x0 }, - { .offset = 0x90093, .val = 0x3c0 }, - { .offset = 0x90094, .val = 0x109 }, - { .offset = 0x90095, .val = 0x18 }, - { .offset = 0x90096, .val = 0x4 }, - { .offset = 0x90097, .val = 0x48 }, - { .offset = 0x90098, .val = 0x18 }, - { .offset = 0x90099, .val = 0x4 }, - { .offset = 0x9009a, .val = 0x58 }, - { .offset = 0x9009b, .val = 0xa }, - { .offset = 0x9009c, .val = 0x10 }, - { .offset = 0x9009d, .val = 0x109 }, - { .offset = 0x9009e, .val = 0x2 }, - { .offset = 0x9009f, .val = 0x10 }, - { .offset = 0x900a0, .val = 0x109 }, - { .offset = 0x900a1, .val = 0x5 }, - { .offset = 0x900a2, .val = 0x7c0 }, - { .offset = 0x900a3, .val = 0x109 }, - { .offset = 0x900a4, .val = 0x10 }, - { .offset = 0x900a5, .val = 0x10 }, - { .offset = 0x900a6, .val = 0x109 }, - { .offset = 0x40000, .val = 0x811 }, - { .offset = 0x40020, .val = 0x880 }, - { .offset = 0x40040, .val = 0x0 }, - { .offset = 0x40060, .val = 0x0 }, - { .offset = 0x40001, .val = 0x4016 }, - { .offset = 0x40021, .val = 0x83 }, - { .offset = 0x40041, .val = 0x4f }, - { .offset = 0x40061, .val = 0x0 }, - { .offset = 0x40002, .val = 0x4040 }, - { .offset = 0x40022, .val = 0x83 }, - { .offset = 0x40042, .val = 0x51 }, - { .offset = 0x40062, .val = 0x0 }, - { .offset = 0x40003, .val = 0x811 }, - { .offset = 0x40023, .val = 0x880 }, - { .offset = 0x40043, .val = 0x0 }, - { .offset = 0x40063, .val = 0x0 }, - { .offset = 0x40004, .val = 0x720 }, - { .offset = 0x40024, .val = 0xf }, - { .offset = 0x40044, .val = 0x1740 }, - { .offset = 0x40064, .val = 0x0 }, - { .offset = 0x40005, .val = 0x16 }, - { .offset = 0x40025, .val = 0x83 }, - { .offset = 0x40045, .val = 0x4b }, - { .offset = 0x40065, .val = 0x0 }, - { .offset = 0x40006, .val = 0x716 }, - { .offset = 0x40026, .val = 0xf }, - { .offset = 0x40046, .val = 0x2001 }, - { .offset = 0x40066, .val = 0x0 }, - { .offset = 0x40007, .val = 0x716 }, - { .offset = 0x40027, .val = 0xf }, - { .offset = 0x40047, .val = 0x2800 }, - { .offset = 0x40067, .val = 0x0 }, - { .offset = 0x40008, .val = 0x716 }, - { .offset = 0x40028, .val = 0xf }, - { .offset = 0x40048, .val = 0xf00 }, - { .offset = 0x40068, .val = 0x0 }, - { .offset = 0x40009, .val = 0x720 }, - { .offset = 0x40029, .val = 0xf }, - { .offset = 0x40049, .val = 0x1400 }, - { .offset = 0x40069, .val = 0x0 }, - { .offset = 0x4000a, .val = 0xe08 }, - { .offset = 0x4002a, .val = 0xc15 }, - { .offset = 0x4004a, .val = 0x0 }, - { .offset = 0x4006a, .val = 0x0 }, - { .offset = 0x4000b, .val = 0x623 }, - { .offset = 0x4002b, .val = 0x15 }, - { .offset = 0x4004b, .val = 0x0 }, - { .offset = 0x4006b, .val = 0x0 }, - { .offset = 0x4000c, .val = 0x4004 }, - { .offset = 0x4002c, .val = 0x80 }, - { .offset = 0x4004c, .val = 0x0 }, - { .offset = 0x4006c, .val = 0x0 }, - { .offset = 0x4000d, .val = 0xe08 }, - { .offset = 0x4002d, .val = 0xc1a }, - { .offset = 0x4004d, .val = 0x0 }, - { .offset = 0x4006d, .val = 0x0 }, - { .offset = 0x4000e, .val = 0x623 }, - { .offset = 0x4002e, .val = 0x1a }, - { .offset = 0x4004e, .val = 0x0 }, - { .offset = 0x4006e, .val = 0x0 }, - { .offset = 0x4000f, .val = 0x4040 }, - { .offset = 0x4002f, .val = 0x80 }, - { .offset = 0x4004f, .val = 0x0 }, - { .offset = 0x4006f, .val = 0x0 }, - { .offset = 0x40010, .val = 0x2604 }, - { .offset = 0x40030, .val = 0x15 }, - { .offset = 0x40050, .val = 0x0 }, - { .offset = 0x40070, .val = 0x0 }, - { .offset = 0x40011, .val = 0x708 }, - { .offset = 0x40031, .val = 0x5 }, - { .offset = 0x40051, .val = 0x0 }, - { .offset = 0x40071, .val = 0x2002 }, - { .offset = 0x40012, .val = 0x8 }, - { .offset = 0x40032, .val = 0x80 }, - { .offset = 0x40052, .val = 0x0 }, - { .offset = 0x40072, .val = 0x0 }, - { .offset = 0x40013, .val = 0x2604 }, - { .offset = 0x40033, .val = 0x1a }, - { .offset = 0x40053, .val = 0x0 }, - { .offset = 0x40073, .val = 0x0 }, - { .offset = 0x40014, .val = 0x708 }, - { .offset = 0x40034, .val = 0xa }, - { .offset = 0x40054, .val = 0x0 }, - { .offset = 0x40074, .val = 0x2002 }, - { .offset = 0x40015, .val = 0x4040 }, - { .offset = 0x40035, .val = 0x80 }, - { .offset = 0x40055, .val = 0x0 }, - { .offset = 0x40075, .val = 0x0 }, - { .offset = 0x40016, .val = 0x60a }, - { .offset = 0x40036, .val = 0x15 }, - { .offset = 0x40056, .val = 0x1200 }, - { .offset = 0x40076, .val = 0x0 }, - { .offset = 0x40017, .val = 0x61a }, - { .offset = 0x40037, .val = 0x15 }, - { .offset = 0x40057, .val = 0x1300 }, - { .offset = 0x40077, .val = 0x0 }, - { .offset = 0x40018, .val = 0x60a }, - { .offset = 0x40038, .val = 0x1a }, - { .offset = 0x40058, .val = 0x1200 }, - { .offset = 0x40078, .val = 0x0 }, - { .offset = 0x40019, .val = 0x642 }, - { .offset = 0x40039, .val = 0x1a }, - { .offset = 0x40059, .val = 0x1300 }, - { .offset = 0x40079, .val = 0x0 }, - { .offset = 0x4001a, .val = 0x4808 }, - { .offset = 0x4003a, .val = 0x880 }, - { .offset = 0x4005a, .val = 0x0 }, - { .offset = 0x4007a, .val = 0x0 }, - { .offset = 0x900a7, .val = 0x0 }, - { .offset = 0x900a8, .val = 0x790 }, - { .offset = 0x900a9, .val = 0x11a }, - { .offset = 0x900aa, .val = 0x8 }, - { .offset = 0x900ab, .val = 0x7aa }, - { .offset = 0x900ac, .val = 0x2a }, - { .offset = 0x900ad, .val = 0x10 }, - { .offset = 0x900ae, .val = 0x7b2 }, - { .offset = 0x900af, .val = 0x2a }, - { .offset = 0x900b0, .val = 0x0 }, - { .offset = 0x900b1, .val = 0x7c8 }, - { .offset = 0x900b2, .val = 0x109 }, - { .offset = 0x900b3, .val = 0x10 }, - { .offset = 0x900b4, .val = 0x2a8 }, - { .offset = 0x900b5, .val = 0x129 }, - { .offset = 0x900b6, .val = 0x8 }, - { .offset = 0x900b7, .val = 0x370 }, - { .offset = 0x900b8, .val = 0x129 }, - { .offset = 0x900b9, .val = 0xa }, - { .offset = 0x900ba, .val = 0x3c8 }, - { .offset = 0x900bb, .val = 0x1a9 }, - { .offset = 0x900bc, .val = 0xc }, - { .offset = 0x900bd, .val = 0x408 }, - { .offset = 0x900be, .val = 0x199 }, - { .offset = 0x900bf, .val = 0x14 }, - { .offset = 0x900c0, .val = 0x790 }, - { .offset = 0x900c1, .val = 0x11a }, - { .offset = 0x900c2, .val = 0x8 }, - { .offset = 0x900c3, .val = 0x4 }, - { .offset = 0x900c4, .val = 0x18 }, - { .offset = 0x900c5, .val = 0xc }, - { .offset = 0x900c6, .val = 0x408 }, - { .offset = 0x900c7, .val = 0x199 }, - { .offset = 0x900c8, .val = 0x8 }, - { .offset = 0x900c9, .val = 0x8568 }, - { .offset = 0x900ca, .val = 0x108 }, - { .offset = 0x900cb, .val = 0x18 }, - { .offset = 0x900cc, .val = 0x790 }, - { .offset = 0x900cd, .val = 0x16a }, - { .offset = 0x900ce, .val = 0x8 }, - { .offset = 0x900cf, .val = 0x1d8 }, - { .offset = 0x900d0, .val = 0x169 }, - { .offset = 0x900d1, .val = 0x10 }, - { .offset = 0x900d2, .val = 0x8558 }, - { .offset = 0x900d3, .val = 0x168 }, - { .offset = 0x900d4, .val = 0x70 }, - { .offset = 0x900d5, .val = 0x788 }, - { .offset = 0x900d6, .val = 0x16a }, - { .offset = 0x900d7, .val = 0x1ff8 }, - { .offset = 0x900d8, .val = 0x85a8 }, - { .offset = 0x900d9, .val = 0x1e8 }, - { .offset = 0x900da, .val = 0x50 }, - { .offset = 0x900db, .val = 0x798 }, - { .offset = 0x900dc, .val = 0x16a }, - { .offset = 0x900dd, .val = 0x60 }, - { .offset = 0x900de, .val = 0x7a0 }, - { .offset = 0x900df, .val = 0x16a }, - { .offset = 0x900e0, .val = 0x8 }, - { .offset = 0x900e1, .val = 0x8310 }, - { .offset = 0x900e2, .val = 0x168 }, - { .offset = 0x900e3, .val = 0x8 }, - { .offset = 0x900e4, .val = 0xa310 }, - { .offset = 0x900e5, .val = 0x168 }, - { .offset = 0x900e6, .val = 0xa }, - { .offset = 0x900e7, .val = 0x408 }, - { .offset = 0x900e8, .val = 0x169 }, - { .offset = 0x900e9, .val = 0x6e }, - { .offset = 0x900ea, .val = 0x0 }, - { .offset = 0x900eb, .val = 0x68 }, - { .offset = 0x900ec, .val = 0x0 }, - { .offset = 0x900ed, .val = 0x408 }, - { .offset = 0x900ee, .val = 0x169 }, - { .offset = 0x900ef, .val = 0x0 }, - { .offset = 0x900f0, .val = 0x8310 }, - { .offset = 0x900f1, .val = 0x168 }, - { .offset = 0x900f2, .val = 0x0 }, - { .offset = 0x900f3, .val = 0xa310 }, - { .offset = 0x900f4, .val = 0x168 }, - { .offset = 0x900f5, .val = 0x1ff8 }, - { .offset = 0x900f6, .val = 0x85a8 }, - { .offset = 0x900f7, .val = 0x1e8 }, - { .offset = 0x900f8, .val = 0x68 }, - { .offset = 0x900f9, .val = 0x798 }, - { .offset = 0x900fa, .val = 0x16a }, - { .offset = 0x900fb, .val = 0x78 }, - { .offset = 0x900fc, .val = 0x7a0 }, - { .offset = 0x900fd, .val = 0x16a }, - { .offset = 0x900fe, .val = 0x68 }, - { .offset = 0x900ff, .val = 0x790 }, - { .offset = 0x90100, .val = 0x16a }, - { .offset = 0x90101, .val = 0x8 }, - { .offset = 0x90102, .val = 0x8b10 }, - { .offset = 0x90103, .val = 0x168 }, - { .offset = 0x90104, .val = 0x8 }, - { .offset = 0x90105, .val = 0xab10 }, - { .offset = 0x90106, .val = 0x168 }, - { .offset = 0x90107, .val = 0xa }, - { .offset = 0x90108, .val = 0x408 }, - { .offset = 0x90109, .val = 0x169 }, - { .offset = 0x9010a, .val = 0x58 }, - { .offset = 0x9010b, .val = 0x0 }, - { .offset = 0x9010c, .val = 0x68 }, - { .offset = 0x9010d, .val = 0x0 }, - { .offset = 0x9010e, .val = 0x408 }, - { .offset = 0x9010f, .val = 0x169 }, - { .offset = 0x90110, .val = 0x0 }, - { .offset = 0x90111, .val = 0x8b10 }, - { .offset = 0x90112, .val = 0x168 }, - { .offset = 0x90113, .val = 0x0 }, - { .offset = 0x90114, .val = 0xab10 }, - { .offset = 0x90115, .val = 0x168 }, - { .offset = 0x90116, .val = 0x0 }, - { .offset = 0x90117, .val = 0x1d8 }, - { .offset = 0x90118, .val = 0x169 }, - { .offset = 0x90119, .val = 0x80 }, - { .offset = 0x9011a, .val = 0x790 }, - { .offset = 0x9011b, .val = 0x16a }, - { .offset = 0x9011c, .val = 0x18 }, - { .offset = 0x9011d, .val = 0x7aa }, - { .offset = 0x9011e, .val = 0x6a }, - { .offset = 0x9011f, .val = 0xa }, - { .offset = 0x90120, .val = 0x0 }, - { .offset = 0x90121, .val = 0x1e9 }, - { .offset = 0x90122, .val = 0x8 }, - { .offset = 0x90123, .val = 0x8080 }, - { .offset = 0x90124, .val = 0x108 }, - { .offset = 0x90125, .val = 0xf }, - { .offset = 0x90126, .val = 0x408 }, - { .offset = 0x90127, .val = 0x169 }, - { .offset = 0x90128, .val = 0xc }, - { .offset = 0x90129, .val = 0x0 }, - { .offset = 0x9012a, .val = 0x68 }, - { .offset = 0x9012b, .val = 0x9 }, - { .offset = 0x9012c, .val = 0x0 }, - { .offset = 0x9012d, .val = 0x1a9 }, - { .offset = 0x9012e, .val = 0x0 }, - { .offset = 0x9012f, .val = 0x408 }, - { .offset = 0x90130, .val = 0x169 }, - { .offset = 0x90131, .val = 0x0 }, - { .offset = 0x90132, .val = 0x8080 }, - { .offset = 0x90133, .val = 0x108 }, - { .offset = 0x90134, .val = 0x8 }, - { .offset = 0x90135, .val = 0x7aa }, - { .offset = 0x90136, .val = 0x6a }, - { .offset = 0x90137, .val = 0x0 }, - { .offset = 0x90138, .val = 0x8568 }, - { .offset = 0x90139, .val = 0x108 }, - { .offset = 0x9013a, .val = 0xb7 }, - { .offset = 0x9013b, .val = 0x790 }, - { .offset = 0x9013c, .val = 0x16a }, - { .offset = 0x9013d, .val = 0x1d }, - { .offset = 0x9013e, .val = 0x0 }, - { .offset = 0x9013f, .val = 0x68 }, - { .offset = 0x90140, .val = 0x8 }, - { .offset = 0x90141, .val = 0x8558 }, - { .offset = 0x90142, .val = 0x168 }, - { .offset = 0x90143, .val = 0xf }, - { .offset = 0x90144, .val = 0x408 }, - { .offset = 0x90145, .val = 0x169 }, - { .offset = 0x90146, .val = 0xc }, - { .offset = 0x90147, .val = 0x0 }, - { .offset = 0x90148, .val = 0x68 }, - { .offset = 0x90149, .val = 0x0 }, - { .offset = 0x9014a, .val = 0x408 }, - { .offset = 0x9014b, .val = 0x169 }, - { .offset = 0x9014c, .val = 0x0 }, - { .offset = 0x9014d, .val = 0x8558 }, - { .offset = 0x9014e, .val = 0x168 }, - { .offset = 0x9014f, .val = 0x8 }, - { .offset = 0x90150, .val = 0x3c8 }, - { .offset = 0x90151, .val = 0x1a9 }, - { .offset = 0x90152, .val = 0x3 }, - { .offset = 0x90153, .val = 0x370 }, - { .offset = 0x90154, .val = 0x129 }, - { .offset = 0x90155, .val = 0x20 }, - { .offset = 0x90156, .val = 0x2aa }, - { .offset = 0x90157, .val = 0x9 }, - { .offset = 0x90158, .val = 0x0 }, - { .offset = 0x90159, .val = 0x400 }, - { .offset = 0x9015a, .val = 0x10e }, - { .offset = 0x9015b, .val = 0x8 }, - { .offset = 0x9015c, .val = 0xe8 }, - { .offset = 0x9015d, .val = 0x109 }, - { .offset = 0x9015e, .val = 0x0 }, - { .offset = 0x9015f, .val = 0x8140 }, - { .offset = 0x90160, .val = 0x10c }, - { .offset = 0x90161, .val = 0x10 }, - { .offset = 0x90162, .val = 0x8138 }, - { .offset = 0x90163, .val = 0x10c }, - { .offset = 0x90164, .val = 0x8 }, - { .offset = 0x90165, .val = 0x7c8 }, - { .offset = 0x90166, .val = 0x101 }, - { .offset = 0x90167, .val = 0x8 }, - { .offset = 0x90168, .val = 0x0 }, - { .offset = 0x90169, .val = 0x8 }, - { .offset = 0x9016a, .val = 0x8 }, - { .offset = 0x9016b, .val = 0x448 }, - { .offset = 0x9016c, .val = 0x109 }, - { .offset = 0x9016d, .val = 0xf }, - { .offset = 0x9016e, .val = 0x7c0 }, - { .offset = 0x9016f, .val = 0x109 }, - { .offset = 0x90170, .val = 0x0 }, - { .offset = 0x90171, .val = 0xe8 }, - { .offset = 0x90172, .val = 0x109 }, - { .offset = 0x90173, .val = 0x47 }, - { .offset = 0x90174, .val = 0x630 }, - { .offset = 0x90175, .val = 0x109 }, - { .offset = 0x90176, .val = 0x8 }, - { .offset = 0x90177, .val = 0x618 }, - { .offset = 0x90178, .val = 0x109 }, - { .offset = 0x90179, .val = 0x8 }, - { .offset = 0x9017a, .val = 0xe0 }, - { .offset = 0x9017b, .val = 0x109 }, - { .offset = 0x9017c, .val = 0x0 }, - { .offset = 0x9017d, .val = 0x7c8 }, - { .offset = 0x9017e, .val = 0x109 }, - { .offset = 0x9017f, .val = 0x8 }, - { .offset = 0x90180, .val = 0x8140 }, - { .offset = 0x90181, .val = 0x10c }, - { .offset = 0x90182, .val = 0x0 }, - { .offset = 0x90183, .val = 0x1 }, - { .offset = 0x90184, .val = 0x8 }, - { .offset = 0x90185, .val = 0x8 }, - { .offset = 0x90186, .val = 0x4 }, - { .offset = 0x90187, .val = 0x8 }, - { .offset = 0x90188, .val = 0x8 }, - { .offset = 0x90189, .val = 0x7c8 }, - { .offset = 0x9018a, .val = 0x101 }, - { .offset = 0x90006, .val = 0x0 }, - { .offset = 0x90007, .val = 0x0 }, - { .offset = 0x90008, .val = 0x8 }, - { .offset = 0x90009, .val = 0x0 }, - { .offset = 0x9000a, .val = 0x0 }, - { .offset = 0x9000b, .val = 0x0 }, - { .offset = 0xd00e7, .val = 0x400 }, - { .offset = 0x90017, .val = 0x0 }, - { .offset = 0x9001f, .val = 0x2a }, - { .offset = 0x90026, .val = 0x6a }, - { .offset = 0x400d0, .val = 0x0 }, - { .offset = 0x400d1, .val = 0x101 }, - { .offset = 0x400d2, .val = 0x105 }, - { .offset = 0x400d3, .val = 0x107 }, - { .offset = 0x400d4, .val = 0x10f }, - { .offset = 0x400d5, .val = 0x202 }, - { .offset = 0x400d6, .val = 0x20a }, - { .offset = 0x400d7, .val = 0x20b }, - { .offset = 0x2003a, .val = 0x2 }, - { .offset = 0x9000c, .val = 0x0 }, - { .offset = 0x9000d, .val = 0x173 }, - { .offset = 0x9000e, .val = 0x60 }, - { .offset = 0x9000f, .val = 0x6110 }, - { .offset = 0x90010, .val = 0x2152 }, - { .offset = 0x90011, .val = 0xdfbd }, - { .offset = 0x90012, .val = 0x60 }, - { .offset = 0x90013, .val = 0x6152 }, - { .offset = 0x20010, .val = 0x5a }, - { .offset = 0x20011, .val = 0x3 }, - { .offset = 0x40080, .val = 0xe0 }, - { .offset = 0x40081, .val = 0x12 }, - { .offset = 0x40082, .val = 0xe0 }, - { .offset = 0x40083, .val = 0x12 }, - { .offset = 0x40084, .val = 0xe0 }, - { .offset = 0x40085, .val = 0x12 }, - { .offset = 0x400fd, .val = 0xf }, - { .offset = 0x10011, .val = 0x1 }, - { .offset = 0x10012, .val = 0x1 }, - { .offset = 0x10013, .val = 0x180 }, - { .offset = 0x10018, .val = 0x1 }, - { .offset = 0x10002, .val = 0x6209 }, - { .offset = 0x100b2, .val = 0x1 }, - { .offset = 0x101b4, .val = 0x1 }, - { .offset = 0x102b4, .val = 0x1 }, - { .offset = 0x103b4, .val = 0x1 }, - { .offset = 0x104b4, .val = 0x1 }, - { .offset = 0x105b4, .val = 0x1 }, - { .offset = 0x106b4, .val = 0x1 }, - { .offset = 0x107b4, .val = 0x1 }, - { .offset = 0x108b4, .val = 0x1 }, - { .offset = 0x11011, .val = 0x1 }, - { .offset = 0x11012, .val = 0x1 }, - { .offset = 0x11013, .val = 0x180 }, - { .offset = 0x11018, .val = 0x1 }, - { .offset = 0x11002, .val = 0x6209 }, - { .offset = 0x110b2, .val = 0x1 }, - { .offset = 0x111b4, .val = 0x1 }, - { .offset = 0x112b4, .val = 0x1 }, - { .offset = 0x113b4, .val = 0x1 }, - { .offset = 0x114b4, .val = 0x1 }, - { .offset = 0x115b4, .val = 0x1 }, - { .offset = 0x116b4, .val = 0x1 }, - { .offset = 0x117b4, .val = 0x1 }, - { .offset = 0x118b4, .val = 0x1 }, - { .offset = 0x12011, .val = 0x1 }, - { .offset = 0x12012, .val = 0x1 }, - { .offset = 0x12013, .val = 0x180 }, - { .offset = 0x12018, .val = 0x1 }, - { .offset = 0x12002, .val = 0x6209 }, - { .offset = 0x120b2, .val = 0x1 }, - { .offset = 0x121b4, .val = 0x1 }, - { .offset = 0x122b4, .val = 0x1 }, - { .offset = 0x123b4, .val = 0x1 }, - { .offset = 0x124b4, .val = 0x1 }, - { .offset = 0x125b4, .val = 0x1 }, - { .offset = 0x126b4, .val = 0x1 }, - { .offset = 0x127b4, .val = 0x1 }, - { .offset = 0x128b4, .val = 0x1 }, - { .offset = 0x13011, .val = 0x1 }, - { .offset = 0x13012, .val = 0x1 }, - { .offset = 0x13013, .val = 0x180 }, - { .offset = 0x13018, .val = 0x1 }, - { .offset = 0x13002, .val = 0x6209 }, - { .offset = 0x130b2, .val = 0x1 }, - { .offset = 0x131b4, .val = 0x1 }, - { .offset = 0x132b4, .val = 0x1 }, - { .offset = 0x133b4, .val = 0x1 }, - { .offset = 0x134b4, .val = 0x1 }, - { .offset = 0x135b4, .val = 0x1 }, - { .offset = 0x136b4, .val = 0x1 }, - { .offset = 0x137b4, .val = 0x1 }, - { .offset = 0x138b4, .val = 0x1 }, - { .offset = 0x2003a, .val = 0x2 }, - { .offset = 0xc0080, .val = 0x2 }, - { .offset = 0xd0000, .val = 0x1 }, -}; - -static bool trained_csr_saved = false; - -/* save the necessary trained CSRs before IO retention */ -static void save_trained_csr(void) -{ - int index, offset, size; - - size = sizeof(lpddr4_saved_trained_csr) / 8; - - dwc_ddrphy_apb_wr(0xd0000, 0x0); - dwc_ddrphy_apb_wr(0xc0080, 0x3); - - for (index = 0; index < size; index++) { - offset = lpddr4_saved_trained_csr[index].offset; - lpddr4_saved_trained_csr[index].val = dwc_ddrphy_apb_rd(offset); - } - - dwc_ddrphy_apb_wr(0xc0080, 0x0); - dwc_ddrphy_apb_wr(0xd0000, 0x1); -} - -/* restore the trained CSRs before exit IO retention */ -static void restore_trained_csr(void) -{ - int index, offset, val, size; - - size = sizeof(lpddr4_saved_trained_csr) / 8; - - for(index = 0; index < size; index++) { - val = lpddr4_saved_trained_csr[index].val; - offset = lpddr4_saved_trained_csr[index].offset; - - dwc_ddrphy_apb_wr(offset, val); - } -} - -static void phy_cfg_before_csr_restore(void) -{ - int index, offset, val, size; - - size = sizeof(data_before_restore) / 8; - - for(index = 0; index < size; index++) { - val = data_before_restore[index].val; - offset = data_before_restore[index].offset; - - dwc_ddrphy_apb_wr(offset, val); - } - -} - -static void phy_cfg_after_csr_restore(void) -{ - int index, offset, val, size; - - size = sizeof(data_after_restore) / 8; - - for(index = 0; index < size; index++) { - val = data_after_restore[index].val; - offset = data_after_restore[index].offset; - - dwc_ddrphy_apb_wr(offset, val); - } -} - -void lpddr4_cfg_umctl2(void) -{ - mmio_write_32(IMX_DDRC_BASE + 0x00000304, 0x00000001); - mmio_write_32(IMX_DDRC_BASE + 0x00000030, 0x00000001); - mmio_write_32(IMX_DDRC_BASE + 0x00000000, 0x83080020); - mmio_write_32(IMX_DDRC_BASE + 0x00000064, 0x006180e0); - mmio_write_32(IMX_DDRC_BASE + 0x000000d0, 0xc003061B); - mmio_write_32(IMX_DDRC_BASE + 0x000000d4, 0x009D0000); - mmio_write_32(IMX_DDRC_BASE + 0x000000d8, 0x0000fe05); - mmio_write_32(IMX_DDRC_BASE + 0x000000dc, 0x00d4002d); - mmio_write_32(IMX_DDRC_BASE + 0x000000e0, 0x00310008); - mmio_write_32(IMX_DDRC_BASE + 0x000000e4, 0x00040009); - mmio_write_32(IMX_DDRC_BASE + 0x000000e8, 0x0046004d); - mmio_write_32(IMX_DDRC_BASE + 0x000000ec, 0x0005004d); - mmio_write_32(IMX_DDRC_BASE + 0x000000f4, 0x00000979); - mmio_write_32(IMX_DDRC_BASE + 0x00000100, 0x1a203522); - mmio_write_32(IMX_DDRC_BASE + 0x00000104, 0x00060630); - mmio_write_32(IMX_DDRC_BASE + 0x00000108, 0x070e1214); - mmio_write_32(IMX_DDRC_BASE + 0x0000010c, 0x00b0c006); - mmio_write_32(IMX_DDRC_BASE + 0x00000110, 0x0f04080f); - mmio_write_32(IMX_DDRC_BASE + 0x00000114, 0x0d0d0c0c); - mmio_write_32(IMX_DDRC_BASE + 0x00000118, 0x01010007); - mmio_write_32(IMX_DDRC_BASE + 0x0000011c, 0x0000060a); - mmio_write_32(IMX_DDRC_BASE + 0x00000120, 0x01010101); - mmio_write_32(IMX_DDRC_BASE + 0x00000124, 0x40000008); - mmio_write_32(IMX_DDRC_BASE + 0x00000128, 0x00050d01); - mmio_write_32(IMX_DDRC_BASE + 0x0000012c, 0x01010008); - mmio_write_32(IMX_DDRC_BASE + 0x00000130, 0x00020000); - mmio_write_32(IMX_DDRC_BASE + 0x00000134, 0x18100002); - mmio_write_32(IMX_DDRC_BASE + 0x00000138, 0x00000dc2); - mmio_write_32(IMX_DDRC_BASE + 0x0000013c, 0x80000000); - mmio_write_32(IMX_DDRC_BASE + 0x00000144, 0x00a00050); - mmio_write_32(IMX_DDRC_BASE + 0x00000180, 0x53200018); - mmio_write_32(IMX_DDRC_BASE + 0x00000184, 0x02800070); - mmio_write_32(IMX_DDRC_BASE + 0x00000188, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + 0x00000190, 0x0397820a); - mmio_write_32(IMX_DDRC_BASE + 0x00002190, 0x0397820a); - mmio_write_32(IMX_DDRC_BASE + 0x00003190, 0x0397820a); - mmio_write_32(IMX_DDRC_BASE + 0x00000194, 0x00020103); - mmio_write_32(IMX_DDRC_BASE + 0x000001a0, 0xe0400018); - mmio_write_32(IMX_DDRC_BASE + 0x000001a4, 0x00df00e4); - mmio_write_32(IMX_DDRC_BASE + 0x000001a8, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + 0x000001b0, 0x00000011); - mmio_write_32(IMX_DDRC_BASE + 0x000001b4, 0x0000170a); - mmio_write_32(IMX_DDRC_BASE + 0x000001c0, 0x00000001); - mmio_write_32(IMX_DDRC_BASE + 0x000001c4, 0x00000000); - - /* DDRC freq P1 config */ - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG0, 0x0d0b010c); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG1, 0x00030410); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG2, 0x0305090c); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG3, 0x00505006); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG4, 0x05040305); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG5, 0x0d0e0504); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG6, 0x0a060004); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG7, 0x0000090e); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG14, 0x00000032); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG15, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DRAMTMG17, 0x0036001b); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DERATEINT, 0x7e9fbeb1); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_RFSHCTL0, 0x0020d040); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DFITMG0, 0x03818200); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_ODTCFG, 0x0a1a096c); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DFITMG2, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_RFSHTMG, 0x00038014); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_INIT3, 0x00840000); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_INIT6, 0x0000004d); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_INIT7, 0x0000004d); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_INIT4, 0x00310000); - - /* DDRC freq P2 config */ - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG0, 0x0d0b010c); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG1, 0x00030410); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG2, 0x0305090c); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG3, 0x00505006); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG4, 0x05040305); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG5, 0x0d0e0504); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG6, 0x0a060004); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG7, 0x0000090e); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG14, 0x00000032); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG15, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DRAMTMG17, 0x0036001b); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DERATEINT, 0x7e9fbeb1); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_RFSHCTL0, 0x0020d040); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DFITMG0, 0x03818200); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_ODTCFG, 0x0a1a096c); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_DFITMG2, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_RFSHTMG, 0x0003800c); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_INIT3, 0x00840000); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_INIT6, 0x0000004d); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_INIT7, 0x0000004d); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ2_INIT4, 0x00310000); - - /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ - mmio_write_32(IMX_DDRC_BASE + DDRC_ADDRMAP0, 0x00000015); - mmio_write_32(IMX_DDRC_BASE + DDRC_ADDRMAP4, 0x00001F1F); - /* bank interleave */ - mmio_write_32(IMX_DDRC_BASE + DDRC_ADDRMAP1, 0x00080808); - mmio_write_32(IMX_DDRC_BASE + DDRC_ADDRMAP5, 0x07070707); - mmio_write_32(IMX_DDRC_BASE + DDRC_ADDRMAP6, 0x08080707); - mmio_write_32(IMX_DDRC_BASE + 0x00000240, 0x020f0c54); - mmio_write_32(IMX_DDRC_BASE + 0x00000244, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + 0x00000490, 0x00000001); - - /* performance setting */ - mmio_write_32(IMX_DDRC_BASE + DDRC_ODTCFG, 0x0b060908); - mmio_write_32(IMX_DDRC_BASE + DDRC_ODTMAP, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + DDRC_SCHED, 0x29511505); - mmio_write_32(IMX_DDRC_BASE + DDRC_SCHED1, 0x0000002c); - mmio_write_32(IMX_DDRC_BASE + DDRC_PERFHPR1, 0x5900575b); - mmio_write_32(IMX_DDRC_BASE + DDRC_PERFLPR1, 0x00000009); - mmio_write_32(IMX_DDRC_BASE + DDRC_PERFWR1, 0x02005574); - mmio_write_32(IMX_DDRC_BASE + DDRC_DBG0, 0x00000016); - mmio_write_32(IMX_DDRC_BASE + DDRC_DBG1, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + DDRC_DBGCMD, 0x00000000); - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x00000001); - mmio_write_32(IMX_DDRC_BASE + DDRC_POISONCFG, 0x00000011); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCCFG, 0x00000111); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCFGR_0, 0x000010f3); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCFGW_0, 0x000072ff); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCTRL_0, 0x00000001); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCFGQOS0_0, 0x01110d00); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCFGQOS1_0, 0x00620790); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCFGWQOS0_0, 0x00100001); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCFGWQOS1_0, 0x0000041f); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DERATEEN, 0x00000202); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_DERATEINT, 0xec78f4b5); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_RFSHCTL0, 0x00618040); - mmio_write_32(IMX_DDRC_BASE + DDRC_FREQ1_RFSHTMG, 0x00610090); -} - -void lpddr4_cfg_phy(void) -{ - /* phy init config before restore the trained CSR */ - phy_cfg_before_csr_restore(); - /* restore the trained CSR, no need to do re-training */ - restore_trained_csr(); - /* load the PIE */ - phy_cfg_after_csr_restore(); -} - -void ddrc_enter_retention(void) -{ - INFO("enter LPDDR4 retention\n"); - - /* save the ddr phy trained csr in ocram */ - if (!trained_csr_saved) { - save_trained_csr(); - trained_csr_saved = true; - } - - /* wait DBGCAM to be empty */ - while (mmio_read_32(IMX_DDRC_BASE + 0x308) != 0x36000000) - ; - /* Block AXI port for any transaction */ - mmio_write_32(IMX_DDRC_BASE + DDRC_PCTRL_0, 0x0); - /* wait for AXI port is idle */ - while (mmio_read_32(IMX_DDRC_BASE + 0x3fc) & 0x10001) - ; - /* enter self refresh */ - mmio_write_32(IMX_DDRC_BASE + DDRC_PWRCTL, 0xaa); - /* wait for STAT refresh type = Self Refresh */ - while ((mmio_read_32(IMX_DDRC_BASE + DDRC_STAT) & 0x33f) != 0x223) - ; - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x00000000); - /* set SWCTL.sw_done to disable quasi-dynamic register programming outside reset */ - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x00000000); - - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x00001f00); - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x00001f20); - - /* wait DFISTAT.dfi_init_complete to 0 */ - while((mmio_read_32(IMX_DDRC_BASE + DDRC_DFISTAT) & 0x1) == 0x1) - ; - - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x00001f00); - - /* wait DFISTAT.dfi_init_complete to 1 */ - while(!(mmio_read_32(IMX_DDRC_BASE + DDRC_DFISTAT) & 0x1)) - ; - - /* set the SWCTL done to enable quasi-dynamic register programming outside reset */ - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x00000001); - - /* - * Transition the PHY to LP3/IO retention state by using a DFI - * frequency operation. - */ - mmio_write_32(0x3c000000 + 4 * 0xd0000, 0x0); - mmio_write_32(0x3c000000 + 4 * 0xd0000, 0x1); - - /* loop for a while */ - for (int i; i < 20; i++); - - /* pwrdnreq_async adbm/adbs of ddr */ - mmio_write_32(0x303a01fc, mmio_read_32(0x303a01fc) & ~(0x2)); - while (mmio_read_32(0x303a01fc) & (1 << 18)); - - /* set the PwrOkIn signal to 0, this will enable the data retention feature on - * the CKE and MEMRESET */ - mmio_write_32(0x30391000, 0x8f000008); - - /* loop for a while */ - for (int i; i < 20; i++); - - /* set CCM CCGR */ - mmio_write_32(0x30384050, 0x0); - mmio_write_32(0x30380950, 0x2); - - /* enable ISO */ - mmio_write_32(0x303a0d40, 0x1); - mmio_write_32(0x303a0104, (1 << 5)); - - /* - * turn off the core VDD and VAA supplies, these supply can be turned - * off in any order, the VDDQ power supply must be active during LP3/IO - * retention. - */ -} - -void ddrc_exit_retention(void) -{ - int i; - - INFO("exit LPDDR4 retention\n"); - - for(i = 0; i < 50; i++); - - /* start the clock and reset the PHY */ - /* assert all reset */ - mmio_write_32(0x30391000 + 0x4, 0x8f000001); - mmio_write_32(0x30391000, 0x8f00000f); - - mmio_write_32(0x30384050, 0x2); - mmio_write_32(0x30380950, 0x2); - - /* power up the DDRMIX */ - mmio_write_32(0x303a00f8, (1 << 5)); - /* wait for DDRMIX is power up suscessfully */ - while (mmio_read_32(0x303a0104) & ( 1 << 5)) - ; - - mmio_write_32(0x303a01fc, mmio_read_32(0x303a01fc) | 0x2); - - mmio_write_32(0x30360060, 0x80000208); - - /* release the src_system_rst_b */ - mmio_write_32(0x30391004, 0x8f000000); - mmio_write_32(0x30391000, 0x8f000006); - - /* short delay */ - for (int i = 0; i < 500; i++); - - /* config umctl2 */ - lpddr4_cfg_umctl2(); - - /* Skip the DRAM init routine and starts up in self-refresh mode */ - /* Program INIT0.skip_dram_init = 2b'11 */ - mmio_write_32(IMX_DDRC_BASE + DDRC_INIT0, 0xc0000000 | mmio_read_32(IMX_DDRC_BASE + DDRC_INIT0)); - - /* keep the controller in self-refresh mode */ - mmio_write_32(IMX_DDRC_BASE + DDRC_PWRCTL, 0x000000aa); - - /* release all reset */ - mmio_write_32(0x30391000, 0x8f000000); - - /* loop for a while */ - for (int i; i < 500; i++); - - mmio_write_32(IMX_DDRC_BASE + DDRC_DBG1, 0x0); - - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x0); - - /* LPDDR4 mode */ - mmio_write_32(0x3d000000, 0x1); - - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x0); - - lpddr4_cfg_phy(); - - mmio_write_32(0x3c000000 + 4 * 0xd0000, 0x0); - while (mmio_read_32(0x3c000000 + 4 * 0x20097)) - ; - /* set the MicroContMuxSel to 1 */ - mmio_write_32(0x3c000000 + 4 * 0xd0000, 0x1); - - /* before write Dynamic reg, sw_done should be 0 */ - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x0); - /* trigger the PHY init start request */ - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x20); - - /* wait for dfi_init_complete done */ - while (!(mmio_read_32(IMX_DDRC_BASE + DDRC_DFISTAT) & 0x1)) - ; - /* clear DFIMISC.dfi_init_start */ - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x0); - /* set the DFIMISC.dfi_init_complete_en */ - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x1); - - /* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset */ - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x1); - /* wait for SWSTAT.sw_done_ack to 1 */ - while((mmio_read_32(IMX_DDRC_BASE + DDRC_SWSTAT) & 0x1) != 0x1) - ; - - mmio_write_32(IMX_DDRC_BASE + DDRC_PWRCTL, 0xaa); - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x0); - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x1); - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x1); - - /* wait STAT to normal state */ - while((mmio_read_32(IMX_DDRC_BASE + DDRC_SWSTAT) & 0x1) != 0x1) - ; - - mmio_write_32(IMX_DDRC_BASE + DDRC_PWRCTL, 0x88); - - while((mmio_read_32(IMX_DDRC_BASE + DDRC_STAT) & 0x7) != 0x1) - - mmio_write_32(IMX_DDRC_BASE + DDRC_DERATEEN, 0x302); - mmio_write_32(IMX_DDRC_BASE + DDRC_PCTRL_0, 0x1); - mmio_write_32(IMX_DDRC_BASE + DDRC_RFSHCTL3, 0x0); -} - -void lpddr4_dvfs_hwffc(int init_vrcg, int init_fsp, int target_freq, - int discamdrain) -{ - uint32_t tmp, tmp_t; - - INFO("hwffc enter\n"); - - /* step 1: hwffc flow enter, set the HWFCCCTL */ - tmp = ((init_fsp << 4) & 0x10) | ((init_vrcg << 5) & 0x20) | 0x40; - tmp |= 0x3; - mmio_write_32(IMX_DDRC_BASE + DDRC_HWFFCCTL, tmp); - - /* - * set SWCTL.sw_done to disable quasi-dynamic register programming - * outside reset - */ - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x0); - - mmio_write_32(IMX_DDRC_BASE + DDRC_DFIMISC, 0x11); - - /* - * set SWCTL.sw_done to enable quasi-dynamic register programming - * outside reset. - */ - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x1); - /*wait SWSTAT.sw_done_ack to 1 */ - while (!(mmio_read_32(IMX_DDRC_BASE + DDRC_SWSTAT) & 0x1)) - ; - - /* wait for DBGCAM is empty */ - if (discamdrain) - while ((mmio_read_32(IMX_DDRC_BASE + DDRC_DBGCAM) & - 0x30000000) != 0x30000000) - ; - - /* set HWFFC requirements, ddrc_csysfreqency_ddrc[1:0] = 2b'10; - * [15]: ccmsrcgpcmix_ddrc_csysdisdrain_ddrc; - * [14:13]: ccmsrcgpcmix_ddrc_csysfrequency_ddrc[1:0]; - * [12]: ccmsrcgpcmix_ddrc_csysmode_ddrc; - */ - tmp = mmio_read_32(0x303a0164); - tmp &= 0xFFFF0FFF; - tmp |= ((discamdrain << 15) & 0x8000); - tmp |= ((target_freq << 13) & 0x6000); - tmp |= 0x1000; - mmio_write_32(0x303a0164, tmp); - - /* set the gpc_ddr1_core_csysreq to active low */ - tmp = mmio_read_32(0x303a01fc); - tmp &= 0xfffffffe; - mmio_write_32(0x303a01fc, tmp); - - /* wait gpc_ddr1_core_csysack to active low */ - while ((mmio_read_32(0x303a01fc) & 0x10000)) - ; - - /* step B: switch the clock */ - if (target_freq == 0x1) { - /* change the clock source of dram_alt_clk_root to source 5 --400MHz */ - mmio_write_32(0x3038a008, (0x7 << 24) | (0x7 << 16)); - mmio_write_32(0x303aa004, (0x5 << 24)); - - /* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */ - mmio_write_32(0x3038a088, (0x7 << 24) | (0x7 << 16)); - mmio_write_32(0x3038a084, (0x2 << 24) | (0x1 << 16));; - - /* bypass the DRAM PLL */ - mmio_write_32(0x30389804, 1 << 24); - - } else if (target_freq == 0x2) { - /* change the clock source of dram_alt_clk_root to source 2 --100MHz */ - mmio_write_32(0x3038a008, (0x7 << 24) | (0x7 << 16)); - mmio_write_32(0x3038a004, (0x2 << 24)); - - /* change the clock source of dram_apb_clk_root to source 2 --40Mhz/2 */ - mmio_write_32(0x3038a088, (0x7 << 24) | (0x7 << 16)); - mmio_write_32(0x3038a084, (0x2 << 24) | (0x1 << 16));; - - /* bypass the DRAM PLL */ - mmio_write_32(0x30389804, 1 << 24); - } else { - /* switch to the default freq fsp = 0x1 3200mts */ - mmio_write_32(0x3038a088,(0x7<<24)|(0x7<<16)); - /* to source 4 --800MHz/ 4 */ - mmio_write_32(0x3038a084,(0x4<<24)|(0x3<<16)); - mmio_write_32(0x30389808, 1<<24); - } - - /* step C: exit hwffc flow */ - tmp = mmio_read_32(0x303a01fc); - tmp |= 0x1; - mmio_write_32(0x303a01fc, tmp); - /* wait gpc_ddr1_core_csysack to high */ - while (!(mmio_read_32(0x303a01fc) & 0x10000)) - ; - - /* [1:0]-->2b'10, to disable HWFFC */ - mmio_write_32(IMX_DDRC_BASE + DDRC_HWFFCCTL, 0x72); - - /*wait until hwffc_in_progress = 0 */ - while(mmio_read_32(IMX_DDRC_BASE + DDRC_HWFFCSTAT) & 0x1) - ; - - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x0); - /* set MSTR.frequency_mode MSTR.[29], MSTR2.target_frequency[1:0] */ - tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_MSTR); - tmp |= 0x20000000; - mmio_write_32(IMX_DDRC_BASE + DDRC_MSTR, tmp); - - tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_HWFFCSTAT); - tmp_t = (tmp >> 4) & 0x3; - tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_MSTR2); - tmp = (tmp & 0xfffffffc) | tmp_t; - mmio_write_32(IMX_DDRC_BASE + DDRC_MSTR2, tmp); - - mmio_write_32(IMX_DDRC_BASE + DDRC_SWCTL, 0x1); - mmio_write_32(IMX_DDRC_BASE + DDRC_HWFFCCTL, 0x70); - - /* why we need below flow */ - mmio_write_32(IMX_DDRC_BASE + DDRC_PWRCTL, 0x1a8); - while ((mmio_read_32(IMX_DDRC_BASE + DDRC_STAT) & 0x3) != 0x3) - ; - /* wait SDRAM into self refresh state */ - while(!(mmio_read_32(IMX_DDRC_BASE + DDRC_STAT) & 0x30)) - ; - - tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_CRCPARSTAT); - tmp = mmio_read_32(IMX_DDRC_BASE + DDRC_CRCPARSTAT); - - mmio_write_32(IMX_DDRC_BASE + DDRC_PWRCTL, 0x188); - - /* wait STAT to normal mode */ - while ((mmio_read_32(IMX_DDRC_BASE + DDRC_STAT) & 0x3) != 0x1) - ; - - INFO("hwffc exit\n"); -} - -spinlock_t dfs_lock; -static unsigned int init_fsp = 0x1; -static unsigned int init_vrcg = 0x1; -static unsigned int discamdrain = 0x1; - -static uint32_t irqs_used [] = {102, 109, 110, 111}; -static volatile uint32_t wfe_done; -static volatile bool wait_ddrc_hwffc_done = true; - -/* - * x1 for frequency setpoint info; - * x2 is used for online cpu info - */ -int lpddr4_dvfs_handler(uint32_t smc_fid, - u_register_t x1, - u_register_t x2, - u_register_t x3) -{ - uint64_t mpidr = read_mpidr_el1(); - unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); - unsigned int target_freq = x1; - uint32_t online_cores = x2; - - if (target_freq == 0xf) { - /* set the WFE done status */ - spin_lock(&dfs_lock); - wfe_done |= (1 << cpu_id * 8); - spin_unlock(&dfs_lock); - - while (1) { - /* ddr frequency change done */ - wfe(); - if (!wait_ddrc_hwffc_done) { - break; - } - } - } else { - wait_ddrc_hwffc_done = true; - /* trigger the IRQ */ - for (int i = 0; i < 4; i++) { - int irq = irqs_used[i] % 32; - if (cpu_id != i && (online_cores & (0x1 << (i * 8)))) { - mmio_write_32(0x38800204 + (irqs_used[i] / 32) * 4, (1 << irq)); - mmio_write_32(0x303a0040, mmio_read_32(0x303a0040) & ~(0x1)); - } - } - - /* make sure all the core in WFE */ - online_cores &= ~(0x1 << (cpu_id * 8)); - while (1) { - mmio_write_32(0x30340004, mmio_read_32(0x30340004) | (1 << 12)); - if (online_cores == wfe_done) - break; - } - - mmio_write_32(0x30340004, mmio_read_32(0x30340004) & ~(1 << 12)); - - /* flush the L1/L2 cache */ - dcsw_op_all(DCCSW); - - lpddr4_dvfs_hwffc(init_vrcg, init_fsp, target_freq, discamdrain); - init_fsp = (~init_fsp) & 0x1; - wait_ddrc_hwffc_done = false; - wfe_done = 0; - dsb(); - sev(); - isb(); - } - return 0; -} diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c index 98f25816..be5ae284 100644 --- a/plat/imx/imx8mq/imx8m_bl31_setup.c +++ b/plat/imx/imx8mq/imx8m_bl31_setup.c @@ -300,6 +300,9 @@ void bl31_platform_setup(void) /* gpc init */ imx_gpc_init(); + + /* switch DDR frequency to 3200 mts */ + lpddr4_switch_to_3200(); } entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) diff --git a/plat/imx/imx8mq/include/ddrc.h b/plat/imx/imx8mq/include/ddrc.h index 8f3db1b3..8eb42fd8 100644 --- a/plat/imx/imx8mq/include/ddrc.h +++ b/plat/imx/imx8mq/include/ddrc.h @@ -1,150 +1,301 @@ #ifndef __IMX_DDRC_H #define __IMX_DDRC_H +#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + (X * 0x2000000)) +#define DDRC_DDR_SS_GPR0 0x3d000000 + /* DWC ddr umctl2 REGs offset*/ -#define DDRC_MSTR 0x0 -#define DDRC_STAT 0x4 -#define DDRC_MSTR1 0x8 -#define DDRC_MRCTRL0 0x10 -#define DDRC_MRCTRL1 0x14 -#define DDRC_MRSTAT 0x18 -#define DDRC_MRCTRL2 0x1c -#define DDRC_DERATEEN 0x20 -#define DDRC_DERATEINT 0x24 -#define DDRC_MSTR2 0x28 -#define DDRC_PWRCTL 0x30 -#define DDRC_PWRTMG 0x34 -#define DDRC_HWLPCTL 0x38 -#define DDRC_HWFFCCTL 0x3c -#define DDRC_HWFFCSTAT 0x40 -#define DDRC_RFSHCTL0 0x50 -#define DDRC_RFSHCTL1 0x54 -#define DDRC_RFSHCTL2 0x58 -#define DDRC_RFSHCTL4 0x5c -#define DDRC_RFSHCTL3 0x60 -#define DDRC_RFSHTMG 0x64 -#define DDRC_RFSHTMG1 0x68 +/**********************/ +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) +#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) +#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) +#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) +#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) +#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) +#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) +#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) +#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) +#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) +#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) +#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) +#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) +#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) +#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) +#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) +#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) +#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) +#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) +#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) +#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) +#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) +#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) +#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) +#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) +#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) +#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) +#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) +#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) +#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) +#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) +#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) +#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) +#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) +#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) +#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) +#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) +#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) +#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) +#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) +#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) +#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) +#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) +#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) +#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) +#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) +#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) +#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) +#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) +#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) +#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) +#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) +#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) +#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) +#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) +#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) +#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) +#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) +#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) +#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) +#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) +#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) +#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) +#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) +#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) +#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) +#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) +#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) +#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) +#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) + +#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) +#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) +#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) +#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) +#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) +#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) +#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) +#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) +#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) +#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) +#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) +#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) +#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) +#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) +#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) + +#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) +#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) +#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) +#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) +#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) +#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) +#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) +#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) +#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) +#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) +#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) +#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) +#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) +#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) +#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) +#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) +#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) +#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) + +#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) +#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) +#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) +#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) +#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) +#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) +#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) +#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) + +#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) + +#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) +#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) +#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) +#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) +#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) +#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) +#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) +#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) +#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) +#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) +#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) + +#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) +#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) +#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) +#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) +#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) +#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) +#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) +#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) +#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) +#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) +#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) +#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) +#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) +#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) +#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) +#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) +#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) +#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) +#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) +#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) +#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) -#define DDRC_INIT0 0xd0 -#define DDRC_INIT1 0xd4 -#define DDRC_INIT2 0xd8 -#define DDRC_INIT3 0xdc -#define DDRC_INIT4 0xe0 -#define DDRC_INIT5 0xe4 -#define DDRC_INIT6 0xe8 -#define DDRC_INIT7 0xec -#define DDRC_DIMMCTL 0xf0 -#define DDRC_RANKCTL 0xf4 -#define DDRC_CHCTL 0xfc +#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) +#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) +#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) +#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) +#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) +#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) +#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) +#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) +#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) +#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) +#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) +#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) +#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) +#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) +#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) +#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) +#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) +#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) +#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) +#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) +#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) +#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) +#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) +#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) +#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) +#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) +#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) +#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) -#define DDRC_CRCPARSTAT 0xcc -#define DDRC_DFIMISC 0x1b0 -#define DDRC_DFISTAT 0x1bc -#define DDRC_ADDRMAP0 0x200 -#define DDRC_ADDRMAP1 0x204 -#define DDRC_ADDRMAP2 0x208 -#define DDRC_ADDRMAP3 0x20c -#define DDRC_ADDRMAP4 0x210 -#define DDRC_ADDRMAP5 0x214 -#define DDRC_ADDRMAP6 0x218 -#define DDRC_ADDRMAP7 0x21c -#define DDRC_ADDRMAP8 0x220 -#define DDRC_ADDRMAP9 0x224 -#define DDRC_ADDRMAP10 0x228 -#define DDRC_ADDRMAP11 0x22c -#define DDRC_ODTCFG 0x240 -#define DDRC_ODTMAP 0x244 -#define DDRC_SCHED 0x250 -#define DDRC_SCHED1 0x254 -#define DDRC_SCHED2 0x258 -#define DDRC_PERFHPR1 0x25c -#define DDRC_PERFLPR1 0x264 -#define DDRC_PERFWR1 0x26c -#define DDRC_DBG0 0x300 -#define DDRC_DBG1 0x304 -#define DDRC_DBGCAM 0x308 -#define DDRC_DBGCMD 0x30c -#define DDRC_DBGSTAT 0x310 -#define DDRC_SWCTL 0x320 -#define DDRC_SWSTAT 0x324 -#define DDRC_POISONCFG 0x36c -#define DDRC_POISONSTAT 0x370 +/* SHADOW registers */ +#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) +#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) +#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) +#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) +#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) +#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) +#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) +#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) +#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) +#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) +#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) +#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) +#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) +#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) +#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) +#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) +#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) +#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) +#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) +#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) +#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) +#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) +#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) +#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) +#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) +#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) +#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) +#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) -#define DDRC_PCCFG 0x400 -#define DDRC_PCFGR_0 0x404 -#define DDRC_PCFGW_0 0x408 -#define DDRC_PCTRL_0 0x490 -#define DDRC_PCFGQOS0_0 0x494 -#define DDRC_PCFGQOS1_0 0x498 -#define DDRC_PCFGWQOS0_0 0x49c -#define DDRC_PCFGWQOS1_0 0x4a0 +#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) +#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) +#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) +#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) +#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) +#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) +#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) +#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) +#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) +#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) +#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) +#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) +#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) +#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) +#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) +#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) +#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) +#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) +#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) +#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) +#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) +#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) +#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) +#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) +#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) +#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) +#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) +#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) +#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) +#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) +#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) +#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) -/* shadow register */ -#define DDRC_FREQ1_DERATEEN 0x2020 -#define DDRC_FREQ1_DERATEINT 0x2024 -#define DDRC_FREQ1_RFSHCTL0 0x2050 -#define DDRC_FREQ1_RFSHTMG 0x2064 -#define DDRC_FREQ1_INIT3 0x20dc -#define DDRC_FREQ1_INIT4 0x20e0 -#define DDRC_FREQ1_INIT6 0x20e8 -#define DDRC_FREQ1_INIT7 0x20ec -#define DDRC_FREQ1_DRAMTMG0 0x2100 -#define DDRC_FREQ1_DRAMTMG1 0x2104 -#define DDRC_FREQ1_DRAMTMG2 0x2108 -#define DDRC_FREQ1_DRAMTMG3 0x210c -#define DDRC_FREQ1_DRAMTMG4 0x2110 -#define DDRC_FREQ1_DRAMTMG5 0x2114 -#define DDRC_FREQ1_DRAMTMG6 0x2118 -#define DDRC_FREQ1_DRAMTMG7 0x211c -#define DDRC_FREQ1_DRAMTMG8 0x2120 -#define DDRC_FREQ1_DRAMTMG9 0x2124 -#define DDRC_FREQ1_DRAMTMG10 0x2128 -#define DDRC_FREQ1_DRAMTMG11 0x212c -#define DDRC_FREQ1_DRAMTMG12 0x2130 -#define DDRC_FREQ1_DRAMTMG13 0x2134 -#define DDRC_FREQ1_DRAMTMG14 0x2138 -#define DDRC_FREQ1_DRAMTMG15 0x213C -#define DDRC_FREQ1_DRAMTMG16 0x2140 -#define DDRC_FREQ1_DRAMTMG17 0x2144 -#define DDRC_FREQ1_ZQCTL0 0x2180 -#define DDRC_FREQ1_DFITMG0 0x2190 -#define DDRC_FREQ1_DFITMG1 0x2194 -#define DDRC_FREQ1_DFITMG2 0x21b4 -#define DDRC_FREQ1_DFITMG3 0x21b8 -#define DDRC_FREQ1_ODTCFG 0x2240 +#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) +#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) +#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) +#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) +#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) +#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) +#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) +#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) +#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) +#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) +#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) +#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) +#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) +#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) +#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) +#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) +#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) +#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) +#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) +#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) +#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) +#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) +#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) +#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) +#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) -#define DDRC_FREQ2_DERATEEN 0x3020 -#define DDRC_FREQ2_DERATEINT 0x3024 -#define DDRC_FREQ2_RFSHCTL0 0x3050 -#define DDRC_FREQ2_RFSHTMG 0x3064 -#define DDRC_FREQ2_INIT3 0x30dc -#define DDRC_FREQ2_INIT4 0x30e0 -#define DDRC_FREQ2_INIT6 0x30e8 -#define DDRC_FREQ2_INIT7 0x30ec -#define DDRC_FREQ2_DRAMTMG0 0x3100 -#define DDRC_FREQ2_DRAMTMG1 0x3104 -#define DDRC_FREQ2_DRAMTMG2 0x3108 -#define DDRC_FREQ2_DRAMTMG3 0x310c -#define DDRC_FREQ2_DRAMTMG4 0x3110 -#define DDRC_FREQ2_DRAMTMG5 0x3114 -#define DDRC_FREQ2_DRAMTMG6 0x3118 -#define DDRC_FREQ2_DRAMTMG7 0x311c -#define DDRC_FREQ2_DRAMTMG8 0x3120 -#define DDRC_FREQ2_DRAMTMG9 0x3124 -#define DDRC_FREQ2_DRAMTMG10 0x3128 -#define DDRC_FREQ2_DRAMTMG11 0x312c -#define DDRC_FREQ2_DRAMTMG12 0x3130 -#define DDRC_FREQ2_DRAMTMG13 0x3134 -#define DDRC_FREQ2_DRAMTMG14 0x3138 -#define DDRC_FREQ2_DRAMTMG15 0x313C -#define DDRC_FREQ2_DRAMTMG16 0x3140 -#define DDRC_FREQ2_DRAMTMG17 0x3144 -#define DDRC_FREQ2_ZQCTL0 0x3180 -#define DDRC_FREQ2_DFITMG0 0x3190 -#define DDRC_FREQ2_DFITMG1 0x3194 -#define DDRC_FREQ2_DFITMG2 0x31b4 -#define DDRC_FREQ2_DFITMG3 0x31b8 -#define DDRC_FREQ2_ODTCFG 0x3240 +#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) +#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) +#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) +#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) +#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) +#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) #define dwc_ddrphy_apb_rd(addr) mmio_read_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) diff --git a/plat/imx/imx8mq/include/platform_def.h b/plat/imx/imx8mq/include/platform_def.h index 3bebf332..117e9015 100644 --- a/plat/imx/imx8mq/include/platform_def.h +++ b/plat/imx/imx8mq/include/platform_def.h @@ -51,6 +51,7 @@ #define IMX_AIPS1_BASE 0x30200000 #define IMX_AIPS3_ARB_BASE 0x30800000 #define IMX_ANAMIX_BASE 0x30360000 +#define IMX_CCM_BASE 0x30380000 #define IMX_SRC_BASE 0x30390000 #define IMX_GPC_BASE 0x303a0000 #define IMX_RDC_BASE 0x303d0000 diff --git a/plat/imx/imx8mq/include/soc.h b/plat/imx/imx8mq/include/soc.h index d2d3b270..0c55a9c7 100644 --- a/plat/imx/imx8mq/include/soc.h +++ b/plat/imx/imx8mq/include/soc.h @@ -23,6 +23,10 @@ void imx_set_sys_lpm(bool retention); void imx_set_rbc_count(void); void imx_clear_rbc_count(void); +void lpddr4_cfg_umctl2(void); +void lpddr4_phy_cfg(void); +void lpddr4_phy_save_trained_csr(void); +void lpddr4_switch_to_3200(void); void ddrc_enter_retention(void); void ddrc_exit_retention(void); diff --git a/plat/imx/imx8mq/platform.mk b/plat/imx/imx8mq/platform.mk index e711ea7c..d4ed50e1 100644 --- a/plat/imx/imx8mq/platform.mk +++ b/plat/imx/imx8mq/platform.mk @@ -7,6 +7,12 @@ PLAT_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \ plat/common/plat_gicv3.c \ plat/imx/common/plat_imx8_gic.c +PLAT_DDR_SOURCES := plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c \ + plat/imx/imx8mq/ddr/lpddr4_phy_cfg.c \ + plat/imx/imx8mq/ddr/lpddr4_dvfs.c \ + plat/imx/imx8mq/ddr/lpddr4_swffc.c \ + plat/imx/imx8mq/ddr/lpddr4_retention.c + BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/common/mxcuart_console.S \ plat/imx/common/sip_svc.c \ @@ -14,7 +20,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/imx8mq/src.c \ plat/imx/imx8mq/hab.c \ plat/imx/imx8mq/gpc.c \ - plat/imx/imx8mq/ddrc.c \ plat/imx/imx8mq/imx8m_psci.c \ plat/imx/imx8mq/imx_csu.c \ plat/imx/imx8mq/imx_rdc.c \ @@ -25,6 +30,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ lib/cpus/aarch64/cortex_a53.S \ drivers/console/aarch64/console.S \ ${PLAT_GIC_SOURCES} \ + ${PLAT_DDR_SOURCES} \ drivers/arm/tzc/tzc380.c ENABLE_PLAT_COMPAT := 0 |