diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-06-07 18:29:29 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:33:03 +0300 |
| commit | ee094d86280c0e3d899d973db24b4b9b563944da (patch) | |
| tree | 9d22b02273f041e492eda91d7bf2a6004cd5ce8b | |
| parent | 7f83fd077208220c57a389871abb987d371ca50c (diff) | |
plat: imx8mm: enable PU domains' clocks before power up
VPU, GPU and PCIE's clock need to be on before power on
these power domains.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
| -rw-r--r-- | plat/imx/imx8mm/gpc.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c index 3a1242dd..b2d00378 100644 --- a/plat/imx/imx8mm/gpc.c +++ b/plat/imx/imx8mm/gpc.c @@ -636,8 +636,17 @@ void imx_gpc_init(void) /* TODO release dispmix sft reset */ /* enable all the PU for bringup up purpose */ - mmio_write_32(IMX_GPC_BASE + 0xf8, 0x3fcf); + mmio_write_32(0x30384450, 0x3); + mmio_write_32(0x303844d0, 0x3); + mmio_write_32(0x303844f0, 0x3); + mmio_write_32(0x30384560, 0x3); + mmio_write_32(0x30384570, 0x3); + mmio_write_32(0x30384590, 0x3); + mmio_write_32(0x303845a0, 0x3); mmio_write_32(0x303845d0, 0x3); + mmio_write_32(0x30384630, 0x3); + mmio_write_32(0x30384660, 0x3); + mmio_write_32(IMX_GPC_BASE + 0xf8, 0x3fcf); mmio_write_32(0x32e28000, 0x7f); mmio_write_32(0x32e28004, 0x1fff); mmio_write_32(0x32e28008, 0x30000); |