diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-06-08 18:21:33 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 11:21:24 +0300 |
| commit | ede5b2ccebd7b5e22d38304def6d449aaa8096d3 (patch) | |
| tree | 663a632c946fe38b730b48dfa5385dd6fb3f18c1 | |
| parent | ee094d86280c0e3d899d973db24b4b9b563944da (diff) | |
plat: imx8mm: switch the CKIL clock source to 32K OSC
Switch the CKIL clock source to 32K OSC. On i.MX8MM,
after SOC PoR, the default clock source for CKIL is from
divided 24MHz OSC, as 24MHz OSC will be power down when
system enters DSM mdoe. So it is better to use 32K OSC
as the default clock source after system bootup.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
| -rw-r--r-- | plat/imx/imx8mm/imx8mm_bl31_setup.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c index d2356654..b4ebb60d 100644 --- a/plat/imx/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c @@ -272,6 +272,9 @@ void bl31_plat_arch_setup(void) void bl31_platform_setup(void) { + /* select the CKIL source to 32K OSC */ + mmio_write_32(0x30360124, 0x1); + /* init the GICv3 cpu and distributor interface */ plat_gic_driver_init(); plat_gic_init(); |