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authorBai Ping <ping.bai@nxp.com>2018-04-11 10:15:13 +0800
committerAbel Vesa <abel.vesa@nxp.com>2018-06-11 10:33:02 +0300
commit7c5fe75ee1493009b7eb16a4afead86139ba3b1d (patch)
tree6e4ccaf87c579f7ac39eccc0b68590dd3c35cbb9
parentb71c6248fe7499b8a19d10c811814e2b33b1b022 (diff)
plat: imx: update the scfw api to the latest one
The SCFW API is updated based on below commit in SCFW: commit 433c7fb773e3a5853e2744ff1f958bb225cd338a Author: Chuck Cannon <chuck.cannon@nxp.com> Date: Tue Apr 17 16:09:56 2018 -0500 Only default start CPUs for EMUL, SIMU, and test builds. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat
-rw-r--r--plat/imx/common/include/imx8qm_pads.h549
-rw-r--r--plat/imx/common/include/imx8qxp_pads.h359
-rw-r--r--plat/imx/common/include/sci/ipc.h9
-rw-r--r--plat/imx/common/include/sci/rpc.h109
-rw-r--r--plat/imx/common/include/sci/svc/pad/api.h140
-rw-r--r--plat/imx/common/include/sci/svc/pm/api.h246
-rw-r--r--plat/imx/common/include/sci/svc/rm/api.h134
-rw-r--r--plat/imx/common/include/sci/svc/timer/api.h103
-rw-r--r--plat/imx/common/include/sci/types.h1470
-rw-r--r--plat/imx/common/sci/svc/pad/pad_rpc_clnt.c623
-rw-r--r--plat/imx/common/sci/svc/pad/rpc.h54
-rw-r--r--plat/imx/common/sci/svc/pm/pm_rpc_clnt.c499
-rw-r--r--plat/imx/common/sci/svc/pm/rpc.h62
-rw-r--r--plat/imx/common/sci/svc/rm/rm_rpc_clnt.c482
-rw-r--r--plat/imx/common/sci/svc/rm/rpc.h83
-rw-r--r--plat/imx/common/sci/svc/timer/rpc.h76
-rw-r--r--plat/imx/common/sci/svc/timer/timer_rpc_clnt.c314
17 files changed, 2792 insertions, 2520 deletions
diff --git a/plat/imx/common/include/imx8qm_pads.h b/plat/imx/common/include/imx8qm_pads.h
index 1bfd30bf..58fa1504 100644
--- a/plat/imx/common/include/imx8qm_pads.h
+++ b/plat/imx/common/include/imx8qm_pads.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,289 +9,286 @@
* Header file used to configure SoC pad list.
*/
-#ifndef _SC_PADS_H
-#define _SC_PADS_H
+#ifndef SC_PADS_H
+#define SC_PADS_H
/* Includes */
/* Defines */
-#define SC_P_ALL UINT16_MAX /*!< All pads */
-
/*!
* @name Pad Definitions
*/
/*@{*/
-#define SC_P_SIM0_CLK 0 /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
-#define SC_P_SIM0_RST 1 /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */
-#define SC_P_SIM0_IO 2 /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */
-#define SC_P_SIM0_PD 3 /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
-#define SC_P_SIM0_POWER_EN 4 /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
-#define SC_P_SIM0_GPIO0_00 5 /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */
-#define SC_P_M40_I2C0_SCL 7 /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
-#define SC_P_M40_I2C0_SDA 8 /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
-#define SC_P_M40_GPIO0_00 9 /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
-#define SC_P_M40_GPIO0_01 10 /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
-#define SC_P_M41_I2C0_SCL 11 /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
-#define SC_P_M41_I2C0_SDA 12 /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
-#define SC_P_M41_GPIO0_00 13 /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
-#define SC_P_M41_GPIO0_01 14 /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
-#define SC_P_GPT0_CLK 15 /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
-#define SC_P_GPT0_CAPTURE 16 /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
-#define SC_P_GPT0_COMPARE 17 /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
-#define SC_P_GPT1_CLK 18 /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
-#define SC_P_GPT1_CAPTURE 19 /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
-#define SC_P_GPT1_COMPARE 20 /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
-#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, LSIO.GPIO0.IO20 */
-#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, LSIO.GPIO0.IO21 */
-#define SC_P_UART0_RTS_B 23 /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
-#define SC_P_UART0_CTS_B 24 /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
-#define SC_P_UART1_TX 25 /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
-#define SC_P_UART1_RX 26 /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
-#define SC_P_UART1_RTS_B 27 /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
-#define SC_P_UART1_CTS_B 28 /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */
-#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */
-#define SC_P_SCU_WDOG_OUT 31 /*!< SCU.WDOG0.WDOG_OUT */
-#define SC_P_PMIC_I2C_SDA 32 /*!< SCU.PMIC_I2C.SDA */
-#define SC_P_PMIC_I2C_SCL 33 /*!< SCU.PMIC_I2C.SCL */
-#define SC_P_PMIC_EARLY_WARNING 34 /*!< SCU.PMIC_EARLY_WARNING */
-#define SC_P_PMIC_INT_B 35 /*!< SCU.DSC.PMIC_INT_B */
-#define SC_P_SCU_GPIO0_00 36 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
-#define SC_P_SCU_GPIO0_01 37 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
-#define SC_P_SCU_GPIO0_02 38 /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
-#define SC_P_SCU_GPIO0_03 39 /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
-#define SC_P_SCU_GPIO0_04 40 /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
-#define SC_P_SCU_GPIO0_05 41 /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
-#define SC_P_SCU_GPIO0_06 42 /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
-#define SC_P_SCU_GPIO0_07 43 /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
-#define SC_P_SCU_BOOT_MODE0 44 /*!< SCU.DSC.BOOT_MODE0 */
-#define SC_P_SCU_BOOT_MODE1 45 /*!< SCU.DSC.BOOT_MODE1 */
-#define SC_P_SCU_BOOT_MODE2 46 /*!< SCU.DSC.BOOT_MODE2 */
-#define SC_P_SCU_BOOT_MODE3 47 /*!< SCU.DSC.BOOT_MODE3 */
-#define SC_P_SCU_BOOT_MODE4 48 /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
-#define SC_P_SCU_BOOT_MODE5 49 /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
-#define SC_P_LVDS0_GPIO00 50 /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
-#define SC_P_LVDS0_GPIO01 51 /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
-#define SC_P_LVDS0_I2C0_SCL 52 /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
-#define SC_P_LVDS0_I2C0_SDA 53 /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
-#define SC_P_LVDS0_I2C1_SCL 54 /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
-#define SC_P_LVDS0_I2C1_SDA 55 /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
-#define SC_P_LVDS1_GPIO00 56 /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
-#define SC_P_LVDS1_GPIO01 57 /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
-#define SC_P_LVDS1_I2C0_SCL 58 /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
-#define SC_P_LVDS1_I2C0_SDA 59 /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
-#define SC_P_LVDS1_I2C1_SCL 60 /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
-#define SC_P_LVDS1_I2C1_SDA 61 /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */
-#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
-#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
-#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
-#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
-#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
-#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
-#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
-#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */
-#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
-#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
-#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, LSIO.GPIO1.IO28 */
-#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
-#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
-#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
-#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
-#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
-#define SC_P_HDMI_TX0_TS_SCL 82 /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
-#define SC_P_HDMI_TX0_TS_SDA 83 /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
-#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */
-#define SC_P_ESAI1_FSR 85 /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
-#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, LSIO.GPIO2.IO05 */
-#define SC_P_ESAI1_SCKR 87 /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
-#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, LSIO.GPIO2.IO07 */
-#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, LSIO.GPIO2.IO08 */
-#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, LSIO.GPIO2.IO09 */
-#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, LSIO.GPIO2.IO10 */
-#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, LSIO.GPIO2.IO11 */
-#define SC_P_ESAI1_TX4_RX1 93 /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
-#define SC_P_ESAI1_TX5_RX0 94 /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
-#define SC_P_SPDIF0_RX 95 /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
-#define SC_P_SPDIF0_TX 96 /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
-#define SC_P_SPDIF0_EXT_CLK 97 /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
-#define SC_P_SPI3_SCK 98 /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
-#define SC_P_SPI3_SDO 99 /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
-#define SC_P_SPI3_SDI 100 /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
-#define SC_P_SPI3_CS0 101 /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
-#define SC_P_SPI3_CS1 102 /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */
-#define SC_P_ESAI0_FSR 104 /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
-#define SC_P_ESAI0_FST 105 /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
-#define SC_P_ESAI0_SCKR 106 /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
-#define SC_P_ESAI0_SCKT 107 /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
-#define SC_P_ESAI0_TX0 108 /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
-#define SC_P_ESAI0_TX1 109 /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
-#define SC_P_ESAI0_TX2_RX3 110 /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
-#define SC_P_ESAI0_TX3_RX2 111 /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
-#define SC_P_ESAI0_TX4_RX1 112 /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
-#define SC_P_ESAI0_TX5_RX0 113 /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
-#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, LSIO.GPIO3.IO00 */
-#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, LSIO.GPIO3.IO01 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */
-#define SC_P_SPI0_SCK 117 /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
-#define SC_P_SPI0_SDO 118 /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
-#define SC_P_SPI0_SDI 119 /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
-#define SC_P_SPI0_CS0 120 /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
-#define SC_P_SPI0_CS1 121 /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
-#define SC_P_SPI2_SCK 122 /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
-#define SC_P_SPI2_SDO 123 /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
-#define SC_P_SPI2_SDI 124 /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
-#define SC_P_SPI2_CS0 125 /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
-#define SC_P_SPI2_CS1 126 /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
-#define SC_P_SAI1_RXC 127 /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
-#define SC_P_SAI1_RXD 128 /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
-#define SC_P_SAI1_RXFS 129 /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
-#define SC_P_SAI1_TXC 130 /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
-#define SC_P_SAI1_TXD 131 /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
-#define SC_P_SAI1_TXFS 132 /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */
-#define SC_P_ADC_IN7 134 /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
-#define SC_P_ADC_IN6 135 /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
-#define SC_P_ADC_IN5 136 /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
-#define SC_P_ADC_IN4 137 /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
-#define SC_P_ADC_IN3 138 /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
-#define SC_P_ADC_IN2 139 /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
-#define SC_P_ADC_IN1 140 /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
-#define SC_P_ADC_IN0 141 /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
-#define SC_P_MLB_SIG 142 /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
-#define SC_P_MLB_CLK 143 /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
-#define SC_P_MLB_DATA 144 /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */
-#define SC_P_FLEXCAN0_RX 146 /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
-#define SC_P_FLEXCAN0_TX 147 /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
-#define SC_P_FLEXCAN1_RX 148 /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
-#define SC_P_FLEXCAN1_TX 149 /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
-#define SC_P_FLEXCAN2_RX 150 /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
-#define SC_P_FLEXCAN2_TX 151 /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */
-#define SC_P_USB_SS3_TC0 153 /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
-#define SC_P_USB_SS3_TC1 154 /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
-#define SC_P_USB_SS3_TC2 155 /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
-#define SC_P_USB_SS3_TC3 156 /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */
-#define SC_P_USDHC1_RESET_B 158 /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
-#define SC_P_USDHC1_VSELECT 159 /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
-#define SC_P_USDHC2_RESET_B 160 /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
-#define SC_P_USDHC2_VSELECT 161 /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
-#define SC_P_USDHC2_WP 162 /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
-#define SC_P_USDHC2_CD_B 163 /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */
-#define SC_P_ENET0_MDIO 165 /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
-#define SC_P_ENET0_MDC 166 /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
-#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
-#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
-#define SC_P_ENET1_MDIO 169 /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
-#define SC_P_ENET1_MDC 170 /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */
-#define SC_P_QSPI1A_SS0_B 172 /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
-#define SC_P_QSPI1A_SS1_B 173 /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
-#define SC_P_QSPI1A_SCLK 174 /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
-#define SC_P_QSPI1A_DQS 175 /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, LSIO.GPIO4.IO23 */
-#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, LSIO.GPIO4.IO24 */
-#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, LSIO.GPIO4.IO25 */
-#define SC_P_QSPI1A_DATA0 179 /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */
-#define SC_P_QSPI0A_DATA0 181 /*!< LSIO.QSPI0A.DATA0 */
-#define SC_P_QSPI0A_DATA1 182 /*!< LSIO.QSPI0A.DATA1 */
-#define SC_P_QSPI0A_DATA2 183 /*!< LSIO.QSPI0A.DATA2 */
-#define SC_P_QSPI0A_DATA3 184 /*!< LSIO.QSPI0A.DATA3 */
-#define SC_P_QSPI0A_DQS 185 /*!< LSIO.QSPI0A.DQS */
-#define SC_P_QSPI0A_SS0_B 186 /*!< LSIO.QSPI0A.SS0_B */
-#define SC_P_QSPI0A_SS1_B 187 /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
-#define SC_P_QSPI0A_SCLK 188 /*!< LSIO.QSPI0A.SCLK */
-#define SC_P_QSPI0B_SCLK 189 /*!< LSIO.QSPI0B.SCLK */
-#define SC_P_QSPI0B_DATA0 190 /*!< LSIO.QSPI0B.DATA0 */
-#define SC_P_QSPI0B_DATA1 191 /*!< LSIO.QSPI0B.DATA1 */
-#define SC_P_QSPI0B_DATA2 192 /*!< LSIO.QSPI0B.DATA2 */
-#define SC_P_QSPI0B_DATA3 193 /*!< LSIO.QSPI0B.DATA3 */
-#define SC_P_QSPI0B_DQS 194 /*!< LSIO.QSPI0B.DQS */
-#define SC_P_QSPI0B_SS0_B 195 /*!< LSIO.QSPI0B.SS0_B */
-#define SC_P_QSPI0B_SS1_B 196 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */
-#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
-#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
-#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
-#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, LSIO.GPIO4.IO30 */
-#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, LSIO.GPIO4.IO31 */
-#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, LSIO.GPIO5.IO00 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */
-#define SC_P_USB_HSIC0_DATA 205 /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
-#define SC_P_USB_HSIC0_STROBE 206 /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
-#define SC_P_CALIBRATION_0_HSIC 207 /*!< */
-#define SC_P_CALIBRATION_1_HSIC 208 /*!< */
-#define SC_P_EMMC0_CLK 209 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */
-#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO5.IO03 */
-#define SC_P_EMMC0_DATA0 211 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
-#define SC_P_EMMC0_DATA1 212 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
-#define SC_P_EMMC0_DATA2 213 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
-#define SC_P_EMMC0_DATA3 214 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
-#define SC_P_EMMC0_DATA4 215 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
-#define SC_P_EMMC0_DATA5 216 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
-#define SC_P_EMMC0_DATA6 217 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
-#define SC_P_EMMC0_DATA7 218 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
-#define SC_P_EMMC0_STROBE 219 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
-#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO5.IO13 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */
-#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK */
-#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, LSIO.GPIO5.IO14 */
-#define SC_P_USDHC1_DATA0 224 /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
-#define SC_P_USDHC1_DATA1 225 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
-#define SC_P_CTL_NAND_RE_P_N 226 /*!< */
-#define SC_P_USDHC1_DATA2 227 /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
-#define SC_P_USDHC1_DATA3 228 /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
-#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */
-#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, LSIO.GPIO5.IO19 */
-#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, LSIO.GPIO5.IO20 */
-#define SC_P_USDHC1_DATA6 232 /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
-#define SC_P_USDHC1_DATA7 233 /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
-#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, LSIO.GPIO5.IO23 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */
-#define SC_P_USDHC2_CLK 236 /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
-#define SC_P_USDHC2_CMD 237 /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
-#define SC_P_USDHC2_DATA0 238 /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
-#define SC_P_USDHC2_DATA1 239 /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
-#define SC_P_USDHC2_DATA2 240 /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
-#define SC_P_USDHC2_DATA3 241 /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */
-#define SC_P_ENET0_RGMII_TXC 243 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
-#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
-#define SC_P_ENET0_RGMII_TXD0 245 /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
-#define SC_P_ENET0_RGMII_TXD1 246 /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
-#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, LSIO.GPIO6.IO02 */
-#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, LSIO.GPIO6.IO03 */
-#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, LSIO.GPIO6.IO04 */
-#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, LSIO.GPIO6.IO05 */
-#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, LSIO.GPIO6.IO06 */
-#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, LSIO.GPIO6.IO07 */
-#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, LSIO.GPIO6.IO08 */
-#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, LSIO.GPIO6.IO09 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */
-#define SC_P_ENET1_RGMII_TXC 256 /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
-#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
-#define SC_P_ENET1_RGMII_TXD0 258 /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
-#define SC_P_ENET1_RGMII_TXD1 259 /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
-#define SC_P_ENET1_RGMII_TXD2 260 /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
-#define SC_P_ENET1_RGMII_TXD3 261 /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
-#define SC_P_ENET1_RGMII_RXC 262 /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
-#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
-#define SC_P_ENET1_RGMII_RXD0 264 /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
-#define SC_P_ENET1_RGMII_RXD1 265 /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
-#define SC_P_ENET1_RGMII_RXD2 266 /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
-#define SC_P_ENET1_RGMII_RXD3 267 /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */
+#define SC_P_SIM0_CLK 0 /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
+#define SC_P_SIM0_RST 1 /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
+#define SC_P_SIM0_IO 2 /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
+#define SC_P_SIM0_PD 3 /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
+#define SC_P_SIM0_POWER_EN 4 /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
+#define SC_P_SIM0_GPIO0_00 5 /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /* */
+#define SC_P_M40_I2C0_SCL 7 /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
+#define SC_P_M40_I2C0_SDA 8 /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
+#define SC_P_M40_GPIO0_00 9 /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
+#define SC_P_M40_GPIO0_01 10 /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
+#define SC_P_M41_I2C0_SCL 11 /* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
+#define SC_P_M41_I2C0_SDA 12 /* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
+#define SC_P_M41_GPIO0_00 13 /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
+#define SC_P_M41_GPIO0_01 14 /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
+#define SC_P_GPT0_CLK 15 /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
+#define SC_P_GPT0_CAPTURE 16 /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
+#define SC_P_GPT0_COMPARE 17 /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
+#define SC_P_GPT1_CLK 18 /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
+#define SC_P_GPT1_CAPTURE 19 /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
+#define SC_P_GPT1_COMPARE 20 /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
+#define SC_P_UART0_RX 21 /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX 22 /* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RTS_B 23 /* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
+#define SC_P_UART0_CTS_B 24 /* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
+#define SC_P_UART1_TX 25 /* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
+#define SC_P_UART1_RX 26 /* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
+#define SC_P_UART1_RTS_B 27 /* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
+#define SC_P_UART1_CTS_B 28 /* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /* */
+#define SC_P_SCU_PMIC_MEMC_ON 30 /* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
+#define SC_P_SCU_WDOG_OUT 31 /* SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SDA 32 /* SCU.PMIC_I2C.SDA */
+#define SC_P_PMIC_I2C_SCL 33 /* SCU.PMIC_I2C.SCL */
+#define SC_P_PMIC_EARLY_WARNING 34 /* SCU.PMIC_EARLY_WARNING */
+#define SC_P_PMIC_INT_B 35 /* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00 36 /* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
+#define SC_P_SCU_GPIO0_01 37 /* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
+#define SC_P_SCU_GPIO0_02 38 /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
+#define SC_P_SCU_GPIO0_03 39 /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
+#define SC_P_SCU_GPIO0_04 40 /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
+#define SC_P_SCU_GPIO0_05 41 /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
+#define SC_P_SCU_GPIO0_06 42 /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
+#define SC_P_SCU_GPIO0_07 43 /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
+#define SC_P_SCU_BOOT_MODE0 44 /* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1 45 /* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2 46 /* SCU.DSC.BOOT_MODE2 */
+#define SC_P_SCU_BOOT_MODE3 47 /* SCU.DSC.BOOT_MODE3 */
+#define SC_P_SCU_BOOT_MODE4 48 /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
+#define SC_P_SCU_BOOT_MODE5 49 /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
+#define SC_P_LVDS0_GPIO00 50 /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
+#define SC_P_LVDS0_GPIO01 51 /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
+#define SC_P_LVDS0_I2C0_SCL 52 /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
+#define SC_P_LVDS0_I2C0_SDA 53 /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
+#define SC_P_LVDS0_I2C1_SCL 54 /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
+#define SC_P_LVDS0_I2C1_SDA 55 /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
+#define SC_P_LVDS1_GPIO00 56 /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
+#define SC_P_LVDS1_GPIO01 57 /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
+#define SC_P_LVDS1_I2C0_SCL 58 /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
+#define SC_P_LVDS1_I2C0_SDA 59 /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
+#define SC_P_LVDS1_I2C1_SCL 60 /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
+#define SC_P_LVDS1_I2C1_SDA 61 /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /* */
+#define SC_P_MIPI_DSI0_I2C0_SCL 63 /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
+#define SC_P_MIPI_DSI0_I2C0_SDA 64 /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
+#define SC_P_MIPI_DSI0_GPIO0_00 65 /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
+#define SC_P_MIPI_DSI0_GPIO0_01 66 /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
+#define SC_P_MIPI_DSI1_I2C0_SCL 67 /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
+#define SC_P_MIPI_DSI1_I2C0_SDA 68 /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
+#define SC_P_MIPI_DSI1_GPIO0_00 69 /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
+#define SC_P_MIPI_DSI1_GPIO0_01 70 /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /* */
+#define SC_P_MIPI_CSI0_MCLK_OUT 72 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
+#define SC_P_MIPI_CSI0_I2C0_SCL 73 /* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_CSI0_I2C0_SDA 74 /* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_CSI0_GPIO0_00 75 /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01 76 /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI1_MCLK_OUT 77 /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_CSI1_GPIO0_00 78 /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_CSI1_GPIO0_01 79 /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_CSI1_I2C0_SCL 80 /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
+#define SC_P_MIPI_CSI1_I2C0_SDA 81 /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
+#define SC_P_HDMI_TX0_TS_SCL 82 /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
+#define SC_P_HDMI_TX0_TS_SDA 83 /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /* */
+#define SC_P_ESAI1_FSR 85 /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
+#define SC_P_ESAI1_FST 86 /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_SCKR 87 /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
+#define SC_P_ESAI1_SCKT 88 /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0 89 /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1 90 /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3 91 /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2 92 /* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_TX4_RX1 93 /* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
+#define SC_P_ESAI1_TX5_RX0 94 /* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
+#define SC_P_SPDIF0_RX 95 /* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
+#define SC_P_SPDIF0_TX 96 /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
+#define SC_P_SPDIF0_EXT_CLK 97 /* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
+#define SC_P_SPI3_SCK 98 /* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
+#define SC_P_SPI3_SDO 99 /* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
+#define SC_P_SPI3_SDI 100 /* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
+#define SC_P_SPI3_CS0 101 /* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
+#define SC_P_SPI3_CS1 102 /* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /* */
+#define SC_P_ESAI0_FSR 104 /* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
+#define SC_P_ESAI0_FST 105 /* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
+#define SC_P_ESAI0_SCKR 106 /* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
+#define SC_P_ESAI0_SCKT 107 /* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
+#define SC_P_ESAI0_TX0 108 /* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
+#define SC_P_ESAI0_TX1 109 /* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
+#define SC_P_ESAI0_TX2_RX3 110 /* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
+#define SC_P_ESAI0_TX3_RX2 111 /* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
+#define SC_P_ESAI0_TX4_RX1 112 /* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
+#define SC_P_ESAI0_TX5_RX0 113 /* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
+#define SC_P_MCLK_IN0 114 /* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0 115 /* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /* */
+#define SC_P_SPI0_SCK 117 /* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
+#define SC_P_SPI0_SDO 118 /* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
+#define SC_P_SPI0_SDI 119 /* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
+#define SC_P_SPI0_CS0 120 /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
+#define SC_P_SPI0_CS1 121 /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
+#define SC_P_SPI2_SCK 122 /* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
+#define SC_P_SPI2_SDO 123 /* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
+#define SC_P_SPI2_SDI 124 /* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
+#define SC_P_SPI2_CS0 125 /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
+#define SC_P_SPI2_CS1 126 /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
+#define SC_P_SAI1_RXC 127 /* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
+#define SC_P_SAI1_RXD 128 /* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
+#define SC_P_SAI1_RXFS 129 /* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
+#define SC_P_SAI1_TXC 130 /* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
+#define SC_P_SAI1_TXD 131 /* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
+#define SC_P_SAI1_TXFS 132 /* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /* */
+#define SC_P_ADC_IN7 134 /* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
+#define SC_P_ADC_IN6 135 /* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
+#define SC_P_ADC_IN5 136 /* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
+#define SC_P_ADC_IN4 137 /* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
+#define SC_P_ADC_IN3 138 /* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
+#define SC_P_ADC_IN2 139 /* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
+#define SC_P_ADC_IN1 140 /* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
+#define SC_P_ADC_IN0 141 /* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
+#define SC_P_MLB_SIG 142 /* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
+#define SC_P_MLB_CLK 143 /* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
+#define SC_P_MLB_DATA 144 /* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /* */
+#define SC_P_FLEXCAN0_RX 146 /* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
+#define SC_P_FLEXCAN0_TX 147 /* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
+#define SC_P_FLEXCAN1_RX 148 /* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
+#define SC_P_FLEXCAN1_TX 149 /* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
+#define SC_P_FLEXCAN2_RX 150 /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
+#define SC_P_FLEXCAN2_TX 151 /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /* */
+#define SC_P_USB_SS3_TC0 153 /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1 154 /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2 155 /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3 156 /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /* */
+#define SC_P_USDHC1_RESET_B 158 /* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
+#define SC_P_USDHC1_VSELECT 159 /* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
+#define SC_P_USDHC2_RESET_B 160 /* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
+#define SC_P_USDHC2_VSELECT 161 /* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
+#define SC_P_USDHC2_WP 162 /* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
+#define SC_P_USDHC2_CD_B 163 /* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /* */
+#define SC_P_ENET0_MDIO 165 /* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
+#define SC_P_ENET0_MDC 166 /* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
+#define SC_P_ENET0_REFCLK_125M_25M 167 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
+#define SC_P_ENET1_REFCLK_125M_25M 168 /* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
+#define SC_P_ENET1_MDIO 169 /* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
+#define SC_P_ENET1_MDC 170 /* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /* */
+#define SC_P_QSPI1A_SS0_B 172 /* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
+#define SC_P_QSPI1A_SS1_B 173 /* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
+#define SC_P_QSPI1A_SCLK 174 /* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
+#define SC_P_QSPI1A_DQS 175 /* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_QSPI1A_DATA3 176 /* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2 177 /* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1 178 /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA0 179 /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /* */
+#define SC_P_QSPI0A_DATA0 181 /* LSIO.QSPI0A.DATA0 */
+#define SC_P_QSPI0A_DATA1 182 /* LSIO.QSPI0A.DATA1 */
+#define SC_P_QSPI0A_DATA2 183 /* LSIO.QSPI0A.DATA2 */
+#define SC_P_QSPI0A_DATA3 184 /* LSIO.QSPI0A.DATA3 */
+#define SC_P_QSPI0A_DQS 185 /* LSIO.QSPI0A.DQS */
+#define SC_P_QSPI0A_SS0_B 186 /* LSIO.QSPI0A.SS0_B */
+#define SC_P_QSPI0A_SS1_B 187 /* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
+#define SC_P_QSPI0A_SCLK 188 /* LSIO.QSPI0A.SCLK */
+#define SC_P_QSPI0B_SCLK 189 /* LSIO.QSPI0B.SCLK */
+#define SC_P_QSPI0B_DATA0 190 /* LSIO.QSPI0B.DATA0 */
+#define SC_P_QSPI0B_DATA1 191 /* LSIO.QSPI0B.DATA1 */
+#define SC_P_QSPI0B_DATA2 192 /* LSIO.QSPI0B.DATA2 */
+#define SC_P_QSPI0B_DATA3 193 /* LSIO.QSPI0B.DATA3 */
+#define SC_P_QSPI0B_DQS 194 /* LSIO.QSPI0B.DQS */
+#define SC_P_QSPI0B_SS0_B 195 /* LSIO.QSPI0B.SS0_B */
+#define SC_P_QSPI0B_SS1_B 196 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /* */
+#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
+#define SC_P_PCIE_CTRL0_WAKE_B 199 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
+#define SC_P_PCIE_CTRL0_PERST_B 200 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B 202 /* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B 203 /* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /* */
+#define SC_P_USB_HSIC0_DATA 205 /* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
+#define SC_P_USB_HSIC0_STROBE 206 /* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
+#define SC_P_CALIBRATION_0_HSIC 207 /* */
+#define SC_P_CALIBRATION_1_HSIC 208 /* */
+#define SC_P_EMMC0_CLK 209 /* CONN.EMMC0.CLK, CONN.NAND.READY_B */
+#define SC_P_EMMC0_CMD 210 /* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_DATA0 211 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
+#define SC_P_EMMC0_DATA1 212 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
+#define SC_P_EMMC0_DATA2 213 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
+#define SC_P_EMMC0_DATA3 214 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
+#define SC_P_EMMC0_DATA4 215 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
+#define SC_P_EMMC0_DATA5 216 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
+#define SC_P_EMMC0_DATA6 217 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
+#define SC_P_EMMC0_DATA7 218 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
+#define SC_P_EMMC0_STROBE 219 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
+#define SC_P_EMMC0_RESET_B 220 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /* */
+#define SC_P_USDHC1_CLK 222 /* CONN.USDHC1.CLK, AUD.MQS.R */
+#define SC_P_USDHC1_CMD 223 /* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_DATA0 224 /* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
+#define SC_P_USDHC1_DATA1 225 /* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
+#define SC_P_CTL_NAND_RE_P_N 226 /* */
+#define SC_P_USDHC1_DATA2 227 /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
+#define SC_P_USDHC1_DATA3 228 /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
+#define SC_P_CTL_NAND_DQS_P_N 229 /* */
+#define SC_P_USDHC1_DATA4 230 /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5 231 /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA6 232 /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
+#define SC_P_USDHC1_DATA7 233 /* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
+#define SC_P_USDHC1_STROBE 234 /* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /* */
+#define SC_P_USDHC2_CLK 236 /* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
+#define SC_P_USDHC2_CMD 237 /* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
+#define SC_P_USDHC2_DATA0 238 /* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
+#define SC_P_USDHC2_DATA1 239 /* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
+#define SC_P_USDHC2_DATA2 240 /* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
+#define SC_P_USDHC2_DATA3 241 /* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /* */
+#define SC_P_ENET0_RGMII_TXC 243 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
+#define SC_P_ENET0_RGMII_TX_CTL 244 /* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
+#define SC_P_ENET0_RGMII_TXD0 245 /* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
+#define SC_P_ENET0_RGMII_TXD1 246 /* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
+#define SC_P_ENET0_RGMII_TXD2 247 /* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3 248 /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC 249 /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL 250 /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0 251 /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1 252 /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2 253 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3 254 /* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /* */
+#define SC_P_ENET1_RGMII_TXC 256 /* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
+#define SC_P_ENET1_RGMII_TX_CTL 257 /* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
+#define SC_P_ENET1_RGMII_TXD0 258 /* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
+#define SC_P_ENET1_RGMII_TXD1 259 /* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
+#define SC_P_ENET1_RGMII_TXD2 260 /* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
+#define SC_P_ENET1_RGMII_TXD3 261 /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
+#define SC_P_ENET1_RGMII_RXC 262 /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
+#define SC_P_ENET1_RGMII_RX_CTL 263 /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
+#define SC_P_ENET1_RGMII_RXD0 264 /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
+#define SC_P_ENET1_RGMII_RXD1 265 /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
+#define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
+#define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */
/*@}*/
-#endif /* _SC_PADS_H */
-
+#endif /* SC_PADS_H */
diff --git a/plat/imx/common/include/imx8qxp_pads.h b/plat/imx/common/include/imx8qxp_pads.h
index e680afc5..0393271b 100644
--- a/plat/imx/common/include/imx8qxp_pads.h
+++ b/plat/imx/common/include/imx8qxp_pads.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,194 +9,191 @@
* Header file used to configure SoC pad list.
*/
-#ifndef _SC_PADS_H
-#define _SC_PADS_H
+#ifndef SC_PADS_H
+#define SC_PADS_H
/* Includes */
/* Defines */
-#define SC_P_ALL UINT16_MAX /*!< All pads */
-
/*!
* @name Pad Definitions
*/
/*@{*/
-#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
-#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
-#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */
-#define SC_P_USB_SS3_TC0 4 /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
-#define SC_P_USB_SS3_TC1 5 /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
-#define SC_P_USB_SS3_TC2 6 /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
-#define SC_P_USB_SS3_TC3 7 /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */
-#define SC_P_EMMC0_CLK 9 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
-#define SC_P_EMMC0_CMD 10 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
-#define SC_P_EMMC0_DATA0 11 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
-#define SC_P_EMMC0_DATA1 12 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
-#define SC_P_EMMC0_DATA2 13 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
-#define SC_P_EMMC0_DATA3 14 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */
-#define SC_P_EMMC0_DATA4 16 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
-#define SC_P_EMMC0_DATA5 17 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
-#define SC_P_EMMC0_DATA6 18 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
-#define SC_P_EMMC0_DATA7 19 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
-#define SC_P_EMMC0_STROBE 20 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
-#define SC_P_EMMC0_RESET_B 21 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */
-#define SC_P_USDHC1_RESET_B 23 /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
-#define SC_P_USDHC1_VSELECT 24 /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
-#define SC_P_CTL_NAND_RE_P_N 25 /*!< */
-#define SC_P_USDHC1_WP 26 /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
-#define SC_P_USDHC1_CD_B 27 /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */
-#define SC_P_USDHC1_CLK 30 /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
-#define SC_P_USDHC1_CMD 31 /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
-#define SC_P_USDHC1_DATA0 32 /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
-#define SC_P_USDHC1_DATA1 33 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
-#define SC_P_USDHC1_DATA2 34 /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
-#define SC_P_USDHC1_DATA3 35 /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */
-#define SC_P_ENET0_RGMII_TXC 37 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
-#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
-#define SC_P_ENET0_RGMII_TXD0 39 /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
-#define SC_P_ENET0_RGMII_TXD1 40 /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
-#define SC_P_ENET0_RGMII_TXD2 41 /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
-#define SC_P_ENET0_RGMII_TXD3 42 /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */
-#define SC_P_ENET0_RGMII_RXC 44 /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
-#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
-#define SC_P_ENET0_RGMII_RXD0 46 /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
-#define SC_P_ENET0_RGMII_RXD1 47 /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
-#define SC_P_ENET0_RGMII_RXD2 48 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
-#define SC_P_ENET0_RGMII_RXD3 49 /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */
-#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
-#define SC_P_ENET0_MDIO 52 /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
-#define SC_P_ENET0_MDC 53 /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */
-#define SC_P_ESAI0_FSR 55 /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
-#define SC_P_ESAI0_FST 56 /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
-#define SC_P_ESAI0_SCKR 57 /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
-#define SC_P_ESAI0_SCKT 58 /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
-#define SC_P_ESAI0_TX0 59 /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
-#define SC_P_ESAI0_TX1 60 /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
-#define SC_P_ESAI0_TX2_RX3 61 /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
-#define SC_P_ESAI0_TX3_RX2 62 /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
-#define SC_P_ESAI0_TX4_RX1 63 /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
-#define SC_P_ESAI0_TX5_RX0 64 /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
-#define SC_P_SPDIF0_RX 65 /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
-#define SC_P_SPDIF0_TX 66 /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
-#define SC_P_SPDIF0_EXT_CLK 67 /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */
-#define SC_P_SPI3_SCK 69 /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
-#define SC_P_SPI3_SDO 70 /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
-#define SC_P_SPI3_SDI 71 /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
-#define SC_P_SPI3_CS0 72 /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
-#define SC_P_SPI3_CS1 73 /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
-#define SC_P_MCLK_IN1 74 /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
-#define SC_P_MCLK_IN0 75 /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
-#define SC_P_MCLK_OUT0 76 /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
-#define SC_P_UART1_TX 77 /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
-#define SC_P_UART1_RX 78 /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
-#define SC_P_UART1_RTS_B 79 /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
-#define SC_P_UART1_CTS_B 80 /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */
-#define SC_P_SAI0_TXD 82 /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
-#define SC_P_SAI0_TXC 83 /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
-#define SC_P_SAI0_RXD 84 /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
-#define SC_P_SAI0_TXFS 85 /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
-#define SC_P_SAI1_RXD 86 /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
-#define SC_P_SAI1_RXC 87 /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
-#define SC_P_SAI1_RXFS 88 /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
-#define SC_P_SPI2_CS0 89 /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
-#define SC_P_SPI2_SDO 90 /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
-#define SC_P_SPI2_SDI 91 /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
-#define SC_P_SPI2_SCK 92 /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
-#define SC_P_SPI0_SCK 93 /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
-#define SC_P_SPI0_SDI 94 /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
-#define SC_P_SPI0_SDO 95 /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
-#define SC_P_SPI0_CS1 96 /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
-#define SC_P_SPI0_CS0 97 /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */
-#define SC_P_ADC_IN1 99 /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
-#define SC_P_ADC_IN0 100 /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
-#define SC_P_ADC_IN3 101 /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
-#define SC_P_ADC_IN2 102 /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
-#define SC_P_ADC_IN5 103 /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
-#define SC_P_ADC_IN4 104 /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
-#define SC_P_FLEXCAN0_RX 105 /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
-#define SC_P_FLEXCAN0_TX 106 /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
-#define SC_P_FLEXCAN1_RX 107 /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
-#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
-#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
-#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
-#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, LSIO.GPIO1.IO21 */
-#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, LSIO.GPIO1.IO22 */
-#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
-#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */
-#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
-#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
-#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
-#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
-#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
-#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */
-#define SC_P_JTAG_TRST_B 125 /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
-#define SC_P_PMIC_I2C_SCL 126 /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
-#define SC_P_PMIC_I2C_SDA 127 /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
-#define SC_P_PMIC_INT_B 128 /*!< SCU.DSC.PMIC_INT_B */
-#define SC_P_SCU_GPIO0_00 129 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
-#define SC_P_SCU_GPIO0_01 130 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
-#define SC_P_SCU_PMIC_STANDBY 131 /*!< SCU.DSC.PMIC_STANDBY */
-#define SC_P_SCU_BOOT_MODE0 132 /*!< SCU.DSC.BOOT_MODE0 */
-#define SC_P_SCU_BOOT_MODE1 133 /*!< SCU.DSC.BOOT_MODE1 */
-#define SC_P_SCU_BOOT_MODE2 134 /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
-#define SC_P_SCU_BOOT_MODE3 135 /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
-#define SC_P_CSI_D00 136 /*!< CI_PI.D02, ADMA.SAI0.RXC */
-#define SC_P_CSI_D01 137 /*!< CI_PI.D03, ADMA.SAI0.RXD */
-#define SC_P_CSI_D02 138 /*!< CI_PI.D04, ADMA.SAI0.RXFS */
-#define SC_P_CSI_D03 139 /*!< CI_PI.D05, ADMA.SAI2.RXC */
-#define SC_P_CSI_D04 140 /*!< CI_PI.D06, ADMA.SAI2.RXD */
-#define SC_P_CSI_D05 141 /*!< CI_PI.D07, ADMA.SAI2.RXFS */
-#define SC_P_CSI_D06 142 /*!< CI_PI.D08, ADMA.SAI3.RXC */
-#define SC_P_CSI_D07 143 /*!< CI_PI.D09, ADMA.SAI3.RXD */
-#define SC_P_CSI_HSYNC 144 /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
-#define SC_P_CSI_VSYNC 145 /*!< CI_PI.VSYNC, CI_PI.D01 */
-#define SC_P_CSI_PCLK 146 /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
-#define SC_P_CSI_MCLK 147 /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
-#define SC_P_CSI_EN 148 /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
-#define SC_P_CSI_RESET 149 /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */
-#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
-#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
-#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
-#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
-#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
-#define SC_P_QSPI0A_DATA0 156 /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
-#define SC_P_QSPI0A_DATA1 157 /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
-#define SC_P_QSPI0A_DATA2 158 /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
-#define SC_P_QSPI0A_DATA3 159 /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
-#define SC_P_QSPI0A_DQS 160 /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
-#define SC_P_QSPI0A_SS0_B 161 /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
-#define SC_P_QSPI0A_SS1_B 162 /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
-#define SC_P_QSPI0A_SCLK 163 /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */
-#define SC_P_QSPI0B_SCLK 165 /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
-#define SC_P_QSPI0B_DATA0 166 /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
-#define SC_P_QSPI0B_DATA1 167 /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
-#define SC_P_QSPI0B_DATA2 168 /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
-#define SC_P_QSPI0B_DATA3 169 /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
-#define SC_P_QSPI0B_DQS 170 /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
-#define SC_P_QSPI0B_SS0_B 171 /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
-#define SC_P_QSPI0B_SS1_B 172 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */
+#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
+#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
+#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */
+#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */
+#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
+#define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
+#define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
+#define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
+#define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
+#define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /* */
+#define SC_P_EMMC0_DATA4 16 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
+#define SC_P_EMMC0_DATA5 17 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
+#define SC_P_EMMC0_DATA6 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
+#define SC_P_EMMC0_DATA7 19 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
+#define SC_P_EMMC0_STROBE 20 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
+#define SC_P_EMMC0_RESET_B 21 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /* */
+#define SC_P_USDHC1_RESET_B 23 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
+#define SC_P_USDHC1_VSELECT 24 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
+#define SC_P_CTL_NAND_RE_P_N 25 /* */
+#define SC_P_USDHC1_WP 26 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
+#define SC_P_USDHC1_CD_B 27 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_CTL_NAND_DQS_P_N 28 /* */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /* */
+#define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
+#define SC_P_USDHC1_CMD 31 /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
+#define SC_P_USDHC1_DATA0 32 /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
+#define SC_P_USDHC1_DATA1 33 /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
+#define SC_P_USDHC1_DATA2 34 /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
+#define SC_P_USDHC1_DATA3 35 /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /* */
+#define SC_P_ENET0_RGMII_TXC 37 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
+#define SC_P_ENET0_RGMII_TX_CTL 38 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
+#define SC_P_ENET0_RGMII_TXD0 39 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
+#define SC_P_ENET0_RGMII_TXD1 40 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
+#define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
+#define SC_P_ENET0_RGMII_TXD3 42 /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /* */
+#define SC_P_ENET0_RGMII_RXC 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
+#define SC_P_ENET0_RGMII_RX_CTL 45 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
+#define SC_P_ENET0_RGMII_RXD0 46 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
+#define SC_P_ENET0_RGMII_RXD1 47 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
+#define SC_P_ENET0_RGMII_RXD2 48 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
+#define SC_P_ENET0_RGMII_RXD3 49 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /* */
+#define SC_P_ENET0_REFCLK_125M_25M 51 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
+#define SC_P_ENET0_MDIO 52 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
+#define SC_P_ENET0_MDC 53 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /* */
+#define SC_P_ESAI0_FSR 55 /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
+#define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
+#define SC_P_ESAI0_SCKR 57 /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
+#define SC_P_ESAI0_SCKT 58 /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
+#define SC_P_ESAI0_TX0 59 /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
+#define SC_P_ESAI0_TX1 60 /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
+#define SC_P_ESAI0_TX2_RX3 61 /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
+#define SC_P_ESAI0_TX3_RX2 62 /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
+#define SC_P_ESAI0_TX4_RX1 63 /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
+#define SC_P_ESAI0_TX5_RX0 64 /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
+#define SC_P_SPDIF0_RX 65 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
+#define SC_P_SPDIF0_TX 66 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
+#define SC_P_SPDIF0_EXT_CLK 67 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /* */
+#define SC_P_SPI3_SCK 69 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
+#define SC_P_SPI3_SDO 70 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
+#define SC_P_SPI3_SDI 71 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
+#define SC_P_SPI3_CS0 72 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
+#define SC_P_SPI3_CS1 73 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
+#define SC_P_MCLK_IN1 74 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
+#define SC_P_MCLK_IN0 75 /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
+#define SC_P_MCLK_OUT0 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
+#define SC_P_UART1_TX 77 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
+#define SC_P_UART1_RX 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
+#define SC_P_UART1_RTS_B 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
+#define SC_P_UART1_CTS_B 80 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /* */
+#define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
+#define SC_P_SAI0_TXC 83 /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
+#define SC_P_SAI0_RXD 84 /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
+#define SC_P_SAI0_TXFS 85 /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
+#define SC_P_SAI1_RXD 86 /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
+#define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
+#define SC_P_SAI1_RXFS 88 /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
+#define SC_P_SPI2_CS0 89 /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
+#define SC_P_SPI2_SDO 90 /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
+#define SC_P_SPI2_SDI 91 /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
+#define SC_P_SPI2_SCK 92 /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
+#define SC_P_SPI0_SCK 93 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
+#define SC_P_SPI0_SDI 94 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
+#define SC_P_SPI0_SDO 95 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
+#define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
+#define SC_P_SPI0_CS0 97 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /* */
+#define SC_P_ADC_IN1 99 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
+#define SC_P_ADC_IN0 100 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
+#define SC_P_ADC_IN3 101 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
+#define SC_P_ADC_IN2 102 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
+#define SC_P_ADC_IN5 103 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
+#define SC_P_ADC_IN4 104 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
+#define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
+#define SC_P_FLEXCAN0_TX 106 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
+#define SC_P_FLEXCAN1_RX 107 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
+#define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
+#define SC_P_FLEXCAN2_RX 109 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
+#define SC_P_FLEXCAN2_TX 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
+#define SC_P_UART0_RX 111 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
+#define SC_P_UART0_TX 112 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
+#define SC_P_UART2_TX 113 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
+#define SC_P_UART2_RX 114 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /* */
+#define SC_P_MIPI_DSI0_I2C0_SCL 116 /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_DSI0_I2C0_SDA 117 /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_DSI0_GPIO0_00 118 /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_DSI0_GPIO0_01 119 /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_DSI1_I2C0_SCL 120 /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_DSI1_I2C0_SDA 121 /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_DSI1_GPIO0_00 122 /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_DSI1_GPIO0_01 123 /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /* */
+#define SC_P_JTAG_TRST_B 125 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SCL 126 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
+#define SC_P_PMIC_I2C_SDA 127 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
+#define SC_P_PMIC_INT_B 128 /* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00 129 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
+#define SC_P_SCU_GPIO0_01 130 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
+#define SC_P_SCU_PMIC_STANDBY 131 /* SCU.DSC.PMIC_STANDBY */
+#define SC_P_SCU_BOOT_MODE0 132 /* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1 133 /* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2 134 /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
+#define SC_P_SCU_BOOT_MODE3 135 /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
+#define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */
+#define SC_P_CSI_D01 137 /* CI_PI.D03, ADMA.SAI0.RXD */
+#define SC_P_CSI_D02 138 /* CI_PI.D04, ADMA.SAI0.RXFS */
+#define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */
+#define SC_P_CSI_D04 140 /* CI_PI.D06, ADMA.SAI2.RXD */
+#define SC_P_CSI_D05 141 /* CI_PI.D07, ADMA.SAI2.RXFS */
+#define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */
+#define SC_P_CSI_D07 143 /* CI_PI.D09, ADMA.SAI3.RXD */
+#define SC_P_CSI_HSYNC 144 /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
+#define SC_P_CSI_VSYNC 145 /* CI_PI.VSYNC, CI_PI.D01 */
+#define SC_P_CSI_PCLK 146 /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
+#define SC_P_CSI_MCLK 147 /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
+#define SC_P_CSI_EN 148 /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
+#define SC_P_CSI_RESET 149 /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /* */
+#define SC_P_MIPI_CSI0_MCLK_OUT 151 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
+#define SC_P_MIPI_CSI0_I2C0_SCL 152 /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
+#define SC_P_MIPI_CSI0_I2C0_SDA 153 /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
+#define SC_P_MIPI_CSI0_GPIO0_01 154 /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
+#define SC_P_MIPI_CSI0_GPIO0_00 155 /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
+#define SC_P_QSPI0A_DATA0 156 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
+#define SC_P_QSPI0A_DATA1 157 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
+#define SC_P_QSPI0A_DATA2 158 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
+#define SC_P_QSPI0A_DATA3 159 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
+#define SC_P_QSPI0A_DQS 160 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
+#define SC_P_QSPI0A_SS0_B 161 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
+#define SC_P_QSPI0A_SS1_B 162 /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
+#define SC_P_QSPI0A_SCLK 163 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /* */
+#define SC_P_QSPI0B_SCLK 165 /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
+#define SC_P_QSPI0B_DATA0 166 /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
+#define SC_P_QSPI0B_DATA1 167 /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
+#define SC_P_QSPI0B_DATA2 168 /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
+#define SC_P_QSPI0B_DATA3 169 /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
+#define SC_P_QSPI0B_DQS 170 /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
+#define SC_P_QSPI0B_SS0_B 171 /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
+#define SC_P_QSPI0B_SS1_B 172 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /* */
/*@}*/
-#endif /* _SC_PADS_H */
-
+#endif /* SC_PADS_H */
diff --git a/plat/imx/common/include/sci/ipc.h b/plat/imx/common/include/sci/ipc.h
index aec7ffb8..6c76c466 100644
--- a/plat/imx/common/include/sci/ipc.h
+++ b/plat/imx/common/include/sci/ipc.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,8 +9,8 @@
* Header file for the IPC implementation.
*/
-#ifndef _SC_IPC_H
-#define _SC_IPC_H
+#ifndef SC_IPC_H
+#define SC_IPC_H
/* Includes */
@@ -63,5 +63,4 @@ void sc_ipc_read(sc_ipc_t ipc, void *data);
*/
void sc_ipc_write(sc_ipc_t ipc, void *data);
-#endif /* _SC_IPC_H */
-
+#endif /* SC_IPC_H */
diff --git a/plat/imx/common/include/sci/rpc.h b/plat/imx/common/include/sci/rpc.h
index b7e5c7f5..86ad904d 100644
--- a/plat/imx/common/include/sci/rpc.h
+++ b/plat/imx/common/include/sci/rpc.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,8 +9,8 @@
* Header file for the RPC implementation.
*/
-#ifndef _SC_RPC_H
-#define _SC_RPC_H
+#ifndef SC_RPC_H
+#define SC_RPC_H
/* Includes */
@@ -19,70 +19,68 @@
/* Defines */
-#define SC_RPC_VERSION 1
+#define SC_RPC_VERSION 1U
-#define SC_RPC_MAX_MSG 8
+#define SC_RPC_MAX_MSG 8U
#define RPC_VER(MSG) ((MSG)->version)
#define RPC_SIZE(MSG) ((MSG)->size)
#define RPC_SVC(MSG) ((MSG)->svc)
#define RPC_FUNC(MSG) ((MSG)->func)
#define RPC_R8(MSG) ((MSG)->func)
-#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4])
-#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2])
+#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
+#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
-#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4])
-#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2])
+#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
+#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
+#define SC_RPC_SVC_UNKNOWN 0U
+#define SC_RPC_SVC_RETURN 1U
+#define SC_RPC_SVC_PM 2U
+#define SC_RPC_SVC_RM 3U
+#define SC_RPC_SVC_TIMER 5U
+#define SC_RPC_SVC_PAD 6U
+#define SC_RPC_SVC_MISC 7U
+#define SC_RPC_SVC_IRQ 8U
+#define SC_RPC_SVC_ABORT 9U
+
+#define SC_RPC_ASYNC_STATE_RD_START 0U
+#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U
+#define SC_RPC_ASYNC_STATE_RD_DONE 2U
+#define SC_RPC_ASYNC_STATE_WR_START 3U
+#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U
+#define SC_RPC_ASYNC_STATE_WR_DONE 5U
+
+#define SC_RPC_MU_GIR_SVC 0x1U
+#define SC_RPC_MU_GIR_DBG 0x8U
+
/* Types */
-typedef enum sc_rpc_svc_e
-{
- SC_RPC_SVC_UNKNOWN = 0,
- SC_RPC_SVC_RETURN = 1,
- SC_RPC_SVC_PM = 2,
- SC_RPC_SVC_RM = 3,
- SC_RPC_SVC_TIMER = 5,
- SC_RPC_SVC_PAD = 6,
- SC_RPC_SVC_MISC = 7,
- SC_RPC_SVC_IRQ = 8,
- SC_RPC_SVC_ABORT = 9
-} sc_rpc_svc_t;
-
-typedef struct sc_rpc_msg_s
-{
- uint8_t version;
- uint8_t size;
- uint8_t svc;
- uint8_t func;
- union
- {
- int32_t i32[(SC_RPC_MAX_MSG - 1)];
- int16_t i16[(SC_RPC_MAX_MSG - 1) * 2];
- int8_t i8[(SC_RPC_MAX_MSG - 1) * 4];
- uint32_t u32[(SC_RPC_MAX_MSG - 1)];
- uint16_t u16[(SC_RPC_MAX_MSG - 1) * 2];
- uint8_t u8[(SC_RPC_MAX_MSG - 1) * 4];
- } DATA;
+typedef uint8_t sc_rpc_svc_t;
+
+typedef struct sc_rpc_msg_s {
+ uint8_t version;
+ uint8_t size;
+ uint8_t svc;
+ uint8_t func;
+ union {
+ int32_t i32[(SC_RPC_MAX_MSG - 1U)];
+ int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U];
+ int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U];
+ uint32_t u32[(SC_RPC_MAX_MSG - 1U)];
+ uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U];
+ uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U];
+ } DATA;
} sc_rpc_msg_t;
-typedef enum sc_rpc_async_state_e
-{
- SC_RPC_ASYNC_STATE_RD_START = 0,
- SC_RPC_ASYNC_STATE_RD_ACTIVE = 1,
- SC_RPC_ASYNC_STATE_RD_DONE = 2,
- SC_RPC_ASYNC_STATE_WR_START = 3,
- SC_RPC_ASYNC_STATE_WR_ACTIVE = 4,
- SC_RPC_ASYNC_STATE_WR_DONE = 5,
-} sc_rpc_async_state_t;
-
-typedef struct sc_rpc_async_msg_s
-{
- sc_rpc_async_state_t state;
- uint8_t wordIdx;
- sc_rpc_msg_t msg;
- uint32_t timeStamp;
+typedef uint8_t sc_rpc_async_state_t;
+
+typedef struct sc_rpc_async_msg_s {
+ sc_rpc_async_state_t state;
+ uint8_t wordIdx;
+ sc_rpc_msg_t msg;
+ uint32_t timeStamp;
} sc_rpc_async_msg_t;
/* Functions */
@@ -95,7 +93,7 @@ typedef struct sc_rpc_async_msg_s
* @param[in,out] msg handle to a message
* @param[in] no_resp response flag
*
- * If \a no_resp is false then this function waits for a response
+ * If \a no_resp is SC_FALSE then this function waits for a response
* and returns the result in \a msg.
*/
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
@@ -126,5 +124,4 @@ void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg);
*/
void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-#endif /* _SC_RPC_H */
-
+#endif /* SC_RPC_H */
diff --git a/plat/imx/common/include/sci/svc/pad/api.h b/plat/imx/common/include/sci/svc/pad/api.h
index f05a59b4..58f2c24c 100644
--- a/plat/imx/common/include/sci/svc/pad/api.h
+++ b/plat/imx/common/include/sci/svc/pad/api.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,14 +45,16 @@
* assigned owners and only the owners can configure the pads. Some of the
* pads are reserved for use by the SCFW itself and this can be overriden
* with the implementation of board_config_sc(). Additionally, pads may
- * be assigned to various other partitions via SCD or via the implementation
- * of board_system_config().
+ * be assigned to various other partitions via the implementation of
+ * board_system_config().
*
+ * Note muxing two input pads to the same IP functional signal will
+ * result in undefined behavior.
* @{
*/
-#ifndef _SC_PAD_API_H
-#define _SC_PAD_API_H
+#ifndef SC_PAD_API_H
+#define SC_PAD_API_H
/* Includes */
@@ -65,79 +67,79 @@
* @name Defines for type widths
*/
/*@{*/
-#define SC_PAD_MUX_W 3 /*!< Width of mux parameter */
+#define SC_PAD_MUX_W 3 /* Width of mux parameter */
/*@}*/
/*!
* @name Defines for sc_pad_config_t
*/
/*@{*/
-#define SC_PAD_CONFIG_NORMAL 0 /*!< Normal */
-#define SC_PAD_CONFIG_OD 1 /*!< Open Drain */
-#define SC_PAD_CONFIG_OD_IN 2 /*!< Open Drain and input */
-#define SC_PAD_CONFIG_OUT_IN 3 /*!< Output and input */
+#define SC_PAD_CONFIG_NORMAL 0U /* Normal */
+#define SC_PAD_CONFIG_OD 1U /* Open Drain */
+#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */
+#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */
/*@}*/
/*!
* @name Defines for sc_pad_iso_t
*/
/*@{*/
-#define SC_PAD_ISO_OFF 0 /*!< ISO latch is transparent */
-#define SC_PAD_ISO_EARLY 1 /*!< Follow EARLY_ISO */
-#define SC_PAD_ISO_LATE 2 /*!< Follow LATE_ISO */
-#define SC_PAD_ISO_ON 3 /*!< ISO latched data is held */
+#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */
+#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */
+#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */
+#define SC_PAD_ISO_ON 3U /* ISO latched data is held */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_dse_t
*/
/*@{*/
-#define SC_PAD_28FDSOI_DSE_18V_1MA 0 /*!< Drive strength of 1mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_2MA 1 /*!< Drive strength of 2mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_4MA 2 /*!< Drive strength of 4mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_6MA 3 /*!< Drive strength of 6mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_8MA 4 /*!< Drive strength of 8mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_10MA 5 /*!< Drive strength of 10mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_12MA 6 /*!< Drive strength of 12mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_HS 7 /*!< High-speed drive strength for 1.8v */
-#define SC_PAD_28FDSOI_DSE_33V_2MA 0 /*!< Drive strength of 2mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_4MA 1 /*!< Drive strength of 4mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_8MA 2 /*!< Drive strength of 8mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_12MA 3 /*!< Drive strength of 12mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_DV_HIGH 0 /*!< High drive strength for dual volt */
-#define SC_PAD_28FDSOI_DSE_DV_LOW 1 /*!< Low drive strength for dual volt */
+#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed drive strength for 1.8v */
+#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength for dual volt */
+#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength for dual volt */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_ps_t
*/
/*@{*/
-#define SC_PAD_28FDSOI_PS_KEEPER 0 /*!< Bus-keeper (only valid for 1.8v) */
-#define SC_PAD_28FDSOI_PS_PU 1 /*!< Pull-up */
-#define SC_PAD_28FDSOI_PS_PD 2 /*!< Pull-down */
-#define SC_PAD_28FDSOI_PS_NONE 3 /*!< No pull (disabled) */
+#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */
+#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */
+#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */
+#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_pus_t
*/
/*@{*/
-#define SC_PAD_28FDSOI_PUS_30K_PD 0 /*!< 30K pull-down */
-#define SC_PAD_28FDSOI_PUS_100K_PU 1 /*!< 100K pull-up */
-#define SC_PAD_28FDSOI_PUS_3K_PU 2 /*!< 3K pull-up */
-#define SC_PAD_28FDSOI_PUS_30K_PU 3 /*!< 30K pull-up */
+#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */
+#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */
+#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */
+#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */
/*@}*/
/*!
* @name Defines for sc_pad_wakeup_t
*/
/*@{*/
-#define SC_PAD_WAKEUP_OFF 0 /*!< Off */
-#define SC_PAD_WAKEUP_CLEAR 1 /*!< Clears pending flag */
-#define SC_PAD_WAKEUP_LOW_LVL 4 /*!< Low level */
-#define SC_PAD_WAKEUP_FALL_EDGE 5 /*!< Falling edge */
-#define SC_PAD_WAKEUP_RISE_EDGE 6 /*!< Rising edge */
-#define SC_PAD_WAKEUP_HIGH_LVL 7 /*!< High-level */
+#define SC_PAD_WAKEUP_OFF 0U /* Off */
+#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */
+#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */
+#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */
+#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */
+#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */
/*@}*/
/* Types */
@@ -205,10 +207,13 @@ typedef uint8_t sc_pad_wakeup_t;
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
+ * Note muxing two input pads to the same IP functional signal will
+ * result in undefined behavior.
+ *
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
- uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
+ uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
/*!
* This function gets the mux settings for a pad. This includes
@@ -229,7 +234,8 @@ sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
- uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso);
+ uint8_t *mux, sc_pad_config_t *config,
+ sc_pad_iso_t *iso);
/*!
* This function configures the general purpose pad control. This
@@ -286,8 +292,7 @@ sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl);
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_wakeup_t wakeup);
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup);
/*!
* This function gets the wakeup mode of a pad.
@@ -304,8 +309,7 @@ sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_wakeup_t *wakeup);
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup);
/*!
* This function configures a pad.
@@ -327,11 +331,14 @@ sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
*
* @return Returns an error code (SC_ERR_NONE = success).
*
+ * Note muxing two input pads to the same IP functional signal will
+ * result in undefined behavior.
+ *
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
- sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
- sc_pad_wakeup_t wakeup);
+ sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+ sc_pad_wakeup_t wakeup);
/*!
* This function gets a pad's config.
@@ -356,8 +363,8 @@ sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
- sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
- sc_pad_wakeup_t *wakeup);
+ sc_pad_config_t *config, sc_pad_iso_t *iso,
+ uint32_t *ctrl, sc_pad_wakeup_t *wakeup);
/* @} */
@@ -427,7 +434,8 @@ sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps);
+ sc_pad_28fdsoi_dse_t dse,
+ sc_pad_28fdsoi_ps_t ps);
/*!
* This function gets the pad control specific to 28FDSOI.
@@ -447,7 +455,8 @@ sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps);
+ sc_pad_28fdsoi_dse_t *dse,
+ sc_pad_28fdsoi_ps_t *ps);
/*!
* This function configures the pad control specific to 28FDSOI.
@@ -470,8 +479,9 @@ sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_28fdsoi_dse_t dse, bool hys, sc_pad_28fdsoi_pus_t pus,
- bool pke, bool pue);
+ sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
+ sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
+ sc_bool_t pue);
/*!
* This function gets the pad control specific to 28FDSOI.
@@ -494,8 +504,9 @@ sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_28fdsoi_dse_t *dse, bool *hys, sc_pad_28fdsoi_pus_t *pus,
- bool *pke, bool *pue);
+ sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
+ sc_pad_28fdsoi_pus_t * pus, sc_bool_t *pke,
+ sc_bool_t *pue);
/*!
* This function configures the compensation control specific to 28FDSOI.
@@ -522,8 +533,9 @@ sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
* operation (e.g. some Ethernet pads).
*/
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
- uint8_t compen, bool fastfrz, uint8_t rasrcp, uint8_t rasrcn,
- bool nasrc_sel, bool psw_ovr);
+ uint8_t compen, sc_bool_t fastfrz,
+ uint8_t rasrcp, uint8_t rasrcn,
+ sc_bool_t nasrc_sel, sc_bool_t psw_ovr);
/*!
* This function gets the compensation control specific to 28FDSOI.
@@ -549,11 +561,13 @@ sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
- uint8_t *compen, bool *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
- bool *nasrc_sel, bool *compok, uint8_t *nasrc, bool *psw_ovr);
+ uint8_t *compen, sc_bool_t *fastfrz,
+ uint8_t *rasrcp, uint8_t *rasrcn,
+ sc_bool_t *nasrc_sel, sc_bool_t *compok,
+ uint8_t *nasrc, sc_bool_t *psw_ovr);
/* @} */
-#endif /* _SC_PAD_API_H */
+#endif /* SC_PAD_API_H */
/**@}*/
diff --git a/plat/imx/common/include/sci/svc/pm/api.h b/plat/imx/common/include/sci/svc/pm/api.h
index 18c0a69c..b12c03e3 100644
--- a/plat/imx/common/include/sci/svc/pm/api.h
+++ b/plat/imx/common/include/sci/svc/pm/api.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,8 +17,8 @@
* @{
*/
-#ifndef _SC_PM_API_H
-#define _SC_PM_API_H
+#ifndef SC_PM_API_H
+#define SC_PM_API_H
/* Includes */
@@ -31,10 +31,10 @@
* @name Defines for type widths
*/
/*@{*/
-#define SC_PM_POWER_MODE_W 2 /*!< Width of sc_pm_power_mode_t */
-#define SC_PM_CLOCK_MODE_W 3 /*!< Width of sc_pm_clock_mode_t */
-#define SC_PM_RESET_TYPE_W 2 /*!< Width of sc_pm_reset_type_t */
-#define SC_PM_RESET_REASON_W 3 /*!< Width of sc_pm_reset_reason_t */
+#define SC_PM_POWER_MODE_W 2 /* Width of sc_pm_power_mode_t */
+#define SC_PM_CLOCK_MODE_W 3 /* Width of sc_pm_clock_mode_t */
+#define SC_PM_RESET_TYPE_W 2 /* Width of sc_pm_reset_type_t */
+#define SC_PM_RESET_REASON_W 3 /* Width of sc_pm_reset_reason_t */
/*@}*/
/*!
@@ -47,92 +47,114 @@
* @name Defines for ALL parameters
*/
/*@{*/
-#define SC_PM_CLK_ALL UINT8_MAX /*!< All clocks */
+#define SC_PM_CLK_ALL UINT8_MAX /* All clocks */
/*@}*/
/*!
* @name Defines for sc_pm_power_mode_t
*/
/*@{*/
-#define SC_PM_PW_MODE_OFF 0 /*!< Power off */
-#define SC_PM_PW_MODE_STBY 1 /*!< Power in standby */
-#define SC_PM_PW_MODE_LP 2 /*!< Power in low-power */
-#define SC_PM_PW_MODE_ON 3 /*!< Power on */
+#define SC_PM_PW_MODE_OFF 0U /* Power off */
+#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
+#define SC_PM_PW_MODE_LP 2U /* Power in low-power */
+#define SC_PM_PW_MODE_ON 3U /* Power on */
/*@}*/
/*!
* @name Defines for sc_pm_clk_t
*/
/*@{*/
-#define SC_PM_CLK_SLV_BUS 0 /*!< Slave bus clock */
-#define SC_PM_CLK_MST_BUS 1 /*!< Master bus clock */
-#define SC_PM_CLK_PER 2 /*!< Peripheral clock */
-#define SC_PM_CLK_PHY 3 /*!< Phy clock */
-#define SC_PM_CLK_MISC 4 /*!< Misc clock */
-#define SC_PM_CLK_MISC0 0 /*!< Misc 0 clock */
-#define SC_PM_CLK_MISC1 1 /*!< Misc 1 clock */
-#define SC_PM_CLK_MISC2 2 /*!< Misc 2 clock */
-#define SC_PM_CLK_MISC3 3 /*!< Misc 3 clock */
-#define SC_PM_CLK_MISC4 4 /*!< Misc 4 clock */
-#define SC_PM_CLK_CPU 2 /*!< CPU clock */
-#define SC_PM_CLK_PLL 4 /*!< PLL */
-#define SC_PM_CLK_BYPASS 4 /*!< Bypass clock */
+#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */
+#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */
+#define SC_PM_CLK_PER 2U /* Peripheral clock */
+#define SC_PM_CLK_PHY 3U /* Phy clock */
+#define SC_PM_CLK_MISC 4U /* Misc clock */
+#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */
+#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */
+#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */
+#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */
+#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */
+#define SC_PM_CLK_CPU 2U /* CPU clock */
+#define SC_PM_CLK_PLL 4U /* PLL */
+#define SC_PM_CLK_BYPASS 4U /* Bypass clock */
/*@}*/
/*!
* @name Defines for sc_pm_clk_mode_t
*/
/*@{*/
-#define SC_PM_CLK_MODE_ROM_INIT 0 /*!< Clock is initialized by ROM. */
-#define SC_PM_CLK_MODE_OFF 1 /*!< Clock is disabled */
-#define SC_PM_CLK_MODE_ON 2 /*!< Clock is enabled. */
-#define SC_PM_CLK_MODE_AUTOGATE_SW 3 /*!< Clock is in SW autogate mode */
-#define SC_PM_CLK_MODE_AUTOGATE_HW 4 /*!< Clock is in HW autogate mode */
-#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5 /*!< Clock is in SW-HW autogate mode */
+#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */
+#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */
+#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */
+#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */
+#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
+#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
/*@}*/
/*!
* @name Defines for sc_pm_clk_parent_t
*/
/*@{*/
-#define SC_PM_PARENT_XTAL 0 /*!< Parent is XTAL. */
-#define SC_PM_PARENT_PLL0 1 /*!< Parent is PLL0 */
-#define SC_PM_PARENT_PLL1 2 /*!< Parent is PLL1 or PLL0/2 */
-#define SC_PM_PARENT_PLL2 3 /*!< Parent in PLL2 or PLL0/4 */
-#define SC_PM_PARENT_BYPS 4 /*!< Parent is a bypass clock. */
+#define SC_PM_PARENT_XTAL 0U /* Parent is XTAL. */
+#define SC_PM_PARENT_PLL0 1U /* Parent is PLL0 */
+#define SC_PM_PARENT_PLL1 2U /* Parent is PLL1 or PLL0/2 */
+#define SC_PM_PARENT_PLL2 3U /* Parent in PLL2 or PLL0/4 */
+#define SC_PM_PARENT_BYPS 4U /* Parent is a bypass clock. */
/*@}*/
/*!
* @name Defines for sc_pm_reset_type_t
*/
/*@{*/
-#define SC_PM_RESET_TYPE_COLD 0 /*!< Cold reset */
-#define SC_PM_RESET_TYPE_WARM 1 /*!< Warm reset */
-#define SC_PM_RESET_TYPE_BOARD 2 /*!< Board reset */
+#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */
+#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */
+#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_reset_cause_t
+ */
+/*@{*/
+#define SC_PM_RESET_CAUSE_TEMP 0U /* Reset due to temp panic alarm */
+#define SC_PM_RESET_CAUSE_FAULT 1U /* Reset due to fault exception */
+#define SC_PM_RESET_CAUSE_IRQ 2U /* Reset due to SCU reset IRQ */
+#define SC_PM_RESET_CAUSE_WDOG 3U /* Reset due to SW WDOG */
+#define SC_PM_RESET_CAUSE_API 4U /* Reset due to pm_reset() or monitor */
/*@}*/
/*!
* @name Defines for sc_pm_reset_reason_t
*/
/*@{*/
-#define SC_PM_RESET_REASON_POR 0 /*!< Power on reset */
-#define SC_PM_RESET_REASON_WARM 1 /*!< Warm reset */
-#define SC_PM_RESET_REASON_SW 2 /*!< Software reset */
-#define SC_PM_RESET_REASON_WDOG 3 /*!< Watchdog reset */
-#define SC_PM_RESET_REASON_LOCKUP 4 /*!< Lockup reset */
-#define SC_PM_RESET_REASON_TAMPER 5 /*!< Tamper reset */
-#define SC_PM_RESET_REASON_TEMP 6 /*!< Temp reset */
-#define SC_PM_RESET_REASON_LOW_VOLT 7 /*!< Low voltage reset */
+#define SC_PM_RESET_REASON_POR 0U /* Power on reset */
+#define SC_PM_RESET_REASON_WARM 1U /* Warm reset */
+#define SC_PM_RESET_REASON_SW 2U /* Software reset */
+#define SC_PM_RESET_REASON_WDOG 3U /* Watchdog reset */
+#define SC_PM_RESET_REASON_LOCKUP 4U /* Lockup reset */
+#define SC_PM_RESET_REASON_TAMPER 5U /* Tamper reset */
+#define SC_PM_RESET_REASON_TEMP 6U /* Temp reset */
+#define SC_PM_RESET_REASON_LOW_VOLT 7U /* Low voltage reset */
/*@}*/
/*!
* @name Defines for sc_pm_sys_if_t
*/
/*@{*/
-#define SC_PM_SYS_IF_INTERCONNECT 0 /*!< System interconnect */
-#define SC_PM_SYS_IF_MU 1 /*!< AP -> SCU message units */
-#define SC_PM_SYS_IF_OCMEM 2 /*!< On-chip memory (ROM/OCRAM) */
-#define SC_PM_SYS_IF_DDR 3 /*!< DDR memory */
+#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */
+#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */
+#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */
+#define SC_PM_SYS_IF_DDR 3U /* DDR memory */
+/*@}*/
+
+/*!
+ * @name Defines for sc_pm_wake_src_t
+ */
+/*@{*/
+#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */
+#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
+#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */
/*@}*/
/* Types */
@@ -170,6 +192,11 @@ typedef uint32_t sc_pm_clock_rate_t;
typedef uint8_t sc_pm_reset_type_t;
/*!
+ * This type is used to declare a desired reset type.
+ */
+typedef uint8_t sc_pm_reset_cause;
+
+/*!
* This type is used to declare a reason for a reset.
*/
typedef uint8_t sc_pm_reset_reason_t;
@@ -179,6 +206,11 @@ typedef uint8_t sc_pm_reset_reason_t;
*/
typedef uint8_t sc_pm_sys_if_t;
+/*!
+ * This type is used to specify a wake source for CPU resources.
+ */
+typedef uint8_t sc_pm_wake_src_t;
+
/* Functions */
/*!
@@ -217,13 +249,13 @@ sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode);
* - SC_ERR_NOACCESS if caller's partition is not the owner or
* parent of \a pt
*
- * All resources owned by \a pt that are on will have their power
- * mode changed to \a mode.
- *
- * @see sc_pm_set_resource_power_mode().
+ * The power mode of the partitions is a max power any resource will
+ * be set to. Calling this will result in all resources owned
+ * by \a pt to have their power changed to the lower of \a mode or the
+ * individual resource mode set using sc_pm_set_resource_power_mode().
*/
sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_pm_power_mode_t mode);
+ sc_pm_power_mode_t mode);
/*!
* This function gets the power mode of a partition.
@@ -238,7 +270,7 @@ sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
* - SC_ERR_PARM if invalid partition
*/
sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_pm_power_mode_t *mode);
+ sc_pm_power_mode_t *mode);
/*!
* This function sets the power mode of a resource.
@@ -254,18 +286,26 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner
*
- * Resources set to SC_PM_PW_MODE_ON will reflect the
- * power mode of the partition and will change as that changes.
+ * This function will record the individual resource power mode
+ * and change it if the requested mode is lower than or equal to the
+ * partition power mode set with sc_pm_set_partition_power_mode().
+ * In other words, the power mode of the resource will be the minimum
+ * of the resource power mode and the partition power mode.
*
* Note some resources are still not accessible even when powered up if bus
* transactions go through a fabric not powered up. Examples of this are
* resources in display and capture subsystems which require the display
* controller or the imaging subsytem to be powered up first.
*
- * @see sc_pm_set_partition_power_mode().
+ * Not that resources are grouped into power domains by the underlying
+ * hardware. If any resource in the domain is on, the entire power domain
+ * will be on. Other power domains required to access the resource will
+ * also be turned on. Clocks required to access the peripheral will be
+ * turned on. Refer to the SoC RM for more info on power domains and access
+ * infrastructure (bus fabrics, clock domains, etc.).
*/
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_power_mode_t mode);
+ sc_pm_power_mode_t mode);
/*!
* This function gets the power mode of a resource.
@@ -280,7 +320,7 @@ sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
* returned does not reflect the power mode of the partition..
*/
sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_power_mode_t *mode);
+ sc_pm_power_mode_t *mode);
/*!
* This function requests the low power mode some of the resources
@@ -295,7 +335,7 @@ sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
- * @param[out] mode pointer to return power mode
+ * @param[in] mode power mode to apply
*
* @return Returns an error code (SC_ERR_NONE = success).
*
@@ -304,6 +344,30 @@ sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode);
/*!
+ * This function requests low-power mode entry for CPU/cluster
+ * resources. This API is only valid for the following resources:
+ * SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x,
+ * SC_R_CCI. For all other resources it will return SC_ERR_PARAM.
+ * For individual core resources, the specified power mode
+ * and wake source will be applied after the core has entered
+ * WFI. For cluster resources, the specified power mode is
+ * applied after all cores in the cluster have entered low-power mode.
+ * For multicluster resources, the specified power mode is applied
+ * after all clusters have reached low-power mode.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] resource ID of the resource
+ * @param[in] mode power mode to apply
+ * @param[in] wake_src wake source for low-power exit
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ */
+sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_power_mode_t mode,
+ sc_pm_wake_src_t wake_src);
+
+/*!
* This function is used to set the resume address of a CPU.
*
* @param[in] ipc IPC handle
@@ -321,6 +385,25 @@ sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
sc_faddr_t address);
/*!
+ * This function is used to set parameters for CPU resume from
+ * low-power mode.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] resource ID of the CPU resource
+ * @param[in] isPrimary set SC_TRUE if primary wake CPU
+ * @param[in] address 64-bit resume address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid resource or address,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ * resource (CPU) owner
+ */
+sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_bool_t isPrimary, sc_faddr_t address);
+
+/*!
* This function requests the power mode configuration for system-level
* interfaces including messaging units, interconnect, and memories. This API
* is only valid for the following resources : SC_R_A53, SC_R_A72, and
@@ -338,7 +421,9 @@ sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
*
*/
sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm);
+ sc_pm_sys_if_t sys_if,
+ sc_pm_power_mode_t hpm,
+ sc_pm_power_mode_t lpm);
/* @} */
@@ -367,7 +452,7 @@ sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
* Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
*/
sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
+ sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
/*!
* This function gets the rate of a resource's clock/PLL.
@@ -388,7 +473,7 @@ sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
* Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
*/
sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
+ sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
/*!
* This function enables/disables a resource's clock.
@@ -396,9 +481,15 @@ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] clk clock to affect
- * @param[in] enable enable if true; otherwise disabled
+ * @param[in] enable enable if SC_TRUE; otherwise disabled
* @param[in] autog HW auto clock gating
*
+ * If \a resource is SC_R_ALL then all resources owned will be affected.
+ * No error will be returned.
+ *
+ * If \a clk is SC_PM_CLK_ALL, then an error will be returned if any
+ * of the available clocks returns an error.
+ *
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
@@ -410,7 +501,7 @@ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
*/
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_clk_t clk, bool enable, bool autog);
+ sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
/*!
* This function sets the parent of a resource's clock.
@@ -429,11 +520,12 @@ sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
* or parent of the owner,
* - SC_ERR_UNAVAILABLE if clock not applicable to this resource
* - SC_ERR_BUSY if clock is currently enabled.
+ * - SC_ERR_NOPOWER if resource not powered
*
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
*/
sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
+ sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
/*!
* This function gets the parent of a resource's clock.
@@ -454,7 +546,7 @@ sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
*/
sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
+ sc_pm_clk_t clk, sc_pm_clk_parent_t * parent);
/* @} */
@@ -509,8 +601,8 @@ sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
* partition to boot
*/
sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
- sc_rsrc_t resource_mu, sc_rsrc_t resource_dev);
+ sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+ sc_rsrc_t resource_mu, sc_rsrc_t resource_dev);
/*!
* This function is used to reboot the caller's partition.
@@ -566,14 +658,14 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
* that are not reset.
*/
sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_pm_reset_type_t type);
+ sc_pm_reset_type_t type);
/*!
* This function is used to start/stop a CPU.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the CPU resource
- * @param[in] enable start if true; otherwise stop
+ * @param[in] enable start if SC_TRUE; otherwise stop
* @param[in] address 64-bit boot address
*
* @return Returns an error code (SC_ERR_NONE = success).
@@ -583,11 +675,11 @@ sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
* resource (CPU) owner
*/
-sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
- sc_faddr_t address);
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
+ sc_faddr_t address);
/* @} */
-#endif /* _SC_PM_API_H */
+#endif /* SC_PM_API_H */
/**@}*/
diff --git a/plat/imx/common/include/sci/svc/rm/api.h b/plat/imx/common/include/sci/svc/rm/api.h
index 1fcbee58..9c42087b 100644
--- a/plat/imx/common/include/sci/svc/rm/api.h
+++ b/plat/imx/common/include/sci/svc/rm/api.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,11 +14,13 @@
*
* Module for the Resource Management (RM) service.
*
+ * @includedoc rm/details.dox
+ *
* @{
*/
-#ifndef _SC_RM_API_H
-#define _SC_RM_API_H
+#ifndef SC_RM_API_H
+#define SC_RM_API_H
/* Includes */
@@ -30,44 +32,44 @@
* @name Defines for type widths
*/
/*@{*/
-#define SC_RM_PARTITION_W 5 /*!< Width of sc_rm_pt_t */
-#define SC_RM_MEMREG_W 6 /*!< Width of sc_rm_mr_t */
-#define SC_RM_DID_W 4 /*!< Width of sc_rm_did_t */
-#define SC_RM_SID_W 6 /*!< Width of sc_rm_sid_t */
-#define SC_RM_SPA_W 2 /*!< Width of sc_rm_spa_t */
-#define SC_RM_PERM_W 3 /*!< Width of sc_rm_perm_t */
+#define SC_RM_PARTITION_W 5 /* Width of sc_rm_pt_t */
+#define SC_RM_MEMREG_W 6 /* Width of sc_rm_mr_t */
+#define SC_RM_DID_W 4 /* Width of sc_rm_did_t */
+#define SC_RM_SID_W 6 /* Width of sc_rm_sid_t */
+#define SC_RM_SPA_W 2 /* Width of sc_rm_spa_t */
+#define SC_RM_PERM_W 3 /* Width of sc_rm_perm_t */
/*@}*/
/*!
* @name Defines for ALL parameters
*/
/*@{*/
-#define SC_RM_PT_ALL UINT8_MAX /*!< All partitions */
-#define SC_RM_MR_ALL UINT8_MAX /*!< All memory regions */
+#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /* All partitions */
+#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /* All memory regions */
/*@}*/
/*!
* @name Defines for sc_rm_spa_t
*/
/*@{*/
-#define SC_RM_SPA_PASSTHRU 0 /*!< Pass through (attribute driven by master) */
-#define SC_RM_SPA_PASSSID 1 /*!< Pass through and output on SID */
-#define SC_RM_SPA_ASSERT 2 /*!< Assert (force to be secure/privileged) */
-#define SC_RM_SPA_NEGATE 3 /*!< Negate (force to be non-secure/user) */
+#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */
+#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */
+#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */
+#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
/*@}*/
/*!
* @name Defines for sc_rm_perm_t
*/
/*@{*/
-#define SC_RM_PERM_NONE 0 /*!< No access */
-#define SC_RM_PERM_SEC_R 1 /*!< Secure RO */
-#define SC_RM_PERM_SECPRIV_RW 2 /*!< Secure privilege R/W */
-#define SC_RM_PERM_SEC_RW 3 /*!< Secure R/W */
-#define SC_RM_PERM_NSPRIV_R 4 /*!< Secure R/W, non-secure privilege RO */
-#define SC_RM_PERM_NS_R 5 /*!< Secure R/W, non-secure RO */
-#define SC_RM_PERM_NSPRIV_RW 6 /*!< Secure R/W, non-secure privilege R/W */
-#define SC_RM_PERM_FULL 7 /*!< Full access */
+#define SC_RM_PERM_NONE 0U /* No access */
+#define SC_RM_PERM_SEC_R 1U /* Secure RO */
+#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */
+#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */
+#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
+#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
+#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
+#define SC_RM_PERM_FULL 7U /* Full access */
/*@}*/
/* Types */
@@ -120,13 +122,13 @@ typedef uint8_t sc_rm_perm_t;
* @param[in] secure boolean indicating if this partition should be secure; only
* valid if caller is secure
* @param[in] isolated boolean indicating if this partition should be HW isolated
- * via XRDC; set true if new DID is desired
+ * via XRDC; set SC_TRUE if new DID is desired
* @param[in] restricted boolean indicating if this partition should be restricted; set
- * true if masters in this partition cannot create new partitions
+ * SC_TRUE if masters in this partition cannot create new partitions
* @param[in] grant boolean indicating if this partition should always grant
* access and control to the parent
* @param[in] coherent boolean indicating if this partition is coherent;
- * set true if only this partition will contain both AP clusters
+ * set SC_TRUE if only this partition will contain both AP clusters
* and they will be coherent via the CCI
*
* @return Returns an error code (SC_ERR_NONE = success).
@@ -145,8 +147,9 @@ typedef uint8_t sc_rm_perm_t;
* memory without isolating the peripheral interface of the master or the API
* controls of that master.
*/
-sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
- bool isolated, bool restricted, bool grant, bool coherent);
+sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
+ sc_bool_t isolated, sc_bool_t restricted,
+ sc_bool_t grant, sc_bool_t coherent);
/*!
* This function makes a partition confidential.
@@ -168,7 +171,7 @@ sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
* If retroactive, then all resources owned by other partitions will have
* access rights for this partition removed, even if locked.
*/
-sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, bool retro);
+sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro);
/*!
* This function frees a partition and assigns all resources to the caller.
@@ -221,8 +224,7 @@ sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc);
* Assumes no assigned resources or memory regions yet! The number of static
* DID is fixed by the SC at boot.
*/
-sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_rm_did_t did);
+sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did);
/*!
* This function locks a partition.
@@ -267,8 +269,7 @@ sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
* - SC_ERR_LOCKED if either partition is locked
*/
-sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_rm_pt_t pt_parent);
+sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
/*!
* This function moves all movable resources/pads owned by a source partition
@@ -298,7 +299,7 @@ sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt,
* - SC_ERR_LOCKED if either partition is locked
*/
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
- bool move_rsrc, bool move_pads);
+ sc_bool_t move_rsrc, sc_bool_t move_pads);
/* @} */
@@ -331,8 +332,7 @@ sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
* of the owner,
* - SC_ERR_LOCKED if the owning partition or \a pt is locked
*/
-sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_rsrc_t resource);
+sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
/*!
* This function flags resources as movable or not.
@@ -340,7 +340,7 @@ sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
* @param[in] ipc IPC handle
* @param[in] resource_fst first resource for which flag should be set
* @param[in] resource_lst last resource for which flag should be set
- * @param[in] movable movable flag (true) is movable
+ * @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
@@ -355,7 +355,7 @@ sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
* resources from moving.
*/
sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
- sc_rsrc_t resource_lst, bool movable);
+ sc_rsrc_t resource_lst, sc_bool_t movable);
/*!
* This function flags all of a subsystem's resources as movable
@@ -363,7 +363,7 @@ sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
*
* @param[in] ipc IPC handle
* @param[in] resource resource to use to identify subsystem
- * @param[in] movable movable flag (true) is movable
+ * @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
@@ -374,7 +374,7 @@ sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
* resources owned by the caller are set.
*/
sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
- bool movable);
+ sc_bool_t movable);
/*!
* This function sets attributes for a resource which is a bus master (i.e.
@@ -399,7 +399,8 @@ sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
* changed if the caller's partition is secure.
*/
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_rm_spa_t sa, sc_rm_spa_t pa, bool smmu_bypass);
+ sc_rm_spa_t sa, sc_rm_spa_t pa,
+ sc_bool_t smmu_bypass);
/*!
* This function sets the StreamID for a resource which is a bus master (i.e.
@@ -423,7 +424,7 @@ sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
* bypass.
*/
sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_rm_sid_t sid);
+ sc_rm_sid_t sid);
/*!
* This function sets access permissions for a peripheral resource.
@@ -446,7 +447,7 @@ sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
* peripheral based on the attributes of a transaction from bus master.
*/
sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_rm_pt_t pt, sc_rm_perm_t perm);
+ sc_rm_pt_t pt, sc_rm_perm_t perm);
/*!
* This function gets ownership status of a resource.
@@ -454,11 +455,11 @@ sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
- * @return Returns a boolean (true if caller's partition owns the resource).
+ * @return Returns a boolean (SC_TRUE if caller's partition owns the resource).
*
- * If \a resource is out of range then false is returned.
+ * If \a resource is out of range then SC_FALSE is returned.
*/
-bool sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
+sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to test if a resource is a bus master.
@@ -466,11 +467,11 @@ bool sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
- * @return Returns a boolean (true if the resource is a bus master).
+ * @return Returns a boolean (SC_TRUE if the resource is a bus master).
*
- * If \a resource is out of range then false is returned.
+ * If \a resource is out of range then SC_FALSE is returned.
*/
-bool sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
+sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to test if a resource is a peripheral.
@@ -478,11 +479,11 @@ bool sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
- * @return Returns a boolean (true if the resource is a peripheral).
+ * @return Returns a boolean (SC_TRUE if the resource is a peripheral).
*
- * If \a resource is out of range then false is returned.
+ * If \a resource is out of range then SC_FALSE is returned.
*/
-bool sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
+sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to obtain info about a resource.
@@ -497,7 +498,7 @@ bool sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
* - SC_PARM if \a resource is out of range
*/
sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_rm_sid_t *sid);
+ sc_rm_sid_t *sid);
/* @} */
@@ -532,7 +533,7 @@ sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
* caller to access.
*/
sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
- sc_faddr_t addr_start, sc_faddr_t addr_end);
+ sc_faddr_t addr_start, sc_faddr_t addr_end);
/*!
* This function requests that the SC split a memory region.
@@ -559,7 +560,8 @@ sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
* Note the new region must start or end on the split region.
*/
sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
- sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end);
+ sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
+ sc_faddr_t addr_end);
/*!
* This function frees a memory region.
@@ -643,7 +645,7 @@ sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr);
* memory region based on the attributes of a transaction from bus master.
*/
sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
- sc_rm_pt_t pt, sc_rm_perm_t perm);
+ sc_rm_pt_t pt, sc_rm_perm_t perm);
/*!
* This function gets ownership status of a memory region.
@@ -651,12 +653,12 @@ sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
* @param[in] ipc IPC handle
* @param[in] mr handle of memory region to check
*
- * @return Returns a boolean (true if caller's partition owns the
+ * @return Returns a boolean (SC_TRUE if caller's partition owns the
* memory region).
*
- * If \a mr is out of range then false is returned.
+ * If \a mr is out of range then SC_FALSE is returned.
*/
-bool sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
+sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
/*!
* This function is used to obtain info about a memory region.
@@ -672,7 +674,7 @@ bool sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
* - SC_PARM if \a mr is out of range
*/
sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
- sc_faddr_t *addr_start, sc_faddr_t *addr_end);
+ sc_faddr_t *addr_start, sc_faddr_t *addr_end);
/* @} */
@@ -706,7 +708,7 @@ sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
* @param[in] ipc IPC handle
* @param[in] pad_fst first pad for which flag should be set
* @param[in] pad_lst last pad for which flag should be set
- * @param[in] movable movable flag (true) is movable
+ * @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
@@ -721,7 +723,7 @@ sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
* pads from moving.
*/
sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
- sc_pad_t pad_lst, bool movable);
+ sc_pad_t pad_lst, sc_bool_t movable);
/*!
* This function gets ownership status of a pad.
@@ -729,11 +731,11 @@ sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
* @param[in] ipc IPC handle
* @param[in] pad pad to check
*
- * @return Returns a boolean (true if caller's partition owns the pad).
+ * @return Returns a boolean (SC_TRUE if caller's partition owns the pad).
*
- * If \a pad is out of range then false is returned.
+ * If \a pad is out of range then SC_FALSE is returned.
*/
-bool sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
+sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
/* @} */
@@ -751,6 +753,6 @@ void sc_rm_dump(sc_ipc_t ipc);
/* @} */
-#endif /* _SC_RM_API_H */
+#endif /* SC_RM_API_H */
/**@}*/
diff --git a/plat/imx/common/include/sci/svc/timer/api.h b/plat/imx/common/include/sci/svc/timer/api.h
index a4adc34a..276e31d6 100644
--- a/plat/imx/common/include/sci/svc/timer/api.h
+++ b/plat/imx/common/include/sci/svc/timer/api.h
@@ -1,31 +1,8 @@
/*
- * Copyright 2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of NXP nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
*/
/*!
@@ -41,8 +18,8 @@
* @{
*/
-#ifndef _SC_TIMER_API_H
-#define _SC_TIMER_API_H
+#ifndef SC_TIMER_API_H
+#define SC_TIMER_API_H
/* Includes */
@@ -55,18 +32,18 @@
* @name Defines for type widths
*/
/*@{*/
-#define SC_TIMER_ACTION_W 3 /*!< Width of sc_timer_wdog_action_t */
+#define SC_TIMER_ACTION_W 3 /* Width of sc_timer_wdog_action_t */
/*@}*/
/*!
* @name Defines for sc_timer_wdog_action_t
*/
/*@{*/
-#define SC_TIMER_WDOG_ACTION_PARTITION 0 /*!< Reset partition */
-#define SC_TIMER_WDOG_ACTION_WARM 1 /*!< Warm reset system */
-#define SC_TIMER_WDOG_ACTION_COLD 2 /*!< Cold reset system */
-#define SC_TIMER_WDOG_ACTION_BOARD 3 /*!< Reset board */
-#define SC_TIMER_WDOG_ACTION_IRQ 4 /*!< Only generate IRQs */
+#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */
+#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */
+#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */
+#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */
+#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */
/*@}*/
/* Types */
@@ -99,8 +76,7 @@ typedef uint32_t sc_timer_wdog_time_t;
* @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED
* = locked).
*/
-sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc,
- sc_timer_wdog_time_t timeout);
+sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout);
/*!
* This function sets the watchdog pre-timeout in milliseconds. If not
@@ -117,7 +93,7 @@ sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc,
* @return Returns an error code (SC_ERR_NONE = success).
*/
sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
- sc_timer_wdog_time_t pre_timeout);
+ sc_timer_wdog_time_t pre_timeout);
/*!
* This function starts the watchdog.
@@ -130,7 +106,7 @@ sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
* If \a lock is set then the watchdog cannot be stopped or the timeout
* period changed.
*/
-sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, bool lock);
+sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock);
/*!
* This function stops the watchdog if it is not locked.
@@ -156,7 +132,7 @@ sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc);
* This function gets the status of the watchdog. All arguments are
* in milliseconds.
*
- * @param[in] ipc IPC handle
+ * @param[in] ipc IPC handle
* @param[out] timeout pointer to return the timeout
* @param[out] max_timeout pointer to return the max timeout
* @param[out] remaining_time pointer to return the time remaining
@@ -165,7 +141,8 @@ sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc);
* @return Returns an error code (SC_ERR_NONE = success).
*/
sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
- sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout,
+ sc_timer_wdog_time_t *timeout,
+ sc_timer_wdog_time_t *max_timeout,
sc_timer_wdog_time_t *remaining_time);
/*!
@@ -181,8 +158,10 @@ sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
*
* @return Returns an error code (SC_ERR_NONE = success).
*/
-sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, bool *enb,
- sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time);
+sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt,
+ sc_bool_t *enb,
+ sc_timer_wdog_time_t *timeout,
+ sc_timer_wdog_time_t *remaining_time);
/*!
* This function configures the action to be taken when a watchdog
@@ -230,7 +209,8 @@ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
* - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner
*/
sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
- uint8_t day, uint8_t hour, uint8_t min, uint8_t sec);
+ uint8_t day, uint8_t hour, uint8_t min,
+ uint8_t sec);
/*!
* This function gets the RTC time.
@@ -246,7 +226,8 @@ sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
* @return Returns an error code (SC_ERR_NONE = success).
*/
sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
- uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec);
+ uint8_t *day, uint8_t *hour, uint8_t *min,
+ uint8_t *sec);
/*!
* This function gets the RTC time in seconds since 1/1/1970.
@@ -277,7 +258,35 @@ sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec);
* - SC_ERR_PARM if invalid time/date parameters
*/
sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
- uint8_t day, uint8_t hour, uint8_t min, uint8_t sec);
+ uint8_t day, uint8_t hour, uint8_t min,
+ uint8_t sec);
+
+/*!
+ * This function sets the RTC alarm.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] sec period in seconds
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid time/date parameters
+ */
+sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec);
+
+/*!
+ * This function sets the RTC alarm.
+ *
+ * @param[in] ipc IPC handle
+ *
+ * Note this alarm setting clears when the alarm is triggered.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid time/date parameters
+ */
+sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc);
/*!
* This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM
@@ -296,6 +305,6 @@ sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count);
/* @} */
-#endif /* _SC_TIMER_API_H */
+#endif /* SC_TIMER_API_H */
/**@}*/
diff --git a/plat/imx/common/include/sci/types.h b/plat/imx/common/include/sci/types.h
index 6f8021d5..426e806e 100644
--- a/plat/imx/common/include/sci/types.h
+++ b/plat/imx/common/include/sci/types.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,8 +9,8 @@
* Header file containing types used across multiple service APIs.
*/
-#ifndef _SC_TYPES_H
-#define _SC_TYPES_H
+#ifndef SC_TYPES_H
+#define SC_TYPES_H
/* Includes */
@@ -23,119 +23,757 @@
* @name Defines for common frequencies
*/
/*@{*/
-#define SC_32KHZ 32768 /*!< 32KHz */
-#define SC_10MHZ 10000000 /*!< 10MHz */
-#define SC_20MHZ 20000000 /*!< 20MHz */
-#define SC_25MHZ 25000000 /*!< 25MHz */
-#define SC_27MHZ 27000000 /*!< 27MHz */
-#define SC_40MHZ 40000000 /*!< 40MHz */
-#define SC_45MHZ 45000000 /*!< 45MHz */
-#define SC_50MHZ 50000000 /*!< 50MHz */
-#define SC_60MHZ 60000000 /*!< 60MHz */
-#define SC_66MHZ 66666666 /*!< 66MHz */
-#define SC_74MHZ 74250000 /*!< 74.25MHz */
-#define SC_80MHZ 80000000 /*!< 80MHz */
-#define SC_83MHZ 83333333 /*!< 83MHz */
-#define SC_84MHZ 84375000 /*!< 84.37MHz */
-#define SC_100MHZ 100000000 /*!< 100MHz */
-#define SC_125MHZ 125000000 /*!< 125MHz */
-#define SC_133MHZ 133333333 /*!< 133MHz */
-#define SC_135MHZ 135000000 /*!< 135MHz */
-#define SC_150MHZ 150000000 /*!< 150MHz */
-#define SC_160MHZ 160000000 /*!< 160MHz */
-#define SC_166MHZ 166666666 /*!< 160MHz */
-#define SC_175MHZ 175000000 /*!< 175MHz */
-#define SC_180MHZ 180000000 /*!< 180MHz */
-#define SC_200MHZ 200000000 /*!< 200MHz */
-#define SC_250MHZ 250000000 /*!< 250MHz */
-#define SC_266MHZ 266666666 /*!< 266MHz */
-#define SC_300MHZ 300000000 /*!< 300MHz */
-#define SC_320MHZ 320000000 /*!< 320MHz */
-#define SC_325MHZ 325000000 /*!< 325MHz */
-#define SC_333MHZ 333333333 /*!< 333MHz */
-#define SC_350MHZ 350000000 /*!< 350MHz */
-#define SC_372MHZ 372000000 /*!< 372MHz */
-#define SC_375MHZ 375000000 /*!< 375MHz */
-#define SC_400MHZ 400000000 /*!< 400MHz */
-#define SC_500MHZ 500000000 /*!< 500MHz */
-#define SC_594MHZ 594000000 /*!< 594MHz */
-#define SC_650MHZ 650000000 /*!< 650MHz */
-#define SC_667MHZ 666666667 /*!< 667MHz */
-#define SC_675MHZ 675000000 /*!< 675MHz */
-#define SC_700MHZ 700000000 /*!< 700MHz */
-#define SC_720MHZ 720000000 /*!< 720MHz */
-#define SC_750MHZ 750000000 /*!< 750MHz */
-#define SC_800MHZ 800000000 /*!< 800MHz */
-#define SC_850MHZ 850000000 /*!< 850MHz */
-#define SC_900MHZ 900000000 /*!< 900MHz */
-#define SC_1000MHZ 1000000000 /*!< 1GHz */
-#define SC_1056MHZ 1056000000 /*!< 1.056GHz */
-#define SC_1188MHZ 1188000000 /*!< 1.188GHz */
-#define SC_1260MHZ 1260000000 /*!< 1.26GHz */
-#define SC_1300MHZ 1300000000 /*!< 1.3GHz */
-#define SC_1400MHZ 1400000000 /*!< 1.4GHz */
-#define SC_1500MHZ 1500000000 /*!< 1.5GHz */
-#define SC_1600MHZ 1600000000 /*!< 1.6GHz */
-#define SC_1800MHZ 1800000000 /*!< 1.8GHz */
-#define SC_2000MHZ 2000000000 /*!< 2.0GHz */
-#define SC_2112MHZ 2112000000 /*!< 2.12GHz */
-
+#define SC_32KHZ 32768U /* 32KHz */
+#define SC_10MHZ 10000000U /* 10MHz */
+#define SC_20MHZ 20000000U /* 20MHz */
+#define SC_25MHZ 25000000U /* 25MHz */
+#define SC_27MHZ 27000000U /* 27MHz */
+#define SC_40MHZ 40000000U /* 40MHz */
+#define SC_45MHZ 45000000U /* 45MHz */
+#define SC_50MHZ 50000000U /* 50MHz */
+#define SC_60MHZ 60000000U /* 60MHz */
+#define SC_66MHZ 66666666U /* 66MHz */
+#define SC_74MHZ 74250000U /* 74.25MHz */
+#define SC_80MHZ 80000000U /* 80MHz */
+#define SC_83MHZ 83333333U /* 83MHz */
+#define SC_84MHZ 84375000U /* 84.37MHz */
+#define SC_100MHZ 100000000U /* 100MHz */
+#define SC_125MHZ 125000000U /* 125MHz */
+#define SC_133MHZ 133333333U /* 133MHz */
+#define SC_135MHZ 135000000U /* 135MHz */
+#define SC_150MHZ 150000000U /* 150MHz */
+#define SC_160MHZ 160000000U /* 160MHz */
+#define SC_166MHZ 166666666U /* 166MHz */
+#define SC_175MHZ 175000000U /* 175MHz */
+#define SC_180MHZ 180000000U /* 180MHz */
+#define SC_200MHZ 200000000U /* 200MHz */
+#define SC_250MHZ 250000000U /* 250MHz */
+#define SC_266MHZ 266666666U /* 266MHz */
+#define SC_300MHZ 300000000U /* 300MHz */
+#define SC_312MHZ 312500000U /* 312.5MHZ */
+#define SC_320MHZ 320000000U /* 320MHz */
+#define SC_325MHZ 325000000U /* 325MHz */
+#define SC_333MHZ 333333333U /* 333MHz */
+#define SC_350MHZ 350000000U /* 350MHz */
+#define SC_372MHZ 372000000U /* 372MHz */
+#define SC_375MHZ 375000000U /* 375MHz */
+#define SC_400MHZ 400000000U /* 400MHz */
+#define SC_500MHZ 500000000U /* 500MHz */
+#define SC_594MHZ 594000000U /* 594MHz */
+#define SC_625MHZ 625000000U /* 625MHz */
+#define SC_640MHZ 640000000U /* 640MHz */
+#define SC_650MHZ 650000000U /* 650MHz */
+#define SC_667MHZ 666666667U /* 667MHz */
+#define SC_675MHZ 675000000U /* 675MHz */
+#define SC_700MHZ 700000000U /* 700MHz */
+#define SC_720MHZ 720000000U /* 720MHz */
+#define SC_750MHZ 750000000U /* 750MHz */
+#define SC_800MHZ 800000000U /* 800MHz */
+#define SC_850MHZ 850000000U /* 850MHz */
+#define SC_900MHZ 900000000U /* 900MHz */
+#define SC_1000MHZ 1000000000U /* 1GHz */
+#define SC_1056MHZ 1056000000U /* 1.056GHz */
+#define SC_1188MHZ 1188000000U /* 1.188GHz */
+#define SC_1260MHZ 1260000000U /* 1.26GHz */
+#define SC_1280MHZ 1280000000U /* 1.28GHz */
+#define SC_1300MHZ 1300000000U /* 1.3GHz */
+#define SC_1400MHZ 1400000000U /* 1.4GHz */
+#define SC_1500MHZ 1500000000U /* 1.5GHz */
+#define SC_1600MHZ 1600000000U /* 1.6GHz */
+#define SC_1800MHZ 1800000000U /* 1.8GHz */
+#define SC_2000MHZ 2000000000U /* 2.0GHz */
+#define SC_2112MHZ 2112000000U /* 2.12GHz */
/*@}*/
/*!
* @name Defines for 24M related frequencies
*/
/*@{*/
-#define SC_8MHZ 8000000 /*!< 8MHz */
-#define SC_12MHZ 12000000 /*!< 12MHz */
-#define SC_19MHZ 19800000 /*!< 19.8MHz */
-#define SC_24MHZ 24000000 /*!< 24MHz */
-#define SC_48MHZ 48000000 /*!< 48MHz */
-#define SC_120MHZ 120000000 /*!< 120MHz */
-#define SC_132MHZ 132000000 /*!< 132MHz */
-#define SC_144MHZ 144000000 /*!< 144MHz */
-#define SC_192MHZ 192000000 /*!< 192MHz */
-#define SC_211MHZ 211200000 /*!< 211.2MHz */
-#define SC_240MHZ 240000000 /*!< 240MHz */
-#define SC_264MHZ 264000000 /*!< 264MHz */
-#define SC_352MHZ 352000000 /*!< 352MHz */
-#define SC_360MHZ 360000000 /*!< 360MHz */
-#define SC_384MHZ 384000000 /*!< 384MHz */
-#define SC_396MHZ 396000000 /*!< 396MHz */
-#define SC_432MHZ 432000000 /*!< 432MHz */
-#define SC_480MHZ 480000000 /*!< 480MHz */
-#define SC_600MHZ 600000000 /*!< 600MHz */
-#define SC_744MHZ 744000000 /*!< 744MHz */
-#define SC_792MHZ 792000000 /*!< 792MHz */
-#define SC_864MHZ 864000000 /*!< 864MHz */
-#define SC_960MHZ 960000000 /*!< 960MHz */
-#define SC_1056MHZ 1056000000 /*!< 1056MHz */
-#define SC_1200MHZ 1200000000 /*!< 1.2GHz */
-#define SC_1464MHZ 1464000000 /*!< 1.464GHz */
-#define SC_2400MHZ 2400000000 /*!< 2.4GHz */
+#define SC_8MHZ 8000000U /* 8MHz */
+#define SC_12MHZ 12000000U /* 12MHz */
+#define SC_19MHZ 19800000U /* 19.8MHz */
+#define SC_24MHZ 24000000U /* 24MHz */
+#define SC_48MHZ 48000000U /* 48MHz */
+#define SC_120MHZ 120000000U /* 120MHz */
+#define SC_132MHZ 132000000U /* 132MHz */
+#define SC_144MHZ 144000000U /* 144MHz */
+#define SC_192MHZ 192000000U /* 192MHz */
+#define SC_211MHZ 211200000U /* 211.2MHz */
+#define SC_240MHZ 240000000U /* 240MHz */
+#define SC_264MHZ 264000000U /* 264MHz */
+#define SC_352MHZ 352000000U /* 352MHz */
+#define SC_360MHZ 360000000U /* 360MHz */
+#define SC_384MHZ 384000000U /* 384MHz */
+#define SC_396MHZ 396000000U /* 396MHz */
+#define SC_432MHZ 432000000U /* 432MHz */
+#define SC_480MHZ 480000000U /* 480MHz */
+#define SC_600MHZ 600000000U /* 600MHz */
+#define SC_744MHZ 744000000U /* 744MHz */
+#define SC_792MHZ 792000000U /* 792MHz */
+#define SC_864MHZ 864000000U /* 864MHz */
+#define SC_960MHZ 960000000U /* 960MHz */
+#define SC_1056MHZ 1056000000U /* 1056MHz */
+#define SC_1200MHZ 1200000000U /* 1.2GHz */
+#define SC_1464MHZ 1464000000U /* 1.464GHz */
+#define SC_2400MHZ 2400000000U /* 2.4GHz */
/*@}*/
/*!
* @name Defines for A/V related frequencies
*/
/*@{*/
-#define SC_62MHZ 62937500 /*!< 62.9375MHz */
-#define SC_755MHZ 755250000 /*!< 755.25MHz */
+#define SC_62MHZ 62937500U /* 62.9375MHz */
+#define SC_755MHZ 755250000U /* 755.25MHz */
/*@}*/
/*!
* @name Defines for type widths
*/
/*@{*/
-#define SC_FADDR_W 36 /*!< Width of sc_faddr_t */
-#define SC_BOOL_W 1 /*!< Width of bool */
-#define SC_ERR_W 4 /*!< Width of sc_err_t */
-#define SC_RSRC_W 10 /*!< Width of sc_rsrc_t */
-#define SC_CTRL_W 6 /*!< Width of sc_ctrl_t */
+#define SC_FADDR_W 36U /* Width of sc_faddr_t */
+#define SC_BOOL_W 1U /* Width of sc_bool_t */
+#define SC_ERR_W 4U /* Width of sc_err_t */
+#define SC_RSRC_W 10U /* Width of sc_rsrc_t */
+#define SC_CTRL_W 6U /* Width of sc_ctrl_t */
+/*@}*/
+
+/*!
+ * @name Defines for sc_bool_t
+ */
+/*@{*/
+#define SC_FALSE ((sc_bool_t) 0U) /* True */
+#define SC_TRUE ((sc_bool_t) 1U) /* False */
/*@}*/
-#define SC_R_ALL UINT16_MAX /*!< All resources */
-#define SC_P_ALL UINT16_MAX /*!< All pads */
+/*!
+ * @name Defines for sc_err_t.
+ */
+/*@{*/
+#define SC_ERR_NONE 0U /* Success */
+#define SC_ERR_VERSION 1U /* Incompatible API version */
+#define SC_ERR_CONFIG 2U /* Configuration error */
+#define SC_ERR_PARM 3U /* Bad parameter */
+#define SC_ERR_NOACCESS 4U /* Permission error (no access) */
+#define SC_ERR_LOCKED 5U /* Permission error (locked) */
+#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */
+#define SC_ERR_NOTFOUND 7U /* Not found */
+#define SC_ERR_NOPOWER 8U /* No power */
+#define SC_ERR_IPC 9U /* Generic IPC error */
+#define SC_ERR_BUSY 10U /* Resource is currently busy/active */
+#define SC_ERR_FAIL 11U /* General I/O failure */
+#define SC_ERR_LAST 12U
+/*@}*/
+
+/*!
+ * @name Defines for sc_rsrc_t.
+ */
+/*@{*/
+#define SC_R_A53 0U
+#define SC_R_A53_0 1U
+#define SC_R_A53_1 2U
+#define SC_R_A53_2 3U
+#define SC_R_A53_3 4U
+#define SC_R_A72 5U
+#define SC_R_A72_0 6U
+#define SC_R_A72_1 7U
+#define SC_R_A72_2 8U
+#define SC_R_A72_3 9U
+#define SC_R_CCI 10U
+#define SC_R_DB 11U
+#define SC_R_DRC_0 12U
+#define SC_R_DRC_1 13U
+#define SC_R_GIC_SMMU 14U
+#define SC_R_IRQSTR_M4_0 15U
+#define SC_R_IRQSTR_M4_1 16U
+#define SC_R_SMMU 17U
+#define SC_R_GIC 18U
+#define SC_R_DC_0_BLIT0 19U
+#define SC_R_DC_0_BLIT1 20U
+#define SC_R_DC_0_BLIT2 21U
+#define SC_R_DC_0_BLIT_OUT 22U
+#define SC_R_DC_0_CAPTURE0 23U
+#define SC_R_DC_0_CAPTURE1 24U
+#define SC_R_DC_0_WARP 25U
+#define SC_R_DC_0_INTEGRAL0 26U
+#define SC_R_DC_0_INTEGRAL1 27U
+#define SC_R_DC_0_VIDEO0 28U
+#define SC_R_DC_0_VIDEO1 29U
+#define SC_R_DC_0_FRAC0 30U
+#define SC_R_DC_0_FRAC1 31U
+#define SC_R_DC_0 32U
+#define SC_R_GPU_2_PID0 33U
+#define SC_R_DC_0_PLL_0 34U
+#define SC_R_DC_0_PLL_1 35U
+#define SC_R_DC_1_BLIT0 36U
+#define SC_R_DC_1_BLIT1 37U
+#define SC_R_DC_1_BLIT2 38U
+#define SC_R_DC_1_BLIT_OUT 39U
+#define SC_R_DC_1_CAPTURE0 40U
+#define SC_R_DC_1_CAPTURE1 41U
+#define SC_R_DC_1_WARP 42U
+#define SC_R_DC_1_INTEGRAL0 43U
+#define SC_R_DC_1_INTEGRAL1 44U
+#define SC_R_DC_1_VIDEO0 45U
+#define SC_R_DC_1_VIDEO1 46U
+#define SC_R_DC_1_FRAC0 47U
+#define SC_R_DC_1_FRAC1 48U
+#define SC_R_DC_1 49U
+#define SC_R_GPU_3_PID0 50U
+#define SC_R_DC_1_PLL_0 51U
+#define SC_R_DC_1_PLL_1 52U
+#define SC_R_SPI_0 53U
+#define SC_R_SPI_1 54U
+#define SC_R_SPI_2 55U
+#define SC_R_SPI_3 56U
+#define SC_R_UART_0 57U
+#define SC_R_UART_1 58U
+#define SC_R_UART_2 59U
+#define SC_R_UART_3 60U
+#define SC_R_UART_4 61U
+#define SC_R_EMVSIM_0 62U
+#define SC_R_EMVSIM_1 63U
+#define SC_R_DMA_0_CH0 64U
+#define SC_R_DMA_0_CH1 65U
+#define SC_R_DMA_0_CH2 66U
+#define SC_R_DMA_0_CH3 67U
+#define SC_R_DMA_0_CH4 68U
+#define SC_R_DMA_0_CH5 69U
+#define SC_R_DMA_0_CH6 70U
+#define SC_R_DMA_0_CH7 71U
+#define SC_R_DMA_0_CH8 72U
+#define SC_R_DMA_0_CH9 73U
+#define SC_R_DMA_0_CH10 74U
+#define SC_R_DMA_0_CH11 75U
+#define SC_R_DMA_0_CH12 76U
+#define SC_R_DMA_0_CH13 77U
+#define SC_R_DMA_0_CH14 78U
+#define SC_R_DMA_0_CH15 79U
+#define SC_R_DMA_0_CH16 80U
+#define SC_R_DMA_0_CH17 81U
+#define SC_R_DMA_0_CH18 82U
+#define SC_R_DMA_0_CH19 83U
+#define SC_R_DMA_0_CH20 84U
+#define SC_R_DMA_0_CH21 85U
+#define SC_R_DMA_0_CH22 86U
+#define SC_R_DMA_0_CH23 87U
+#define SC_R_DMA_0_CH24 88U
+#define SC_R_DMA_0_CH25 89U
+#define SC_R_DMA_0_CH26 90U
+#define SC_R_DMA_0_CH27 91U
+#define SC_R_DMA_0_CH28 92U
+#define SC_R_DMA_0_CH29 93U
+#define SC_R_DMA_0_CH30 94U
+#define SC_R_DMA_0_CH31 95U
+#define SC_R_I2C_0 96U
+#define SC_R_I2C_1 97U
+#define SC_R_I2C_2 98U
+#define SC_R_I2C_3 99U
+#define SC_R_I2C_4 100U
+#define SC_R_ADC_0 101U
+#define SC_R_ADC_1 102U
+#define SC_R_FTM_0 103U
+#define SC_R_FTM_1 104U
+#define SC_R_CAN_0 105U
+#define SC_R_CAN_1 106U
+#define SC_R_CAN_2 107U
+#define SC_R_DMA_1_CH0 108U
+#define SC_R_DMA_1_CH1 109U
+#define SC_R_DMA_1_CH2 110U
+#define SC_R_DMA_1_CH3 111U
+#define SC_R_DMA_1_CH4 112U
+#define SC_R_DMA_1_CH5 113U
+#define SC_R_DMA_1_CH6 114U
+#define SC_R_DMA_1_CH7 115U
+#define SC_R_DMA_1_CH8 116U
+#define SC_R_DMA_1_CH9 117U
+#define SC_R_DMA_1_CH10 118U
+#define SC_R_DMA_1_CH11 119U
+#define SC_R_DMA_1_CH12 120U
+#define SC_R_DMA_1_CH13 121U
+#define SC_R_DMA_1_CH14 122U
+#define SC_R_DMA_1_CH15 123U
+#define SC_R_DMA_1_CH16 124U
+#define SC_R_DMA_1_CH17 125U
+#define SC_R_DMA_1_CH18 126U
+#define SC_R_DMA_1_CH19 127U
+#define SC_R_DMA_1_CH20 128U
+#define SC_R_DMA_1_CH21 129U
+#define SC_R_DMA_1_CH22 130U
+#define SC_R_DMA_1_CH23 131U
+#define SC_R_DMA_1_CH24 132U
+#define SC_R_DMA_1_CH25 133U
+#define SC_R_DMA_1_CH26 134U
+#define SC_R_DMA_1_CH27 135U
+#define SC_R_DMA_1_CH28 136U
+#define SC_R_DMA_1_CH29 137U
+#define SC_R_DMA_1_CH30 138U
+#define SC_R_DMA_1_CH31 139U
+#define SC_R_UNUSED1 140U
+#define SC_R_UNUSED2 141U
+#define SC_R_UNUSED3 142U
+#define SC_R_UNUSED4 143U
+#define SC_R_GPU_0_PID0 144U
+#define SC_R_GPU_0_PID1 145U
+#define SC_R_GPU_0_PID2 146U
+#define SC_R_GPU_0_PID3 147U
+#define SC_R_GPU_1_PID0 148U
+#define SC_R_GPU_1_PID1 149U
+#define SC_R_GPU_1_PID2 150U
+#define SC_R_GPU_1_PID3 151U
+#define SC_R_PCIE_A 152U
+#define SC_R_SERDES_0 153U
+#define SC_R_MATCH_0 154U
+#define SC_R_MATCH_1 155U
+#define SC_R_MATCH_2 156U
+#define SC_R_MATCH_3 157U
+#define SC_R_MATCH_4 158U
+#define SC_R_MATCH_5 159U
+#define SC_R_MATCH_6 160U
+#define SC_R_MATCH_7 161U
+#define SC_R_MATCH_8 162U
+#define SC_R_MATCH_9 163U
+#define SC_R_MATCH_10 164U
+#define SC_R_MATCH_11 165U
+#define SC_R_MATCH_12 166U
+#define SC_R_MATCH_13 167U
+#define SC_R_MATCH_14 168U
+#define SC_R_PCIE_B 169U
+#define SC_R_SATA_0 170U
+#define SC_R_SERDES_1 171U
+#define SC_R_HSIO_GPIO 172U
+#define SC_R_MATCH_15 173U
+#define SC_R_MATCH_16 174U
+#define SC_R_MATCH_17 175U
+#define SC_R_MATCH_18 176U
+#define SC_R_MATCH_19 177U
+#define SC_R_MATCH_20 178U
+#define SC_R_MATCH_21 179U
+#define SC_R_MATCH_22 180U
+#define SC_R_MATCH_23 181U
+#define SC_R_MATCH_24 182U
+#define SC_R_MATCH_25 183U
+#define SC_R_MATCH_26 184U
+#define SC_R_MATCH_27 185U
+#define SC_R_MATCH_28 186U
+#define SC_R_LCD_0 187U
+#define SC_R_LCD_0_PWM_0 188U
+#define SC_R_LCD_0_I2C_0 189U
+#define SC_R_LCD_0_I2C_1 190U
+#define SC_R_PWM_0 191U
+#define SC_R_PWM_1 192U
+#define SC_R_PWM_2 193U
+#define SC_R_PWM_3 194U
+#define SC_R_PWM_4 195U
+#define SC_R_PWM_5 196U
+#define SC_R_PWM_6 197U
+#define SC_R_PWM_7 198U
+#define SC_R_GPIO_0 199U
+#define SC_R_GPIO_1 200U
+#define SC_R_GPIO_2 201U
+#define SC_R_GPIO_3 202U
+#define SC_R_GPIO_4 203U
+#define SC_R_GPIO_5 204U
+#define SC_R_GPIO_6 205U
+#define SC_R_GPIO_7 206U
+#define SC_R_GPT_0 207U
+#define SC_R_GPT_1 208U
+#define SC_R_GPT_2 209U
+#define SC_R_GPT_3 210U
+#define SC_R_GPT_4 211U
+#define SC_R_KPP 212U
+#define SC_R_MU_0A 213U
+#define SC_R_MU_1A 214U
+#define SC_R_MU_2A 215U
+#define SC_R_MU_3A 216U
+#define SC_R_MU_4A 217U
+#define SC_R_MU_5A 218U
+#define SC_R_MU_6A 219U
+#define SC_R_MU_7A 220U
+#define SC_R_MU_8A 221U
+#define SC_R_MU_9A 222U
+#define SC_R_MU_10A 223U
+#define SC_R_MU_11A 224U
+#define SC_R_MU_12A 225U
+#define SC_R_MU_13A 226U
+#define SC_R_MU_5B 227U
+#define SC_R_MU_6B 228U
+#define SC_R_MU_7B 229U
+#define SC_R_MU_8B 230U
+#define SC_R_MU_9B 231U
+#define SC_R_MU_10B 232U
+#define SC_R_MU_11B 233U
+#define SC_R_MU_12B 234U
+#define SC_R_MU_13B 235U
+#define SC_R_ROM_0 236U
+#define SC_R_FSPI_0 237U
+#define SC_R_FSPI_1 238U
+#define SC_R_IEE 239U
+#define SC_R_IEE_R0 240U
+#define SC_R_IEE_R1 241U
+#define SC_R_IEE_R2 242U
+#define SC_R_IEE_R3 243U
+#define SC_R_IEE_R4 244U
+#define SC_R_IEE_R5 245U
+#define SC_R_IEE_R6 246U
+#define SC_R_IEE_R7 247U
+#define SC_R_SDHC_0 248U
+#define SC_R_SDHC_1 249U
+#define SC_R_SDHC_2 250U
+#define SC_R_ENET_0 251U
+#define SC_R_ENET_1 252U
+#define SC_R_MLB_0 253U
+#define SC_R_DMA_2_CH0 254U
+#define SC_R_DMA_2_CH1 255U
+#define SC_R_DMA_2_CH2 256U
+#define SC_R_DMA_2_CH3 257U
+#define SC_R_DMA_2_CH4 258U
+#define SC_R_USB_0 259U
+#define SC_R_USB_1 260U
+#define SC_R_USB_0_PHY 261U
+#define SC_R_USB_2 262U
+#define SC_R_USB_2_PHY 263U
+#define SC_R_DTCP 264U
+#define SC_R_NAND 265U
+#define SC_R_LVDS_0 266U
+#define SC_R_LVDS_0_PWM_0 267U
+#define SC_R_LVDS_0_I2C_0 268U
+#define SC_R_LVDS_0_I2C_1 269U
+#define SC_R_LVDS_1 270U
+#define SC_R_LVDS_1_PWM_0 271U
+#define SC_R_LVDS_1_I2C_0 272U
+#define SC_R_LVDS_1_I2C_1 273U
+#define SC_R_LVDS_2 274U
+#define SC_R_LVDS_2_PWM_0 275U
+#define SC_R_LVDS_2_I2C_0 276U
+#define SC_R_LVDS_2_I2C_1 277U
+#define SC_R_M4_0_PID0 278U
+#define SC_R_M4_0_PID1 279U
+#define SC_R_M4_0_PID2 280U
+#define SC_R_M4_0_PID3 281U
+#define SC_R_M4_0_PID4 282U
+#define SC_R_M4_0_RGPIO 283U
+#define SC_R_M4_0_SEMA42 284U
+#define SC_R_M4_0_TPM 285U
+#define SC_R_M4_0_PIT 286U
+#define SC_R_M4_0_UART 287U
+#define SC_R_M4_0_I2C 288U
+#define SC_R_M4_0_INTMUX 289U
+#define SC_R_M4_0_SIM 290U
+#define SC_R_M4_0_WDOG 291U
+#define SC_R_M4_0_MU_0B 292U
+#define SC_R_M4_0_MU_0A0 293U
+#define SC_R_M4_0_MU_0A1 294U
+#define SC_R_M4_0_MU_0A2 295U
+#define SC_R_M4_0_MU_0A3 296U
+#define SC_R_M4_0_MU_1A 297U
+#define SC_R_M4_1_PID0 298U
+#define SC_R_M4_1_PID1 299U
+#define SC_R_M4_1_PID2 300U
+#define SC_R_M4_1_PID3 301U
+#define SC_R_M4_1_PID4 302U
+#define SC_R_M4_1_RGPIO 303U
+#define SC_R_M4_1_SEMA42 304U
+#define SC_R_M4_1_TPM 305U
+#define SC_R_M4_1_PIT 306U
+#define SC_R_M4_1_UART 307U
+#define SC_R_M4_1_I2C 308U
+#define SC_R_M4_1_INTMUX 309U
+#define SC_R_M4_1_SIM 310U
+#define SC_R_M4_1_WDOG 311U
+#define SC_R_M4_1_MU_0B 312U
+#define SC_R_M4_1_MU_0A0 313U
+#define SC_R_M4_1_MU_0A1 314U
+#define SC_R_M4_1_MU_0A2 315U
+#define SC_R_M4_1_MU_0A3 316U
+#define SC_R_M4_1_MU_1A 317U
+#define SC_R_SAI_0 318U
+#define SC_R_SAI_1 319U
+#define SC_R_SAI_2 320U
+#define SC_R_IRQSTR_SCU2 321U
+#define SC_R_IRQSTR_DSP 322U
+#define SC_R_UNUSED5 323U
+#define SC_R_OCRAM 324U
+#define SC_R_AUDIO_PLL_0 325U
+#define SC_R_PI_0 326U
+#define SC_R_PI_0_PWM_0 327U
+#define SC_R_PI_0_PWM_1 328U
+#define SC_R_PI_0_I2C_0 329U
+#define SC_R_PI_0_PLL 330U
+#define SC_R_PI_1 331U
+#define SC_R_PI_1_PWM_0 332U
+#define SC_R_PI_1_PWM_1 333U
+#define SC_R_PI_1_I2C_0 334U
+#define SC_R_PI_1_PLL 335U
+#define SC_R_SC_PID0 336U
+#define SC_R_SC_PID1 337U
+#define SC_R_SC_PID2 338U
+#define SC_R_SC_PID3 339U
+#define SC_R_SC_PID4 340U
+#define SC_R_SC_SEMA42 341U
+#define SC_R_SC_TPM 342U
+#define SC_R_SC_PIT 343U
+#define SC_R_SC_UART 344U
+#define SC_R_SC_I2C 345U
+#define SC_R_SC_MU_0B 346U
+#define SC_R_SC_MU_0A0 347U
+#define SC_R_SC_MU_0A1 348U
+#define SC_R_SC_MU_0A2 349U
+#define SC_R_SC_MU_0A3 350U
+#define SC_R_SC_MU_1A 351U
+#define SC_R_SYSCNT_RD 352U
+#define SC_R_SYSCNT_CMP 353U
+#define SC_R_DEBUG 354U
+#define SC_R_SYSTEM 355U
+#define SC_R_SNVS 356U
+#define SC_R_OTP 357U
+#define SC_R_VPU_PID0 358U
+#define SC_R_VPU_PID1 359U
+#define SC_R_VPU_PID2 360U
+#define SC_R_VPU_PID3 361U
+#define SC_R_VPU_PID4 362U
+#define SC_R_VPU_PID5 363U
+#define SC_R_VPU_PID6 364U
+#define SC_R_VPU_PID7 365U
+#define SC_R_VPU_UART 366U
+#define SC_R_VPUCORE 367U
+#define SC_R_VPUCORE_0 368U
+#define SC_R_VPUCORE_1 369U
+#define SC_R_VPUCORE_2 370U
+#define SC_R_VPUCORE_3 371U
+#define SC_R_DMA_4_CH0 372U
+#define SC_R_DMA_4_CH1 373U
+#define SC_R_DMA_4_CH2 374U
+#define SC_R_DMA_4_CH3 375U
+#define SC_R_DMA_4_CH4 376U
+#define SC_R_ISI_CH0 377U
+#define SC_R_ISI_CH1 378U
+#define SC_R_ISI_CH2 379U
+#define SC_R_ISI_CH3 380U
+#define SC_R_ISI_CH4 381U
+#define SC_R_ISI_CH5 382U
+#define SC_R_ISI_CH6 383U
+#define SC_R_ISI_CH7 384U
+#define SC_R_MJPEG_DEC_S0 385U
+#define SC_R_MJPEG_DEC_S1 386U
+#define SC_R_MJPEG_DEC_S2 387U
+#define SC_R_MJPEG_DEC_S3 388U
+#define SC_R_MJPEG_ENC_S0 389U
+#define SC_R_MJPEG_ENC_S1 390U
+#define SC_R_MJPEG_ENC_S2 391U
+#define SC_R_MJPEG_ENC_S3 392U
+#define SC_R_MIPI_0 393U
+#define SC_R_MIPI_0_PWM_0 394U
+#define SC_R_MIPI_0_I2C_0 395U
+#define SC_R_MIPI_0_I2C_1 396U
+#define SC_R_MIPI_1 397U
+#define SC_R_MIPI_1_PWM_0 398U
+#define SC_R_MIPI_1_I2C_0 399U
+#define SC_R_MIPI_1_I2C_1 400U
+#define SC_R_CSI_0 401U
+#define SC_R_CSI_0_PWM_0 402U
+#define SC_R_CSI_0_I2C_0 403U
+#define SC_R_CSI_1 404U
+#define SC_R_CSI_1_PWM_0 405U
+#define SC_R_CSI_1_I2C_0 406U
+#define SC_R_HDMI 407U
+#define SC_R_HDMI_I2S 408U
+#define SC_R_HDMI_I2C_0 409U
+#define SC_R_HDMI_PLL_0 410U
+#define SC_R_HDMI_RX 411U
+#define SC_R_HDMI_RX_BYPASS 412U
+#define SC_R_HDMI_RX_I2C_0 413U
+#define SC_R_ASRC_0 414U
+#define SC_R_ESAI_0 415U
+#define SC_R_SPDIF_0 416U
+#define SC_R_SPDIF_1 417U
+#define SC_R_SAI_3 418U
+#define SC_R_SAI_4 419U
+#define SC_R_SAI_5 420U
+#define SC_R_GPT_5 421U
+#define SC_R_GPT_6 422U
+#define SC_R_GPT_7 423U
+#define SC_R_GPT_8 424U
+#define SC_R_GPT_9 425U
+#define SC_R_GPT_10 426U
+#define SC_R_DMA_2_CH5 427U
+#define SC_R_DMA_2_CH6 428U
+#define SC_R_DMA_2_CH7 429U
+#define SC_R_DMA_2_CH8 430U
+#define SC_R_DMA_2_CH9 431U
+#define SC_R_DMA_2_CH10 432U
+#define SC_R_DMA_2_CH11 433U
+#define SC_R_DMA_2_CH12 434U
+#define SC_R_DMA_2_CH13 435U
+#define SC_R_DMA_2_CH14 436U
+#define SC_R_DMA_2_CH15 437U
+#define SC_R_DMA_2_CH16 438U
+#define SC_R_DMA_2_CH17 439U
+#define SC_R_DMA_2_CH18 440U
+#define SC_R_DMA_2_CH19 441U
+#define SC_R_DMA_2_CH20 442U
+#define SC_R_DMA_2_CH21 443U
+#define SC_R_DMA_2_CH22 444U
+#define SC_R_DMA_2_CH23 445U
+#define SC_R_DMA_2_CH24 446U
+#define SC_R_DMA_2_CH25 447U
+#define SC_R_DMA_2_CH26 448U
+#define SC_R_DMA_2_CH27 449U
+#define SC_R_DMA_2_CH28 450U
+#define SC_R_DMA_2_CH29 451U
+#define SC_R_DMA_2_CH30 452U
+#define SC_R_DMA_2_CH31 453U
+#define SC_R_ASRC_1 454U
+#define SC_R_ESAI_1 455U
+#define SC_R_SAI_6 456U
+#define SC_R_SAI_7 457U
+#define SC_R_AMIX 458U
+#define SC_R_MQS_0 459U
+#define SC_R_DMA_3_CH0 460U
+#define SC_R_DMA_3_CH1 461U
+#define SC_R_DMA_3_CH2 462U
+#define SC_R_DMA_3_CH3 463U
+#define SC_R_DMA_3_CH4 464U
+#define SC_R_DMA_3_CH5 465U
+#define SC_R_DMA_3_CH6 466U
+#define SC_R_DMA_3_CH7 467U
+#define SC_R_DMA_3_CH8 468U
+#define SC_R_DMA_3_CH9 469U
+#define SC_R_DMA_3_CH10 470U
+#define SC_R_DMA_3_CH11 471U
+#define SC_R_DMA_3_CH12 472U
+#define SC_R_DMA_3_CH13 473U
+#define SC_R_DMA_3_CH14 474U
+#define SC_R_DMA_3_CH15 475U
+#define SC_R_DMA_3_CH16 476U
+#define SC_R_DMA_3_CH17 477U
+#define SC_R_DMA_3_CH18 478U
+#define SC_R_DMA_3_CH19 479U
+#define SC_R_DMA_3_CH20 480U
+#define SC_R_DMA_3_CH21 481U
+#define SC_R_DMA_3_CH22 482U
+#define SC_R_DMA_3_CH23 483U
+#define SC_R_DMA_3_CH24 484U
+#define SC_R_DMA_3_CH25 485U
+#define SC_R_DMA_3_CH26 486U
+#define SC_R_DMA_3_CH27 487U
+#define SC_R_DMA_3_CH28 488U
+#define SC_R_DMA_3_CH29 489U
+#define SC_R_DMA_3_CH30 490U
+#define SC_R_DMA_3_CH31 491U
+#define SC_R_AUDIO_PLL_1 492U
+#define SC_R_AUDIO_CLK_0 493U
+#define SC_R_AUDIO_CLK_1 494U
+#define SC_R_MCLK_OUT_0 495U
+#define SC_R_MCLK_OUT_1 496U
+#define SC_R_PMIC_0 497U
+#define SC_R_PMIC_1 498U
+#define SC_R_SECO 499U
+#define SC_R_CAAM_JR1 500U
+#define SC_R_CAAM_JR2 501U
+#define SC_R_CAAM_JR3 502U
+#define SC_R_SECO_MU_2 503U
+#define SC_R_SECO_MU_3 504U
+#define SC_R_SECO_MU_4 505U
+#define SC_R_HDMI_RX_PWM_0 506U
+#define SC_R_A35 507U
+#define SC_R_A35_0 508U
+#define SC_R_A35_1 509U
+#define SC_R_A35_2 510U
+#define SC_R_A35_3 511U
+#define SC_R_DSP 512U
+#define SC_R_DSP_RAM 513U
+#define SC_R_CAAM_JR1_OUT 514U
+#define SC_R_CAAM_JR2_OUT 515U
+#define SC_R_CAAM_JR3_OUT 516U
+#define SC_R_VPU_DEC_0 517U
+#define SC_R_VPU_ENC_0 518U
+#define SC_R_CAAM_JR0 519U
+#define SC_R_CAAM_JR0_OUT 520U
+#define SC_R_PMIC_2 521U
+#define SC_R_DBLOGIC 522U
+#define SC_R_HDMI_PLL_1 523U
+#define SC_R_BOARD_R0 524U
+#define SC_R_BOARD_R1 525U
+#define SC_R_BOARD_R2 526U
+#define SC_R_BOARD_R3 527U
+#define SC_R_BOARD_R4 528U
+#define SC_R_BOARD_R5 529U
+#define SC_R_BOARD_R6 530U
+#define SC_R_BOARD_R7 531U
+#define SC_R_MJPEG_DEC_MP 532U
+#define SC_R_MJPEG_ENC_MP 533U
+#define SC_R_VPU_TS_0 534U
+#define SC_R_VPU_MU_0 535U
+#define SC_R_VPU_MU_1 536U
+#define SC_R_VPU_MU_2 537U
+#define SC_R_VPU_MU_3 538U
+#define SC_R_VPU_ENC_1 539U
+#define SC_R_VPU 540U
+#define SC_R_LAST 541U
+#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /* All resources */
+/*@}*/
+
+/* NOTE - please add by replacing some of the UNUSED from above! */
+
+/*!
+ * Defnes for sc_ctrl_t.
+ */
+#define SC_C_TEMP 0U
+#define SC_C_TEMP_HI 1U
+#define SC_C_TEMP_LOW 2U
+#define SC_C_PXL_LINK_MST1_ADDR 3U
+#define SC_C_PXL_LINK_MST2_ADDR 4U
+#define SC_C_PXL_LINK_MST_ENB 5U
+#define SC_C_PXL_LINK_MST1_ENB 6U
+#define SC_C_PXL_LINK_MST2_ENB 7U
+#define SC_C_PXL_LINK_SLV1_ADDR 8U
+#define SC_C_PXL_LINK_SLV2_ADDR 9U
+#define SC_C_PXL_LINK_MST_VLD 10U
+#define SC_C_PXL_LINK_MST1_VLD 11U
+#define SC_C_PXL_LINK_MST2_VLD 12U
+#define SC_C_SINGLE_MODE 13U
+#define SC_C_ID 14U
+#define SC_C_PXL_CLK_POLARITY 15U
+#define SC_C_LINESTATE 16U
+#define SC_C_PCIE_G_RST 17U
+#define SC_C_PCIE_BUTTON_RST 18U
+#define SC_C_PCIE_PERST 19U
+#define SC_C_PHY_RESET 20U
+#define SC_C_PXL_LINK_RATE_CORRECTION 21U
+#define SC_C_PANIC 22U
+#define SC_C_PRIORITY_GROUP 23U
+#define SC_C_TXCLK 24U
+#define SC_C_CLKDIV 25U
+#define SC_C_DISABLE_50 26U
+#define SC_C_DISABLE_125 27U
+#define SC_C_SEL_125 28U
+#define SC_C_MODE 29U
+#define SC_C_SYNC_CTRL0 30U
+#define SC_C_KACHUNK_CNT 31U
+#define SC_C_KACHUNK_SEL 32U
+#define SC_C_SYNC_CTRL1 33U
+#define SC_C_DPI_RESET 34U
+#define SC_C_MIPI_RESET 35U
+#define SC_C_DUAL_MODE 36U
+#define SC_C_VOLTAGE 37U
+#define SC_C_PXL_LINK_SEL 38U
+#define SC_C_OFS_SEL 39U
+#define SC_C_OFS_AUDIO 40U
+#define SC_C_OFS_PERIPH 41U
+#define SC_C_OFS_IRQ 42U
+#define SC_C_RST0 43U
+#define SC_C_RST1 44U
+#define SC_C_SEL0 45U
+#define SC_C_LAST 46U
+
+#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /* All pads */
+
+/* Types */
+
+/*!
+ * This type is used to store a boolean
+ */
+typedef uint8_t sc_bool_t;
/*!
* This type is used to store a system (full-size) address.
@@ -145,629 +783,19 @@ typedef uint64_t sc_faddr_t;
/*!
* This type is used to indicate error response for most functions.
*/
-typedef enum sc_err_e
-{
- SC_ERR_NONE = 0, /*!< Success */
- SC_ERR_VERSION = 1, /*!< Incompatible API version */
- SC_ERR_CONFIG = 2, /*!< Configuration error */
- SC_ERR_PARM = 3, /*!< Bad parameter */
- SC_ERR_NOACCESS = 4, /*!< Permission error (no access) */
- SC_ERR_LOCKED = 5, /*!< Permission error (locked) */
- SC_ERR_UNAVAILABLE = 6, /*!< Unavailable (out of resources) */
- SC_ERR_NOTFOUND = 7, /*!< Not found */
- SC_ERR_NOPOWER = 8, /*!< No power */
- SC_ERR_IPC = 9, /*!< Generic IPC error */
- SC_ERR_BUSY = 10, /*!< Resource is currently busy/active */
- SC_ERR_FAIL = 11, /*!< General I/O failure */
- SC_ERR_LAST
-} sc_err_t;
+typedef uint8_t sc_err_t;
/*!
* This type is used to indicate a resource. Resources include peripherals
* and bus masters (but not memory regions). Note items from list should
* never be changed or removed (only added to at the end of the list).
*/
-typedef enum sc_rsrc_e
-{
- SC_R_A53 = 0,
- SC_R_A53_0 = 1,
- SC_R_A53_1 = 2,
- SC_R_A53_2 = 3,
- SC_R_A53_3 = 4,
- SC_R_A72 = 5,
- SC_R_A72_0 = 6,
- SC_R_A72_1 = 7,
- SC_R_A72_2 = 8,
- SC_R_A72_3 = 9,
- SC_R_CCI = 10,
- SC_R_DB = 11,
- SC_R_DRC_0 = 12,
- SC_R_DRC_1 = 13,
- SC_R_GIC_SMMU = 14,
- SC_R_IRQSTR_M4_0 = 15,
- SC_R_IRQSTR_M4_1 = 16,
- SC_R_SMMU = 17,
- SC_R_GIC = 18,
- SC_R_DC_0_BLIT0 = 19,
- SC_R_DC_0_BLIT1 = 20,
- SC_R_DC_0_BLIT2 = 21,
- SC_R_DC_0_BLIT_OUT = 22,
- SC_R_DC_0_CAPTURE0 = 23,
- SC_R_DC_0_CAPTURE1 = 24,
- SC_R_DC_0_WARP = 25,
- SC_R_DC_0_INTEGRAL0 = 26,
- SC_R_DC_0_INTEGRAL1 = 27,
- SC_R_DC_0_VIDEO0 = 28,
- SC_R_DC_0_VIDEO1 = 29,
- SC_R_DC_0_FRAC0 = 30,
- SC_R_DC_0_FRAC1 = 31,
- SC_R_DC_0 = 32,
- SC_R_GPU_2_PID0 = 33,
- SC_R_DC_0_PLL_0 = 34,
- SC_R_DC_0_PLL_1 = 35,
- SC_R_DC_1_BLIT0 = 36,
- SC_R_DC_1_BLIT1 = 37,
- SC_R_DC_1_BLIT2 = 38,
- SC_R_DC_1_BLIT_OUT = 39,
- SC_R_DC_1_CAPTURE0 = 40,
- SC_R_DC_1_CAPTURE1 = 41,
- SC_R_DC_1_WARP = 42,
- SC_R_DC_1_INTEGRAL0 = 43,
- SC_R_DC_1_INTEGRAL1 = 44,
- SC_R_DC_1_VIDEO0 = 45,
- SC_R_DC_1_VIDEO1 = 46,
- SC_R_DC_1_FRAC0 = 47,
- SC_R_DC_1_FRAC1 = 48,
- SC_R_DC_1 = 49,
- SC_R_GPU_3_PID0 = 50,
- SC_R_DC_1_PLL_0 = 51,
- SC_R_DC_1_PLL_1 = 52,
- SC_R_SPI_0 = 53,
- SC_R_SPI_1 = 54,
- SC_R_SPI_2 = 55,
- SC_R_SPI_3 = 56,
- SC_R_UART_0 = 57,
- SC_R_UART_1 = 58,
- SC_R_UART_2 = 59,
- SC_R_UART_3 = 60,
- SC_R_UART_4 = 61,
- SC_R_EMVSIM_0 = 62,
- SC_R_EMVSIM_1 = 63,
- SC_R_DMA_0_CH0 = 64,
- SC_R_DMA_0_CH1 = 65,
- SC_R_DMA_0_CH2 = 66,
- SC_R_DMA_0_CH3 = 67,
- SC_R_DMA_0_CH4 = 68,
- SC_R_DMA_0_CH5 = 69,
- SC_R_DMA_0_CH6 = 70,
- SC_R_DMA_0_CH7 = 71,
- SC_R_DMA_0_CH8 = 72,
- SC_R_DMA_0_CH9 = 73,
- SC_R_DMA_0_CH10 = 74,
- SC_R_DMA_0_CH11 = 75,
- SC_R_DMA_0_CH12 = 76,
- SC_R_DMA_0_CH13 = 77,
- SC_R_DMA_0_CH14 = 78,
- SC_R_DMA_0_CH15 = 79,
- SC_R_DMA_0_CH16 = 80,
- SC_R_DMA_0_CH17 = 81,
- SC_R_DMA_0_CH18 = 82,
- SC_R_DMA_0_CH19 = 83,
- SC_R_DMA_0_CH20 = 84,
- SC_R_DMA_0_CH21 = 85,
- SC_R_DMA_0_CH22 = 86,
- SC_R_DMA_0_CH23 = 87,
- SC_R_DMA_0_CH24 = 88,
- SC_R_DMA_0_CH25 = 89,
- SC_R_DMA_0_CH26 = 90,
- SC_R_DMA_0_CH27 = 91,
- SC_R_DMA_0_CH28 = 92,
- SC_R_DMA_0_CH29 = 93,
- SC_R_DMA_0_CH30 = 94,
- SC_R_DMA_0_CH31 = 95,
- SC_R_I2C_0 = 96,
- SC_R_I2C_1 = 97,
- SC_R_I2C_2 = 98,
- SC_R_I2C_3 = 99,
- SC_R_I2C_4 = 100,
- SC_R_ADC_0 = 101,
- SC_R_ADC_1 = 102,
- SC_R_FTM_0 = 103,
- SC_R_FTM_1 = 104,
- SC_R_CAN_0 = 105,
- SC_R_CAN_1 = 106,
- SC_R_CAN_2 = 107,
- SC_R_DMA_1_CH0 = 108,
- SC_R_DMA_1_CH1 = 109,
- SC_R_DMA_1_CH2 = 110,
- SC_R_DMA_1_CH3 = 111,
- SC_R_DMA_1_CH4 = 112,
- SC_R_DMA_1_CH5 = 113,
- SC_R_DMA_1_CH6 = 114,
- SC_R_DMA_1_CH7 = 115,
- SC_R_DMA_1_CH8 = 116,
- SC_R_DMA_1_CH9 = 117,
- SC_R_DMA_1_CH10 = 118,
- SC_R_DMA_1_CH11 = 119,
- SC_R_DMA_1_CH12 = 120,
- SC_R_DMA_1_CH13 = 121,
- SC_R_DMA_1_CH14 = 122,
- SC_R_DMA_1_CH15 = 123,
- SC_R_DMA_1_CH16 = 124,
- SC_R_DMA_1_CH17 = 125,
- SC_R_DMA_1_CH18 = 126,
- SC_R_DMA_1_CH19 = 127,
- SC_R_DMA_1_CH20 = 128,
- SC_R_DMA_1_CH21 = 129,
- SC_R_DMA_1_CH22 = 130,
- SC_R_DMA_1_CH23 = 131,
- SC_R_DMA_1_CH24 = 132,
- SC_R_DMA_1_CH25 = 133,
- SC_R_DMA_1_CH26 = 134,
- SC_R_DMA_1_CH27 = 135,
- SC_R_DMA_1_CH28 = 136,
- SC_R_DMA_1_CH29 = 137,
- SC_R_DMA_1_CH30 = 138,
- SC_R_DMA_1_CH31 = 139,
- SC_R_UNUSED1 = 140,
- SC_R_UNUSED2 = 141,
- SC_R_UNUSED3 = 142,
- SC_R_UNUSED4 = 143,
- SC_R_GPU_0_PID0 = 144,
- SC_R_GPU_0_PID1 = 145,
- SC_R_GPU_0_PID2 = 146,
- SC_R_GPU_0_PID3 = 147,
- SC_R_GPU_1_PID0 = 148,
- SC_R_GPU_1_PID1 = 149,
- SC_R_GPU_1_PID2 = 150,
- SC_R_GPU_1_PID3 = 151,
- SC_R_PCIE_A = 152,
- SC_R_SERDES_0 = 153,
- SC_R_MATCH_0 = 154,
- SC_R_MATCH_1 = 155,
- SC_R_MATCH_2 = 156,
- SC_R_MATCH_3 = 157,
- SC_R_MATCH_4 = 158,
- SC_R_MATCH_5 = 159,
- SC_R_MATCH_6 = 160,
- SC_R_MATCH_7 = 161,
- SC_R_MATCH_8 = 162,
- SC_R_MATCH_9 = 163,
- SC_R_MATCH_10 = 164,
- SC_R_MATCH_11 = 165,
- SC_R_MATCH_12 = 166,
- SC_R_MATCH_13 = 167,
- SC_R_MATCH_14 = 168,
- SC_R_PCIE_B = 169,
- SC_R_SATA_0 = 170,
- SC_R_SERDES_1 = 171,
- SC_R_HSIO_GPIO = 172,
- SC_R_MATCH_15 = 173,
- SC_R_MATCH_16 = 174,
- SC_R_MATCH_17 = 175,
- SC_R_MATCH_18 = 176,
- SC_R_MATCH_19 = 177,
- SC_R_MATCH_20 = 178,
- SC_R_MATCH_21 = 179,
- SC_R_MATCH_22 = 180,
- SC_R_MATCH_23 = 181,
- SC_R_MATCH_24 = 182,
- SC_R_MATCH_25 = 183,
- SC_R_MATCH_26 = 184,
- SC_R_MATCH_27 = 185,
- SC_R_MATCH_28 = 186,
- SC_R_LCD_0 = 187,
- SC_R_LCD_0_PWM_0 = 188,
- SC_R_LCD_0_I2C_0 = 189,
- SC_R_LCD_0_I2C_1 = 190,
- SC_R_PWM_0 = 191,
- SC_R_PWM_1 = 192,
- SC_R_PWM_2 = 193,
- SC_R_PWM_3 = 194,
- SC_R_PWM_4 = 195,
- SC_R_PWM_5 = 196,
- SC_R_PWM_6 = 197,
- SC_R_PWM_7 = 198,
- SC_R_GPIO_0 = 199,
- SC_R_GPIO_1 = 200,
- SC_R_GPIO_2 = 201,
- SC_R_GPIO_3 = 202,
- SC_R_GPIO_4 = 203,
- SC_R_GPIO_5 = 204,
- SC_R_GPIO_6 = 205,
- SC_R_GPIO_7 = 206,
- SC_R_GPT_0 = 207,
- SC_R_GPT_1 = 208,
- SC_R_GPT_2 = 209,
- SC_R_GPT_3 = 210,
- SC_R_GPT_4 = 211,
- SC_R_KPP = 212,
- SC_R_MU_0A = 213,
- SC_R_MU_1A = 214,
- SC_R_MU_2A = 215,
- SC_R_MU_3A = 216,
- SC_R_MU_4A = 217,
- SC_R_MU_5A = 218,
- SC_R_MU_6A = 219,
- SC_R_MU_7A = 220,
- SC_R_MU_8A = 221,
- SC_R_MU_9A = 222,
- SC_R_MU_10A = 223,
- SC_R_MU_11A = 224,
- SC_R_MU_12A = 225,
- SC_R_MU_13A = 226,
- SC_R_MU_5B = 227,
- SC_R_MU_6B = 228,
- SC_R_MU_7B = 229,
- SC_R_MU_8B = 230,
- SC_R_MU_9B = 231,
- SC_R_MU_10B = 232,
- SC_R_MU_11B = 233,
- SC_R_MU_12B = 234,
- SC_R_MU_13B = 235,
- SC_R_ROM_0 = 236,
- SC_R_FSPI_0 = 237,
- SC_R_FSPI_1 = 238,
- SC_R_IEE = 239,
- SC_R_IEE_R0 = 240,
- SC_R_IEE_R1 = 241,
- SC_R_IEE_R2 = 242,
- SC_R_IEE_R3 = 243,
- SC_R_IEE_R4 = 244,
- SC_R_IEE_R5 = 245,
- SC_R_IEE_R6 = 246,
- SC_R_IEE_R7 = 247,
- SC_R_SDHC_0 = 248,
- SC_R_SDHC_1 = 249,
- SC_R_SDHC_2 = 250,
- SC_R_ENET_0 = 251,
- SC_R_ENET_1 = 252,
- SC_R_MLB_0 = 253,
- SC_R_DMA_2_CH0 = 254,
- SC_R_DMA_2_CH1 = 255,
- SC_R_DMA_2_CH2 = 256,
- SC_R_DMA_2_CH3 = 257,
- SC_R_DMA_2_CH4 = 258,
- SC_R_USB_0 = 259,
- SC_R_USB_1 = 260,
- SC_R_USB_0_PHY = 261,
- SC_R_USB_2 = 262,
- SC_R_USB_2_PHY = 263,
- SC_R_DTCP = 264,
- SC_R_NAND = 265,
- SC_R_LVDS_0 = 266,
- SC_R_LVDS_0_PWM_0 = 267,
- SC_R_LVDS_0_I2C_0 = 268,
- SC_R_LVDS_0_I2C_1 = 269,
- SC_R_LVDS_1 = 270,
- SC_R_LVDS_1_PWM_0 = 271,
- SC_R_LVDS_1_I2C_0 = 272,
- SC_R_LVDS_1_I2C_1 = 273,
- SC_R_LVDS_2 = 274,
- SC_R_LVDS_2_PWM_0 = 275,
- SC_R_LVDS_2_I2C_0 = 276,
- SC_R_LVDS_2_I2C_1 = 277,
- SC_R_M4_0_PID0 = 278,
- SC_R_M4_0_PID1 = 279,
- SC_R_M4_0_PID2 = 280,
- SC_R_M4_0_PID3 = 281,
- SC_R_M4_0_PID4 = 282,
- SC_R_M4_0_RGPIO = 283,
- SC_R_M4_0_SEMA42 = 284,
- SC_R_M4_0_TPM = 285,
- SC_R_M4_0_PIT = 286,
- SC_R_M4_0_UART = 287,
- SC_R_M4_0_I2C = 288,
- SC_R_M4_0_INTMUX = 289,
- SC_R_M4_0_SIM = 290,
- SC_R_M4_0_WDOG = 291,
- SC_R_M4_0_MU_0B = 292,
- SC_R_M4_0_MU_0A0 = 293,
- SC_R_M4_0_MU_0A1 = 294,
- SC_R_M4_0_MU_0A2 = 295,
- SC_R_M4_0_MU_0A3 = 296,
- SC_R_M4_0_MU_1A = 297,
- SC_R_M4_1_PID0 = 298,
- SC_R_M4_1_PID1 = 299,
- SC_R_M4_1_PID2 = 300,
- SC_R_M4_1_PID3 = 301,
- SC_R_M4_1_PID4 = 302,
- SC_R_M4_1_RGPIO = 303,
- SC_R_M4_1_SEMA42 = 304,
- SC_R_M4_1_TPM = 305,
- SC_R_M4_1_PIT = 306,
- SC_R_M4_1_UART = 307,
- SC_R_M4_1_I2C = 308,
- SC_R_M4_1_INTMUX = 309,
- SC_R_M4_1_SIM = 310,
- SC_R_M4_1_WDOG = 311,
- SC_R_M4_1_MU_0B = 312,
- SC_R_M4_1_MU_0A0 = 313,
- SC_R_M4_1_MU_0A1 = 314,
- SC_R_M4_1_MU_0A2 = 315,
- SC_R_M4_1_MU_0A3 = 316,
- SC_R_M4_1_MU_1A = 317,
- SC_R_SAI_0 = 318,
- SC_R_SAI_1 = 319,
- SC_R_SAI_2 = 320,
- SC_R_IRQSTR_SCU2 = 321,
- SC_R_IRQSTR_DSP = 322,
- SC_R_UNUSED5 = 323,
- SC_R_UNUSED6 = 324,
- SC_R_AUDIO_PLL_0 = 325,
- SC_R_PI_0 = 326,
- SC_R_PI_0_PWM_0 = 327,
- SC_R_PI_0_PWM_1 = 328,
- SC_R_PI_0_I2C_0 = 329,
- SC_R_PI_0_PLL = 330,
- SC_R_PI_1 = 331,
- SC_R_PI_1_PWM_0 = 332,
- SC_R_PI_1_PWM_1 = 333,
- SC_R_PI_1_I2C_0 = 334,
- SC_R_PI_1_PLL = 335,
- SC_R_SC_PID0 = 336,
- SC_R_SC_PID1 = 337,
- SC_R_SC_PID2 = 338,
- SC_R_SC_PID3 = 339,
- SC_R_SC_PID4 = 340,
- SC_R_SC_SEMA42 = 341,
- SC_R_SC_TPM = 342,
- SC_R_SC_PIT = 343,
- SC_R_SC_UART = 344,
- SC_R_SC_I2C = 345,
- SC_R_SC_MU_0B = 346,
- SC_R_SC_MU_0A0 = 347,
- SC_R_SC_MU_0A1 = 348,
- SC_R_SC_MU_0A2 = 349,
- SC_R_SC_MU_0A3 = 350,
- SC_R_SC_MU_1A = 351,
- SC_R_SYSCNT_RD = 352,
- SC_R_SYSCNT_CMP = 353,
- SC_R_DEBUG = 354,
- SC_R_SYSTEM = 355,
- SC_R_SNVS = 356,
- SC_R_OTP = 357,
- SC_R_VPU_PID0 = 358,
- SC_R_VPU_PID1 = 359,
- SC_R_VPU_PID2 = 360,
- SC_R_VPU_PID3 = 361,
- SC_R_VPU_PID4 = 362,
- SC_R_VPU_PID5 = 363,
- SC_R_VPU_PID6 = 364,
- SC_R_VPU_PID7 = 365,
- SC_R_VPU_UART = 366,
- SC_R_VPUCORE = 367,
- SC_R_VPUCORE_0 = 368,
- SC_R_VPUCORE_1 = 369,
- SC_R_VPUCORE_2 = 370,
- SC_R_VPUCORE_3 = 371,
- SC_R_DMA_4_CH0 = 372,
- SC_R_DMA_4_CH1 = 373,
- SC_R_DMA_4_CH2 = 374,
- SC_R_DMA_4_CH3 = 375,
- SC_R_DMA_4_CH4 = 376,
- SC_R_ISI_CH0 = 377,
- SC_R_ISI_CH1 = 378,
- SC_R_ISI_CH2 = 379,
- SC_R_ISI_CH3 = 380,
- SC_R_ISI_CH4 = 381,
- SC_R_ISI_CH5 = 382,
- SC_R_ISI_CH6 = 383,
- SC_R_ISI_CH7 = 384,
- SC_R_MJPEG_DEC_S0 = 385,
- SC_R_MJPEG_DEC_S1 = 386,
- SC_R_MJPEG_DEC_S2 = 387,
- SC_R_MJPEG_DEC_S3 = 388,
- SC_R_MJPEG_ENC_S0 = 389,
- SC_R_MJPEG_ENC_S1 = 390,
- SC_R_MJPEG_ENC_S2 = 391,
- SC_R_MJPEG_ENC_S3 = 392,
- SC_R_MIPI_0 = 393,
- SC_R_MIPI_0_PWM_0 = 394,
- SC_R_MIPI_0_I2C_0 = 395,
- SC_R_MIPI_0_I2C_1 = 396,
- SC_R_MIPI_1 = 397,
- SC_R_MIPI_1_PWM_0 = 398,
- SC_R_MIPI_1_I2C_0 = 399,
- SC_R_MIPI_1_I2C_1 = 400,
- SC_R_CSI_0 = 401,
- SC_R_CSI_0_PWM_0 = 402,
- SC_R_CSI_0_I2C_0 = 403,
- SC_R_CSI_1 = 404,
- SC_R_CSI_1_PWM_0 = 405,
- SC_R_CSI_1_I2C_0 = 406,
- SC_R_HDMI = 407,
- SC_R_HDMI_I2S = 408,
- SC_R_HDMI_I2C_0 = 409,
- SC_R_HDMI_PLL_0 = 410,
- SC_R_HDMI_RX = 411,
- SC_R_HDMI_RX_BYPASS = 412,
- SC_R_HDMI_RX_I2C_0 = 413,
- SC_R_ASRC_0 = 414,
- SC_R_ESAI_0 = 415,
- SC_R_SPDIF_0 = 416,
- SC_R_SPDIF_1 = 417,
- SC_R_SAI_3 = 418,
- SC_R_SAI_4 = 419,
- SC_R_SAI_5 = 420,
- SC_R_GPT_5 = 421,
- SC_R_GPT_6 = 422,
- SC_R_GPT_7 = 423,
- SC_R_GPT_8 = 424,
- SC_R_GPT_9 = 425,
- SC_R_GPT_10 = 426,
- SC_R_DMA_2_CH5 = 427,
- SC_R_DMA_2_CH6 = 428,
- SC_R_DMA_2_CH7 = 429,
- SC_R_DMA_2_CH8 = 430,
- SC_R_DMA_2_CH9 = 431,
- SC_R_DMA_2_CH10 = 432,
- SC_R_DMA_2_CH11 = 433,
- SC_R_DMA_2_CH12 = 434,
- SC_R_DMA_2_CH13 = 435,
- SC_R_DMA_2_CH14 = 436,
- SC_R_DMA_2_CH15 = 437,
- SC_R_DMA_2_CH16 = 438,
- SC_R_DMA_2_CH17 = 439,
- SC_R_DMA_2_CH18 = 440,
- SC_R_DMA_2_CH19 = 441,
- SC_R_DMA_2_CH20 = 442,
- SC_R_DMA_2_CH21 = 443,
- SC_R_DMA_2_CH22 = 444,
- SC_R_DMA_2_CH23 = 445,
- SC_R_DMA_2_CH24 = 446,
- SC_R_DMA_2_CH25 = 447,
- SC_R_DMA_2_CH26 = 448,
- SC_R_DMA_2_CH27 = 449,
- SC_R_DMA_2_CH28 = 450,
- SC_R_DMA_2_CH29 = 451,
- SC_R_DMA_2_CH30 = 452,
- SC_R_DMA_2_CH31 = 453,
- SC_R_ASRC_1 = 454,
- SC_R_ESAI_1 = 455,
- SC_R_SAI_6 = 456,
- SC_R_SAI_7 = 457,
- SC_R_AMIX = 458,
- SC_R_MQS_0 = 459,
- SC_R_DMA_3_CH0 = 460,
- SC_R_DMA_3_CH1 = 461,
- SC_R_DMA_3_CH2 = 462,
- SC_R_DMA_3_CH3 = 463,
- SC_R_DMA_3_CH4 = 464,
- SC_R_DMA_3_CH5 = 465,
- SC_R_DMA_3_CH6 = 466,
- SC_R_DMA_3_CH7 = 467,
- SC_R_DMA_3_CH8 = 468,
- SC_R_DMA_3_CH9 = 469,
- SC_R_DMA_3_CH10 = 470,
- SC_R_DMA_3_CH11 = 471,
- SC_R_DMA_3_CH12 = 472,
- SC_R_DMA_3_CH13 = 473,
- SC_R_DMA_3_CH14 = 474,
- SC_R_DMA_3_CH15 = 475,
- SC_R_DMA_3_CH16 = 476,
- SC_R_DMA_3_CH17 = 477,
- SC_R_DMA_3_CH18 = 478,
- SC_R_DMA_3_CH19 = 479,
- SC_R_DMA_3_CH20 = 480,
- SC_R_DMA_3_CH21 = 481,
- SC_R_DMA_3_CH22 = 482,
- SC_R_DMA_3_CH23 = 483,
- SC_R_DMA_3_CH24 = 484,
- SC_R_DMA_3_CH25 = 485,
- SC_R_DMA_3_CH26 = 486,
- SC_R_DMA_3_CH27 = 487,
- SC_R_DMA_3_CH28 = 488,
- SC_R_DMA_3_CH29 = 489,
- SC_R_DMA_3_CH30 = 490,
- SC_R_DMA_3_CH31 = 491,
- SC_R_AUDIO_PLL_1 = 492,
- SC_R_AUDIO_CLK_0 = 493,
- SC_R_AUDIO_CLK_1 = 494,
- SC_R_MCLK_OUT_0 = 495,
- SC_R_MCLK_OUT_1 = 496,
- SC_R_PMIC_0 = 497,
- SC_R_PMIC_1 = 498,
- SC_R_SECO = 499,
- SC_R_CAAM_JR1 = 500,
- SC_R_CAAM_JR2 = 501,
- SC_R_CAAM_JR3 = 502,
- SC_R_SECO_MU_2 = 503,
- SC_R_SECO_MU_3 = 504,
- SC_R_SECO_MU_4 = 505,
- SC_R_HDMI_RX_PWM_0 = 506,
- SC_R_A35 = 507,
- SC_R_A35_0 = 508,
- SC_R_A35_1 = 509,
- SC_R_A35_2 = 510,
- SC_R_A35_3 = 511,
- SC_R_DSP = 512,
- SC_R_DSP_RAM = 513,
- SC_R_CAAM_JR1_OUT = 514,
- SC_R_CAAM_JR2_OUT = 515,
- SC_R_CAAM_JR3_OUT = 516,
- SC_R_VPU_DEC_0 = 517,
- SC_R_VPU_ENC_0 = 518,
- SC_R_CAAM_JR0 = 519,
- SC_R_CAAM_JR0_OUT = 520,
- SC_R_PMIC_2 = 521,
- SC_R_DBLOGIC = 522,
- SC_R_HDMI_PLL_1 = 523,
- SC_R_BOARD_R0 = 524,
- SC_R_BOARD_R1 = 525,
- SC_R_BOARD_R2 = 526,
- SC_R_BOARD_R3 = 527,
- SC_R_BOARD_R4 = 528,
- SC_R_BOARD_R5 = 529,
- SC_R_BOARD_R6 = 530,
- SC_R_BOARD_R7 = 531,
- SC_R_MJPEG_DEC_MP = 532,
- SC_R_MJPEG_ENC_MP = 533,
- SC_R_VPU_TS_0 = 534,
- SC_R_VPU_MU_0 = 535,
- SC_R_VPU_MU_1 = 536,
- SC_R_VPU_MU_2 = 537,
- SC_R_VPU_MU_3 = 538,
- SC_R_VPU_ENC_1 = 539,
- SC_R_VPU = 540,
- SC_R_LAST
-} sc_rsrc_t;
-
-/* NOTE - please add by replacing some of the UNUSED from above! */
+typedef uint16_t sc_rsrc_t;
/*!
* This type is used to indicate a control.
*/
-typedef enum sc_ctrl_e
-{
-
- SC_C_TEMP = 0,
- SC_C_TEMP_HI = 1,
- SC_C_TEMP_LOW = 2,
- SC_C_PXL_LINK_MST1_ADDR = 3,
- SC_C_PXL_LINK_MST2_ADDR = 4,
- SC_C_PXL_LINK_MST_ENB = 5,
- SC_C_PXL_LINK_MST1_ENB = 6,
- SC_C_PXL_LINK_MST2_ENB = 7,
- SC_C_PXL_LINK_SLV1_ADDR = 8,
- SC_C_PXL_LINK_SLV2_ADDR = 9,
- SC_C_PXL_LINK_MST_VLD = 10,
- SC_C_PXL_LINK_MST1_VLD = 11,
- SC_C_PXL_LINK_MST2_VLD = 12,
- SC_C_SINGLE_MODE = 13,
- SC_C_ID = 14,
- SC_C_PXL_CLK_POLARITY = 15,
- SC_C_LINESTATE = 16,
- SC_C_PCIE_G_RST = 17,
- SC_C_PCIE_BUTTON_RST = 18,
- SC_C_PCIE_PERST = 19,
- SC_C_PHY_RESET = 20,
- SC_C_PXL_LINK_RATE_CORRECTION = 21,
- SC_C_PANIC = 22,
- SC_C_PRIORITY_GROUP = 23,
- SC_C_TXCLK = 24,
- SC_C_CLKDIV = 25,
- SC_C_DISABLE_50 = 26,
- SC_C_DISABLE_125 = 27,
- SC_C_SEL_125 = 28,
- SC_C_MODE = 29,
- SC_C_SYNC_CTRL0 = 30,
- SC_C_KACHUNK_CNT = 31,
- SC_C_KACHUNK_SEL = 32,
- SC_C_SYNC_CTRL1 = 33,
- SC_C_DPI_RESET = 34,
- SC_C_MIPI_RESET = 35,
- SC_C_DUAL_MODE = 36,
- SC_C_VOLTAGE = 37,
- SC_C_PXL_LINK_SEL = 38,
- SC_C_OFS_SEL = 39,
- SC_C_OFS_AUDIO = 40,
- SC_C_OFS_PERIPH = 41,
- SC_C_OFS_IRQ = 42,
- SC_C_RST0 = 43,
- SC_C_RST1 = 44,
- SC_C_LAST
-} sc_ctrl_t;
+typedef uint8_t sc_ctrl_t;
/*!
* This type is used to indicate a pad. Valid values are SoC specific.
@@ -780,50 +808,44 @@ typedef uint16_t sc_pad_t;
#ifdef DOXYGEN
/*!
- * Type used to declare a true/false boolean.
- */
- typedef enum {false = 0, true = 1} bool;
-
- /*!
* Type used to declare an 8-bit integer.
*/
- typedef __INT8_TYPE__ int8_t;
+typedef __INT8_TYPE__ int8_t;
/*!
* Type used to declare a 16-bit integer.
*/
- typedef __INT16_TYPE__ int16_t;
+typedef __INT16_TYPE__ int16_t;
/*!
* Type used to declare a 32-bit integer.
*/
- typedef __INT32_TYPE__ int32_t;
+typedef __INT32_TYPE__ int32_t;
/*!
* Type used to declare a 64-bit integer.
*/
- typedef __INT64_TYPE__ int64_t;
+typedef __INT64_TYPE__ int64_t;
/*!
* Type used to declare an 8-bit unsigned integer.
*/
- typedef __UINT8_TYPE__ uint8_t;
+typedef __UINT8_TYPE__ uint8_t;
/*!
* Type used to declare a 16-bit unsigned integer.
*/
- typedef __UINT16_TYPE__ uint16_t;
+typedef __UINT16_TYPE__ uint16_t;
/*!
* Type used to declare a 32-bit unsigned integer.
*/
- typedef __UINT32_TYPE__ uint32_t;
+typedef __UINT32_TYPE__ uint32_t;
/*!
* Type used to declare a 64-bit unsigned integer.
*/
- typedef __UINT64_TYPE__ uint64_t;
+typedef __UINT64_TYPE__ uint64_t;
#endif
-#endif /* _SC_TYPES_H */
-
+#endif /* SC_TYPES_H */
diff --git a/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c b/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c
index 3383fa63..0450723d 100644
--- a/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,369 +29,426 @@
/* Local Functions */
sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
- uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
+ uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_MUX;
- RPC_U16(&msg, 0) = pad;
- RPC_U8(&msg, 2) = mux;
- RPC_U8(&msg, 3) = config;
- RPC_U8(&msg, 4) = iso;
- RPC_SIZE(&msg) = 3;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_MUX;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_U8(&msg, 2U) = (uint8_t)mux;
+ RPC_U8(&msg, 3U) = (uint8_t)config;
+ RPC_U8(&msg, 4U) = (uint8_t)iso;
+ RPC_SIZE(&msg) = 3U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
- uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso)
+ uint8_t *mux, sc_pad_config_t *config,
+ sc_pad_iso_t *iso)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_MUX;
- RPC_U16(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- if (mux != NULL)
- *mux = RPC_U8(&msg, 0);
- if (config != NULL)
- *config = RPC_U8(&msg, 1);
- if (iso != NULL)
- *iso = RPC_U8(&msg, 2);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_MUX;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ if (mux != NULL) {
+ *mux = RPC_U8(&msg, 0U);
+ }
+
+ if (config != NULL) {
+ *config = RPC_U8(&msg, 1U);
+ }
+
+ if (iso != NULL) {
+ *iso = RPC_U8(&msg, 2U);
+ }
+
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP;
- RPC_U32(&msg, 0) = ctrl;
- RPC_U16(&msg, 4) = pad;
- RPC_SIZE(&msg) = 3;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP;
+ RPC_U32(&msg, 0U) = (uint32_t)ctrl;
+ RPC_U16(&msg, 4U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 3U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP;
- RPC_U16(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- if (ctrl != NULL)
- *ctrl = RPC_U32(&msg, 0);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ if (ctrl != NULL) {
+ *ctrl = RPC_U32(&msg, 0U);
+ }
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
-sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_wakeup_t wakeup)
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_WAKEUP;
- RPC_U16(&msg, 0) = pad;
- RPC_U8(&msg, 2) = wakeup;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_WAKEUP;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_U8(&msg, 2U) = (uint8_t)wakeup;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
-sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_wakeup_t *wakeup)
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_WAKEUP;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 2U;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_WAKEUP;
- RPC_U16(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- sc_call_rpc(ipc, &msg, false);
+ result = RPC_R8(&msg);
+ if (wakeup != NULL) {
+ *wakeup = RPC_U8(&msg, 0U);
+ }
- result = RPC_R8(&msg);
- if (wakeup != NULL)
- *wakeup = RPC_U8(&msg, 0);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
- sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
- sc_pad_wakeup_t wakeup)
+ sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+ sc_pad_wakeup_t wakeup)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_ALL;
- RPC_U32(&msg, 0) = ctrl;
- RPC_U16(&msg, 4) = pad;
- RPC_U8(&msg, 6) = mux;
- RPC_U8(&msg, 7) = config;
- RPC_U8(&msg, 8) = iso;
- RPC_U8(&msg, 9) = wakeup;
- RPC_SIZE(&msg) = 4;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_ALL;
+ RPC_U32(&msg, 0U) = (uint32_t)ctrl;
+ RPC_U16(&msg, 4U) = (uint16_t)pad;
+ RPC_U8(&msg, 6U) = (uint8_t)mux;
+ RPC_U8(&msg, 7U) = (uint8_t)config;
+ RPC_U8(&msg, 8U) = (uint8_t)iso;
+ RPC_U8(&msg, 9U) = (uint8_t)wakeup;
+ RPC_SIZE(&msg) = 4U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
- sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
- sc_pad_wakeup_t *wakeup)
+ sc_pad_config_t *config, sc_pad_iso_t *iso,
+ uint32_t *ctrl, sc_pad_wakeup_t *wakeup)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_ALL;
- RPC_U16(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
-
- sc_call_rpc(ipc, &msg, false);
-
- if (ctrl != NULL)
- *ctrl = RPC_U32(&msg, 0);
- result = RPC_R8(&msg);
- if (mux != NULL)
- *mux = RPC_U8(&msg, 4);
- if (config != NULL)
- *config = RPC_U8(&msg, 5);
- if (iso != NULL)
- *iso = RPC_U8(&msg, 6);
- if (wakeup != NULL)
- *wakeup = RPC_U8(&msg, 7);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_ALL;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ if (ctrl != NULL) {
+ *ctrl = RPC_U32(&msg, 0U);
+ }
+
+ result = RPC_R8(&msg);
+ if (mux != NULL) {
+ *mux = RPC_U8(&msg, 4U);
+ }
+
+ if (config != NULL) {
+ *config = RPC_U8(&msg, 5U);
+ }
+
+ if (iso != NULL) {
+ *iso = RPC_U8(&msg, 6U);
+ }
+
+ if (wakeup != NULL) {
+ *wakeup = RPC_U8(&msg, 7U);
+ }
+
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET;
- RPC_U32(&msg, 0) = val;
- RPC_U16(&msg, 4) = pad;
- RPC_SIZE(&msg) = 3;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET;
+ RPC_U32(&msg, 0U) = (uint32_t)val;
+ RPC_U16(&msg, 4U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 3U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET;
- RPC_U16(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- if (val != NULL)
- *val = RPC_U32(&msg, 0);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ if (val != NULL) {
+ *val = RPC_U32(&msg, 0U);
+ }
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI;
- RPC_U16(&msg, 0) = pad;
- RPC_U8(&msg, 2) = dse;
- RPC_U8(&msg, 3) = ps;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_U8(&msg, 2U) = (uint8_t)dse;
+ RPC_U8(&msg, 3U) = (uint8_t)ps;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps)
+ sc_pad_28fdsoi_dse_t *dse,
+ sc_pad_28fdsoi_ps_t *ps)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI;
- RPC_U16(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- if (dse != NULL)
- *dse = RPC_U8(&msg, 0);
- if (ps != NULL)
- *ps = RPC_U8(&msg, 1);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ if (dse != NULL) {
+ *dse = RPC_U8(&msg, 0U);
+ }
+
+ if (ps != NULL) {
+ *ps = RPC_U8(&msg, 1U);
+ }
+
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_28fdsoi_dse_t dse, bool hys, sc_pad_28fdsoi_pus_t pus,
- bool pke, bool pue)
+ sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
+ sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
+ sc_bool_t pue)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI_HSIC;
- RPC_U16(&msg, 0) = pad;
- RPC_U8(&msg, 2) = dse;
- RPC_U8(&msg, 3) = pus;
- RPC_U8(&msg, 4) = hys;
- RPC_U8(&msg, 5) = pke;
- RPC_U8(&msg, 6) = pue;
- RPC_SIZE(&msg) = 3;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_HSIC;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_U8(&msg, 2U) = (uint8_t)dse;
+ RPC_U8(&msg, 3U) = (uint8_t)pus;
+ RPC_U8(&msg, 4U) = (uint8_t)hys;
+ RPC_U8(&msg, 5U) = (uint8_t)pke;
+ RPC_U8(&msg, 6U) = (uint8_t)pue;
+ RPC_SIZE(&msg) = 3U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
- sc_pad_28fdsoi_dse_t *dse, bool *hys, sc_pad_28fdsoi_pus_t *pus,
- bool *pke, bool *pue)
+ sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
+ sc_pad_28fdsoi_pus_t * pus, sc_bool_t *pke,
+ sc_bool_t *pue)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI_HSIC;
- RPC_U16(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- if (dse != NULL)
- *dse = RPC_U8(&msg, 0);
- if (pus != NULL)
- *pus = RPC_U8(&msg, 1);
- if (hys != NULL)
- *hys = RPC_U8(&msg, 2);
- if (pke != NULL)
- *pke = RPC_U8(&msg, 3);
- if (pue != NULL)
- *pue = RPC_U8(&msg, 4);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_HSIC;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ if (dse != NULL) {
+ *dse = RPC_U8(&msg, 0U);
+ }
+
+ if (pus != NULL) {
+ *pus = RPC_U8(&msg, 1U);
+ }
+
+ if (hys != NULL) {
+ *hys = RPC_U8(&msg, 2U);
+ }
+
+ if (pke != NULL) {
+ *pke = RPC_U8(&msg, 3U);
+ }
+
+ if (pue != NULL) {
+ *pue = RPC_U8(&msg, 4U);
+ }
+
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
- uint8_t compen, bool fastfrz, uint8_t rasrcp, uint8_t rasrcn,
- bool nasrc_sel, bool psw_ovr)
+ uint8_t compen, sc_bool_t fastfrz,
+ uint8_t rasrcp, uint8_t rasrcn,
+ sc_bool_t nasrc_sel, sc_bool_t psw_ovr)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI_COMP;
- RPC_U16(&msg, 0) = pad;
- RPC_U8(&msg, 2) = compen;
- RPC_U8(&msg, 3) = rasrcp;
- RPC_U8(&msg, 4) = rasrcn;
- RPC_U8(&msg, 5) = fastfrz;
- RPC_U8(&msg, 6) = nasrc_sel;
- RPC_U8(&msg, 7) = psw_ovr;
- RPC_SIZE(&msg) = 3;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_COMP;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_U8(&msg, 2U) = (uint8_t)compen;
+ RPC_U8(&msg, 3U) = (uint8_t)rasrcp;
+ RPC_U8(&msg, 4U) = (uint8_t)rasrcn;
+ RPC_U8(&msg, 5U) = (uint8_t)fastfrz;
+ RPC_U8(&msg, 6U) = (uint8_t)nasrc_sel;
+ RPC_U8(&msg, 7U) = (uint8_t)psw_ovr;
+ RPC_SIZE(&msg) = 3U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
- uint8_t *compen, bool *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
- bool *nasrc_sel, bool *compok, uint8_t *nasrc, bool *psw_ovr)
+ uint8_t *compen, sc_bool_t *fastfrz,
+ uint8_t *rasrcp, uint8_t *rasrcn,
+ sc_bool_t *nasrc_sel, sc_bool_t *compok,
+ uint8_t *nasrc, sc_bool_t *psw_ovr)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI_COMP;
- RPC_U16(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- if (compen != NULL)
- *compen = RPC_U8(&msg, 0);
- if (rasrcp != NULL)
- *rasrcp = RPC_U8(&msg, 1);
- if (rasrcn != NULL)
- *rasrcn = RPC_U8(&msg, 2);
- if (nasrc != NULL)
- *nasrc = RPC_U8(&msg, 3);
- if (fastfrz != NULL)
- *fastfrz = RPC_U8(&msg, 4);
- if (nasrc_sel != NULL)
- *nasrc_sel = RPC_U8(&msg, 5);
- if (compok != NULL)
- *compok = RPC_U8(&msg, 6);
- if (psw_ovr != NULL)
- *psw_ovr = RPC_U8(&msg, 7);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_COMP;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ if (compen != NULL) {
+ *compen = RPC_U8(&msg, 0U);
+ }
+
+ if (rasrcp != NULL) {
+ *rasrcp = RPC_U8(&msg, 1U);
+ }
+
+ if (rasrcn != NULL) {
+ *rasrcn = RPC_U8(&msg, 2U);
+ }
+
+ if (nasrc != NULL) {
+ *nasrc = RPC_U8(&msg, 3U);
+ }
+
+ if (fastfrz != NULL) {
+ *fastfrz = RPC_U8(&msg, 4U);
+ }
+
+ if (nasrc_sel != NULL) {
+ *nasrc_sel = RPC_U8(&msg, 5U);
+ }
+
+ if (compok != NULL) {
+ *compok = RPC_U8(&msg, 6U);
+ }
+
+ if (psw_ovr != NULL) {
+ *psw_ovr = RPC_U8(&msg, 7U);
+ }
+
+ return (sc_err_t)result;
}
/**@}*/
diff --git a/plat/imx/common/sci/svc/pad/rpc.h b/plat/imx/common/sci/svc/pad/rpc.h
index 571e06d3..a6416fb3 100644
--- a/plat/imx/common/sci/svc/pad/rpc.h
+++ b/plat/imx/common/sci/svc/pad/rpc.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,38 +12,37 @@
* @{
*/
-#ifndef _SC_PAD_RPC_H
-#define _SC_PAD_RPC_H
+#ifndef SC_PAD_RPC_H
+#define SC_PAD_RPC_H
/* Includes */
/* Defines */
-/* Types */
-
/*!
- * This type is used to indicate RPC PAD function calls.
+ * @name Defines for RPC PAD function calls
*/
-typedef enum pad_func_e
-{
- PAD_FUNC_UNKNOWN = 0, /*!< Unknown function */
- PAD_FUNC_SET_MUX = 1, /*!< Index for pad_set_mux() RPC call */
- PAD_FUNC_GET_MUX = 6, /*!< Index for pad_get_mux() RPC call */
- PAD_FUNC_SET_GP = 2, /*!< Index for pad_set_gp() RPC call */
- PAD_FUNC_GET_GP = 7, /*!< Index for pad_get_gp() RPC call */
- PAD_FUNC_SET_WAKEUP = 4, /*!< Index for pad_set_wakeup() RPC call */
- PAD_FUNC_GET_WAKEUP = 9, /*!< Index for pad_get_wakeup() RPC call */
- PAD_FUNC_SET_ALL = 5, /*!< Index for pad_set_all() RPC call */
- PAD_FUNC_GET_ALL = 10, /*!< Index for pad_get_all() RPC call */
- PAD_FUNC_SET = 15, /*!< Index for pad_set() RPC call */
- PAD_FUNC_GET = 16, /*!< Index for pad_get() RPC call */
- PAD_FUNC_SET_GP_28FDSOI = 11, /*!< Index for pad_set_gp_28fdsoi() RPC call */
- PAD_FUNC_GET_GP_28FDSOI = 12, /*!< Index for pad_get_gp_28fdsoi() RPC call */
- PAD_FUNC_SET_GP_28FDSOI_HSIC = 3, /*!< Index for pad_set_gp_28fdsoi_hsic() RPC call */
- PAD_FUNC_GET_GP_28FDSOI_HSIC = 8, /*!< Index for pad_get_gp_28fdsoi_hsic() RPC call */
- PAD_FUNC_SET_GP_28FDSOI_COMP = 13, /*!< Index for pad_set_gp_28fdsoi_comp() RPC call */
- PAD_FUNC_GET_GP_28FDSOI_COMP = 14, /*!< Index for pad_get_gp_28fdsoi_comp() RPC call */
-} pad_func_t;
+/*@{*/
+#define PAD_FUNC_UNKNOWN 0 /* Unknown function */
+#define PAD_FUNC_SET_MUX 1U /* Index for pad_set_mux() RPC call */
+#define PAD_FUNC_GET_MUX 6U /* Index for pad_get_mux() RPC call */
+#define PAD_FUNC_SET_GP 2U /* Index for pad_set_gp() RPC call */
+#define PAD_FUNC_GET_GP 7U /* Index for pad_get_gp() RPC call */
+#define PAD_FUNC_SET_WAKEUP 4U /* Index for pad_set_wakeup() RPC call */
+#define PAD_FUNC_GET_WAKEUP 9U /* Index for pad_get_wakeup() RPC call */
+#define PAD_FUNC_SET_ALL 5U /* Index for pad_set_all() RPC call */
+#define PAD_FUNC_GET_ALL 10U /* Index for pad_get_all() RPC call */
+#define PAD_FUNC_SET 15U /* Index for pad_set() RPC call */
+#define PAD_FUNC_GET 16U /* Index for pad_get() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI 11U /* Index for pad_set_gp_28fdsoi() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI 12U /* Index for pad_get_gp_28fdsoi() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /* Index for pad_set_gp_28fdsoi_hsic() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /* Index for pad_get_gp_28fdsoi_hsic() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /* Index for pad_set_gp_28fdsoi_comp() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /* Index for pad_get_gp_28fdsoi_comp() RPC call */
+/*@}*/
+
+/* Types */
/* Functions */
@@ -63,7 +62,6 @@ void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
*/
void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-#endif /* _SC_PAD_RPC_H */
+#endif /* SC_PAD_RPC_H */
/**@}*/
-
diff --git a/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c b/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c
index 58206a2d..30da7d75 100644
--- a/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c
@@ -1,13 +1,13 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*!
* File containing client-side RPC functions for the PM service. These
- * function are ported to clients that communicate to the SC.
+ * functions are ported to clients that communicate to the SC.
*
* @addtogroup PM_SVC
* @{
@@ -30,97 +30,101 @@
sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_SYS_POWER_MODE;
- RPC_U8(&msg, 0) = mode;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_SYS_POWER_MODE;
+ RPC_U8(&msg, 0U) = (uint8_t)mode;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_pm_power_mode_t mode)
+ sc_pm_power_mode_t mode)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_SYS_POWER_MODE;
- RPC_U8(&msg, 0) = pt;
- RPC_U8(&msg, 1) = mode;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_PARTITION_POWER_MODE;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_U8(&msg, 1U) = (uint8_t)mode;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_pm_power_mode_t *mode)
+ sc_pm_power_mode_t *mode)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_GET_SYS_POWER_MODE;
- RPC_U8(&msg, 0) = pt;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_SYS_POWER_MODE;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- if (mode != NULL)
- *mode = RPC_U8(&msg, 0);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ if (mode != NULL) {
+ *mode = RPC_U8(&msg, 0U);
+ }
+
+ return (sc_err_t)result;
}
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_power_mode_t mode)
+ sc_pm_power_mode_t mode)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_RESOURCE_POWER_MODE;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = mode;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_RESOURCE_POWER_MODE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)mode;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_power_mode_t *mode)
+ sc_pm_power_mode_t *mode)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_RESOURCE_POWER_MODE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_SIZE(&msg) = 2U;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_GET_RESOURCE_POWER_MODE;
- RPC_U16(&msg, 0) = resource;
- RPC_SIZE(&msg) = 2;
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- sc_call_rpc(ipc, &msg, false);
+ result = RPC_R8(&msg);
+ if (mode != NULL) {
+ *mode = RPC_U8(&msg, 0U);
+ }
- result = RPC_R8(&msg);
- if (mode != NULL)
- *mode = RPC_U8(&msg, 0);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
@@ -130,13 +134,34 @@ sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_REQ_LOW_POWER_MODE;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = mode;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_LOW_POWER_MODE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)mode;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
+}
+
+sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_pm_power_mode_t mode,
+ sc_pm_wake_src_t wake_src)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_CPU_LOW_POWER_MODE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)mode;
+ RPC_U8(&msg, 3U) = (uint8_t)wake_src;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -149,141 +174,168 @@ sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_CPU_RESUME_ADDR;
- RPC_U32(&msg, 0) = address >> 32;
- RPC_U32(&msg, 4) = address;
- RPC_U16(&msg, 8) = resource;
- RPC_SIZE(&msg) = 4;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME_ADDR;
+ RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
+ RPC_U32(&msg, 4U) = (uint32_t)address;
+ RPC_U16(&msg, 8U) = (uint16_t)resource;
+ RPC_SIZE(&msg) = 4U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
+}
+
+sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_bool_t isPrimary, sc_faddr_t address)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME;
+ RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
+ RPC_U32(&msg, 4U) = (uint32_t)address;
+ RPC_U16(&msg, 8U) = (uint16_t)resource;
+ RPC_U8(&msg, 10U) = (uint8_t)isPrimary;
+ RPC_SIZE(&msg) = 4U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm)
+ sc_pm_sys_if_t sys_if,
+ sc_pm_power_mode_t hpm,
+ sc_pm_power_mode_t lpm)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_REQ_SYS_IF_POWER_MODE;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = sys_if;
- RPC_U8(&msg, 3) = hpm;
- RPC_U8(&msg, 4) = lpm;
- RPC_SIZE(&msg) = 3;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_SYS_IF_POWER_MODE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)sys_if;
+ RPC_U8(&msg, 3U) = (uint8_t)hpm;
+ RPC_U8(&msg, 4U) = (uint8_t)lpm;
+ RPC_SIZE(&msg) = 3U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+ sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_CLOCK_RATE;
- RPC_U32(&msg, 0) = *rate;
- RPC_U16(&msg, 4) = resource;
- RPC_U8(&msg, 6) = clk;
- RPC_SIZE(&msg) = 3;
-
- sc_call_rpc(ipc, &msg, false);
-
- *rate = RPC_U32(&msg, 0);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_RATE;
+ RPC_U32(&msg, 0U) = *(uint32_t *)rate;
+ RPC_U16(&msg, 4U) = (uint16_t)resource;
+ RPC_U8(&msg, 6U) = (uint8_t)clk;
+ RPC_SIZE(&msg) = 3U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ *rate = RPC_U32(&msg, 0U);
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+ sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_GET_CLOCK_RATE;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = clk;
- RPC_SIZE(&msg) = 2;
-
- sc_call_rpc(ipc, &msg, false);
-
- if (rate != NULL)
- *rate = RPC_U32(&msg, 0);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_RATE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)clk;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ if (rate != NULL) {
+ *rate = RPC_U32(&msg, 0U);
+ }
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_pm_clk_t clk, bool enable, bool autog)
+ sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_CLOCK_ENABLE;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = clk;
- RPC_U8(&msg, 3) = enable;
- RPC_U8(&msg, 4) = autog;
- RPC_SIZE(&msg) = 3;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CLOCK_ENABLE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)clk;
+ RPC_U8(&msg, 3U) = (uint8_t)enable;
+ RPC_U8(&msg, 4U) = (uint8_t)autog;
+ RPC_SIZE(&msg) = 3U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clk_parent_t parent)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_SET_CLOCK_PARENT;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = clk;
- RPC_U8(&msg, 3) = parent;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_PARENT;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)clk;
+ RPC_U8(&msg, 3U) = (uint8_t)parent;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, sc_pm_clk_parent_t * parent)
{
- sc_rpc_msg_t msg;
+ sc_rpc_msg_t msg;
uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_GET_CLOCK_PARENT;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = clk;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_PARENT;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)clk;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- if (parent != NULL)
- *parent = RPC_U8(&msg, 0);
+ if (parent != NULL) {
+ *parent = RPC_U8(&msg, 0U);
+ }
+
return (sc_err_t)result;
}
@@ -293,12 +345,12 @@ sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_RESET;
- RPC_U8(&msg, 0) = type;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET;
+ RPC_U8(&msg, 0U) = (uint8_t)type;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -306,19 +358,21 @@ sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
{
- sc_rpc_msg_t msg;
+ sc_rpc_msg_t msg;
uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_RESET_REASON;
- RPC_SIZE(&msg) = 1;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET_REASON;
+ RPC_SIZE(&msg) = 1U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- if (reason != NULL)
- *reason = RPC_U8(&msg, 0);
+ if (reason != NULL) {
+ *reason = RPC_U8(&msg, 0U);
+ }
+
return (sc_err_t)result;
}
@@ -326,24 +380,24 @@ sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
sc_rsrc_t resource_mu, sc_rsrc_t resource_dev)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_BOOT;
- RPC_U32(&msg, 0) = boot_addr >> 32;
- RPC_U32(&msg, 4) = boot_addr;
- RPC_U16(&msg, 8) = resource_cpu;
- RPC_U16(&msg, 10) = resource_mu;
- RPC_U16(&msg, 12) = resource_dev;
- RPC_U8(&msg, 14) = pt;
- RPC_SIZE(&msg) = 5;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_BOOT;
+ RPC_U32(&msg, 0U) = (uint32_t)(boot_addr >> 32U);
+ RPC_U32(&msg, 4U) = (uint32_t)boot_addr;
+ RPC_U16(&msg, 8U) = (uint16_t)resource_cpu;
+ RPC_U16(&msg, 10U) = (uint16_t)resource_mu;
+ RPC_U16(&msg, 12U) = (uint16_t)resource_dev;
+ RPC_U8(&msg, 14U) = (uint8_t)pt;
+ RPC_SIZE(&msg) = 5U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
@@ -351,55 +405,54 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_REBOOT;
- RPC_U8(&msg, 0) = type;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT;
+ RPC_U8(&msg, 0U) = (uint8_t)type;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, true);
+ sc_call_rpc(ipc, &msg, SC_TRUE);
return;
}
sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_pm_reset_type_t type)
+ sc_pm_reset_type_t type)
{
- sc_rpc_msg_t msg;
- uint8_t result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_REBOOT_PARTITION;
- RPC_U8(&msg, 0) = pt;
- RPC_U8(&msg, 1) = type;
- RPC_SIZE(&msg) = 2;
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT_PARTITION;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_U8(&msg, 1U) = (uint8_t)type;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
-sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
sc_faddr_t address)
{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_CPU_START;
- RPC_U32(&msg, 0) = address >> 32;
- RPC_U32(&msg, 4) = address;
- RPC_U16(&msg, 8) = resource;
- RPC_U8(&msg, 10) = enable;
- RPC_SIZE(&msg) = 4;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CPU_START;
+ RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
+ RPC_U32(&msg, 4U) = (uint32_t)address;
+ RPC_U16(&msg, 8U) = (uint16_t)resource;
+ RPC_U8(&msg, 10U) = (uint8_t)enable;
+ RPC_SIZE(&msg) = 4U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
}
/**@}*/
-
diff --git a/plat/imx/common/sci/svc/pm/rpc.h b/plat/imx/common/sci/svc/pm/rpc.h
index bd63b8fc..9e9304f0 100644
--- a/plat/imx/common/sci/svc/pm/rpc.h
+++ b/plat/imx/common/sci/svc/pm/rpc.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,41 +12,42 @@
* @{
*/
-#ifndef _SC_PM_RPC_H
-#define _SC_PM_RPC_H
+#ifndef SC_PM_RPC_H
+#define SC_PM_RPC_H
/* Includes */
/* Defines */
-/* Types */
-
/*!
- * This type is used to indicate RPC PM function calls.
+ * @name Defines for RPC PM function calls
*/
-typedef enum pm_func_e
-{
- PM_FUNC_UNKNOWN = 0, /*!< Unknown function */
- PM_FUNC_SET_SYS_POWER_MODE = 19, /*!< Index for pm_set_sys_power_mode() RPC call */
- PM_FUNC_SET_PARTITION_POWER_MODE = 1, /*!< Index for pm_set_partition_power_mode() RPC call */
- PM_FUNC_GET_SYS_POWER_MODE = 2, /*!< Index for pm_get_sys_power_mode() RPC call */
- PM_FUNC_SET_RESOURCE_POWER_MODE = 3, /*!< Index for pm_set_resource_power_mode() RPC call */
- PM_FUNC_GET_RESOURCE_POWER_MODE = 4, /*!< Index for pm_get_resource_power_mode() RPC call */
- PM_FUNC_REQ_LOW_POWER_MODE = 16, /*!< Index for pm_req_low_power_mode() RPC call */
- PM_FUNC_SET_CPU_RESUME_ADDR = 17, /*!< Index for pm_set_cpu_resume_addr() RPC call */
- PM_FUNC_REQ_SYS_IF_POWER_MODE = 18, /*!< Index for pm_req_sys_if_power_mode() RPC call */
- PM_FUNC_SET_CLOCK_RATE = 5, /*!< Index for pm_set_clock_rate() RPC call */
- PM_FUNC_GET_CLOCK_RATE = 6, /*!< Index for pm_get_clock_rate() RPC call */
- PM_FUNC_CLOCK_ENABLE = 7, /*!< Index for pm_clock_enable() RPC call */
- PM_FUNC_SET_CLOCK_PARENT = 14, /*!< Index for pm_set_clock_parent() RPC call */
- PM_FUNC_GET_CLOCK_PARENT = 15, /*!< Index for pm_get_clock_parent() RPC call */
- PM_FUNC_RESET = 13, /*!< Index for pm_reset() RPC call */
- PM_FUNC_RESET_REASON = 10, /*!< Index for pm_reset_reason() RPC call */
- PM_FUNC_BOOT = 8, /*!< Index for pm_boot() RPC call */
- PM_FUNC_REBOOT = 9, /*!< Index for pm_reboot() RPC call */
- PM_FUNC_REBOOT_PARTITION = 12, /*!< Index for pm_reboot_partition() RPC call */
- PM_FUNC_CPU_START = 11, /*!< Index for pm_cpu_start() RPC call */
-} pm_func_t;
+/*@{*/
+#define PM_FUNC_UNKNOWN 0 /* Unknown function */
+#define PM_FUNC_SET_SYS_POWER_MODE 19U /* Index for pm_set_sys_power_mode() RPC call */
+#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /* Index for pm_set_partition_power_mode() RPC call */
+#define PM_FUNC_GET_SYS_POWER_MODE 2U /* Index for pm_get_sys_power_mode() RPC call */
+#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /* Index for pm_set_resource_power_mode() RPC call */
+#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /* Index for pm_get_resource_power_mode() RPC call */
+#define PM_FUNC_REQ_LOW_POWER_MODE 16U /* Index for pm_req_low_power_mode() RPC call */
+#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /* Index for pm_req_cpu_low_power_mode() RPC call */
+#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /* Index for pm_set_cpu_resume_addr() RPC call */
+#define PM_FUNC_SET_CPU_RESUME 21U /* Index for pm_set_cpu_resume() RPC call */
+#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /* Index for pm_req_sys_if_power_mode() RPC call */
+#define PM_FUNC_SET_CLOCK_RATE 5U /* Index for pm_set_clock_rate() RPC call */
+#define PM_FUNC_GET_CLOCK_RATE 6U /* Index for pm_get_clock_rate() RPC call */
+#define PM_FUNC_CLOCK_ENABLE 7U /* Index for pm_clock_enable() RPC call */
+#define PM_FUNC_SET_CLOCK_PARENT 14U /* Index for pm_set_clock_parent() RPC call */
+#define PM_FUNC_GET_CLOCK_PARENT 15U /* Index for pm_get_clock_parent() RPC call */
+#define PM_FUNC_RESET 13U /* Index for pm_reset() RPC call */
+#define PM_FUNC_RESET_REASON 10U /* Index for pm_reset_reason() RPC call */
+#define PM_FUNC_BOOT 8U /* Index for pm_boot() RPC call */
+#define PM_FUNC_REBOOT 9U /* Index for pm_reboot() RPC call */
+#define PM_FUNC_REBOOT_PARTITION 12U /* Index for pm_reboot_partition() RPC call */
+#define PM_FUNC_CPU_START 11U /* Index for pm_cpu_start() RPC call */
+/*@}*/
+
+/* Types */
/* Functions */
@@ -66,7 +67,6 @@ void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
*/
void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-#endif /* _SC_PM_RPC_H */
+#endif /* SC_PM_RPC_H */
/**@}*/
-
diff --git a/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c b/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c
index 4cb76134..f0591ed8 100644
--- a/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,44 +27,46 @@
/* Local Functions */
-sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
- bool isolated, bool restricted, bool grant,
- bool coherent)
+sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
+ sc_bool_t isolated, sc_bool_t restricted,
+ sc_bool_t grant, sc_bool_t coherent)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_PARTITION_ALLOC;
- RPC_U8(&msg, 0) = secure;
- RPC_U8(&msg, 1) = isolated;
- RPC_U8(&msg, 2) = restricted;
- RPC_U8(&msg, 3) = grant;
- RPC_U8(&msg, 4) = coherent;
- RPC_SIZE(&msg) = 3;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_ALLOC;
+ RPC_U8(&msg, 0U) = (uint8_t)secure;
+ RPC_U8(&msg, 1U) = (uint8_t)isolated;
+ RPC_U8(&msg, 2U) = (uint8_t)restricted;
+ RPC_U8(&msg, 3U) = (uint8_t)grant;
+ RPC_U8(&msg, 4U) = (uint8_t)coherent;
+ RPC_SIZE(&msg) = 3U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- if (pt != NULL)
- *pt = RPC_U8(&msg, 0);
+ if (pt != NULL) {
+ *pt = RPC_U8(&msg, 0U);
+ }
+
return (sc_err_t)result;
}
-sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, bool retro)
+sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_CONFIDENTIAL;
- RPC_U8(&msg, 0) = pt;
- RPC_U8(&msg, 1) = retro;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_CONFIDENTIAL;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_U8(&msg, 1U) = (uint8_t)retro;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -76,12 +78,12 @@ sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_PARTITION_FREE;
- RPC_U8(&msg, 0) = pt;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_FREE;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -93,30 +95,29 @@ sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_GET_DID;
- RPC_SIZE(&msg) = 1;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_DID;
+ RPC_SIZE(&msg) = 1U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_rm_did_t) result;
}
-sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_rm_did_t did)
+sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_PARTITION_STATIC;
- RPC_U8(&msg, 0) = pt;
- RPC_U8(&msg, 1) = did;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_STATIC;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_U8(&msg, 1U) = (uint8_t)did;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -128,12 +129,12 @@ sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_PARTITION_LOCK;
- RPC_U8(&msg, 0) = pt;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_LOCK;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -145,151 +146,151 @@ sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_GET_PARTITION;
- RPC_SIZE(&msg) = 1;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_PARTITION;
+ RPC_SIZE(&msg) = 1U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- if (pt != NULL)
- *pt = RPC_U8(&msg, 0);
+ if (pt != NULL) {
+ *pt = RPC_U8(&msg, 0U);
+ }
+
return (sc_err_t)result;
}
-sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_rm_pt_t pt_parent)
+sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_PARENT;
- RPC_U8(&msg, 0) = pt;
- RPC_U8(&msg, 1) = pt_parent;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PARENT;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_U8(&msg, 1U) = (uint8_t)pt_parent;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
- bool move_rsrc, bool move_pads)
+ sc_bool_t move_rsrc, sc_bool_t move_pads)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_MOVE_ALL;
- RPC_U8(&msg, 0) = pt_src;
- RPC_U8(&msg, 1) = pt_dst;
- RPC_U8(&msg, 2) = move_rsrc;
- RPC_U8(&msg, 3) = move_pads;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MOVE_ALL;
+ RPC_U8(&msg, 0U) = (uint8_t)pt_src;
+ RPC_U8(&msg, 1U) = (uint8_t)pt_dst;
+ RPC_U8(&msg, 2U) = (uint8_t)move_rsrc;
+ RPC_U8(&msg, 3U) = (uint8_t)move_pads;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
-sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_rsrc_t resource)
+sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_ASSIGN_RESOURCE;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = pt;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_RESOURCE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)pt;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
- sc_rsrc_t resource_lst, bool movable)
+ sc_rsrc_t resource_lst, sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_RESOURCE_MOVABLE;
- RPC_U16(&msg, 0) = resource_fst;
- RPC_U16(&msg, 2) = resource_lst;
- RPC_U8(&msg, 4) = movable;
- RPC_SIZE(&msg) = 3;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_RESOURCE_MOVABLE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource_fst;
+ RPC_U16(&msg, 2U) = (uint16_t)resource_lst;
+ RPC_U8(&msg, 4U) = (uint8_t)movable;
+ RPC_SIZE(&msg) = 3U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
- bool movable)
+ sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = movable;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)movable;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_rm_spa_t sa, sc_rm_spa_t pa, bool smmu_bypass)
+ sc_rm_spa_t sa, sc_rm_spa_t pa,
+ sc_bool_t smmu_bypass)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_MASTER_ATTRIBUTES;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = sa;
- RPC_U8(&msg, 3) = pa;
- RPC_U8(&msg, 4) = smmu_bypass;
- RPC_SIZE(&msg) = 3;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_ATTRIBUTES;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)sa;
+ RPC_U8(&msg, 3U) = (uint8_t)pa;
+ RPC_U8(&msg, 4U) = (uint8_t)smmu_bypass;
+ RPC_SIZE(&msg) = 3U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
-sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_rm_sid_t sid)
+sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_MASTER_SID;
- RPC_U16(&msg, 0) = resource;
- RPC_U16(&msg, 2) = sid;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_SID;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U16(&msg, 2U) = (uint16_t)sid;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -302,68 +303,68 @@ sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
- RPC_U16(&msg, 0) = resource;
- RPC_U8(&msg, 2) = pt;
- RPC_U8(&msg, 3) = perm;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_U8(&msg, 2U) = (uint8_t)pt;
+ RPC_U8(&msg, 3U) = (uint8_t)perm;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
-bool sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
+sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_OWNED;
- RPC_U16(&msg, 0) = resource;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_OWNED;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- return (bool)result;
+ return (sc_bool_t)result;
}
-bool sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource)
+sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_MASTER;
- RPC_U16(&msg, 0) = resource;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_MASTER;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- return (bool)result;
+ return (sc_bool_t)result;
}
-bool sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource)
+sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_PERIPHERAL;
- RPC_U16(&msg, 0) = resource;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_PERIPHERAL;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- return (bool)result;
+ return (sc_bool_t)result;
}
sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
@@ -373,15 +374,17 @@ sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_GET_RESOURCE_INFO;
- RPC_U16(&msg, 0) = resource;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_RESOURCE_INFO;
+ RPC_U16(&msg, 0U) = (uint16_t)resource;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ if (sid != NULL) {
+ *sid = RPC_U16(&msg, 0U);
+ }
- if (sid != NULL)
- *sid = RPC_U16(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
@@ -393,43 +396,48 @@ sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_MEMREG_ALLOC;
- RPC_U32(&msg, 0) = addr_start >> 32;
- RPC_U32(&msg, 4) = addr_start;
- RPC_U32(&msg, 8) = addr_end >> 32;
- RPC_U32(&msg, 12) = addr_end;
- RPC_SIZE(&msg) = 5;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_ALLOC;
+ RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
+ RPC_U32(&msg, 4U) = (uint32_t)addr_start;
+ RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
+ RPC_U32(&msg, 12U) = (uint32_t)addr_end;
+ RPC_SIZE(&msg) = 5U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- if (mr != NULL)
- *mr = RPC_U8(&msg, 0);
+ if (mr != NULL) {
+ *mr = RPC_U8(&msg, 0U);
+ }
+
return (sc_err_t)result;
}
sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
- sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end)
+ sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
+ sc_faddr_t addr_end)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_MEMREG_SPLIT;
- RPC_U32(&msg, 0) = addr_start >> 32;
- RPC_U32(&msg, 4) = addr_start;
- RPC_U32(&msg, 8) = addr_end >> 32;
- RPC_U32(&msg, 12) = addr_end;
- RPC_U8(&msg, 16) = mr;
- RPC_SIZE(&msg) = 6;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_SPLIT;
+ RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
+ RPC_U32(&msg, 4U) = (uint32_t)addr_start;
+ RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
+ RPC_U32(&msg, 12U) = (uint32_t)addr_end;
+ RPC_U8(&msg, 16U) = (uint8_t)mr;
+ RPC_SIZE(&msg) = 6U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- if (mr_ret != NULL)
- *mr_ret = RPC_U8(&msg, 0);
+ if (mr_ret != NULL) {
+ *mr_ret = RPC_U8(&msg, 0U);
+ }
+
return (sc_err_t)result;
}
@@ -439,12 +447,12 @@ sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_MEMREG_FREE;
- RPC_U8(&msg, 0) = mr;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_FREE;
+ RPC_U8(&msg, 0U) = (uint8_t)mr;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -457,19 +465,21 @@ sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_FIND_MEMREG;
- RPC_U32(&msg, 0) = addr_start >> 32;
- RPC_U32(&msg, 4) = addr_start;
- RPC_U32(&msg, 8) = addr_end >> 32;
- RPC_U32(&msg, 12) = addr_end;
- RPC_SIZE(&msg) = 5;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_FIND_MEMREG;
+ RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
+ RPC_U32(&msg, 4U) = (uint32_t)addr_start;
+ RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
+ RPC_U32(&msg, 12U) = (uint32_t)addr_end;
+ RPC_SIZE(&msg) = 5U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- if (mr != NULL)
- *mr = RPC_U8(&msg, 0);
+ if (mr != NULL) {
+ *mr = RPC_U8(&msg, 0U);
+ }
+
return (sc_err_t)result;
}
@@ -479,13 +489,13 @@ sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_ASSIGN_MEMREG;
- RPC_U8(&msg, 0) = pt;
- RPC_U8(&msg, 1) = mr;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_MEMREG;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_U8(&msg, 1U) = (uint8_t)mr;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -498,34 +508,34 @@ sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_MEMREG_PERMISSIONS;
- RPC_U8(&msg, 0) = mr;
- RPC_U8(&msg, 1) = pt;
- RPC_U8(&msg, 2) = perm;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MEMREG_PERMISSIONS;
+ RPC_U8(&msg, 0U) = (uint8_t)mr;
+ RPC_U8(&msg, 1U) = (uint8_t)pt;
+ RPC_U8(&msg, 2U) = (uint8_t)perm;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
-bool sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
+sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_MEMREG_OWNED;
- RPC_U8(&msg, 0) = mr;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_MEMREG_OWNED;
+ RPC_U8(&msg, 0U) = (uint8_t)mr;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- return (bool)result;
+ return (sc_bool_t)result;
}
sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
@@ -535,17 +545,23 @@ sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_GET_MEMREG_INFO;
- RPC_U8(&msg, 0) = mr;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_MEMREG_INFO;
+ RPC_U8(&msg, 0U) = (uint8_t)mr;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ if (addr_start != NULL) {
+ *addr_start =
+ ((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U);
+ }
- sc_call_rpc(ipc, &msg, false);
+ if (addr_end != NULL) {
+ *addr_end =
+ ((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U);
+ }
- if (addr_start != NULL)
- *addr_start = ((uint64_t) RPC_U32(&msg, 0) << 32) | RPC_U32(&msg, 4);
- if (addr_end != NULL)
- *addr_end = ((uint64_t) RPC_U32(&msg, 8) << 32) | RPC_U32(&msg, 12);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
@@ -556,53 +572,53 @@ sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_ASSIGN_PAD;
- RPC_U16(&msg, 0) = pad;
- RPC_U8(&msg, 2) = pt;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_PAD;
+ RPC_U16(&msg, 0U) = (uint16_t)pad;
+ RPC_U8(&msg, 2U) = (uint8_t)pt;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
- sc_pad_t pad_lst, bool movable)
+ sc_pad_t pad_lst, sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_PAD_MOVABLE;
- RPC_U16(&msg, 0) = pad_fst;
- RPC_U16(&msg, 2) = pad_lst;
- RPC_U8(&msg, 4) = movable;
- RPC_SIZE(&msg) = 3;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PAD_MOVABLE;
+ RPC_U16(&msg, 0U) = (uint16_t)pad_fst;
+ RPC_U16(&msg, 2U) = (uint16_t)pad_lst;
+ RPC_U8(&msg, 4U) = (uint8_t)movable;
+ RPC_SIZE(&msg) = 3U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
-bool sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
+sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_PAD_OWNED;
- RPC_U8(&msg, 0) = pad;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_PAD_OWNED;
+ RPC_U8(&msg, 0U) = (uint8_t)pad;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
- return (bool)result;
+ return (sc_bool_t)result;
}
void sc_rm_dump(sc_ipc_t ipc)
@@ -610,11 +626,11 @@ void sc_rm_dump(sc_ipc_t ipc)
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_DUMP;
- RPC_SIZE(&msg) = 1;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
+ RPC_FUNC(&msg) = (uint8_t)RM_FUNC_DUMP;
+ RPC_SIZE(&msg) = 1U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
return;
}
diff --git a/plat/imx/common/sci/svc/rm/rpc.h b/plat/imx/common/sci/svc/rm/rpc.h
index 3376b9c9..65eaa609 100644
--- a/plat/imx/common/sci/svc/rm/rpc.h
+++ b/plat/imx/common/sci/svc/rm/rpc.h
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,53 +12,52 @@
* @{
*/
-#ifndef _SC_RM_RPC_H
-#define _SC_RM_RPC_H
+#ifndef SC_RM_RPC_H
+#define SC_RM_RPC_H
/* Includes */
/* Defines */
-/* Types */
-
/*!
- * This type is used to indicate RPC RM function calls.
+ * @name Defines for RPC RM function calls
*/
-typedef enum rm_func_e
-{
- RM_FUNC_UNKNOWN = 0, /*!< Unknown function */
- RM_FUNC_PARTITION_ALLOC = 1, /*!< Index for rm_partition_alloc() RPC call */
- RM_FUNC_SET_CONFIDENTIAL = 31, /*!< Index for rm_set_confidential() RPC call */
- RM_FUNC_PARTITION_FREE = 2, /*!< Index for rm_partition_free() RPC call */
- RM_FUNC_GET_DID = 26, /*!< Index for rm_get_did() RPC call */
- RM_FUNC_PARTITION_STATIC = 3, /*!< Index for rm_partition_static() RPC call */
- RM_FUNC_PARTITION_LOCK = 4, /*!< Index for rm_partition_lock() RPC call */
- RM_FUNC_GET_PARTITION = 5, /*!< Index for rm_get_partition() RPC call */
- RM_FUNC_SET_PARENT = 6, /*!< Index for rm_set_parent() RPC call */
- RM_FUNC_MOVE_ALL = 7, /*!< Index for rm_move_all() RPC call */
- RM_FUNC_ASSIGN_RESOURCE = 8, /*!< Index for rm_assign_resource() RPC call */
- RM_FUNC_SET_RESOURCE_MOVABLE = 9, /*!< Index for rm_set_resource_movable() RPC call */
- RM_FUNC_SET_SUBSYS_RSRC_MOVABLE = 28, /*!< Index for rm_set_subsys_rsrc_movable() RPC call */
- RM_FUNC_SET_MASTER_ATTRIBUTES = 10, /*!< Index for rm_set_master_attributes() RPC call */
- RM_FUNC_SET_MASTER_SID = 11, /*!< Index for rm_set_master_sid() RPC call */
- RM_FUNC_SET_PERIPHERAL_PERMISSIONS = 12, /*!< Index for rm_set_peripheral_permissions() RPC call */
- RM_FUNC_IS_RESOURCE_OWNED = 13, /*!< Index for rm_is_resource_owned() RPC call */
- RM_FUNC_IS_RESOURCE_MASTER = 14, /*!< Index for rm_is_resource_master() RPC call */
- RM_FUNC_IS_RESOURCE_PERIPHERAL = 15, /*!< Index for rm_is_resource_peripheral() RPC call */
- RM_FUNC_GET_RESOURCE_INFO = 16, /*!< Index for rm_get_resource_info() RPC call */
- RM_FUNC_MEMREG_ALLOC = 17, /*!< Index for rm_memreg_alloc() RPC call */
- RM_FUNC_MEMREG_SPLIT = 29, /*!< Index for rm_memreg_split() RPC call */
- RM_FUNC_MEMREG_FREE = 18, /*!< Index for rm_memreg_free() RPC call */
- RM_FUNC_FIND_MEMREG = 30, /*!< Index for rm_find_memreg() RPC call */
- RM_FUNC_ASSIGN_MEMREG = 19, /*!< Index for rm_assign_memreg() RPC call */
- RM_FUNC_SET_MEMREG_PERMISSIONS = 20, /*!< Index for rm_set_memreg_permissions() RPC call */
- RM_FUNC_IS_MEMREG_OWNED = 21, /*!< Index for rm_is_memreg_owned() RPC call */
- RM_FUNC_GET_MEMREG_INFO = 22, /*!< Index for rm_get_memreg_info() RPC call */
- RM_FUNC_ASSIGN_PAD = 23, /*!< Index for rm_assign_pad() RPC call */
- RM_FUNC_SET_PAD_MOVABLE = 24, /*!< Index for rm_set_pad_movable() RPC call */
- RM_FUNC_IS_PAD_OWNED = 25, /*!< Index for rm_is_pad_owned() RPC call */
- RM_FUNC_DUMP = 27, /*!< Index for rm_dump() RPC call */
-} rm_func_t;
+/*@{*/
+#define RM_FUNC_UNKNOWN 0 /* Unknown function */
+#define RM_FUNC_PARTITION_ALLOC 1U /* Index for rm_partition_alloc() RPC call */
+#define RM_FUNC_SET_CONFIDENTIAL 31U /* Index for rm_set_confidential() RPC call */
+#define RM_FUNC_PARTITION_FREE 2U /* Index for rm_partition_free() RPC call */
+#define RM_FUNC_GET_DID 26U /* Index for rm_get_did() RPC call */
+#define RM_FUNC_PARTITION_STATIC 3U /* Index for rm_partition_static() RPC call */
+#define RM_FUNC_PARTITION_LOCK 4U /* Index for rm_partition_lock() RPC call */
+#define RM_FUNC_GET_PARTITION 5U /* Index for rm_get_partition() RPC call */
+#define RM_FUNC_SET_PARENT 6U /* Index for rm_set_parent() RPC call */
+#define RM_FUNC_MOVE_ALL 7U /* Index for rm_move_all() RPC call */
+#define RM_FUNC_ASSIGN_RESOURCE 8U /* Index for rm_assign_resource() RPC call */
+#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /* Index for rm_set_resource_movable() RPC call */
+#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /* Index for rm_set_subsys_rsrc_movable() RPC call */
+#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /* Index for rm_set_master_attributes() RPC call */
+#define RM_FUNC_SET_MASTER_SID 11U /* Index for rm_set_master_sid() RPC call */
+#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /* Index for rm_set_peripheral_permissions() RPC call */
+#define RM_FUNC_IS_RESOURCE_OWNED 13U /* Index for rm_is_resource_owned() RPC call */
+#define RM_FUNC_IS_RESOURCE_MASTER 14U /* Index for rm_is_resource_master() RPC call */
+#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /* Index for rm_is_resource_peripheral() RPC call */
+#define RM_FUNC_GET_RESOURCE_INFO 16U /* Index for rm_get_resource_info() RPC call */
+#define RM_FUNC_MEMREG_ALLOC 17U /* Index for rm_memreg_alloc() RPC call */
+#define RM_FUNC_MEMREG_SPLIT 29U /* Index for rm_memreg_split() RPC call */
+#define RM_FUNC_MEMREG_FREE 18U /* Index for rm_memreg_free() RPC call */
+#define RM_FUNC_FIND_MEMREG 30U /* Index for rm_find_memreg() RPC call */
+#define RM_FUNC_ASSIGN_MEMREG 19U /* Index for rm_assign_memreg() RPC call */
+#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /* Index for rm_set_memreg_permissions() RPC call */
+#define RM_FUNC_IS_MEMREG_OWNED 21U /* Index for rm_is_memreg_owned() RPC call */
+#define RM_FUNC_GET_MEMREG_INFO 22U /* Index for rm_get_memreg_info() RPC call */
+#define RM_FUNC_ASSIGN_PAD 23U /* Index for rm_assign_pad() RPC call */
+#define RM_FUNC_SET_PAD_MOVABLE 24U /* Index for rm_set_pad_movable() RPC call */
+#define RM_FUNC_IS_PAD_OWNED 25U /* Index for rm_is_pad_owned() RPC call */
+#define RM_FUNC_DUMP 27U /* Index for rm_dump() RPC call */
+/*@}*/
+
+/* Types */
/* Functions */
@@ -78,6 +77,6 @@ void rm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
*/
void rm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-#endif /* _SC_RM_RPC_H */
+#endif /* SC_RM_RPC_H */
/**@}*/
diff --git a/plat/imx/common/sci/svc/timer/rpc.h b/plat/imx/common/sci/svc/timer/rpc.h
index eeb41a49..1f99d823 100644
--- a/plat/imx/common/sci/svc/timer/rpc.h
+++ b/plat/imx/common/sci/svc/timer/rpc.h
@@ -1,31 +1,8 @@
/*
- * Copyright 2017 NXP
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of NXP nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
/*!
@@ -35,35 +12,36 @@
* @{
*/
-#ifndef _SC_TIMER_RPC_H
-#define _SC_TIMER_RPC_H
+#ifndef SC_TIMER_RPC_H
+#define SC_TIMER_RPC_H
/* Includes */
/* Defines */
-/* Types */
-
/*!
- * This type is used to indicate RPC TIMER function calls.
+ * @name Defines for RPC TIMER function calls
*/
-typedef enum timer_func_e
-{
- TIMER_FUNC_UNKNOWN = 0, /*!< Unknown function */
- TIMER_FUNC_SET_WDOG_TIMEOUT = 1, /*!< Index for timer_set_wdog_timeout() RPC call */
- TIMER_FUNC_SET_WDOG_PRE_TIMEOUT = 12, /*!< Index for timer_set_wdog_pre_timeout() RPC call */
- TIMER_FUNC_START_WDOG = 2, /*!< Index for timer_start_wdog() RPC call */
- TIMER_FUNC_STOP_WDOG = 3, /*!< Index for timer_stop_wdog() RPC call */
- TIMER_FUNC_PING_WDOG = 4, /*!< Index for timer_ping_wdog() RPC call */
- TIMER_FUNC_GET_WDOG_STATUS = 5, /*!< Index for timer_get_wdog_status() RPC call */
- TIMER_FUNC_PT_GET_WDOG_STATUS = 13, /*!< Index for timer_pt_get_wdog_status() RPC call */
- TIMER_FUNC_SET_WDOG_ACTION = 10, /*!< Index for timer_set_wdog_action() RPC call */
- TIMER_FUNC_SET_RTC_TIME = 6, /*!< Index for timer_set_rtc_time() RPC call */
- TIMER_FUNC_GET_RTC_TIME = 7, /*!< Index for timer_get_rtc_time() RPC call */
- TIMER_FUNC_GET_RTC_SEC1970 = 9, /*!< Index for timer_get_rtc_sec1970() RPC call */
- TIMER_FUNC_SET_RTC_ALARM = 8, /*!< Index for timer_set_rtc_alarm() RPC call */
- TIMER_FUNC_SET_RTC_CALB = 11, /*!< Index for timer_set_rtc_calb() RPC call */
-} timer_func_t;
+/*@{*/
+#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
+#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for timer_set_wdog_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_START_WDOG 2U /* Index for timer_start_wdog() RPC call */
+#define TIMER_FUNC_STOP_WDOG 3U /* Index for timer_stop_wdog() RPC call */
+#define TIMER_FUNC_PING_WDOG 4U /* Index for timer_ping_wdog() RPC call */
+#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for timer_get_wdog_status() RPC call */
+#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for timer_pt_get_wdog_status() RPC call */
+#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for timer_set_wdog_action() RPC call */
+#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for timer_set_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for timer_get_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for timer_get_rtc_sec1970() RPC call */
+#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for timer_set_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for timer_set_rtc_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for timer_cancel_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for timer_set_rtc_calb() RPC call */
+/*@}*/
+
+/* Types */
/* Functions */
@@ -83,6 +61,6 @@ void timer_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
*/
void timer_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-#endif /* _SC_TIMER_RPC_H */
+#endif /* SC_TIMER_RPC_H */
/**@}*/
diff --git a/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c b/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c
index 22494030..6ce14843 100644
--- a/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c
@@ -1,31 +1,8 @@
/*
- * Copyright 2017 NXP
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of NXP nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
*/
/*!
@@ -51,19 +28,18 @@
/* Local Functions */
-sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc,
- sc_timer_wdog_time_t timeout)
+sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_WDOG_TIMEOUT;
- RPC_U32(&msg, 0) = timeout;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_TIMEOUT;
+ RPC_U32(&msg, 0U) = (uint32_t)timeout;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -76,29 +52,29 @@ sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_WDOG_PRE_TIMEOUT;
- RPC_U32(&msg, 0) = pre_timeout;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_PRE_TIMEOUT;
+ RPC_U32(&msg, 0U) = (uint32_t)pre_timeout;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
-sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, bool lock)
+sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_START_WDOG;
- RPC_U8(&msg, 0) = lock;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_START_WDOG;
+ RPC_U8(&msg, 0U) = (uint8_t)lock;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -110,11 +86,11 @@ sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_STOP_WDOG;
- RPC_SIZE(&msg) = 1;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_STOP_WDOG;
+ RPC_SIZE(&msg) = 1U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -126,61 +102,76 @@ sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_PING_WDOG;
- RPC_SIZE(&msg) = 1;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_PING_WDOG;
+ RPC_SIZE(&msg) = 1U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
- sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout,
+ sc_timer_wdog_time_t *timeout,
+ sc_timer_wdog_time_t *max_timeout,
sc_timer_wdog_time_t *remaining_time)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_GET_WDOG_STATUS;
- RPC_SIZE(&msg) = 1;
-
- sc_call_rpc(ipc, &msg, false);
-
- if (timeout != NULL)
- *timeout = RPC_U32(&msg, 0);
- if (max_timeout != NULL)
- *max_timeout = RPC_U32(&msg, 4);
- if (remaining_time != NULL)
- *remaining_time = RPC_U32(&msg, 8);
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_WDOG_STATUS;
+ RPC_SIZE(&msg) = 1U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ if (timeout != NULL) {
+ *timeout = RPC_U32(&msg, 0U);
+ }
+
+ if (max_timeout != NULL) {
+ *max_timeout = RPC_U32(&msg, 4U);
+ }
+
+ if (remaining_time != NULL) {
+ *remaining_time = RPC_U32(&msg, 8U);
+ }
+
result = RPC_R8(&msg);
return (sc_err_t)result;
}
-sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, bool *enb,
- sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time)
+sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt,
+ sc_bool_t *enb,
+ sc_timer_wdog_time_t *timeout,
+ sc_timer_wdog_time_t *remaining_time)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_PT_GET_WDOG_STATUS;
- RPC_U8(&msg, 0) = pt;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_PT_GET_WDOG_STATUS;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ if (timeout != NULL) {
+ *timeout = RPC_U32(&msg, 0U);
+ }
- sc_call_rpc(ipc, &msg, false);
+ if (remaining_time != NULL) {
+ *remaining_time = RPC_U32(&msg, 4U);
+ }
- if (timeout != NULL)
- *timeout = RPC_U32(&msg, 0);
- if (remaining_time != NULL)
- *remaining_time = RPC_U32(&msg, 4);
result = RPC_R8(&msg);
- if (enb != NULL)
- *enb = RPC_U8(&msg, 8);
+ if (enb != NULL) {
+ *enb = RPC_U8(&msg, 8U);
+ }
+
return (sc_err_t)result;
}
@@ -191,67 +182,81 @@ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_WDOG_ACTION;
- RPC_U8(&msg, 0) = pt;
- RPC_U8(&msg, 1) = action;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_ACTION;
+ RPC_U8(&msg, 0U) = (uint8_t)pt;
+ RPC_U8(&msg, 1U) = (uint8_t)action;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
- uint8_t day, uint8_t hour, uint8_t min, uint8_t sec)
+ uint8_t day, uint8_t hour, uint8_t min,
+ uint8_t sec)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_TIME;
- RPC_U16(&msg, 0) = year;
- RPC_U8(&msg, 2) = mon;
- RPC_U8(&msg, 3) = day;
- RPC_U8(&msg, 4) = hour;
- RPC_U8(&msg, 5) = min;
- RPC_U8(&msg, 6) = sec;
- RPC_SIZE(&msg) = 3;
-
- sc_call_rpc(ipc, &msg, false);
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_TIME;
+ RPC_U16(&msg, 0U) = (uint16_t)year;
+ RPC_U8(&msg, 2U) = (uint8_t)mon;
+ RPC_U8(&msg, 3U) = (uint8_t)day;
+ RPC_U8(&msg, 4U) = (uint8_t)hour;
+ RPC_U8(&msg, 5U) = (uint8_t)min;
+ RPC_U8(&msg, 6U) = (uint8_t)sec;
+ RPC_SIZE(&msg) = 3U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
- uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec)
+ uint8_t *day, uint8_t *hour, uint8_t *min,
+ uint8_t *sec)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_GET_RTC_TIME;
- RPC_SIZE(&msg) = 1;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_RTC_TIME;
+ RPC_SIZE(&msg) = 1U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- sc_call_rpc(ipc, &msg, false);
+ if (year != NULL) {
+ *year = RPC_U16(&msg, 0U);
+ }
- if (year != NULL)
- *year = RPC_U16(&msg, 0);
result = RPC_R8(&msg);
- if (mon != NULL)
- *mon = RPC_U8(&msg, 2);
- if (day != NULL)
- *day = RPC_U8(&msg, 3);
- if (hour != NULL)
- *hour = RPC_U8(&msg, 4);
- if (min != NULL)
- *min = RPC_U8(&msg, 5);
- if (sec != NULL)
- *sec = RPC_U8(&msg, 6);
+ if (mon != NULL) {
+ *mon = RPC_U8(&msg, 2U);
+ }
+
+ if (day != NULL) {
+ *day = RPC_U8(&msg, 3U);
+ }
+
+ if (hour != NULL) {
+ *hour = RPC_U8(&msg, 4U);
+ }
+
+ if (min != NULL) {
+ *min = RPC_U8(&msg, 5U);
+ }
+
+ if (sec != NULL) {
+ *sec = RPC_U8(&msg, 6U);
+ }
+
return (sc_err_t)result;
}
@@ -261,36 +266,72 @@ sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_GET_RTC_SEC1970;
- RPC_SIZE(&msg) = 1;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_RTC_SEC1970;
+ RPC_SIZE(&msg) = 1U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
- sc_call_rpc(ipc, &msg, false);
+ if (sec != NULL) {
+ *sec = RPC_U32(&msg, 0U);
+ }
- if (sec != NULL)
- *sec = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
- uint8_t day, uint8_t hour, uint8_t min, uint8_t sec)
+ uint8_t day, uint8_t hour, uint8_t min,
+ uint8_t sec)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_ALARM;
+ RPC_U16(&msg, 0U) = (uint16_t)year;
+ RPC_U8(&msg, 2U) = (uint8_t)mon;
+ RPC_U8(&msg, 3U) = (uint8_t)day;
+ RPC_U8(&msg, 4U) = (uint8_t)hour;
+ RPC_U8(&msg, 5U) = (uint8_t)min;
+ RPC_U8(&msg, 6U) = (uint8_t)sec;
+ RPC_SIZE(&msg) = 3U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
+}
+
+sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_ALARM;
- RPC_U16(&msg, 0) = year;
- RPC_U8(&msg, 2) = mon;
- RPC_U8(&msg, 3) = day;
- RPC_U8(&msg, 4) = hour;
- RPC_U8(&msg, 5) = min;
- RPC_U8(&msg, 6) = sec;
- RPC_SIZE(&msg) = 3;
-
- sc_call_rpc(ipc, &msg, false);
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_PERIODIC_ALARM;
+ RPC_U32(&msg, 0U) = (uint32_t)sec;
+ RPC_SIZE(&msg) = 2U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t)result;
+}
+
+sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_CANCEL_RTC_ALARM;
+ RPC_SIZE(&msg) = 1U;
+
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@@ -302,14 +343,15 @@ sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_CALB;
- RPC_I8(&msg, 0) = count;
- RPC_SIZE(&msg) = 2;
+ RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
+ RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_CALB;
+ RPC_I8(&msg, 0U) = (int8_t) count;
+ RPC_SIZE(&msg) = 2U;
- sc_call_rpc(ipc, &msg, false);
+ sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
+
/**@}*/
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-18 18:55:34 +0000