diff options
| author | Teo Hall <teo.hall@nxp.com> | 2018-05-03 14:29:41 -0500 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:33:03 +0300 |
| commit | 3fe838d094437933a111ca1fab90501fb95c284f (patch) | |
| tree | 8655a7303b7109c98d13f6d954f52080cd33a245 | |
| parent | ca803a791056da5a2acdf7118bbacf0f119e6433 (diff) | |
plat: imx8qxp: Use MU0 for SCu communication
Use MU0 to comply with boot image usage of MU0
Also power on and pass MU1 for OS/Hypervisor
Signed-off-by: Teo Hall <teo.hall@nxp.com>
| -rw-r--r-- | plat/imx/common/include/sci/sci.h | 2 | ||||
| -rw-r--r-- | plat/imx/imx8qxp/imx8qxp_bl31_setup.c | 5 | ||||
| -rw-r--r-- | plat/imx/imx8qxp/include/sec_rsrc.h | 2 |
3 files changed, 7 insertions, 2 deletions
diff --git a/plat/imx/common/include/sci/sci.h b/plat/imx/common/include/sci/sci.h index ef50a2b5..1c33eea0 100644 --- a/plat/imx/common/include/sci/sci.h +++ b/plat/imx/common/include/sci/sci.h @@ -54,6 +54,6 @@ #define SC_IPC_AP_CH3 (MU_BASE_ADDR(3)) #define SC_IPC_AP_CH4 (MU_BASE_ADDR(4)) -#define SC_IPC_CH SC_IPC_AP_CH1 +#define SC_IPC_CH SC_IPC_AP_CH0 #endif /* _SC_SCI_H */ diff --git a/plat/imx/imx8qxp/imx8qxp_bl31_setup.c b/plat/imx/imx8qxp/imx8qxp_bl31_setup.c index d4c4ddcd..bece635b 100644 --- a/plat/imx/imx8qxp/imx8qxp_bl31_setup.c +++ b/plat/imx/imx8qxp/imx8qxp_bl31_setup.c @@ -310,6 +310,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, IMX_CONSOLE_BAUDRATE); #endif + /* Turn on MU1 for non-secure OS/Hypervisor + * + */ + sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON); + /* create new partition for non-secure OS/Hypervisor * * uses global structs defined in sec_rsrc.h diff --git a/plat/imx/imx8qxp/include/sec_rsrc.h b/plat/imx/imx8qxp/include/sec_rsrc.h index aba3ce90..2a25bf06 100644 --- a/plat/imx/imx8qxp/include/sec_rsrc.h +++ b/plat/imx/imx8qxp/include/sec_rsrc.h @@ -3,7 +3,7 @@ /* resources that are going to stay in secure partition */ sc_rsrc_t secure_rsrcs[] = { - SC_R_MU_1A, + SC_R_MU_0A, SC_R_A35, SC_R_A35_0, SC_R_A35_1, |