diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-06-05 10:58:39 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:33:03 +0300 |
| commit | 21fa6238d98517739e9e65cd6431a1e5a0880a52 (patch) | |
| tree | f3302746c17d447a7c54695ade5d790d49f69594 | |
| parent | 44e209cb87f078abc78839c5e138aae5122ddd78 (diff) | |
MLK-18502-01 plat: imx8mm: fix audio fifo underrun issue
A53 WAIT mode is specific for OS cpuilde. The MASTER1 & MASTER2
mapping in A53 domain should be clear, otherwise the 'noc2supermix'
and 'supermix2noc' ADB400 async port will be power down when A53
enters WAIT mode.If the ADB400 is power down in WAIT mode, all the bus
request from supermix to noc wrapper will be blocked.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
| -rw-r--r-- | plat/imx/imx8mm/gpc.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c index 319e1054..bfa0c5c1 100644 --- a/plat/imx/imx8mm/gpc.c +++ b/plat/imx/imx8mm/gpc.c @@ -19,7 +19,6 @@ #include <fsl_sip.h> #include <soc.h> -#define GPC_MST_CPU_MAPPING 0x18 #define GPC_PGC_ACK_SEL_A53 0x24 #define GPC_IMR1_CORE0_A53 0x30 #define GPC_IMR1_CORE1_A53 0x40 @@ -35,6 +34,7 @@ #define PGC_PCR 0 +/* BSC */ #define LPCR_A53_BSC 0x0 #define LPCR_A53_BSC2 0x108 #define LPCR_M4 0x8 @@ -50,8 +50,9 @@ #define A53_LPM_STOP 0xa #define A53_CLK_ON_LPM (1 << 14) -#define SRC_GPR1_OFFSET 0x74 +#define MST_CPU_MAPPING 0x18 +#define SRC_GPR1_OFFSET 0x74 /* AD */ #define LPCR_A53_AD 0x4 @@ -612,10 +613,13 @@ void imx_gpc_init(void) val |= 0x30c00000; /* clear the MASTER0 LPM handshake */ val &= ~(1 << 6); - val &= ~(1 << 7); - val &= ~(1 << 8); mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); + /* clear MASTER1&MASTER2 mapping in CPU0(A53) */ + val = mmio_read_32(IMX_GPC_BASE + MST_CPU_MAPPING); + val &= ~(0x3 << 1); + mmio_write_32(IMX_GPC_BASE + MST_CPU_MAPPING, val); + /* mask M4 DSM trigger if M4 is NOT enabled */ val = mmio_read_32(IMX_GPC_BASE + LPCR_M4); val |= 1 << 31; |