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<a href="#define-members">Macros</a> </div>
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<div class="title">SPI Slave Select Mode</div> </div>
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<p>Specifies SPI slave select mode.
<a href="#details">More...</a></p>
<table class="memberdecls">
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Macros</h2></td></tr>
<tr class="memitem:gae19343adc7bd71408b51733171f99dc7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#gae19343adc7bd71408b51733171f99dc7">ARM_SPI_SS_MASTER_UNUSED</a>   (0UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="memdesc:gae19343adc7bd71408b51733171f99dc7"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Master: Not used (default) <a href="#gae19343adc7bd71408b51733171f99dc7"></a><br/></td></tr>
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<tr class="memitem:gab5e319aa3f9d4d8c9ed92f0fe865f624"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#gab5e319aa3f9d4d8c9ed92f0fe865f624">ARM_SPI_SS_MASTER_SW</a>   (1UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="memdesc:gab5e319aa3f9d4d8c9ed92f0fe865f624"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Master: Software controlled. <a href="#gab5e319aa3f9d4d8c9ed92f0fe865f624"></a><br/></td></tr>
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<tr class="memitem:ga07762709a40dc90aca85553f500c8761"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#ga07762709a40dc90aca85553f500c8761">ARM_SPI_SS_MASTER_HW_OUTPUT</a>   (2UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="memdesc:ga07762709a40dc90aca85553f500c8761"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Master: Hardware controlled Output. <a href="#ga07762709a40dc90aca85553f500c8761"></a><br/></td></tr>
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<tr class="memitem:ga8561bd0cc25ab2bb02b138c1c6a586cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#ga8561bd0cc25ab2bb02b138c1c6a586cd">ARM_SPI_SS_MASTER_HW_INPUT</a>   (3UL << ARM_SPI_SS_MASTER_MODE_Pos)</td></tr>
<tr class="memdesc:ga8561bd0cc25ab2bb02b138c1c6a586cd"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Master: Hardware monitored Input. <a href="#ga8561bd0cc25ab2bb02b138c1c6a586cd"></a><br/></td></tr>
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<tr class="memitem:ga2bd0d1f3ade2dc0cc48cc0593336ad70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#ga2bd0d1f3ade2dc0cc48cc0593336ad70">ARM_SPI_SS_SLAVE_HW</a>   (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)</td></tr>
<tr class="memdesc:ga2bd0d1f3ade2dc0cc48cc0593336ad70"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Slave: Hardware monitored (default) <a href="#ga2bd0d1f3ade2dc0cc48cc0593336ad70"></a><br/></td></tr>
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<tr class="memitem:gad371f6ba0d12a57bdcc3217c351abfb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__spi__slave__select__mode__ctrls.html#gad371f6ba0d12a57bdcc3217c351abfb0">ARM_SPI_SS_SLAVE_SW</a>   (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)</td></tr>
<tr class="memdesc:gad371f6ba0d12a57bdcc3217c351abfb0"><td class="mdescLeft"> </td><td class="mdescRight">SPI Slave Select when Slave: Software controlled. <a href="#gad371f6ba0d12a57bdcc3217c351abfb0"></a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>Specifies SPI slave select mode. </p>
<p><b>SPI</b> <b>Slave</b> <b>Select</b> <b>Mode</b> configures the behavior of the <b>Slave</b> <b>Select</b> <b></b>(SS) signal. The configuration is separate for <b>Master</b> (ARM_SPI_SS_MASTER_*) and for <b>Slave</b> (<a class="el" href="group__spi__slave__select__mode__ctrls.html#ga2bd0d1f3ade2dc0cc48cc0593336ad70">ARM_SPI_SS_SLAVE_HW</a>, <a class="el" href="group__spi__slave__select__mode__ctrls.html#gad371f6ba0d12a57bdcc3217c351abfb0">ARM_SPI_SS_SLAVE_SW</a>). The active configuration depends on the current state (Master/Slave). </p>
<h2 class="groupheader">Macro Definition Documentation</h2>
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<p>SPI Slave Select when Master: Not used (default) </p>
<p>An SPI master does not drive or monitor the SS line. For example, when connecting to a single slave, the SS line can be connected to a fixed low level. </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a" title="Control SPI Interface.">ARM_SPI_Control</a> </dd></dl>
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<td class="memname">#define ARM_SPI_SS_MASTER_SW   (1UL << ARM_SPI_SS_MASTER_MODE_Pos)</td>
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<p>SPI Slave Select when Master: Software controlled. </p>
<p>SS is configured as an output and controlled via <a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a">ARM_SPI_Control</a> (<a class="el" href="group__spi__misc__ctrls.html#ga5776272b82decff92da003568540c92f">ARM_SPI_CONTROL_SS</a>). By default, it is not active (high). It is activated (low) by <a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a">ARM_SPI_Control</a> (<a class="el" href="group__spi__misc__ctrls.html#ga5776272b82decff92da003568540c92f">ARM_SPI_CONTROL_SS</a>, <a class="el" href="_driver___s_p_i_8h.html#a3f465cdbd1238ddd74f78e14457076c4">ARM_SPI_SS_ACTIVE</a>) and deactivated by <a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a">ARM_SPI_Control</a> (<a class="el" href="group__spi__misc__ctrls.html#ga5776272b82decff92da003568540c92f">ARM_SPI_CONTROL_SS</a>, <a class="el" href="_driver___s_p_i_8h.html#a335b448e07422e9c25616a693ec581cc">ARM_SPI_SS_INACTIVE</a>). It is not affected by transfer/send/receive functions. </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a" title="Control SPI Interface.">ARM_SPI_Control</a> </dd></dl>
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<td class="memname">#define ARM_SPI_SS_MASTER_HW_OUTPUT   (2UL << ARM_SPI_SS_MASTER_MODE_Pos)</td>
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<p>SPI Slave Select when Master: Hardware controlled Output. </p>
<p>Here, SS is configured as an output. It will be automatically activated/deactivated for the transfers by hardware (not controlled by <a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a">ARM_SPI_Control</a> (<a class="el" href="group__spi__misc__ctrls.html#ga5776272b82decff92da003568540c92f">ARM_SPI_CONTROL_SS</a>)). The activation/deactivation of the line is completely hardware dependent. Typically, the hardware will activate it before starting a transfer and deactivate it after a transfer completes. Some hardware will leave it activated as long as the SPI stays master. Due to different hardware behavior, this mode is typically not useful because certain devices require that the SS signal is strictly defined with regards to transfers. </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a" title="Control SPI Interface.">ARM_SPI_Control</a> </dd></dl>
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<td class="memname">#define ARM_SPI_SS_MASTER_HW_INPUT   (3UL << ARM_SPI_SS_MASTER_MODE_Pos)</td>
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<p>SPI Slave Select when Master: Hardware monitored Input. </p>
<p>This is normally used in a multi-master configuration, where a master does not drive the SS line when driving the bus but only monitors it. When another master activates this line, the active master backs off. This is called <b>mode</b> <b>fault</b>. SS is configured as input and the hardware only monitors it. When it is externally deactivated while being the master, it presents a mode fault and the SPI switches to <b>inactive</b> mode. </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a" title="Control SPI Interface.">ARM_SPI_Control</a> </dd></dl>
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<td class="memname">#define ARM_SPI_SS_SLAVE_HW   (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)</td>
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<p>SPI Slave Select when Slave: Hardware monitored (default) </p>
<p>Hardware monitors the SS line and accepts transfers only when SS line is activate. Transfers while SS is not active are ignored. </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a" title="Control SPI Interface.">ARM_SPI_Control</a> </dd></dl>
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<td class="memname">#define ARM_SPI_SS_SLAVE_SW   (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)</td>
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<p>SPI Slave Select when Slave: Software controlled. </p>
<p>Used only when SS line is not used. For example, when a single master and slave are connected in a system, the SS line is not needed (reduces the number of lines and pins used). Slave responses are controlled by software (by default, it is not responding). Software enables/disables transfers by calling <a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a">ARM_SPI_Control</a> (<a class="el" href="group__spi__misc__ctrls.html#ga5776272b82decff92da003568540c92f">ARM_SPI_CONTROL_SS</a>, <a class="el" href="_driver___s_p_i_8h.html#a3f465cdbd1238ddd74f78e14457076c4">ARM_SPI_SS_ACTIVE</a> / <a class="el" href="_driver___s_p_i_8h.html#a335b448e07422e9c25616a693ec581cc">ARM_SPI_SS_INACTIVE</a>). </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="group__spi__interface__gr.html#gad18d229992598d6677bec250015e5d1a" title="Control SPI Interface.">ARM_SPI_Control</a> </dd></dl>
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