/* * Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. * Copyright (c) 2016, Toradex AG * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of Freescale Semiconductor, Inc. nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 16 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ CPU2CPU_INT0_IRQ = 0, CPU2CPU_INT1_IRQ = 1, CPU2CPU_INT2_IRQ = 2, CPU2CPU_INT3_IRQ = 3, DIRECTED0_SEMA4_IRQ = 4, DIRECTED1_MCM_IRQ = 5, DIRECTED2_IRQ = 6, DIRECTED3_IRQ = 7, DMA0_IRQ = 8, DMA0_ERROR_IRQ = 9, DMA1_IRQ = 10, DMA1_ERROR_IRQ = 11, RESERVED0_IRQ = 12, RESERVED1_IRQ = 13, MSCM_ECC0_IRQ = 14, MSCM_ECC1_IRQ = 15, CSU_ALARM_IRQ = 16, RESERVED2_IRQ = 17, MSCM_ACTZS_IRQ = 18, RESERVED3_IRQ = 19, WDOG_A5_IRQ = 20, WDOG_M4_IRQ = 21, WDOG_SNVS_IRQ = 22, CP1_BOOT_FAIL_IRQ = 23, QSPI0_IRQ = 24, QSPI1_IRQ = 25, DDRMC_IRQ = 26, SDHC0_IRQ = 27, SDHC1_IRQ = 28, RESERVED4_IRQ = 29, DCU0_IRQ = 30, DCU1_IRQ = 31, VIU_IRQ = 32, RESERVED5_IRQ = 33, RESERVED6_IRQ = 34, RLE_IRQ = 35, SEG_LCD_IRQ = 36, RESERVED7_IRQ = 37, RESERVED8_IRQ = 38, PIT_IRQ = 39, LPTIMER0_IRQ = 40, RESERVED9_IRQ = 41, FLEXTIMER0_IRQ = 42, FLEXTIMER1_IRQ = 43, FLEXTIMER2_IRQ = 44, FLEXTIMER3_IRQ = 45, RESERVED10_IRQ = 46, RESERVED11_IRQ = 47, RESERVED12_IRQ = 48, RESERVED13_IRQ = 49, USBPHY0_IRQ = 50, USBPHY1_IRQ = 51, RESERVED14_IRQ = 52, ADC0_IRQ = 53, ADC1_IRQ = 54, DAC0_IRQ = 55, DAC1_IRQ = 56, RESERVED15_IRQ = 57, FLEXCAN0_IRQ = 58, FLEXCAN1_IRQ = 59, RESERVED16_IRQ = 60, UART0_IRQ = 61, UART1_IRQ = 62, UART2_IRQ = 63, UART3_IRQ = 64, UART4_IRQ = 65, UART5_IRQ = 66, SPI0_IRQ = 67, SPI1_IRQ = 68, SPI2_IRQ = 69, SPI3_IRQ = 70, I2C0_IRQ = 71, I2C1_IRQ = 72, I2C2_IRQ = 73, I2C3_IRQ = 74, USBC0_IRQ = 75, USBC1_IRQ = 76, RESERVED17_IRQ = 77, ENET0_IRQ = 78, ENET1_IRQ = 79, ENET0_1588_IRQ = 80, ENET1_1588_IRQ = 81, ENET_SWITCH_IRQ = 82, NFC_IRQ = 83, SAI0_IRQ = 84, SAI1_IRQ = 85, SAI2_IRQ = 86, SAI3_IRQ = 87, ESAI_BIFIFO_IRQ = 88, SPDIF_IRQ = 89, ASRC_IRQ = 90, VREG_IRQ = 91, WKPU0_IRQ = 92, RESERVED18_IRQ = 93, CCM_FXOSC_IRQ = 94, CCM_IRQ = 95, SRC_IRQ = 96, PDB_IRQ = 97, EWM_IRQ = 98, RESERVED19_IRQ = 99, RESERVED20_IRQ = 100, RESERVED21_IRQ = 101, RESERVED22_IRQ = 102, RESERVED23_IRQ = 103, RESERVED24_IRQ = 104, RESERVED25_IRQ = 105, RESERVED26_IRQ = 106, GPIO0_IRQ = 107, GPIO1_IRQ = 108, GPIO2_IRQ = 109, GPIO3_IRQ = 110, GPIO4_IRQ = 111, } IRQn_Type; /* ---------------------------------------------------------------------------- -- Cortex M4 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration * @{ */ #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ /* Memory map for all busses */ #define PERIPH_BASE (0x40000000U) #define PERIPH_BASE_AIPS0 (PERIPH_BASE + 0x00000) #define PERIPH_BASE_AIPS1 (PERIPH_BASE + 0x80000) /* Pheripheral addresses */ /* AIPS0 */ #define MSCM_BASE (PERIPH_BASE_AIPS0 + 0x01000) #define SEMA4_BASE (PERIPH_BASE_AIPS0 + 0x1D000) #define UART0_BASE (PERIPH_BASE_AIPS0 + 0x27000) #define UART1_BASE (PERIPH_BASE_AIPS0 + 0x28000) #define UART2_BASE (PERIPH_BASE_AIPS0 + 0x29000) #define UART3_BASE (PERIPH_BASE_AIPS0 + 0x2A000) #define SPI0_BASE (PERIPH_BASE_AIPS0 + 0x2C000) #define SPI1_BASE (PERIPH_BASE_AIPS0 + 0x2D000) #define IOMUXC_BASE (PERIPH_BASE_AIPS0 + 0x48000) #define PORTA_MUX_BASE (PERIPH_BASE_AIPS0 + 0x49000) #define PORTB_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4A000) #define PORTC_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4B000) #define PORTD_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4C000) #define PORTE_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4D000) #define ANADIG_BASE (PERIPH_BASE_AIPS0 + 0x50000) #define CCM_BASE (PERIPH_BASE_AIPS0 + 0x6B000) /* AIPS1 */ #define UART4_BASE (PERIPH_BASE_AIPS1 + 0x29000) #define UART5_BASE (PERIPH_BASE_AIPS1 + 0x2A000) #define GPIO_BASE (PERIPH_BASE + 0xff000) #define GPIO0_BASE (GPIO_BASE + 0x000) #define GPIO1_BASE (GPIO_BASE + 0x040) #define GPIO2_BASE (GPIO_BASE + 0x080) #define GPIO3_BASE (GPIO_BASE + 0x0C0) #define GPIO4_BASE (GPIO_BASE + 0x100) /* --- ANADIG registers ---------------------------------------------------- */ /** ANADIG - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[16]; __IO uint32_t ANADIG_PLL3_CTRL; uint8_t RESERVED_1[12]; __IO uint32_t ANADIG_PLL7_CTRL; uint8_t RESERVED_2[12]; __IO uint32_t ANADIG_PLL2_CTRL; uint8_t RESERVED_3[12]; __IO uint32_t ANADIG_PLL2_SS; uint8_t RESERVED_4[12]; __IO uint32_t ANADIG_PLL2_NUM; uint8_t RESERVED_5[12]; __IO uint32_t ANADIG_PLL2_DENOM; uint8_t RESERVED_6[12]; __IO uint32_t ANADIG_PLL4_CTRL; uint8_t RESERVED_7[12]; __IO uint32_t ANADIG_PLL4_NUM; uint8_t RESERVED_8[12]; __IO uint32_t ANADIG_PLL4_DENOM; uint8_t RESERVED_9[12]; __IO uint32_t ANADIG_PLL6_CTRL; uint8_t RESERVED_10[12]; __IO uint32_t ANADIG_PLL6_NUM; uint8_t RESERVED_12[12]; __IO uint32_t ANADIG_PLL6_DENOM; uint8_t RESERVED_13[28]; __IO uint32_t ANADIG_PLL5_CTRL; uint8_t RESERVED_14[12]; __IO uint32_t ANADIG_PLL3_PFD; uint8_t RESERVED_15[12]; __IO uint32_t ANADIG_PLL2_PFD; uint8_t RESERVED_16[12]; __IO uint32_t ANADIG_1P1; uint8_t RESERVED_17[12]; __IO uint32_t ANADIG_REGU_3P0; uint8_t RESERVED_18[12]; __IO uint32_t ANADIG_REGU_2P5; uint8_t RESERVED_19[28]; __IO uint32_t ANADIG_ANA_MISC0; uint8_t RESERVED_20[12]; __IO uint32_t ANADIG_ANA_MISC1; uint8_t RESERVED_21[252]; __IO uint32_t ANADIG_DIGPROG; uint8_t RESERVED_22[12]; __IO uint32_t ANADIG_PLL1_CTRL; uint8_t RESERVED_23[12]; __IO uint32_t ANADIG_PLL1_SS; uint8_t RESERVED_24[12]; __IO uint32_t ANADIG_PLL1_NUM; uint8_t RESERVED_25[12]; __IO uint32_t ANADIG_PLL1_DENOM; uint8_t RESERVED_26[12]; __IO uint32_t ANADIG_PLL1_PFD; uint8_t RESERVED_27[12]; __IO uint32_t ANADIG_PLL_LOCK; } ANADIG_Type, *ANADIG_MemMapPtr; #define ANADIG_PLL3_CTRL_REG(base) ((base)->ANADIG_PLL3_CTRL) #define ANADIG_PLL7_CTRL_REG(base) ((base)->ANADIG_PLL7_CTRL) #define ANADIG_PLL2_CTRL_REG(base) ((base)->ANADIG_PLL2_CTRL) #define ANADIG_PLL2_SS_REG(base) ((base)->ANADIG_PLL2_SS) #define ANADIG_PLL2_NUM_REG(base) ((base)->ANADIG_PLL2_NUM) #define ANADIG_PLL2_DENOM_REG(base) ((base)->ANADIG_PLL2_DENOM) #define ANADIG_PLL4_CTRL_REG(base) ((base)->ANADIG_PLL4_CTRL) #define ANADIG_PLL4_NUM_REG(base) ((base)->ANADIG_PLL4_NUM) #define ANADIG_PLL4_DENOM_REG(base) ((base)->ANADIG_PLL4_DENOM) #define ANADIG_PLL6_CTRL_REG(base) ((base)->ANADIG_PLL6_CTRL) #define ANADIG_PLL6_NUM_REG(base) ((base)->ANADIG_PLL6_NUM) #define ANADIG_PLL6_DENOM_REG(base) ((base)->ANADIG_PLL6_DENOM) #define ANADIG_PLL5_CTRL_REG(base) ((base)->ANADIG_PLL5_CTRL) #define ANADIG_PLL3_PFD_REG(base) ((base)->ANADIG_PLL3_PFD) #define ANADIG_PLL2_PFD_REG(base) ((base)->ANADIG_PLL2_PFD) #define ANADIG_REGU_1P1_REG(base) ((base)->ANADIG_REGU_1P1) #define ANADIG_REGU_3P0_REG(base) ((base)->ANADIG_REGU_3P0) #define ANADIG_REGU_2P5_REG(base) ((base)->ANADIG_REGU_2P5) #define ANADIG_ANA_MISC0_REG(base) ((base)->ANADIG_ANA_MISC0) #define ANADIG_ANA_MISC1_REG(base) ((base)->ANADIG_ANA_MISC1) #define ANADIG_DIGPROG_REG(base) ((base)->ANADIG_DIGPROG) #define ANADIG_PLL1_CTRL_REG(base) ((base)->ANADIG_PLL1_CTRL) #define ANADIG_PLL1_SS_REG(base) ((base)->ANADIG_PLL1_SS) #define ANADIG_PLL1_NUM_REG(base) ((base)->ANADIG_PLL1_NUM) #define ANADIG_PLL1_DENOM_REG(base) ((base)->ANADIG_PLL1_DENOM) #define ANADIG_PLL1_PFD_REG(base) ((base)->ANADIG_PLL1_PFD) #define ANADIG_PLL_LOCK_REG(base) ((base)->ANADIG_PLL_LOCK) /* ANADIG - Peripheral instance base addresses */ /** Peripheral CCM_ANALOG base pointer */ #define ANADIG ((ANADIG_Type *)ANADIG_BASE) #define ANADIG_BASE_PTR (ANADIG) /** Array initializer of CCM_ANALOG peripheral base adresses */ #define ANADIG_BASE_ADDRS { ANADIG_BASE } /** Array initializer of CCM_ANALOG peripheral base pointers */ #define ANADIG_BASE_PTRS { ANADIG } /* ANADIG - Register instance definitions */ #define ANADIG_PLL3_CTRL ANADIG_PLL3_CTRL_REG(ANADIG_BASE_PTR) #define ANADIG_PLL7_CTRL ANADIG_PLL7_CTRL_REG(ANADIG_BASE_PTR) #define ANADIG_PLL2_CTRL ANADIG_PLL2_CTRL_REG(ANADIG_BASE_PTR) #define ANADIG_PLL2_SS ANADIG_PLL2_SS_REG(ANADIG_BASE_PTR) #define ANADIG_PLL2_NUM ANADIG_PLL2_NUM_REG(ANADIG_BASE_PTR) #define ANADIG_PLL2_DENOM ANADIG_PLL2_DENOM_REG(ANADIG_BASE_PTR) #define ANADIG_PLL4_CTRL ANADIG_PLL4_CTRL_REG(ANADIG_BASE_PTR) #define ANADIG_PLL4_NUM ANADIG_PLL4_NUM_REG(ANADIG_BASE_PTR) #define ANADIG_PLL4_DENOM ANADIG_PLL4_DENOM_REG(ANADIG_BASE_PTR) #define ANADIG_PLL6_CTRL ANADIG_PLL6_CTRL_REG(ANADIG_BASE_PTR) #define ANADIG_PLL6_NUM ANADIG_PLL6_NUM_REG(ANADIG_BASE_PTR)) #define ANADIG_PLL6_DENOM ANADIG_PLL6_DENOM_REG(ANADIG_BASE_PTR) #define ANADIG_PLL5_CTRL ANADIG_PLL5_CTRL_REG(ANADIG_BASE_PTR) #define ANADIG_PLL3_PFD ANADIG_PLL3_PFD_REG(ANADIG_BASE_PTR) #define ANADIG_PLL2_PFD ANADIG_PLL2_PFD_REG(ANADIG_BASE_PTR) #define ANADIG_REGU_1P1 ANADIG_REGU_1P1_REG(ANADIG_BASE_PTR) #define ANADIG__REGU_3P0 ANADIG__REGU_3P0_REG(ANADIG_BASE_PTR) #define ANADIG_REGU_2P5 ANADIG_REGU_2P5_REG(ANADIG_BASE_PTR) #define ANADIG_ANA_MISC0 ANADIG_ANA_MISC0_REG(ANADIG_BASE_PTR) #define ANADIG_ANA_MISC1 ANADIG_ANA_MISC1_REG(ANADIG_BASE_PTR) #define ANADIG_DIGPROG ANADIG_DIGPROG_REG(ANADIG_BASE_PTR) #define ANADIG_PLL1_CTRL ANADIG_PLL1_CTRL_REG(ANADIG_BASE_PTR) #define ANADIG_PLL1_SS ANADIG_PLL1_SS_REG(ANADIG_BASE_PTR) #define ANADIG_PLL1_NUM ANADIG_PLL1_NUM_REG(ANADIG_BASE_PTR) #define ANADIG_PLL1_DENO ANADIG_PLL1_DENOM_REG(ANADIG_BASE_PTR) #define ANADIG_PLL1_PFD ANADIG_PLL1_PFD_REG(ANADIG_BASE_PTR) #define ANADIG_PLL_LOCK ANADIG_PLL_LOCK_REG(ANADIG_BASE_PTR) /* --- ANADIG values -....-------------------------------------------------- */ /* ANADIG_PLL3_CTRL: PLL3 Control Register (480MHz PLL of USB0) */ #define ANADIG_PLL3_CTRL_LOCK (1 << 31) #define ANADIG_PLL3_CTRL_BYPASS (1 << 16) #define ANADIG_PLL3_CTRL_BYPASS_CLK_SRC (1 << 14) #define ANADIG_PLL3_CTRL_ENABLE (1 << 13) #define ANADIG_PLL3_CTRL_POWER (1 << 12) #define ANADIG_PLL3_CTRL_EN_USB_CLKS (1 << 6) #define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) /* ANADIG_PLL7_CTRL: PLL7 Control Register (480MHz PLL of USB1) */ #define ANADIG_PLL7_CTRL_LOCK (1 << 31) #define ANADIG_PLL7_CTRL_BYPASS (1 << 16) #define ANADIG_PLL7_CTRL_BYPASS_CLK_SRC (1 << 14) #define ANADIG_PLL7_CTRL_ENABLE (1 << 13) #define ANADIG_PLL7_CTRL_POWER (1 << 12) #define ANADIG_PLL7_CTRL_EN_USB_CLKS (1 << 6) #define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) /* ANADIG_PLL2_CTRL: PLL2 Control Register (528MHz PLL) */ #define ANADIG_PLL2_CTRL_LOCK (1 << 31) #define ANADIG_PLL2_CTRL_PFD_OFFSET_EN (1 << 18) #define ANADIG_PLL2_CTRL_DITHER_ENABLE (1 << 17) #define ANADIG_PLL2_CTRL_BYPASS (1 << 16) #define ANADIG_PLL2_CTRL_BYPASS_CLK_SRC (1 << 14) #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL2_CTRL_DIV_SELECT (1 << 1) /* ANADIG_PLL2_SS: PLL2 Spread Spectrum definition register */ #define ANADIG_PLL2_SS_STOP_MASK (0xffff << 16) #define ANADIG_PLL2_SS_ENABLE (1 << 15) #define ANADIG_PLL2_SS_STEP_MASK 0x8fff /* ANADIG_PLL2_NUM: PLL2 Numerator definition register */ #define ANADIG_PLL2_NUM_MFN_MASK 0x3fffffff /* ANADIG_PLL2_DENOM: PLL2 Denominator definition register */ #define ANADIG_PLL2_DENOM_MFN_MASK 0x3fffffff /* ANADIG_PLL4_CTRL: PLL4 Control Register (audio PLL) */ #define ANADIG_PLL4_CTRL_LOCK (1 << 31) #define ANADIG_PLL4_CTRL_PFD_OFFSET_EN (1 << 18) #define ANADIG_PLL4_CTRL_DITHER_ENABLE (1 << 17) #define ANADIG_PLL4_CTRL_BYPASS (1 << 16) #define ANADIG_PLL4_CTRL_BYPASS_CLK_SRC (1 << 14) #define ANADIG_PLL4_CTRL_ENABLE (1 << 13) #define ANADIG_PLL4_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL4_CTRL_DIV_SELECT_MASK (0x7f) /* ANADIG_PLL4_NUM: PLL4 Numerator definition register */ #define ANADIG_PLL4_NUM_MFN_MASK 0x3fffffff /* ANADIG_PLL4_DENOM: PLL4 Denominator definition register */ #define ANADIG_PLL4_DENOM_MFN_MASK 0x3fffffff /* ANADIG_PLL6_CTRL: PLL6 Control Register (video PLL) */ #define ANADIG_PLL6_CTRL_LOCK (1 << 31) #define ANADIG_PLL6_CTRL_PFD_OFFSET_EN (1 << 18) #define ANADIG_PLL6_CTRL_DITHER_ENABLE (1 << 17) #define ANADIG_PLL6_CTRL_BYPASS (1 << 16) #define ANADIG_PLL6_CTRL_BYPASS_CLK_SRC (1 << 14) #define ANADIG_PLL6_CTRL_ENABLE (1 << 13) #define ANADIG_PLL6_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL6_CTRL_DIV_SELECT_MASK (0x7f) /* ANADIG_PLL6_NUM: PLL6 Numerator definition register */ #define ANADIG_PLL6_NUM_MFN_MASK 0x3fffffff /* ANADIG_PLL6_DENOM: PLL6 Denominator definition register */ #define ANADIG_PLL6_DENOM_MFN_MASK 0x3fffffff /* ANADIG_PLL5_CTRL: PLL5 Control Register (video PLL) */ #define ANADIG_PLL5_CTRL_LOCK (1 << 31) #define ANADIG_PLL5_CTRL_PFD_OFFSET_EN (1 << 18) #define ANADIG_PLL5_CTRL_DITHER_ENABLE (1 << 17) #define ANADIG_PLL5_CTRL_BYPASS (1 << 16) #define ANADIG_PLL5_CTRL_BYPASS_CLK_SRC (1 << 14) #define ANADIG_PLL5_CTRL_ENABLE (1 << 13) #define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL5_CTRL_DIV_SELECT_MASK (0x3) /* ANADIG_PLL_PFD: PLL1/PLL2/PLL3 PFD Clocks */ #define ANADIG_PLL_PFD4_CLKGATE (1 << 31) #define ANADIG_PLL_PFD4_STABLE (1 << 30) #define ANADIG_PLL_PFD4_FRAC_SHIFT 24 #define ANADIG_PLL_PFD4_FRAC_MASK (0x3f << 24) #define ANADIG_PLL_PFD3_CLKGATE (1 << 23) #define ANADIG_PLL_PFD3_STABLE (1 << 22) #define ANADIG_PLL_PFD3_FRAC_SHIFT 16 #define ANADIG_PLL_PFD3_FRAC_MASK (0x3f << 16) #define ANADIG_PLL_PFD2_CLKGATE (1 << 15) #define ANADIG_PLL_PFD2_STABLE (1 << 14) #define ANADIG_PLL_PFD2_FRAC_SHIFT 8 #define ANADIG_PLL_PFD2_FRAC_MASK (0x3f << 8) #define ANADIG_PLL_PFD1_CLKGATE (1 << 7) #define ANADIG_PLL_PFD1_STABLE (1 << 6) #define ANADIG_PLL_PFD1_FRAC_SHIFT 0 #define ANADIG_PLL_PFD1_FRAC_MASK (0x3f << 0) /* AANADIG_ANA_MISC0: miscellaneous analog blocks */ #define ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17) #define ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16) #define ANADIG_ANA_MISC0_CLK_24M_IRC_XTAL_SEL (1 << 13) #define ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12) #define ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7) #define ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3) #define ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2) #define ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1) #define ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0) /* AANADIG_ANA_MISC0: miscellaneous analog blocks */ #define ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30) #define ANADIG_ANA_MISC1_IRQ_TEMPSENSE (1 << 29) #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) /* AANADIG_ANA_DIGPROG: Digital Program register */ #define ANADIG_ANADIG_DIGPROG_MAJOR_MASK (0xffff << 8) #define ANADIG_ANADIG_DIGPROG_MINOR_MASK (0xff << 0) /* ANADIG_PLL1_CTRL: PLL1 Control Register (video PLL) */ #define ANADIG_PLL1_CTRL_LOCK (1 << 31) #define ANADIG_PLL1_CTRL_PFD_OFFSET_EN (1 << 18) #define ANADIG_PLL1_CTRL_DITHER_ENABLE (1 << 17) #define ANADIG_PLL1_CTRL_BYPASS (1 << 16) #define ANADIG_PLL1_CTRL_BYPASS_CLK_SRC (1 << 14) #define ANADIG_PLL1_CTRL_ENABLE (1 << 13) #define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL1_CTRL_DIV_SELECT (1 << 1) /* ANADIG_PLL1_SS: PLL1 Spread Spectrum definition register */ #define ANADIG_PLL1_SS_STOP_MASK (0xffff << 16) #define ANADIG_PLL1_SS_ENABLE (1 << 15) #define ANADIG_PLL1_SS_STEP_MASK 0x8fff /* ANADIG_PLL1_NUM: PLL1 Numerator definition register */ #define ANADIG_PLL1_NUM_MFN_MASK 0x3fffffff /* ANADIG_PLL1_DENOM: PLL1 Denominator definition register */ #define ANADIG_PLL1_DENOM_MFN_MASK 0x3fffffff /* ANADIG_PLL_LOCK: PLL Lock Register */ #define ANADIG_PLL_LOCK_PLL1 (1 << 6) #define ANADIG_PLL_LOCK_PLL2 (1 << 5) #define ANADIG_PLL_LOCK_PLL4 (1 << 4) #define ANADIG_PLL_LOCK_PLL6 (1 << 3) #define ANADIG_PLL_LOCK_PLL5 (1 << 2) #define ANADIG_PLL_LOCK_PLL3 (1 << 1) #define ANADIG_PLL_LOCK_PLL7 (1 << 0) /** CCM - Register Layout Typedef */ typedef struct { __IO uint32_t CCM_CCR; __IO uint32_t CCM_CSR; __IO uint32_t CCM_CCSR; __IO uint32_t CCM_CACRR; __IO uint32_t CCM_CSCMR1; __IO uint32_t CCM_CSCDR1; __IO uint32_t CCM_CSCDR2; __IO uint32_t CCM_CSCDR3; __IO uint32_t CCM_CSCMR2; __IO uint8_t RESERVED_0[4]; __IO uint32_t CCM_CTOR; __IO uint32_t CCM_CLPCR; __IO uint32_t CCM_CISR; __IO uint32_t CCM_CIMR; __IO uint32_t CCM_CCOSR; __IO uint32_t CCM_CGPR; __IO uint32_t CCM_CCGR0; __IO uint32_t CCM_CCGR1; __IO uint32_t CCM_CCGR2; __IO uint32_t CCM_CCGR3; __IO uint32_t CCM_CCGR4; __IO uint32_t CCM_CCGR5; __IO uint32_t CCM_CCGR6; __IO uint32_t CCM_CCGR7; __IO uint32_t CCM_CCGR8; __IO uint32_t CCM_CCGR9; __IO uint32_t CCM_CCGR10; __IO uint32_t CCM_CCGR11; __IO uint32_t CCM_CMEOR0; __IO uint32_t CCM_CMEOR1; __IO uint32_t CCM_CMEOR2; __IO uint32_t CCM_CMEOR3; __IO uint32_t CCM_CMEOR4; __IO uint32_t CCM_CMEOR5; __IO uint32_t CCM_CPPDSR; __IO uint32_t CCM_CCOWR; __IO uint32_t CCM_CCPGR0; __IO uint32_t CCM_CCPGR1; __IO uint32_t CCM_CCPGR2; __IO uint32_t CCM_CCPGR3; } CCM_Type, *CCM_MemMapPtr; #define CCM_CCR_REG(base) ((base)->CCM_CCR) #define CCM_CSR_REG(base) ((base)->CCM_CSR) #define CCM_CCSR_REG(base) ((base)->CCM_CCSR) #define CCM_CACRR_REG(base) ((base)->CCM_CACRR) #define CCM_CSCMR1_REG(base) ((base)->CCM_CACMR1) #define CCM_CSCDR1_REG(base) ((base)->CCM_CSCDR1) #define CCM_CSCDR2_REG(base) ((base)->CCM_CSCDR2) #define CCM_CSCDR3_REG(base) ((base)->CCM_CSCDR3) #define CCM_CSCMR2_REG(base) ((base)->CCM_CSCMR2) #define CCM_CTOR_REG(base) ((base)->CCM_CTOR) #define CCM_CLPCR_REG(base) ((base)->CCM_CLPCR) #define CCM_CISR_REG(base) ((base)->CCM_CISR) #define CCM_CIMR_REG(base) ((base)->CCM_CIMR) #define CCM_CCOSR_REG(base) ((base)->CCM_CCOSR) #define CCM_CGPR_REG(base) ((base)->CCM_CGRP) #define CCM_CCGR0_REG(base) ((base)->CCM_CCGR0) #define CCM_CCGR1_REG(base) ((base)->CCM_CCGR1) #define CCM_CCGR2_REG(base) ((base)->CCM_CCGR2) #define CCM_CCGR3_REG(base) ((base)->CCM_CCGR3) #define CCM_CCGR4_REG(base) ((base)->CCM_CCGR4) #define CCM_CCGR5_REG(base) ((base)->CCM_CCGR5) #define CCM_CCGR6_REG(base) ((base)->CCM_CCGR6) #define CCM_CCGR7_REG(base) ((base)->CCM_CCGR7) #define CCM_CCGR8_REG(base) ((base)->CCM_CCGR8) #define CCM_CCGR9_REG(base) ((base)->CCM_CCGR9) #define CCM_CCGR10_REG(base) ((base)->CCM_CCGR10) #define CCM_CCGR11_REG(base) ((base)->CCM_CCGR11) #define CCM_CMEOR0_REG(base) ((base)->CCM_CMEOR0) #define CCM_CMEOR1_REG(base) ((base)->CCM_CMEOR1) #define CCM_CMEOR2_REG(base) ((base)->CCM_CMEOR2) #define CCM_CMEOR3_REG(base) ((base)->CCM_CMEOR3) #define CCM_CMEOR4_REG(base) ((base)->CCM_CMEOR4) #define CCM_CMEOR5_REG(base) ((base)->CCM_CMEOR5) #define CCM_CPPDSR_REG(base) ((base)->CCM_CPPDSR) #define CCM_CCOWR_REG(base) ((base)->CCM_CCOWR) #define CCM_CCPGR0_REG(base) ((base)->CCM_CCPGR0) #define CCM_CCPGR1_REG(base) ((base)->CCM_CCPGR1) #define CCM_CCPGR2_REG(base) ((base)->CCM_CCPGR2) #define CCM_CCPGR3_REG(base) ((base)->CCM_CCRGR3) /* CCM - Peripheral instance base addresses */ /** Peripheral CCM base pointer */ #define CCM ((CCM_Type *)CCM_BASE) #define CCM_BASE_PTR (CCM) /** Array initializer of CCM peripheral base adresses */ #define CCM_BASE_ADDRS { CCM_BASE } /** Array initializer of CCM peripheral base pointers */ #define CCM_BASE_PTRS { CCM } /* --- CCM registers ------------------------------------------------------- */ #define CCM_CCR CCM_CCR_REG(CCM_BASE_PTR) #define CCM_CSR CCM_CSR_REG(CCM_BASE_PTR) #define CCM_CCSR CCM_CCSR_REG(CCM_BASE_PTR) #define CCM_CACRR CCM_CACRR_REG(CCM_BASE_PTR) #define CCM_CSCMR1 CCM_CSCMR1_REG(CCM_BASE_PTR) #define CCM_CSCDR1 CCM_CSCDR1_REG(CCM_BASE_PTR) #define CCM_CSCDR2 CCM_CSCDR2_REG(CCM_BASE_PTR) #define CCM_CSCDR3 CCM_CSCDR3_REG(CCM_BASE_PTR) #define CCM_CSCMR2 CCM_CSCMR2_REG(CCM_BASE_PTR) #define CCM_CTOR CCM_CTOR_REG(CCM_BASE_PTR) #define CCM_CLPCR CCM_CLPCR_REG(CCM_BASE_PTR) #define CCM_CISR CCM_CISR_REG(CCM_BASE_PTR) #define CCM_CIMR CCM_CIMR_REG(CCM_BASE_PTR) #define CCM_CCOSR CCM_CCOSR_REG(CCM_BASE_PTR) #define CCM_CGPR CCM_CGPR_REG(CCM_BASE_PTR) #define CCM_CCGR0 CCM_CCGR0_REG(CCM_BASE_PTR) #define CCM_CCGR1 CCM_CCGR1_REG(CCM_BASE_PTR) #define CCM_CCGR2 CCM_CCGR2_REG(CCM_BASE_PTR) #define CCM_CCGR3 CCM_CCGR3_REG(CCM_BASE_PTR) #define CCM_CCGR4 CCM_CCGR4_REG(CCM_BASE_PTR) #define CCM_CCGR5 CCM_CCGR5_REG(CCM_BASE_PTR) #define CCM_CCGR6 CCM_CCGR6_REG(CCM_BASE_PTR) #define CCM_CCGR7 CCM_CCGR7_REG(CCM_BASE_PTR) #define CCM_CCGR8 CCM_CCGR8_REG(CCM_BASE_PTR) #define CCM_CCGR9 CCM_CCGR9_REG(CCM_BASE_PTR) #define CCM_CCGR10 CCM_CCGR10_REG(CCM_BASE_PTR) #define CCM_CCGR11 CCM_CCGR11_REG(CCM_BASE_PTR) #define CCM_CMEOR0 CCM_CMEOR0_REG(CCM_BASE_PTR) #define CCM_CMEOR1 CCM_CMEOR1_REG(CCM_BASE_PTR) #define CCM_CMEOR2 CCM_CMEOR2_REG(CCM_BASE_PTR) #define CCM_CMEOR3 CCM_CMEOR3_REG(CCM_BASE_PTR) #define CCM_CMEOR4 CCM_CMEOR4_REG(CCM_BASE_PTR) #define CCM_CMEOR5 CCM_CMEOR5_REG(CCM_BASE_PTR) #define CCM_CPPDSR CCM_CPPDSR_REG(CCM_BASE_PTR) #define CCM_CCOWR CCM_CCOWR_REG(CCM_BASE_PTR) #define CCM_CCPGR0 CCM_CCPGR0_REG(CCM_BASE_PTR) #define CCM_CCPGR1 CCM_CCPGR1_REG(CCM_BASE_PTR) #define CCM_CCPGR2 CCM_CCPGR2_REG(CCM_BASE_PTR) #define CCM_CCPGR3 CCM_CCPGR3_REG(CCM_BASE_PTR) /* --- CCM values -....----------------------------------------------------- */ /* CCR: CCM Control Register */ #define CCM_CCR_FIRC_EN (1 << 16) #define CCM_CCR_FXOSC_EN (1 << 12) #define CCM_CCR_OSCNT_MASK 0xff /* CSR: CCM Status Register */ #define CCM_CSR_FXOSC_RDY (1 << 5) /* CCSR: CCM Clock Switcher Register */ #define CCM_CCSR_PLL3_PFDN4_EN (1 << 31) #define CCM_CCSR_PLL3_PFDN3_EN (1 << 30) #define CCM_CCSR_PLL3_PFDN2_EN (1 << 29) #define CCM_CCSR_PLL3_PFDN1_EN (1 << 28) #define CCM_CCSR_DAP_EN (1 << 24) /* PLL1/PLL2 PFD SEL definition */ #define CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT 19 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) #define CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT 16 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) #define CCM_CCSR_PLL_PFD_CLK_SEL_MAIN 0x0 #define CCM_CCSR_PLL_PFD_CLK_SEL_PFD1 0x1 #define CCM_CCSR_PLL_PFD_CLK_SEL_PFD2 0x2 #define CCM_CCSR_PLL_PFD_CLK_SEL_PFD3 0x3 #define CCM_CCSR_PLL_PFD_CLK_SEL_PFD4 0x4 #define CCM_CCSR_PLL2_PFDN4_EN (1 << 15) #define CCM_CCSR_PLL2_PFDN3_EN (1 << 14) #define CCM_CCSR_PLL2_PFDN2_EN (1 << 13) #define CCM_CCSR_PLL2_PFDN1_EN (1 << 12) #define CCM_CCSR_PLL1_PFDN4_EN (1 << 11) #define CCM_CCSR_PLL1_PFDN3_EN (1 << 10) #define CCM_CCSR_PLL1_PFDN2_EN (1 << 9) #define CCM_CCSR_PLL1_PFDN1_EN (1 << 8) #define CCM_CCSR_DDRC_CLK_SEL (1 << 7) #define CCM_CCSR_FAST_CLK_SEL (1 << 6) #define CCM_CCSR_SLOW_CLK_SEL (1 << 5) #define CCM_CCSR_SYS_CLK_SEL_SHIFT 0 #define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 #define CCM_CCSR_SYS_CLK_SEL_FAST 0x0 #define CCM_CCSR_SYS_CLK_SEL_SLOW 0x1 #define CCM_CCSR_SYS_CLK_SEL_PLL2_PFD 0x2 #define CCM_CCSR_SYS_CLK_SEL_PLL2 0x3 #define CCM_CCSR_SYS_CLK_SEL_PLL1_PFD 0x4 #define CCM_CCSR_SYS_CLK_SEL_PLL3 0x5 /* CACRR: ARM Clock Root Register */ #define CCM_CACRR_FLEX_CLK_DIV_SHIFT 22 #define CCM_CACRR_FLEX_CLK_DIV_MASK (0x7 << 22) #define CCM_CACRR_PLL6_CLK_DIV (1 << 21) #define CCM_CACRR_PLL3_CLK_DIV (1 << 20) #define CCM_CACRR_PLL1_PFD_CLK_DIV_SHIFT 16 #define CCM_CACRR_PLL1_PFD_CLK_DIV_MASK (0x3 << 16) #define CCM_CACRR_IPG_CLK_DIV_SHIFT 11 #define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) #define CCM_CACRR_PLL4_CLK_DIV_SHIFT 6 #define CCM_CACRR_PLL4_CLK_DIV_MASK (0x7 << 6) #define CCM_CACRR_BUS_CLK_DIV_SHIFT 3 #define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) #define CCM_CACRR_ARM_CLK_DIV_SHIFT 0 #define CCM_CACRR_ARM_CLK_DIV_MASK (0x7 << 0) #define CCM_CGR_MASK(gate) ((gate % 16) << 1) /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer * @{ */ /** GPIO - Register Layout Typedef */ typedef struct { __IO uint32_t PDOR; __IO uint32_t PSOR; __IO uint32_t PCOR; __IO uint32_t PTOR; __IO uint32_t PDIR; } GPIO_Type, *GPIO_MemMapPtr; /* ---------------------------------------------------------------------------- -- GPIO - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros * @{ */ /* GPIO - Register accessors */ #define GPIO_PDOR_REG(base) ((base)->PDOR) #define GPIO_PSOR_REG(base) ((base)->PSOR) #define GPIO_PCOR_REG(base) ((base)->PCOR) #define GPIO_PTOR_REG(base) ((base)->PTOR) #define GPIO_PDIR_REG(base) ((base)->PDIR) /*! * @} */ /* end of group GPIO_Register_Accessor_Macros */ /* Calculate GPIO port base based on GPIO pin */ #define GPIO(pin) (GPIO_Type *)(GPIO_BASE + ((pin >> 5) << 6)) #define GPIO_OFFSET(gpio) (0x1 << (gpio & 0x1F)) /* GPIO - Peripheral instance base addresses */ /** Peripheral GPIO0 base pointer */ #define GPIO0 ((GPIO_Type *)GPIO0_BASE) #define GPIO0_BASE_PTR (GPIO0) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((GPIO_Type *)GPIO1_BASE) #define GPIO1_BASE_PTR (GPIO1) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((GPIO_Type *)GPIO2_BASE) #define GPIO2_BASE_PTR (GPIO2) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((GPIO_Type *)GPIO3_BASE) #define GPIO3_BASE_PTR (GPIO3) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((GPIO_Type *)GPIO4_BASE) #define GPIO4_BASE_PTR (GPIO4) /** Array initializer of GPIO peripheral base adresses */ #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } /* ---------------------------------------------------------------------------- -- UART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer * @{ */ /** UART - Register Layout Typedef */ typedef struct { __IO uint8_t UART_BDH; __IO uint8_t UART_BDL; __IO uint8_t UART_C1; __IO uint8_t UART_C2; __IO uint8_t UART_S1; __IO uint8_t UART_S2; __IO uint8_t UART_C3; __IO uint8_t UART_D; __IO uint8_t UART_MA1; __IO uint8_t UART_MA2; __IO uint8_t UART_C4; __IO uint8_t UART_C5; __IO uint8_t UART_ED; __IO uint8_t UART_MODEM; __IO uint8_t UART_IR; __IO uint8_t UART_PFIFO; __IO uint8_t UART_CFIFO; __IO uint8_t UART_SFIFO; __IO uint8_t UART_TWFIFO; __IO uint8_t UART_TCFIFO; __IO uint8_t UART_RWFIFO; __IO uint8_t UART_RCFIFO; __IO uint8_t UART_C7816; __IO uint8_t UART_IS7816; __IO uint8_t UART_WP7816T0; __IO uint8_t UART_WP7816T1; __IO uint8_t UART_WN7816; __IO uint8_t UART_WF7816; __IO uint8_t UART_ET7816; __IO uint8_t UART_TL7816; } UART_Type, *UART_MemMapPtr; /* ---------------------------------------------------------------------------- -- UART - Register accessor macros ---------------------------------------------------------------------------- */ /* UART - Peripheral instance base addresses */ /** Peripheral UART1 base pointer */ #define UART1 ((UART_Type *)UART1_BASE) #define UART1_BASE_PTR (UART1) /** Peripheral UART2 base pointer */ #define UART2 ((UART_Type *)UART2_BASE) #define UART2_BASE_PTR (UART2) /** Peripheral UART3 base pointer */ #define UART3 ((UART_Type *)UART3_BASE) #define UART3_BASE_PTR (UART3) /** Peripheral UART4 base pointer */ #define UART4 ((UART_Type *)UART4_BASE) #define UART4_BASE_PTR (UART4) /** Peripheral UART5 base pointer */ #define UART5 ((UART_Type *)UART5_BASE) #define UART5_BASE_PTR (UART5) /** Array initializer of UART peripheral base adresses */ #define UART_BASE_ADDRS { UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE } /** Array initializer of UART peripheral base pointers */ #define UART_BASE_PTRS { UART1, UART2, UART3, UART4, UART5 } /** Interrupt vectors for the UART peripheral type */ #define UART_IRQS { UART0_IRQ, UART1_IRQ, UART2_IRQ, UART3_IRQ, UART4_IRQ, UART5_IRQ } /*! * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros * @{ */ /* UART - Register accessors */ #define UART_BDH_REG(base) ((base)->UART_BDH) #define UART_BDL_REG(base) ((base)->UART_BDL) #define UART_C1_REG(base) ((base)->UART_C1) #define UART_C2_REG(base) ((base)->UART_C2) #define UART_S1_REG(base) ((base)->UART_S1) #define UART_S2_REG(base) ((base)->UART_S2) #define UART_C3_REG(base) ((base)->UART_C3) #define UART_D_REG(base) ((base)->UART_D) #define UART_MA1_REG(base) ((base)->UART_MA1) #define UART_MA2_REG(base) ((base)->UART_MA2) #define UART_C4_REG(base) ((base)->UART_C4) #define UART_C5_REG(base) ((base)->UART_C5) #define UART_ED_REG(base) ((base)->UART_ED) #define UART_MODEM_REG(base) ((base)->UART_MODEM) #define UART_IR_REG(base) ((base)->UART_IR) #define UART_PFIFO_REG(base) ((base)->UART_PFIFO) #define UART_CFIFO_REG(base) ((base)->UART_CFIFO) #define UART_SFIFO_REG(base) ((base)->UART_SFIFO) #define UART_TWFIFO_REG(base) ((base)->UART_TWFIFO) #define UART_TCFIFO_REG(base) ((base)->UART_TCFIFO) #define UART_RWFIFO_REG(base) ((base)->UART_RWFIFO) #define UART_RCFIFO_REG(base) ((base)->UART_RCFIFO) #define UART_C7816_REG(base) ((base)->UART_C7816) #define UART_IS7816_REG(base) ((base)->UART_IS7816) #define UART_WP7816T0_REG(base) ((base)->UART_WP7816T0) #define UART_WP7816T1_REG(base) ((base)->UART_WP7816T1) #define UART_WN7816_REG(base) ((base)->UART_WN7816) #define UART_WF7816_REG(base) ((base)->UART_WF7816) #define UART_ET7816_REG(base) ((base)->UART_ET7816) #define UART_TL7816_REG(base) ((base)->UART_TL7816) /* BDH: Baud Rate Register High */ #define UART_BDH_LBKDIE (1 << 7) #define UART_BDH_RXEDGIE (1 << 6) #define UART_BDH_SBR_MASK 0x1f #define UART_C4_BRFA_MASK 0x1f /* BDL: Baud Rate Register Low */ #define UART_BDL_SBR_MASK 0xff /* C1: Control register 1 */ #define UART_UCR1_LOOPS (1 << 7) #define UART_UCR1_RSRC (1 << 5) #define UART_UCR1_M (1 << 4) #define UART_UCR1_WAKE (1 << 3) #define UART_UCR1_ILT (1 << 2) #define UART_UCR1_PE (1 << 1) #define UART_UCR1_PT (1 << 0) /* C2: Control register 2 */ #define UART_UCR2_TIE (1 << 7) #define UART_UCR2_TCIE (1 << 6) #define UART_UCR2_RIE (1 << 5) #define UART_UCR2_ILIE (1 << 4) #define UART_UCR2_TE (1 << 3) #define UART_UCR2_RE (1 << 2) #define UART_UCR2_RWU (1 << 1) #define UART_UCR2_SBK (1 << 0) /* S1: Status register 1 */ #define UART_S1_TDRE (1 << 7) #define UART_S1_TC (1 << 6) #define UART_S1_RDRF (1 << 5) #define UART_S1_IDLE (1 << 4) #define UART_S1_OR (1 << 3) #define UART_S1_NF (1 << 2) #define UART_S1_FE (1 << 1) #define UART_S1_PF (1 << 0) /* S2: Status register 2 */ #define UART_S2_LBKDIF (1 << 7) #define UART_S2_RXEDGIF (1 << 6) #define UART_S2_MSBF (1 << 5) #define UART_S2_RXINV (1 << 4) #define UART_S2_RWUID (1 << 3) #define UART_S2_BRK13 (1 << 2) #define UART_S2_LBKDE (1 << 1) #define UART_S2_RAF (1 << 0) /* C3: Control register 3 */ #define UART_C3_R8 (1 << 7) #define UART_C3_T8 (1 << 6) #define UART_C3_TXDIR (1 << 5) #define UART_C3_TXINV (1 << 4) #define UART_C3_ORIE (1 << 3) #define UART_C3_NEIE (1 << 2) #define UART_C3_FEIE (1 << 1) #define UART_C3_PEIE (1 << 0) /* MODEM: Modem configuration register */ #define UART_MODEM_RXRTSE (1 << 3) #define UART_MODEM_TXRTSPOL (1 << 2) #define UART_MODEM_TXRTSE (1 << 1) #define UART_MODEM_TXCTSE (1 << 0) /****************************************************************************/ /** @defgroup uart_parity UART Parity Selection @ingroup VF6xx_uart_defines @{*/ #define UART_PARITY_NONE 0x00 #define UART_PARITY_EVEN UART_C1_PE #define UART_PARITY_ODD (UART_C1_PE | UART_C1_PT) /**@}*/ #define UART_PARITY_MASK 0x3 /* CR3_CTSE/CR3_RTSE combined values */ /****************************************************************************/ /** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection @ingroup STM32F_usart_defines @{*/ #define UART_FLOWCONTROL_NONE 0x00 #define UART_FLOWCONTROL_RTS UART_MODEM_RXRTSE #define UART_FLOWCONTROL_CTS UART_MODEM_TXCTSE #define UART_FLOWCONTROL_RTS_CTS (UART_MODEM_RXRTSE | UART_MODEM_TXCTSE) /**@}*/ #define UART_FLOWCONTROL_MASK (UART_MODEM_RXRTSE | UART_MODEM_TXCTSE) /*! * @} */ /* end of group UART_Peripheral */ /* ---------------------------------------------------------------------------- -- IOMUXC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer * @{ */ /** IOMUXC - Register Layout Typedef */ typedef struct { __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA6; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA8; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA9; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA10; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA11; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA12; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA16; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA17; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA18; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA19; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA20; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA21; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA22; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA23; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA24; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA25; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA26; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA27; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA28; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA29; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA30; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA31; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB2; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB3; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB4; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB5; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB6; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB7; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB8; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB9; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB10; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB11; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB12; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB13; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB14; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB15; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB16; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB17; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB18; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB19; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB20; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB21; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB22; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC2; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC3; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC4; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC5; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC6; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC7; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC8; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC9; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC10; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC11; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC12; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC13; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC14; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC15; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC16; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC17; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD31; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD30; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD29; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD28; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD27; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD26; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD25; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD24; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD23; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD22; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD21; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD20; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD19; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD18; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD17; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD16; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD2; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD3; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD4; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD5; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD6; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD7; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD8; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD9; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD10; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD11; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD12; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTD13; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB23; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB24; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB25; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB26; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB27; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTB28; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC26; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC27; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC28; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC29; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC30; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTC31; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE2; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE3; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE4; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE5; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE6; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE7; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE8; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE9; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE10; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE11; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE12; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE13; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE14; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE15; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE16; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE17; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE18; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE19; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE20; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE21; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE22; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE23; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE24; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE25; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE26; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE27; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTE28; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_PTA7; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A15; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A14; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A13; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A12; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A11; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A10; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A9; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A8; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A7; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A6; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A5; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A4; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A3; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A2; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_A0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_BA2; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_BA1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_BA0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CAS_B; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CKE0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CLK0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_B0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D15; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D14; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D13; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D12; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D11; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D10; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D9; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D8; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D7; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D6; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D5; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D4; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D3; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D2; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_DQM1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_DQM0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_DQS1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_DQS0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_RAS_B; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_WE_B; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_ODT0; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_ODT1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_DDRBYTE1; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DDR_DDRBYTE2; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SRC_IPP_BOOT_CFG_18_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SRC_IPP_BOOT_CFG_19_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_SRC_IPP_BOOT_CFG_20_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT; __IO uint32_t SW_MUX_CTL_PAD_IOMUXC_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT; } IOMUXC_Type, *IOMUXC_MemMapPtr; #define IOMUXC_SW_MUX_CTL_PAD_PTA6_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA6) #define IOMUXC_SW_MUX_CTL_PAD_PTA8_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA8) #define IOMUXC_SW_MUX_CTL_PAD_PTA9_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA9) #define IOMUXC_SW_MUX_CTL_PAD_PTA10_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA10) #define IOMUXC_SW_MUX_CTL_PAD_PTA11_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA11) #define IOMUXC_SW_MUX_CTL_PAD_PTA12_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA12) #define IOMUXC_SW_MUX_CTL_PAD_PTA16_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA16) #define IOMUXC_SW_MUX_CTL_PAD_PTA17_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA17) #define IOMUXC_SW_MUX_CTL_PAD_PTA18_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA18) #define IOMUXC_SW_MUX_CTL_PAD_PTA19_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA19) #define IOMUXC_SW_MUX_CTL_PAD_PTA20_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA20) #define IOMUXC_SW_MUX_CTL_PAD_PTA21_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA21) #define IOMUXC_SW_MUX_CTL_PAD_PTA22_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA22) #define IOMUXC_SW_MUX_CTL_PAD_PTA23_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA23) #define IOMUXC_SW_MUX_CTL_PAD_PTA24_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA24) #define IOMUXC_SW_MUX_CTL_PAD_PTA25_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA25) #define IOMUXC_SW_MUX_CTL_PAD_PTA26_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA26) #define IOMUXC_SW_MUX_CTL_PAD_PTA27_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA27) #define IOMUXC_SW_MUX_CTL_PAD_PTA28_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA28) #define IOMUXC_SW_MUX_CTL_PAD_PTA29_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA29) #define IOMUXC_SW_MUX_CTL_PAD_PTA30_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA30) #define IOMUXC_SW_MUX_CTL_PAD_PTA31_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA31) #define IOMUXC_SW_MUX_CTL_PAD_PTB0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB0) #define IOMUXC_SW_MUX_CTL_PAD_PTB1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB1) #define IOMUXC_SW_MUX_CTL_PAD_PTB2_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB2) #define IOMUXC_SW_MUX_CTL_PAD_PTB3_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB3) #define IOMUXC_SW_MUX_CTL_PAD_PTB4_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB4) #define IOMUXC_SW_MUX_CTL_PAD_PTB5_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB5) #define IOMUXC_SW_MUX_CTL_PAD_PTB6_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB6) #define IOMUXC_SW_MUX_CTL_PAD_PTB7_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB7) #define IOMUXC_SW_MUX_CTL_PAD_PTB8_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB8) #define IOMUXC_SW_MUX_CTL_PAD_PTB9_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB9) #define IOMUXC_SW_MUX_CTL_PAD_PTB10_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB10) #define IOMUXC_SW_MUX_CTL_PAD_PTB11_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB11) #define IOMUXC_SW_MUX_CTL_PAD_PTB12_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB12) #define IOMUXC_SW_MUX_CTL_PAD_PTB13_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB13) #define IOMUXC_SW_MUX_CTL_PAD_PTB14_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB14) #define IOMUXC_SW_MUX_CTL_PAD_PTB15_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB15) #define IOMUXC_SW_MUX_CTL_PAD_PTB16_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB16) #define IOMUXC_SW_MUX_CTL_PAD_PTB17_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB17) #define IOMUXC_SW_MUX_CTL_PAD_PTB18_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB18) #define IOMUXC_SW_MUX_CTL_PAD_PTB19_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB19) #define IOMUXC_SW_MUX_CTL_PAD_PTB20_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB20) #define IOMUXC_SW_MUX_CTL_PAD_PTB21_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB21) #define IOMUXC_SW_MUX_CTL_PAD_PTB22_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB22) #define IOMUXC_SW_MUX_CTL_PAD_PTC0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC0) #define IOMUXC_SW_MUX_CTL_PAD_PTC1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC1) #define IOMUXC_SW_MUX_CTL_PAD_PTC2_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC2) #define IOMUXC_SW_MUX_CTL_PAD_PTC3_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC3) #define IOMUXC_SW_MUX_CTL_PAD_PTC4_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC4) #define IOMUXC_SW_MUX_CTL_PAD_PTC5_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC5) #define IOMUXC_SW_MUX_CTL_PAD_PTC6_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC6) #define IOMUXC_SW_MUX_CTL_PAD_PTC7_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC7) #define IOMUXC_SW_MUX_CTL_PAD_PTC8_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC8) #define IOMUXC_SW_MUX_CTL_PAD_PTC9_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC9) #define IOMUXC_SW_MUX_CTL_PAD_PTC10_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC10) #define IOMUXC_SW_MUX_CTL_PAD_PTC11_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC11) #define IOMUXC_SW_MUX_CTL_PAD_PTC12_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC12) #define IOMUXC_SW_MUX_CTL_PAD_PTC13_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC13) #define IOMUXC_SW_MUX_CTL_PAD_PTC14_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC14) #define IOMUXC_SW_MUX_CTL_PAD_PTC15_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC15) #define IOMUXC_SW_MUX_CTL_PAD_PTC16_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC16) #define IOMUXC_SW_MUX_CTL_PAD_PTC17_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC17) #define IOMUXC_SW_MUX_CTL_PAD_PTD31_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD31) #define IOMUXC_SW_MUX_CTL_PAD_PTD30_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD30) #define IOMUXC_SW_MUX_CTL_PAD_PTD29_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD29) #define IOMUXC_SW_MUX_CTL_PAD_PTD28_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD28) #define IOMUXC_SW_MUX_CTL_PAD_PTD27_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD27) #define IOMUXC_SW_MUX_CTL_PAD_PTD26_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD26) #define IOMUXC_SW_MUX_CTL_PAD_PTD25_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD25) #define IOMUXC_SW_MUX_CTL_PAD_PTD24_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD24) #define IOMUXC_SW_MUX_CTL_PAD_PTD23_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD23) #define IOMUXC_SW_MUX_CTL_PAD_PTD22_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD22) #define IOMUXC_SW_MUX_CTL_PAD_PTD21_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD21) #define IOMUXC_SW_MUX_CTL_PAD_PTD20_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD20) #define IOMUXC_SW_MUX_CTL_PAD_PTD19_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD19) #define IOMUXC_SW_MUX_CTL_PAD_PTD18_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD18) #define IOMUXC_SW_MUX_CTL_PAD_PTD17_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD17) #define IOMUXC_SW_MUX_CTL_PAD_PTD16_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD16) #define IOMUXC_SW_MUX_CTL_PAD_PTD0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD0) #define IOMUXC_SW_MUX_CTL_PAD_PTD1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD1) #define IOMUXC_SW_MUX_CTL_PAD_PTD2_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD2) #define IOMUXC_SW_MUX_CTL_PAD_PTD3_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD3) #define IOMUXC_SW_MUX_CTL_PAD_PTD4_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD4) #define IOMUXC_SW_MUX_CTL_PAD_PTD5_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD5) #define IOMUXC_SW_MUX_CTL_PAD_PTD6_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD6) #define IOMUXC_SW_MUX_CTL_PAD_PTD7_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD7) #define IOMUXC_SW_MUX_CTL_PAD_PTD8_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD8) #define IOMUXC_SW_MUX_CTL_PAD_PTD9_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD9) #define IOMUXC_SW_MUX_CTL_PAD_PTD10_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD10) #define IOMUXC_SW_MUX_CTL_PAD_PTD11_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD11) #define IOMUXC_SW_MUX_CTL_PAD_PTD12_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD12) #define IOMUXC_SW_MUX_CTL_PAD_PTD13_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTD13) #define IOMUXC_SW_MUX_CTL_PAD_PTB23_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB23) #define IOMUXC_SW_MUX_CTL_PAD_PTB24_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB24) #define IOMUXC_SW_MUX_CTL_PAD_PTB25_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB25) #define IOMUXC_SW_MUX_CTL_PAD_PTB26_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB26) #define IOMUXC_SW_MUX_CTL_PAD_PTB27_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB27) #define IOMUXC_SW_MUX_CTL_PAD_PTB28_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTB28) #define IOMUXC_SW_MUX_CTL_PAD_PTC26_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC26) #define IOMUXC_SW_MUX_CTL_PAD_PTC27_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC27) #define IOMUXC_SW_MUX_CTL_PAD_PTC28_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC28) #define IOMUXC_SW_MUX_CTL_PAD_PTC29_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC29) #define IOMUXC_SW_MUX_CTL_PAD_PTC30_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC30) #define IOMUXC_SW_MUX_CTL_PAD_PTC31_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTC31) #define IOMUXC_SW_MUX_CTL_PAD_PTE0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE0) #define IOMUXC_SW_MUX_CTL_PAD_PTE1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE1) #define IOMUXC_SW_MUX_CTL_PAD_PTE2_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE2) #define IOMUXC_SW_MUX_CTL_PAD_PTE3_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE3) #define IOMUXC_SW_MUX_CTL_PAD_PTE4_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE4) #define IOMUXC_SW_MUX_CTL_PAD_PTE5_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE5) #define IOMUXC_SW_MUX_CTL_PAD_PTE6_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE6) #define IOMUXC_SW_MUX_CTL_PAD_PTE7_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE7) #define IOMUXC_SW_MUX_CTL_PAD_PTE8_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE8) #define IOMUXC_SW_MUX_CTL_PAD_PTE9_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE9) #define IOMUXC_SW_MUX_CTL_PAD_PTE10_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE10) #define IOMUXC_SW_MUX_CTL_PAD_PTE11_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE11) #define IOMUXC_SW_MUX_CTL_PAD_PTE12_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE12) #define IOMUXC_SW_MUX_CTL_PAD_PTE13_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE13) #define IOMUXC_SW_MUX_CTL_PAD_PTE14_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE14) #define IOMUXC_SW_MUX_CTL_PAD_PTE15_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE15) #define IOMUXC_SW_MUX_CTL_PAD_PTE16_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE16) #define IOMUXC_SW_MUX_CTL_PAD_PTE17_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE17) #define IOMUXC_SW_MUX_CTL_PAD_PTE18_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE18) #define IOMUXC_SW_MUX_CTL_PAD_PTE19_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE19) #define IOMUXC_SW_MUX_CTL_PAD_PTE20_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE20) #define IOMUXC_SW_MUX_CTL_PAD_PTE21_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE21) #define IOMUXC_SW_MUX_CTL_PAD_PTE22_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE22) #define IOMUXC_SW_MUX_CTL_PAD_PTE23_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE23) #define IOMUXC_SW_MUX_CTL_PAD_PTE24_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE24) #define IOMUXC_SW_MUX_CTL_PAD_PTE25_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE25) #define IOMUXC_SW_MUX_CTL_PAD_PTE26_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE26) #define IOMUXC_SW_MUX_CTL_PAD_PTE27_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE27) #define IOMUXC_SW_MUX_CTL_PAD_PTE28_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTE28) #define IOMUXC_SW_MUX_CTL_PAD_PTA7_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_PTA7) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A15_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A15) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A14_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A14) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A13_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A13) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A12_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A12) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A11_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A11) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A10_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A10) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A9_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A9) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A8_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A8) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A7_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A7) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A6_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A6) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A5_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A5) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A4_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A4) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A3_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A3) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A2_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A2) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A1) #define IOMUXC_SW_MUX_CTL_PAD_DDR_A0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_A0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_BA2_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_BA2) #define IOMUXC_SW_MUX_CTL_PAD_DDR_BA1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_BA1) #define IOMUXC_SW_MUX_CTL_PAD_DDR_BA0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_BA0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CAS_B_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CAS_B) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CKE0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CKE0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CLK0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CLK0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_B0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_B0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D15_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D15) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D14_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D14) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D13_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D13) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D12_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D12) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D11_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D11) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D10_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D10) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D9_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D9) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D8_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D8) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D7_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D7) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D6_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D6) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D5_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D5) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D4_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D4) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D3_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D3) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D2_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D2) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D1) #define IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_CS_D0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_DQM1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_DQM1) #define IOMUXC_SW_MUX_CTL_PAD_DDR_DQM0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_DQM0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_DQS1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_DQS1) #define IOMUXC_SW_MUX_CTL_PAD_DDR_DQS0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_DQS0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_RAS_B_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_RAS_B) #define IOMUXC_SW_MUX_CTL_PAD_DDR_WE_B_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_WE_B) #define IOMUXC_SW_MUX_CTL_PAD_DDR_ODT0_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_ODT0) #define IOMUXC_SW_MUX_CTL_PAD_DDR_ODT1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_ODT1) #define IOMUXC_SW_MUX_CTL_PAD_DDR_DDRBYTE1_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_DDRBYTE1) #define IOMUXC_SW_MUX_CTL_PAD_DDR_DDRBYTE2_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DDR_DDRBYTE2) #define IOMUXC_SW_MUX_CTL_PAD_CCM_AUD_EXT_CLK_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_CCM_ENET_EXT_CLK_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_CCM_ENET_TS_CLK_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_DSPI1_IPP_IND_SCK_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_DSPI1_IPP_IND_SIN_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_DSPI1_IPP_IND_SS_B_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_MAC0_TIMER_0_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_MAC0_TIMER_0_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_MAC0_TIMER_1_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_MAC0_TIMER_1_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_FST_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_I2C0_IPP_SCL_IND_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_I2C0_IPP_SDA_IND_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_I2C1_IPP_SCL_IND_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_I2C1_IPP_SDA_IND_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_I2C2_IPP_SCL_IND_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_I2C2_IPP_SDA_IND_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_MLB_TOP_MLBCLK_IN_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_MLB_TOP_MLBDAT_IN_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_MLB_TOP_MLBSIG_IN_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT)) #define IOMUXC_SW_MUX_CTL_PAD_SRC_IPP_BOOT_CFG_18_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SRC_IPP_BOOT_CFG_18_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SRC_IPP_BOOT_CFG_19_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SRC_IPP_BOOT_CFG_19_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_SRC_IPP_BOOT_CFG_20_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_SRC_IPP_BOOT_CFG_20_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT) #define IOMUXC_SW_MUX_CTL_PAD_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT_REG(base) ((base)->SW_MUX_CTL_PAD_IOMUXC_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT) /* IOMUXC - Peripheral instance base addresses */ /** Peripheral IOMUXC base pointer */ #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) #define IOMUXC_BASE_PTR (IOMUXC) /** Array initializer of IOMUXC peripheral base adresses */ #define IOMUXC_BASE_ADDRS { IOMUXC_BASE } /** Array initializer of IOMUXC peripheral base pointers */ #define IOMUXC_BASE_PTRS { IOMUXC } #define IOMUXC_PTA6 IOMUXC_SW_MUX_CTL_PAD_PTA6_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA8 IOMUXC_SW_MUX_CTL_PAD_PTA8_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA9 IOMUXC_SW_MUX_CTL_PAD_PTA9_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA10 IOMUXC_SW_MUX_CTL_PAD_PTA10_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA11 IOMUXC_SW_MUX_CTL_PAD_PTA11_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA12 IOMUXC_SW_MUX_CTL_PAD_PTA12_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA16 IOMUXC_SW_MUX_CTL_PAD_PTA16_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA17 IOMUXC_SW_MUX_CTL_PAD_PTA17_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA18 IOMUXC_SW_MUX_CTL_PAD_PTA18_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA19 IOMUXC_SW_MUX_CTL_PAD_PTA19_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA20 IOMUXC_SW_MUX_CTL_PAD_PTA20_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA21 IOMUXC_SW_MUX_CTL_PAD_PTA21_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA22 IOMUXC_SW_MUX_CTL_PAD_PTA22_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA23 IOMUXC_SW_MUX_CTL_PAD_PTA23_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA24 IOMUXC_SW_MUX_CTL_PAD_PTA24_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA25 IOMUXC_SW_MUX_CTL_PAD_PTA25_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA26 IOMUXC_SW_MUX_CTL_PAD_PTA26_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA27 IOMUXC_SW_MUX_CTL_PAD_PTA27_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA28 IOMUXC_SW_MUX_CTL_PAD_PTA28_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA29 IOMUXC_SW_MUX_CTL_PAD_PTA29_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA30 IOMUXC_SW_MUX_CTL_PAD_PTA30_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA31 IOMUXC_SW_MUX_CTL_PAD_PTA31_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB0 IOMUXC_SW_MUX_CTL_PAD_PTB0_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB1 IOMUXC_SW_MUX_CTL_PAD_PTB1_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB2 IOMUXC_SW_MUX_CTL_PAD_PTB2_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB3 IOMUXC_SW_MUX_CTL_PAD_PTB3_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB4 IOMUXC_SW_MUX_CTL_PAD_PTB4_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB5 IOMUXC_SW_MUX_CTL_PAD_PTB5_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB6 IOMUXC_SW_MUX_CTL_PAD_PTB6_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB7 IOMUXC_SW_MUX_CTL_PAD_PTB7_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB8 IOMUXC_SW_MUX_CTL_PAD_PTB8_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB9 IOMUXC_SW_MUX_CTL_PAD_PTB9_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB10 IOMUXC_SW_MUX_CTL_PAD_PTB10_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB11 IOMUXC_SW_MUX_CTL_PAD_PTB11_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB12 IOMUXC_SW_MUX_CTL_PAD_PTB12_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB13 IOMUXC_SW_MUX_CTL_PAD_PTB13_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB14 IOMUXC_SW_MUX_CTL_PAD_PTB14_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB15 IOMUXC_SW_MUX_CTL_PAD_PTB15_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB16 IOMUXC_SW_MUX_CTL_PAD_PTB16_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB17 IOMUXC_SW_MUX_CTL_PAD_PTB17_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB18 IOMUXC_SW_MUX_CTL_PAD_PTB18_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB19 IOMUXC_SW_MUX_CTL_PAD_PTB19_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB20 IOMUXC_SW_MUX_CTL_PAD_PTB20_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB21 IOMUXC_SW_MUX_CTL_PAD_PTB21_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB22 IOMUXC_SW_MUX_CTL_PAD_PTB22_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC0 IOMUXC_SW_MUX_CTL_PAD_PTC0_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC1 IOMUXC_SW_MUX_CTL_PAD_PTC1_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC2 IOMUXC_SW_MUX_CTL_PAD_PTC2_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC3 IOMUXC_SW_MUX_CTL_PAD_PTC3_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC4 IOMUXC_SW_MUX_CTL_PAD_PTC4_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC5 IOMUXC_SW_MUX_CTL_PAD_PTC5_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC6 IOMUXC_SW_MUX_CTL_PAD_PTC6_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC7 IOMUXC_SW_MUX_CTL_PAD_PTC7_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC8 IOMUXC_SW_MUX_CTL_PAD_PTC8_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC9 IOMUXC_SW_MUX_CTL_PAD_PTC9_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC10 IOMUXC_SW_MUX_CTL_PAD_PTC10_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC11 IOMUXC_SW_MUX_CTL_PAD_PTC11_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC12 IOMUXC_SW_MUX_CTL_PAD_PTC12_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC13 IOMUXC_SW_MUX_CTL_PAD_PTC13_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC14 IOMUXC_SW_MUX_CTL_PAD_PTC14_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC15 IOMUXC_SW_MUX_CTL_PAD_PTC15_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC16 IOMUXC_SW_MUX_CTL_PAD_PTC16_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC17 IOMUXC_SW_MUX_CTL_PAD_PTC17_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD31 IOMUXC_SW_MUX_CTL_PAD_PTD31_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD30 IOMUXC_SW_MUX_CTL_PAD_PTD30_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD29 IOMUXC_SW_MUX_CTL_PAD_PTD29_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD28 IOMUXC_SW_MUX_CTL_PAD_PTD28_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD27 IOMUXC_SW_MUX_CTL_PAD_PTD27_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD26 IOMUXC_SW_MUX_CTL_PAD_PTD26_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD25 IOMUXC_SW_MUX_CTL_PAD_PTD25_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD24 IOMUXC_SW_MUX_CTL_PAD_PTD24_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD23 IOMUXC_SW_MUX_CTL_PAD_PTD23_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD22 IOMUXC_SW_MUX_CTL_PAD_PTD22_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD21 IOMUXC_SW_MUX_CTL_PAD_PTD21_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD20 IOMUXC_SW_MUX_CTL_PAD_PTD20_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD19 IOMUXC_SW_MUX_CTL_PAD_PTD19_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD18 IOMUXC_SW_MUX_CTL_PAD_PTD18_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD17 IOMUXC_SW_MUX_CTL_PAD_PTD17_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD16 IOMUXC_SW_MUX_CTL_PAD_PTD16_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD0 IOMUXC_SW_MUX_CTL_PAD_PTD0_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD1 IOMUXC_SW_MUX_CTL_PAD_PTD1_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD2 IOMUXC_SW_MUX_CTL_PAD_PTD2_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD3 IOMUXC_SW_MUX_CTL_PAD_PTD3_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD4 IOMUXC_SW_MUX_CTL_PAD_PTD4_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD5 IOMUXC_SW_MUX_CTL_PAD_PTD5_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD6 IOMUXC_SW_MUX_CTL_PAD_PTD6_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD7 IOMUXC_SW_MUX_CTL_PAD_PTD7_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD8 IOMUXC_SW_MUX_CTL_PAD_PTD8_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD9 IOMUXC_SW_MUX_CTL_PAD_PTD9_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD10 IOMUXC_SW_MUX_CTL_PAD_PTD10_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD11 IOMUXC_SW_MUX_CTL_PAD_PTD11_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD12 IOMUXC_SW_MUX_CTL_PAD_PTD12_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTD13 IOMUXC_SW_MUX_CTL_PAD_PTD13_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB23 IOMUXC_SW_MUX_CTL_PAD_PTB23_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB24 IOMUXC_SW_MUX_CTL_PAD_PTB24_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB25 IOMUXC_SW_MUX_CTL_PAD_PTB25_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB26 IOMUXC_SW_MUX_CTL_PAD_PTB26_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB27 IOMUXC_SW_MUX_CTL_PAD_PTB27_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTB28 IOMUXC_SW_MUX_CTL_PAD_PTB28_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC26 IOMUXC_SW_MUX_CTL_PAD_PTC26_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC27 IOMUXC_SW_MUX_CTL_PAD_PTC27_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC28 IOMUXC_SW_MUX_CTL_PAD_PTC28_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC29 IOMUXC_SW_MUX_CTL_PAD_PTC29_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC30 IOMUXC_SW_MUX_CTL_PAD_PTC30_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTC31 IOMUXC_SW_MUX_CTL_PAD_PTC31_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE0 IOMUXC_SW_MUX_CTL_PAD_PTE0_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE1 IOMUXC_SW_MUX_CTL_PAD_PTE1_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE2 IOMUXC_SW_MUX_CTL_PAD_PTE2_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE3 IOMUXC_SW_MUX_CTL_PAD_PTE3_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE4 IOMUXC_SW_MUX_CTL_PAD_PTE4_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE5 IOMUXC_SW_MUX_CTL_PAD_PTE5_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE6 IOMUXC_SW_MUX_CTL_PAD_PTE6_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE7 IOMUXC_SW_MUX_CTL_PAD_PTE7_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE8 IOMUXC_SW_MUX_CTL_PAD_PTE8_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE9 IOMUXC_SW_MUX_CTL_PAD_PTE9_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE10 IOMUXC_SW_MUX_CTL_PAD_PTE10_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE11 IOMUXC_SW_MUX_CTL_PAD_PTE11_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE12 IOMUXC_SW_MUX_CTL_PAD_PTE12_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE13 IOMUXC_SW_MUX_CTL_PAD_PTE13_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE14 IOMUXC_SW_MUX_CTL_PAD_PTE14_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE15 IOMUXC_SW_MUX_CTL_PAD_PTE15_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE16 IOMUXC_SW_MUX_CTL_PAD_PTE16_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE17 IOMUXC_SW_MUX_CTL_PAD_PTE17_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE18 IOMUXC_SW_MUX_CTL_PAD_PTE18_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE19 IOMUXC_SW_MUX_CTL_PAD_PTE19_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE20 IOMUXC_SW_MUX_CTL_PAD_PTE20_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE21 IOMUXC_SW_MUX_CTL_PAD_PTE21_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE22 IOMUXC_SW_MUX_CTL_PAD_PTE22_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE23 IOMUXC_SW_MUX_CTL_PAD_PTE23_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE24 IOMUXC_SW_MUX_CTL_PAD_PTE24_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE25 IOMUXC_SW_MUX_CTL_PAD_PTE25_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE26 IOMUXC_SW_MUX_CTL_PAD_PTE26_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE27 IOMUXC_SW_MUX_CTL_PAD_PTE27_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTE28 IOMUXC_SW_MUX_CTL_PAD_PTE28_REG(IOMUXC_BASE_PTR) #define IOMUXC_PTA7 IOMUXC_SW_MUX_CTL_PAD_PTA7_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A15 IOMUXC_SW_MUX_CTL_PAD_DDR_A15_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A14 IOMUXC_SW_MUX_CTL_PAD_DDR_A14_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A13 IOMUXC_SW_MUX_CTL_PAD_DDR_A13_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A12 IOMUXC_SW_MUX_CTL_PAD_DDR_A12_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A11 IOMUXC_SW_MUX_CTL_PAD_DDR_A11_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A10 IOMUXC_SW_MUX_CTL_PAD_DDR_A10_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A9 IOMUXC_SW_MUX_CTL_PAD_DDR_A9_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A8 IOMUXC_SW_MUX_CTL_PAD_DDR_A8_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A7 IOMUXC_SW_MUX_CTL_PAD_DDR_A7_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A6 IOMUXC_SW_MUX_CTL_PAD_DDR_A6_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A5 IOMUXC_SW_MUX_CTL_PAD_DDR_A5_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A4 IOMUXC_SW_MUX_CTL_PAD_DDR_A4_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A3 IOMUXC_SW_MUX_CTL_PAD_DDR_A3_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A2 IOMUXC_SW_MUX_CTL_PAD_DDR_A2_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A1 IOMUXC_SW_MUX_CTL_PAD_DDR_A1_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_A0 IOMUXC_SW_MUX_CTL_PAD_DDR_A0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_BA2 IOMUXC_SW_MUX_CTL_PAD_DDR_BA2_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_BA1 IOMUXC_SW_MUX_CTL_PAD_DDR_BA1_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_BA0 IOMUXC_SW_MUX_CTL_PAD_DDR_BA0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CAS_B IOMUXC_SW_MUX_CTL_PAD_DDR_CAS_B_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CKE0 IOMUXC_SW_MUX_CTL_PAD_DDR_CKE0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CLK0 IOMUXC_SW_MUX_CTL_PAD_DDR_CLK0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_B0 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_B0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D15 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D15_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D14 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D14_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D13 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D13_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D12 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D12_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D11 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D11_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D10 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D10_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D9 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D9_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D8 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D8_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D7 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D7_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D6 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D6_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D5 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D5_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D4 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D4_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D3 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D3_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D2 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D2_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D1 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D1_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_CS_D0 IOMUXC_SW_MUX_CTL_PAD_DDR_CS_D0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_DQM1 IOMUXC_SW_MUX_CTL_PAD_DDR_DQM1_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_DQM0 IOMUXC_SW_MUX_CTL_PAD_DDR_DQM0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_DQS1 IOMUXC_SW_MUX_CTL_PAD_DDR_DQS1_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_DQS0 IOMUXC_SW_MUX_CTL_PAD_DDR_DQS0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_RAS_B IOMUXC_SW_MUX_CTL_PAD_DDR_RAS_B_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_WE_B IOMUXC_SW_MUX_CTL_PAD_DDR_WE_B_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_ODT0 IOMUXC_SW_MUX_CTL_PAD_DDR_ODT0_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_ODT1 IOMUXC_SW_MUX_CTL_PAD_DDR_ODT1_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_DDRBYTE1 IOMUXC_SW_MUX_CTL_PAD_DDR_DDRBYTE1_REG(IOMUXC_BASE_PTR) #define IOMUXC_DDR_DDRBYTE2 IOMUXC_SW_MUX_CTL_PAD_DDR_DDRBYTE2_REG(IOMUXC_BASE_PTR) #define IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_CCM_AUD_EXT_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_CCM_ENET_EXT_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_CCM_ENET_TS_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_DSPI1_IPP_IND_SCK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_DSPI1_IPP_IND_SIN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_DSPI1_IPP_IND_SS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_MAC0_TIMER_0_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_MAC0_TIMER_0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_MAC0_TIMER_1_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_MAC0_TIMER_1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_FST_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_I2C0_IPP_SCL_IND_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_I2C0_IPP_SDA_IND_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_I2C1_IPP_SCL_IND_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_I2C1_IPP_SDA_IND_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_I2C2_IPP_SCL_IND_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_I2C2_IPP_SDA_IND_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_MLB_TOP_MLBCLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_MLB_TOP_MLBDAT_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_MLB_TOP_MLBSIG_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SRC_IPP_BOOT_CFG_18_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SRC_IPP_BOOT_CFG_18_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SRC_IPP_BOOT_CFG_19_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SRC_IPP_BOOT_CFG_19_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SRC_IPP_BOOT_CFG_20_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_SRC_IPP_BOOT_CFG_20_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT IOMUXC_SW_MUX_CTL_PAD_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_PAD(mode, speed, dse, pus, flags) \ ((IOMUXC_##mode) << IOMUXC_MUX_MODE_SHIFT | \ (IOMUXC_##speed) << IOMUXC_SPEED_SHIFT | \ (IOMUXC_##dse) << IOMUXC_DSE_SHIFT | \ (IOMUXC_##pus) << IOMUXC_PUS_SHIFT | \ (flags)) #define IOMUXC_MUX_MODE_SHIFT 20 #define IOMUXC_MUX_MODE_MASK (0x7 << 20) #define IOMUXC_MUX_MODE_ALT0 0x0 #define IOMUXC_MUX_MODE_ALT1 0x1 #define IOMUXC_MUX_MODE_ALT2 0x2 #define IOMUXC_MUX_MODE_ALT3 0x3 #define IOMUXC_MUX_MODE_ALT4 0x4 #define IOMUXC_MUX_MODE_ALT5 0x5 #define IOMUXC_MUX_MODE_ALT6 0x6 #define IOMUXC_MUX_MODE_ALT7 0x7 #define IOMUXC_SPEED_SHIFT 12 #define IOMUXC_SPEED_MASK (0x3 << 12) #define IOMUXC_SPEED_LOW 0x0 #define IOMUXC_SPEED_MEDIUM 0x1 #define IOMUXC_SPEED_HIGH 0x3 #define IOMUXC_SRE (0x1 << 11) #define IOMUXC_ODE (0x1 << 10) #define IOMUXC_HYS (0x1 << 9) #define IOMUXC_DSE_SHIFT 6 #define IOMUXC_DSE_MASK (0x7 << 6) #define IOMUXC_DSE_OFF 0x0 #define IOMUXC_DSE_150OHM 0x1 #define IOMUXC_DSE_75OHM 0x2 #define IOMUXC_DSE_50OHM 0x3 #define IOMUXC_DSE_37OHM 0x4 #define IOMUXC_DSE_30OHM 0x5 #define IOMUXC_DSE_25OHM 0x6 #define IOMUXC_DSE_20OHM 0x7 #define IOMUXC_PUS_SHIFT 4 #define IOMUXC_PUS_MASK (0x3 << 4) #define IOMUXC_PUS_PD_100KOHM 0x0 #define IOMUXC_PUS_PU_47KOHM 0x1 #define IOMUXC_PUS_PU_100KOHM 0x2 #define IOMUXC_PUS_PU_22KOHM 0x3 #define IOMUXC_PKE (0x1 << 3) #define IOMUXC_PUE (0x1 << 2) #define IOMUXC_OBE (0x1 << 1) #define IOMUXC_IBE (0x1 << 0) /* ---------------------------------------------------------------------------- -- SEMA4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer * @{ */ typedef struct { __IO uint8_t GATE03; /**< Semaphores GATE 03 Register, offset: 0x0 */ __IO uint8_t GATE02; /**< Semaphores GATE 02 Register, offset: 0x1 */ __IO uint8_t GATE01; /**< Semaphores GATE 01 Register, offset: 0x2 */ __IO uint8_t GATE00; /**< Semaphores GATE 00 Register, offset: 0x3 */ __IO uint8_t GATE07; /**< Semaphores GATE 07 Register, offset: 0x4 */ __IO uint8_t GATE06; /**< Semaphores GATE 06 Register, offset: 0x5 */ __IO uint8_t GATE05; /**< Semaphores GATE 05 Register, offset: 0x6 */ __IO uint8_t GATE04; /**< Semaphores GATE 04 Register, offset: 0x7 */ __IO uint8_t GATE11; /**< Semaphores GATE 11 Register, offset: 0x8 */ __IO uint8_t GATE10; /**< Semaphores GATE 10 Register, offset: 0x9 */ __IO uint8_t GATE09; /**< Semaphores GATE 09 Register, offset: 0xA */ __IO uint8_t GATE08; /**< Semaphores GATE 08 Register, offset: 0xB */ __IO uint8_t GATE15; /**< Semaphores GATE 15 Register, offset: 0xC */ __IO uint8_t GATE14; /**< Semaphores GATE 14 Register, offset: 0xD */ __IO uint8_t GATE13; /**< Semaphores GATE 13 Register, offset: 0xE */ __IO uint8_t GATE12; /**< Semaphores GATE 12 Register, offset: 0xF */ uint8_t RESERVED_0[48]; struct { /* offset: 0x40, array step: 0x8 */ __IO uint16_t INE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ uint8_t RESERVED_0[6]; } CPnINE[2]; uint8_t RESERVED_1[48]; struct { /* offset: 0x80, array step: 0x8 */ __IO uint16_t NTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */ uint8_t RESERVED_0[6]; } CPnNTF[2]; uint8_t RESERVED_2[112]; __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */ uint8_t RESERVED_3[2]; __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */ } SEMA4_Type, *SEMA4_MemMapPtr; /* ---------------------------------------------------------------------------- -- SEMA4 - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros * @{ */ /* SEMA4 - Register accessors */ #define SEMA4_GATE03_REG(base) ((base)->Gate03) #define SEMA4_GATE02_REG(base) ((base)->Gate02) #define SEMA4_GATE01_REG(base) ((base)->Gate01) #define SEMA4_GATE00_REG(base) ((base)->Gate00) #define SEMA4_GATE07_REG(base) ((base)->Gate07) #define SEMA4_GATE06_REG(base) ((base)->Gate06) #define SEMA4_GATE05_REG(base) ((base)->Gate05) #define SEMA4_GATE04_REG(base) ((base)->Gate04) #define SEMA4_GATE11_REG(base) ((base)->Gate11) #define SEMA4_GATE10_REG(base) ((base)->Gate10) #define SEMA4_GATE09_REG(base) ((base)->Gate09) #define SEMA4_GATE08_REG(base) ((base)->Gate08) #define SEMA4_GATE15_REG(base) ((base)->Gate15) #define SEMA4_GATE14_REG(base) ((base)->Gate14) #define SEMA4_GATE13_REG(base) ((base)->Gate13) #define SEMA4_GATE12_REG(base) ((base)->Gate12) #define SEMA4_CPINE_REG(base,index) ((base)->CPINE[index].CPINE) #define SEMA4_CPNTF_REG(base,index) ((base)->CPNTF[index].CPNTF) #define SEMA4_RSTGT_REG(base) ((base)->RSTGT) #define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) /*! * @} */ /* end of group SEMA4_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SEMA4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks * @{ */ /* Gate03 Bit Fields */ #define SEMA4_GATE03_GTFSM_MASK 0x3u #define SEMA4_GATE03_GTFSM_SHIFT 0 #define SEMA4_GATE03_GTFSM(x) (((uint8_t)(((uint8_t)(x))<HC[index]) #define ADC_HS_REG(base) ((base)->HS) #define ADC_R_REG(base,index) ((base)->R[index]) #define ADC_CFG_REG(base) ((base)->CFG) #define ADC_GC_REG(base) ((base)->GC) #define ADC_GS_REG(base) ((base)->GS) #define ADC_CV_REG(base) ((base)->CV) #define ADC_OFS_REG(base) ((base)->OFS) #define ADC_CAL_REG(base) ((base)->CAL) #define ADC_PCTL_REG(base) ((base)->PCTL) /*! * @} */ /* end of group ADC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /* HC Bit Fields */ #define ADC_HC_ADCH_MASK 0x1Fu #define ADC_HC_ADCH_SHIFT 0 #define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x))<SC) #define PDB_MOD_REG(base) ((base)->MOD) #define PDB_CNT_REG(base) ((base)->CNT) #define PDB_IDLY_REG(base) ((base)->IDLY) #define PDB_C1_REG(base,index) ((base)->CH[index].C1) #define PDB_S_REG(base,index) ((base)->CH[index].S) #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) #define PDB_INT_REG(base,index) ((base)->DAC[index].INT) /*! * @} */ /* end of group PDB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PDB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PDB_Register_Masks PDB Register Masks * @{ */ /* SC Bit Fields */ #define PDB_SC_LDOK_MASK 0x1u #define PDB_SC_LDOK_SHIFT 0 #define PDB_SC_CONT_MASK 0x2u #define PDB_SC_CONT_SHIFT 1 #define PDB_SC_MULT_MASK 0xCu #define PDB_SC_MULT_SHIFT 2 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) #define PIT_LTMR64H_REG(base) ((base)->LTMR64H) #define PIT_LTMR64L_REG(base) ((base)->LTMR64L) #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) /*! * @} */ /* end of group PIT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PIT_Register_Masks PIT Register Masks * @{ */ /* MCR Bit Fields */ #define PIT_MCR_FRZ_MASK 0x1u #define PIT_MCR_FRZ_SHIFT 0 #define PIT_MCR_MDIS_MASK 0x2u #define PIT_MCR_MDIS_SHIFT 1 /* LTMR64H Bit Fields */ #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu #define PIT_LTMR64H_LTH_SHIFT 0 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<MCR) #define CAN_CTRL1_REG(base) ((base)->CTRL1) #define CAN_TIMER_REG(base) ((base)->TIMER) #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) #define CAN_RX14MASK_REG(base) ((base)->RX14MASK) #define CAN_RX15MASK_REG(base) ((base)->RX15MASK) #define CAN_ECR_REG(base) ((base)->ECR) #define CAN_ESR1_REG(base) ((base)->ESR1) #define CAN_IMASK2_REG(base) ((base)->IMASK2) #define CAN_IMASK1_REG(base) ((base)->IMASK1) #define CAN_IFLAG2_REG(base) ((base)->IFLAG2) #define CAN_IFLAG1_REG(base) ((base)->IFLAG1) #define CAN_CTRL2_REG(base) ((base)->CTRL2) #define CAN_ESR2_REG(base) ((base)->ESR2) #define CAN_CRCR_REG(base) ((base)->CRCR) #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) #define CAN_RXFIR_REG(base) ((base)->RXFIR) #define CAN_CS_REG(base,index) ((base)->MB[index].CS) #define CAN_ID_REG(base,index) ((base)->MB[index].ID) #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) #define CAN_MECR_REG(base) ((base)->MECR) #define CAN_ERRIAR_REG(base) ((base)->ERRIAR) #define CAN_ERRIDPR_REG(base) ((base)->ERRIDPR) #define CAN_ERRIPPR_REG(base) ((base)->ERRIPPR) #define CAN_RERRAR_REG(base) ((base)->RERRAR) #define CAN_RERRDR_REG(base) ((base)->RERRDR) #define CAN_RERRSYNR_REG(base) ((base)->RERRSYNR) #define CAN_ERRSR_REG(base) ((base)->ERRSR) /*! * @} */ /* end of group CAN_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /* MCR Bit Fields */ #define CAN_MCR_MAXMB_MASK 0x7Fu #define CAN_MCR_MAXMB_SHIFT 0 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<ACCESS16BIT.DATAL) #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) #define CRC_DATA_REG(base) ((base)->DATA) #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) #define CRC_GPOLY_REG(base) ((base)->GPOLY) #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) #define CRC_CTRL_REG(base) ((base)->CTRL) #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) /*! * @} */ /* end of group CRC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CRC Register Masks ---------------------------------------------------------------------------- */ /* ---------------------------------------------------------------------------- -- CSU ---------------------------------------------------------------------------- */ /*! * @addtogroup CSU_Peripheral CSU * @{ */ /** CSU - Peripheral register structure */ typedef struct CSU_MemMap { uint32_t CSL[64]; /**< Config Security Level, array offset: 0x0, array step: 0x4 */ uint8_t RESERVED_0[256]; uint32_t HP[2]; /**< Hprot Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_1[16]; uint32_t SA[2]; /**< Secure Access register, array offset: 0x218, array step: 0x4 */ uint8_t RESERVED_2[16]; uint32_t AMK[1]; /**< Alarm Mask register, array offset: 0x230, array step: 0x4 */ uint8_t RESERVED_3[16]; uint32_t AROUT[13]; /**< Alarm Routing Register, array offset: 0x244, array step: 0x4 */ uint8_t RESERVED_4[204]; uint8_t ASOFT; /**< Soft Alarm Register, offset: 0x344 */ uint8_t RESERVED_5[3]; uint16_t ACOUNTER; /**< Alarm Counter Register, offset: 0x348 */ uint8_t RESERVED_6[2]; uint16_t ACONTROL; /**< Alarm Control Register, offset: 0x34C */ uint8_t RESERVED_7[10]; uint32_t HPC[2]; /**< Hprot Control Register, array offset: 0x358, array step: 0x4 */ uint8_t RESERVED_8[24]; uint32_t ISR[1]; /**< Interrupt Status Register, array offset: 0x378, array step: 0x4 */ } volatile *CSU_MemMapPtr; /* ---------------------------------------------------------------------------- -- CSU - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup CSU_Register_Accessor_Macros CSU - Register accessor macros * @{ */ /* CSU - Register accessors */ #define CSU_CSL_REG(base,index) ((base)->CSL[index]) #define CSU_HP_REG(base,index) ((base)->HP[index]) #define CSU_SA_REG(base,index) ((base)->SA[index]) #define CSU_AMK_REG(base,index) ((base)->AMK[index]) #define CSU_AROUT_REG(base,index) ((base)->AROUT[index]) #define CSU_ASOFT_REG(base) ((base)->ASOFT) #define CSU_ACOUNTER_REG(base) ((base)->ACOUNTER) #define CSU_ACONTROL_REG(base) ((base)->ACONTROL) #define CSU_HPC_REG(base,index) ((base)->HPC[index]) #define CSU_ISR_REG(base,index) ((base)->ISR[index]) /*! * @} */ /* end of group CSU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CSU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CSU_Register_Masks CSU Register Masks * @{ */ /* CSL Bit Fields */ #define CSU_CSL_CSL_2n_MASK 0xFFu #define CSU_CSL_CSL_2n_SHIFT 0 #define CSU_CSL_CSL_2n(x) (((uint32_t)(((uint32_t)(x))<DAT16[index2]) #define DAC_DAT_REG(base,index2) ((base)->DAT[index2]) #define DAC_STATCTRL_REG(base) ((base)->STATCTRL) /*! * @} */ /* end of group DAC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DAC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Register_Masks DAC Register Masks * @{ */ /* DAT16 Bit Fields */ #define DAC_DAT16_DATA_MASK 0xFFFu #define DAC_DAT16_DATA_SHIFT 0 #define DAC_DAT16_DATA(x) (((uint16_t)(((uint16_t)(x))<CR) #define DMA_ES_REG(base) ((base)->ES) #define DMA_ERQ_REG(base) ((base)->ERQ) #define DMA_EEI_REG(base) ((base)->EEI) #define DMA_CEEI_REG(base) ((base)->CEEI) #define DMA_SEEI_REG(base) ((base)->SEEI) #define DMA_CERQ_REG(base) ((base)->CERQ) #define DMA_SERQ_REG(base) ((base)->SERQ) #define DMA_CDNE_REG(base) ((base)->CDNE) #define DMA_SSRT_REG(base) ((base)->SSRT) #define DMA_CERR_REG(base) ((base)->CERR) #define DMA_CINT_REG(base) ((base)->CINT) #define DMA_INT_REG(base) ((base)->INT) #define DMA_ERR_REG(base) ((base)->ERR) #define DMA_HRS_REG(base) ((base)->HRS) #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) #define DMA_DCHPRI19_REG(base) ((base)->DCHPRI19) #define DMA_DCHPRI18_REG(base) ((base)->DCHPRI18) #define DMA_DCHPRI17_REG(base) ((base)->DCHPRI17) #define DMA_DCHPRI16_REG(base) ((base)->DCHPRI16) #define DMA_DCHPRI23_REG(base) ((base)->DCHPRI23) #define DMA_DCHPRI22_REG(base) ((base)->DCHPRI22) #define DMA_DCHPRI21_REG(base) ((base)->DCHPRI21) #define DMA_DCHPRI20_REG(base) ((base)->DCHPRI20) #define DMA_DCHPRI27_REG(base) ((base)->DCHPRI27) #define DMA_DCHPRI26_REG(base) ((base)->DCHPRI26) #define DMA_DCHPRI25_REG(base) ((base)->DCHPRI25) #define DMA_DCHPRI24_REG(base) ((base)->DCHPRI24) #define DMA_DCHPRI31_REG(base) ((base)->DCHPRI31) #define DMA_DCHPRI30_REG(base) ((base)->DCHPRI30) #define DMA_DCHPRI29_REG(base) ((base)->DCHPRI29) #define DMA_DCHPRI28_REG(base) ((base)->DCHPRI28) #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) /*! * @} */ /* end of group DMA_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /* CR Bit Fields */ #define DMA_CR_EDBG_MASK 0x2u #define DMA_CR_EDBG_SHIFT 1 #define DMA_CR_ERCA_MASK 0x4u #define DMA_CR_ERCA_SHIFT 2 #define DMA_CR_ERGA_MASK 0x8u #define DMA_CR_ERGA_SHIFT 3 #define DMA_CR_HOE_MASK 0x10u #define DMA_CR_HOE_SHIFT 4 #define DMA_CR_HALT_MASK 0x20u #define DMA_CR_HALT_SHIFT 5 #define DMA_CR_CLM_MASK 0x40u #define DMA_CR_CLM_SHIFT 6 #define DMA_CR_EMLM_MASK 0x80u #define DMA_CR_EMLM_SHIFT 7 #define DMA_CR_GRP0PRI_MASK 0x100u #define DMA_CR_GRP0PRI_SHIFT 8 #define DMA_CR_GRP1PRI_MASK 0x400u #define DMA_CR_GRP1PRI_SHIFT 10 #define DMA_CR_ECX_MASK 0x10000u #define DMA_CR_ECX_SHIFT 16 #define DMA_CR_CX_MASK 0x20000u #define DMA_CR_CX_SHIFT 17 /* ES Bit Fields */ #define DMA_ES_DBE_MASK 0x1u #define DMA_ES_DBE_SHIFT 0 #define DMA_ES_SBE_MASK 0x2u #define DMA_ES_SBE_SHIFT 1 #define DMA_ES_SGE_MASK 0x4u #define DMA_ES_SGE_SHIFT 2 #define DMA_ES_NCE_MASK 0x8u #define DMA_ES_NCE_SHIFT 3 #define DMA_ES_DOE_MASK 0x10u #define DMA_ES_DOE_SHIFT 4 #define DMA_ES_DAE_MASK 0x20u #define DMA_ES_DAE_SHIFT 5 #define DMA_ES_SOE_MASK 0x40u #define DMA_ES_SOE_SHIFT 6 #define DMA_ES_SAE_MASK 0x80u #define DMA_ES_SAE_SHIFT 7 #define DMA_ES_ERRCHN_MASK 0x1F00u #define DMA_ES_ERRCHN_SHIFT 8 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) /*! * @} */ /* end of group DMAMUX_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks * @{ */ /* CHCFG Bit Fields */ #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu #define DMAMUX_CHCFG_SOURCE_SHIFT 0 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<SC) #define FTM_CNT_REG(base) ((base)->CNT) #define FTM_MOD_REG(base) ((base)->MOD) #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) #define FTM_CNTIN_REG(base) ((base)->CNTIN) #define FTM_STATUS_REG(base) ((base)->STATUS) #define FTM_MODE_REG(base) ((base)->MODE) #define FTM_SYNC_REG(base) ((base)->SYNC) #define FTM_OUTINIT_REG(base) ((base)->OUTINIT) #define FTM_OUTMASK_REG(base) ((base)->OUTMASK) #define FTM_COMBINE_REG(base) ((base)->COMBINE) #define FTM_DEADTIME_REG(base) ((base)->DEADTIME) #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) #define FTM_POL_REG(base) ((base)->POL) #define FTM_FMS_REG(base) ((base)->FMS) #define FTM_FILTER_REG(base) ((base)->FILTER) #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) #define FTM_QDCTRL_REG(base) ((base)->QDCTRL) #define FTM_CONF_REG(base) ((base)->CONF) #define FTM_FLTPOL_REG(base) ((base)->FLTPOL) #define FTM_SYNCONF_REG(base) ((base)->SYNCONF) #define FTM_INVCTRL_REG(base) ((base)->INVCTRL) #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) /*! * @} */ /* end of group FTM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FTM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Register_Masks FTM Register Masks * @{ */ /* SC Bit Fields */ #define FTM_SC_PS_MASK 0x7u #define FTM_SC_PS_SHIFT 0 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<IBAD) #define I2C_IBFD_REG(base) ((base)->IBFD) #define I2C_IBCR_REG(base) ((base)->IBCR) #define I2C_IBSR_REG(base) ((base)->IBSR) #define I2C_IBDR_REG(base) ((base)->IBDR) #define I2C_IBIC_REG(base) ((base)->IBIC) #define I2C_IBDBG_REG(base) ((base)->IBDBG) /*! * @} */ /* end of group I2C_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Masks I2C Register Masks * @{ */ /* IBAD Bit Fields */ #define I2C_IBAD_ADR_MASK 0xFEu #define I2C_IBAD_ADR_SHIFT 1 #define I2C_IBAD_ADR(x) (((uint8_t)(((uint8_t)(x))<CSR) #define LPTMR_PSR_REG(base) ((base)->PSR) #define LPTMR_CMR_REG(base) ((base)->CMR) #define LPTMR_CNR_REG(base) ((base)->CNR) /*! * @} */ /* end of group LPTMR_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /* CSR Bit Fields */ #define LPTMR_CSR_TEN_MASK 0x1u #define LPTMR_CSR_TEN_SHIFT 0 #define LPTMR_CSR_TMS_MASK 0x2u #define LPTMR_CSR_TMS_SHIFT 1 #define LPTMR_CSR_TFC_MASK 0x4u #define LPTMR_CSR_TFC_SHIFT 2 #define LPTMR_CSR_TPP_MASK 0x8u #define LPTMR_CSR_TPP_SHIFT 3 #define LPTMR_CSR_TPS_MASK 0x30u #define LPTMR_CSR_TPS_SHIFT 4 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<PLASC) #define MCM_PLAMC_REG(base) ((base)->PLAMC) #define MCM_CR_REG(base) ((base)->CR) #define MCM_ISCR_REG(base) ((base)->ISCR) #define MCM_FADR_REG(base) ((base)->FADR) #define MCM_FATR_REG(base) ((base)->FATR) #define MCM_FDR_REG(base) ((base)->FDR) /*! * @} */ /* end of group MCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /* PLASC Bit Fields */ #define MCM_PLASC_ASC_MASK 0xFFu #define MCM_PLASC_ASC_SHIFT 0 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CPxTYPE) #define MSCM_CPxNUM_REG(base) ((base)->CPxNUM) #define MSCM_CPxMASTER_REG(base) ((base)->CPxMASTER) #define MSCM_CPxCOUNT_REG(base) ((base)->CPxCOUNT) #define MSCM_CPxCFG_REG(base,index) ((base)->CPxCFG[index]) #define MSCM_CP0TYPE_REG(base) ((base)->CP0TYPE) #define MSCM_CP0NUM_REG(base) ((base)->CP0NUM) #define MSCM_CP0MASTER_REG(base) ((base)->CP0MASTER) #define MSCM_CP0COUNT_REG(base) ((base)->CP0COUNT) #define MSCM_CP0CFG_REG(base,index) ((base)->CP0CFG[index]) #define MSCM_CP1TYPE_REG(base) ((base)->CP1TYPE) #define MSCM_CP1NUM_REG(base) ((base)->CP1NUM) #define MSCM_CP1MASTER_REG(base) ((base)->CP1MASTER) #define MSCM_CP1COUNT_REG(base) ((base)->CP1COUNT) #define MSCM_CP1CFG_REG(base,index) ((base)->CP1CFG[index]) #define MSCM_IRCP0IR_REG(base) ((base)->IRCP0IR) #define MSCM_IRCP1IR_REG(base) ((base)->IRCP1IR) #define MSCM_IRCPGIR_REG(base) ((base)->IRCPGIR) #define MSCM_IRSPRC_REG(base,index) ((base)->IRSPRC[index]) #define MSCM_TZENR_REG(base) ((base)->TZENR) #define MSCM_TZIR_REG(base) ((base)->TZIR) #define MSCM_CSLIER_REG(base) ((base)->CSLIER) #define MSCM_CSLIR_REG(base) ((base)->CSLIR) #define MSCM_CSOVR_REG(base) ((base)->CSOVR) #define MSCM_CSFAR_REG(base,index) ((base)->CSFCAP[index].CSFAR) #define MSCM_CSFCR_REG(base,index) ((base)->CSFCAP[index].CSFCR) #define MSCM_CSFIR_REG(base,index) ((base)->CSFCAP[index].CSFIR) /*! * @} */ /* end of group MSCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MSCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MSCM_Register_Masks MSCM Register Masks * @{ */ /* CPxTYPE Bit Fields */ #define MSCM_CPxTYPE_rYpZ_MASK 0xFFu #define MSCM_CPxTYPE_rYpZ_SHIFT 0 #define MSCM_CPxTYPE_rYpZ(x) (((uint32_t)(((uint32_t)(x))<PCR[index]) #define PORT_ISFR_REG(base) ((base)->ISFR) #define PORT_DFER_REG(base) ((base)->DFER) #define PORT_DFCR_REG(base) ((base)->DFCR) #define PORT_DFWR_REG(base) ((base)->DFWR) /*! * @} */ /* end of group PORT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /* PCR Bit Fields */ #define PORT_PCR_IRQC_MASK 0xF0000u #define PORT_PCR_IRQC_SHIFT 16 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<MCR) #define SPI_TCR_REG(base) ((base)->TCR) #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) #define SPI_SR_REG(base) ((base)->SR) #define SPI_RSER_REG(base) ((base)->RSER) #define SPI_PUSHR_REG(base) ((base)->PUSHR) #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) #define SPI_POPR_REG(base) ((base)->POPR) #define SPI_TXFR_REG(base,index) ((base)->TXFR[index]) #define SPI_RXFR_REG(base,index) ((base)->RXFR[index]) /*! * @} */ /* end of group SPI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPI_Register_Masks SPI Register Masks * @{ */ /* MCR Bit Fields */ #define SPI_MCR_HALT_MASK 0x1u #define SPI_MCR_HALT_SHIFT 0 #define SPI_MCR_PES_MASK 0x2u #define SPI_MCR_PES_SHIFT 1 #define SPI_MCR_FCPCS_MASK 0x4u #define SPI_MCR_FCPCS_SHIFT 2 #define SPI_MCR_SMPL_PT_MASK 0x300u #define SPI_MCR_SMPL_PT_SHIFT 8 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<CSR) #define SysTick_RVR_REG(base) ((base)->RVR) #define SysTick_CVR_REG(base) ((base)->CVR) #define SysTick_CALIB_REG(base) ((base)->CALIB) /*! * @} */ /* end of group SysTick_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SysTick Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SysTick_Register_Masks SysTick Register Masks * @{ */ /* CSR Bit Fields */ #define SysTick_CSR_ENABLE_MASK 0x1u #define SysTick_CSR_ENABLE_SHIFT 0 #define SysTick_CSR_TICKINT_MASK 0x2u #define SysTick_CSR_TICKINT_SHIFT 1 #define SysTick_CSR_CLKSOURCE_MASK 0x4u #define SysTick_CSR_CLKSOURCE_SHIFT 2 #define SysTick_CSR_COUNTFLAG_MASK 0x10000u #define SysTick_CSR_COUNTFLAG_SHIFT 16 /* RVR Bit Fields */ #define SysTick_RVR_RELOAD_MASK 0xFFFFFFu #define SysTick_RVR_RELOAD_SHIFT 0 #define SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<WCR) #define WDOG_WSR_REG(base) ((base)->WSR) #define WDOG_WRSR_REG(base) ((base)->WRSR) #define WDOG_WICR_REG(base) ((base)->WICR) #define WDOG_WMCR_REG(base) ((base)->WMCR) /*! * @} */ /* end of group WDOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /* WCR Bit Fields */ #define WDOG_WCR_WDZST_MASK 0x1u #define WDOG_WCR_WDZST_SHIFT 0 #define WDOG_WCR_WDBG_MASK 0x2u #define WDOG_WCR_WDBG_SHIFT 1 #define WDOG_WCR_WDE_MASK 0x4u #define WDOG_WCR_WDE_SHIFT 2 #define WDOG_WCR_WDT_MASK 0x8u #define WDOG_WCR_WDT_SHIFT 3 #define WDOG_WCR_SRS_MASK 0x10u #define WDOG_WCR_SRS_SHIFT 4 #define WDOG_WCR_WDA_MASK 0x20u #define WDOG_WCR_WDA_SHIFT 5 #define WDOG_WCR_SRE_MASK 0x40u #define WDOG_WCR_SRE_SHIFT 6 #define WDOG_WCR_WDW_MASK 0x80u #define WDOG_WCR_WDW_SHIFT 7 #define WDOG_WCR_WT_MASK 0xFF00u #define WDOG_WCR_WT_SHIFT 8 #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<