From 6be00a6dd5032d7330d761a33f5b027658bab140 Mon Sep 17 00:00:00 2001 From: Dominik Sliwa Date: Fri, 23 Mar 2018 12:50:30 +0100 Subject: style and -wall fixes Signed-off-by: Dominik Sliwa --- drivers/fsl_dspi.c | 10 +- source/adc_task.c | 108 ++++++++------- source/adc_task.h | 4 +- source/apalis-tk1-k20-api.h | 123 +++++++++++++++++ source/can_task.c | 326 ++++++++++++++++---------------------------- source/can_task.h | 8 +- source/com_task.c | 34 ++--- source/com_task.h | 134 +----------------- source/main.c | 11 +- 9 files changed, 337 insertions(+), 421 deletions(-) create mode 100644 source/apalis-tk1-k20-api.h diff --git a/drivers/fsl_dspi.c b/drivers/fsl_dspi.c index cacb52a..66f8974 100644 --- a/drivers/fsl_dspi.c +++ b/drivers/fsl_dspi.c @@ -1482,11 +1482,8 @@ void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle) /* Receive buffer is not null, store data into it */ *handle->rxData = dataReceived; ++handle->rxData; - } - /* Decrease remaining receive byte count */ - --handle->remainingReceiveByteCount; - if (handle->remainingSendByteCount == 0 && handle->rxData){ + if (handle->remainingSendByteCount == 0){ if ( *(handle->rxData - 2) == APALIS_TK1_K20_READ_INST) { base->PUSHR_SLAVE = registers[dataReceived]; @@ -1509,6 +1506,11 @@ void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle) base->PUSHR_SLAVE = 0x55; } } + } + + /* Decrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + if (handle->remainingSendByteCount > 0) { if (handle->txData) diff --git a/source/adc_task.c b/source/adc_task.c index 3bb4714..56a46c1 100644 --- a/source/adc_task.c +++ b/source/adc_task.c @@ -10,6 +10,14 @@ #include "errno.h" #include "stdlib.h" +struct adc_data { + uint16_t adc[ADC0_CHANNEL_CNT]; + uint16_t tsc_xm; + uint16_t tsc_xp; + uint16_t tsc_ym; + uint16_t tsc_yp; +} adc_data; + /* * Apalis ADC0 -> PTB0 -> ADC0_SE8 * Apalis ADC1 -> PTB1 -> ADC0_SE9 @@ -110,9 +118,9 @@ void adc_task(void *pvParameters) while(1) { for (i = 0; i < ADC0_CHANNEL_CNT;i ++){ channel.channelNumber = adc0_channels[i]; - gen_regs.adc[i] = do_adc_conversion(ADC0, &channel); - registers[APALIS_TK1_K20_ADC_CH0L + 2 * i] = gen_regs.adc[i] & 0xFF; - registers[APALIS_TK1_K20_ADC_CH0L + 2 * i + 1] = (gen_regs.adc[i] >> 8) & 0xFF; + adc_data.adc[i] = do_adc_conversion(ADC0, &channel); + registers[APALIS_TK1_K20_ADC_CH0L + 2 * i] = adc_data.adc[i] & 0xFF; + registers[APALIS_TK1_K20_ADC_CH0L + 2 * i + 1] = (adc_data.adc[i] >> 8) & 0xFF; } vTaskDelay(5); } @@ -176,37 +184,35 @@ void tsc_task(void *pvParameters) ts_force_drive(0, 0, 1, 1); vTaskDelay(10); channel.channelNumber = tsc_channels[0]; - gen_regs.tsc_ym = do_adc_conversion(ADC1, &channel); + adc_data.tsc_ym = do_adc_conversion(ADC1, &channel); //probe yp with power across Y plane channel.channelNumber = tsc_channels[1]; - gen_regs.tsc_yp = do_adc_conversion(ADC1, &channel); + adc_data.tsc_yp = do_adc_conversion(ADC1, &channel); //probe xm with power across X plane ts_force_drive(1, 1, 0, 0); vTaskDelay(10); channel.channelNumber = tsc_channels[2]; - gen_regs.tsc_xm = do_adc_conversion(ADC1, &channel); + adc_data.tsc_xm = do_adc_conversion(ADC1, &channel); //probe xp with power across X plane channel.channelNumber = tsc_channels[3]; - gen_regs.tsc_xp = do_adc_conversion(ADC1, &channel); + adc_data.tsc_xp = do_adc_conversion(ADC1, &channel); - if (irq_stat == 0) { - generate_irq(APALIS_TK1_K20_TSC_IRQ); - irq_stat = 1; - } } else { - gen_regs.tsc_xm = 0; - gen_regs.tsc_xp = 0; - gen_regs.tsc_ym = 0; - gen_regs.tsc_yp = 0; + adc_data.tsc_xm = 0; + adc_data.tsc_xp = 0; + adc_data.tsc_ym = 0; + adc_data.tsc_yp = 0; vTaskDelay(20); - if (irq_stat == 0) { - generate_irq(APALIS_TK1_K20_TSC_IRQ); - irq_stat = 1; - } } + + if (irq_stat == 0) { + generate_irq(APALIS_TK1_K20_TSC_IRQ); + irq_stat = 1; + } + vTaskDelay(10); } @@ -227,33 +233,33 @@ int tsc_registers(dspi_transfer_t *spi_transfer) } else if (rx_buf[0] == APALIS_TK1_K20_BULK_READ_INST) { if (rx_buf[1] == APALIS_TK1_K20_TSC_XML) { if (rx_buf[1] == 2) { - tx_buf[0] = gen_regs.tsc_xm & 0xFF; - tx_buf[1] = (gen_regs.tsc_xm >> 8) & 0xFF; + tx_buf[0] = adc_data.tsc_xm & 0xFF; + tx_buf[1] = (adc_data.tsc_xm >> 8) & 0xFF; return 2; } else if (rx_buf[1] == 8) { - tx_buf[0] = gen_regs.tsc_xm & 0xFF; - tx_buf[1] = (gen_regs.tsc_xm >> 8) & 0xFF; - tx_buf[2] = gen_regs.tsc_xp & 0xFF; - tx_buf[3] = (gen_regs.tsc_xp >> 8) & 0xFF; - tx_buf[4] = gen_regs.tsc_ym & 0xFF; - tx_buf[5] = (gen_regs.tsc_ym >> 8) & 0xFF; - tx_buf[6] = gen_regs.tsc_yp & 0xFF; - tx_buf[7] = (gen_regs.tsc_yp >> 8) & 0xFF; + tx_buf[0] = adc_data.tsc_xm & 0xFF; + tx_buf[1] = (adc_data.tsc_xm >> 8) & 0xFF; + tx_buf[2] = adc_data.tsc_xp & 0xFF; + tx_buf[3] = (adc_data.tsc_xp >> 8) & 0xFF; + tx_buf[4] = adc_data.tsc_ym & 0xFF; + tx_buf[5] = (adc_data.tsc_ym >> 8) & 0xFF; + tx_buf[6] = adc_data.tsc_yp & 0xFF; + tx_buf[7] = (adc_data.tsc_yp >> 8) & 0xFF; return 8; } } switch (rx_buf[1]) { case APALIS_TK1_K20_TSC_XPL: - tx_buf[0] = gen_regs.tsc_xp & 0xFF; - tx_buf[1] = (gen_regs.tsc_xp >> 8) & 0xFF; + tx_buf[0] = adc_data.tsc_xp & 0xFF; + tx_buf[1] = (adc_data.tsc_xp >> 8) & 0xFF; return 2; case APALIS_TK1_K20_TSC_YML: - tx_buf[0] = gen_regs.tsc_ym & 0xFF; - tx_buf[1] = (gen_regs.tsc_ym >> 8) & 0xFF; + tx_buf[0] = adc_data.tsc_ym & 0xFF; + tx_buf[1] = (adc_data.tsc_ym >> 8) & 0xFF; return 2; case APALIS_TK1_K20_TSC_YPL: - tx_buf[0] = gen_regs.tsc_yp & 0xFF; - tx_buf[1] = (gen_regs.tsc_yp >> 8) & 0xFF; + tx_buf[0] = adc_data.tsc_yp & 0xFF; + tx_buf[1] = (adc_data.tsc_yp >> 8) & 0xFF; return 2; default: return -ENOENT; @@ -277,33 +283,33 @@ int adc_registers(dspi_transfer_t *spi_transfer) } else if (rx_buf[0] == APALIS_TK1_K20_BULK_READ_INST) { if (rx_buf[1] == APALIS_TK1_K20_ADC_CH0L) { if (rx_buf[2] == 2) { - tx_buf[0] = gen_regs.adc[0] & 0xFF; - tx_buf[1] = (gen_regs.adc[0] >> 8) & 0xFF; + tx_buf[0] = adc_data.adc[0] & 0xFF; + tx_buf[1] = (adc_data.adc[0] >> 8) & 0xFF; return 2; } else if (rx_buf[2] == 8) { - tx_buf[0] = gen_regs.adc[0] & 0xFF; - tx_buf[1] = (gen_regs.adc[0] >> 8) & 0xFF; - tx_buf[2] = gen_regs.adc[1] & 0xFF; - tx_buf[3] = (gen_regs.adc[1] >> 8) & 0xFF; - tx_buf[4] = gen_regs.adc[2] & 0xFF; - tx_buf[5] = (gen_regs.adc[2] >> 8) & 0xFF; - tx_buf[6] = gen_regs.adc[3] & 0xFF; - tx_buf[7] = (gen_regs.adc[3] >> 8) & 0xFF; + tx_buf[0] = adc_data.adc[0] & 0xFF; + tx_buf[1] = (adc_data.adc[0] >> 8) & 0xFF; + tx_buf[2] = adc_data.adc[1] & 0xFF; + tx_buf[3] = (adc_data.adc[1] >> 8) & 0xFF; + tx_buf[4] = adc_data.adc[2] & 0xFF; + tx_buf[5] = (adc_data.adc[2] >> 8) & 0xFF; + tx_buf[6] = adc_data.adc[3] & 0xFF; + tx_buf[7] = (adc_data.adc[3] >> 8) & 0xFF; return 8; } } switch (rx_buf[1]){ case APALIS_TK1_K20_ADC_CH1L: - tx_buf[0] = gen_regs.adc[1] & 0xFF; - tx_buf[1] = (gen_regs.adc[1] >> 8) & 0xFF; + tx_buf[0] = adc_data.adc[1] & 0xFF; + tx_buf[1] = (adc_data.adc[1] >> 8) & 0xFF; return 2; case APALIS_TK1_K20_ADC_CH2L: - tx_buf[0] = gen_regs.adc[2] & 0xFF; - tx_buf[1] = (gen_regs.adc[2] >> 8) & 0xFF; + tx_buf[0] = adc_data.adc[2] & 0xFF; + tx_buf[1] = (adc_data.adc[2] >> 8) & 0xFF; return 2; case APALIS_TK1_K20_ADC_CH3L: - tx_buf[0] = gen_regs.adc[3] & 0xFF; - tx_buf[1] = (gen_regs.adc[3] >> 8) & 0xFF; + tx_buf[0] = adc_data.adc[3] & 0xFF; + tx_buf[1] = (adc_data.adc[3] >> 8) & 0xFF; return 2; default: diff --git a/source/adc_task.h b/source/adc_task.h index 101bffd..98a25aa 100644 --- a/source/adc_task.h +++ b/source/adc_task.h @@ -9,8 +9,8 @@ #include "fsl_dspi.h" #ifdef BOARD_USES_ADC -TaskHandle_t adc_task_handle; -TaskHandle_t tsc_task_handle; +extern TaskHandle_t adc_task_handle; +extern TaskHandle_t tsc_task_handle; void adc_task(void *pvParameters); void tsc_task(void *pvParameters); int adc_registers(dspi_transfer_t *spi_transfer); diff --git a/source/apalis-tk1-k20-api.h b/source/apalis-tk1-k20-api.h new file mode 100644 index 0000000..85bbf9f --- /dev/null +++ b/source/apalis-tk1-k20-api.h @@ -0,0 +1,123 @@ +/* + * Copyright 2016-2017 Toradex AG + * Dominik Sliwa + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#ifndef __LINUX_MFD_APALIS_TK1_K20_API_H +#define __LINUX_MFD_APALIS_TK1_K20_API_H + +/* Commands and registers used in SPI communication */ + +/* Commands*/ +#define APALIS_TK1_K20_READ_INST 0x0F +#define APALIS_TK1_K20_WRITE_INST 0xF0 +#define APALIS_TK1_K20_BULK_WRITE_INST 0x3C +#define APALIS_TK1_K20_BULK_READ_INST 0xC3 + +#define APALIS_TK1_K20_MAX_BULK 250u +#define APALIS_TK1_K20_HEADER 4u + +/* General registers*/ +#define APALIS_TK1_K20_STAREG 0x00 /* general status register RO */ +#define APALIS_TK1_K20_REVREG 0x01 /* FW revision register RO*/ +#define APALIS_TK1_K20_IRQREG 0x02 /* IRQ status RO(reset of read) */ +#define APALIS_TK1_K20_CTRREG 0x03 /* general control register RW */ +#define APALIS_TK1_K20_MSQREG 0x04 /* IRQ mask register RW */ + +/* 0x05-0x0F Reserved */ + +/* CAN Registers */ +#define APALIS_TK1_K20_CANREG 0x10 /* CAN0 control & status register RW */ +#define APALIS_TK1_K20_CANREG_CLR 0x11 /* CAN0 CANREG clear register WO */ +#define APALIS_TK1_K20_CANERR 0x12 /* CAN0 error register RW */ +#define APALIS_TK1_K20_CAN_BAUD_REG 0x13 /* CAN0 baud set register RW */ +#define APALIS_TK1_K20_CAN_BIT_1 0x14 /* CAN0 bit timing register 1 RW */ +#define APALIS_TK1_K20_CAN_BIT_2 0x15 /* CAN0 bit timing register 2 RW */ +#define APALIS_TK1_K20_CAN_IN_BUF_CNT 0x16 /* CAN0 IN received data count RO */ +#define APALIS_TK1_K20_CAN_IN_BUF 0x17 /* CAN0 IN RO */ +/* buffer size is 13 bytes */ +#define APALIS_TK1_K20_CAN_IN_BUF_END 0x23 /* CAN0 IN RO */ +#define APALIS_TK1_K20_CAN_OUT_BUF 0x24 /* CAN0 OUT WO */ +/* buffer size is 13 bytes */ +#define APALIS_TK1_K20_CAN_OUT_BUF_END (APALIS_TK1_K20_CAN_OUT_BUF + 13 - 1)/* CAN OUT BUF END */ +#define APALIS_TK1_K20_CAN_OFFSET 0x30 +#define APALIS_TK1_K20_CAN_DEV_OFFSET(x) (x ? APALIS_TK1_K20_CAN_OFFSET : 0) + +/* 0x30-0x3F Reserved */ +/* 0x40-0x62 CAN1 registers same layout as CAN0*/ +/* 0x63-0x6F Reserved */ + +/* ADC Registers */ +#define APALIS_TK1_K20_ADCREG 0x70 /* ADC control & status register RW */ +#define APALIS_TK1_K20_ADC_CH0L 0x71 /* ADC Channel 0 LSB RO */ +#define APALIS_TK1_K20_ADC_CH0H 0x72 /* ADC Channel 0 MSB RO */ +#define APALIS_TK1_K20_ADC_CH1L 0x73 /* ADC Channel 1 LSB RO */ +#define APALIS_TK1_K20_ADC_CH1H 0x74 /* ADC Channel 1 MSB RO */ +#define APALIS_TK1_K20_ADC_CH2L 0x75 /* ADC Channel 2 LSB RO */ +#define APALIS_TK1_K20_ADC_CH2H 0x76 /* ADC Channel 2 MSB RO */ +#define APALIS_TK1_K20_ADC_CH3L 0x77 /* ADC Channel 3 LSB RO */ +#define APALIS_TK1_K20_ADC_CH3H 0x78 /* ADC Channel 3 MSB RO */ +/* Bulk read of LSB register can be use to read entire 16-bit in one command */ +/* Bulk read of APALIS_TK1_K20_ADC_CH0L register can be use to read all + * ADC channels in one command */ + +/* 0x79-0x7F reserved */ + +/* TSC Register */ +#define APALIS_TK1_K20_TSCREG 0x80 /* TSC control & status register RW */ +#define APALIS_TK1_K20_TSC_XML 0x81 /* TSC X- data LSB RO */ +#define APALIS_TK1_K20_TSC_XMH 0x82 /* TSC X- data MSB RO */ +#define APALIS_TK1_K20_TSC_XPL 0x83 /* TSC X+ data LSB RO */ +#define APALIS_TK1_K20_TSC_XPH 0x84 /* TSC X+ data MSB RO */ +#define APALIS_TK1_K20_TSC_YML 0x85 /* TSC Y- data LSB RO */ +#define APALIS_TK1_K20_TSC_YMH 0x86 /* TSC Y- data MSB RO */ +#define APALIS_TK1_K20_TSC_YPL 0x87 /* TSC Y+ data LSB RO */ +#define APALIS_TK1_K20_TSC_YPH 0x88 /* TSC Y+ data MSB RO */ +/* Bulk read of LSB register can be use to read entire 16-bit in one command */ +#define APALIS_TK1_K20_TSC_ENA BIT(0) +#define APALIS_TK1_K20_TSC_ENA_MASK BIT(0) + +/* 0x89-0x8F Reserved */ + +/* GPIO Registers */ +#define APALIS_TK1_K20_GPIOREG 0x90 /* GPIO control & status register RW */ +#define APALIS_TK1_K20_GPIO_NO 0x91 /* currently configured GPIO RW */ +#define APALIS_TK1_K20_GPIO_STA 0x92 /* Status register for the APALIS_TK1_K20_GPIO_NO GPIO RW */ +/* MSB | 0 ... 0 | VALUE | Output-1 / Input-0 | LSB */ +#define APALIS_TK1_K20_GPIO_STA_OE BIT(0) +#define APALIS_TK1_K20_GPIO_STA_VAL BIT(1) + +/* 0x93-0xFC Reserved */ +#define APALIS_TK1_K20_LAST_REG 0xFD +#define APALIS_TK1_K20_RET_REQ 0xFE +/* 0xFF Reserved */ + +/* Interrupt flags */ +#define APALIS_TK1_K20_GEN_IRQ 0 +#define APALIS_TK1_K20_CAN0_IRQ 1 +#define APALIS_TK1_K20_CAN1_IRQ 2 +#define APALIS_TK1_K20_ADC_IRQ 3 +#define APALIS_TK1_K20_TSC_IRQ 4 +#define APALIS_TK1_K20_GPIO_IRQ 5 + +#define APALIS_TK1_K20_FW_VER 0x10 + +#define FW_MINOR (APALIS_TK1_K20_FW_VER & 0x0F) +#define FW_MAJOR ((APALIS_TK1_K20_FW_VER & 0xF0) >> 4) + +#define TK1_K20_SENTINEL 0x55 +#define TK1_K20_INVAL 0xAA + +#define APALIS_TK1_K20_NUMREGS 0x3f +#define APALIS_TK1_K20_IRQ_REG_CNT 1 +#define APALIS_TK1_K20_IRQ_PER_REG 8 + +#define APALIS_TK1_CAN_CLK_UNIT 6250 + +#define APALIS_TK1_MAX_CAN_DMA_XREF 19u + +#endif /* ifndef __LINUX_MFD_APALIS_TK1_K20_API_H */ diff --git a/source/can_task.c b/source/can_task.c index 205e397..bab19ac 100644 --- a/source/can_task.c +++ b/source/can_task.c @@ -36,31 +36,22 @@ #define EFLG_TXBO 0x20 #define EFLG_RXOVR 0x40 -static flexcan_handle_t flexcanHandle[2]; -static volatile bool txComplete[2] = {false, false}; -static volatile bool rxComplete[2] = {false, false}; - -struct can_task { - uint8_t id; - flexcan_frame_t rx_frame; -}; - struct can_registers { + CAN_Type *base; + flexcan_handle_t handle; uint8_t can_status_reg; uint8_t can_err_reg; uint8_t can_mode; - uint8_t recived_frames_cnt; + uint8_t frames_in_buf; uint8_t rx_buf_top; uint8_t rx_buf_bottom; }; -static flexcan_frame_t tx_frame[2]; -static uint8_t data_buffer[2][APALIS_TK1_CAN_RX_BUF_SIZE][CAN_TRANSFER_BUF_LEN]; +static uint8_t data_buffer[2][CAN_RX_BUF_SIZE][CAN_TRANSFER_BUF_LEN]; static struct can_registers can_regs[2]; -uint8_t resume_can; -void generate_can_irq(uint8_t id) +static void generate_can_irq(uint8_t id) { if (id == 0) GPIO_TogglePinsOutput(GPIOB, 1u << 8u); @@ -85,7 +76,7 @@ void can_tx_notify_task(void *pvParameters) } } -static void flexcan_callback0(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData) +static void flexcan_callback(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData) { callback_message_t * cb = (callback_message_t*) userData; BaseType_t reschedule = pdFALSE; @@ -100,32 +91,16 @@ static void flexcan_callback0(CAN_Type *base, flexcan_handle_t *handle, status_t case kStatus_FLEXCAN_TxIdle: if (TX_MESSAGE_BUFFER_NUM0 == result) { - xTaskNotifyFromISR(can_tx_notify_task_handle, 0x01, eSetBits, &reschedule); - } - break; - - default: - break; - } - portYIELD_FROM_ISR(reschedule); -} - -static void flexcan_callback1(CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData) -{ - callback_message_t * cb = (callback_message_t*) userData; - BaseType_t reschedule = pdFALSE; - - switch (status) - { - case kStatus_FLEXCAN_RxFifoIdle: - cb->async_status = pdTRUE; - xSemaphoreGiveFromISR(cb->sem, &reschedule); - break; + switch ((int)base) + { + case (int)CAN0: + xTaskNotifyFromISR(can_tx_notify_task_handle, 0x01, eSetBits, &reschedule); + break; + case (int)CAN1: + xTaskNotifyFromISR(can_tx_notify_task_handle, 0x02, eSetBits, &reschedule); + break; + } - case kStatus_FLEXCAN_TxIdle: - if (TX_MESSAGE_BUFFER_NUM0 == result) - { - xTaskNotifyFromISR(can_tx_notify_task_handle, 0x02, eSetBits, &reschedule); } break; @@ -135,7 +110,7 @@ static void flexcan_callback1(CAN_Type *base, flexcan_handle_t *handle, status_t portYIELD_FROM_ISR(reschedule); } -static void CAN0_Init() +static void CAN_Init(uint8_t id) { flexcan_config_t flexcanConfig; flexcan_rx_fifo_config_t fifoConfig; @@ -147,74 +122,36 @@ static void CAN0_Init() /* Init FlexCAN module. */ flexcanConfig.clkSrc = kFLEXCAN_ClkSrcPeri; - FLEXCAN_Init(CAN0, &flexcanConfig, CLOCK_GetFreq(kCLOCK_BusClk)); + FLEXCAN_Init(can_regs[id].base, &flexcanConfig, CLOCK_GetFreq(kCLOCK_BusClk)); /* Create FlexCAN handle structure and set call back function. */ - FLEXCAN_TransferCreateHandle(CAN0, &flexcanHandle[0], flexcan_callback0, flexcanHandle[0].userData); + FLEXCAN_TransferCreateHandle(can_regs[id].base, &can_regs[id].handle, flexcan_callback, + can_regs[id].handle.userData); /* Set Rx Mask to don't care on all bits. */ - FLEXCAN_SetRxMbGlobalMask(CAN0, FLEXCAN_RX_MB_EXT_MASK(0x00, 0, 0)); - FLEXCAN_SetRxFifoGlobalMask(CAN0, FLEXCAN_RX_MB_EXT_MASK(0x00, 0, 0)); + FLEXCAN_SetRxMbGlobalMask(can_regs[id].base, FLEXCAN_RX_MB_EXT_MASK(0x00, 0, 0)); + FLEXCAN_SetRxFifoGlobalMask(can_regs[id].base, FLEXCAN_RX_MB_EXT_MASK(0x00, 0, 0)); fifoConfig.idFilterNum = 0; fifoConfig.idFilterTable = &fifoFilter; fifoConfig.idFilterType = kFLEXCAN_RxFifoFilterTypeC; fifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; - FLEXCAN_SetRxFifoConfig(CAN0, &fifoConfig, true); + FLEXCAN_SetRxFifoConfig(can_regs[id].base, &fifoConfig, true); /* errata #5641 */ - FLEXCAN_SetTxMbConfig(CAN0, TX_MESSAGE_BUFFER_NUM0 - 1, true); + FLEXCAN_SetTxMbConfig(can_regs[id].base, TX_MESSAGE_BUFFER_NUM0 - 1, true); /* Setup Tx Message Buffer. */ - FLEXCAN_SetTxMbConfig(CAN0, TX_MESSAGE_BUFFER_NUM0, true); - memset(&can_regs[0], 0x00u,sizeof(struct can_registers)); - - PRINTF("CAN0 init done \r\n"); + FLEXCAN_SetTxMbConfig(can_regs[id].base, TX_MESSAGE_BUFFER_NUM0, true); } -static void CAN1_Init() -{ - flexcan_config_t flexcanConfig; - flexcan_rx_fifo_config_t fifoConfig; - uint32_t fifoFilter = 0xFFFFFFFF; - - FLEXCAN_GetDefaultConfig(&flexcanConfig); - - flexcanConfig.baudRate = 1000000U; /* set default to 1Mbit/s */ - - /* Init FlexCAN module. */ - flexcanConfig.clkSrc = kFLEXCAN_ClkSrcPeri; - FLEXCAN_Init(CAN1, &flexcanConfig, CLOCK_GetFreq(kCLOCK_BusClk)); - - /* Create FlexCAN handle structure and set call back function. */ - FLEXCAN_TransferCreateHandle(CAN1, &flexcanHandle[1], flexcan_callback1, flexcanHandle[1].userData); - - /* Set Rx Mask to don't care on all bits. */ - FLEXCAN_SetRxMbGlobalMask(CAN1, FLEXCAN_RX_MB_EXT_MASK(0x00, 0, 0)); - FLEXCAN_SetRxFifoGlobalMask(CAN1, FLEXCAN_RX_MB_EXT_MASK(0x00, 0, 0)); - - fifoConfig.idFilterNum = 0; - fifoConfig.idFilterTable = &fifoFilter; - fifoConfig.idFilterType = kFLEXCAN_RxFifoFilterTypeC; - fifoConfig.priority = kFLEXCAN_RxFifoPrioHigh; - FLEXCAN_SetRxFifoConfig(CAN1, &fifoConfig, true); - - /* errata #5641 */ - FLEXCAN_SetTxMbConfig(CAN1, TX_MESSAGE_BUFFER_NUM0 - 1, true); - - /* Setup Tx Message Buffer. */ - FLEXCAN_SetTxMbConfig(CAN1, TX_MESSAGE_BUFFER_NUM0, true); - memset(&can_regs[0], 0x00u,sizeof(struct can_registers)); - - PRINTF("CAN1 init done \r\n"); -} uint8_t available_data[2]; -void can_calculate_available_data(uint8_t id) { +static void can_calculate_available_data(uint8_t id) { if ( can_regs[id].rx_buf_bottom <= can_regs[id].rx_buf_top) available_data[id] = can_regs[id].rx_buf_top - can_regs[id].rx_buf_bottom; else - available_data[id] = APALIS_TK1_CAN_RX_BUF_SIZE - can_regs[id].rx_buf_bottom; + available_data[id] = CAN_RX_BUF_SIZE - can_regs[id].rx_buf_bottom; available_data[id] = (available_data[id] > APALIS_TK1_MAX_CAN_DMA_XREF) ? APALIS_TK1_MAX_CAN_DMA_XREF:available_data[id]; registers[APALIS_TK1_K20_CAN_IN_BUF_CNT + APALIS_TK1_K20_CAN_DEV_OFFSET(id)] = available_data[id]; @@ -222,20 +159,29 @@ void can_calculate_available_data(uint8_t id) { registers[APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(id)] &= ~CANINTF_RX; } -void frame_to_buffer(flexcan_frame_t *frame, uint8_t id) { +void can_spi_read_complete(uint8_t id) +{ + +} + +static void frame_to_buffer(flexcan_frame_t *frame, uint8_t id) { uint8_t top_frame = can_regs[id].rx_buf_top; - if (frame->format == kFLEXCAN_FrameFormatExtend) { + switch (frame->format){ + case kFLEXCAN_FrameFormatExtend: data_buffer[id][top_frame][0] = frame->id & 0xFF; data_buffer[id][top_frame][1] = (frame->id >> 8 ) & 0xFF; data_buffer[id][top_frame][2] = (frame->id >> 16 ) & 0xFF; data_buffer[id][top_frame][3] = (frame->id >> 24 ) & 0x1F; data_buffer[id][top_frame][3] |= CAN_EFF_FLAG >> 24; - } else { + break; + case kFLEXCAN_FrameFormatStandard: data_buffer[id][top_frame][0] = (frame->id >> 18) & 0xFF; data_buffer[id][top_frame][1] = ((frame->id >> 18) >> 8 ) & 0x7F; data_buffer[id][top_frame][2] = 0x00; data_buffer[id][top_frame][3] = 0x00; + break; } + data_buffer[id][top_frame][3] |= frame->type ? (CAN_RTR_FLAG >> 24):0x00; data_buffer[id][top_frame][4] = frame->length; @@ -250,72 +196,68 @@ void frame_to_buffer(flexcan_frame_t *frame, uint8_t id) { case 1:data_buffer[id][top_frame][5] = frame->dataByte0; } can_regs[id].rx_buf_top++; - can_regs[id].rx_buf_top %= APALIS_TK1_CAN_RX_BUF_SIZE; + can_regs[id].rx_buf_top %= CAN_RX_BUF_SIZE; can_calculate_available_data(id); } +static void can_fifo_rx(uint8_t id, flexcan_fifo_transfer_t * rxXfer) +{ + callback_message_t *can_msg = (callback_message_t *) can_regs[id].handle.userData; + taskENTER_CRITICAL(); + FLEXCAN_TransferReceiveFifoNonBlocking(can_regs[id].base, &can_regs[id].handle, rxXfer); + taskEXIT_CRITICAL(); + xSemaphoreTake(can_msg->sem, portMAX_DELAY); + frame_to_buffer(rxXfer->frame, id); + can_regs[id].frames_in_buf++; + registers[APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(id)] |= CANINTF_RX; + generate_can_irq(id); + if (can_regs[id].frames_in_buf >= CAN_RX_BUF_SIZE) + vTaskSuspend(NULL); +} + void can0_task(void *pvParameters) { flexcan_frame_t rxFrame; flexcan_fifo_transfer_t rxXfer; - callback_message_t cb_msg; - cb_msg.sem = xSemaphoreCreateBinary(); - cb_msg.async_status = pdFALSE; - flexcanHandle[0].userData = (void *) &cb_msg; - CAN0_Init(); + callback_message_t can_msg; + + can_msg.sem = xSemaphoreCreateBinary(); + can_msg.async_status = pdFALSE; + memset(&can_regs[0], 0x00u, sizeof(struct can_registers)); + can_regs[0].handle.userData = (void *) &can_msg; + can_regs[0].base = CAN0; + + CAN_Init(0); + PRINTF("CAN0 init done \r\n"); + rxXfer.frame = &rxFrame; while(1) { - taskENTER_CRITICAL(); - FLEXCAN_TransferReceiveFifoNonBlocking(CAN0, &flexcanHandle[0], &rxXfer); - taskEXIT_CRITICAL(); - if (xSemaphoreTake(cb_msg.sem, portMAX_DELAY) == pdTRUE) { - if (cb_msg.async_status == pdTRUE) { - cb_msg.async_status = pdFALSE; - frame_to_buffer(&rxFrame, 0); - can_regs[0].recived_frames_cnt++; - registers[APALIS_TK1_K20_CANREG] |= CANINTF_RX; - generate_can_irq(0); - } - - if (can_regs[0].recived_frames_cnt >= APALIS_TK1_CAN_RX_BUF_SIZE) - vTaskSuspend(NULL); - } - + can_fifo_rx(0, &rxXfer); } - vSemaphoreDelete(cb_msg.sem); + vSemaphoreDelete(can_msg.sem); } void can1_task(void *pvParameters) { flexcan_frame_t rxFrame; flexcan_fifo_transfer_t rxXfer; - callback_message_t cb_msg; + callback_message_t can_msg; - cb_msg.sem = xSemaphoreCreateBinary(); - flexcanHandle[1].userData = (void *) &cb_msg; - CAN1_Init(); + can_msg.sem = xSemaphoreCreateBinary(); + can_msg.async_status = pdFALSE; + memset(&can_regs[1], 0x00u, sizeof(struct can_registers)); + can_regs[1].handle.userData = (void *) &can_msg; + can_regs[1].base = CAN1; + + CAN_Init(1); + PRINTF("CAN1 init done \r\n"); rxXfer.frame = &rxFrame; while(1) { - taskENTER_CRITICAL(); - FLEXCAN_TransferReceiveFifoNonBlocking(CAN1, &flexcanHandle[1], &rxXfer); - taskEXIT_CRITICAL(); - if (xSemaphoreTake(cb_msg.sem, portMAX_DELAY) == pdTRUE) { - if (cb_msg.async_status == pdTRUE) { - cb_msg.async_status = pdFALSE; - frame_to_buffer(&rxFrame, 1); - can_regs[1].recived_frames_cnt++; - registers[APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_OFFSET] |= CANINTF_RX; - generate_can_irq(1); - } - - if (can_regs[1].recived_frames_cnt >= APALIS_TK1_CAN_RX_BUF_SIZE) { - vTaskSuspend(NULL); - } - } + can_fifo_rx(1, &rxXfer); } - vSemaphoreDelete(cb_msg.sem); + vSemaphoreDelete(can_msg.sem); } @@ -335,105 +277,73 @@ static void can_change_mode(int id, uint8_t new_mode) } -uint8_t set_canreg (int id, uint8_t value) +static uint8_t set_canreg (int id, uint8_t value) { registers[APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(id)] = value; if ( can_regs[id].can_mode != (value & CANCTRL_MODMASK) ) can_change_mode(id, (value & CANCTRL_MODMASK)); - return 1; + return 0; } -uint8_t clr_canreg (int id, uint8_t mask) +static uint8_t clr_canreg (int id, uint8_t mask) { mask &= (CANINTF_TX | CANINTF_ERR); registers[APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(id)] &= ~mask; - return 1; + return 0; } -uint8_t set_canerr (int id, uint8_t value) +static uint8_t set_canerr (int id, uint8_t value) { - return 1; + return 0; } -uint8_t set_canbadreg (int id, uint8_t value) +static uint8_t set_canbadreg (int id, uint8_t value) { - FLEXCAN_SetBitRate(id ? CAN1:CAN0, CLOCK_GetFreq(kCLOCK_BusClk), value * APALIS_TK1_CAN_CLK_UNIT); - return 1; + FLEXCAN_SetBitRate(can_regs[id].base, CLOCK_GetFreq(kCLOCK_BusClk), value * APALIS_TK1_CAN_CLK_UNIT); + return 0; } -#if 0 -static flexcan_timing_config_t timingConfig; -#endif - -uint8_t set_canbittimig (int id, uint16_t value, int16_t mask) +static uint8_t set_canbittimig (int id, uint16_t value, int16_t mask) { -#if 0 - if(mask & 0xFF) { - timingConfig.phaseSeg1 = 0; - timingConfig.phaseSeg2 = 0; - timingConfig.rJumpwidth = 0; - } - if (mask & 0xFF00) { - timingConfig.propSeg = 0; - timingConfig.preDivider = 0; - - } -#endif - return 1; + /* According to NXP we should use default setting */ + return 0; } -uint8_t can0_transmit(){ +uint8_t can_sendframe(uint8_t id, uint8_t *data, uint8_t len) +{ flexcan_mb_transfer_t txXfer; + flexcan_frame_t tx_frame; - txXfer.frame = &tx_frame[0]; - txXfer.mbIdx = TX_MESSAGE_BUFFER_NUM0; + tx_frame.length = data[4]; + tx_frame.id = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0]; - taskENTER_CRITICAL(); - FLEXCAN_TransferSendNonBlocking(CAN0, &flexcanHandle[0], &txXfer); - taskEXIT_CRITICAL(); - return 0; -} - -uint8_t can1_transmit(){ - flexcan_mb_transfer_t txXfer; + tx_frame.format = (data[3] << 24 & CAN_EFF_FLAG) ? + kFLEXCAN_FrameFormatExtend:kFLEXCAN_FrameFormatStandard; + tx_frame.type = (data[3] << 24 & CAN_RTR_FLAG) ? + kFLEXCAN_FrameTypeRemote:kFLEXCAN_FrameTypeData; - txXfer.frame = &tx_frame[1]; + if (tx_frame.format == kFLEXCAN_FrameFormatExtend) + tx_frame.id = FLEXCAN_ID_EXT(tx_frame.id); + else + tx_frame.id = FLEXCAN_ID_STD(tx_frame.id); + + tx_frame.dataByte0 = data[5]; + tx_frame.dataByte1 = data[5 + 1]; + tx_frame.dataByte2 = data[5 + 2]; + tx_frame.dataByte3 = data[5 + 3]; + tx_frame.dataByte4 = data[5 + 4]; + tx_frame.dataByte5 = data[5 + 5]; + tx_frame.dataByte6 = data[5 + 6]; + tx_frame.dataByte7 = data[5 + 7]; + + txXfer.frame = &tx_frame; txXfer.mbIdx = TX_MESSAGE_BUFFER_NUM0; taskENTER_CRITICAL(); - FLEXCAN_TransferSendNonBlocking(CAN1, &flexcanHandle[1], &txXfer); + FLEXCAN_TransferSendNonBlocking(can_regs[id].base , &can_regs[id].handle, &txXfer); taskEXIT_CRITICAL(); - return 0; -} - -uint8_t can_sendframe(uint8_t id, uint8_t *data, uint8_t len) -{ - tx_frame[id].length = data[4]; - tx_frame[id].id = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0]; - - tx_frame[id].format = (data[3] << 24 & CAN_EFF_FLAG) ? - kFLEXCAN_FrameFormatExtend:kFLEXCAN_FrameFormatStandard; - tx_frame[id].type = (data[3] << 24 & CAN_RTR_FLAG) ? - kFLEXCAN_FrameTypeRemote:kFLEXCAN_FrameTypeData; - if (tx_frame[id].format == kFLEXCAN_FrameFormatExtend) - tx_frame[id].id = FLEXCAN_ID_EXT(tx_frame[id].id); - else - tx_frame[id].id = FLEXCAN_ID_STD(tx_frame[id].id); - - tx_frame[id].dataByte0 = data[5]; - tx_frame[id].dataByte1 = data[5 + 1]; - tx_frame[id].dataByte2 = data[5 + 2]; - tx_frame[id].dataByte3 = data[5 + 3]; - tx_frame[id].dataByte4 = data[5 + 4]; - tx_frame[id].dataByte5 = data[5 + 5]; - tx_frame[id].dataByte6 = data[5 + 6]; - tx_frame[id].dataByte7 = data[5 + 7]; - if (id == 0) - can0_transmit(); - else if (id == 1) - can1_transmit(); return 0; } @@ -445,11 +355,9 @@ uint16_t can_readframe(uint8_t id, dspi_transfer_t *spi_transfer) if (rx_size > available_data[id]) rx_size = available_data[id]; can_regs[id].rx_buf_bottom = can_regs[id].rx_buf_bottom + rx_size; - can_regs[id].rx_buf_bottom %= APALIS_TK1_CAN_RX_BUF_SIZE; - - resume_can = id + 1; + can_regs[id].rx_buf_bottom %= CAN_RX_BUF_SIZE; - can_regs[id].recived_frames_cnt -= rx_size; + can_regs[id].frames_in_buf -= rx_size; can_calculate_available_data(id); return rx_size * CAN_TRANSFER_BUF_LEN; diff --git a/source/can_task.h b/source/can_task.h index 9ad77f9..8934c0a 100644 --- a/source/can_task.h +++ b/source/can_task.h @@ -10,13 +10,13 @@ #include "task.h" #include "fsl_dspi.h" -TaskHandle_t can0_task_handle; -TaskHandle_t can1_task_handle; -TaskHandle_t can_tx_notify_task_handle; +extern TaskHandle_t can0_task_handle; +extern TaskHandle_t can1_task_handle; +extern TaskHandle_t can_tx_notify_task_handle; void can0_task(void *pvParameters); void can1_task(void *pvParameters); void can_tx_notify_task(void *pvParameters); int canx_registers(dspi_transfer_t *spi_transfer, int id); -void can_calculate_available_data(uint8_t id); +void can_spi_read_complete(uint8_t id); #endif /* SOURCE_CAN_TASK_H_ */ diff --git a/source/com_task.c b/source/com_task.c index a141c40..4b73209 100644 --- a/source/com_task.c +++ b/source/com_task.c @@ -7,7 +7,7 @@ volatile uint8_t registers[APALIS_TK1_K20_LAST_REG]; volatile uint8_t regRxHandled; -/* Put FW version at known address in binary. Make it 32-bit to have room for the future*/ +/* Put FW version at known address in a binary. Make it 32-bit to have room for the future*/ const uint32_t __attribute__((section(".FwVersion"), used)) fw_version = APALIS_TK1_K20_FW_VER; static dspi_slave_handle_t spi_handle; @@ -151,16 +151,17 @@ static void SPI_init() { } void spi_task(void *pvParameters) { - callback_message_t cb_msg; + callback_message_t spi_msg; dspi_transfer_t slaveXfer; int ret = 0; + int can_read = -1; #ifdef SPI_DMA uint32_t slaveRxChannel, slaveTxChannel; edma_config_t userConfig; #endif - cb_msg.sem = xSemaphoreCreateBinary(); - spi_handle.userData = &cb_msg; + spi_msg.sem = xSemaphoreCreateBinary(); + spi_handle.userData = &spi_msg; SPI_init(); #ifdef SPI_DMA slaveRxChannel = 0U; @@ -178,8 +179,8 @@ void spi_task(void *pvParameters) { EDMA_CreateHandle(&dspiEdmaSlaveRxHandle, DMA0, slaveRxChannel); EDMA_CreateHandle(&dspiEdmaSlaveTxHandle, DMA0, slaveTxChannel); - g_dspi_edma_s_handle.userData = &cb_msg; - DSPI_SlaveTransferCreateHandleEDMA(SPI2, &g_dspi_edma_s_handle, SPI_callback, &cb_msg, &dspiEdmaSlaveRxHandle, &dspiEdmaSlaveTxHandle); + g_dspi_edma_s_handle.userData = &spi_msg; + DSPI_SlaveTransferCreateHandleEDMA(SPI2, &g_dspi_edma_s_handle, SPI_callback, &spi_msg, &dspiEdmaSlaveRxHandle, &dspiEdmaSlaveTxHandle); #endif memset(registers, 0x00, APALIS_TK1_K20_LAST_REG); registers[APALIS_TK1_K20_REVREG] = APALIS_TK1_K20_FW_VER; @@ -194,7 +195,7 @@ void spi_task(void *pvParameters) { ret = DSPI_SlaveTransferNonBlocking(SPI2, &spi_handle, &slaveXfer); if ( ret == kStatus_Success) { - xSemaphoreTake(cb_msg.sem, portMAX_DELAY); + xSemaphoreTake(spi_msg.sem, portMAX_DELAY); slaveXfer.txData = slaveTxData; slaveXfer.rxData = slaveRxData; @@ -204,10 +205,12 @@ void spi_task(void *pvParameters) { } else if ((slaveRxData[1] >= APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(0)) && (slaveRxData[1] <= APALIS_TK1_K20_CAN_OUT_BUF_END + APALIS_TK1_K20_CAN_DEV_OFFSET(0))) { ret = canx_registers(&slaveXfer, 0); + can_read = 0; } else if ((slaveRxData[1] >= APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(1)) && (slaveRxData[1] <= APALIS_TK1_K20_CAN_OUT_BUF_END + APALIS_TK1_K20_CAN_DEV_OFFSET(1))) { ret = canx_registers(&slaveXfer, 1); + can_read = 1; #ifdef BOARD_USES_ADC } else if ((slaveRxData[1] >= APALIS_TK1_K20_ADCREG) && (slaveRxData[1] <= APALIS_TK1_K20_ADC_CH3H)) { ret = adc_registers(&slaveXfer); @@ -223,7 +226,7 @@ void spi_task(void *pvParameters) { } - if (ret <= 0) { + if (ret < 0) { slaveTxData[0] = TK1_K20_INVAL; slaveTxData[1] = ret; slaveTxData[2] = slaveRxData[0]; @@ -242,17 +245,10 @@ void spi_task(void *pvParameters) { #else DSPI_SlaveTransferNonBlocking(SPI2, &spi_handle, &slaveXfer); #endif - xSemaphoreTake(cb_msg.sem, portMAX_DELAY); - if (resume_can != 0) { - if (resume_can == 1) { - vTaskResume(can0_task_handle); - can_calculate_available_data(0); - } - else { - vTaskResume(can1_task_handle); - can_calculate_available_data(1); - } - resume_can = 0; + xSemaphoreTake(spi_msg.sem, portMAX_DELAY); + if (can_read >= 0) { + can_spi_read_complete(can_read); + can_read = -1; } } } diff --git a/source/com_task.h b/source/com_task.h index 46728ac..4a9557d 100644 --- a/source/com_task.h +++ b/source/com_task.h @@ -12,6 +12,7 @@ #include "fsl_edma.h" #include "fsl_dspi_edma.h" #include "fsl_dmamux.h" +#include "apalis-tk1-k20-api.h" /* FreeRTOS kernel includes. */ #include "FreeRTOS.h" @@ -27,145 +28,16 @@ typedef struct _callback_message_t SemaphoreHandle_t sem; } callback_message_t; -TaskHandle_t spi_task_handle; +extern TaskHandle_t spi_task_handle; void generate_irq(uint8_t irq); void clear_irq_flag(uint8_t irq); void spi_task(void *pvParameters); #define BIT(nr) (1UL << (nr)) - - -/* Commands and registers used in SPI communication */ - -/* Commands*/ -#define APALIS_TK1_K20_READ_INST 0x0F -#define APALIS_TK1_K20_WRITE_INST 0xF0 -#define APALIS_TK1_K20_BULK_WRITE_INST 0x3C -#define APALIS_TK1_K20_BULK_READ_INST 0xC3 - -#define APALIS_TK1_K20_MAX_BULK (250) - -/* General registers*/ -#define APALIS_TK1_K20_STAREG 0x00 /* general status register RO */ -#define APALIS_TK1_K20_REVREG 0x01 /* FW revision register RO*/ -#define APALIS_TK1_K20_IRQREG 0x02 /* IRQ status RO(reset of read) */ -#define APALIS_TK1_K20_CTRREG 0x03 /* general control register RW */ -#define APALIS_TK1_K20_MSQREG 0x04 /* IRQ mask register RW */ - -/* 0x05-0x0F Reserved */ - -/* CAN Registers */ -#define APALIS_TK1_K20_CANREG 0x10 /* CAN0 control & status register RW */ -#define APALIS_TK1_K20_CANREG_CLR 0x11 /* CAN0 CANREG clear register WO */ -#define APALIS_TK1_K20_CANERR 0x12 /* CAN0 error register RW */ -#define APALIS_TK1_K20_CAN_BAUD_REG 0x13 /* CAN0 baud set register RW */ -#define APALIS_TK1_K20_CAN_BIT_1 0x14 /* CAN0 bit timing register 1 RW */ -#define APALIS_TK1_K20_CAN_BIT_2 0x15 /* CAN0 bit timing register 2 RW */ -#define APALIS_TK1_K20_CAN_IN_BUF_CNT 0x16 /* CAN0 IN received data count RO */ -#define APALIS_TK1_K20_CAN_IN_BUF 0x17 /* CAN0 IN RO */ -/* buffer size is 13 bytes */ -#define APALIS_TK1_K20_CAN_IN_BUF_END 0x23 /* CAN0 IN RO */ -#define APALIS_TK1_K20_CAN_OUT_BUF 0x24 /* CAN0 OUT WO */ -/* buffer size is 13 bytes */ -#define APALIS_TK1_K20_CAN_OUT_BUF_END (APALIS_TK1_K20_CAN_OUT_BUF + 13 - 1)/* CAN OUT BUF END */ -#define APALIS_TK1_K20_CAN_OFFSET 0x30 -#define APALIS_TK1_K20_CAN_DEV_OFFSET(x) (x ? APALIS_TK1_K20_CAN_OFFSET : 0) - -/* 0x30-0x3F Reserved */ -/* 0x40-0x62 CAN1 registers same layout as CAN0*/ -/* 0x63-0x6F Reserved */ - -/* ADC Registers */ -#define APALIS_TK1_K20_ADCREG 0x70 /* ADC control & status register RW */ -#define APALIS_TK1_K20_ADC_CH0L 0x71 /* ADC Channel 0 LSB RO */ -#define APALIS_TK1_K20_ADC_CH0H 0x72 /* ADC Channel 0 MSB RO */ -#define APALIS_TK1_K20_ADC_CH1L 0x73 /* ADC Channel 1 LSB RO */ -#define APALIS_TK1_K20_ADC_CH1H 0x74 /* ADC Channel 1 MSB RO */ -#define APALIS_TK1_K20_ADC_CH2L 0x75 /* ADC Channel 2 LSB RO */ -#define APALIS_TK1_K20_ADC_CH2H 0x76 /* ADC Channel 2 MSB RO */ -#define APALIS_TK1_K20_ADC_CH3L 0x77 /* ADC Channel 3 LSB RO */ -#define APALIS_TK1_K20_ADC_CH3H 0x78 /* ADC Channel 3 MSB RO */ -/* Bulk read of LSB register can be use to read entire 16-bit in one command */ -/* Bulk read of APALIS_TK1_K20_ADC_CH0L register can be use to read all - * ADC channels in one command */ - -/* 0x79-0x7F reserved */ - -/* TSC Register */ -#define APALIS_TK1_K20_TSCREG 0x80 /* TSC control & status register RW */ -#define APALIS_TK1_K20_TSC_XML 0x81 /* TSC X- data LSB RO */ -#define APALIS_TK1_K20_TSC_XMH 0x82 /* TSC X- data MSB RO */ -#define APALIS_TK1_K20_TSC_XPL 0x83 /* TSC X+ data LSB RO */ -#define APALIS_TK1_K20_TSC_XPH 0x84 /* TSC X+ data MSB RO */ -#define APALIS_TK1_K20_TSC_YML 0x85 /* TSC Y- data LSB RO */ -#define APALIS_TK1_K20_TSC_YMH 0x86 /* TSC Y- data MSB RO */ -#define APALIS_TK1_K20_TSC_YPL 0x87 /* TSC Y+ data LSB RO */ -#define APALIS_TK1_K20_TSC_YPH 0x88 /* TSC Y+ data MSB RO */ -/* Bulk read of LSB register can be use to read entire 16-bit in one command */ -#define APALIS_TK1_K20_TSC_ENA BIT(0) -#define APALIS_TK1_K20_TSC_ENA_MASK BIT(0) - -/* 0x89-0x8F Reserved */ - -/* GPIO Registers */ -#define APALIS_TK1_K20_GPIOREG 0x90 /* GPIO control & status register RW */ -#define APALIS_TK1_K20_GPIO_NO 0x91 /* currently configured GPIO RW */ -#define APALIS_TK1_K20_GPIO_STA 0x92 /* Status register for the APALIS_TK1_K20_GPIO_NO GPIO RW */ -/* MSB | 0 ... 0 | VALUE | Output-1 / Input-0 | LSB */ -#define APALIS_TK1_K20_GPIO_STA_OE BIT(0) -#define APALIS_TK1_K20_GPIO_STA_VAL BIT(1) - -/* 0x93-0xFC Reserved */ -#define APALIS_TK1_K20_LAST_REG 0xFD -#define APALIS_TK1_K20_RET_REQ 0xFE -/* 0xFF Reserved */ - -/* Interrupt flags */ -#define APALIS_TK1_K20_GEN_IRQ 0 -#define APALIS_TK1_K20_CAN0_IRQ 1 -#define APALIS_TK1_K20_CAN1_IRQ 2 -#define APALIS_TK1_K20_ADC_IRQ 3 -#define APALIS_TK1_K20_TSC_IRQ 4 -#define APALIS_TK1_K20_GPIO_IRQ 5 - -#define APALIS_TK1_K20_FW_VER 0x0D - -#define FW_MINOR (APALIS_TK1_K20_FW_VER & 0x0F) -#define FW_MAJOR ((APALIS_TK1_K20_FW_VER & 0xF0) >> 4) - -#define TK1_K20_SENTINEL 0x55 -#define TK1_K20_INVAL 0xAA - -#define APALIS_TK1_K20_NUMREGS 0x3f -#define APALIS_TK1_K20_IRQ_REG_CNT 1 -#define APALIS_TK1_K20_IRQ_PER_REG 8 - -#define APALIS_TK1_CAN_CLK_UNIT 6250 - -#define APALIS_TK1_CAN_RX_BUF_SIZE 256 -#define APALIS_TK1_MAX_CAN_DMA_XREF 19 - -#define APALIS_TK1_K20_HEADER 4 - #define ADC0_CHANNEL_CNT 4 - #define TSC0_CHANNEL_CNT 4 - -/* Structure with general registers */ -struct register_struct { - uint8_t status; - uint8_t control; - uint8_t irq_mask; - uint8_t irq; - uint8_t gpio_no; - uint16_t adc[ADC0_CHANNEL_CNT]; - uint16_t tsc_xm; - uint16_t tsc_xp; - uint16_t tsc_ym; - uint16_t tsc_yp; -} gen_regs; +#define CAN_RX_BUF_SIZE 256 extern volatile uint8_t registers[APALIS_TK1_K20_LAST_REG]; -extern uint8_t resume_can; #endif /* COM_TASK_H_ */ diff --git a/source/main.c b/source/main.c index d2f86c2..c076e43 100644 --- a/source/main.c +++ b/source/main.c @@ -56,6 +56,16 @@ #define CONTROLLER_ID kUSB_ControllerEhci0 #endif +#ifdef BOARD_USES_ADC +TaskHandle_t adc_task_handle; +TaskHandle_t tsc_task_handle; +#endif +TaskHandle_t can0_task_handle; +TaskHandle_t can1_task_handle; +TaskHandle_t can_tx_notify_task_handle; +TaskHandle_t spi_task_handle; + + /*! * @brief Application entry point. */ @@ -73,7 +83,6 @@ int main(void) { PRINTF("create SPI task error\r\n"); } - if(xTaskCreate(can0_task, "CAN0_task", 1000L / sizeof(portSTACK_TYPE), NULL, 2, &can0_task_handle) != pdPASS) { PRINTF("create CAN0 task error\r\n"); -- cgit v1.2.3