diff options
Diffstat (limited to 'CMSIS/Documentation/SVD/html/group__cpu_section__gr.html')
| -rw-r--r-- | CMSIS/Documentation/SVD/html/group__cpu_section__gr.html | 201 |
1 files changed, 201 insertions, 0 deletions
diff --git a/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html b/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html new file mode 100644 index 0000000..b728a35 --- /dev/null +++ b/CMSIS/Documentation/SVD/html/group__cpu_section__gr.html @@ -0,0 +1,201 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>CPU Section</title> +<title>CMSIS-SVD: CPU Section</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); +</script> +<link href="stylsheetf" rel="stylesheet" type="text/css" /> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-SVD +  <span id="projectnumber">Version 1.3.1</span> + </div> + <div id="projectbrief">CMSIS System View Description</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.2 --> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('group__cpu_section__gr.html','');}); +</script> +<div id="doc-content"> +<div class="header"> + <div class="headertitle"> +<div class="title">CPU Section</div> </div> +<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extensions</a></div></div><!--header--> +<div class="contents"> +<p>The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.</p> +<pre> +<span class="opt"><cpu></span> + <span class="mand"><name><em>cpuNameType</em></name> + <revision><em>revisionType</em></revision> + <endian><em>endianType</em></endian> + <mpuPresent><em>xs:boolean</em></mpuPresent> + <fpuPresent><em>xs:boolean</em></fpuPresent> + <fpuDP><em>xs:boolean</em></fpuDP> + <icachePresent><em>xs:boolean</em></icachePresent> + <dcachePresent><em>xs:boolean</em></dcachePresent> + <itcmPresent><em>xs:boolean</em></itcmPresent> + <dtcmPresent><em>xs:boolean</em></dtcmPresent> + <vtorPresent><em>xs:boolean</em></vtorPresent> + <nvicPrioBits><em>scaledNonNegativeInteger</em></nvicPrioBits> + <vendorSystickConfig><em>xs:boolean</em></vendorSystickConfig> + <deviceNumInterrupts><em>scaledNonNegativeInteger</em><deviceNumInterrupts> + <sauNumRegions><em>scaledNonNegativeInteger</em></sauRegions> + <sauRegionsConfig><em>sauRegionsConfigType</em></sauRegionsConfig> + </span> +<span class="opt"></cpu></span> +</pre><table class="cmtable" summary="CPU Section Elements"> +<tr> +<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr> +<tr> +<td>name </td><td>The predefined tokens are:<ul> +<li><span class="XML-Token">CM0</span>: ARM Cortex-M0</li> +<li><span class="XML-Token">CM0PLUS</span>: ARM Cortex-M0+</li> +<li><span class="XML-Token">CM3</span>: ARM Cortex-M3</li> +<li><span class="XML-Token">CM4</span>: ARM Cortex-M4</li> +<li><span class="XML-Token">CM7</span>: ARM Cortex-M7</li> +<li><span class="XML-Token">SC000</span>: ARM Secure Core SC000</li> +<li><span class="XML-Token">SC300</span>: ARM Secure Core SC300</li> +<li><span class="XML-Token">other</span>: other processor architectures </li> +</ul> +</td><td>cpuNameType </td><td>1..1 </td></tr> +<tr> +<td>revisionType </td><td>Defines the HW revision of the processor. The defined version format is <span class="XML-Token">r<em>N</em>p<em>M</em></span> (N,M = [0 - 9]). </td><td>revisionType </td><td>1..1 </td></tr> +<tr> +<td>endian </td><td>Defines the endianess of the processor being one of:<ul> +<li><span class="XML-Token">little</span>: little endian memory (least significant byte gets allocated at the lowest address).</li> +<li><span class="XML-Token">big</span>: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).</li> +<li><span class="XML-Token">selectable</span>: little and big endian are configurable for the device and become active after the next reset.</li> +<li><span class="XML-Token">other</span>: the endianess is neither little nor big endian. </li> +</ul> +</td><td>endianType </td><td>1..1 </td></tr> +<tr> +<td>mpuPresent </td><td>Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +<tr> +<td>fpuPresent </td><td>Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 and Cortex-M7 are the only available Cortex-M processor with an optional FPU. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +<tr> +<td>fpuDP </td><td>Indicates that the processor is equipped with a double precision floating point unit. Flag is only valid if fpuPresent is set true. Cortex-M7 is currently the only Cortex-M processor available with a double precision floating point unit. </td><td>boolean </td><td>0..1 </td></tr> +<tr> +<td>icachePresent </td><td>Indicates that the processor has an instruction cache. Note: only an option for Cortex-M7 based devices. </td><td>boolean </td><td>0..1 </td></tr> +<tr> +<td>dcachePresent </td><td>Indicates that the processor has an data cache. Note: only an option for Cortex-M7 based devices. </td><td>boolean </td><td>0..1 </td></tr> +<tr> +<td>itcmPresent </td><td>Indicates that the processor has an instruction tightly coupled memory. Note: only an option for Cortex-M7 based devices. </td><td>boolean </td><td>0..1 </td></tr> +<tr> +<td>dtcmPresent </td><td>Indicates that the processor has an data tightly coupled memory. Note: only an option for Cortex-M7 based devices. </td><td>boolean </td><td>0..1 </td></tr> +<tr> +<td>vtorPresent </td><td>This is an optional flag used for the Cortex-M0+ based devices only. It indicates whether the Vector Table Offset Register (VTOR) is implemented in the Cortex-M0+ device or not. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. If it is not specified VTOR is assumed to be present. </td><td>boolean </td><td>1..1 </td></tr> +<tr> +<td>nvicPrioBits </td><td>Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. </td><td>scaledNonNegativeInteger </td><td>1..1 </td></tr> +<tr> +<td>vendorSystickConfig </td><td>Indicates whether the processor implements a vendor-specific System Tick Timer. If <span class="XML-Token">false</span>, then the ARM defined System Tick Timer is available. If <span class="XML-Token">true</span>, then a vendor-specific System Tick Timer must be implemented. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr> +<tr> +<td>deviceNumInterrupts </td><td>Specifies the total number of interrupts implemented by the device. This value can be used to validate the number of described interrupts </td><td>scaledNonNegativeInteger </td><td>0..1 </td></tr> +<tr> +<td>sauNumRegions </td><td>If set and not zero this flag indicates that the device is equipped with a Security Attribution Unit (SAU) and the maximum number of available address regions. </td><td>scaledNonNegativeInteger </td><td>0..1 </td></tr> +<tr> +<td>sauRegionsConfig </td><td><p class="starttd">If the Secure Attribution Unit is preconfigured by HW or Firmware, the settings are described here.</p> +<p><span class="XML-Token"><sauRegionsConfig</span> enabled=true protectionWhenDisabled="s"<span class="XML-Token">></span></p> +<ul> +<li><span class="XML-Token"><base><em>adddress</em></base></span>: SAU Region base adddress (type=scaledNonNegativeInteger) [1..1]</li> +<li><span class="XML-Token"><limit><em>address</em></limit></span>: SAU Region limit adddress (type=scaledNonNegativeInteger) [1..1]</li> +<li><span class="XML-Token"><access><em>flag</em></access></span>: one of "n" = non-secure or "c" = secure callable (type=string) [1..1]</li> +<li>attribute: <span class="XML-Token">enabled =</span> [true|false]: SAU Region is active (type=boolean) [0..1]</li> +<li>attribute: <span class="XML-Token">name =</span> [string]: brief name for identifying the SAU Region(type=string) [0..1]</li> +</ul> +<p class="endtd"><span class="XML-Token"></sauRegionsConfig></span></p> +<ul> +<li>attribute: <span class="XML-Token">enabled =</span> [true|false]: enable/disable the complete SAU (type=boolean) [0..1]</li> +<li>attribute: <span class="XML-Token">protectionWhenDisabled =</span> [s|n]: if the complete SAU is disabled the whole memory is treated either "s" = secure or "n" non-secure - [0..1] (default="s") </li> +</ul> +</td><td>SauRegionsConfigType </td><td><p class="starttd">0..1 </p> +<p class="endtd"></p> +</td></tr> +</table> +<h1><a class="anchor" id="cpuSection_ex"></a> +Example:</h1> +<div class="fragment"><div class="line">...</div> +<div class="line"><cpu></div> +<div class="line"> <name>CM7</name> </div> +<div class="line"> <revision>r0p0</revision></div> +<div class="line"> <endian>little</endian></div> +<div class="line"> <mpuPresent><span class="keyword">true</span></mpuPresent></div> +<div class="line"> <!-- has <span class="keywordtype">double</span> precision FPU --></div> +<div class="line"> <fpuPresent><span class="keyword">true</span></fpuPresent></div> +<div class="line"> <fpuDP><span class="keyword">true</span></fpuDP></div> +<div class="line"> <!-- has instruction and data cache --></div> +<div class="line"> <icachePresent><span class="keyword">true</span></icachePresent></div> +<div class="line"> <dcachePresent><span class="keyword">true</span></dcachePresent></div> +<div class="line"> <!-- has no instruction nor data tighly coupled memory --></div> +<div class="line"> <itcmPresent><span class="keyword">false</span></itcmPresent></div> +<div class="line"> <dtcmPresent><span class="keyword">false</span></dtcmPresent></div> +<div class="line"> <nvicPrioBits>4</nvicPrioBits></div> +<div class="line"> <vendorSystickConfig><span class="keyword">false</span></vendorSystickConfig> </div> +<div class="line"></cpu></div> +<div class="line">...</div> +</div><!-- fragment --><p>This example describes a device based on a Cortex-M7 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and double precision hardware Floating Point Unit. It has and instruction and a data cache but no Tightly Coupled Memories. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM. </p> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Tue Oct 27 2015 14:35:46 for CMSIS-SVD by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2 + --> + </li> + </ul> +</div> +</body> +</html> |