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diff --git a/CMSIS/Documentation/Driver/html/group__nand__bus__mode__codes.html b/CMSIS/Documentation/Driver/html/group__nand__bus__mode__codes.html new file mode 100644 index 0000000..7b94e51 --- /dev/null +++ b/CMSIS/Documentation/Driver/html/group__nand__bus__mode__codes.html @@ -0,0 +1,515 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>NAND Bus Modes</title> +<title>CMSIS-Driver: NAND Bus Modes</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link 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Middleware and Application Code</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.2 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + 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onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerations</a><a 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Codes</a></div></div><!--header--> +<div class="contents"> + +<p>Specify bus mode of the NAND interface. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gac7743aeb6411b97f9fc6a24b556f4963">ARM_NAND_BUS_SDR</a>   (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr> +<tr class="memdesc:gac7743aeb6411b97f9fc6a24b556f4963"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: SDR (Single Data Rate) - Traditional interface (default) <a href="#gac7743aeb6411b97f9fc6a24b556f4963"></a><br/></td></tr> +<tr class="separator:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga82b8261b3d0d85881535adada318a7df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga82b8261b3d0d85881535adada318a7df">ARM_NAND_BUS_DDR</a>   (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr> +<tr class="memdesc:ga82b8261b3d0d85881535adada318a7df"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: NV-DDR (Double Data Rate) <a href="#ga82b8261b3d0d85881535adada318a7df"></a><br/></td></tr> +<tr class="separator:ga82b8261b3d0d85881535adada318a7df"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga13c102201d6021db184a2f068656c518"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga13c102201d6021db184a2f068656c518">ARM_NAND_BUS_DDR2</a>   (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr> +<tr class="memdesc:ga13c102201d6021db184a2f068656c518"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: NV-DDR2 (Double Data Rate) <a href="#ga13c102201d6021db184a2f068656c518"></a><br/></td></tr> +<tr class="separator:ga13c102201d6021db184a2f068656c518"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga971e574ac412bbba445055e9afc384ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga971e574ac412bbba445055e9afc384ba">ARM_NAND_BUS_TIMING_MODE_0</a>   (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr> +<tr class="memdesc:ga971e574ac412bbba445055e9afc384ba"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 0 (default) <a href="#ga971e574ac412bbba445055e9afc384ba"></a><br/></td></tr> +<tr class="separator:ga971e574ac412bbba445055e9afc384ba"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga475a339e929eca46e11bc8a7b330aa45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga475a339e929eca46e11bc8a7b330aa45">ARM_NAND_BUS_TIMING_MODE_1</a>   (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr> +<tr class="memdesc:ga475a339e929eca46e11bc8a7b330aa45"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 1. <a href="#ga475a339e929eca46e11bc8a7b330aa45"></a><br/></td></tr> +<tr class="separator:ga475a339e929eca46e11bc8a7b330aa45"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaed6154fb03b5516faf0bfd11d7a46309">ARM_NAND_BUS_TIMING_MODE_2</a>   (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr> +<tr class="memdesc:gaed6154fb03b5516faf0bfd11d7a46309"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 2. <a href="#gaed6154fb03b5516faf0bfd11d7a46309"></a><br/></td></tr> +<tr class="separator:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gacbc4e07e1af6ef0e4c656428e81464a9">ARM_NAND_BUS_TIMING_MODE_3</a>   (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr> +<tr class="memdesc:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 3. <a href="#gacbc4e07e1af6ef0e4c656428e81464a9"></a><br/></td></tr> +<tr class="separator:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga709d51a5215cd23ce2d85aec57141456"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga709d51a5215cd23ce2d85aec57141456">ARM_NAND_BUS_TIMING_MODE_4</a>   (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr> +<tr class="memdesc:ga709d51a5215cd23ce2d85aec57141456"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 4 (SDR EDO capable) <a href="#ga709d51a5215cd23ce2d85aec57141456"></a><br/></td></tr> +<tr class="separator:ga709d51a5215cd23ce2d85aec57141456"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaee3cad14ce2b8b9af69149bf74597791"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaee3cad14ce2b8b9af69149bf74597791">ARM_NAND_BUS_TIMING_MODE_5</a>   (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr> +<tr class="memdesc:gaee3cad14ce2b8b9af69149bf74597791"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 5 (SDR EDO capable) <a href="#gaee3cad14ce2b8b9af69149bf74597791"></a><br/></td></tr> +<tr class="separator:gaee3cad14ce2b8b9af69149bf74597791"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga4a3524e0eba994b3a66e06cde877f0f6">ARM_NAND_BUS_TIMING_MODE_6</a>   (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr> +<tr class="memdesc:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 6 (NV-DDR2 only) <a href="#ga4a3524e0eba994b3a66e06cde877f0f6"></a><br/></td></tr> +<tr class="separator:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaa63d75f5f2b48a7345a066d58de1bd23">ARM_NAND_BUS_TIMING_MODE_7</a>   (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr> +<tr class="memdesc:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 7 (NV-DDR2 only) <a href="#gaa63d75f5f2b48a7345a066d58de1bd23"></a><br/></td></tr> +<tr class="separator:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga77348df5f5c2c96bcaeec60b6da02c1b">ARM_NAND_BUS_DDR2_DO_WCYC_0</a>   (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr> +<tr class="memdesc:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 0 (default) <a href="#ga77348df5f5c2c96bcaeec60b6da02c1b"></a><br/></td></tr> +<tr class="separator:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga5839be0b4b2eb930ec039a3403b5e89e">ARM_NAND_BUS_DDR2_DO_WCYC_1</a>   (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr> +<tr class="memdesc:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 1. <a href="#ga5839be0b4b2eb930ec039a3403b5e89e"></a><br/></td></tr> +<tr class="separator:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga10a1ef3be69bfa7e6cc657bee751a077">ARM_NAND_BUS_DDR2_DO_WCYC_2</a>   (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr> +<tr class="memdesc:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 2. <a href="#ga10a1ef3be69bfa7e6cc657bee751a077"></a><br/></td></tr> +<tr class="separator:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga7f9e8416c4a4e20c4a04323e39f2100d">ARM_NAND_BUS_DDR2_DO_WCYC_4</a>   (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr> +<tr class="memdesc:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 4. <a href="#ga7f9e8416c4a4e20c4a04323e39f2100d"></a><br/></td></tr> +<tr class="separator:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaeee1853dea5e96cb19d2596cc0e70169">ARM_NAND_BUS_DDR2_DI_WCYC_0</a>   (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr> +<tr class="memdesc:gaeee1853dea5e96cb19d2596cc0e70169"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 0 (default) <a href="#gaeee1853dea5e96cb19d2596cc0e70169"></a><br/></td></tr> +<tr class="separator:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga42560a1f046e20cc4956276156c4ce25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">ARM_NAND_BUS_DDR2_DI_WCYC_1</a>   (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr> +<tr class="memdesc:ga42560a1f046e20cc4956276156c4ce25"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 1. <a href="#ga42560a1f046e20cc4956276156c4ce25"></a><br/></td></tr> +<tr class="separator:ga42560a1f046e20cc4956276156c4ce25"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaad2e7807292d84a5070143626f5c2756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaad2e7807292d84a5070143626f5c2756">ARM_NAND_BUS_DDR2_DI_WCYC_2</a>   (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr> +<tr class="memdesc:gaad2e7807292d84a5070143626f5c2756"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 2. <a href="#gaad2e7807292d84a5070143626f5c2756"></a><br/></td></tr> +<tr class="separator:gaad2e7807292d84a5070143626f5c2756"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">ARM_NAND_BUS_DDR2_DI_WCYC_4</a>   (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr> +<tr class="memdesc:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 4. <a href="#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"></a><br/></td></tr> +<tr class="separator:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga465ae06a6e097959620346304182e273"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga465ae06a6e097959620346304182e273">ARM_NAND_BUS_DDR2_VEN</a>   (1UL << 16)</td></tr> +<tr class="memdesc:ga465ae06a6e097959620346304182e273"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable external VREFQ as reference. <a href="#ga465ae06a6e097959620346304182e273"></a><br/></td></tr> +<tr class="separator:ga465ae06a6e097959620346304182e273"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad38354e4a34adbf881afc7f89ff06e89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89">ARM_NAND_BUS_DDR2_CMPD</a>   (1UL << 17)</td></tr> +<tr class="memdesc:gad38354e4a34adbf881afc7f89ff06e89"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable complementary DQS (DQS_c) signal. <a href="#gad38354e4a34adbf881afc7f89ff06e89"></a><br/></td></tr> +<tr class="separator:gad38354e4a34adbf881afc7f89ff06e89"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">ARM_NAND_BUS_DDR2_CMPR</a>   (1UL << 18)</td></tr> +<tr class="memdesc:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable complementary RE_n (RE_c) signal. <a href="#ga8a2d599082b9fe56cee1c6454bb3c6a1"></a><br/></td></tr> +<tr class="separator:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>Specify bus mode of the NAND interface. </p> +<p>The defines can be used in the function <a class="el" href="group__nand__interface__gr.html#ga83061d6d53ffb148853efbc87a864607">ARM_NAND_Control</a> for the parameter <em>arg</em> and with the <a class="el" href="group__nand__control__codes.html#ga9b063c3078e86b50d4aa892518b2e2d8">ARM_NAND_BUS_MODE</a> as the <em>control</em> code. </p> +<h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="gac7743aeb6411b97f9fc6a24b556f4963"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_SDR   (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Data Interface: SDR (Single Data Rate) - Traditional interface (default) </p> + +</div> +</div> +<a class="anchor" id="ga82b8261b3d0d85881535adada318a7df"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR   (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Data Interface: NV-DDR (Double Data Rate) </p> + +</div> +</div> +<a class="anchor" id="ga13c102201d6021db184a2f068656c518"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2   (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Data Interface: NV-DDR2 (Double Data Rate) </p> + +</div> +</div> +<a class="anchor" id="ga971e574ac412bbba445055e9afc384ba"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_0   (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Timing Mode 0 (default) </p> + +</div> +</div> +<a class="anchor" id="ga475a339e929eca46e11bc8a7b330aa45"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_1   (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Timing Mode 1. </p> + +</div> +</div> +<a class="anchor" id="gaed6154fb03b5516faf0bfd11d7a46309"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_2   (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Timing Mode 2. </p> + +</div> +</div> +<a class="anchor" id="gacbc4e07e1af6ef0e4c656428e81464a9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_3   (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Timing Mode 3. </p> + +</div> +</div> +<a class="anchor" id="ga709d51a5215cd23ce2d85aec57141456"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_4   (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Timing Mode 4 (SDR EDO capable) </p> + +</div> +</div> +<a class="anchor" id="gaee3cad14ce2b8b9af69149bf74597791"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_5   (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Timing Mode 5 (SDR EDO capable) </p> + +</div> +</div> +<a class="anchor" id="ga4a3524e0eba994b3a66e06cde877f0f6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_6   (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Timing Mode 6 (NV-DDR2 only) </p> + +</div> +</div> +<a class="anchor" id="gaa63d75f5f2b48a7345a066d58de1bd23"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_7   (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>Timing Mode 7 (NV-DDR2 only) </p> + +</div> +</div> +<a class="anchor" id="ga77348df5f5c2c96bcaeec60b6da02c1b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_0   (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Data Output Warm-up cycles: 0 (default) </p> + +</div> +</div> +<a class="anchor" id="ga5839be0b4b2eb930ec039a3403b5e89e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_1   (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Data Output Warm-up cycles: 1. </p> + +</div> +</div> +<a class="anchor" id="ga10a1ef3be69bfa7e6cc657bee751a077"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_2   (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Data Output Warm-up cycles: 2. </p> + +</div> +</div> +<a class="anchor" id="ga7f9e8416c4a4e20c4a04323e39f2100d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_4   (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Data Output Warm-up cycles: 4. </p> + +</div> +</div> +<a class="anchor" id="gaeee1853dea5e96cb19d2596cc0e70169"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_0   (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Data Input Warm-up cycles: 0 (default) </p> + +</div> +</div> +<a class="anchor" id="ga42560a1f046e20cc4956276156c4ce25"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_1   (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Data Input Warm-up cycles: 1. </p> + +</div> +</div> +<a class="anchor" id="gaad2e7807292d84a5070143626f5c2756"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_2   (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Data Input Warm-up cycles: 2. </p> + +</div> +</div> +<a class="anchor" id="ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_4   (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Data Input Warm-up cycles: 4. </p> + +</div> +</div> +<a class="anchor" id="ga465ae06a6e097959620346304182e273"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_VEN   (1UL << 16)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Enable external VREFQ as reference. </p> + +</div> +</div> +<a class="anchor" id="gad38354e4a34adbf881afc7f89ff06e89"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_CMPD   (1UL << 17)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Enable complementary DQS (DQS_c) signal. </p> + +</div> +</div> +<a class="anchor" id="ga8a2d599082b9fe56cee1c6454bb3c6a1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_NAND_BUS_DDR2_CMPR   (1UL << 18)</td> + </tr> + </table> +</div><div class="memdoc"> + +<p>DDR2 Enable complementary RE_n (RE_c) signal. </p> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Tue Oct 27 2015 14:35:25 for CMSIS-Driver by ARM Ltd. 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