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diff --git a/CMSIS/Documentation/Core/html/struct_s_c_b___type.html b/CMSIS/Documentation/Core/html/struct_s_c_b___type.html new file mode 100644 index 0000000..2bc4a47 --- /dev/null +++ b/CMSIS/Documentation/Core/html/struct_s_c_b___type.html @@ -0,0 +1,460 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>SCB_Type Struct Reference</title> +<title>CMSIS-CORE: SCB_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" 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devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.2 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow2" class="tabs2"> + <ul class="tablist"> + <li><a href="annotated.html"><span>Data Structures</span></a></li> + <li><a href="functions.html"><span>Data Fields</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('struct_s_c_b___type.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">SCB_Type Struct Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the System Control Block (SCB). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a21e08d546d8b641bee298a459ea73e46"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a21e08d546d8b641bee298a459ea73e46">CPUID</a></td></tr> +<tr class="memdesc:a21e08d546d8b641bee298a459ea73e46"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/ ) CPUID Base Register. <a href="#a21e08d546d8b641bee298a459ea73e46"></a><br/></td></tr> +<tr class="separator:a21e08d546d8b641bee298a459ea73e46"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">ICSR</a></td></tr> +<tr class="memdesc:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Control and State Register. <a href="#a0ca18ef984d132c6bf4d9b61cd00f05a"></a><br/></td></tr> +<tr class="separator:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a187a4578e920544ed967f98020fb8170"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a187a4578e920544ed967f98020fb8170">VTOR</a></td></tr> +<tr class="memdesc:a187a4578e920544ed967f98020fb8170"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Vector Table Offset Register. <a href="#a187a4578e920544ed967f98020fb8170"></a><br/></td></tr> +<tr class="separator:a187a4578e920544ed967f98020fb8170"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ad3e5b8934c647eb1b7383c1894f01380"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ad3e5b8934c647eb1b7383c1894f01380">AIRCR</a></td></tr> +<tr class="memdesc:ad3e5b8934c647eb1b7383c1894f01380"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Application Interrupt and Reset Control Register. <a href="#ad3e5b8934c647eb1b7383c1894f01380"></a><br/></td></tr> +<tr class="separator:ad3e5b8934c647eb1b7383c1894f01380"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a3a4840c6fa4d1ee75544f4032c88ec34">SCR</a></td></tr> +<tr class="memdesc:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) System Control Register. <a href="#a3a4840c6fa4d1ee75544f4032c88ec34"></a><br/></td></tr> +<tr class="separator:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2d6653b0b70faac936046a02809b577f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a2d6653b0b70faac936046a02809b577f">CCR</a></td></tr> +<tr class="memdesc:a2d6653b0b70faac936046a02809b577f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/W) Configuration Control Register. <a href="#a2d6653b0b70faac936046a02809b577f"></a><br/></td></tr> +<tr class="separator:a2d6653b0b70faac936046a02809b577f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a85768f4b3dbbc41fd760041ee1202162"><td class="memItemLeft" align="right" valign="top">__IOM uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a85768f4b3dbbc41fd760041ee1202162">SHP</a> [12]</td></tr> +<tr class="memdesc:a85768f4b3dbbc41fd760041ee1202162"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) <a href="#a85768f4b3dbbc41fd760041ee1202162"></a><br/></td></tr> +<tr class="separator:a85768f4b3dbbc41fd760041ee1202162"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7b5ae9741a99808043394c4743b635c4"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a7b5ae9741a99808043394c4743b635c4">SHCSR</a></td></tr> +<tr class="memdesc:a7b5ae9741a99808043394c4743b635c4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) System Handler Control and State Register. <a href="#a7b5ae9741a99808043394c4743b635c4"></a><br/></td></tr> +<tr class="separator:a7b5ae9741a99808043394c4743b635c4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0cda9e061b42373383418663092ad19a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a0cda9e061b42373383418663092ad19a">CFSR</a></td></tr> +<tr class="memdesc:a0cda9e061b42373383418663092ad19a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) Configurable Fault Status Register. <a href="#a0cda9e061b42373383418663092ad19a"></a><br/></td></tr> +<tr class="separator:a0cda9e061b42373383418663092ad19a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a14ad254659362b9752c69afe3fd80934"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a14ad254659362b9752c69afe3fd80934">HFSR</a></td></tr> +<tr class="memdesc:a14ad254659362b9752c69afe3fd80934"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02C (R/W) HardFault Status Register. <a href="#a14ad254659362b9752c69afe3fd80934"></a><br/></td></tr> +<tr class="separator:a14ad254659362b9752c69afe3fd80934"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a191579bde0d21ff51d30a714fd887033"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a191579bde0d21ff51d30a714fd887033">DFSR</a></td></tr> +<tr class="memdesc:a191579bde0d21ff51d30a714fd887033"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x030 (R/W) Debug Fault Status Register. <a href="#a191579bde0d21ff51d30a714fd887033"></a><br/></td></tr> +<tr class="separator:a191579bde0d21ff51d30a714fd887033"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a2d03d0b7cec2254f39eb1c46c7445e80">MMFAR</a></td></tr> +<tr class="memdesc:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x034 (R/W) MemManage Fault Address Register. <a href="#a2d03d0b7cec2254f39eb1c46c7445e80"></a><br/></td></tr> +<tr class="separator:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a3f8e7e58be4e41c88dfa78f54589271c"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a3f8e7e58be4e41c88dfa78f54589271c">BFAR</a></td></tr> +<tr class="memdesc:a3f8e7e58be4e41c88dfa78f54589271c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x038 (R/W) BusFault Address Register. <a href="#a3f8e7e58be4e41c88dfa78f54589271c"></a><br/></td></tr> +<tr class="separator:a3f8e7e58be4e41c88dfa78f54589271c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ab65372404ce64b0f0b35e2709429404e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ab65372404ce64b0f0b35e2709429404e">AFSR</a></td></tr> +<tr class="memdesc:ab65372404ce64b0f0b35e2709429404e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x03C (R/W) Auxiliary Fault Status Register. <a href="#ab65372404ce64b0f0b35e2709429404e"></a><br/></td></tr> +<tr class="separator:ab65372404ce64b0f0b35e2709429404e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a681c9d9e518b217976bef38c2423d83d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a681c9d9e518b217976bef38c2423d83d">PFR</a> [2]</td></tr> +<tr class="memdesc:a681c9d9e518b217976bef38c2423d83d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x040 (R/ ) Processor Feature Register. <a href="#a681c9d9e518b217976bef38c2423d83d"></a><br/></td></tr> +<tr class="separator:a681c9d9e518b217976bef38c2423d83d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a85dd6fe77aab17e7ea89a52c59da6004"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a85dd6fe77aab17e7ea89a52c59da6004">DFR</a></td></tr> +<tr class="memdesc:a85dd6fe77aab17e7ea89a52c59da6004"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x048 (R/ ) Debug Feature Register. <a href="#a85dd6fe77aab17e7ea89a52c59da6004"></a><br/></td></tr> +<tr class="separator:a85dd6fe77aab17e7ea89a52c59da6004"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af084e1b2dad004a88668efea1dfe7fa1"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#af084e1b2dad004a88668efea1dfe7fa1">ADR</a></td></tr> +<tr class="memdesc:af084e1b2dad004a88668efea1dfe7fa1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04C (R/ ) Auxiliary Feature Register. <a href="#af084e1b2dad004a88668efea1dfe7fa1"></a><br/></td></tr> +<tr class="separator:af084e1b2dad004a88668efea1dfe7fa1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aa11887804412bda283cc85a83fdafa7c"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#aa11887804412bda283cc85a83fdafa7c">MMFR</a> [4]</td></tr> +<tr class="memdesc:aa11887804412bda283cc85a83fdafa7c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x050 (R/ ) Memory Model Feature Register. <a href="#aa11887804412bda283cc85a83fdafa7c"></a><br/></td></tr> +<tr class="separator:aa11887804412bda283cc85a83fdafa7c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ae0136a2d2d3c45f016b2c449e92b2066"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ae0136a2d2d3c45f016b2c449e92b2066">ISAR</a> [5]</td></tr> +<tr class="memdesc:ae0136a2d2d3c45f016b2c449e92b2066"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x060 (R/ ) Instruction Set Attributes Register. <a href="#ae0136a2d2d3c45f016b2c449e92b2066"></a><br/></td></tr> +<tr class="separator:ae0136a2d2d3c45f016b2c449e92b2066"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac89a5d9901e3748d22a7090bfca2bee6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6">RESERVED0</a> [5]</td></tr> +<tr class="memdesc:ac89a5d9901e3748d22a7090bfca2bee6"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac89a5d9901e3748d22a7090bfca2bee6"></a><br/></td></tr> +<tr class="separator:ac89a5d9901e3748d22a7090bfca2bee6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac6a860c1b8d8154a1f00d99d23b67764"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ac6a860c1b8d8154a1f00d99d23b67764">CPACR</a></td></tr> +<tr class="memdesc:ac6a860c1b8d8154a1f00d99d23b67764"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x088 (R/W) Coprocessor Access Control Register. <a href="#ac6a860c1b8d8154a1f00d99d23b67764"></a><br/></td></tr> +<tr class="separator:ac6a860c1b8d8154a1f00d99d23b67764"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="af084e1b2dad004a88668efea1dfe7fa1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::ADR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ab65372404ce64b0f0b35e2709429404e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::AFSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ad3e5b8934c647eb1b7383c1894f01380"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::AIRCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a3f8e7e58be4e41c88dfa78f54589271c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::BFAR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a2d6653b0b70faac936046a02809b577f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::CCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a0cda9e061b42373383418663092ad19a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::CFSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ac6a860c1b8d8154a1f00d99d23b67764"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::CPACR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a21e08d546d8b641bee298a459ea73e46"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::CPUID</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a85dd6fe77aab17e7ea89a52c59da6004"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::DFR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a191579bde0d21ff51d30a714fd887033"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::DFSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a14ad254659362b9752c69afe3fd80934"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::HFSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a0ca18ef984d132c6bf4d9b61cd00f05a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::ICSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ae0136a2d2d3c45f016b2c449e92b2066"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::ISAR[5]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a2d03d0b7cec2254f39eb1c46c7445e80"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::MMFAR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="aa11887804412bda283cc85a83fdafa7c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::MMFR[4]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a681c9d9e518b217976bef38c2423d83d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::PFR[2]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ac89a5d9901e3748d22a7090bfca2bee6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t SCB_Type::RESERVED0[5]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a3a4840c6fa4d1ee75544f4032c88ec34"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::SCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a7b5ae9741a99808043394c4743b635c4"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::SHCSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a85768f4b3dbbc41fd760041ee1202162"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint8_t SCB_Type::SHP[12]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a187a4578e920544ed967f98020fb8170"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::VTOR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="struct_s_c_b___type.html">SCB_Type</a></li> + <li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2 + --> + </li> + </ul> +</div> +</body> +</html> |