diff options
| author | Dominik Sliwa <dominik.sliwa@toradex.com> | 2016-06-27 13:46:01 +0200 |
|---|---|---|
| committer | Dominik Sliwa <dominik.sliwa@toradex.com> | 2016-06-27 13:46:01 +0200 |
| commit | 44f7d1e90427b2e2cdd69cd9a9cc094a02c5ea56 (patch) | |
| tree | 3c8e786b1774f828da3ba788daeb37f560673cff /startup | |
k20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial commitk20_tester: Initial
commitk20_tester: Initial commit
Diffstat (limited to 'startup')
| -rw-r--r-- | startup/startup_MK20D10.S | 1015 | ||||
| -rw-r--r-- | startup/system_MK20D10.c | 232 | ||||
| -rw-r--r-- | startup/system_MK20D10.h | 166 |
3 files changed, 1413 insertions, 0 deletions
diff --git a/startup/startup_MK20D10.S b/startup/startup_MK20D10.S new file mode 100644 index 0000000..849036b --- /dev/null +++ b/startup/startup_MK20D10.S @@ -0,0 +1,1015 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_MK20D10.s */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* MK20D10 */ +/* @version: 1.8 */ +/* @date: 2014-10-14 */ +/* @build: b151210 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* o Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/ + .long DMA4_IRQHandler /* DMA channel 4 transfer complete*/ + .long DMA5_IRQHandler /* DMA channel 5 transfer complete*/ + .long DMA6_IRQHandler /* DMA channel 6 transfer complete*/ + .long DMA7_IRQHandler /* DMA channel 7 transfer complete*/ + .long DMA8_IRQHandler /* DMA channel 8 transfer complete*/ + .long DMA9_IRQHandler /* DMA channel 9 transfer complete*/ + .long DMA10_IRQHandler /* DMA channel 10 transfer complete*/ + .long DMA11_IRQHandler /* DMA channel 11 transfer complete*/ + .long DMA12_IRQHandler /* DMA channel 12 transfer complete*/ + .long DMA13_IRQHandler /* DMA channel 13 transfer complete*/ + .long DMA14_IRQHandler /* DMA channel 14 transfer complete*/ + .long DMA15_IRQHandler /* DMA channel 15 transfer complete*/ + .long DMA_Error_IRQHandler /* DMA channel 0 - 15 error*/ + .long MCM_IRQHandler /* MCM normal interrupt*/ + .long FTFL_IRQHandler /* FTFL command complete*/ + .long Read_Collision_IRQHandler /* FTFL read collision*/ + .long LVD_LVW_IRQHandler /* PMC controller low-voltage detect, low-voltage warning*/ + .long LLWU_IRQHandler /* Low leakage wakeup*/ + .long WDOG_EWM_IRQHandler /* Single interrupt vector for WDOG and EWM*/ + .long Reserved39_IRQHandler /* Reserved interrupt*/ + .long I2C0_IRQHandler /* Inter-integrated circuit 0*/ + .long I2C1_IRQHandler /* Inter-integrated circuit 1*/ + .long SPI0_IRQHandler /* Serial peripheral Interface 0*/ + .long SPI1_IRQHandler /* Serial peripheral Interface 1*/ + .long SPI2_IRQHandler /* Serial peripheral Interface 1*/ + .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 ORed message buffers*/ + .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off*/ + .long CAN0_Error_IRQHandler /* CAN0 error*/ + .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning*/ + .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning*/ + .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up*/ + .long I2S0_Tx_IRQHandler /* Integrated interchip sound 0 transmit interrupt*/ + .long I2S0_Rx_IRQHandler /* Integrated interchip sound 0 receive interrupt*/ + .long CAN1_ORed_Message_buffer_IRQHandler /* CAN1 OR'd message buffers interrupt*/ + .long CAN1_Bus_Off_IRQHandler /* CAN1 bus off interrupt*/ + .long CAN1_Error_IRQHandler /* CAN1 error interrupt*/ + .long CAN1_Tx_Warning_IRQHandler /* CAN1 Tx warning interrupt*/ + .long CAN1_Rx_Warning_IRQHandler /* CAN1 Rx warning interrupt*/ + .long CAN1_Wake_Up_IRQHandler /* CAN1 wake up interrupt*/ + .long Reserved59_IRQHandler /* Reserved interrupt*/ + .long UART0_LON_IRQHandler /* UART0 LON*/ + .long UART0_RX_TX_IRQHandler /* UART0 receive/transmit interrupt*/ + .long UART0_ERR_IRQHandler /* UART0 error interrupt*/ + .long UART1_RX_TX_IRQHandler /* UART1 receive/transmit interrupt*/ + .long UART1_ERR_IRQHandler /* UART1 error interrupt*/ + .long UART2_RX_TX_IRQHandler /* UART2 receive/transmit interrupt*/ + .long UART2_ERR_IRQHandler /* UART2 error interrupt*/ + .long UART3_RX_TX_IRQHandler /* UART3 receive/transmit interrupt*/ + .long UART3_ERR_IRQHandler /* UART3 error interrupt*/ + .long UART4_RX_TX_IRQHandler /* UART4 receive/transmit interrupt*/ + .long UART4_ERR_IRQHandler /* UART4 error interrupt*/ + .long UART5_RX_TX_IRQHandler /* UART5 receive/transmit interrupt*/ + .long UART5_ERR_IRQHandler /* UART5 error interrupt*/ + .long ADC0_IRQHandler /* Analog-to-digital converter 0*/ + .long ADC1_IRQHandler /* Analog-to-digital converter 1*/ + .long CMP0_IRQHandler /* Comparator 0*/ + .long CMP1_IRQHandler /* Comparator 1*/ + .long CMP2_IRQHandler /* Comparator 2*/ + .long FTM0_IRQHandler /* FlexTimer module 0 fault, overflow and channels interrupt*/ + .long FTM1_IRQHandler /* FlexTimer module 1 fault, overflow and channels interrupt*/ + .long FTM2_IRQHandler /* FlexTimer module 2 fault, overflow and channels interrupt*/ + .long CMT_IRQHandler /* Carrier modulator transmitter*/ + .long RTC_IRQHandler /* Real time clock*/ + .long RTC_Seconds_IRQHandler /* Real time clock seconds*/ + .long PIT0_IRQHandler /* Periodic interrupt timer channel 0*/ + .long PIT1_IRQHandler /* Periodic interrupt timer channel 1*/ + .long PIT2_IRQHandler /* Periodic interrupt timer channel 2*/ + .long PIT3_IRQHandler /* Periodic interrupt timer channel 3*/ + .long PDB0_IRQHandler /* Programmable delay block*/ + .long USB0_IRQHandler /* USB OTG interrupt*/ + .long USBDCD_IRQHandler /* USB charger detect*/ + .long Reserved91_IRQHandler /* Reserved interrupt*/ + .long Reserved92_IRQHandler /* Reserved interrupt*/ + .long Reserved93_IRQHandler /* Reserved interrupt*/ + .long Reserved94_IRQHandler /* Reserved interrupt*/ + .long Reserved95_IRQHandler /* Reserved interrupt*/ + .long SDHC_IRQHandler /* Secured digital host controller*/ + .long DAC0_IRQHandler /* Digital-to-analog converter 0*/ + .long DAC1_IRQHandler /* Digital-to-analog converter 1*/ + .long TSI0_IRQHandler /* TSI0 Interrupt*/ + .long MCG_IRQHandler /* Multipurpose clock generator*/ + .long LPTMR0_IRQHandler /* Low power timer interrupt*/ + .long Reserved102_IRQHandler /* Reserved interrupt*/ + .long PORTA_IRQHandler /* Port A interrupt*/ + .long PORTB_IRQHandler /* Port B interrupt*/ + .long PORTC_IRQHandler /* Port C interrupt*/ + .long PORTD_IRQHandler /* Port D interrupt*/ + .long PORTE_IRQHandler /* Port E interrupt*/ + .long Reserved108_IRQHandler /* Reserved interrupt*/ + .long Reserved109_IRQHandler /* Reserved interrupt*/ + .long SWI_IRQHandler /* Software interrupt*/ + .long Reserved111_IRQHandler /* Reserved interrupt*/ + .long Reserved112_IRQHandler /* Reserved interrupt*/ + .long Reserved113_IRQHandler /* Reserved interrupt*/ + .long Reserved114_IRQHandler /* Reserved interrupt*/ + .long Reserved115_IRQHandler /* Reserved interrupt*/ + .long Reserved116_IRQHandler /* Reserved interrupt*/ + .long Reserved117_IRQHandler /* Reserved interrupt*/ + .long Reserved118_IRQHandler /* Reserved interrupt*/ + .long Reserved119_IRQHandler /* Reserved interrupt*/ + .long DefaultISR /* 120*/ + .long DefaultISR /* 121*/ + .long DefaultISR /* 122*/ + .long DefaultISR /* 123*/ + .long DefaultISR /* 124*/ + .long DefaultISR /* 125*/ + .long DefaultISR /* 126*/ + .long DefaultISR /* 127*/ + .long DefaultISR /* 128*/ + .long DefaultISR /* 129*/ + .long DefaultISR /* 130*/ + .long DefaultISR /* 131*/ + .long DefaultISR /* 132*/ + .long DefaultISR /* 133*/ + .long DefaultISR /* 134*/ + .long DefaultISR /* 135*/ + .long DefaultISR /* 136*/ + .long DefaultISR /* 137*/ + .long DefaultISR /* 138*/ + .long DefaultISR /* 139*/ + .long DefaultISR /* 140*/ + .long DefaultISR /* 141*/ + .long DefaultISR /* 142*/ + .long DefaultISR /* 143*/ + .long DefaultISR /* 144*/ + .long DefaultISR /* 145*/ + .long DefaultISR /* 146*/ + .long DefaultISR /* 147*/ + .long DefaultISR /* 148*/ + .long DefaultISR /* 149*/ + .long DefaultISR /* 150*/ + .long DefaultISR /* 151*/ + .long DefaultISR /* 152*/ + .long DefaultISR /* 153*/ + .long DefaultISR /* 154*/ + .long DefaultISR /* 155*/ + .long DefaultISR /* 156*/ + .long DefaultISR /* 157*/ + .long DefaultISR /* 158*/ + .long DefaultISR /* 159*/ + .long DefaultISR /* 160*/ + .long DefaultISR /* 161*/ + .long DefaultISR /* 162*/ + .long DefaultISR /* 163*/ + .long DefaultISR /* 164*/ + .long DefaultISR /* 165*/ + .long DefaultISR /* 166*/ + .long DefaultISR /* 167*/ + .long DefaultISR /* 168*/ + .long DefaultISR /* 169*/ + .long DefaultISR /* 170*/ + .long DefaultISR /* 171*/ + .long DefaultISR /* 172*/ + .long DefaultISR /* 173*/ + .long DefaultISR /* 174*/ + .long DefaultISR /* 175*/ + .long DefaultISR /* 176*/ + .long DefaultISR /* 177*/ + .long DefaultISR /* 178*/ + .long DefaultISR /* 179*/ + .long DefaultISR /* 180*/ + .long DefaultISR /* 181*/ + .long DefaultISR /* 182*/ + .long DefaultISR /* 183*/ + .long DefaultISR /* 184*/ + .long DefaultISR /* 185*/ + .long DefaultISR /* 186*/ + .long DefaultISR /* 187*/ + .long DefaultISR /* 188*/ + .long DefaultISR /* 189*/ + .long DefaultISR /* 190*/ + .long DefaultISR /* 191*/ + .long DefaultISR /* 192*/ + .long DefaultISR /* 193*/ + .long DefaultISR /* 194*/ + .long DefaultISR /* 195*/ + .long DefaultISR /* 196*/ + .long DefaultISR /* 197*/ + .long DefaultISR /* 198*/ + .long DefaultISR /* 199*/ + .long DefaultISR /* 200*/ + .long DefaultISR /* 201*/ + .long DefaultISR /* 202*/ + .long DefaultISR /* 203*/ + .long DefaultISR /* 204*/ + .long DefaultISR /* 205*/ + .long DefaultISR /* 206*/ + .long DefaultISR /* 207*/ + .long DefaultISR /* 208*/ + .long DefaultISR /* 209*/ + .long DefaultISR /* 210*/ + .long DefaultISR /* 211*/ + .long DefaultISR /* 212*/ + .long DefaultISR /* 213*/ + .long DefaultISR /* 214*/ + .long DefaultISR /* 215*/ + .long DefaultISR /* 216*/ + .long DefaultISR /* 217*/ + .long DefaultISR /* 218*/ + .long DefaultISR /* 219*/ + .long DefaultISR /* 220*/ + .long DefaultISR /* 221*/ + .long DefaultISR /* 222*/ + .long DefaultISR /* 223*/ + .long DefaultISR /* 224*/ + .long DefaultISR /* 225*/ + .long DefaultISR /* 226*/ + .long DefaultISR /* 227*/ + .long DefaultISR /* 228*/ + .long DefaultISR /* 229*/ + .long DefaultISR /* 230*/ + .long DefaultISR /* 231*/ + .long DefaultISR /* 232*/ + .long DefaultISR /* 233*/ + .long DefaultISR /* 234*/ + .long DefaultISR /* 235*/ + .long DefaultISR /* 236*/ + .long DefaultISR /* 237*/ + .long DefaultISR /* 238*/ + .long DefaultISR /* 239*/ + .long DefaultISR /* 240*/ + .long DefaultISR /* 241*/ + .long DefaultISR /* 242*/ + .long DefaultISR /* 243*/ + .long DefaultISR /* 244*/ + .long DefaultISR /* 245*/ + .long DefaultISR /* 246*/ + .long DefaultISR /* 247*/ + .long DefaultISR /* 248*/ + .long DefaultISR /* 249*/ + .long DefaultISR /* 250*/ + .long DefaultISR /* 251*/ + .long DefaultISR /* 252*/ + .long DefaultISR /* 253*/ + .long DefaultISR /* 254*/ + .long 0xFFFFFFFF /* Reserved for user TRIM value*/ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_IRQHandler + .type DMA2_IRQHandler, %function +DMA2_IRQHandler: + ldr r0,=DMA2_DriverIRQHandler + bx r0 + .size DMA2_IRQHandler, . - DMA2_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_IRQHandler + .type DMA3_IRQHandler, %function +DMA3_IRQHandler: + ldr r0,=DMA3_DriverIRQHandler + bx r0 + .size DMA3_IRQHandler, . - DMA3_IRQHandler + + .align 1 + .thumb_func + .weak DMA4_IRQHandler + .type DMA4_IRQHandler, %function +DMA4_IRQHandler: + ldr r0,=DMA4_DriverIRQHandler + bx r0 + .size DMA4_IRQHandler, . - DMA4_IRQHandler + + .align 1 + .thumb_func + .weak DMA5_IRQHandler + .type DMA5_IRQHandler, %function +DMA5_IRQHandler: + ldr r0,=DMA5_DriverIRQHandler + bx r0 + .size DMA5_IRQHandler, . - DMA5_IRQHandler + + .align 1 + .thumb_func + .weak DMA6_IRQHandler + .type DMA6_IRQHandler, %function +DMA6_IRQHandler: + ldr r0,=DMA6_DriverIRQHandler + bx r0 + .size DMA6_IRQHandler, . - DMA6_IRQHandler + + .align 1 + .thumb_func + .weak DMA7_IRQHandler + .type DMA7_IRQHandler, %function +DMA7_IRQHandler: + ldr r0,=DMA7_DriverIRQHandler + bx r0 + .size DMA7_IRQHandler, . - DMA7_IRQHandler + + .align 1 + .thumb_func + .weak DMA8_IRQHandler + .type DMA8_IRQHandler, %function +DMA8_IRQHandler: + ldr r0,=DMA8_DriverIRQHandler + bx r0 + .size DMA8_IRQHandler, . - DMA8_IRQHandler + + .align 1 + .thumb_func + .weak DMA9_IRQHandler + .type DMA9_IRQHandler, %function +DMA9_IRQHandler: + ldr r0,=DMA9_DriverIRQHandler + bx r0 + .size DMA9_IRQHandler, . - DMA9_IRQHandler + + .align 1 + .thumb_func + .weak DMA10_IRQHandler + .type DMA10_IRQHandler, %function +DMA10_IRQHandler: + ldr r0,=DMA10_DriverIRQHandler + bx r0 + .size DMA10_IRQHandler, . - DMA10_IRQHandler + + .align 1 + .thumb_func + .weak DMA11_IRQHandler + .type DMA11_IRQHandler, %function +DMA11_IRQHandler: + ldr r0,=DMA11_DriverIRQHandler + bx r0 + .size DMA11_IRQHandler, . - DMA11_IRQHandler + + .align 1 + .thumb_func + .weak DMA12_IRQHandler + .type DMA12_IRQHandler, %function +DMA12_IRQHandler: + ldr r0,=DMA12_DriverIRQHandler + bx r0 + .size DMA12_IRQHandler, . - DMA12_IRQHandler + + .align 1 + .thumb_func + .weak DMA13_IRQHandler + .type DMA13_IRQHandler, %function +DMA13_IRQHandler: + ldr r0,=DMA13_DriverIRQHandler + bx r0 + .size DMA13_IRQHandler, . - DMA13_IRQHandler + + .align 1 + .thumb_func + .weak DMA14_IRQHandler + .type DMA14_IRQHandler, %function +DMA14_IRQHandler: + ldr r0,=DMA14_DriverIRQHandler + bx r0 + .size DMA14_IRQHandler, . - DMA14_IRQHandler + + .align 1 + .thumb_func + .weak DMA15_IRQHandler + .type DMA15_IRQHandler, %function +DMA15_IRQHandler: + ldr r0,=DMA15_DriverIRQHandler + bx r0 + .size DMA15_IRQHandler, . - DMA15_IRQHandler + + .align 1 + .thumb_func + .weak DMA_Error_IRQHandler + .type DMA_Error_IRQHandler, %function +DMA_Error_IRQHandler: + ldr r0,=DMA_Error_DriverIRQHandler + bx r0 + .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler + + .align 1 + .thumb_func + .weak I2C0_IRQHandler + .type I2C0_IRQHandler, %function +I2C0_IRQHandler: + ldr r0,=I2C0_DriverIRQHandler + bx r0 + .size I2C0_IRQHandler, . - I2C0_IRQHandler + + .align 1 + .thumb_func + .weak I2C1_IRQHandler + .type I2C1_IRQHandler, %function +I2C1_IRQHandler: + ldr r0,=I2C1_DriverIRQHandler + bx r0 + .size I2C1_IRQHandler, . - I2C1_IRQHandler + + .align 1 + .thumb_func + .weak SPI0_IRQHandler + .type SPI0_IRQHandler, %function +SPI0_IRQHandler: + ldr r0,=SPI0_DriverIRQHandler + bx r0 + .size SPI0_IRQHandler, . - SPI0_IRQHandler + + .align 1 + .thumb_func + .weak SPI1_IRQHandler + .type SPI1_IRQHandler, %function +SPI1_IRQHandler: + ldr r0,=SPI1_DriverIRQHandler + bx r0 + .size SPI1_IRQHandler, . - SPI1_IRQHandler + + .align 1 + .thumb_func + .weak SPI2_IRQHandler + .type SPI2_IRQHandler, %function +SPI2_IRQHandler: + ldr r0,=SPI2_DriverIRQHandler + bx r0 + .size SPI2_IRQHandler, . - SPI2_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_ORed_Message_buffer_IRQHandler + .type CAN0_ORed_Message_buffer_IRQHandler, %function +CAN0_ORed_Message_buffer_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_ORed_Message_buffer_IRQHandler, . - CAN0_ORed_Message_buffer_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Bus_Off_IRQHandler + .type CAN0_Bus_Off_IRQHandler, %function +CAN0_Bus_Off_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Bus_Off_IRQHandler, . - CAN0_Bus_Off_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Error_IRQHandler + .type CAN0_Error_IRQHandler, %function +CAN0_Error_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Error_IRQHandler, . - CAN0_Error_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Tx_Warning_IRQHandler + .type CAN0_Tx_Warning_IRQHandler, %function +CAN0_Tx_Warning_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Tx_Warning_IRQHandler, . - CAN0_Tx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Rx_Warning_IRQHandler + .type CAN0_Rx_Warning_IRQHandler, %function +CAN0_Rx_Warning_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Rx_Warning_IRQHandler, . - CAN0_Rx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Wake_Up_IRQHandler + .type CAN0_Wake_Up_IRQHandler, %function +CAN0_Wake_Up_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Wake_Up_IRQHandler, . - CAN0_Wake_Up_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Tx_IRQHandler + .type I2S0_Tx_IRQHandler, %function +I2S0_Tx_IRQHandler: + ldr r0,=I2S0_Tx_DriverIRQHandler + bx r0 + .size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Rx_IRQHandler + .type I2S0_Rx_IRQHandler, %function +I2S0_Rx_IRQHandler: + ldr r0,=I2S0_Rx_DriverIRQHandler + bx r0 + .size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_ORed_Message_buffer_IRQHandler + .type CAN1_ORed_Message_buffer_IRQHandler, %function +CAN1_ORed_Message_buffer_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_ORed_Message_buffer_IRQHandler, . - CAN1_ORed_Message_buffer_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_Bus_Off_IRQHandler + .type CAN1_Bus_Off_IRQHandler, %function +CAN1_Bus_Off_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_Bus_Off_IRQHandler, . - CAN1_Bus_Off_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_Error_IRQHandler + .type CAN1_Error_IRQHandler, %function +CAN1_Error_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_Error_IRQHandler, . - CAN1_Error_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_Tx_Warning_IRQHandler + .type CAN1_Tx_Warning_IRQHandler, %function +CAN1_Tx_Warning_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_Tx_Warning_IRQHandler, . - CAN1_Tx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_Rx_Warning_IRQHandler + .type CAN1_Rx_Warning_IRQHandler, %function +CAN1_Rx_Warning_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_Rx_Warning_IRQHandler, . - CAN1_Rx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_Wake_Up_IRQHandler + .type CAN1_Wake_Up_IRQHandler, %function +CAN1_Wake_Up_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_Wake_Up_IRQHandler, . - CAN1_Wake_Up_IRQHandler + + .align 1 + .thumb_func + .weak UART0_LON_IRQHandler + .type UART0_LON_IRQHandler, %function +UART0_LON_IRQHandler: + ldr r0,=UART0_LON_DriverIRQHandler + bx r0 + .size UART0_LON_IRQHandler, . - UART0_LON_IRQHandler + + .align 1 + .thumb_func + .weak UART0_RX_TX_IRQHandler + .type UART0_RX_TX_IRQHandler, %function +UART0_RX_TX_IRQHandler: + ldr r0,=UART0_RX_TX_DriverIRQHandler + bx r0 + .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART0_ERR_IRQHandler + .type UART0_ERR_IRQHandler, %function +UART0_ERR_IRQHandler: + ldr r0,=UART0_ERR_DriverIRQHandler + bx r0 + .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART1_RX_TX_IRQHandler + .type UART1_RX_TX_IRQHandler, %function +UART1_RX_TX_IRQHandler: + ldr r0,=UART1_RX_TX_DriverIRQHandler + bx r0 + .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART1_ERR_IRQHandler + .type UART1_ERR_IRQHandler, %function +UART1_ERR_IRQHandler: + ldr r0,=UART1_ERR_DriverIRQHandler + bx r0 + .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART2_RX_TX_IRQHandler + .type UART2_RX_TX_IRQHandler, %function +UART2_RX_TX_IRQHandler: + ldr r0,=UART2_RX_TX_DriverIRQHandler + bx r0 + .size UART2_RX_TX_IRQHandler, . - UART2_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART2_ERR_IRQHandler + .type UART2_ERR_IRQHandler, %function +UART2_ERR_IRQHandler: + ldr r0,=UART2_ERR_DriverIRQHandler + bx r0 + .size UART2_ERR_IRQHandler, . - UART2_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART3_RX_TX_IRQHandler + .type UART3_RX_TX_IRQHandler, %function +UART3_RX_TX_IRQHandler: + ldr r0,=UART3_RX_TX_DriverIRQHandler + bx r0 + .size UART3_RX_TX_IRQHandler, . - UART3_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART3_ERR_IRQHandler + .type UART3_ERR_IRQHandler, %function +UART3_ERR_IRQHandler: + ldr r0,=UART3_ERR_DriverIRQHandler + bx r0 + .size UART3_ERR_IRQHandler, . - UART3_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART4_RX_TX_IRQHandler + .type UART4_RX_TX_IRQHandler, %function +UART4_RX_TX_IRQHandler: + ldr r0,=UART4_RX_TX_DriverIRQHandler + bx r0 + .size UART4_RX_TX_IRQHandler, . - UART4_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART4_ERR_IRQHandler + .type UART4_ERR_IRQHandler, %function +UART4_ERR_IRQHandler: + ldr r0,=UART4_ERR_DriverIRQHandler + bx r0 + .size UART4_ERR_IRQHandler, . - UART4_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART5_RX_TX_IRQHandler + .type UART5_RX_TX_IRQHandler, %function +UART5_RX_TX_IRQHandler: + ldr r0,=UART5_RX_TX_DriverIRQHandler + bx r0 + .size UART5_RX_TX_IRQHandler, . - UART5_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART5_ERR_IRQHandler + .type UART5_ERR_IRQHandler, %function +UART5_ERR_IRQHandler: + ldr r0,=UART5_ERR_DriverIRQHandler + bx r0 + .size UART5_ERR_IRQHandler, . - UART5_ERR_IRQHandler + + .align 1 + .thumb_func + .weak SDHC_IRQHandler + .type SDHC_IRQHandler, %function +SDHC_IRQHandler: + ldr r0,=SDHC_DriverIRQHandler + bx r0 + .size SDHC_IRQHandler, . - SDHC_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler DMA2_DriverIRQHandler + def_irq_handler DMA3_DriverIRQHandler + def_irq_handler DMA4_DriverIRQHandler + def_irq_handler DMA5_DriverIRQHandler + def_irq_handler DMA6_DriverIRQHandler + def_irq_handler DMA7_DriverIRQHandler + def_irq_handler DMA8_DriverIRQHandler + def_irq_handler DMA9_DriverIRQHandler + def_irq_handler DMA10_DriverIRQHandler + def_irq_handler DMA11_DriverIRQHandler + def_irq_handler DMA12_DriverIRQHandler + def_irq_handler DMA13_DriverIRQHandler + def_irq_handler DMA14_DriverIRQHandler + def_irq_handler DMA15_DriverIRQHandler + def_irq_handler DMA_Error_DriverIRQHandler + def_irq_handler MCM_IRQHandler + def_irq_handler FTFL_IRQHandler + def_irq_handler Read_Collision_IRQHandler + def_irq_handler LVD_LVW_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler WDOG_EWM_IRQHandler + def_irq_handler Reserved39_IRQHandler + def_irq_handler I2C0_DriverIRQHandler + def_irq_handler I2C1_DriverIRQHandler + def_irq_handler SPI0_DriverIRQHandler + def_irq_handler SPI1_DriverIRQHandler + def_irq_handler SPI2_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler I2S0_Tx_DriverIRQHandler + def_irq_handler I2S0_Rx_DriverIRQHandler + def_irq_handler CAN1_DriverIRQHandler + def_irq_handler Reserved59_IRQHandler + def_irq_handler UART0_LON_DriverIRQHandler + def_irq_handler UART0_RX_TX_DriverIRQHandler + def_irq_handler UART0_ERR_DriverIRQHandler + def_irq_handler UART1_RX_TX_DriverIRQHandler + def_irq_handler UART1_ERR_DriverIRQHandler + def_irq_handler UART2_RX_TX_DriverIRQHandler + def_irq_handler UART2_ERR_DriverIRQHandler + def_irq_handler UART3_RX_TX_DriverIRQHandler + def_irq_handler UART3_ERR_DriverIRQHandler + def_irq_handler UART4_RX_TX_DriverIRQHandler + def_irq_handler UART4_ERR_DriverIRQHandler + def_irq_handler UART5_RX_TX_DriverIRQHandler + def_irq_handler UART5_ERR_DriverIRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler CMP1_IRQHandler + def_irq_handler CMP2_IRQHandler + def_irq_handler FTM0_IRQHandler + def_irq_handler FTM1_IRQHandler + def_irq_handler FTM2_IRQHandler + def_irq_handler CMT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT0_IRQHandler + def_irq_handler PIT1_IRQHandler + def_irq_handler PIT2_IRQHandler + def_irq_handler PIT3_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler USBDCD_IRQHandler + def_irq_handler Reserved91_IRQHandler + def_irq_handler Reserved92_IRQHandler + def_irq_handler Reserved93_IRQHandler + def_irq_handler Reserved94_IRQHandler + def_irq_handler Reserved95_IRQHandler + def_irq_handler SDHC_DriverIRQHandler + def_irq_handler DAC0_IRQHandler + def_irq_handler DAC1_IRQHandler + def_irq_handler TSI0_IRQHandler + def_irq_handler MCG_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler Reserved102_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTB_IRQHandler + def_irq_handler PORTC_IRQHandler + def_irq_handler PORTD_IRQHandler + def_irq_handler PORTE_IRQHandler + def_irq_handler Reserved108_IRQHandler + def_irq_handler Reserved109_IRQHandler + def_irq_handler SWI_IRQHandler + def_irq_handler Reserved111_IRQHandler + def_irq_handler Reserved112_IRQHandler + def_irq_handler Reserved113_IRQHandler + def_irq_handler Reserved114_IRQHandler + def_irq_handler Reserved115_IRQHandler + def_irq_handler Reserved116_IRQHandler + def_irq_handler Reserved117_IRQHandler + def_irq_handler Reserved118_IRQHandler + def_irq_handler Reserved119_IRQHandler + + .end diff --git a/startup/system_MK20D10.c b/startup/system_MK20D10.c new file mode 100644 index 0000000..a4d9140 --- /dev/null +++ b/startup/system_MK20D10.c @@ -0,0 +1,232 @@ +/* +** ################################################################### +** Processors: MK20DN512VLK10 +** MK20DN512VLL10 +** MK20DN512VLQ10 +** MK20DN512VMC10 +** MK20DN512VMD10 +** MK20DX128VLQ10 +** MK20DX128VMD10 +** MK20DX256VLK10 +** MK20DX256VLL10 +** MK20DX256VLQ10 +** MK20DX256VMC10 +** MK20DX256VMD10 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K20P144M100SF2V2RM Rev. 2, Jun 2012 +** Version: rev. 1.9, 2015-07-29 +** Build: b151217 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2012-01-03) +** Initial version +** - rev. 1.1 (2012-04-13) +** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR. +** Added new #define symbols <peripheralType>_BASE_PTRS. +** - rev. 1.2 (2012-07-09) +** UART0 - Fixed register definition - CEA709.1-B (LON) registers added. +** - rev. 1.3 (2012-10-29) +** Registers updated according to the new reference manual revision - Rev. 2, Jun 2012 +** - rev. 1.4 (2013-04-05) +** Changed start of doxygen comment. +** - rev. 1.5 (2013-06-24) +** NV_FOPT register - NMI_DIS bit added. +** SPI - PCSIS bit group in MCR register updated. +** - rev. 1.6 (2014-07-23) +** Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. +** Predefined SystemInit() implementation updated: +** - External clock sources available on TWR board used. +** - Added 1 ms waiting loop after entering FLL engaged MCG mode. +** - rev. 1.7 (2014-08-28) +** Update of startup files - possibility to override DefaultISR added. +** - rev. 1.8 (2014-10-14) +** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0 +** - rev. 1.9 (2015-07-29) +** Correction of backward compatibility. +** +** ################################################################### +*/ + +/*! + * @file MK20D10 + * @version 1.9 + * @date 2015-07-29 + * @brief Device specific configuration file for MK20D10 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include <stdint.h> +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { + + /* Watchdog disable */ +#if (DISABLE_WDOG) + /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ + WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ + /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ + WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ + /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | + WDOG_STCTRLH_WAITEN_MASK | + WDOG_STCTRLH_STOPEN_MASK | + WDOG_STCTRLH_ALLOWUPDATE_MASK | + WDOG_STCTRLH_CLKSRC_MASK | + 0x0100U; +#endif /* (DISABLE_WDOG) */ + +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint16_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { + /* External reference clock is selected */ + if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } + if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { + switch (MCG->C1 & MCG_C1_FRDIV_MASK) { + case 0x38U: + Divider = 1536U; + break; + case 0x30U: + Divider = 1280U; + break; + default: + Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + break; + } + } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ + Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + } + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x00U: + MCGOUTClock *= 640U; + break; + case 0x20U: + MCGOUTClock *= 1280U; + break; + case 0x40U: + MCGOUTClock *= 1920U; + break; + case 0x60U: + MCGOUTClock *= 2560U; + break; + case 0x80U: + MCGOUTClock *= 732U; + break; + case 0xA0U: + MCGOUTClock *= 1464U; + break; + case 0xC0U: + MCGOUTClock *= 2197U; + break; + case 0xE0U: + MCGOUTClock *= 2929U; + break; + default: + break; + } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + /* PLL is selected */ + Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { + /* External reference clock is selected */ + if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) { + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + } else { + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + } + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); + +} diff --git a/startup/system_MK20D10.h b/startup/system_MK20D10.h new file mode 100644 index 0000000..30d9c76 --- /dev/null +++ b/startup/system_MK20D10.h @@ -0,0 +1,166 @@ +/* +** ################################################################### +** Processors: MK20DN512VLK10 +** MK20DN512VLL10 +** MK20DN512VLQ10 +** MK20DN512VMC10 +** MK20DN512VMD10 +** MK20DX128VLQ10 +** MK20DX128VMD10 +** MK20DX256VLK10 +** MK20DX256VLL10 +** MK20DX256VLQ10 +** MK20DX256VMC10 +** MK20DX256VMD10 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K20P144M100SF2V2RM Rev. 2, Jun 2012 +** Version: rev. 1.9, 2015-07-29 +** Build: b151217 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2012-01-03) +** Initial version +** - rev. 1.1 (2012-04-13) +** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR. +** Added new #define symbols <peripheralType>_BASE_PTRS. +** - rev. 1.2 (2012-07-09) +** UART0 - Fixed register definition - CEA709.1-B (LON) registers added. +** - rev. 1.3 (2012-10-29) +** Registers updated according to the new reference manual revision - Rev. 2, Jun 2012 +** - rev. 1.4 (2013-04-05) +** Changed start of doxygen comment. +** - rev. 1.5 (2013-06-24) +** NV_FOPT register - NMI_DIS bit added. +** SPI - PCSIS bit group in MCR register updated. +** - rev. 1.6 (2014-07-23) +** Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. +** Predefined SystemInit() implementation updated: +** - External clock sources available on TWR board used. +** - Added 1 ms waiting loop after entering FLL engaged MCG mode. +** - rev. 1.7 (2014-08-28) +** Update of startup files - possibility to override DefaultISR added. +** - rev. 1.8 (2014-10-14) +** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0 +** - rev. 1.9 (2015-07-29) +** Correction of backward compatibility. +** +** ################################################################### +*/ + +/*! + * @file MK20D10 + * @version 1.9 + * @date 2015-07-29 + * @brief Device specific configuration file for MK20D10 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MK20D10_H_ +#define _SYSTEM_MK20D10_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + + + + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 8000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */ +#define CPU_XTAL32k_CLK_HZ 32768U /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */ + +/* Low power mode enable */ +/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ +#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ + +#define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MK20D10_H_ */ |