diff options
| author | Stefan Agner <stefan@agner.ch> | 2016-05-02 19:13:19 -0700 |
|---|---|---|
| committer | Stefan Agner <stefan@agner.ch> | 2016-05-09 17:17:05 -0700 |
| commit | 21d6d84123de8e6e2ebdf5543b530403951b3059 (patch) | |
| tree | 046a7fa39e1c7cff49792ac67f1ae899271a56b7 /platform | |
| parent | 2fb8ccd4adf6433033a402e2fa07c2f11c489518 (diff) | |
resync with FreeRTOS_BSP_1.0.1_iMX7D
Diffstat (limited to 'platform')
47 files changed, 14736 insertions, 65718 deletions
diff --git a/platform/devices/MCIMX7D/include/MCIMX7D_M4.h b/platform/devices/MCIMX7D/include/MCIMX7D_M4.h index 87670aa..7bb2f15 100644 --- a/platform/devices/MCIMX7D/include/MCIMX7D_M4.h +++ b/platform/devices/MCIMX7D/include/MCIMX7D_M4.h @@ -9,11 +9,11 @@ ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: -** Version: rev. 1.0, 2015-04-23 -** Build: b150423 +** Version: rev. 1.0, 2015-07-15 +** Build: b150715 ** ** Abstract: -** CMSIS Peripheral Access Layer for iMX7D +** CMSIS Peripheral Access Layer for MCIMX7D_M4 ** ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. ** All rights reserved. @@ -47,8 +47,8 @@ ** mail: support@freescale.com ** ** Revisions: -** - rev. 1.0 (2015-04-23) -** Initial version by Wang Ge. +** - rev. 1.0 (2015-07-15) +** Initial version . ** ** ################################################################### */ @@ -56,7 +56,7 @@ /*! * @file MCIMX7D_M4.h * @version 1.0 - * @date 2015-04-23 + * @date 2015-07-15 * @brief CMSIS Peripheral Access Layer for MCIMX7D_M4 * * CMSIS Peripheral Access Layer for MCIMX7D_M4 @@ -86,6 +86,7 @@ /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000u + /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ @@ -96,7 +97,7 @@ */ /** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 16 /**< Number of interrupts in the Vector table */ +#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ @@ -118,14 +119,14 @@ typedef enum IRQn { DAP_IRQn = 1, /**< DAP Interrupt */ SDMA_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */ DBGMON_IRQn = 3, /**< DBGMON Sync Interrupt */ - SNVS_IRQn = 4, /**< WRAPPER ON-OFF button press shorter than 5 seconds (pulse event) */ + SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */ LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */ SIM2_IRQn = 6, /**< SIM Interrupt */ CSI_IRQn = 7, /**< CSI Interrupt */ PXP1_IRQn = 8, /**< PXP Interrupt */ Reserved_IRQn = 9, /**< Reserved */ WDOG3_IRQn = 10, /**< Watchdog Timer reset */ - HS1_IRQn = 11, /**< SEMA4-HS M4 Interrupt Request */ + SEMA4_HS_M4_IRQn = 11, /**< SEMA4-HS M4 Interrupt Request */ APBHDMA_IRQn = 12, /**< GPMI operation channel 0 description complete interrupt */ EIM_IRQn = 13, /**< EIM Interrupt */ BCH_IRQn = 14, /**< BCH operation complete interrupt */ @@ -136,9 +137,9 @@ typedef enum IRQn { SNVS_CONSOLIDATED_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */ SNVS_SECURITY_IRQn = 20, /**< SRTC Security Interrupt. TZ. */ CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted */ - USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ - USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ - USDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */ + uSDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ + uSDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ + uSDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */ MIPI_CSI_IRQn = 25, /**< MIPI CSI interrupt */ UART1_IRQn = 26, /**< UART-1 ORed interrupt */ UART2_IRQn = 27, /**< UART-2 ORed interrupt */ @@ -199,21 +200,21 @@ typedef enum IRQn { PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ - CCM_INT1_IRQn = 85, /**< CCM, Interrupt Request 1 */ - CCM_INT2_IRQn = 86, /**< CCM, Interrupt Request 2 */ + CCM1_IRQn = 85, /**< CCM, Interrupt Request 1 */ + CCM2_IRQn = 86, /**< CCM, Interrupt Request 2 */ GPC_IRQn = 87, /**< GPC Interrupt Request 1 */ - MU_IRQn = 88, /**< Interrupt to A7 */ + MU_A7_IRQn = 88, /**< Interrupt to A7 */ SRC_IRQn = 89, /**< SRC interrupt request */ SIM1_IRQn = 90, /**< Sim Interrupt */ RTIC_IRQn = 91, /**< RTIC Interrupt */ - CPU_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[0]) */ - /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[1]) */ - CPU_CTI_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[0]) */ - /**< CTI trigger outputs (internal: nCTIIRQ[1]) */ + CPU_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[0]) + Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[1]) */ + CPU_CTI_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[0]) + CTI trigger outputs (internal: nCTIIRQ[1]) */ CCM_SRC_GPC_IRQn = 94, /**< SRC GPC Combined CPU wdog interrupts (4x) out of SRC. */ SAI1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */ SAI2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */ - MU_INT_M4_IRQn = 97, /**< Interrupt to M4 */ + MU_M4_IRQn = 97, /**< Interrupt to M4 */ ADC1_IRQn = 98, /**< ADC-1 Interrupt */ ADC2_IRQn = 99, /**< ADC-2 Interrupt */ ENET2_MAC0_TRANS1_IRQn = 100, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ @@ -232,7 +233,7 @@ typedef enum IRQn { PERFMON2_IRQn = 113, /**< General interrupt */ CAAM_WRAPPER1_IRQn = 114, /**< CAAM interrupt queue for JQ */ CAAM_WRAPPER2_IRQn = 115, /**< Recoverable error interrupt */ - HS0_IRQn = 116, /**< SEMA4-HS processor A7 Interrupt Request */ + SEMA4_HS_A7_IRQn = 116, /**< SEMA4-HS processor A7 Interrupt Request */ EPDC_IRQn = 117, /**< EPDC Interrupt */ ENET1_MAC0_TRANS1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ ENET1_MAC0_TRANS2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ @@ -250,7 +251,6 @@ typedef enum IRQn { * @} */ /* end of group Interrupt_vector_numbers */ - /* ---------------------------------------------------------------------------- -- Cortex M4 Core Configuration ---------------------------------------------------------------------------- */ @@ -260,7 +260,7 @@ typedef enum IRQn { * @{ */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ @@ -271,8 +271,8 @@ typedef enum IRQn { /*! * @} */ /* end of group Cortex_Core_Configuration */ - - + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -290,9 +290,6 @@ typedef enum IRQn { #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) @@ -300,7 +297,6 @@ typedef enum IRQn { #else #error Not supported compiler type #endif - /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -352,7 +348,6 @@ typedef struct { uint8_t RESERVED_18[12]; __IO uint32_t ADC_CFG; /**< ADC Configuration, offset: 0x130 */ } ADC_Type, *ADC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- ADC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -388,8 +383,6 @@ typedef struct { /*! * @} */ /* end of group ADC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ @@ -706,7 +699,6 @@ typedef struct { * @} */ /* end of group ADC_Register_Masks */ - /* ADC - Peripheral instance base addresses */ /** Peripheral ADC1 base address */ #define ADC1_BASE (0x30610000u) @@ -718,11 +710,12 @@ typedef struct { /** Peripheral ADC2 base pointer */ #define ADC2 ((ADC_Type *)ADC2_BASE) #define ADC2_BASE_PTR (ADC2) -/** Array initializer of ADC peripheral base adresses */ +/** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC1_BASE, ADC2_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC1, ADC2 } - +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC1_IRQn, ADC2_IRQn } /* ---------------------------------------------------------------------------- -- ADC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -776,7 +769,6 @@ typedef struct { #define ADC2_CH_SW_CNV_RSLT ADC_CH_SW_CNV_RSLT_REG(ADC2_BASE_PTR) #define ADC2_DMA_FIFO_DAT ADC_DMA_FIFO_DAT_REG(ADC2_BASE_PTR) #define ADC2_ADC_CFG ADC_ADC_CFG_REG(ADC2_BASE_PTR) - /*! * @} */ /* end of group ADC_Register_Accessor_Macros */ @@ -786,7 +778,6 @@ typedef struct { * @} */ /* end of group ADC_Peripheral */ - /* ---------------------------------------------------------------------------- -- APBH Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -835,10 +826,9 @@ typedef struct { uint8_t RESERVED_5[12]; __IO uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */ uint8_t RESERVED_6[12]; - } CH_[16]; + } CH[16]; __IO uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ } APBH_Type, *APBH_MemMapPtr; - /* ---------------------------------------------------------------------------- -- APBH - Register accessor macros ---------------------------------------------------------------------------- */ @@ -869,20 +859,18 @@ typedef struct { #define APBH_DEVSEL_REG(base) ((base)->DEVSEL) #define APBH_DMA_BURST_SIZE_REG(base) ((base)->DMA_BURST_SIZE) #define APBH_DEBUG_REG(base) ((base)->DEBUG) -#define APBH_CH_CURCMDAR_REG(base,index) ((base)->CH_[index].CH_CURCMDAR) -#define APBH_CH_NXTCMDAR_REG(base,index) ((base)->CH_[index].CH_NXTCMDAR) -#define APBH_CH_CMD_REG(base,index) ((base)->CH_[index].CH_CMD) -#define APBH_CH_BAR_REG(base,index) ((base)->CH_[index].CH_BAR) -#define APBH_CH_SEMA_REG(base,index) ((base)->CH_[index].CH_SEMA) -#define APBH_CH_DEBUG1_REG(base,index) ((base)->CH_[index].CH_DEBUG1) -#define APBH_CH_DEBUG2_REG(base,index) ((base)->CH_[index].CH_DEBUG2) +#define APBH_CH_CURCMDAR_REG(base,index) ((base)->CH[index].CH_CURCMDAR) +#define APBH_CH_NXTCMDAR_REG(base,index) ((base)->CH[index].CH_NXTCMDAR) +#define APBH_CH_CMD_REG(base,index) ((base)->CH[index].CH_CMD) +#define APBH_CH_BAR_REG(base,index) ((base)->CH[index].CH_BAR) +#define APBH_CH_SEMA_REG(base,index) ((base)->CH[index].CH_SEMA) +#define APBH_CH_DEBUG1_REG(base,index) ((base)->CH[index].CH_DEBUG1) +#define APBH_CH_DEBUG2_REG(base,index) ((base)->CH[index].CH_DEBUG2) #define APBH_VERSION_REG(base) ((base)->VERSION) /*! * @} */ /* end of group APBH_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- APBH Register Masks ---------------------------------------------------------------------------- */ @@ -1697,18 +1685,18 @@ typedef struct { * @} */ /* end of group APBH_Register_Masks */ - /* APBH - Peripheral instance base addresses */ /** Peripheral APBH base address */ #define APBH_BASE (0x33000000u) /** Peripheral APBH base pointer */ #define APBH ((APBH_Type *)APBH_BASE) #define APBH_BASE_PTR (APBH) -/** Array initializer of APBH peripheral base adresses */ +/** Array initializer of APBH peripheral base addresses */ #define APBH_BASE_ADDRS { APBH_BASE } /** Array initializer of APBH peripheral base pointers */ #define APBH_BASE_PTRS { APBH } - +/** Interrupt vectors for the APBH peripheral type */ +#define APBH_IRQS { APBHDMA_IRQn } /* ---------------------------------------------------------------------------- -- APBH - Register accessor macros ---------------------------------------------------------------------------- */ @@ -1853,7 +1841,6 @@ typedef struct { #define APBH_CH15_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,15) #define APBH_CH15_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,15) #define APBH_VERSION APBH_VERSION_REG(APBH_BASE_PTR) - /* APBH - Register array accessors */ #define APBH_CH_CURCMDAR(index) APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,index) #define APBH_CH_NXTCMDAR(index) APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,index) @@ -1862,7 +1849,6 @@ typedef struct { #define APBH_CH_SEMA(index) APBH_CH_SEMA_REG(APBH_BASE_PTR,index) #define APBH_CH_DEBUG1(index) APBH_CH_DEBUG1_REG(APBH_BASE_PTR,index) #define APBH_CH_DEBUG2(index) APBH_CH_DEBUG2_REG(APBH_BASE_PTR,index) - /*! * @} */ /* end of group APBH_Register_Accessor_Macros */ @@ -1872,7 +1858,6 @@ typedef struct { * @} */ /* end of group APBH_Peripheral */ - /* ---------------------------------------------------------------------------- -- BCH Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -1973,12 +1958,11 @@ typedef struct { __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ - __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ - __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ - __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ - __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ + __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1 , offset: 0x170 */ + __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1 , offset: 0x174 */ + __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1 , offset: 0x178 */ + __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1 , offset: 0x17C */ } BCH_Type, *BCH_MemMapPtr; - /* ---------------------------------------------------------------------------- -- BCH - Register accessor macros ---------------------------------------------------------------------------- */ @@ -2086,8 +2070,6 @@ typedef struct { /*! * @} */ /* end of group BCH_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- BCH Register Masks ---------------------------------------------------------------------------- */ @@ -3326,18 +3308,18 @@ typedef struct { * @} */ /* end of group BCH_Register_Masks */ - /* BCH - Peripheral instance base addresses */ /** Peripheral BCH base address */ #define BCH_BASE (0x33004000u) /** Peripheral BCH base pointer */ #define BCH ((BCH_Type *)BCH_BASE) #define BCH_BASE_PTR (BCH) -/** Array initializer of BCH peripheral base adresses */ +/** Array initializer of BCH peripheral base addresses */ #define BCH_BASE_ADDRS { BCH_BASE } /** Array initializer of BCH peripheral base pointers */ #define BCH_BASE_PTRS { BCH } - +/** Interrupt vectors for the BCH peripheral type */ +#define BCH_IRQS { BCH_IRQn } /* ---------------------------------------------------------------------------- -- BCH - Register accessor macros ---------------------------------------------------------------------------- */ @@ -3442,7 +3424,6 @@ typedef struct { #define BCH_DEBUG1_SET BCH_DEBUG1_SET_REG(BCH_BASE_PTR) #define BCH_DEBUG1_CLR BCH_DEBUG1_CLR_REG(BCH_BASE_PTR) #define BCH_DEBUG1_TOG BCH_DEBUG1_TOG_REG(BCH_BASE_PTR) - /*! * @} */ /* end of group BCH_Register_Accessor_Macros */ @@ -3452,7 +3433,6 @@ typedef struct { * @} */ /* end of group BCH_Peripheral */ - /* ---------------------------------------------------------------------------- -- CAN Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -3464,40 +3444,39 @@ typedef struct { /** CAN - Register Layout Typedef */ typedef struct { - __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ - __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ - __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ - __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ - __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ - __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ - __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ - __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ - __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ - __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ - __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ - __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ - __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ - uint8_t RESERVED_1[8]; - __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ - __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ - __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ - uint8_t RESERVED_2[48]; - struct { /**< offset: 0x80, array step: 0x10 */ - __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ - __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ - __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ - __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ - } MB[64]; - uint8_t RESERVED_3[1024]; - __IO uint32_t RXIMR[64]; /**< RX Individual Mask Registers, array offset: 0x880, array step: 0x4 */ - uint8_t RESERVED_4[96]; - __IO uint32_t GFWR; /**< Glitch Filter Width Registers, Address: Base address + 9E0h offset */ + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[48]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_3[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_4[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ } CAN_Type, *CAN_MemMapPtr; - /* ---------------------------------------------------------------------------- - -- FLEXCAN - Register accessor macros + -- CAN - Register accessor macros ---------------------------------------------------------------------------- */ /*! @@ -3506,7 +3485,7 @@ typedef struct { */ -/* FLEXCAN - Register accessors */ +/* CAN - Register accessors */ #define CAN_MCR_REG(base) ((base)->MCR) #define CAN_CTRL1_REG(base) ((base)->CTRL1) #define CAN_TIMER_REG(base) ((base)->TIMER) @@ -3539,8 +3518,6 @@ typedef struct { /*! * @} */ /* end of group CAN_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ @@ -3816,7 +3793,6 @@ typedef struct { * @} */ /* end of group CAN_Register_Masks */ - /* CAN - Peripheral instance base addresses */ /** Peripheral CAN1 base address */ #define CAN1_BASE (0x30A00000u) @@ -3832,7 +3808,8 @@ typedef struct { #define CAN_BASE_ADDRS { CAN1_BASE, CAN2_BASE } /** Array initializer of CAN peripheral base pointers */ #define CAN_BASE_PTRS { CAN1, CAN2 } - +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_IRQS { FLEXCAN1_IRQn, FLEXCAN2_IRQn } /* ---------------------------------------------------------------------------- -- CAN - Register accessor macros ---------------------------------------------------------------------------- */ @@ -3843,7 +3820,7 @@ typedef struct { */ -/* FLEXCAN - Register instance definitions */ +/* CAN - Register instance definitions */ /* CAN1 */ #define CAN1_MCR CAN_MCR_REG(CAN1_BASE_PTR) #define CAN1_CTRL1 CAN_CTRL1_REG(CAN1_BASE_PTR) @@ -3862,11 +3839,326 @@ typedef struct { #define CAN1_CRCR CAN_CRCR_REG(CAN1_BASE_PTR) #define CAN1_RXFGMASK CAN_RXFGMASK_REG(CAN1_BASE_PTR) #define CAN1_RXFIR CAN_RXFIR_REG(CAN1_BASE_PTR) -#define CAN1_CS(index) CAN_CS_REG(CAN1,index) -#define CAN1_ID(index) CAN_ID_REG(CAN1,index) -#define CAN1_WORD0(index) CAN_WORD0_REG(CAN1,index) -#define CAN1_WORD1(index) CAN_WORD1_REG(CAN1,index) -#define CAN1_RXIMR(index) CAN_RXIMR_REG(CAN1,index) +#define CAN1_CS0 CAN_CS_REG(CAN1_BASE_PTR,0) +#define CAN1_ID0 CAN_ID_REG(CAN1_BASE_PTR,0) +#define CAN1_WORD00 CAN_WORD0_REG(CAN1_BASE_PTR,0) +#define CAN1_WORD10 CAN_WORD1_REG(CAN1_BASE_PTR,0) +#define CAN1_CS1 CAN_CS_REG(CAN1_BASE_PTR,1) +#define CAN1_ID1 CAN_ID_REG(CAN1_BASE_PTR,1) +#define CAN1_WORD01 CAN_WORD0_REG(CAN1_BASE_PTR,1) +#define CAN1_WORD11 CAN_WORD1_REG(CAN1_BASE_PTR,1) +#define CAN1_CS2 CAN_CS_REG(CAN1_BASE_PTR,2) +#define CAN1_ID2 CAN_ID_REG(CAN1_BASE_PTR,2) +#define CAN1_WORD02 CAN_WORD0_REG(CAN1_BASE_PTR,2) +#define CAN1_WORD12 CAN_WORD1_REG(CAN1_BASE_PTR,2) +#define CAN1_CS3 CAN_CS_REG(CAN1_BASE_PTR,3) +#define CAN1_ID3 CAN_ID_REG(CAN1_BASE_PTR,3) +#define CAN1_WORD03 CAN_WORD0_REG(CAN1_BASE_PTR,3) +#define CAN1_WORD13 CAN_WORD1_REG(CAN1_BASE_PTR,3) +#define CAN1_CS4 CAN_CS_REG(CAN1_BASE_PTR,4) +#define CAN1_ID4 CAN_ID_REG(CAN1_BASE_PTR,4) +#define CAN1_WORD04 CAN_WORD0_REG(CAN1_BASE_PTR,4) +#define CAN1_WORD14 CAN_WORD1_REG(CAN1_BASE_PTR,4) +#define CAN1_CS5 CAN_CS_REG(CAN1_BASE_PTR,5) +#define CAN1_ID5 CAN_ID_REG(CAN1_BASE_PTR,5) +#define CAN1_WORD05 CAN_WORD0_REG(CAN1_BASE_PTR,5) +#define CAN1_WORD15 CAN_WORD1_REG(CAN1_BASE_PTR,5) +#define CAN1_CS6 CAN_CS_REG(CAN1_BASE_PTR,6) +#define CAN1_ID6 CAN_ID_REG(CAN1_BASE_PTR,6) +#define CAN1_WORD06 CAN_WORD0_REG(CAN1_BASE_PTR,6) +#define CAN1_WORD16 CAN_WORD1_REG(CAN1_BASE_PTR,6) +#define CAN1_CS7 CAN_CS_REG(CAN1_BASE_PTR,7) +#define CAN1_ID7 CAN_ID_REG(CAN1_BASE_PTR,7) +#define CAN1_WORD07 CAN_WORD0_REG(CAN1_BASE_PTR,7) +#define CAN1_WORD17 CAN_WORD1_REG(CAN1_BASE_PTR,7) +#define CAN1_CS8 CAN_CS_REG(CAN1_BASE_PTR,8) +#define CAN1_ID8 CAN_ID_REG(CAN1_BASE_PTR,8) +#define CAN1_WORD08 CAN_WORD0_REG(CAN1_BASE_PTR,8) +#define CAN1_WORD18 CAN_WORD1_REG(CAN1_BASE_PTR,8) +#define CAN1_CS9 CAN_CS_REG(CAN1_BASE_PTR,9) +#define CAN1_ID9 CAN_ID_REG(CAN1_BASE_PTR,9) +#define CAN1_WORD09 CAN_WORD0_REG(CAN1_BASE_PTR,9) +#define CAN1_WORD19 CAN_WORD1_REG(CAN1_BASE_PTR,9) +#define CAN1_CS10 CAN_CS_REG(CAN1_BASE_PTR,10) +#define CAN1_ID10 CAN_ID_REG(CAN1_BASE_PTR,10) +#define CAN1_WORD010 CAN_WORD0_REG(CAN1_BASE_PTR,10) +#define CAN1_WORD110 CAN_WORD1_REG(CAN1_BASE_PTR,10) +#define CAN1_CS11 CAN_CS_REG(CAN1_BASE_PTR,11) +#define CAN1_ID11 CAN_ID_REG(CAN1_BASE_PTR,11) +#define CAN1_WORD011 CAN_WORD0_REG(CAN1_BASE_PTR,11) +#define CAN1_WORD111 CAN_WORD1_REG(CAN1_BASE_PTR,11) +#define CAN1_CS12 CAN_CS_REG(CAN1_BASE_PTR,12) +#define CAN1_ID12 CAN_ID_REG(CAN1_BASE_PTR,12) +#define CAN1_WORD012 CAN_WORD0_REG(CAN1_BASE_PTR,12) +#define CAN1_WORD112 CAN_WORD1_REG(CAN1_BASE_PTR,12) +#define CAN1_CS13 CAN_CS_REG(CAN1_BASE_PTR,13) +#define CAN1_ID13 CAN_ID_REG(CAN1_BASE_PTR,13) +#define CAN1_WORD013 CAN_WORD0_REG(CAN1_BASE_PTR,13) +#define CAN1_WORD113 CAN_WORD1_REG(CAN1_BASE_PTR,13) +#define CAN1_CS14 CAN_CS_REG(CAN1_BASE_PTR,14) +#define CAN1_ID14 CAN_ID_REG(CAN1_BASE_PTR,14) +#define CAN1_WORD014 CAN_WORD0_REG(CAN1_BASE_PTR,14) +#define CAN1_WORD114 CAN_WORD1_REG(CAN1_BASE_PTR,14) +#define CAN1_CS15 CAN_CS_REG(CAN1_BASE_PTR,15) +#define CAN1_ID15 CAN_ID_REG(CAN1_BASE_PTR,15) +#define CAN1_WORD015 CAN_WORD0_REG(CAN1_BASE_PTR,15) +#define CAN1_WORD115 CAN_WORD1_REG(CAN1_BASE_PTR,15) +#define CAN1_CS16 CAN_CS_REG(CAN1_BASE_PTR,16) +#define CAN1_ID16 CAN_ID_REG(CAN1_BASE_PTR,16) +#define CAN1_WORD016 CAN_WORD0_REG(CAN1_BASE_PTR,16) +#define CAN1_WORD116 CAN_WORD1_REG(CAN1_BASE_PTR,16) +#define CAN1_CS17 CAN_CS_REG(CAN1_BASE_PTR,17) +#define CAN1_ID17 CAN_ID_REG(CAN1_BASE_PTR,17) +#define CAN1_WORD017 CAN_WORD0_REG(CAN1_BASE_PTR,17) +#define CAN1_WORD117 CAN_WORD1_REG(CAN1_BASE_PTR,17) +#define CAN1_CS18 CAN_CS_REG(CAN1_BASE_PTR,18) +#define CAN1_ID18 CAN_ID_REG(CAN1_BASE_PTR,18) +#define CAN1_WORD018 CAN_WORD0_REG(CAN1_BASE_PTR,18) +#define CAN1_WORD118 CAN_WORD1_REG(CAN1_BASE_PTR,18) +#define CAN1_CS19 CAN_CS_REG(CAN1_BASE_PTR,19) +#define CAN1_ID19 CAN_ID_REG(CAN1_BASE_PTR,19) +#define CAN1_WORD019 CAN_WORD0_REG(CAN1_BASE_PTR,19) +#define CAN1_WORD119 CAN_WORD1_REG(CAN1_BASE_PTR,19) +#define CAN1_CS20 CAN_CS_REG(CAN1_BASE_PTR,20) +#define CAN1_ID20 CAN_ID_REG(CAN1_BASE_PTR,20) +#define CAN1_WORD020 CAN_WORD0_REG(CAN1_BASE_PTR,20) +#define CAN1_WORD120 CAN_WORD1_REG(CAN1_BASE_PTR,20) +#define CAN1_CS21 CAN_CS_REG(CAN1_BASE_PTR,21) +#define CAN1_ID21 CAN_ID_REG(CAN1_BASE_PTR,21) +#define CAN1_WORD021 CAN_WORD0_REG(CAN1_BASE_PTR,21) +#define CAN1_WORD121 CAN_WORD1_REG(CAN1_BASE_PTR,21) +#define CAN1_CS22 CAN_CS_REG(CAN1_BASE_PTR,22) +#define CAN1_ID22 CAN_ID_REG(CAN1_BASE_PTR,22) +#define CAN1_WORD022 CAN_WORD0_REG(CAN1_BASE_PTR,22) +#define CAN1_WORD122 CAN_WORD1_REG(CAN1_BASE_PTR,22) +#define CAN1_CS23 CAN_CS_REG(CAN1_BASE_PTR,23) +#define CAN1_ID23 CAN_ID_REG(CAN1_BASE_PTR,23) +#define CAN1_WORD023 CAN_WORD0_REG(CAN1_BASE_PTR,23) +#define CAN1_WORD123 CAN_WORD1_REG(CAN1_BASE_PTR,23) +#define CAN1_CS24 CAN_CS_REG(CAN1_BASE_PTR,24) +#define CAN1_ID24 CAN_ID_REG(CAN1_BASE_PTR,24) +#define CAN1_WORD024 CAN_WORD0_REG(CAN1_BASE_PTR,24) +#define CAN1_WORD124 CAN_WORD1_REG(CAN1_BASE_PTR,24) +#define CAN1_CS25 CAN_CS_REG(CAN1_BASE_PTR,25) +#define CAN1_ID25 CAN_ID_REG(CAN1_BASE_PTR,25) +#define CAN1_WORD025 CAN_WORD0_REG(CAN1_BASE_PTR,25) +#define CAN1_WORD125 CAN_WORD1_REG(CAN1_BASE_PTR,25) +#define CAN1_CS26 CAN_CS_REG(CAN1_BASE_PTR,26) +#define CAN1_ID26 CAN_ID_REG(CAN1_BASE_PTR,26) +#define CAN1_WORD026 CAN_WORD0_REG(CAN1_BASE_PTR,26) +#define CAN1_WORD126 CAN_WORD1_REG(CAN1_BASE_PTR,26) +#define CAN1_CS27 CAN_CS_REG(CAN1_BASE_PTR,27) +#define CAN1_ID27 CAN_ID_REG(CAN1_BASE_PTR,27) +#define CAN1_WORD027 CAN_WORD0_REG(CAN1_BASE_PTR,27) +#define CAN1_WORD127 CAN_WORD1_REG(CAN1_BASE_PTR,27) +#define CAN1_CS28 CAN_CS_REG(CAN1_BASE_PTR,28) +#define CAN1_ID28 CAN_ID_REG(CAN1_BASE_PTR,28) +#define CAN1_WORD028 CAN_WORD0_REG(CAN1_BASE_PTR,28) +#define CAN1_WORD128 CAN_WORD1_REG(CAN1_BASE_PTR,28) +#define CAN1_CS29 CAN_CS_REG(CAN1_BASE_PTR,29) +#define CAN1_ID29 CAN_ID_REG(CAN1_BASE_PTR,29) +#define CAN1_WORD029 CAN_WORD0_REG(CAN1_BASE_PTR,29) +#define CAN1_WORD129 CAN_WORD1_REG(CAN1_BASE_PTR,29) +#define CAN1_CS30 CAN_CS_REG(CAN1_BASE_PTR,30) +#define CAN1_ID30 CAN_ID_REG(CAN1_BASE_PTR,30) +#define CAN1_WORD030 CAN_WORD0_REG(CAN1_BASE_PTR,30) +#define CAN1_WORD130 CAN_WORD1_REG(CAN1_BASE_PTR,30) +#define CAN1_CS31 CAN_CS_REG(CAN1_BASE_PTR,31) +#define CAN1_ID31 CAN_ID_REG(CAN1_BASE_PTR,31) +#define CAN1_WORD031 CAN_WORD0_REG(CAN1_BASE_PTR,31) +#define CAN1_WORD131 CAN_WORD1_REG(CAN1_BASE_PTR,31) +#define CAN1_CS32 CAN_CS_REG(CAN1_BASE_PTR,32) +#define CAN1_ID32 CAN_ID_REG(CAN1_BASE_PTR,32) +#define CAN1_WORD032 CAN_WORD0_REG(CAN1_BASE_PTR,32) +#define CAN1_WORD132 CAN_WORD1_REG(CAN1_BASE_PTR,32) +#define CAN1_CS33 CAN_CS_REG(CAN1_BASE_PTR,33) +#define CAN1_ID33 CAN_ID_REG(CAN1_BASE_PTR,33) +#define CAN1_WORD033 CAN_WORD0_REG(CAN1_BASE_PTR,33) +#define CAN1_WORD133 CAN_WORD1_REG(CAN1_BASE_PTR,33) +#define CAN1_CS34 CAN_CS_REG(CAN1_BASE_PTR,34) +#define CAN1_ID34 CAN_ID_REG(CAN1_BASE_PTR,34) +#define CAN1_WORD034 CAN_WORD0_REG(CAN1_BASE_PTR,34) +#define CAN1_WORD134 CAN_WORD1_REG(CAN1_BASE_PTR,34) +#define CAN1_CS35 CAN_CS_REG(CAN1_BASE_PTR,35) +#define CAN1_ID35 CAN_ID_REG(CAN1_BASE_PTR,35) +#define CAN1_WORD035 CAN_WORD0_REG(CAN1_BASE_PTR,35) +#define CAN1_WORD135 CAN_WORD1_REG(CAN1_BASE_PTR,35) +#define CAN1_CS36 CAN_CS_REG(CAN1_BASE_PTR,36) +#define CAN1_ID36 CAN_ID_REG(CAN1_BASE_PTR,36) +#define CAN1_WORD036 CAN_WORD0_REG(CAN1_BASE_PTR,36) +#define CAN1_WORD136 CAN_WORD1_REG(CAN1_BASE_PTR,36) +#define CAN1_CS37 CAN_CS_REG(CAN1_BASE_PTR,37) +#define CAN1_ID37 CAN_ID_REG(CAN1_BASE_PTR,37) +#define CAN1_WORD037 CAN_WORD0_REG(CAN1_BASE_PTR,37) +#define CAN1_WORD137 CAN_WORD1_REG(CAN1_BASE_PTR,37) +#define CAN1_CS38 CAN_CS_REG(CAN1_BASE_PTR,38) +#define CAN1_ID38 CAN_ID_REG(CAN1_BASE_PTR,38) +#define CAN1_WORD038 CAN_WORD0_REG(CAN1_BASE_PTR,38) +#define CAN1_WORD138 CAN_WORD1_REG(CAN1_BASE_PTR,38) +#define CAN1_CS39 CAN_CS_REG(CAN1_BASE_PTR,39) +#define CAN1_ID39 CAN_ID_REG(CAN1_BASE_PTR,39) +#define CAN1_WORD039 CAN_WORD0_REG(CAN1_BASE_PTR,39) +#define CAN1_WORD139 CAN_WORD1_REG(CAN1_BASE_PTR,39) +#define CAN1_CS40 CAN_CS_REG(CAN1_BASE_PTR,40) +#define CAN1_ID40 CAN_ID_REG(CAN1_BASE_PTR,40) +#define CAN1_WORD040 CAN_WORD0_REG(CAN1_BASE_PTR,40) +#define CAN1_WORD140 CAN_WORD1_REG(CAN1_BASE_PTR,40) +#define CAN1_CS41 CAN_CS_REG(CAN1_BASE_PTR,41) +#define CAN1_ID41 CAN_ID_REG(CAN1_BASE_PTR,41) +#define CAN1_WORD041 CAN_WORD0_REG(CAN1_BASE_PTR,41) +#define CAN1_WORD141 CAN_WORD1_REG(CAN1_BASE_PTR,41) +#define CAN1_CS42 CAN_CS_REG(CAN1_BASE_PTR,42) +#define CAN1_ID42 CAN_ID_REG(CAN1_BASE_PTR,42) +#define CAN1_WORD042 CAN_WORD0_REG(CAN1_BASE_PTR,42) +#define CAN1_WORD142 CAN_WORD1_REG(CAN1_BASE_PTR,42) +#define CAN1_CS43 CAN_CS_REG(CAN1_BASE_PTR,43) +#define CAN1_ID43 CAN_ID_REG(CAN1_BASE_PTR,43) +#define CAN1_WORD043 CAN_WORD0_REG(CAN1_BASE_PTR,43) +#define CAN1_WORD143 CAN_WORD1_REG(CAN1_BASE_PTR,43) +#define CAN1_CS44 CAN_CS_REG(CAN1_BASE_PTR,44) +#define CAN1_ID44 CAN_ID_REG(CAN1_BASE_PTR,44) +#define CAN1_WORD044 CAN_WORD0_REG(CAN1_BASE_PTR,44) +#define CAN1_WORD144 CAN_WORD1_REG(CAN1_BASE_PTR,44) +#define CAN1_CS45 CAN_CS_REG(CAN1_BASE_PTR,45) +#define CAN1_ID45 CAN_ID_REG(CAN1_BASE_PTR,45) +#define CAN1_WORD045 CAN_WORD0_REG(CAN1_BASE_PTR,45) +#define CAN1_WORD145 CAN_WORD1_REG(CAN1_BASE_PTR,45) +#define CAN1_CS46 CAN_CS_REG(CAN1_BASE_PTR,46) +#define CAN1_ID46 CAN_ID_REG(CAN1_BASE_PTR,46) +#define CAN1_WORD046 CAN_WORD0_REG(CAN1_BASE_PTR,46) +#define CAN1_WORD146 CAN_WORD1_REG(CAN1_BASE_PTR,46) +#define CAN1_CS47 CAN_CS_REG(CAN1_BASE_PTR,47) +#define CAN1_ID47 CAN_ID_REG(CAN1_BASE_PTR,47) +#define CAN1_WORD047 CAN_WORD0_REG(CAN1_BASE_PTR,47) +#define CAN1_WORD147 CAN_WORD1_REG(CAN1_BASE_PTR,47) +#define CAN1_CS48 CAN_CS_REG(CAN1_BASE_PTR,48) +#define CAN1_ID48 CAN_ID_REG(CAN1_BASE_PTR,48) +#define CAN1_WORD048 CAN_WORD0_REG(CAN1_BASE_PTR,48) +#define CAN1_WORD148 CAN_WORD1_REG(CAN1_BASE_PTR,48) +#define CAN1_CS49 CAN_CS_REG(CAN1_BASE_PTR,49) +#define CAN1_ID49 CAN_ID_REG(CAN1_BASE_PTR,49) +#define CAN1_WORD049 CAN_WORD0_REG(CAN1_BASE_PTR,49) +#define CAN1_WORD149 CAN_WORD1_REG(CAN1_BASE_PTR,49) +#define CAN1_CS50 CAN_CS_REG(CAN1_BASE_PTR,50) +#define CAN1_ID50 CAN_ID_REG(CAN1_BASE_PTR,50) +#define CAN1_WORD050 CAN_WORD0_REG(CAN1_BASE_PTR,50) +#define CAN1_WORD150 CAN_WORD1_REG(CAN1_BASE_PTR,50) +#define CAN1_CS51 CAN_CS_REG(CAN1_BASE_PTR,51) +#define CAN1_ID51 CAN_ID_REG(CAN1_BASE_PTR,51) +#define CAN1_WORD051 CAN_WORD0_REG(CAN1_BASE_PTR,51) +#define CAN1_WORD151 CAN_WORD1_REG(CAN1_BASE_PTR,51) +#define CAN1_CS52 CAN_CS_REG(CAN1_BASE_PTR,52) +#define CAN1_ID52 CAN_ID_REG(CAN1_BASE_PTR,52) +#define CAN1_WORD052 CAN_WORD0_REG(CAN1_BASE_PTR,52) +#define CAN1_WORD152 CAN_WORD1_REG(CAN1_BASE_PTR,52) +#define CAN1_CS53 CAN_CS_REG(CAN1_BASE_PTR,53) +#define CAN1_ID53 CAN_ID_REG(CAN1_BASE_PTR,53) +#define CAN1_WORD053 CAN_WORD0_REG(CAN1_BASE_PTR,53) +#define CAN1_WORD153 CAN_WORD1_REG(CAN1_BASE_PTR,53) +#define CAN1_CS54 CAN_CS_REG(CAN1_BASE_PTR,54) +#define CAN1_ID54 CAN_ID_REG(CAN1_BASE_PTR,54) +#define CAN1_WORD054 CAN_WORD0_REG(CAN1_BASE_PTR,54) +#define CAN1_WORD154 CAN_WORD1_REG(CAN1_BASE_PTR,54) +#define CAN1_CS55 CAN_CS_REG(CAN1_BASE_PTR,55) +#define CAN1_ID55 CAN_ID_REG(CAN1_BASE_PTR,55) +#define CAN1_WORD055 CAN_WORD0_REG(CAN1_BASE_PTR,55) +#define CAN1_WORD155 CAN_WORD1_REG(CAN1_BASE_PTR,55) +#define CAN1_CS56 CAN_CS_REG(CAN1_BASE_PTR,56) +#define CAN1_ID56 CAN_ID_REG(CAN1_BASE_PTR,56) +#define CAN1_WORD056 CAN_WORD0_REG(CAN1_BASE_PTR,56) +#define CAN1_WORD156 CAN_WORD1_REG(CAN1_BASE_PTR,56) +#define CAN1_CS57 CAN_CS_REG(CAN1_BASE_PTR,57) +#define CAN1_ID57 CAN_ID_REG(CAN1_BASE_PTR,57) +#define CAN1_WORD057 CAN_WORD0_REG(CAN1_BASE_PTR,57) +#define CAN1_WORD157 CAN_WORD1_REG(CAN1_BASE_PTR,57) +#define CAN1_CS58 CAN_CS_REG(CAN1_BASE_PTR,58) +#define CAN1_ID58 CAN_ID_REG(CAN1_BASE_PTR,58) +#define CAN1_WORD058 CAN_WORD0_REG(CAN1_BASE_PTR,58) +#define CAN1_WORD158 CAN_WORD1_REG(CAN1_BASE_PTR,58) +#define CAN1_CS59 CAN_CS_REG(CAN1_BASE_PTR,59) +#define CAN1_ID59 CAN_ID_REG(CAN1_BASE_PTR,59) +#define CAN1_WORD059 CAN_WORD0_REG(CAN1_BASE_PTR,59) +#define CAN1_WORD159 CAN_WORD1_REG(CAN1_BASE_PTR,59) +#define CAN1_CS60 CAN_CS_REG(CAN1_BASE_PTR,60) +#define CAN1_ID60 CAN_ID_REG(CAN1_BASE_PTR,60) +#define CAN1_WORD060 CAN_WORD0_REG(CAN1_BASE_PTR,60) +#define CAN1_WORD160 CAN_WORD1_REG(CAN1_BASE_PTR,60) +#define CAN1_CS61 CAN_CS_REG(CAN1_BASE_PTR,61) +#define CAN1_ID61 CAN_ID_REG(CAN1_BASE_PTR,61) +#define CAN1_WORD061 CAN_WORD0_REG(CAN1_BASE_PTR,61) +#define CAN1_WORD161 CAN_WORD1_REG(CAN1_BASE_PTR,61) +#define CAN1_CS62 CAN_CS_REG(CAN1_BASE_PTR,62) +#define CAN1_ID62 CAN_ID_REG(CAN1_BASE_PTR,62) +#define CAN1_WORD062 CAN_WORD0_REG(CAN1_BASE_PTR,62) +#define CAN1_WORD162 CAN_WORD1_REG(CAN1_BASE_PTR,62) +#define CAN1_CS63 CAN_CS_REG(CAN1_BASE_PTR,63) +#define CAN1_ID63 CAN_ID_REG(CAN1_BASE_PTR,63) +#define CAN1_WORD063 CAN_WORD0_REG(CAN1_BASE_PTR,63) +#define CAN1_WORD163 CAN_WORD1_REG(CAN1_BASE_PTR,63) +#define CAN1_RXIMR0 CAN_RXIMR_REG(CAN1_BASE_PTR,0) +#define CAN1_RXIMR1 CAN_RXIMR_REG(CAN1_BASE_PTR,1) +#define CAN1_RXIMR2 CAN_RXIMR_REG(CAN1_BASE_PTR,2) +#define CAN1_RXIMR3 CAN_RXIMR_REG(CAN1_BASE_PTR,3) +#define CAN1_RXIMR4 CAN_RXIMR_REG(CAN1_BASE_PTR,4) +#define CAN1_RXIMR5 CAN_RXIMR_REG(CAN1_BASE_PTR,5) +#define CAN1_RXIMR6 CAN_RXIMR_REG(CAN1_BASE_PTR,6) +#define CAN1_RXIMR7 CAN_RXIMR_REG(CAN1_BASE_PTR,7) +#define CAN1_RXIMR8 CAN_RXIMR_REG(CAN1_BASE_PTR,8) +#define CAN1_RXIMR9 CAN_RXIMR_REG(CAN1_BASE_PTR,9) +#define CAN1_RXIMR10 CAN_RXIMR_REG(CAN1_BASE_PTR,10) +#define CAN1_RXIMR11 CAN_RXIMR_REG(CAN1_BASE_PTR,11) +#define CAN1_RXIMR12 CAN_RXIMR_REG(CAN1_BASE_PTR,12) +#define CAN1_RXIMR13 CAN_RXIMR_REG(CAN1_BASE_PTR,13) +#define CAN1_RXIMR14 CAN_RXIMR_REG(CAN1_BASE_PTR,14) +#define CAN1_RXIMR15 CAN_RXIMR_REG(CAN1_BASE_PTR,15) +#define CAN1_RXIMR16 CAN_RXIMR_REG(CAN1_BASE_PTR,16) +#define CAN1_RXIMR17 CAN_RXIMR_REG(CAN1_BASE_PTR,17) +#define CAN1_RXIMR18 CAN_RXIMR_REG(CAN1_BASE_PTR,18) +#define CAN1_RXIMR19 CAN_RXIMR_REG(CAN1_BASE_PTR,19) +#define CAN1_RXIMR20 CAN_RXIMR_REG(CAN1_BASE_PTR,20) +#define CAN1_RXIMR21 CAN_RXIMR_REG(CAN1_BASE_PTR,21) +#define CAN1_RXIMR22 CAN_RXIMR_REG(CAN1_BASE_PTR,22) +#define CAN1_RXIMR23 CAN_RXIMR_REG(CAN1_BASE_PTR,23) +#define CAN1_RXIMR24 CAN_RXIMR_REG(CAN1_BASE_PTR,24) +#define CAN1_RXIMR25 CAN_RXIMR_REG(CAN1_BASE_PTR,25) +#define CAN1_RXIMR26 CAN_RXIMR_REG(CAN1_BASE_PTR,26) +#define CAN1_RXIMR27 CAN_RXIMR_REG(CAN1_BASE_PTR,27) +#define CAN1_RXIMR28 CAN_RXIMR_REG(CAN1_BASE_PTR,28) +#define CAN1_RXIMR29 CAN_RXIMR_REG(CAN1_BASE_PTR,29) +#define CAN1_RXIMR30 CAN_RXIMR_REG(CAN1_BASE_PTR,30) +#define CAN1_RXIMR31 CAN_RXIMR_REG(CAN1_BASE_PTR,31) +#define CAN1_RXIMR32 CAN_RXIMR_REG(CAN1_BASE_PTR,32) +#define CAN1_RXIMR33 CAN_RXIMR_REG(CAN1_BASE_PTR,33) +#define CAN1_RXIMR34 CAN_RXIMR_REG(CAN1_BASE_PTR,34) +#define CAN1_RXIMR35 CAN_RXIMR_REG(CAN1_BASE_PTR,35) +#define CAN1_RXIMR36 CAN_RXIMR_REG(CAN1_BASE_PTR,36) +#define CAN1_RXIMR37 CAN_RXIMR_REG(CAN1_BASE_PTR,37) +#define CAN1_RXIMR38 CAN_RXIMR_REG(CAN1_BASE_PTR,38) +#define CAN1_RXIMR39 CAN_RXIMR_REG(CAN1_BASE_PTR,39) +#define CAN1_RXIMR40 CAN_RXIMR_REG(CAN1_BASE_PTR,40) +#define CAN1_RXIMR41 CAN_RXIMR_REG(CAN1_BASE_PTR,41) +#define CAN1_RXIMR42 CAN_RXIMR_REG(CAN1_BASE_PTR,42) +#define CAN1_RXIMR43 CAN_RXIMR_REG(CAN1_BASE_PTR,43) +#define CAN1_RXIMR44 CAN_RXIMR_REG(CAN1_BASE_PTR,44) +#define CAN1_RXIMR45 CAN_RXIMR_REG(CAN1_BASE_PTR,45) +#define CAN1_RXIMR46 CAN_RXIMR_REG(CAN1_BASE_PTR,46) +#define CAN1_RXIMR47 CAN_RXIMR_REG(CAN1_BASE_PTR,47) +#define CAN1_RXIMR48 CAN_RXIMR_REG(CAN1_BASE_PTR,48) +#define CAN1_RXIMR49 CAN_RXIMR_REG(CAN1_BASE_PTR,49) +#define CAN1_RXIMR50 CAN_RXIMR_REG(CAN1_BASE_PTR,50) +#define CAN1_RXIMR51 CAN_RXIMR_REG(CAN1_BASE_PTR,51) +#define CAN1_RXIMR52 CAN_RXIMR_REG(CAN1_BASE_PTR,52) +#define CAN1_RXIMR53 CAN_RXIMR_REG(CAN1_BASE_PTR,53) +#define CAN1_RXIMR54 CAN_RXIMR_REG(CAN1_BASE_PTR,54) +#define CAN1_RXIMR55 CAN_RXIMR_REG(CAN1_BASE_PTR,55) +#define CAN1_RXIMR56 CAN_RXIMR_REG(CAN1_BASE_PTR,56) +#define CAN1_RXIMR57 CAN_RXIMR_REG(CAN1_BASE_PTR,57) +#define CAN1_RXIMR58 CAN_RXIMR_REG(CAN1_BASE_PTR,58) +#define CAN1_RXIMR59 CAN_RXIMR_REG(CAN1_BASE_PTR,59) +#define CAN1_RXIMR60 CAN_RXIMR_REG(CAN1_BASE_PTR,60) +#define CAN1_RXIMR61 CAN_RXIMR_REG(CAN1_BASE_PTR,61) +#define CAN1_RXIMR62 CAN_RXIMR_REG(CAN1_BASE_PTR,62) +#define CAN1_RXIMR63 CAN_RXIMR_REG(CAN1_BASE_PTR,63) #define CAN1_GFWR CAN_GFWR_REG(CAN1_BASE_PTR) /* CAN2 */ #define CAN2_MCR CAN_MCR_REG(CAN2_BASE_PTR) @@ -3886,14 +4178,338 @@ typedef struct { #define CAN2_CRCR CAN_CRCR_REG(CAN2_BASE_PTR) #define CAN2_RXFGMASK CAN_RXFGMASK_REG(CAN2_BASE_PTR) #define CAN2_RXFIR CAN_RXFIR_REG(CAN2_BASE_PTR) -#define CAN2_RXFIR CAN_RXFIR_REG(CAN2_BASE_PTR) -#define CAN2_CS(index) CAN_CS_REG(CAN2,index) -#define CAN2_ID(index) CAN_ID_REG(CAN2,index) -#define CAN2_WORD0(index) CAN_WORD0_REG(CAN2,index) -#define CAN2_WORD1(index) CAN_WORD1_REG(CAN2,index) -#define CAN2_RXIMR(index) CAN_RXIMR_REG(CAN2,index) +#define CAN2_CS0 CAN_CS_REG(CAN2_BASE_PTR,0) +#define CAN2_ID0 CAN_ID_REG(CAN2_BASE_PTR,0) +#define CAN2_WORD00 CAN_WORD0_REG(CAN2_BASE_PTR,0) +#define CAN2_WORD10 CAN_WORD1_REG(CAN2_BASE_PTR,0) +#define CAN2_CS1 CAN_CS_REG(CAN2_BASE_PTR,1) +#define CAN2_ID1 CAN_ID_REG(CAN2_BASE_PTR,1) +#define CAN2_WORD01 CAN_WORD0_REG(CAN2_BASE_PTR,1) +#define CAN2_WORD11 CAN_WORD1_REG(CAN2_BASE_PTR,1) +#define CAN2_CS2 CAN_CS_REG(CAN2_BASE_PTR,2) +#define CAN2_ID2 CAN_ID_REG(CAN2_BASE_PTR,2) +#define CAN2_WORD02 CAN_WORD0_REG(CAN2_BASE_PTR,2) +#define CAN2_WORD12 CAN_WORD1_REG(CAN2_BASE_PTR,2) +#define CAN2_CS3 CAN_CS_REG(CAN2_BASE_PTR,3) +#define CAN2_ID3 CAN_ID_REG(CAN2_BASE_PTR,3) +#define CAN2_WORD03 CAN_WORD0_REG(CAN2_BASE_PTR,3) +#define CAN2_WORD13 CAN_WORD1_REG(CAN2_BASE_PTR,3) +#define CAN2_CS4 CAN_CS_REG(CAN2_BASE_PTR,4) +#define CAN2_ID4 CAN_ID_REG(CAN2_BASE_PTR,4) +#define CAN2_WORD04 CAN_WORD0_REG(CAN2_BASE_PTR,4) +#define CAN2_WORD14 CAN_WORD1_REG(CAN2_BASE_PTR,4) +#define CAN2_CS5 CAN_CS_REG(CAN2_BASE_PTR,5) +#define CAN2_ID5 CAN_ID_REG(CAN2_BASE_PTR,5) +#define CAN2_WORD05 CAN_WORD0_REG(CAN2_BASE_PTR,5) +#define CAN2_WORD15 CAN_WORD1_REG(CAN2_BASE_PTR,5) +#define CAN2_CS6 CAN_CS_REG(CAN2_BASE_PTR,6) +#define CAN2_ID6 CAN_ID_REG(CAN2_BASE_PTR,6) +#define CAN2_WORD06 CAN_WORD0_REG(CAN2_BASE_PTR,6) +#define CAN2_WORD16 CAN_WORD1_REG(CAN2_BASE_PTR,6) +#define CAN2_CS7 CAN_CS_REG(CAN2_BASE_PTR,7) +#define CAN2_ID7 CAN_ID_REG(CAN2_BASE_PTR,7) +#define CAN2_WORD07 CAN_WORD0_REG(CAN2_BASE_PTR,7) +#define CAN2_WORD17 CAN_WORD1_REG(CAN2_BASE_PTR,7) +#define CAN2_CS8 CAN_CS_REG(CAN2_BASE_PTR,8) +#define CAN2_ID8 CAN_ID_REG(CAN2_BASE_PTR,8) +#define CAN2_WORD08 CAN_WORD0_REG(CAN2_BASE_PTR,8) +#define CAN2_WORD18 CAN_WORD1_REG(CAN2_BASE_PTR,8) +#define CAN2_CS9 CAN_CS_REG(CAN2_BASE_PTR,9) +#define CAN2_ID9 CAN_ID_REG(CAN2_BASE_PTR,9) +#define CAN2_WORD09 CAN_WORD0_REG(CAN2_BASE_PTR,9) +#define CAN2_WORD19 CAN_WORD1_REG(CAN2_BASE_PTR,9) +#define CAN2_CS10 CAN_CS_REG(CAN2_BASE_PTR,10) +#define CAN2_ID10 CAN_ID_REG(CAN2_BASE_PTR,10) +#define CAN2_WORD010 CAN_WORD0_REG(CAN2_BASE_PTR,10) +#define CAN2_WORD110 CAN_WORD1_REG(CAN2_BASE_PTR,10) +#define CAN2_CS11 CAN_CS_REG(CAN2_BASE_PTR,11) +#define CAN2_ID11 CAN_ID_REG(CAN2_BASE_PTR,11) +#define CAN2_WORD011 CAN_WORD0_REG(CAN2_BASE_PTR,11) +#define CAN2_WORD111 CAN_WORD1_REG(CAN2_BASE_PTR,11) +#define CAN2_CS12 CAN_CS_REG(CAN2_BASE_PTR,12) +#define CAN2_ID12 CAN_ID_REG(CAN2_BASE_PTR,12) +#define CAN2_WORD012 CAN_WORD0_REG(CAN2_BASE_PTR,12) +#define CAN2_WORD112 CAN_WORD1_REG(CAN2_BASE_PTR,12) +#define CAN2_CS13 CAN_CS_REG(CAN2_BASE_PTR,13) +#define CAN2_ID13 CAN_ID_REG(CAN2_BASE_PTR,13) +#define CAN2_WORD013 CAN_WORD0_REG(CAN2_BASE_PTR,13) +#define CAN2_WORD113 CAN_WORD1_REG(CAN2_BASE_PTR,13) +#define CAN2_CS14 CAN_CS_REG(CAN2_BASE_PTR,14) +#define CAN2_ID14 CAN_ID_REG(CAN2_BASE_PTR,14) +#define CAN2_WORD014 CAN_WORD0_REG(CAN2_BASE_PTR,14) +#define CAN2_WORD114 CAN_WORD1_REG(CAN2_BASE_PTR,14) +#define CAN2_CS15 CAN_CS_REG(CAN2_BASE_PTR,15) +#define CAN2_ID15 CAN_ID_REG(CAN2_BASE_PTR,15) +#define CAN2_WORD015 CAN_WORD0_REG(CAN2_BASE_PTR,15) +#define CAN2_WORD115 CAN_WORD1_REG(CAN2_BASE_PTR,15) +#define CAN2_CS16 CAN_CS_REG(CAN2_BASE_PTR,16) +#define CAN2_ID16 CAN_ID_REG(CAN2_BASE_PTR,16) +#define CAN2_WORD016 CAN_WORD0_REG(CAN2_BASE_PTR,16) +#define CAN2_WORD116 CAN_WORD1_REG(CAN2_BASE_PTR,16) +#define CAN2_CS17 CAN_CS_REG(CAN2_BASE_PTR,17) +#define CAN2_ID17 CAN_ID_REG(CAN2_BASE_PTR,17) +#define CAN2_WORD017 CAN_WORD0_REG(CAN2_BASE_PTR,17) +#define CAN2_WORD117 CAN_WORD1_REG(CAN2_BASE_PTR,17) +#define CAN2_CS18 CAN_CS_REG(CAN2_BASE_PTR,18) +#define CAN2_ID18 CAN_ID_REG(CAN2_BASE_PTR,18) +#define CAN2_WORD018 CAN_WORD0_REG(CAN2_BASE_PTR,18) +#define CAN2_WORD118 CAN_WORD1_REG(CAN2_BASE_PTR,18) +#define CAN2_CS19 CAN_CS_REG(CAN2_BASE_PTR,19) +#define CAN2_ID19 CAN_ID_REG(CAN2_BASE_PTR,19) +#define CAN2_WORD019 CAN_WORD0_REG(CAN2_BASE_PTR,19) +#define CAN2_WORD119 CAN_WORD1_REG(CAN2_BASE_PTR,19) +#define CAN2_CS20 CAN_CS_REG(CAN2_BASE_PTR,20) +#define CAN2_ID20 CAN_ID_REG(CAN2_BASE_PTR,20) +#define CAN2_WORD020 CAN_WORD0_REG(CAN2_BASE_PTR,20) +#define CAN2_WORD120 CAN_WORD1_REG(CAN2_BASE_PTR,20) +#define CAN2_CS21 CAN_CS_REG(CAN2_BASE_PTR,21) +#define CAN2_ID21 CAN_ID_REG(CAN2_BASE_PTR,21) +#define CAN2_WORD021 CAN_WORD0_REG(CAN2_BASE_PTR,21) +#define CAN2_WORD121 CAN_WORD1_REG(CAN2_BASE_PTR,21) +#define CAN2_CS22 CAN_CS_REG(CAN2_BASE_PTR,22) +#define CAN2_ID22 CAN_ID_REG(CAN2_BASE_PTR,22) +#define CAN2_WORD022 CAN_WORD0_REG(CAN2_BASE_PTR,22) +#define CAN2_WORD122 CAN_WORD1_REG(CAN2_BASE_PTR,22) +#define CAN2_CS23 CAN_CS_REG(CAN2_BASE_PTR,23) +#define CAN2_ID23 CAN_ID_REG(CAN2_BASE_PTR,23) +#define CAN2_WORD023 CAN_WORD0_REG(CAN2_BASE_PTR,23) +#define CAN2_WORD123 CAN_WORD1_REG(CAN2_BASE_PTR,23) +#define CAN2_CS24 CAN_CS_REG(CAN2_BASE_PTR,24) +#define CAN2_ID24 CAN_ID_REG(CAN2_BASE_PTR,24) +#define CAN2_WORD024 CAN_WORD0_REG(CAN2_BASE_PTR,24) +#define CAN2_WORD124 CAN_WORD1_REG(CAN2_BASE_PTR,24) +#define CAN2_CS25 CAN_CS_REG(CAN2_BASE_PTR,25) +#define CAN2_ID25 CAN_ID_REG(CAN2_BASE_PTR,25) +#define CAN2_WORD025 CAN_WORD0_REG(CAN2_BASE_PTR,25) +#define CAN2_WORD125 CAN_WORD1_REG(CAN2_BASE_PTR,25) +#define CAN2_CS26 CAN_CS_REG(CAN2_BASE_PTR,26) +#define CAN2_ID26 CAN_ID_REG(CAN2_BASE_PTR,26) +#define CAN2_WORD026 CAN_WORD0_REG(CAN2_BASE_PTR,26) +#define CAN2_WORD126 CAN_WORD1_REG(CAN2_BASE_PTR,26) +#define CAN2_CS27 CAN_CS_REG(CAN2_BASE_PTR,27) +#define CAN2_ID27 CAN_ID_REG(CAN2_BASE_PTR,27) +#define CAN2_WORD027 CAN_WORD0_REG(CAN2_BASE_PTR,27) +#define CAN2_WORD127 CAN_WORD1_REG(CAN2_BASE_PTR,27) +#define CAN2_CS28 CAN_CS_REG(CAN2_BASE_PTR,28) +#define CAN2_ID28 CAN_ID_REG(CAN2_BASE_PTR,28) +#define CAN2_WORD028 CAN_WORD0_REG(CAN2_BASE_PTR,28) +#define CAN2_WORD128 CAN_WORD1_REG(CAN2_BASE_PTR,28) +#define CAN2_CS29 CAN_CS_REG(CAN2_BASE_PTR,29) +#define CAN2_ID29 CAN_ID_REG(CAN2_BASE_PTR,29) +#define CAN2_WORD029 CAN_WORD0_REG(CAN2_BASE_PTR,29) +#define CAN2_WORD129 CAN_WORD1_REG(CAN2_BASE_PTR,29) +#define CAN2_CS30 CAN_CS_REG(CAN2_BASE_PTR,30) +#define CAN2_ID30 CAN_ID_REG(CAN2_BASE_PTR,30) +#define CAN2_WORD030 CAN_WORD0_REG(CAN2_BASE_PTR,30) +#define CAN2_WORD130 CAN_WORD1_REG(CAN2_BASE_PTR,30) +#define CAN2_CS31 CAN_CS_REG(CAN2_BASE_PTR,31) +#define CAN2_ID31 CAN_ID_REG(CAN2_BASE_PTR,31) +#define CAN2_WORD031 CAN_WORD0_REG(CAN2_BASE_PTR,31) +#define CAN2_WORD131 CAN_WORD1_REG(CAN2_BASE_PTR,31) +#define CAN2_CS32 CAN_CS_REG(CAN2_BASE_PTR,32) +#define CAN2_ID32 CAN_ID_REG(CAN2_BASE_PTR,32) +#define CAN2_WORD032 CAN_WORD0_REG(CAN2_BASE_PTR,32) +#define CAN2_WORD132 CAN_WORD1_REG(CAN2_BASE_PTR,32) +#define CAN2_CS33 CAN_CS_REG(CAN2_BASE_PTR,33) +#define CAN2_ID33 CAN_ID_REG(CAN2_BASE_PTR,33) +#define CAN2_WORD033 CAN_WORD0_REG(CAN2_BASE_PTR,33) +#define CAN2_WORD133 CAN_WORD1_REG(CAN2_BASE_PTR,33) +#define CAN2_CS34 CAN_CS_REG(CAN2_BASE_PTR,34) +#define CAN2_ID34 CAN_ID_REG(CAN2_BASE_PTR,34) +#define CAN2_WORD034 CAN_WORD0_REG(CAN2_BASE_PTR,34) +#define CAN2_WORD134 CAN_WORD1_REG(CAN2_BASE_PTR,34) +#define CAN2_CS35 CAN_CS_REG(CAN2_BASE_PTR,35) +#define CAN2_ID35 CAN_ID_REG(CAN2_BASE_PTR,35) +#define CAN2_WORD035 CAN_WORD0_REG(CAN2_BASE_PTR,35) +#define CAN2_WORD135 CAN_WORD1_REG(CAN2_BASE_PTR,35) +#define CAN2_CS36 CAN_CS_REG(CAN2_BASE_PTR,36) +#define CAN2_ID36 CAN_ID_REG(CAN2_BASE_PTR,36) +#define CAN2_WORD036 CAN_WORD0_REG(CAN2_BASE_PTR,36) +#define CAN2_WORD136 CAN_WORD1_REG(CAN2_BASE_PTR,36) +#define CAN2_CS37 CAN_CS_REG(CAN2_BASE_PTR,37) +#define CAN2_ID37 CAN_ID_REG(CAN2_BASE_PTR,37) +#define CAN2_WORD037 CAN_WORD0_REG(CAN2_BASE_PTR,37) +#define CAN2_WORD137 CAN_WORD1_REG(CAN2_BASE_PTR,37) +#define CAN2_CS38 CAN_CS_REG(CAN2_BASE_PTR,38) +#define CAN2_ID38 CAN_ID_REG(CAN2_BASE_PTR,38) +#define CAN2_WORD038 CAN_WORD0_REG(CAN2_BASE_PTR,38) +#define CAN2_WORD138 CAN_WORD1_REG(CAN2_BASE_PTR,38) +#define CAN2_CS39 CAN_CS_REG(CAN2_BASE_PTR,39) +#define CAN2_ID39 CAN_ID_REG(CAN2_BASE_PTR,39) +#define CAN2_WORD039 CAN_WORD0_REG(CAN2_BASE_PTR,39) +#define CAN2_WORD139 CAN_WORD1_REG(CAN2_BASE_PTR,39) +#define CAN2_CS40 CAN_CS_REG(CAN2_BASE_PTR,40) +#define CAN2_ID40 CAN_ID_REG(CAN2_BASE_PTR,40) +#define CAN2_WORD040 CAN_WORD0_REG(CAN2_BASE_PTR,40) +#define CAN2_WORD140 CAN_WORD1_REG(CAN2_BASE_PTR,40) +#define CAN2_CS41 CAN_CS_REG(CAN2_BASE_PTR,41) +#define CAN2_ID41 CAN_ID_REG(CAN2_BASE_PTR,41) +#define CAN2_WORD041 CAN_WORD0_REG(CAN2_BASE_PTR,41) +#define CAN2_WORD141 CAN_WORD1_REG(CAN2_BASE_PTR,41) +#define CAN2_CS42 CAN_CS_REG(CAN2_BASE_PTR,42) +#define CAN2_ID42 CAN_ID_REG(CAN2_BASE_PTR,42) +#define CAN2_WORD042 CAN_WORD0_REG(CAN2_BASE_PTR,42) +#define CAN2_WORD142 CAN_WORD1_REG(CAN2_BASE_PTR,42) +#define CAN2_CS43 CAN_CS_REG(CAN2_BASE_PTR,43) +#define CAN2_ID43 CAN_ID_REG(CAN2_BASE_PTR,43) +#define CAN2_WORD043 CAN_WORD0_REG(CAN2_BASE_PTR,43) +#define CAN2_WORD143 CAN_WORD1_REG(CAN2_BASE_PTR,43) +#define CAN2_CS44 CAN_CS_REG(CAN2_BASE_PTR,44) +#define CAN2_ID44 CAN_ID_REG(CAN2_BASE_PTR,44) +#define CAN2_WORD044 CAN_WORD0_REG(CAN2_BASE_PTR,44) +#define CAN2_WORD144 CAN_WORD1_REG(CAN2_BASE_PTR,44) +#define CAN2_CS45 CAN_CS_REG(CAN2_BASE_PTR,45) +#define CAN2_ID45 CAN_ID_REG(CAN2_BASE_PTR,45) +#define CAN2_WORD045 CAN_WORD0_REG(CAN2_BASE_PTR,45) +#define CAN2_WORD145 CAN_WORD1_REG(CAN2_BASE_PTR,45) +#define CAN2_CS46 CAN_CS_REG(CAN2_BASE_PTR,46) +#define CAN2_ID46 CAN_ID_REG(CAN2_BASE_PTR,46) +#define CAN2_WORD046 CAN_WORD0_REG(CAN2_BASE_PTR,46) +#define CAN2_WORD146 CAN_WORD1_REG(CAN2_BASE_PTR,46) +#define CAN2_CS47 CAN_CS_REG(CAN2_BASE_PTR,47) +#define CAN2_ID47 CAN_ID_REG(CAN2_BASE_PTR,47) +#define CAN2_WORD047 CAN_WORD0_REG(CAN2_BASE_PTR,47) +#define CAN2_WORD147 CAN_WORD1_REG(CAN2_BASE_PTR,47) +#define CAN2_CS48 CAN_CS_REG(CAN2_BASE_PTR,48) +#define CAN2_ID48 CAN_ID_REG(CAN2_BASE_PTR,48) +#define CAN2_WORD048 CAN_WORD0_REG(CAN2_BASE_PTR,48) +#define CAN2_WORD148 CAN_WORD1_REG(CAN2_BASE_PTR,48) +#define CAN2_CS49 CAN_CS_REG(CAN2_BASE_PTR,49) +#define CAN2_ID49 CAN_ID_REG(CAN2_BASE_PTR,49) +#define CAN2_WORD049 CAN_WORD0_REG(CAN2_BASE_PTR,49) +#define CAN2_WORD149 CAN_WORD1_REG(CAN2_BASE_PTR,49) +#define CAN2_CS50 CAN_CS_REG(CAN2_BASE_PTR,50) +#define CAN2_ID50 CAN_ID_REG(CAN2_BASE_PTR,50) +#define CAN2_WORD050 CAN_WORD0_REG(CAN2_BASE_PTR,50) +#define CAN2_WORD150 CAN_WORD1_REG(CAN2_BASE_PTR,50) +#define CAN2_CS51 CAN_CS_REG(CAN2_BASE_PTR,51) +#define CAN2_ID51 CAN_ID_REG(CAN2_BASE_PTR,51) +#define CAN2_WORD051 CAN_WORD0_REG(CAN2_BASE_PTR,51) +#define CAN2_WORD151 CAN_WORD1_REG(CAN2_BASE_PTR,51) +#define CAN2_CS52 CAN_CS_REG(CAN2_BASE_PTR,52) +#define CAN2_ID52 CAN_ID_REG(CAN2_BASE_PTR,52) +#define CAN2_WORD052 CAN_WORD0_REG(CAN2_BASE_PTR,52) +#define CAN2_WORD152 CAN_WORD1_REG(CAN2_BASE_PTR,52) +#define CAN2_CS53 CAN_CS_REG(CAN2_BASE_PTR,53) +#define CAN2_ID53 CAN_ID_REG(CAN2_BASE_PTR,53) +#define CAN2_WORD053 CAN_WORD0_REG(CAN2_BASE_PTR,53) +#define CAN2_WORD153 CAN_WORD1_REG(CAN2_BASE_PTR,53) +#define CAN2_CS54 CAN_CS_REG(CAN2_BASE_PTR,54) +#define CAN2_ID54 CAN_ID_REG(CAN2_BASE_PTR,54) +#define CAN2_WORD054 CAN_WORD0_REG(CAN2_BASE_PTR,54) +#define CAN2_WORD154 CAN_WORD1_REG(CAN2_BASE_PTR,54) +#define CAN2_CS55 CAN_CS_REG(CAN2_BASE_PTR,55) +#define CAN2_ID55 CAN_ID_REG(CAN2_BASE_PTR,55) +#define CAN2_WORD055 CAN_WORD0_REG(CAN2_BASE_PTR,55) +#define CAN2_WORD155 CAN_WORD1_REG(CAN2_BASE_PTR,55) +#define CAN2_CS56 CAN_CS_REG(CAN2_BASE_PTR,56) +#define CAN2_ID56 CAN_ID_REG(CAN2_BASE_PTR,56) +#define CAN2_WORD056 CAN_WORD0_REG(CAN2_BASE_PTR,56) +#define CAN2_WORD156 CAN_WORD1_REG(CAN2_BASE_PTR,56) +#define CAN2_CS57 CAN_CS_REG(CAN2_BASE_PTR,57) +#define CAN2_ID57 CAN_ID_REG(CAN2_BASE_PTR,57) +#define CAN2_WORD057 CAN_WORD0_REG(CAN2_BASE_PTR,57) +#define CAN2_WORD157 CAN_WORD1_REG(CAN2_BASE_PTR,57) +#define CAN2_CS58 CAN_CS_REG(CAN2_BASE_PTR,58) +#define CAN2_ID58 CAN_ID_REG(CAN2_BASE_PTR,58) +#define CAN2_WORD058 CAN_WORD0_REG(CAN2_BASE_PTR,58) +#define CAN2_WORD158 CAN_WORD1_REG(CAN2_BASE_PTR,58) +#define CAN2_CS59 CAN_CS_REG(CAN2_BASE_PTR,59) +#define CAN2_ID59 CAN_ID_REG(CAN2_BASE_PTR,59) +#define CAN2_WORD059 CAN_WORD0_REG(CAN2_BASE_PTR,59) +#define CAN2_WORD159 CAN_WORD1_REG(CAN2_BASE_PTR,59) +#define CAN2_CS60 CAN_CS_REG(CAN2_BASE_PTR,60) +#define CAN2_ID60 CAN_ID_REG(CAN2_BASE_PTR,60) +#define CAN2_WORD060 CAN_WORD0_REG(CAN2_BASE_PTR,60) +#define CAN2_WORD160 CAN_WORD1_REG(CAN2_BASE_PTR,60) +#define CAN2_CS61 CAN_CS_REG(CAN2_BASE_PTR,61) +#define CAN2_ID61 CAN_ID_REG(CAN2_BASE_PTR,61) +#define CAN2_WORD061 CAN_WORD0_REG(CAN2_BASE_PTR,61) +#define CAN2_WORD161 CAN_WORD1_REG(CAN2_BASE_PTR,61) +#define CAN2_CS62 CAN_CS_REG(CAN2_BASE_PTR,62) +#define CAN2_ID62 CAN_ID_REG(CAN2_BASE_PTR,62) +#define CAN2_WORD062 CAN_WORD0_REG(CAN2_BASE_PTR,62) +#define CAN2_WORD162 CAN_WORD1_REG(CAN2_BASE_PTR,62) +#define CAN2_CS63 CAN_CS_REG(CAN2_BASE_PTR,63) +#define CAN2_ID63 CAN_ID_REG(CAN2_BASE_PTR,63) +#define CAN2_WORD063 CAN_WORD0_REG(CAN2_BASE_PTR,63) +#define CAN2_WORD163 CAN_WORD1_REG(CAN2_BASE_PTR,63) +#define CAN2_RXIMR0 CAN_RXIMR_REG(CAN2_BASE_PTR,0) +#define CAN2_RXIMR1 CAN_RXIMR_REG(CAN2_BASE_PTR,1) +#define CAN2_RXIMR2 CAN_RXIMR_REG(CAN2_BASE_PTR,2) +#define CAN2_RXIMR3 CAN_RXIMR_REG(CAN2_BASE_PTR,3) +#define CAN2_RXIMR4 CAN_RXIMR_REG(CAN2_BASE_PTR,4) +#define CAN2_RXIMR5 CAN_RXIMR_REG(CAN2_BASE_PTR,5) +#define CAN2_RXIMR6 CAN_RXIMR_REG(CAN2_BASE_PTR,6) +#define CAN2_RXIMR7 CAN_RXIMR_REG(CAN2_BASE_PTR,7) +#define CAN2_RXIMR8 CAN_RXIMR_REG(CAN2_BASE_PTR,8) +#define CAN2_RXIMR9 CAN_RXIMR_REG(CAN2_BASE_PTR,9) +#define CAN2_RXIMR10 CAN_RXIMR_REG(CAN2_BASE_PTR,10) +#define CAN2_RXIMR11 CAN_RXIMR_REG(CAN2_BASE_PTR,11) +#define CAN2_RXIMR12 CAN_RXIMR_REG(CAN2_BASE_PTR,12) +#define CAN2_RXIMR13 CAN_RXIMR_REG(CAN2_BASE_PTR,13) +#define CAN2_RXIMR14 CAN_RXIMR_REG(CAN2_BASE_PTR,14) +#define CAN2_RXIMR15 CAN_RXIMR_REG(CAN2_BASE_PTR,15) +#define CAN2_RXIMR16 CAN_RXIMR_REG(CAN2_BASE_PTR,16) +#define CAN2_RXIMR17 CAN_RXIMR_REG(CAN2_BASE_PTR,17) +#define CAN2_RXIMR18 CAN_RXIMR_REG(CAN2_BASE_PTR,18) +#define CAN2_RXIMR19 CAN_RXIMR_REG(CAN2_BASE_PTR,19) +#define CAN2_RXIMR20 CAN_RXIMR_REG(CAN2_BASE_PTR,20) +#define CAN2_RXIMR21 CAN_RXIMR_REG(CAN2_BASE_PTR,21) +#define CAN2_RXIMR22 CAN_RXIMR_REG(CAN2_BASE_PTR,22) +#define CAN2_RXIMR23 CAN_RXIMR_REG(CAN2_BASE_PTR,23) +#define CAN2_RXIMR24 CAN_RXIMR_REG(CAN2_BASE_PTR,24) +#define CAN2_RXIMR25 CAN_RXIMR_REG(CAN2_BASE_PTR,25) +#define CAN2_RXIMR26 CAN_RXIMR_REG(CAN2_BASE_PTR,26) +#define CAN2_RXIMR27 CAN_RXIMR_REG(CAN2_BASE_PTR,27) +#define CAN2_RXIMR28 CAN_RXIMR_REG(CAN2_BASE_PTR,28) +#define CAN2_RXIMR29 CAN_RXIMR_REG(CAN2_BASE_PTR,29) +#define CAN2_RXIMR30 CAN_RXIMR_REG(CAN2_BASE_PTR,30) +#define CAN2_RXIMR31 CAN_RXIMR_REG(CAN2_BASE_PTR,31) +#define CAN2_RXIMR32 CAN_RXIMR_REG(CAN2_BASE_PTR,32) +#define CAN2_RXIMR33 CAN_RXIMR_REG(CAN2_BASE_PTR,33) +#define CAN2_RXIMR34 CAN_RXIMR_REG(CAN2_BASE_PTR,34) +#define CAN2_RXIMR35 CAN_RXIMR_REG(CAN2_BASE_PTR,35) +#define CAN2_RXIMR36 CAN_RXIMR_REG(CAN2_BASE_PTR,36) +#define CAN2_RXIMR37 CAN_RXIMR_REG(CAN2_BASE_PTR,37) +#define CAN2_RXIMR38 CAN_RXIMR_REG(CAN2_BASE_PTR,38) +#define CAN2_RXIMR39 CAN_RXIMR_REG(CAN2_BASE_PTR,39) +#define CAN2_RXIMR40 CAN_RXIMR_REG(CAN2_BASE_PTR,40) +#define CAN2_RXIMR41 CAN_RXIMR_REG(CAN2_BASE_PTR,41) +#define CAN2_RXIMR42 CAN_RXIMR_REG(CAN2_BASE_PTR,42) +#define CAN2_RXIMR43 CAN_RXIMR_REG(CAN2_BASE_PTR,43) +#define CAN2_RXIMR44 CAN_RXIMR_REG(CAN2_BASE_PTR,44) +#define CAN2_RXIMR45 CAN_RXIMR_REG(CAN2_BASE_PTR,45) +#define CAN2_RXIMR46 CAN_RXIMR_REG(CAN2_BASE_PTR,46) +#define CAN2_RXIMR47 CAN_RXIMR_REG(CAN2_BASE_PTR,47) +#define CAN2_RXIMR48 CAN_RXIMR_REG(CAN2_BASE_PTR,48) +#define CAN2_RXIMR49 CAN_RXIMR_REG(CAN2_BASE_PTR,49) +#define CAN2_RXIMR50 CAN_RXIMR_REG(CAN2_BASE_PTR,50) +#define CAN2_RXIMR51 CAN_RXIMR_REG(CAN2_BASE_PTR,51) +#define CAN2_RXIMR52 CAN_RXIMR_REG(CAN2_BASE_PTR,52) +#define CAN2_RXIMR53 CAN_RXIMR_REG(CAN2_BASE_PTR,53) +#define CAN2_RXIMR54 CAN_RXIMR_REG(CAN2_BASE_PTR,54) +#define CAN2_RXIMR55 CAN_RXIMR_REG(CAN2_BASE_PTR,55) +#define CAN2_RXIMR56 CAN_RXIMR_REG(CAN2_BASE_PTR,56) +#define CAN2_RXIMR57 CAN_RXIMR_REG(CAN2_BASE_PTR,57) +#define CAN2_RXIMR58 CAN_RXIMR_REG(CAN2_BASE_PTR,58) +#define CAN2_RXIMR59 CAN_RXIMR_REG(CAN2_BASE_PTR,59) +#define CAN2_RXIMR60 CAN_RXIMR_REG(CAN2_BASE_PTR,60) +#define CAN2_RXIMR61 CAN_RXIMR_REG(CAN2_BASE_PTR,61) +#define CAN2_RXIMR62 CAN_RXIMR_REG(CAN2_BASE_PTR,62) +#define CAN2_RXIMR63 CAN_RXIMR_REG(CAN2_BASE_PTR,63) #define CAN2_GFWR CAN_GFWR_REG(CAN2_BASE_PTR) - +/* CAN - Register array accessors */ +#define CAN1_CS(index) CAN_CS_REG(CAN1_BASE_PTR,index) +#define CAN2_CS(index) CAN_CS_REG(CAN2_BASE_PTR,index) +#define CAN1_ID(index) CAN_ID_REG(CAN1_BASE_PTR,index) +#define CAN2_ID(index) CAN_ID_REG(CAN2_BASE_PTR,index) +#define CAN1_WORD0(index) CAN_WORD0_REG(CAN1_BASE_PTR,index) +#define CAN2_WORD0(index) CAN_WORD0_REG(CAN2_BASE_PTR,index) +#define CAN1_WORD1(index) CAN_WORD1_REG(CAN1_BASE_PTR,index) +#define CAN2_WORD1(index) CAN_WORD1_REG(CAN2_BASE_PTR,index) +#define CAN1_RXIMR(index) CAN_RXIMR_REG(CAN1_BASE_PTR,index) +#define CAN2_RXIMR(index) CAN_RXIMR_REG(CAN2_BASE_PTR,index) /*! * @} */ /* end of group CAN_Register_Accessor_Macros */ @@ -3903,7 +4519,6 @@ typedef struct { * @} */ /* end of group CAN_Peripheral */ - /* ---------------------------------------------------------------------------- -- CCM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -3919,3085 +4534,45 @@ typedef struct { __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */ __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */ __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */ - uint8_t RESERVED[2032]; - __IO uint32_t PLL_CTRL0; /**< CCM PLL Control Register, offset: 0x800 */ - __IO uint32_t PLL_CTRL0_SET; /**< CCM PLL Control Register, offset: 0x804 */ - __IO uint32_t PLL_CTRL0_CLR; /**< CCM PLL Control Register, offset: 0x808 */ - __IO uint32_t PLL_CTRL0_TOG; /**< CCM PLL Control Register, offset: 0x80C */ - __IO uint32_t PLL_CTRL1; /**< CCM PLL Control Register, offset: 0x810 */ - __IO uint32_t PLL_CTRL1_SET; /**< CCM PLL Control Register, offset: 0x814 */ - __IO uint32_t PLL_CTRL1_CLR; /**< CCM PLL Control Register, offset: 0x818 */ - __IO uint32_t PLL_CTRL1_TOG; /**< CCM PLL Control Register, offset: 0x81C */ - __IO uint32_t PLL_CTRL2; /**< CCM PLL Control Register, offset: 0x820 */ - __IO uint32_t PLL_CTRL2_SET; /**< CCM PLL Control Register, offset: 0x824 */ - __IO uint32_t PLL_CTRL2_CLR; /**< CCM PLL Control Register, offset: 0x828 */ - __IO uint32_t PLL_CTRL2_TOG; /**< CCM PLL Control Register, offset: 0x82C */ - __IO uint32_t PLL_CTRL3; /**< CCM PLL Control Register, offset: 0x830 */ - __IO uint32_t PLL_CTRL3_SET; /**< CCM PLL Control Register, offset: 0x834 */ - __IO uint32_t PLL_CTRL3_CLR; /**< CCM PLL Control Register, offset: 0x838 */ - __IO uint32_t PLL_CTRL3_TOG; /**< CCM PLL Control Register, offset: 0x83C */ - __IO uint32_t PLL_CTRL4; /**< CCM PLL Control Register, offset: 0x840 */ - __IO uint32_t PLL_CTRL4_SET; /**< CCM PLL Control Register, offset: 0x844 */ - __IO uint32_t PLL_CTRL4_CLR; /**< CCM PLL Control Register, offset: 0x848 */ - __IO uint32_t PLL_CTRL4_TOG; /**< CCM PLL Control Register, offset: 0x84C */ - __IO uint32_t PLL_CTRL5; /**< CCM PLL Control Register, offset: 0x850 */ - __IO uint32_t PLL_CTRL5_SET; /**< CCM PLL Control Register, offset: 0x854 */ - __IO uint32_t PLL_CTRL5_CLR; /**< CCM PLL Control Register, offset: 0x858 */ - __IO uint32_t PLL_CTRL5_TOG; /**< CCM PLL Control Register, offset: 0x85C */ - __IO uint32_t PLL_CTRL6; /**< CCM PLL Control Register, offset: 0x860 */ - __IO uint32_t PLL_CTRL6_SET; /**< CCM PLL Control Register, offset: 0x864 */ - __IO uint32_t PLL_CTRL6_CLR; /**< CCM PLL Control Register, offset: 0x868 */ - __IO uint32_t PLL_CTRL6_TOG; /**< CCM PLL Control Register, offset: 0x86C */ - __IO uint32_t PLL_CTRL7; /**< CCM PLL Control Register, offset: 0x870 */ - __IO uint32_t PLL_CTRL7_SET; /**< CCM PLL Control Register, offset: 0x874 */ - __IO uint32_t PLL_CTRL7_CLR; /**< CCM PLL Control Register, offset: 0x878 */ - __IO uint32_t PLL_CTRL7_TOG; /**< CCM PLL Control Register, offset: 0x87C */ - __IO uint32_t PLL_CTRL8; /**< CCM PLL Control Register, offset: 0x880 */ - __IO uint32_t PLL_CTRL8_SET; /**< CCM PLL Control Register, offset: 0x884 */ - __IO uint32_t PLL_CTRL8_CLR; /**< CCM PLL Control Register, offset: 0x888 */ - __IO uint32_t PLL_CTRL8_TOG; /**< CCM PLL Control Register, offset: 0x88C */ - __IO uint32_t PLL_CTRL9; /**< CCM PLL Control Register, offset: 0x890 */ - __IO uint32_t PLL_CTRL9_SET; /**< CCM PLL Control Register, offset: 0x894 */ - __IO uint32_t PLL_CTRL9_CLR; /**< CCM PLL Control Register, offset: 0x898 */ - __IO uint32_t PLL_CTRL9_TOG; /**< CCM PLL Control Register, offset: 0x89C */ - __IO uint32_t PLL_CTRL10; /**< CCM PLL Control Register, offset: 0x8A0 */ - __IO uint32_t PLL_CTRL10_SET; /**< CCM PLL Control Register, offset: 0x8A4 */ - __IO uint32_t PLL_CTRL10_CLR; /**< CCM PLL Control Register, offset: 0x8A8 */ - __IO uint32_t PLL_CTRL10_TOG; /**< CCM PLL Control Register, offset: 0x8AC */ - __IO uint32_t PLL_CTRL11; /**< CCM PLL Control Register, offset: 0x8B0 */ - __IO uint32_t PLL_CTRL11_SET; /**< CCM PLL Control Register, offset: 0x8B4 */ - __IO uint32_t PLL_CTRL11_CLR; /**< CCM PLL Control Register, offset: 0x8B8 */ - __IO uint32_t PLL_CTRL11_TOG; /**< CCM PLL Control Register, offset: 0x8BC */ - __IO uint32_t PLL_CTRL12; /**< CCM PLL Control Register, offset: 0x8C0 */ - __IO uint32_t PLL_CTRL12_SET; /**< CCM PLL Control Register, offset: 0x8C4 */ - __IO uint32_t PLL_CTRL12_CLR; /**< CCM PLL Control Register, offset: 0x8C8 */ - __IO uint32_t PLL_CTRL12_TOG; /**< CCM PLL Control Register, offset: 0x8CC */ - __IO uint32_t PLL_CTRL13; /**< CCM PLL Control Register, offset: 0x8D0 */ - __IO uint32_t PLL_CTRL13_SET; /**< CCM PLL Control Register, offset: 0x8D4 */ - __IO uint32_t PLL_CTRL13_CLR; /**< CCM PLL Control Register, offset: 0x8D8 */ - __IO uint32_t PLL_CTRL13_TOG; /**< CCM PLL Control Register, offset: 0x8DC */ - __IO uint32_t PLL_CTRL14; /**< CCM PLL Control Register, offset: 0x8E0 */ - __IO uint32_t PLL_CTRL14_SET; /**< CCM PLL Control Register, offset: 0x8E4 */ - __IO uint32_t PLL_CTRL14_CLR; /**< CCM PLL Control Register, offset: 0x8E8 */ - __IO uint32_t PLL_CTRL14_TOG; /**< CCM PLL Control Register, offset: 0x8EC */ - __IO uint32_t PLL_CTRL15; /**< CCM PLL Control Register, offset: 0x8F0 */ - __IO uint32_t PLL_CTRL15_SET; /**< CCM PLL Control Register, offset: 0x8F4 */ - __IO uint32_t PLL_CTRL15_CLR; /**< CCM PLL Control Register, offset: 0x8F8 */ - __IO uint32_t PLL_CTRL15_TOG; /**< CCM PLL Control Register, offset: 0x8FC */ - __IO uint32_t PLL_CTRL16; /**< CCM PLL Control Register, offset: 0x900 */ - __IO uint32_t PLL_CTRL16_SET; /**< CCM PLL Control Register, offset: 0x904 */ - __IO uint32_t PLL_CTRL16_CLR; /**< CCM PLL Control Register, offset: 0x908 */ - __IO uint32_t PLL_CTRL16_TOG; /**< CCM PLL Control Register, offset: 0x90C */ - __IO uint32_t PLL_CTRL17; /**< CCM PLL Control Register, offset: 0x910 */ - __IO uint32_t PLL_CTRL17_SET; /**< CCM PLL Control Register, offset: 0x914 */ - __IO uint32_t PLL_CTRL17_CLR; /**< CCM PLL Control Register, offset: 0x918 */ - __IO uint32_t PLL_CTRL17_TOG; /**< CCM PLL Control Register, offset: 0x91C */ - __IO uint32_t PLL_CTRL18; /**< CCM PLL Control Register, offset: 0x920 */ - __IO uint32_t PLL_CTRL18_SET; /**< CCM PLL Control Register, offset: 0x924 */ - __IO uint32_t PLL_CTRL18_CLR; /**< CCM PLL Control Register, offset: 0x928 */ - __IO uint32_t PLL_CTRL18_TOG; /**< CCM PLL Control Register, offset: 0x92C */ - __IO uint32_t PLL_CTRL19; /**< CCM PLL Control Register, offset: 0x930 */ - __IO uint32_t PLL_CTRL19_SET; /**< CCM PLL Control Register, offset: 0x934 */ - __IO uint32_t PLL_CTRL19_CLR; /**< CCM PLL Control Register, offset: 0x938 */ - __IO uint32_t PLL_CTRL19_TOG; /**< CCM PLL Control Register, offset: 0x93C */ - __IO uint32_t PLL_CTRL20; /**< CCM PLL Control Register, offset: 0x940 */ - __IO uint32_t PLL_CTRL20_SET; /**< CCM PLL Control Register, offset: 0x944 */ - __IO uint32_t PLL_CTRL20_CLR; /**< CCM PLL Control Register, offset: 0x948 */ - __IO uint32_t PLL_CTRL20_TOG; /**< CCM PLL Control Register, offset: 0x94C */ - __IO uint32_t PLL_CTRL21; /**< CCM PLL Control Register, offset: 0x950 */ - __IO uint32_t PLL_CTRL21_SET; /**< CCM PLL Control Register, offset: 0x954 */ - __IO uint32_t PLL_CTRL21_CLR; /**< CCM PLL Control Register, offset: 0x958 */ - __IO uint32_t PLL_CTRL21_TOG; /**< CCM PLL Control Register, offset: 0x95C */ - __IO uint32_t PLL_CTRL22; /**< CCM PLL Control Register, offset: 0x960 */ - __IO uint32_t PLL_CTRL22_SET; /**< CCM PLL Control Register, offset: 0x964 */ - __IO uint32_t PLL_CTRL22_CLR; /**< CCM PLL Control Register, offset: 0x968 */ - __IO uint32_t PLL_CTRL22_TOG; /**< CCM PLL Control Register, offset: 0x96C */ - __IO uint32_t PLL_CTRL23; /**< CCM PLL Control Register, offset: 0x970 */ - __IO uint32_t PLL_CTRL23_SET; /**< CCM PLL Control Register, offset: 0x974 */ - __IO uint32_t PLL_CTRL23_CLR; /**< CCM PLL Control Register, offset: 0x978 */ - __IO uint32_t PLL_CTRL23_TOG; /**< CCM PLL Control Register, offset: 0x97C */ - __IO uint32_t PLL_CTRL24; /**< CCM PLL Control Register, offset: 0x980 */ - __IO uint32_t PLL_CTRL24_SET; /**< CCM PLL Control Register, offset: 0x984 */ - __IO uint32_t PLL_CTRL24_CLR; /**< CCM PLL Control Register, offset: 0x988 */ - __IO uint32_t PLL_CTRL24_TOG; /**< CCM PLL Control Register, offset: 0x98C */ - __IO uint32_t PLL_CTRL25; /**< CCM PLL Control Register, offset: 0x990 */ - __IO uint32_t PLL_CTRL25_SET; /**< CCM PLL Control Register, offset: 0x994 */ - __IO uint32_t PLL_CTRL25_CLR; /**< CCM PLL Control Register, offset: 0x998 */ - __IO uint32_t PLL_CTRL25_TOG; /**< CCM PLL Control Register, offset: 0x99C */ - __IO uint32_t PLL_CTRL26; /**< CCM PLL Control Register, offset: 0x9A0 */ - __IO uint32_t PLL_CTRL26_SET; /**< CCM PLL Control Register, offset: 0x9A4 */ - __IO uint32_t PLL_CTRL26_CLR; /**< CCM PLL Control Register, offset: 0x9A8 */ - __IO uint32_t PLL_CTRL26_TOG; /**< CCM PLL Control Register, offset: 0x9AC */ - __IO uint32_t PLL_CTRL27; /**< CCM PLL Control Register, offset: 0x9B0 */ - __IO uint32_t PLL_CTRL27_SET; /**< CCM PLL Control Register, offset: 0x9B4 */ - __IO uint32_t PLL_CTRL27_CLR; /**< CCM PLL Control Register, offset: 0x9B8 */ - __IO uint32_t PLL_CTRL27_TOG; /**< CCM PLL Control Register, offset: 0x9BC */ - __IO uint32_t PLL_CTRL28; /**< CCM PLL Control Register, offset: 0x9C0 */ - __IO uint32_t PLL_CTRL28_SET; /**< CCM PLL Control Register, offset: 0x9C4 */ - __IO uint32_t PLL_CTRL28_CLR; /**< CCM PLL Control Register, offset: 0x9C8 */ - __IO uint32_t PLL_CTRL28_TOG; /**< CCM PLL Control Register, offset: 0x9CC */ - __IO uint32_t PLL_CTRL29; /**< CCM PLL Control Register, offset: 0x9D0 */ - __IO uint32_t PLL_CTRL29_SET; /**< CCM PLL Control Register, offset: 0x9D4 */ - __IO uint32_t PLL_CTRL29_CLR; /**< CCM PLL Control Register, offset: 0x9D8 */ - __IO uint32_t PLL_CTRL29_TOG; /**< CCM PLL Control Register, offset: 0x9DC */ - __IO uint32_t PLL_CTRL30; /**< CCM PLL Control Register, offset: 0x9E0 */ - __IO uint32_t PLL_CTRL30_SET; /**< CCM PLL Control Register, offset: 0x9E4 */ - __IO uint32_t PLL_CTRL30_CLR; /**< CCM PLL Control Register, offset: 0x9E8 */ - __IO uint32_t PLL_CTRL30_TOG; /**< CCM PLL Control Register, offset: 0x9EC */ - __IO uint32_t PLL_CTRL31; /**< CCM PLL Control Register, offset: 0x9F0 */ - __IO uint32_t PLL_CTRL31_SET; /**< CCM PLL Control Register, offset: 0x9F4 */ - __IO uint32_t PLL_CTRL31_CLR; /**< CCM PLL Control Register, offset: 0x9F8 */ - __IO uint32_t PLL_CTRL31_TOG; /**< CCM PLL Control Register, offset: 0x9FC */ - __IO uint32_t PLL_CTRL32; /**< CCM PLL Control Register, offset: 0xA00 */ - __IO uint32_t PLL_CTRL32_SET; /**< CCM PLL Control Register, offset: 0xA04 */ - __IO uint32_t PLL_CTRL32_CLR; /**< CCM PLL Control Register, offset: 0xA08 */ - __IO uint32_t PLL_CTRL32_TOG; /**< CCM PLL Control Register, offset: 0xA0C */ - uint8_t RESERVED_0[13808]; - __IO uint32_t CCGR0; /**< CCM Clock Gating Register, offset: 0x4000 */ - __IO uint32_t CCGR0_SET; /**< CCM Clock Gating Register, offset: 0x4004 */ - __IO uint32_t CCGR0_CLR; /**< CCM Clock Gating Register, offset: 0x4008 */ - __IO uint32_t CCGR0_TOG; /**< CCM Clock Gating Register, offset: 0x400C */ - __IO uint32_t CCGR1; /**< CCM Clock Gating Register, offset: 0x4010 */ - __IO uint32_t CCGR1_SET; /**< CCM Clock Gating Register, offset: 0x4014 */ - __IO uint32_t CCGR1_CLR; /**< CCM Clock Gating Register, offset: 0x4018 */ - __IO uint32_t CCGR1_TOG; /**< CCM Clock Gating Register, offset: 0x401C */ - __IO uint32_t CCGR2; /**< CCM Clock Gating Register, offset: 0x4020 */ - __IO uint32_t CCGR2_SET; /**< CCM Clock Gating Register, offset: 0x4024 */ - __IO uint32_t CCGR2_CLR; /**< CCM Clock Gating Register, offset: 0x4028 */ - __IO uint32_t CCGR2_TOG; /**< CCM Clock Gating Register, offset: 0x402C */ - __IO uint32_t CCGR3; /**< CCM Clock Gating Register, offset: 0x4030 */ - __IO uint32_t CCGR3_SET; /**< CCM Clock Gating Register, offset: 0x4034 */ - __IO uint32_t CCGR3_CLR; /**< CCM Clock Gating Register, offset: 0x4038 */ - __IO uint32_t CCGR3_TOG; /**< CCM Clock Gating Register, offset: 0x403C */ - __IO uint32_t CCGR4; /**< CCM Clock Gating Register, offset: 0x4040 */ - __IO uint32_t CCGR4_SET; /**< CCM Clock Gating Register, offset: 0x4044 */ - __IO uint32_t CCGR4_CLR; /**< CCM Clock Gating Register, offset: 0x4048 */ - __IO uint32_t CCGR4_TOG; /**< CCM Clock Gating Register, offset: 0x404C */ - __IO uint32_t CCGR5; /**< CCM Clock Gating Register, offset: 0x4050 */ - __IO uint32_t CCGR5_SET; /**< CCM Clock Gating Register, offset: 0x4054 */ - __IO uint32_t CCGR5_CLR; /**< CCM Clock Gating Register, offset: 0x4058 */ - __IO uint32_t CCGR5_TOG; /**< CCM Clock Gating Register, offset: 0x405C */ - __IO uint32_t CCGR6; /**< CCM Clock Gating Register, offset: 0x4060 */ - __IO uint32_t CCGR6_SET; /**< CCM Clock Gating Register, offset: 0x4064 */ - __IO uint32_t CCGR6_CLR; /**< CCM Clock Gating Register, offset: 0x4068 */ - __IO uint32_t CCGR6_TOG; /**< CCM Clock Gating Register, offset: 0x406C */ - __IO uint32_t CCGR7; /**< CCM Clock Gating Register, offset: 0x4070 */ - __IO uint32_t CCGR7_SET; /**< CCM Clock Gating Register, offset: 0x4074 */ - __IO uint32_t CCGR7_CLR; /**< CCM Clock Gating Register, offset: 0x4078 */ - __IO uint32_t CCGR7_TOG; /**< CCM Clock Gating Register, offset: 0x407C */ - __IO uint32_t CCGR8; /**< CCM Clock Gating Register, offset: 0x4080 */ - __IO uint32_t CCGR8_SET; /**< CCM Clock Gating Register, offset: 0x4084 */ - __IO uint32_t CCGR8_CLR; /**< CCM Clock Gating Register, offset: 0x4088 */ - __IO uint32_t CCGR8_TOG; /**< CCM Clock Gating Register, offset: 0x408C */ - __IO uint32_t CCGR9; /**< CCM Clock Gating Register, offset: 0x4090 */ - __IO uint32_t CCGR9_SET; /**< CCM Clock Gating Register, offset: 0x4094 */ - __IO uint32_t CCGR9_CLR; /**< CCM Clock Gating Register, offset: 0x4098 */ - __IO uint32_t CCGR9_TOG; /**< CCM Clock Gating Register, offset: 0x409C */ - __IO uint32_t CCGR10; /**< CCM Clock Gating Register, offset: 0x40A0 */ - __IO uint32_t CCGR10_SET; /**< CCM Clock Gating Register, offset: 0x40A4 */ - __IO uint32_t CCGR10_CLR; /**< CCM Clock Gating Register, offset: 0x40A8 */ - __IO uint32_t CCGR10_TOG; /**< CCM Clock Gating Register, offset: 0x40AC */ - __IO uint32_t CCGR11; /**< CCM Clock Gating Register, offset: 0x40B0 */ - __IO uint32_t CCGR11_SET; /**< CCM Clock Gating Register, offset: 0x40B4 */ - __IO uint32_t CCGR11_CLR; /**< CCM Clock Gating Register, offset: 0x40B8 */ - __IO uint32_t CCGR11_TOG; /**< CCM Clock Gating Register, offset: 0x40BC */ - __IO uint32_t CCGR12; /**< CCM Clock Gating Register, offset: 0x40C0 */ - __IO uint32_t CCGR12_SET; /**< CCM Clock Gating Register, offset: 0x40C4 */ - __IO uint32_t CCGR12_CLR; /**< CCM Clock Gating Register, offset: 0x40C8 */ - __IO uint32_t CCGR12_TOG; /**< CCM Clock Gating Register, offset: 0x40CC */ - __IO uint32_t CCGR13; /**< CCM Clock Gating Register, offset: 0x40D0 */ - __IO uint32_t CCGR13_SET; /**< CCM Clock Gating Register, offset: 0x40D4 */ - __IO uint32_t CCGR13_CLR; /**< CCM Clock Gating Register, offset: 0x40D8 */ - __IO uint32_t CCGR13_TOG; /**< CCM Clock Gating Register, offset: 0x40DC */ - __IO uint32_t CCGR14; /**< CCM Clock Gating Register, offset: 0x40E0 */ - __IO uint32_t CCGR14_SET; /**< CCM Clock Gating Register, offset: 0x40E4 */ - __IO uint32_t CCGR14_CLR; /**< CCM Clock Gating Register, offset: 0x40E8 */ - __IO uint32_t CCGR14_TOG; /**< CCM Clock Gating Register, offset: 0x40EC */ - __IO uint32_t CCGR15; /**< CCM Clock Gating Register, offset: 0x40F0 */ - __IO uint32_t CCGR15_SET; /**< CCM Clock Gating Register, offset: 0x40F4 */ - __IO uint32_t CCGR15_CLR; /**< CCM Clock Gating Register, offset: 0x40F8 */ - __IO uint32_t CCGR15_TOG; /**< CCM Clock Gating Register, offset: 0x40FC */ - __IO uint32_t CCGR16; /**< CCM Clock Gating Register, offset: 0x4100 */ - __IO uint32_t CCGR16_SET; /**< CCM Clock Gating Register, offset: 0x4104 */ - __IO uint32_t CCGR16_CLR; /**< CCM Clock Gating Register, offset: 0x4108 */ - __IO uint32_t CCGR16_TOG; /**< CCM Clock Gating Register, offset: 0x410C */ - __IO uint32_t CCGR17; /**< CCM Clock Gating Register, offset: 0x4110 */ - __IO uint32_t CCGR17_SET; /**< CCM Clock Gating Register, offset: 0x4114 */ - __IO uint32_t CCGR17_CLR; /**< CCM Clock Gating Register, offset: 0x4118 */ - __IO uint32_t CCGR17_TOG; /**< CCM Clock Gating Register, offset: 0x411C */ - __IO uint32_t CCGR18; /**< CCM Clock Gating Register, offset: 0x4120 */ - __IO uint32_t CCGR18_SET; /**< CCM Clock Gating Register, offset: 0x4124 */ - __IO uint32_t CCGR18_CLR; /**< CCM Clock Gating Register, offset: 0x4128 */ - __IO uint32_t CCGR18_TOG; /**< CCM Clock Gating Register, offset: 0x412C */ - __IO uint32_t CCGR19; /**< CCM Clock Gating Register, offset: 0x4130 */ - __IO uint32_t CCGR19_SET; /**< CCM Clock Gating Register, offset: 0x4134 */ - __IO uint32_t CCGR19_CLR; /**< CCM Clock Gating Register, offset: 0x4138 */ - __IO uint32_t CCGR19_TOG; /**< CCM Clock Gating Register, offset: 0x413C */ - __IO uint32_t CCGR20; /**< CCM Clock Gating Register, offset: 0x4140 */ - __IO uint32_t CCGR20_SET; /**< CCM Clock Gating Register, offset: 0x4144 */ - __IO uint32_t CCGR20_CLR; /**< CCM Clock Gating Register, offset: 0x4148 */ - __IO uint32_t CCGR20_TOG; /**< CCM Clock Gating Register, offset: 0x414C */ - __IO uint32_t CCGR21; /**< CCM Clock Gating Register, offset: 0x4150 */ - __IO uint32_t CCGR21_SET; /**< CCM Clock Gating Register, offset: 0x4154 */ - __IO uint32_t CCGR21_CLR; /**< CCM Clock Gating Register, offset: 0x4158 */ - __IO uint32_t CCGR21_TOG; /**< CCM Clock Gating Register, offset: 0x415C */ - __IO uint32_t CCGR22; /**< CCM Clock Gating Register, offset: 0x4160 */ - __IO uint32_t CCGR22_SET; /**< CCM Clock Gating Register, offset: 0x4164 */ - __IO uint32_t CCGR22_CLR; /**< CCM Clock Gating Register, offset: 0x4168 */ - __IO uint32_t CCGR22_TOG; /**< CCM Clock Gating Register, offset: 0x416C */ - __IO uint32_t CCGR23; /**< CCM Clock Gating Register, offset: 0x4170 */ - __IO uint32_t CCGR23_SET; /**< CCM Clock Gating Register, offset: 0x4174 */ - __IO uint32_t CCGR23_CLR; /**< CCM Clock Gating Register, offset: 0x4178 */ - __IO uint32_t CCGR23_TOG; /**< CCM Clock Gating Register, offset: 0x417C */ - __IO uint32_t CCGR24; /**< CCM Clock Gating Register, offset: 0x4180 */ - __IO uint32_t CCGR24_SET; /**< CCM Clock Gating Register, offset: 0x4184 */ - __IO uint32_t CCGR24_CLR; /**< CCM Clock Gating Register, offset: 0x4188 */ - __IO uint32_t CCGR24_TOG; /**< CCM Clock Gating Register, offset: 0x418C */ - __IO uint32_t CCGR25; /**< CCM Clock Gating Register, offset: 0x4190 */ - __IO uint32_t CCGR25_SET; /**< CCM Clock Gating Register, offset: 0x4194 */ - __IO uint32_t CCGR25_CLR; /**< CCM Clock Gating Register, offset: 0x4198 */ - __IO uint32_t CCGR25_TOG; /**< CCM Clock Gating Register, offset: 0x419C */ - __IO uint32_t CCGR26; /**< CCM Clock Gating Register, offset: 0x41A0 */ - __IO uint32_t CCGR26_SET; /**< CCM Clock Gating Register, offset: 0x41A4 */ - __IO uint32_t CCGR26_CLR; /**< CCM Clock Gating Register, offset: 0x41A8 */ - __IO uint32_t CCGR26_TOG; /**< CCM Clock Gating Register, offset: 0x41AC */ - __IO uint32_t CCGR27; /**< CCM Clock Gating Register, offset: 0x41B0 */ - __IO uint32_t CCGR27_SET; /**< CCM Clock Gating Register, offset: 0x41B4 */ - __IO uint32_t CCGR27_CLR; /**< CCM Clock Gating Register, offset: 0x41B8 */ - __IO uint32_t CCGR27_TOG; /**< CCM Clock Gating Register, offset: 0x41BC */ - __IO uint32_t CCGR28; /**< CCM Clock Gating Register, offset: 0x41C0 */ - __IO uint32_t CCGR28_SET; /**< CCM Clock Gating Register, offset: 0x41C4 */ - __IO uint32_t CCGR28_CLR; /**< CCM Clock Gating Register, offset: 0x41C8 */ - __IO uint32_t CCGR28_TOG; /**< CCM Clock Gating Register, offset: 0x41CC */ - __IO uint32_t CCGR29; /**< CCM Clock Gating Register, offset: 0x41D0 */ - __IO uint32_t CCGR29_SET; /**< CCM Clock Gating Register, offset: 0x41D4 */ - __IO uint32_t CCGR29_CLR; /**< CCM Clock Gating Register, offset: 0x41D8 */ - __IO uint32_t CCGR29_TOG; /**< CCM Clock Gating Register, offset: 0x41DC */ - __IO uint32_t CCGR30; /**< CCM Clock Gating Register, offset: 0x41E0 */ - __IO uint32_t CCGR30_SET; /**< CCM Clock Gating Register, offset: 0x41E4 */ - __IO uint32_t CCGR30_CLR; /**< CCM Clock Gating Register, offset: 0x41E8 */ - __IO uint32_t CCGR30_TOG; /**< CCM Clock Gating Register, offset: 0x41EC */ - __IO uint32_t CCGR31; /**< CCM Clock Gating Register, offset: 0x41F0 */ - __IO uint32_t CCGR31_SET; /**< CCM Clock Gating Register, offset: 0x41F4 */ - __IO uint32_t CCGR31_CLR; /**< CCM Clock Gating Register, offset: 0x41F8 */ - __IO uint32_t CCGR31_TOG; /**< CCM Clock Gating Register, offset: 0x41FC */ - __IO uint32_t CCGR32; /**< CCM Clock Gating Register, offset: 0x4200 */ - __IO uint32_t CCGR32_SET; /**< CCM Clock Gating Register, offset: 0x4204 */ - __IO uint32_t CCGR32_CLR; /**< CCM Clock Gating Register, offset: 0x4208 */ - __IO uint32_t CCGR32_TOG; /**< CCM Clock Gating Register, offset: 0x420C */ - __IO uint32_t CCGR33; /**< CCM Clock Gating Register, offset: 0x4210 */ - __IO uint32_t CCGR33_SET; /**< CCM Clock Gating Register, offset: 0x4214 */ - __IO uint32_t CCGR33_CLR; /**< CCM Clock Gating Register, offset: 0x4218 */ - __IO uint32_t CCGR33_TOG; /**< CCM Clock Gating Register, offset: 0x421C */ - __IO uint32_t CCGR34; /**< CCM Clock Gating Register, offset: 0x4220 */ - __IO uint32_t CCGR34_SET; /**< CCM Clock Gating Register, offset: 0x4224 */ - __IO uint32_t CCGR34_CLR; /**< CCM Clock Gating Register, offset: 0x4228 */ - __IO uint32_t CCGR34_TOG; /**< CCM Clock Gating Register, offset: 0x422C */ - __IO uint32_t CCGR35; /**< CCM Clock Gating Register, offset: 0x4230 */ - __IO uint32_t CCGR35_SET; /**< CCM Clock Gating Register, offset: 0x4234 */ - __IO uint32_t CCGR35_CLR; /**< CCM Clock Gating Register, offset: 0x4238 */ - __IO uint32_t CCGR35_TOG; /**< CCM Clock Gating Register, offset: 0x423C */ - __IO uint32_t CCGR36; /**< CCM Clock Gating Register, offset: 0x4240 */ - __IO uint32_t CCGR36_SET; /**< CCM Clock Gating Register, offset: 0x4244 */ - __IO uint32_t CCGR36_CLR; /**< CCM Clock Gating Register, offset: 0x4248 */ - __IO uint32_t CCGR36_TOG; /**< CCM Clock Gating Register, offset: 0x424C */ - __IO uint32_t CCGR37; /**< CCM Clock Gating Register, offset: 0x4250 */ - __IO uint32_t CCGR37_SET; /**< CCM Clock Gating Register, offset: 0x4254 */ - __IO uint32_t CCGR37_CLR; /**< CCM Clock Gating Register, offset: 0x4258 */ - __IO uint32_t CCGR37_TOG; /**< CCM Clock Gating Register, offset: 0x425C */ - __IO uint32_t CCGR38; /**< CCM Clock Gating Register, offset: 0x4260 */ - __IO uint32_t CCGR38_SET; /**< CCM Clock Gating Register, offset: 0x4264 */ - __IO uint32_t CCGR38_CLR; /**< CCM Clock Gating Register, offset: 0x4268 */ - __IO uint32_t CCGR38_TOG; /**< CCM Clock Gating Register, offset: 0x426C */ - __IO uint32_t CCGR39; /**< CCM Clock Gating Register, offset: 0x4270 */ - __IO uint32_t CCGR39_SET; /**< CCM Clock Gating Register, offset: 0x4274 */ - __IO uint32_t CCGR39_CLR; /**< CCM Clock Gating Register, offset: 0x4278 */ - __IO uint32_t CCGR39_TOG; /**< CCM Clock Gating Register, offset: 0x427C */ - __IO uint32_t CCGR40; /**< CCM Clock Gating Register, offset: 0x4280 */ - __IO uint32_t CCGR40_SET; /**< CCM Clock Gating Register, offset: 0x4284 */ - __IO uint32_t CCGR40_CLR; /**< CCM Clock Gating Register, offset: 0x4288 */ - __IO uint32_t CCGR40_TOG; /**< CCM Clock Gating Register, offset: 0x428C */ - __IO uint32_t CCGR41; /**< CCM Clock Gating Register, offset: 0x4290 */ - __IO uint32_t CCGR41_SET; /**< CCM Clock Gating Register, offset: 0x4294 */ - __IO uint32_t CCGR41_CLR; /**< CCM Clock Gating Register, offset: 0x4298 */ - __IO uint32_t CCGR41_TOG; /**< CCM Clock Gating Register, offset: 0x429C */ - __IO uint32_t CCGR42; /**< CCM Clock Gating Register, offset: 0x42A0 */ - __IO uint32_t CCGR42_SET; /**< CCM Clock Gating Register, offset: 0x42A4 */ - __IO uint32_t CCGR42_CLR; /**< CCM Clock Gating Register, offset: 0x42A8 */ - __IO uint32_t CCGR42_TOG; /**< CCM Clock Gating Register, offset: 0x42AC */ - __IO uint32_t CCGR43; /**< CCM Clock Gating Register, offset: 0x42B0 */ - __IO uint32_t CCGR43_SET; /**< CCM Clock Gating Register, offset: 0x42B4 */ - __IO uint32_t CCGR43_CLR; /**< CCM Clock Gating Register, offset: 0x42B8 */ - __IO uint32_t CCGR43_TOG; /**< CCM Clock Gating Register, offset: 0x42BC */ - __IO uint32_t CCGR44; /**< CCM Clock Gating Register, offset: 0x42C0 */ - __IO uint32_t CCGR44_SET; /**< CCM Clock Gating Register, offset: 0x42C4 */ - __IO uint32_t CCGR44_CLR; /**< CCM Clock Gating Register, offset: 0x42C8 */ - __IO uint32_t CCGR44_TOG; /**< CCM Clock Gating Register, offset: 0x42CC */ - __IO uint32_t CCGR45; /**< CCM Clock Gating Register, offset: 0x42D0 */ - __IO uint32_t CCGR45_SET; /**< CCM Clock Gating Register, offset: 0x42D4 */ - __IO uint32_t CCGR45_CLR; /**< CCM Clock Gating Register, offset: 0x42D8 */ - __IO uint32_t CCGR45_TOG; /**< CCM Clock Gating Register, offset: 0x42DC */ - __IO uint32_t CCGR46; /**< CCM Clock Gating Register, offset: 0x42E0 */ - __IO uint32_t CCGR46_SET; /**< CCM Clock Gating Register, offset: 0x42E4 */ - __IO uint32_t CCGR46_CLR; /**< CCM Clock Gating Register, offset: 0x42E8 */ - __IO uint32_t CCGR46_TOG; /**< CCM Clock Gating Register, offset: 0x42EC */ - __IO uint32_t CCGR47; /**< CCM Clock Gating Register, offset: 0x42F0 */ - __IO uint32_t CCGR47_SET; /**< CCM Clock Gating Register, offset: 0x42F4 */ - __IO uint32_t CCGR47_CLR; /**< CCM Clock Gating Register, offset: 0x42F8 */ - __IO uint32_t CCGR47_TOG; /**< CCM Clock Gating Register, offset: 0x42FC */ - __IO uint32_t CCGR48; /**< CCM Clock Gating Register, offset: 0x4300 */ - __IO uint32_t CCGR48_SET; /**< CCM Clock Gating Register, offset: 0x4304 */ - __IO uint32_t CCGR48_CLR; /**< CCM Clock Gating Register, offset: 0x4308 */ - __IO uint32_t CCGR48_TOG; /**< CCM Clock Gating Register, offset: 0x430C */ - __IO uint32_t CCGR49; /**< CCM Clock Gating Register, offset: 0x4310 */ - __IO uint32_t CCGR49_SET; /**< CCM Clock Gating Register, offset: 0x4314 */ - __IO uint32_t CCGR49_CLR; /**< CCM Clock Gating Register, offset: 0x4318 */ - __IO uint32_t CCGR49_TOG; /**< CCM Clock Gating Register, offset: 0x431C */ - __IO uint32_t CCGR50; /**< CCM Clock Gating Register, offset: 0x4320 */ - __IO uint32_t CCGR50_SET; /**< CCM Clock Gating Register, offset: 0x4324 */ - __IO uint32_t CCGR50_CLR; /**< CCM Clock Gating Register, offset: 0x4328 */ - __IO uint32_t CCGR50_TOG; /**< CCM Clock Gating Register, offset: 0x432C */ - __IO uint32_t CCGR51; /**< CCM Clock Gating Register, offset: 0x4330 */ - __IO uint32_t CCGR51_SET; /**< CCM Clock Gating Register, offset: 0x4334 */ - __IO uint32_t CCGR51_CLR; /**< CCM Clock Gating Register, offset: 0x4338 */ - __IO uint32_t CCGR51_TOG; /**< CCM Clock Gating Register, offset: 0x433C */ - __IO uint32_t CCGR52; /**< CCM Clock Gating Register, offset: 0x4340 */ - __IO uint32_t CCGR52_SET; /**< CCM Clock Gating Register, offset: 0x4344 */ - __IO uint32_t CCGR52_CLR; /**< CCM Clock Gating Register, offset: 0x4348 */ - __IO uint32_t CCGR52_TOG; /**< CCM Clock Gating Register, offset: 0x434C */ - __IO uint32_t CCGR53; /**< CCM Clock Gating Register, offset: 0x4350 */ - __IO uint32_t CCGR53_SET; /**< CCM Clock Gating Register, offset: 0x4354 */ - __IO uint32_t CCGR53_CLR; /**< CCM Clock Gating Register, offset: 0x4358 */ - __IO uint32_t CCGR53_TOG; /**< CCM Clock Gating Register, offset: 0x435C */ - __IO uint32_t CCGR54; /**< CCM Clock Gating Register, offset: 0x4360 */ - __IO uint32_t CCGR54_SET; /**< CCM Clock Gating Register, offset: 0x4364 */ - __IO uint32_t CCGR54_CLR; /**< CCM Clock Gating Register, offset: 0x4368 */ - __IO uint32_t CCGR54_TOG; /**< CCM Clock Gating Register, offset: 0x436C */ - __IO uint32_t CCGR55; /**< CCM Clock Gating Register, offset: 0x4370 */ - __IO uint32_t CCGR55_SET; /**< CCM Clock Gating Register, offset: 0x4374 */ - __IO uint32_t CCGR55_CLR; /**< CCM Clock Gating Register, offset: 0x4378 */ - __IO uint32_t CCGR55_TOG; /**< CCM Clock Gating Register, offset: 0x437C */ - __IO uint32_t CCGR56; /**< CCM Clock Gating Register, offset: 0x4380 */ - __IO uint32_t CCGR56_SET; /**< CCM Clock Gating Register, offset: 0x4384 */ - __IO uint32_t CCGR56_CLR; /**< CCM Clock Gating Register, offset: 0x4388 */ - __IO uint32_t CCGR56_TOG; /**< CCM Clock Gating Register, offset: 0x438C */ - __IO uint32_t CCGR57; /**< CCM Clock Gating Register, offset: 0x4390 */ - __IO uint32_t CCGR57_SET; /**< CCM Clock Gating Register, offset: 0x4394 */ - __IO uint32_t CCGR57_CLR; /**< CCM Clock Gating Register, offset: 0x4398 */ - __IO uint32_t CCGR57_TOG; /**< CCM Clock Gating Register, offset: 0x439C */ - __IO uint32_t CCGR58; /**< CCM Clock Gating Register, offset: 0x43A0 */ - __IO uint32_t CCGR58_SET; /**< CCM Clock Gating Register, offset: 0x43A4 */ - __IO uint32_t CCGR58_CLR; /**< CCM Clock Gating Register, offset: 0x43A8 */ - __IO uint32_t CCGR58_TOG; /**< CCM Clock Gating Register, offset: 0x43AC */ - __IO uint32_t CCGR59; /**< CCM Clock Gating Register, offset: 0x43B0 */ - __IO uint32_t CCGR59_SET; /**< CCM Clock Gating Register, offset: 0x43B4 */ - __IO uint32_t CCGR59_CLR; /**< CCM Clock Gating Register, offset: 0x43B8 */ - __IO uint32_t CCGR59_TOG; /**< CCM Clock Gating Register, offset: 0x43BC */ - __IO uint32_t CCGR60; /**< CCM Clock Gating Register, offset: 0x43C0 */ - __IO uint32_t CCGR60_SET; /**< CCM Clock Gating Register, offset: 0x43C4 */ - __IO uint32_t CCGR60_CLR; /**< CCM Clock Gating Register, offset: 0x43C8 */ - __IO uint32_t CCGR60_TOG; /**< CCM Clock Gating Register, offset: 0x43CC */ - __IO uint32_t CCGR61; /**< CCM Clock Gating Register, offset: 0x43D0 */ - __IO uint32_t CCGR61_SET; /**< CCM Clock Gating Register, offset: 0x43D4 */ - __IO uint32_t CCGR61_CLR; /**< CCM Clock Gating Register, offset: 0x43D8 */ - __IO uint32_t CCGR61_TOG; /**< CCM Clock Gating Register, offset: 0x43DC */ - __IO uint32_t CCGR62; /**< CCM Clock Gating Register, offset: 0x43E0 */ - __IO uint32_t CCGR62_SET; /**< CCM Clock Gating Register, offset: 0x43E4 */ - __IO uint32_t CCGR62_CLR; /**< CCM Clock Gating Register, offset: 0x43E8 */ - __IO uint32_t CCGR62_TOG; /**< CCM Clock Gating Register, offset: 0x43EC */ - __IO uint32_t CCGR63; /**< CCM Clock Gating Register, offset: 0x43F0 */ - __IO uint32_t CCGR63_SET; /**< CCM Clock Gating Register, offset: 0x43F4 */ - __IO uint32_t CCGR63_CLR; /**< CCM Clock Gating Register, offset: 0x43F8 */ - __IO uint32_t CCGR63_TOG; /**< CCM Clock Gating Register, offset: 0x43FC */ - __IO uint32_t CCGR64; /**< CCM Clock Gating Register, offset: 0x4400 */ - __IO uint32_t CCGR64_SET; /**< CCM Clock Gating Register, offset: 0x4404 */ - __IO uint32_t CCGR64_CLR; /**< CCM Clock Gating Register, offset: 0x4408 */ - __IO uint32_t CCGR64_TOG; /**< CCM Clock Gating Register, offset: 0x440C */ - __IO uint32_t CCGR65; /**< CCM Clock Gating Register, offset: 0x4410 */ - __IO uint32_t CCGR65_SET; /**< CCM Clock Gating Register, offset: 0x4414 */ - __IO uint32_t CCGR65_CLR; /**< CCM Clock Gating Register, offset: 0x4418 */ - __IO uint32_t CCGR65_TOG; /**< CCM Clock Gating Register, offset: 0x441C */ - __IO uint32_t CCGR66; /**< CCM Clock Gating Register, offset: 0x4420 */ - __IO uint32_t CCGR66_SET; /**< CCM Clock Gating Register, offset: 0x4424 */ - __IO uint32_t CCGR66_CLR; /**< CCM Clock Gating Register, offset: 0x4428 */ - __IO uint32_t CCGR66_TOG; /**< CCM Clock Gating Register, offset: 0x442C */ - __IO uint32_t CCGR67; /**< CCM Clock Gating Register, offset: 0x4430 */ - __IO uint32_t CCGR67_SET; /**< CCM Clock Gating Register, offset: 0x4434 */ - __IO uint32_t CCGR67_CLR; /**< CCM Clock Gating Register, offset: 0x4438 */ - __IO uint32_t CCGR67_TOG; /**< CCM Clock Gating Register, offset: 0x443C */ - __IO uint32_t CCGR68; /**< CCM Clock Gating Register, offset: 0x4440 */ - __IO uint32_t CCGR68_SET; /**< CCM Clock Gating Register, offset: 0x4444 */ - __IO uint32_t CCGR68_CLR; /**< CCM Clock Gating Register, offset: 0x4448 */ - __IO uint32_t CCGR68_TOG; /**< CCM Clock Gating Register, offset: 0x444C */ - __IO uint32_t CCGR69; /**< CCM Clock Gating Register, offset: 0x4450 */ - __IO uint32_t CCGR69_SET; /**< CCM Clock Gating Register, offset: 0x4454 */ - __IO uint32_t CCGR69_CLR; /**< CCM Clock Gating Register, offset: 0x4458 */ - __IO uint32_t CCGR69_TOG; /**< CCM Clock Gating Register, offset: 0x445C */ - __IO uint32_t CCGR70; /**< CCM Clock Gating Register, offset: 0x4460 */ - __IO uint32_t CCGR70_SET; /**< CCM Clock Gating Register, offset: 0x4464 */ - __IO uint32_t CCGR70_CLR; /**< CCM Clock Gating Register, offset: 0x4468 */ - __IO uint32_t CCGR70_TOG; /**< CCM Clock Gating Register, offset: 0x446C */ - __IO uint32_t CCGR71; /**< CCM Clock Gating Register, offset: 0x4470 */ - __IO uint32_t CCGR71_SET; /**< CCM Clock Gating Register, offset: 0x4474 */ - __IO uint32_t CCGR71_CLR; /**< CCM Clock Gating Register, offset: 0x4478 */ - __IO uint32_t CCGR71_TOG; /**< CCM Clock Gating Register, offset: 0x447C */ - __IO uint32_t CCGR72; /**< CCM Clock Gating Register, offset: 0x4480 */ - __IO uint32_t CCGR72_SET; /**< CCM Clock Gating Register, offset: 0x4484 */ - __IO uint32_t CCGR72_CLR; /**< CCM Clock Gating Register, offset: 0x4488 */ - __IO uint32_t CCGR72_TOG; /**< CCM Clock Gating Register, offset: 0x448C */ - __IO uint32_t CCGR73; /**< CCM Clock Gating Register, offset: 0x4490 */ - __IO uint32_t CCGR73_SET; /**< CCM Clock Gating Register, offset: 0x4494 */ - __IO uint32_t CCGR73_CLR; /**< CCM Clock Gating Register, offset: 0x4498 */ - __IO uint32_t CCGR73_TOG; /**< CCM Clock Gating Register, offset: 0x449C */ - __IO uint32_t CCGR74; /**< CCM Clock Gating Register, offset: 0x44A0 */ - __IO uint32_t CCGR74_SET; /**< CCM Clock Gating Register, offset: 0x44A4 */ - __IO uint32_t CCGR74_CLR; /**< CCM Clock Gating Register, offset: 0x44A8 */ - __IO uint32_t CCGR74_TOG; /**< CCM Clock Gating Register, offset: 0x44AC */ - __IO uint32_t CCGR75; /**< CCM Clock Gating Register, offset: 0x44B0 */ - __IO uint32_t CCGR75_SET; /**< CCM Clock Gating Register, offset: 0x44B4 */ - __IO uint32_t CCGR75_CLR; /**< CCM Clock Gating Register, offset: 0x44B8 */ - __IO uint32_t CCGR75_TOG; /**< CCM Clock Gating Register, offset: 0x44BC */ - __IO uint32_t CCGR76; /**< CCM Clock Gating Register, offset: 0x44C0 */ - __IO uint32_t CCGR76_SET; /**< CCM Clock Gating Register, offset: 0x44C4 */ - __IO uint32_t CCGR76_CLR; /**< CCM Clock Gating Register, offset: 0x44C8 */ - __IO uint32_t CCGR76_TOG; /**< CCM Clock Gating Register, offset: 0x44CC */ - __IO uint32_t CCGR77; /**< CCM Clock Gating Register, offset: 0x44D0 */ - __IO uint32_t CCGR77_SET; /**< CCM Clock Gating Register, offset: 0x44D4 */ - __IO uint32_t CCGR77_CLR; /**< CCM Clock Gating Register, offset: 0x44D8 */ - __IO uint32_t CCGR77_TOG; /**< CCM Clock Gating Register, offset: 0x44DC */ - __IO uint32_t CCGR78; /**< CCM Clock Gating Register, offset: 0x44E0 */ - __IO uint32_t CCGR78_SET; /**< CCM Clock Gating Register, offset: 0x44E4 */ - __IO uint32_t CCGR78_CLR; /**< CCM Clock Gating Register, offset: 0x44E8 */ - __IO uint32_t CCGR78_TOG; /**< CCM Clock Gating Register, offset: 0x44EC */ - __IO uint32_t CCGR79; /**< CCM Clock Gating Register, offset: 0x44F0 */ - __IO uint32_t CCGR79_SET; /**< CCM Clock Gating Register, offset: 0x44F4 */ - __IO uint32_t CCGR79_CLR; /**< CCM Clock Gating Register, offset: 0x44F8 */ - __IO uint32_t CCGR79_TOG; /**< CCM Clock Gating Register, offset: 0x44FC */ - __IO uint32_t CCGR80; /**< CCM Clock Gating Register, offset: 0x4500 */ - __IO uint32_t CCGR80_SET; /**< CCM Clock Gating Register, offset: 0x4504 */ - __IO uint32_t CCGR80_CLR; /**< CCM Clock Gating Register, offset: 0x4508 */ - __IO uint32_t CCGR80_TOG; /**< CCM Clock Gating Register, offset: 0x450C */ - __IO uint32_t CCGR81; /**< CCM Clock Gating Register, offset: 0x4510 */ - __IO uint32_t CCGR81_SET; /**< CCM Clock Gating Register, offset: 0x4514 */ - __IO uint32_t CCGR81_CLR; /**< CCM Clock Gating Register, offset: 0x4518 */ - __IO uint32_t CCGR81_TOG; /**< CCM Clock Gating Register, offset: 0x451C */ - __IO uint32_t CCGR82; /**< CCM Clock Gating Register, offset: 0x4520 */ - __IO uint32_t CCGR82_SET; /**< CCM Clock Gating Register, offset: 0x4524 */ - __IO uint32_t CCGR82_CLR; /**< CCM Clock Gating Register, offset: 0x4528 */ - __IO uint32_t CCGR82_TOG; /**< CCM Clock Gating Register, offset: 0x452C */ - __IO uint32_t CCGR83; /**< CCM Clock Gating Register, offset: 0x4530 */ - __IO uint32_t CCGR83_SET; /**< CCM Clock Gating Register, offset: 0x4534 */ - __IO uint32_t CCGR83_CLR; /**< CCM Clock Gating Register, offset: 0x4538 */ - __IO uint32_t CCGR83_TOG; /**< CCM Clock Gating Register, offset: 0x453C */ - __IO uint32_t CCGR84; /**< CCM Clock Gating Register, offset: 0x4540 */ - __IO uint32_t CCGR84_SET; /**< CCM Clock Gating Register, offset: 0x4544 */ - __IO uint32_t CCGR84_CLR; /**< CCM Clock Gating Register, offset: 0x4548 */ - __IO uint32_t CCGR84_TOG; /**< CCM Clock Gating Register, offset: 0x454C */ - __IO uint32_t CCGR85; /**< CCM Clock Gating Register, offset: 0x4550 */ - __IO uint32_t CCGR85_SET; /**< CCM Clock Gating Register, offset: 0x4554 */ - __IO uint32_t CCGR85_CLR; /**< CCM Clock Gating Register, offset: 0x4558 */ - __IO uint32_t CCGR85_TOG; /**< CCM Clock Gating Register, offset: 0x455C */ - __IO uint32_t CCGR86; /**< CCM Clock Gating Register, offset: 0x4560 */ - __IO uint32_t CCGR86_SET; /**< CCM Clock Gating Register, offset: 0x4564 */ - __IO uint32_t CCGR86_CLR; /**< CCM Clock Gating Register, offset: 0x4568 */ - __IO uint32_t CCGR86_TOG; /**< CCM Clock Gating Register, offset: 0x456C */ - __IO uint32_t CCGR87; /**< CCM Clock Gating Register, offset: 0x4570 */ - __IO uint32_t CCGR87_SET; /**< CCM Clock Gating Register, offset: 0x4574 */ - __IO uint32_t CCGR87_CLR; /**< CCM Clock Gating Register, offset: 0x4578 */ - __IO uint32_t CCGR87_TOG; /**< CCM Clock Gating Register, offset: 0x457C */ - __IO uint32_t CCGR88; /**< CCM Clock Gating Register, offset: 0x4580 */ - __IO uint32_t CCGR88_SET; /**< CCM Clock Gating Register, offset: 0x4584 */ - __IO uint32_t CCGR88_CLR; /**< CCM Clock Gating Register, offset: 0x4588 */ - __IO uint32_t CCGR88_TOG; /**< CCM Clock Gating Register, offset: 0x458C */ - __IO uint32_t CCGR89; /**< CCM Clock Gating Register, offset: 0x4590 */ - __IO uint32_t CCGR89_SET; /**< CCM Clock Gating Register, offset: 0x4594 */ - __IO uint32_t CCGR89_CLR; /**< CCM Clock Gating Register, offset: 0x4598 */ - __IO uint32_t CCGR89_TOG; /**< CCM Clock Gating Register, offset: 0x459C */ - __IO uint32_t CCGR90; /**< CCM Clock Gating Register, offset: 0x45A0 */ - __IO uint32_t CCGR90_SET; /**< CCM Clock Gating Register, offset: 0x45A4 */ - __IO uint32_t CCGR90_CLR; /**< CCM Clock Gating Register, offset: 0x45A8 */ - __IO uint32_t CCGR90_TOG; /**< CCM Clock Gating Register, offset: 0x45AC */ - __IO uint32_t CCGR91; /**< CCM Clock Gating Register, offset: 0x45B0 */ - __IO uint32_t CCGR91_SET; /**< CCM Clock Gating Register, offset: 0x45B4 */ - __IO uint32_t CCGR91_CLR; /**< CCM Clock Gating Register, offset: 0x45B8 */ - __IO uint32_t CCGR91_TOG; /**< CCM Clock Gating Register, offset: 0x45BC */ - __IO uint32_t CCGR92; /**< CCM Clock Gating Register, offset: 0x45C0 */ - __IO uint32_t CCGR92_SET; /**< CCM Clock Gating Register, offset: 0x45C4 */ - __IO uint32_t CCGR92_CLR; /**< CCM Clock Gating Register, offset: 0x45C8 */ - __IO uint32_t CCGR92_TOG; /**< CCM Clock Gating Register, offset: 0x45CC */ - __IO uint32_t CCGR93; /**< CCM Clock Gating Register, offset: 0x45D0 */ - __IO uint32_t CCGR93_SET; /**< CCM Clock Gating Register, offset: 0x45D4 */ - __IO uint32_t CCGR93_CLR; /**< CCM Clock Gating Register, offset: 0x45D8 */ - __IO uint32_t CCGR93_TOG; /**< CCM Clock Gating Register, offset: 0x45DC */ - __IO uint32_t CCGR94; /**< CCM Clock Gating Register, offset: 0x45E0 */ - __IO uint32_t CCGR94_SET; /**< CCM Clock Gating Register, offset: 0x45E4 */ - __IO uint32_t CCGR94_CLR; /**< CCM Clock Gating Register, offset: 0x45E8 */ - __IO uint32_t CCGR94_TOG; /**< CCM Clock Gating Register, offset: 0x45EC */ - __IO uint32_t CCGR95; /**< CCM Clock Gating Register, offset: 0x45F0 */ - __IO uint32_t CCGR95_SET; /**< CCM Clock Gating Register, offset: 0x45F4 */ - __IO uint32_t CCGR95_CLR; /**< CCM Clock Gating Register, offset: 0x45F8 */ - __IO uint32_t CCGR95_TOG; /**< CCM Clock Gating Register, offset: 0x45FC */ - __IO uint32_t CCGR96; /**< CCM Clock Gating Register, offset: 0x4600 */ - __IO uint32_t CCGR96_SET; /**< CCM Clock Gating Register, offset: 0x4604 */ - __IO uint32_t CCGR96_CLR; /**< CCM Clock Gating Register, offset: 0x4608 */ - __IO uint32_t CCGR96_TOG; /**< CCM Clock Gating Register, offset: 0x460C */ - __IO uint32_t CCGR97; /**< CCM Clock Gating Register, offset: 0x4610 */ - __IO uint32_t CCGR97_SET; /**< CCM Clock Gating Register, offset: 0x4614 */ - __IO uint32_t CCGR97_CLR; /**< CCM Clock Gating Register, offset: 0x4618 */ - __IO uint32_t CCGR97_TOG; /**< CCM Clock Gating Register, offset: 0x461C */ - __IO uint32_t CCGR98; /**< CCM Clock Gating Register, offset: 0x4620 */ - __IO uint32_t CCGR98_SET; /**< CCM Clock Gating Register, offset: 0x4624 */ - __IO uint32_t CCGR98_CLR; /**< CCM Clock Gating Register, offset: 0x4628 */ - __IO uint32_t CCGR98_TOG; /**< CCM Clock Gating Register, offset: 0x462C */ - __IO uint32_t CCGR99; /**< CCM Clock Gating Register, offset: 0x4630 */ - __IO uint32_t CCGR99_SET; /**< CCM Clock Gating Register, offset: 0x4634 */ - __IO uint32_t CCGR99_CLR; /**< CCM Clock Gating Register, offset: 0x4638 */ - __IO uint32_t CCGR99_TOG; /**< CCM Clock Gating Register, offset: 0x463C */ - __IO uint32_t CCGR100; /**< CCM Clock Gating Register, offset: 0x4640 */ - __IO uint32_t CCGR100_SET; /**< CCM Clock Gating Register, offset: 0x4644 */ - __IO uint32_t CCGR100_CLR; /**< CCM Clock Gating Register, offset: 0x4648 */ - __IO uint32_t CCGR100_TOG; /**< CCM Clock Gating Register, offset: 0x464C */ - __IO uint32_t CCGR101; /**< CCM Clock Gating Register, offset: 0x4650 */ - __IO uint32_t CCGR101_SET; /**< CCM Clock Gating Register, offset: 0x4654 */ - __IO uint32_t CCGR101_CLR; /**< CCM Clock Gating Register, offset: 0x4658 */ - __IO uint32_t CCGR101_TOG; /**< CCM Clock Gating Register, offset: 0x465C */ - __IO uint32_t CCGR102; /**< CCM Clock Gating Register, offset: 0x4660 */ - __IO uint32_t CCGR102_SET; /**< CCM Clock Gating Register, offset: 0x4664 */ - __IO uint32_t CCGR102_CLR; /**< CCM Clock Gating Register, offset: 0x4668 */ - __IO uint32_t CCGR102_TOG; /**< CCM Clock Gating Register, offset: 0x466C */ - __IO uint32_t CCGR103; /**< CCM Clock Gating Register, offset: 0x4670 */ - __IO uint32_t CCGR103_SET; /**< CCM Clock Gating Register, offset: 0x4674 */ - __IO uint32_t CCGR103_CLR; /**< CCM Clock Gating Register, offset: 0x4678 */ - __IO uint32_t CCGR103_TOG; /**< CCM Clock Gating Register, offset: 0x467C */ - __IO uint32_t CCGR104; /**< CCM Clock Gating Register, offset: 0x4680 */ - __IO uint32_t CCGR104_SET; /**< CCM Clock Gating Register, offset: 0x4684 */ - __IO uint32_t CCGR104_CLR; /**< CCM Clock Gating Register, offset: 0x4688 */ - __IO uint32_t CCGR104_TOG; /**< CCM Clock Gating Register, offset: 0x468C */ - __IO uint32_t CCGR105; /**< CCM Clock Gating Register, offset: 0x4690 */ - __IO uint32_t CCGR105_SET; /**< CCM Clock Gating Register, offset: 0x4694 */ - __IO uint32_t CCGR105_CLR; /**< CCM Clock Gating Register, offset: 0x4698 */ - __IO uint32_t CCGR105_TOG; /**< CCM Clock Gating Register, offset: 0x469C */ - __IO uint32_t CCGR106; /**< CCM Clock Gating Register, offset: 0x46A0 */ - __IO uint32_t CCGR106_SET; /**< CCM Clock Gating Register, offset: 0x46A4 */ - __IO uint32_t CCGR106_CLR; /**< CCM Clock Gating Register, offset: 0x46A8 */ - __IO uint32_t CCGR106_TOG; /**< CCM Clock Gating Register, offset: 0x46AC */ - __IO uint32_t CCGR107; /**< CCM Clock Gating Register, offset: 0x46B0 */ - __IO uint32_t CCGR107_SET; /**< CCM Clock Gating Register, offset: 0x46B4 */ - __IO uint32_t CCGR107_CLR; /**< CCM Clock Gating Register, offset: 0x46B8 */ - __IO uint32_t CCGR107_TOG; /**< CCM Clock Gating Register, offset: 0x46BC */ - __IO uint32_t CCGR108; /**< CCM Clock Gating Register, offset: 0x46C0 */ - __IO uint32_t CCGR108_SET; /**< CCM Clock Gating Register, offset: 0x46C4 */ - __IO uint32_t CCGR108_CLR; /**< CCM Clock Gating Register, offset: 0x46C8 */ - __IO uint32_t CCGR108_TOG; /**< CCM Clock Gating Register, offset: 0x46CC */ - __IO uint32_t CCGR109; /**< CCM Clock Gating Register, offset: 0x46D0 */ - __IO uint32_t CCGR109_SET; /**< CCM Clock Gating Register, offset: 0x46D4 */ - __IO uint32_t CCGR109_CLR; /**< CCM Clock Gating Register, offset: 0x46D8 */ - __IO uint32_t CCGR109_TOG; /**< CCM Clock Gating Register, offset: 0x46DC */ - __IO uint32_t CCGR110; /**< CCM Clock Gating Register, offset: 0x46E0 */ - __IO uint32_t CCGR110_SET; /**< CCM Clock Gating Register, offset: 0x46E4 */ - __IO uint32_t CCGR110_CLR; /**< CCM Clock Gating Register, offset: 0x46E8 */ - __IO uint32_t CCGR110_TOG; /**< CCM Clock Gating Register, offset: 0x46EC */ - __IO uint32_t CCGR111; /**< CCM Clock Gating Register, offset: 0x46F0 */ - __IO uint32_t CCGR111_SET; /**< CCM Clock Gating Register, offset: 0x46F4 */ - __IO uint32_t CCGR111_CLR; /**< CCM Clock Gating Register, offset: 0x46F8 */ - __IO uint32_t CCGR111_TOG; /**< CCM Clock Gating Register, offset: 0x46FC */ - __IO uint32_t CCGR112; /**< CCM Clock Gating Register, offset: 0x4700 */ - __IO uint32_t CCGR112_SET; /**< CCM Clock Gating Register, offset: 0x4704 */ - __IO uint32_t CCGR112_CLR; /**< CCM Clock Gating Register, offset: 0x4708 */ - __IO uint32_t CCGR112_TOG; /**< CCM Clock Gating Register, offset: 0x470C */ - __IO uint32_t CCGR113; /**< CCM Clock Gating Register, offset: 0x4710 */ - __IO uint32_t CCGR113_SET; /**< CCM Clock Gating Register, offset: 0x4714 */ - __IO uint32_t CCGR113_CLR; /**< CCM Clock Gating Register, offset: 0x4718 */ - __IO uint32_t CCGR113_TOG; /**< CCM Clock Gating Register, offset: 0x471C */ - __IO uint32_t CCGR114; /**< CCM Clock Gating Register, offset: 0x4720 */ - __IO uint32_t CCGR114_SET; /**< CCM Clock Gating Register, offset: 0x4724 */ - __IO uint32_t CCGR114_CLR; /**< CCM Clock Gating Register, offset: 0x4728 */ - __IO uint32_t CCGR114_TOG; /**< CCM Clock Gating Register, offset: 0x472C */ - __IO uint32_t CCGR115; /**< CCM Clock Gating Register, offset: 0x4730 */ - __IO uint32_t CCGR115_SET; /**< CCM Clock Gating Register, offset: 0x4734 */ - __IO uint32_t CCGR115_CLR; /**< CCM Clock Gating Register, offset: 0x4738 */ - __IO uint32_t CCGR115_TOG; /**< CCM Clock Gating Register, offset: 0x473C */ - __IO uint32_t CCGR116; /**< CCM Clock Gating Register, offset: 0x4740 */ - __IO uint32_t CCGR116_SET; /**< CCM Clock Gating Register, offset: 0x4744 */ - __IO uint32_t CCGR116_CLR; /**< CCM Clock Gating Register, offset: 0x4748 */ - __IO uint32_t CCGR116_TOG; /**< CCM Clock Gating Register, offset: 0x474C */ - __IO uint32_t CCGR117; /**< CCM Clock Gating Register, offset: 0x4750 */ - __IO uint32_t CCGR117_SET; /**< CCM Clock Gating Register, offset: 0x4754 */ - __IO uint32_t CCGR117_CLR; /**< CCM Clock Gating Register, offset: 0x4758 */ - __IO uint32_t CCGR117_TOG; /**< CCM Clock Gating Register, offset: 0x475C */ - __IO uint32_t CCGR118; /**< CCM Clock Gating Register, offset: 0x4760 */ - __IO uint32_t CCGR118_SET; /**< CCM Clock Gating Register, offset: 0x4764 */ - __IO uint32_t CCGR118_CLR; /**< CCM Clock Gating Register, offset: 0x4768 */ - __IO uint32_t CCGR118_TOG; /**< CCM Clock Gating Register, offset: 0x476C */ - __IO uint32_t CCGR119; /**< CCM Clock Gating Register, offset: 0x4770 */ - __IO uint32_t CCGR119_SET; /**< CCM Clock Gating Register, offset: 0x4774 */ - __IO uint32_t CCGR119_CLR; /**< CCM Clock Gating Register, offset: 0x4778 */ - __IO uint32_t CCGR119_TOG; /**< CCM Clock Gating Register, offset: 0x477C */ - __IO uint32_t CCGR120; /**< CCM Clock Gating Register, offset: 0x4780 */ - __IO uint32_t CCGR120_SET; /**< CCM Clock Gating Register, offset: 0x4784 */ - __IO uint32_t CCGR120_CLR; /**< CCM Clock Gating Register, offset: 0x4788 */ - __IO uint32_t CCGR120_TOG; /**< CCM Clock Gating Register, offset: 0x478C */ - __IO uint32_t CCGR121; /**< CCM Clock Gating Register, offset: 0x4790 */ - __IO uint32_t CCGR121_SET; /**< CCM Clock Gating Register, offset: 0x4794 */ - __IO uint32_t CCGR121_CLR; /**< CCM Clock Gating Register, offset: 0x4798 */ - __IO uint32_t CCGR121_TOG; /**< CCM Clock Gating Register, offset: 0x479C */ - __IO uint32_t CCGR122; /**< CCM Clock Gating Register, offset: 0x47A0 */ - __IO uint32_t CCGR122_SET; /**< CCM Clock Gating Register, offset: 0x47A4 */ - __IO uint32_t CCGR122_CLR; /**< CCM Clock Gating Register, offset: 0x47A8 */ - __IO uint32_t CCGR122_TOG; /**< CCM Clock Gating Register, offset: 0x47AC */ - __IO uint32_t CCGR123; /**< CCM Clock Gating Register, offset: 0x47B0 */ - __IO uint32_t CCGR123_SET; /**< CCM Clock Gating Register, offset: 0x47B4 */ - __IO uint32_t CCGR123_CLR; /**< CCM Clock Gating Register, offset: 0x47B8 */ - __IO uint32_t CCGR123_TOG; /**< CCM Clock Gating Register, offset: 0x47BC */ - __IO uint32_t CCGR124; /**< CCM Clock Gating Register, offset: 0x47C0 */ - __IO uint32_t CCGR124_SET; /**< CCM Clock Gating Register, offset: 0x47C4 */ - __IO uint32_t CCGR124_CLR; /**< CCM Clock Gating Register, offset: 0x47C8 */ - __IO uint32_t CCGR124_TOG; /**< CCM Clock Gating Register, offset: 0x47CC */ - __IO uint32_t CCGR125; /**< CCM Clock Gating Register, offset: 0x47D0 */ - __IO uint32_t CCGR125_SET; /**< CCM Clock Gating Register, offset: 0x47D4 */ - __IO uint32_t CCGR125_CLR; /**< CCM Clock Gating Register, offset: 0x47D8 */ - __IO uint32_t CCGR125_TOG; /**< CCM Clock Gating Register, offset: 0x47DC */ - __IO uint32_t CCGR126; /**< CCM Clock Gating Register, offset: 0x47E0 */ - __IO uint32_t CCGR126_SET; /**< CCM Clock Gating Register, offset: 0x47E4 */ - __IO uint32_t CCGR126_CLR; /**< CCM Clock Gating Register, offset: 0x47E8 */ - __IO uint32_t CCGR126_TOG; /**< CCM Clock Gating Register, offset: 0x47EC */ - __IO uint32_t CCGR127; /**< CCM Clock Gating Register, offset: 0x47F0 */ - __IO uint32_t CCGR127_SET; /**< CCM Clock Gating Register, offset: 0x47F4 */ - __IO uint32_t CCGR127_CLR; /**< CCM Clock Gating Register, offset: 0x47F8 */ - __IO uint32_t CCGR127_TOG; /**< CCM Clock Gating Register, offset: 0x47FC */ - __IO uint32_t CCGR128; /**< CCM Clock Gating Register, offset: 0x4800 */ - __IO uint32_t CCGR128_SET; /**< CCM Clock Gating Register, offset: 0x4804 */ - __IO uint32_t CCGR128_CLR; /**< CCM Clock Gating Register, offset: 0x4808 */ - __IO uint32_t CCGR128_TOG; /**< CCM Clock Gating Register, offset: 0x480C */ - __IO uint32_t CCGR129; /**< CCM Clock Gating Register, offset: 0x4810 */ - __IO uint32_t CCGR129_SET; /**< CCM Clock Gating Register, offset: 0x4814 */ - __IO uint32_t CCGR129_CLR; /**< CCM Clock Gating Register, offset: 0x4818 */ - __IO uint32_t CCGR129_TOG; /**< CCM Clock Gating Register, offset: 0x481C */ - __IO uint32_t CCGR130; /**< CCM Clock Gating Register, offset: 0x4820 */ - __IO uint32_t CCGR130_SET; /**< CCM Clock Gating Register, offset: 0x4824 */ - __IO uint32_t CCGR130_CLR; /**< CCM Clock Gating Register, offset: 0x4828 */ - __IO uint32_t CCGR130_TOG; /**< CCM Clock Gating Register, offset: 0x482C */ - __IO uint32_t CCGR131; /**< CCM Clock Gating Register, offset: 0x4830 */ - __IO uint32_t CCGR131_SET; /**< CCM Clock Gating Register, offset: 0x4834 */ - __IO uint32_t CCGR131_CLR; /**< CCM Clock Gating Register, offset: 0x4838 */ - __IO uint32_t CCGR131_TOG; /**< CCM Clock Gating Register, offset: 0x483C */ - __IO uint32_t CCGR132; /**< CCM Clock Gating Register, offset: 0x4840 */ - __IO uint32_t CCGR132_SET; /**< CCM Clock Gating Register, offset: 0x4844 */ - __IO uint32_t CCGR132_CLR; /**< CCM Clock Gating Register, offset: 0x4848 */ - __IO uint32_t CCGR132_TOG; /**< CCM Clock Gating Register, offset: 0x484C */ - __IO uint32_t CCGR133; /**< CCM Clock Gating Register, offset: 0x4850 */ - __IO uint32_t CCGR133_SET; /**< CCM Clock Gating Register, offset: 0x4854 */ - __IO uint32_t CCGR133_CLR; /**< CCM Clock Gating Register, offset: 0x4858 */ - __IO uint32_t CCGR133_TOG; /**< CCM Clock Gating Register, offset: 0x485C */ - __IO uint32_t CCGR134; /**< CCM Clock Gating Register, offset: 0x4860 */ - __IO uint32_t CCGR134_SET; /**< CCM Clock Gating Register, offset: 0x4864 */ - __IO uint32_t CCGR134_CLR; /**< CCM Clock Gating Register, offset: 0x4868 */ - __IO uint32_t CCGR134_TOG; /**< CCM Clock Gating Register, offset: 0x486C */ - __IO uint32_t CCGR135; /**< CCM Clock Gating Register, offset: 0x4870 */ - __IO uint32_t CCGR135_SET; /**< CCM Clock Gating Register, offset: 0x4874 */ - __IO uint32_t CCGR135_CLR; /**< CCM Clock Gating Register, offset: 0x4878 */ - __IO uint32_t CCGR135_TOG; /**< CCM Clock Gating Register, offset: 0x487C */ - __IO uint32_t CCGR136; /**< CCM Clock Gating Register, offset: 0x4880 */ - __IO uint32_t CCGR136_SET; /**< CCM Clock Gating Register, offset: 0x4884 */ - __IO uint32_t CCGR136_CLR; /**< CCM Clock Gating Register, offset: 0x4888 */ - __IO uint32_t CCGR136_TOG; /**< CCM Clock Gating Register, offset: 0x488C */ - __IO uint32_t CCGR137; /**< CCM Clock Gating Register, offset: 0x4890 */ - __IO uint32_t CCGR137_SET; /**< CCM Clock Gating Register, offset: 0x4894 */ - __IO uint32_t CCGR137_CLR; /**< CCM Clock Gating Register, offset: 0x4898 */ - __IO uint32_t CCGR137_TOG; /**< CCM Clock Gating Register, offset: 0x489C */ - __IO uint32_t CCGR138; /**< CCM Clock Gating Register, offset: 0x48A0 */ - __IO uint32_t CCGR138_SET; /**< CCM Clock Gating Register, offset: 0x48A4 */ - __IO uint32_t CCGR138_CLR; /**< CCM Clock Gating Register, offset: 0x48A8 */ - __IO uint32_t CCGR138_TOG; /**< CCM Clock Gating Register, offset: 0x48AC */ - __IO uint32_t CCGR139; /**< CCM Clock Gating Register, offset: 0x48B0 */ - __IO uint32_t CCGR139_SET; /**< CCM Clock Gating Register, offset: 0x48B4 */ - __IO uint32_t CCGR139_CLR; /**< CCM Clock Gating Register, offset: 0x48B8 */ - __IO uint32_t CCGR139_TOG; /**< CCM Clock Gating Register, offset: 0x48BC */ - __IO uint32_t CCGR140; /**< CCM Clock Gating Register, offset: 0x48C0 */ - __IO uint32_t CCGR140_SET; /**< CCM Clock Gating Register, offset: 0x48C4 */ - __IO uint32_t CCGR140_CLR; /**< CCM Clock Gating Register, offset: 0x48C8 */ - __IO uint32_t CCGR140_TOG; /**< CCM Clock Gating Register, offset: 0x48CC */ - __IO uint32_t CCGR141; /**< CCM Clock Gating Register, offset: 0x48D0 */ - __IO uint32_t CCGR141_SET; /**< CCM Clock Gating Register, offset: 0x48D4 */ - __IO uint32_t CCGR141_CLR; /**< CCM Clock Gating Register, offset: 0x48D8 */ - __IO uint32_t CCGR141_TOG; /**< CCM Clock Gating Register, offset: 0x48DC */ - __IO uint32_t CCGR142; /**< CCM Clock Gating Register, offset: 0x48E0 */ - __IO uint32_t CCGR142_SET; /**< CCM Clock Gating Register, offset: 0x48E4 */ - __IO uint32_t CCGR142_CLR; /**< CCM Clock Gating Register, offset: 0x48E8 */ - __IO uint32_t CCGR142_TOG; /**< CCM Clock Gating Register, offset: 0x48EC */ - __IO uint32_t CCGR143; /**< CCM Clock Gating Register, offset: 0x48F0 */ - __IO uint32_t CCGR143_SET; /**< CCM Clock Gating Register, offset: 0x48F4 */ - __IO uint32_t CCGR143_CLR; /**< CCM Clock Gating Register, offset: 0x48F8 */ - __IO uint32_t CCGR143_TOG; /**< CCM Clock Gating Register, offset: 0x48FC */ - __IO uint32_t CCGR144; /**< CCM Clock Gating Register, offset: 0x4900 */ - __IO uint32_t CCGR144_SET; /**< CCM Clock Gating Register, offset: 0x4904 */ - __IO uint32_t CCGR144_CLR; /**< CCM Clock Gating Register, offset: 0x4908 */ - __IO uint32_t CCGR144_TOG; /**< CCM Clock Gating Register, offset: 0x490C */ - __IO uint32_t CCGR145; /**< CCM Clock Gating Register, offset: 0x4910 */ - __IO uint32_t CCGR145_SET; /**< CCM Clock Gating Register, offset: 0x4914 */ - __IO uint32_t CCGR145_CLR; /**< CCM Clock Gating Register, offset: 0x4918 */ - __IO uint32_t CCGR145_TOG; /**< CCM Clock Gating Register, offset: 0x491C */ - __IO uint32_t CCGR146; /**< CCM Clock Gating Register, offset: 0x4920 */ - __IO uint32_t CCGR146_SET; /**< CCM Clock Gating Register, offset: 0x4924 */ - __IO uint32_t CCGR146_CLR; /**< CCM Clock Gating Register, offset: 0x4928 */ - __IO uint32_t CCGR146_TOG; /**< CCM Clock Gating Register, offset: 0x492C */ - __IO uint32_t CCGR147; /**< CCM Clock Gating Register, offset: 0x4930 */ - __IO uint32_t CCGR147_SET; /**< CCM Clock Gating Register, offset: 0x4934 */ - __IO uint32_t CCGR147_CLR; /**< CCM Clock Gating Register, offset: 0x4938 */ - __IO uint32_t CCGR147_TOG; /**< CCM Clock Gating Register, offset: 0x493C */ - __IO uint32_t CCGR148; /**< CCM Clock Gating Register, offset: 0x4940 */ - __IO uint32_t CCGR148_SET; /**< CCM Clock Gating Register, offset: 0x4944 */ - __IO uint32_t CCGR148_CLR; /**< CCM Clock Gating Register, offset: 0x4948 */ - __IO uint32_t CCGR148_TOG; /**< CCM Clock Gating Register, offset: 0x494C */ - __IO uint32_t CCGR149; /**< CCM Clock Gating Register, offset: 0x4950 */ - __IO uint32_t CCGR149_SET; /**< CCM Clock Gating Register, offset: 0x4954 */ - __IO uint32_t CCGR149_CLR; /**< CCM Clock Gating Register, offset: 0x4958 */ - __IO uint32_t CCGR149_TOG; /**< CCM Clock Gating Register, offset: 0x495C */ - __IO uint32_t CCGR150; /**< CCM Clock Gating Register, offset: 0x4960 */ - __IO uint32_t CCGR150_SET; /**< CCM Clock Gating Register, offset: 0x4964 */ - __IO uint32_t CCGR150_CLR; /**< CCM Clock Gating Register, offset: 0x4968 */ - __IO uint32_t CCGR150_TOG; /**< CCM Clock Gating Register, offset: 0x496C */ - __IO uint32_t CCGR151; /**< CCM Clock Gating Register, offset: 0x4970 */ - __IO uint32_t CCGR151_SET; /**< CCM Clock Gating Register, offset: 0x4974 */ - __IO uint32_t CCGR151_CLR; /**< CCM Clock Gating Register, offset: 0x4978 */ - __IO uint32_t CCGR151_TOG; /**< CCM Clock Gating Register, offset: 0x497C */ - __IO uint32_t CCGR152; /**< CCM Clock Gating Register, offset: 0x4980 */ - __IO uint32_t CCGR152_SET; /**< CCM Clock Gating Register, offset: 0x4984 */ - __IO uint32_t CCGR152_CLR; /**< CCM Clock Gating Register, offset: 0x4988 */ - __IO uint32_t CCGR152_TOG; /**< CCM Clock Gating Register, offset: 0x498C */ - __IO uint32_t CCGR153; /**< CCM Clock Gating Register, offset: 0x4990 */ - __IO uint32_t CCGR153_SET; /**< CCM Clock Gating Register, offset: 0x4994 */ - __IO uint32_t CCGR153_CLR; /**< CCM Clock Gating Register, offset: 0x4998 */ - __IO uint32_t CCGR153_TOG; /**< CCM Clock Gating Register, offset: 0x499C */ - __IO uint32_t CCGR154; /**< CCM Clock Gating Register, offset: 0x49A0 */ - __IO uint32_t CCGR154_SET; /**< CCM Clock Gating Register, offset: 0x49A4 */ - __IO uint32_t CCGR154_CLR; /**< CCM Clock Gating Register, offset: 0x49A8 */ - __IO uint32_t CCGR154_TOG; /**< CCM Clock Gating Register, offset: 0x49AC */ - __IO uint32_t CCGR155; /**< CCM Clock Gating Register, offset: 0x49B0 */ - __IO uint32_t CCGR155_SET; /**< CCM Clock Gating Register, offset: 0x49B4 */ - __IO uint32_t CCGR155_CLR; /**< CCM Clock Gating Register, offset: 0x49B8 */ - __IO uint32_t CCGR155_TOG; /**< CCM Clock Gating Register, offset: 0x49BC */ - __IO uint32_t CCGR156; /**< CCM Clock Gating Register, offset: 0x49C0 */ - __IO uint32_t CCGR156_SET; /**< CCM Clock Gating Register, offset: 0x49C4 */ - __IO uint32_t CCGR156_CLR; /**< CCM Clock Gating Register, offset: 0x49C8 */ - __IO uint32_t CCGR156_TOG; /**< CCM Clock Gating Register, offset: 0x49CC */ - __IO uint32_t CCGR157; /**< CCM Clock Gating Register, offset: 0x49D0 */ - __IO uint32_t CCGR157_SET; /**< CCM Clock Gating Register, offset: 0x49D4 */ - __IO uint32_t CCGR157_CLR; /**< CCM Clock Gating Register, offset: 0x49D8 */ - __IO uint32_t CCGR157_TOG; /**< CCM Clock Gating Register, offset: 0x49DC */ - __IO uint32_t CCGR158; /**< CCM Clock Gating Register, offset: 0x49E0 */ - __IO uint32_t CCGR158_SET; /**< CCM Clock Gating Register, offset: 0x49E4 */ - __IO uint32_t CCGR158_CLR; /**< CCM Clock Gating Register, offset: 0x49E8 */ - __IO uint32_t CCGR158_TOG; /**< CCM Clock Gating Register, offset: 0x49EC */ - __IO uint32_t CCGR159; /**< CCM Clock Gating Register, offset: 0x49F0 */ - __IO uint32_t CCGR159_SET; /**< CCM Clock Gating Register, offset: 0x49F4 */ - __IO uint32_t CCGR159_CLR; /**< CCM Clock Gating Register, offset: 0x49F8 */ - __IO uint32_t CCGR159_TOG; /**< CCM Clock Gating Register, offset: 0x49FC */ - __IO uint32_t CCGR160; /**< CCM Clock Gating Register, offset: 0x4A00 */ - __IO uint32_t CCGR160_SET; /**< CCM Clock Gating Register, offset: 0x4A04 */ - __IO uint32_t CCGR160_CLR; /**< CCM Clock Gating Register, offset: 0x4A08 */ - __IO uint32_t CCGR160_TOG; /**< CCM Clock Gating Register, offset: 0x4A0C */ - __IO uint32_t CCGR161; /**< CCM Clock Gating Register, offset: 0x4A10 */ - __IO uint32_t CCGR161_SET; /**< CCM Clock Gating Register, offset: 0x4A14 */ - __IO uint32_t CCGR161_CLR; /**< CCM Clock Gating Register, offset: 0x4A18 */ - __IO uint32_t CCGR161_TOG; /**< CCM Clock Gating Register, offset: 0x4A1C */ - __IO uint32_t CCGR162; /**< CCM Clock Gating Register, offset: 0x4A20 */ - __IO uint32_t CCGR162_SET; /**< CCM Clock Gating Register, offset: 0x4A24 */ - __IO uint32_t CCGR162_CLR; /**< CCM Clock Gating Register, offset: 0x4A28 */ - __IO uint32_t CCGR162_TOG; /**< CCM Clock Gating Register, offset: 0x4A2C */ - __IO uint32_t CCGR163; /**< CCM Clock Gating Register, offset: 0x4A30 */ - __IO uint32_t CCGR163_SET; /**< CCM Clock Gating Register, offset: 0x4A34 */ - __IO uint32_t CCGR163_CLR; /**< CCM Clock Gating Register, offset: 0x4A38 */ - __IO uint32_t CCGR163_TOG; /**< CCM Clock Gating Register, offset: 0x4A3C */ - __IO uint32_t CCGR164; /**< CCM Clock Gating Register, offset: 0x4A40 */ - __IO uint32_t CCGR164_SET; /**< CCM Clock Gating Register, offset: 0x4A44 */ - __IO uint32_t CCGR164_CLR; /**< CCM Clock Gating Register, offset: 0x4A48 */ - __IO uint32_t CCGR164_TOG; /**< CCM Clock Gating Register, offset: 0x4A4C */ - __IO uint32_t CCGR165; /**< CCM Clock Gating Register, offset: 0x4A50 */ - __IO uint32_t CCGR165_SET; /**< CCM Clock Gating Register, offset: 0x4A54 */ - __IO uint32_t CCGR165_CLR; /**< CCM Clock Gating Register, offset: 0x4A58 */ - __IO uint32_t CCGR165_TOG; /**< CCM Clock Gating Register, offset: 0x4A5C */ - __IO uint32_t CCGR166; /**< CCM Clock Gating Register, offset: 0x4A60 */ - __IO uint32_t CCGR166_SET; /**< CCM Clock Gating Register, offset: 0x4A64 */ - __IO uint32_t CCGR166_CLR; /**< CCM Clock Gating Register, offset: 0x4A68 */ - __IO uint32_t CCGR166_TOG; /**< CCM Clock Gating Register, offset: 0x4A6C */ - __IO uint32_t CCGR167; /**< CCM Clock Gating Register, offset: 0x4A70 */ - __IO uint32_t CCGR167_SET; /**< CCM Clock Gating Register, offset: 0x4A74 */ - __IO uint32_t CCGR167_CLR; /**< CCM Clock Gating Register, offset: 0x4A78 */ - __IO uint32_t CCGR167_TOG; /**< CCM Clock Gating Register, offset: 0x4A7C */ - __IO uint32_t CCGR168; /**< CCM Clock Gating Register, offset: 0x4A80 */ - __IO uint32_t CCGR168_SET; /**< CCM Clock Gating Register, offset: 0x4A84 */ - __IO uint32_t CCGR168_CLR; /**< CCM Clock Gating Register, offset: 0x4A88 */ - __IO uint32_t CCGR168_TOG; /**< CCM Clock Gating Register, offset: 0x4A8C */ - __IO uint32_t CCGR169; /**< CCM Clock Gating Register, offset: 0x4A90 */ - __IO uint32_t CCGR169_SET; /**< CCM Clock Gating Register, offset: 0x4A94 */ - __IO uint32_t CCGR169_CLR; /**< CCM Clock Gating Register, offset: 0x4A98 */ - __IO uint32_t CCGR169_TOG; /**< CCM Clock Gating Register, offset: 0x4A9C */ - __IO uint32_t CCGR170; /**< CCM Clock Gating Register, offset: 0x4AA0 */ - __IO uint32_t CCGR170_SET; /**< CCM Clock Gating Register, offset: 0x4AA4 */ - __IO uint32_t CCGR170_CLR; /**< CCM Clock Gating Register, offset: 0x4AA8 */ - __IO uint32_t CCGR170_TOG; /**< CCM Clock Gating Register, offset: 0x4AAC */ - __IO uint32_t CCGR171; /**< CCM Clock Gating Register, offset: 0x4AB0 */ - __IO uint32_t CCGR171_SET; /**< CCM Clock Gating Register, offset: 0x4AB4 */ - __IO uint32_t CCGR171_CLR; /**< CCM Clock Gating Register, offset: 0x4AB8 */ - __IO uint32_t CCGR171_TOG; /**< CCM Clock Gating Register, offset: 0x4ABC */ - __IO uint32_t CCGR172; /**< CCM Clock Gating Register, offset: 0x4AC0 */ - __IO uint32_t CCGR172_SET; /**< CCM Clock Gating Register, offset: 0x4AC4 */ - __IO uint32_t CCGR172_CLR; /**< CCM Clock Gating Register, offset: 0x4AC8 */ - __IO uint32_t CCGR172_TOG; /**< CCM Clock Gating Register, offset: 0x4ACC */ - __IO uint32_t CCGR173; /**< CCM Clock Gating Register, offset: 0x4AD0 */ - __IO uint32_t CCGR173_SET; /**< CCM Clock Gating Register, offset: 0x4AD4 */ - __IO uint32_t CCGR173_CLR; /**< CCM Clock Gating Register, offset: 0x4AD8 */ - __IO uint32_t CCGR173_TOG; /**< CCM Clock Gating Register, offset: 0x4ADC */ - __IO uint32_t CCGR174; /**< CCM Clock Gating Register, offset: 0x4AE0 */ - __IO uint32_t CCGR174_SET; /**< CCM Clock Gating Register, offset: 0x4AE4 */ - __IO uint32_t CCGR174_CLR; /**< CCM Clock Gating Register, offset: 0x4AE8 */ - __IO uint32_t CCGR174_TOG; /**< CCM Clock Gating Register, offset: 0x4AEC */ - __IO uint32_t CCGR175; /**< CCM Clock Gating Register, offset: 0x4AF0 */ - __IO uint32_t CCGR175_SET; /**< CCM Clock Gating Register, offset: 0x4AF4 */ - __IO uint32_t CCGR175_CLR; /**< CCM Clock Gating Register, offset: 0x4AF8 */ - __IO uint32_t CCGR175_TOG; /**< CCM Clock Gating Register, offset: 0x4AFC */ - __IO uint32_t CCGR176; /**< CCM Clock Gating Register, offset: 0x4B00 */ - __IO uint32_t CCGR176_SET; /**< CCM Clock Gating Register, offset: 0x4B04 */ - __IO uint32_t CCGR176_CLR; /**< CCM Clock Gating Register, offset: 0x4B08 */ - __IO uint32_t CCGR176_TOG; /**< CCM Clock Gating Register, offset: 0x4B0C */ - __IO uint32_t CCGR177; /**< CCM Clock Gating Register, offset: 0x4B10 */ - __IO uint32_t CCGR177_SET; /**< CCM Clock Gating Register, offset: 0x4B14 */ - __IO uint32_t CCGR177_CLR; /**< CCM Clock Gating Register, offset: 0x4B18 */ - __IO uint32_t CCGR177_TOG; /**< CCM Clock Gating Register, offset: 0x4B1C */ - __IO uint32_t CCGR178; /**< CCM Clock Gating Register, offset: 0x4B20 */ - __IO uint32_t CCGR178_SET; /**< CCM Clock Gating Register, offset: 0x4B24 */ - __IO uint32_t CCGR178_CLR; /**< CCM Clock Gating Register, offset: 0x4B28 */ - __IO uint32_t CCGR178_TOG; /**< CCM Clock Gating Register, offset: 0x4B2C */ - __IO uint32_t CCGR179; /**< CCM Clock Gating Register, offset: 0x4B30 */ - __IO uint32_t CCGR179_SET; /**< CCM Clock Gating Register, offset: 0x4B34 */ - __IO uint32_t CCGR179_CLR; /**< CCM Clock Gating Register, offset: 0x4B38 */ - __IO uint32_t CCGR179_TOG; /**< CCM Clock Gating Register, offset: 0x4B3C */ - __IO uint32_t CCGR180; /**< CCM Clock Gating Register, offset: 0x4B40 */ - __IO uint32_t CCGR180_SET; /**< CCM Clock Gating Register, offset: 0x4B44 */ - __IO uint32_t CCGR180_CLR; /**< CCM Clock Gating Register, offset: 0x4B48 */ - __IO uint32_t CCGR180_TOG; /**< CCM Clock Gating Register, offset: 0x4B4C */ - __IO uint32_t CCGR181; /**< CCM Clock Gating Register, offset: 0x4B50 */ - __IO uint32_t CCGR181_SET; /**< CCM Clock Gating Register, offset: 0x4B54 */ - __IO uint32_t CCGR181_CLR; /**< CCM Clock Gating Register, offset: 0x4B58 */ - __IO uint32_t CCGR181_TOG; /**< CCM Clock Gating Register, offset: 0x4B5C */ - __IO uint32_t CCGR182; /**< CCM Clock Gating Register, offset: 0x4B60 */ - __IO uint32_t CCGR182_SET; /**< CCM Clock Gating Register, offset: 0x4B64 */ - __IO uint32_t CCGR182_CLR; /**< CCM Clock Gating Register, offset: 0x4B68 */ - __IO uint32_t CCGR182_TOG; /**< CCM Clock Gating Register, offset: 0x4B6C */ - __IO uint32_t CCGR183; /**< CCM Clock Gating Register, offset: 0x4B70 */ - __IO uint32_t CCGR183_SET; /**< CCM Clock Gating Register, offset: 0x4B74 */ - __IO uint32_t CCGR183_CLR; /**< CCM Clock Gating Register, offset: 0x4B78 */ - __IO uint32_t CCGR183_TOG; /**< CCM Clock Gating Register, offset: 0x4B7C */ - __IO uint32_t CCGR184; /**< CCM Clock Gating Register, offset: 0x4B80 */ - __IO uint32_t CCGR184_SET; /**< CCM Clock Gating Register, offset: 0x4B84 */ - __IO uint32_t CCGR184_CLR; /**< CCM Clock Gating Register, offset: 0x4B88 */ - __IO uint32_t CCGR184_TOG; /**< CCM Clock Gating Register, offset: 0x4B8C */ - __IO uint32_t CCGR185; /**< CCM Clock Gating Register, offset: 0x4B90 */ - __IO uint32_t CCGR185_SET; /**< CCM Clock Gating Register, offset: 0x4B94 */ - __IO uint32_t CCGR185_CLR; /**< CCM Clock Gating Register, offset: 0x4B98 */ - __IO uint32_t CCGR185_TOG; /**< CCM Clock Gating Register, offset: 0x4B9C */ - __IO uint32_t CCGR186; /**< CCM Clock Gating Register, offset: 0x4BA0 */ - __IO uint32_t CCGR186_SET; /**< CCM Clock Gating Register, offset: 0x4BA4 */ - __IO uint32_t CCGR186_CLR; /**< CCM Clock Gating Register, offset: 0x4BA8 */ - __IO uint32_t CCGR186_TOG; /**< CCM Clock Gating Register, offset: 0x4BAC */ - __IO uint32_t CCGR187; /**< CCM Clock Gating Register, offset: 0x4BB0 */ - __IO uint32_t CCGR187_SET; /**< CCM Clock Gating Register, offset: 0x4BB4 */ - __IO uint32_t CCGR187_CLR; /**< CCM Clock Gating Register, offset: 0x4BB8 */ - __IO uint32_t CCGR187_TOG; /**< CCM Clock Gating Register, offset: 0x4BBC */ - __IO uint32_t CCGR188; /**< CCM Clock Gating Register, offset: 0x4BC0 */ - __IO uint32_t CCGR188_SET; /**< CCM Clock Gating Register, offset: 0x4BC4 */ - __IO uint32_t CCGR188_CLR; /**< CCM Clock Gating Register, offset: 0x4BC8 */ - __IO uint32_t CCGR188_TOG; /**< CCM Clock Gating Register, offset: 0x4BCC */ - __IO uint32_t CCGR189; /**< CCM Clock Gating Register, offset: 0x4BD0 */ - __IO uint32_t CCGR189_SET; /**< CCM Clock Gating Register, offset: 0x4BD4 */ - __IO uint32_t CCGR189_CLR; /**< CCM Clock Gating Register, offset: 0x4BD8 */ - __IO uint32_t CCGR189_TOG; /**< CCM Clock Gating Register, offset: 0x4BDC */ - __IO uint32_t CCGR190; /**< CCM Clock Gating Register, offset: 0x4BE0 */ - __IO uint32_t CCGR190_SET; /**< CCM Clock Gating Register, offset: 0x4BE4 */ - __IO uint32_t CCGR190_CLR; /**< CCM Clock Gating Register, offset: 0x4BE8 */ - __IO uint32_t CCGR190_TOG; /**< CCM Clock Gating Register, offset: 0x4BEC */ - uint8_t RESERVED_1[13328]; - __IO uint32_t TARGET_ROOT0; /**< Target Register, offset: 0x8000 */ - __IO uint32_t TARGET_ROOT0_SET; /**< Target Register, offset: 0x8004 */ - __IO uint32_t TARGET_ROOT0_CLR; /**< Target Register, offset: 0x8008 */ - __IO uint32_t TARGET_ROOT0_TOG; /**< Target Register, offset: 0x800C */ - uint8_t RESERVED_2[16]; - __IO uint32_t POST0; /**< Post Divider Register, offset: 0x8020 */ - __IO uint32_t POST_ROOT0_SET; /**< Post Divider Register, offset: 0x8024 */ - __IO uint32_t POST_ROOT0_CLR; /**< Post Divider Register, offset: 0x8028 */ - __IO uint32_t POST_ROOT0_TOG; /**< Post Divider Register, offset: 0x802C */ - __IO uint32_t PRE0; /**< Pre Divider Register, offset: 0x8030 */ - __IO uint32_t PRE_ROOT0_SET; /**< Pre Divider Register, offset: 0x8034 */ - __IO uint32_t PRE_ROOT0_CLR; /**< Pre Divider Register, offset: 0x8038 */ - __IO uint32_t PRE_ROOT0_TOG; /**< Pre Divider Register, offset: 0x803C */ - uint8_t RESERVED_3[48]; - __IO uint32_t ACCESS_CTRL0; /**< Access Control Register, offset: 0x8070 */ - __IO uint32_t ACCESS_CTRL0_ROOT_SET; /**< Access Control Register, offset: 0x8074 */ - __IO uint32_t ACCESS_CTRL0_ROOT_CLR; /**< Access Control Register, offset: 0x8078 */ - __IO uint32_t ACCESS_CTRL0_ROOT_TOG; /**< Access Control Register, offset: 0x807C */ - __IO uint32_t TARGET_ROOT1; /**< Target Register, offset: 0x8080 */ - __IO uint32_t TARGET_ROOT1_SET; /**< Target Register, offset: 0x8084 */ - __IO uint32_t TARGET_ROOT1_CLR; /**< Target Register, offset: 0x8088 */ - __IO uint32_t TARGET_ROOT1_TOG; /**< Target Register, offset: 0x808C */ - uint8_t RESERVED_4[16]; - __IO uint32_t POST1; /**< Post Divider Register, offset: 0x80A0 */ - __IO uint32_t POST_ROOT1_SET; /**< Post Divider Register, offset: 0x80A4 */ - __IO uint32_t POST_ROOT1_CLR; /**< Post Divider Register, offset: 0x80A8 */ - __IO uint32_t POST_ROOT1_TOG; /**< Post Divider Register, offset: 0x80AC */ - __IO uint32_t PRE1; /**< Pre Divider Register, offset: 0x80B0 */ - __IO uint32_t PRE_ROOT1_SET; /**< Pre Divider Register, offset: 0x80B4 */ - __IO uint32_t PRE_ROOT1_CLR; /**< Pre Divider Register, offset: 0x80B8 */ - __IO uint32_t PRE_ROOT1_TOG; /**< Pre Divider Register, offset: 0x80BC */ - uint8_t RESERVED_5[48]; - __IO uint32_t ACCESS_CTRL1; /**< Access Control Register, offset: 0x80F0 */ - __IO uint32_t ACCESS_CTRL1_ROOT_SET; /**< Access Control Register, offset: 0x80F4 */ - __IO uint32_t ACCESS_CTRL1_ROOT_CLR; /**< Access Control Register, offset: 0x80F8 */ - __IO uint32_t ACCESS_CTRL1_ROOT_TOG; /**< Access Control Register, offset: 0x80FC */ - __IO uint32_t TARGET_ROOT2; /**< Target Register, offset: 0x8100 */ - __IO uint32_t TARGET_ROOT2_SET; /**< Target Register, offset: 0x8104 */ - __IO uint32_t TARGET_ROOT2_CLR; /**< Target Register, offset: 0x8108 */ - __IO uint32_t TARGET_ROOT2_TOG; /**< Target Register, offset: 0x810C */ - uint8_t RESERVED_6[16]; - __IO uint32_t POST2; /**< Post Divider Register, offset: 0x8120 */ - __IO uint32_t POST_ROOT2_SET; /**< Post Divider Register, offset: 0x8124 */ - __IO uint32_t POST_ROOT2_CLR; /**< Post Divider Register, offset: 0x8128 */ - __IO uint32_t POST_ROOT2_TOG; /**< Post Divider Register, offset: 0x812C */ - __IO uint32_t PRE2; /**< Pre Divider Register, offset: 0x8130 */ - __IO uint32_t PRE_ROOT2_SET; /**< Pre Divider Register, offset: 0x8134 */ - __IO uint32_t PRE_ROOT2_CLR; /**< Pre Divider Register, offset: 0x8138 */ - __IO uint32_t PRE_ROOT2_TOG; /**< Pre Divider Register, offset: 0x813C */ - uint8_t RESERVED_7[48]; - __IO uint32_t ACCESS_CTRL2; /**< Access Control Register, offset: 0x8170 */ - __IO uint32_t ACCESS_CTRL2_ROOT_SET; /**< Access Control Register, offset: 0x8174 */ - __IO uint32_t ACCESS_CTRL2_ROOT_CLR; /**< Access Control Register, offset: 0x8178 */ - __IO uint32_t ACCESS_CTRL2_ROOT_TOG; /**< Access Control Register, offset: 0x817C */ - __IO uint32_t TARGET_ROOT3; /**< Target Register, offset: 0x8180 */ - __IO uint32_t TARGET_ROOT3_SET; /**< Target Register, offset: 0x8184 */ - __IO uint32_t TARGET_ROOT3_CLR; /**< Target Register, offset: 0x8188 */ - __IO uint32_t TARGET_ROOT3_TOG; /**< Target Register, offset: 0x818C */ - uint8_t RESERVED_8[16]; - __IO uint32_t POST3; /**< Post Divider Register, offset: 0x81A0 */ - __IO uint32_t POST_ROOT3_SET; /**< Post Divider Register, offset: 0x81A4 */ - __IO uint32_t POST_ROOT3_CLR; /**< Post Divider Register, offset: 0x81A8 */ - __IO uint32_t POST_ROOT3_TOG; /**< Post Divider Register, offset: 0x81AC */ - __IO uint32_t PRE3; /**< Pre Divider Register, offset: 0x81B0 */ - __IO uint32_t PRE_ROOT3_SET; /**< Pre Divider Register, offset: 0x81B4 */ - __IO uint32_t PRE_ROOT3_CLR; /**< Pre Divider Register, offset: 0x81B8 */ - __IO uint32_t PRE_ROOT3_TOG; /**< Pre Divider Register, offset: 0x81BC */ - uint8_t RESERVED_9[48]; - __IO uint32_t ACCESS_CTRL3; /**< Access Control Register, offset: 0x81F0 */ - __IO uint32_t ACCESS_CTRL3_ROOT_SET; /**< Access Control Register, offset: 0x81F4 */ - __IO uint32_t ACCESS_CTRL3_ROOT_CLR; /**< Access Control Register, offset: 0x81F8 */ - __IO uint32_t ACCESS_CTRL3_ROOT_TOG; /**< Access Control Register, offset: 0x81FC */ - __IO uint32_t TARGET_ROOT4; /**< Target Register, offset: 0x8200 */ - __IO uint32_t TARGET_ROOT4_SET; /**< Target Register, offset: 0x8204 */ - __IO uint32_t TARGET_ROOT4_CLR; /**< Target Register, offset: 0x8208 */ - __IO uint32_t TARGET_ROOT4_TOG; /**< Target Register, offset: 0x820C */ - uint8_t RESERVED_10[16]; - __IO uint32_t POST4; /**< Post Divider Register, offset: 0x8220 */ - __IO uint32_t POST_ROOT4_SET; /**< Post Divider Register, offset: 0x8224 */ - __IO uint32_t POST_ROOT4_CLR; /**< Post Divider Register, offset: 0x8228 */ - __IO uint32_t POST_ROOT4_TOG; /**< Post Divider Register, offset: 0x822C */ - __IO uint32_t PRE4; /**< Pre Divider Register, offset: 0x8230 */ - __IO uint32_t PRE_ROOT4_SET; /**< Pre Divider Register, offset: 0x8234 */ - __IO uint32_t PRE_ROOT4_CLR; /**< Pre Divider Register, offset: 0x8238 */ - __IO uint32_t PRE_ROOT4_TOG; /**< Pre Divider Register, offset: 0x823C */ - uint8_t RESERVED_11[48]; - __IO uint32_t ACCESS_CTRL4; /**< Access Control Register, offset: 0x8270 */ - __IO uint32_t ACCESS_CTRL4_ROOT_SET; /**< Access Control Register, offset: 0x8274 */ - __IO uint32_t ACCESS_CTRL4_ROOT_CLR; /**< Access Control Register, offset: 0x8278 */ - __IO uint32_t ACCESS_CTRL4_ROOT_TOG; /**< Access Control Register, offset: 0x827C */ - __IO uint32_t TARGET_ROOT5; /**< Target Register, offset: 0x8280 */ - __IO uint32_t TARGET_ROOT5_SET; /**< Target Register, offset: 0x8284 */ - __IO uint32_t TARGET_ROOT5_CLR; /**< Target Register, offset: 0x8288 */ - __IO uint32_t TARGET_ROOT5_TOG; /**< Target Register, offset: 0x828C */ - uint8_t RESERVED_12[16]; - __IO uint32_t POST5; /**< Post Divider Register, offset: 0x82A0 */ - __IO uint32_t POST_ROOT5_SET; /**< Post Divider Register, offset: 0x82A4 */ - __IO uint32_t POST_ROOT5_CLR; /**< Post Divider Register, offset: 0x82A8 */ - __IO uint32_t POST_ROOT5_TOG; /**< Post Divider Register, offset: 0x82AC */ - __IO uint32_t PRE5; /**< Pre Divider Register, offset: 0x82B0 */ - __IO uint32_t PRE_ROOT5_SET; /**< Pre Divider Register, offset: 0x82B4 */ - __IO uint32_t PRE_ROOT5_CLR; /**< Pre Divider Register, offset: 0x82B8 */ - __IO uint32_t PRE_ROOT5_TOG; /**< Pre Divider Register, offset: 0x82BC */ - uint8_t RESERVED_13[48]; - __IO uint32_t ACCESS_CTRL5; /**< Access Control Register, offset: 0x82F0 */ - __IO uint32_t ACCESS_CTRL5_ROOT_SET; /**< Access Control Register, offset: 0x82F4 */ - __IO uint32_t ACCESS_CTRL5_ROOT_CLR; /**< Access Control Register, offset: 0x82F8 */ - __IO uint32_t ACCESS_CTRL5_ROOT_TOG; /**< Access Control Register, offset: 0x82FC */ - __IO uint32_t TARGET_ROOT6; /**< Target Register, offset: 0x8300 */ - __IO uint32_t TARGET_ROOT6_SET; /**< Target Register, offset: 0x8304 */ - __IO uint32_t TARGET_ROOT6_CLR; /**< Target Register, offset: 0x8308 */ - __IO uint32_t TARGET_ROOT6_TOG; /**< Target Register, offset: 0x830C */ - uint8_t RESERVED_14[16]; - __IO uint32_t POST6; /**< Post Divider Register, offset: 0x8320 */ - __IO uint32_t POST_ROOT6_SET; /**< Post Divider Register, offset: 0x8324 */ - __IO uint32_t POST_ROOT6_CLR; /**< Post Divider Register, offset: 0x8328 */ - __IO uint32_t POST_ROOT6_TOG; /**< Post Divider Register, offset: 0x832C */ - __IO uint32_t PRE6; /**< Pre Divider Register, offset: 0x8330 */ - __IO uint32_t PRE_ROOT6_SET; /**< Pre Divider Register, offset: 0x8334 */ - __IO uint32_t PRE_ROOT6_CLR; /**< Pre Divider Register, offset: 0x8338 */ - __IO uint32_t PRE_ROOT6_TOG; /**< Pre Divider Register, offset: 0x833C */ - uint8_t RESERVED_15[48]; - __IO uint32_t ACCESS_CTRL6; /**< Access Control Register, offset: 0x8370 */ - __IO uint32_t ACCESS_CTRL6_ROOT_SET; /**< Access Control Register, offset: 0x8374 */ - __IO uint32_t ACCESS_CTRL6_ROOT_CLR; /**< Access Control Register, offset: 0x8378 */ - __IO uint32_t ACCESS_CTRL6_ROOT_TOG; /**< Access Control Register, offset: 0x837C */ - __IO uint32_t TARGET_ROOT7; /**< Target Register, offset: 0x8380 */ - __IO uint32_t TARGET_ROOT7_SET; /**< Target Register, offset: 0x8384 */ - __IO uint32_t TARGET_ROOT7_CLR; /**< Target Register, offset: 0x8388 */ - __IO uint32_t TARGET_ROOT7_TOG; /**< Target Register, offset: 0x838C */ - uint8_t RESERVED_16[16]; - __IO uint32_t POST7; /**< Post Divider Register, offset: 0x83A0 */ - __IO uint32_t POST_ROOT7_SET; /**< Post Divider Register, offset: 0x83A4 */ - __IO uint32_t POST_ROOT7_CLR; /**< Post Divider Register, offset: 0x83A8 */ - __IO uint32_t POST_ROOT7_TOG; /**< Post Divider Register, offset: 0x83AC */ - __IO uint32_t PRE7; /**< Pre Divider Register, offset: 0x83B0 */ - __IO uint32_t PRE_ROOT7_SET; /**< Pre Divider Register, offset: 0x83B4 */ - __IO uint32_t PRE_ROOT7_CLR; /**< Pre Divider Register, offset: 0x83B8 */ - __IO uint32_t PRE_ROOT7_TOG; /**< Pre Divider Register, offset: 0x83BC */ - uint8_t RESERVED_17[48]; - __IO uint32_t ACCESS_CTRL7; /**< Access Control Register, offset: 0x83F0 */ - __IO uint32_t ACCESS_CTRL7_ROOT_SET; /**< Access Control Register, offset: 0x83F4 */ - __IO uint32_t ACCESS_CTRL7_ROOT_CLR; /**< Access Control Register, offset: 0x83F8 */ - __IO uint32_t ACCESS_CTRL7_ROOT_TOG; /**< Access Control Register, offset: 0x83FC */ - __IO uint32_t TARGET_ROOT8; /**< Target Register, offset: 0x8400 */ - __IO uint32_t TARGET_ROOT8_SET; /**< Target Register, offset: 0x8404 */ - __IO uint32_t TARGET_ROOT8_CLR; /**< Target Register, offset: 0x8408 */ - __IO uint32_t TARGET_ROOT8_TOG; /**< Target Register, offset: 0x840C */ - uint8_t RESERVED_18[16]; - __IO uint32_t POST8; /**< Post Divider Register, offset: 0x8420 */ - __IO uint32_t POST_ROOT8_SET; /**< Post Divider Register, offset: 0x8424 */ - __IO uint32_t POST_ROOT8_CLR; /**< Post Divider Register, offset: 0x8428 */ - __IO uint32_t POST_ROOT8_TOG; /**< Post Divider Register, offset: 0x842C */ - __IO uint32_t PRE8; /**< Pre Divider Register, offset: 0x8430 */ - __IO uint32_t PRE_ROOT8_SET; /**< Pre Divider Register, offset: 0x8434 */ - __IO uint32_t PRE_ROOT8_CLR; /**< Pre Divider Register, offset: 0x8438 */ - __IO uint32_t PRE_ROOT8_TOG; /**< Pre Divider Register, offset: 0x843C */ - uint8_t RESERVED_19[48]; - __IO uint32_t ACCESS_CTRL8; /**< Access Control Register, offset: 0x8470 */ - __IO uint32_t ACCESS_CTRL8_ROOT_SET; /**< Access Control Register, offset: 0x8474 */ - __IO uint32_t ACCESS_CTRL8_ROOT_CLR; /**< Access Control Register, offset: 0x8478 */ - __IO uint32_t ACCESS_CTRL8_ROOT_TOG; /**< Access Control Register, offset: 0x847C */ - __IO uint32_t TARGET_ROOT9; /**< Target Register, offset: 0x8480 */ - __IO uint32_t TARGET_ROOT9_SET; /**< Target Register, offset: 0x8484 */ - __IO uint32_t TARGET_ROOT9_CLR; /**< Target Register, offset: 0x8488 */ - __IO uint32_t TARGET_ROOT9_TOG; /**< Target Register, offset: 0x848C */ - uint8_t RESERVED_20[16]; - __IO uint32_t POST9; /**< Post Divider Register, offset: 0x84A0 */ - __IO uint32_t POST_ROOT9_SET; /**< Post Divider Register, offset: 0x84A4 */ - __IO uint32_t POST_ROOT9_CLR; /**< Post Divider Register, offset: 0x84A8 */ - __IO uint32_t POST_ROOT9_TOG; /**< Post Divider Register, offset: 0x84AC */ - __IO uint32_t PRE9; /**< Pre Divider Register, offset: 0x84B0 */ - __IO uint32_t PRE_ROOT9_SET; /**< Pre Divider Register, offset: 0x84B4 */ - __IO uint32_t PRE_ROOT9_CLR; /**< Pre Divider Register, offset: 0x84B8 */ - __IO uint32_t PRE_ROOT9_TOG; /**< Pre Divider Register, offset: 0x84BC */ - uint8_t RESERVED_21[48]; - __IO uint32_t ACCESS_CTRL9; /**< Access Control Register, offset: 0x84F0 */ - __IO uint32_t ACCESS_CTRL9_ROOT_SET; /**< Access Control Register, offset: 0x84F4 */ - __IO uint32_t ACCESS_CTRL9_ROOT_CLR; /**< Access Control Register, offset: 0x84F8 */ - __IO uint32_t ACCESS_CTRL9_ROOT_TOG; /**< Access Control Register, offset: 0x84FC */ - __IO uint32_t TARGET_ROOT10; /**< Target Register, offset: 0x8500 */ - __IO uint32_t TARGET_ROOT10_SET; /**< Target Register, offset: 0x8504 */ - __IO uint32_t TARGET_ROOT10_CLR; /**< Target Register, offset: 0x8508 */ - __IO uint32_t TARGET_ROOT10_TOG; /**< Target Register, offset: 0x850C */ - uint8_t RESERVED_22[16]; - __IO uint32_t POST10; /**< Post Divider Register, offset: 0x8520 */ - __IO uint32_t POST_ROOT10_SET; /**< Post Divider Register, offset: 0x8524 */ - __IO uint32_t POST_ROOT10_CLR; /**< Post Divider Register, offset: 0x8528 */ - __IO uint32_t POST_ROOT10_TOG; /**< Post Divider Register, offset: 0x852C */ - __IO uint32_t PRE10; /**< Pre Divider Register, offset: 0x8530 */ - __IO uint32_t PRE_ROOT10_SET; /**< Pre Divider Register, offset: 0x8534 */ - __IO uint32_t PRE_ROOT10_CLR; /**< Pre Divider Register, offset: 0x8538 */ - __IO uint32_t PRE_ROOT10_TOG; /**< Pre Divider Register, offset: 0x853C */ - uint8_t RESERVED_23[48]; - __IO uint32_t ACCESS_CTRL10; /**< Access Control Register, offset: 0x8570 */ - __IO uint32_t ACCESS_CTRL10_ROOT_SET; /**< Access Control Register, offset: 0x8574 */ - __IO uint32_t ACCESS_CTRL10_ROOT_CLR; /**< Access Control Register, offset: 0x8578 */ - __IO uint32_t ACCESS_CTRL10_ROOT_TOG; /**< Access Control Register, offset: 0x857C */ - __IO uint32_t TARGET_ROOT11; /**< Target Register, offset: 0x8580 */ - __IO uint32_t TARGET_ROOT11_SET; /**< Target Register, offset: 0x8584 */ - __IO uint32_t TARGET_ROOT11_CLR; /**< Target Register, offset: 0x8588 */ - __IO uint32_t TARGET_ROOT11_TOG; /**< Target Register, offset: 0x858C */ - uint8_t RESERVED_24[16]; - __IO uint32_t POST11; /**< Post Divider Register, offset: 0x85A0 */ - __IO uint32_t POST_ROOT11_SET; /**< Post Divider Register, offset: 0x85A4 */ - __IO uint32_t POST_ROOT11_CLR; /**< Post Divider Register, offset: 0x85A8 */ - __IO uint32_t POST_ROOT11_TOG; /**< Post Divider Register, offset: 0x85AC */ - __IO uint32_t PRE11; /**< Pre Divider Register, offset: 0x85B0 */ - __IO uint32_t PRE_ROOT11_SET; /**< Pre Divider Register, offset: 0x85B4 */ - __IO uint32_t PRE_ROOT11_CLR; /**< Pre Divider Register, offset: 0x85B8 */ - __IO uint32_t PRE_ROOT11_TOG; /**< Pre Divider Register, offset: 0x85BC */ - uint8_t RESERVED_25[48]; - __IO uint32_t ACCESS_CTRL11; /**< Access Control Register, offset: 0x85F0 */ - __IO uint32_t ACCESS_CTRL11_ROOT_SET; /**< Access Control Register, offset: 0x85F4 */ - __IO uint32_t ACCESS_CTRL11_ROOT_CLR; /**< Access Control Register, offset: 0x85F8 */ - __IO uint32_t ACCESS_CTRL11_ROOT_TOG; /**< Access Control Register, offset: 0x85FC */ - __IO uint32_t TARGET_ROOT12; /**< Target Register, offset: 0x8600 */ - __IO uint32_t TARGET_ROOT12_SET; /**< Target Register, offset: 0x8604 */ - __IO uint32_t TARGET_ROOT12_CLR; /**< Target Register, offset: 0x8608 */ - __IO uint32_t TARGET_ROOT12_TOG; /**< Target Register, offset: 0x860C */ - uint8_t RESERVED_26[16]; - __IO uint32_t POST12; /**< Post Divider Register, offset: 0x8620 */ - __IO uint32_t POST_ROOT12_SET; /**< Post Divider Register, offset: 0x8624 */ - __IO uint32_t POST_ROOT12_CLR; /**< Post Divider Register, offset: 0x8628 */ - __IO uint32_t POST_ROOT12_TOG; /**< Post Divider Register, offset: 0x862C */ - __IO uint32_t PRE12; /**< Pre Divider Register, offset: 0x8630 */ - __IO uint32_t PRE_ROOT12_SET; /**< Pre Divider Register, offset: 0x8634 */ - __IO uint32_t PRE_ROOT12_CLR; /**< Pre Divider Register, offset: 0x8638 */ - __IO uint32_t PRE_ROOT12_TOG; /**< Pre Divider Register, offset: 0x863C */ - uint8_t RESERVED_27[48]; - __IO uint32_t ACCESS_CTRL12; /**< Access Control Register, offset: 0x8670 */ - __IO uint32_t ACCESS_CTRL12_ROOT_SET; /**< Access Control Register, offset: 0x8674 */ - __IO uint32_t ACCESS_CTRL12_ROOT_CLR; /**< Access Control Register, offset: 0x8678 */ - __IO uint32_t ACCESS_CTRL12_ROOT_TOG; /**< Access Control Register, offset: 0x867C */ - __IO uint32_t TARGET_ROOT13; /**< Target Register, offset: 0x8680 */ - __IO uint32_t TARGET_ROOT13_SET; /**< Target Register, offset: 0x8684 */ - __IO uint32_t TARGET_ROOT13_CLR; /**< Target Register, offset: 0x8688 */ - __IO uint32_t TARGET_ROOT13_TOG; /**< Target Register, offset: 0x868C */ - uint8_t RESERVED_28[16]; - __IO uint32_t POST13; /**< Post Divider Register, offset: 0x86A0 */ - __IO uint32_t POST_ROOT13_SET; /**< Post Divider Register, offset: 0x86A4 */ - __IO uint32_t POST_ROOT13_CLR; /**< Post Divider Register, offset: 0x86A8 */ - __IO uint32_t POST_ROOT13_TOG; /**< Post Divider Register, offset: 0x86AC */ - __IO uint32_t PRE13; /**< Pre Divider Register, offset: 0x86B0 */ - __IO uint32_t PRE_ROOT13_SET; /**< Pre Divider Register, offset: 0x86B4 */ - __IO uint32_t PRE_ROOT13_CLR; /**< Pre Divider Register, offset: 0x86B8 */ - __IO uint32_t PRE_ROOT13_TOG; /**< Pre Divider Register, offset: 0x86BC */ - uint8_t RESERVED_29[48]; - __IO uint32_t ACCESS_CTRL13; /**< Access Control Register, offset: 0x86F0 */ - __IO uint32_t ACCESS_CTRL13_ROOT_SET; /**< Access Control Register, offset: 0x86F4 */ - __IO uint32_t ACCESS_CTRL13_ROOT_CLR; /**< Access Control Register, offset: 0x86F8 */ - __IO uint32_t ACCESS_CTRL13_ROOT_TOG; /**< Access Control Register, offset: 0x86FC */ - __IO uint32_t TARGET_ROOT14; /**< Target Register, offset: 0x8700 */ - __IO uint32_t TARGET_ROOT14_SET; /**< Target Register, offset: 0x8704 */ - __IO uint32_t TARGET_ROOT14_CLR; /**< Target Register, offset: 0x8708 */ - __IO uint32_t TARGET_ROOT14_TOG; /**< Target Register, offset: 0x870C */ - uint8_t RESERVED_30[16]; - __IO uint32_t POST14; /**< Post Divider Register, offset: 0x8720 */ - __IO uint32_t POST_ROOT14_SET; /**< Post Divider Register, offset: 0x8724 */ - __IO uint32_t POST_ROOT14_CLR; /**< Post Divider Register, offset: 0x8728 */ - __IO uint32_t POST_ROOT14_TOG; /**< Post Divider Register, offset: 0x872C */ - __IO uint32_t PRE14; /**< Pre Divider Register, offset: 0x8730 */ - __IO uint32_t PRE_ROOT14_SET; /**< Pre Divider Register, offset: 0x8734 */ - __IO uint32_t PRE_ROOT14_CLR; /**< Pre Divider Register, offset: 0x8738 */ - __IO uint32_t PRE_ROOT14_TOG; /**< Pre Divider Register, offset: 0x873C */ - uint8_t RESERVED_31[48]; - __IO uint32_t ACCESS_CTRL14; /**< Access Control Register, offset: 0x8770 */ - __IO uint32_t ACCESS_CTRL14_ROOT_SET; /**< Access Control Register, offset: 0x8774 */ - __IO uint32_t ACCESS_CTRL14_ROOT_CLR; /**< Access Control Register, offset: 0x8778 */ - __IO uint32_t ACCESS_CTRL14_ROOT_TOG; /**< Access Control Register, offset: 0x877C */ - __IO uint32_t TARGET_ROOT15; /**< Target Register, offset: 0x8780 */ - __IO uint32_t TARGET_ROOT15_SET; /**< Target Register, offset: 0x8784 */ - __IO uint32_t TARGET_ROOT15_CLR; /**< Target Register, offset: 0x8788 */ - __IO uint32_t TARGET_ROOT15_TOG; /**< Target Register, offset: 0x878C */ - uint8_t RESERVED_32[16]; - __IO uint32_t POST15; /**< Post Divider Register, offset: 0x87A0 */ - __IO uint32_t POST_ROOT15_SET; /**< Post Divider Register, offset: 0x87A4 */ - __IO uint32_t POST_ROOT15_CLR; /**< Post Divider Register, offset: 0x87A8 */ - __IO uint32_t POST_ROOT15_TOG; /**< Post Divider Register, offset: 0x87AC */ - __IO uint32_t PRE15; /**< Pre Divider Register, offset: 0x87B0 */ - __IO uint32_t PRE_ROOT15_SET; /**< Pre Divider Register, offset: 0x87B4 */ - __IO uint32_t PRE_ROOT15_CLR; /**< Pre Divider Register, offset: 0x87B8 */ - __IO uint32_t PRE_ROOT15_TOG; /**< Pre Divider Register, offset: 0x87BC */ - uint8_t RESERVED_33[48]; - __IO uint32_t ACCESS_CTRL15; /**< Access Control Register, offset: 0x87F0 */ - __IO uint32_t ACCESS_CTRL15_ROOT_SET; /**< Access Control Register, offset: 0x87F4 */ - __IO uint32_t ACCESS_CTRL15_ROOT_CLR; /**< Access Control Register, offset: 0x87F8 */ - __IO uint32_t ACCESS_CTRL15_ROOT_TOG; /**< Access Control Register, offset: 0x87FC */ - __IO uint32_t TARGET_ROOT16; /**< Target Register, offset: 0x8800 */ - __IO uint32_t TARGET_ROOT16_SET; /**< Target Register, offset: 0x8804 */ - __IO uint32_t TARGET_ROOT16_CLR; /**< Target Register, offset: 0x8808 */ - __IO uint32_t TARGET_ROOT16_TOG; /**< Target Register, offset: 0x880C */ - uint8_t RESERVED_34[16]; - __IO uint32_t POST16; /**< Post Divider Register, offset: 0x8820 */ - __IO uint32_t POST_ROOT16_SET; /**< Post Divider Register, offset: 0x8824 */ - __IO uint32_t POST_ROOT16_CLR; /**< Post Divider Register, offset: 0x8828 */ - __IO uint32_t POST_ROOT16_TOG; /**< Post Divider Register, offset: 0x882C */ - __IO uint32_t PRE16; /**< Pre Divider Register, offset: 0x8830 */ - __IO uint32_t PRE_ROOT16_SET; /**< Pre Divider Register, offset: 0x8834 */ - __IO uint32_t PRE_ROOT16_CLR; /**< Pre Divider Register, offset: 0x8838 */ - __IO uint32_t PRE_ROOT16_TOG; /**< Pre Divider Register, offset: 0x883C */ - uint8_t RESERVED_35[48]; - __IO uint32_t ACCESS_CTRL16; /**< Access Control Register, offset: 0x8870 */ - __IO uint32_t ACCESS_CTRL16_ROOT_SET; /**< Access Control Register, offset: 0x8874 */ - __IO uint32_t ACCESS_CTRL16_ROOT_CLR; /**< Access Control Register, offset: 0x8878 */ - __IO uint32_t ACCESS_CTRL16_ROOT_TOG; /**< Access Control Register, offset: 0x887C */ - __IO uint32_t TARGET_ROOT17; /**< Target Register, offset: 0x8880 */ - __IO uint32_t TARGET_ROOT17_SET; /**< Target Register, offset: 0x8884 */ - __IO uint32_t TARGET_ROOT17_CLR; /**< Target Register, offset: 0x8888 */ - __IO uint32_t TARGET_ROOT17_TOG; /**< Target Register, offset: 0x888C */ - uint8_t RESERVED_36[16]; - __IO uint32_t POST17; /**< Post Divider Register, offset: 0x88A0 */ - __IO uint32_t POST_ROOT17_SET; /**< Post Divider Register, offset: 0x88A4 */ - __IO uint32_t POST_ROOT17_CLR; /**< Post Divider Register, offset: 0x88A8 */ - __IO uint32_t POST_ROOT17_TOG; /**< Post Divider Register, offset: 0x88AC */ - __IO uint32_t PRE17; /**< Pre Divider Register, offset: 0x88B0 */ - __IO uint32_t PRE_ROOT17_SET; /**< Pre Divider Register, offset: 0x88B4 */ - __IO uint32_t PRE_ROOT17_CLR; /**< Pre Divider Register, offset: 0x88B8 */ - __IO uint32_t PRE_ROOT17_TOG; /**< Pre Divider Register, offset: 0x88BC */ - uint8_t RESERVED_37[48]; - __IO uint32_t ACCESS_CTRL17; /**< Access Control Register, offset: 0x88F0 */ - __IO uint32_t ACCESS_CTRL17_ROOT_SET; /**< Access Control Register, offset: 0x88F4 */ - __IO uint32_t ACCESS_CTRL17_ROOT_CLR; /**< Access Control Register, offset: 0x88F8 */ - __IO uint32_t ACCESS_CTRL17_ROOT_TOG; /**< Access Control Register, offset: 0x88FC */ - __IO uint32_t TARGET_ROOT18; /**< Target Register, offset: 0x8900 */ - __IO uint32_t TARGET_ROOT18_SET; /**< Target Register, offset: 0x8904 */ - __IO uint32_t TARGET_ROOT18_CLR; /**< Target Register, offset: 0x8908 */ - __IO uint32_t TARGET_ROOT18_TOG; /**< Target Register, offset: 0x890C */ - uint8_t RESERVED_38[16]; - __IO uint32_t POST18; /**< Post Divider Register, offset: 0x8920 */ - __IO uint32_t POST_ROOT18_SET; /**< Post Divider Register, offset: 0x8924 */ - __IO uint32_t POST_ROOT18_CLR; /**< Post Divider Register, offset: 0x8928 */ - __IO uint32_t POST_ROOT18_TOG; /**< Post Divider Register, offset: 0x892C */ - __IO uint32_t PRE18; /**< Pre Divider Register, offset: 0x8930 */ - __IO uint32_t PRE_ROOT18_SET; /**< Pre Divider Register, offset: 0x8934 */ - __IO uint32_t PRE_ROOT18_CLR; /**< Pre Divider Register, offset: 0x8938 */ - __IO uint32_t PRE_ROOT18_TOG; /**< Pre Divider Register, offset: 0x893C */ - uint8_t RESERVED_39[48]; - __IO uint32_t ACCESS_CTRL18; /**< Access Control Register, offset: 0x8970 */ - __IO uint32_t ACCESS_CTRL18_ROOT_SET; /**< Access Control Register, offset: 0x8974 */ - __IO uint32_t ACCESS_CTRL18_ROOT_CLR; /**< Access Control Register, offset: 0x8978 */ - __IO uint32_t ACCESS_CTRL18_ROOT_TOG; /**< Access Control Register, offset: 0x897C */ - __IO uint32_t TARGET_ROOT19; /**< Target Register, offset: 0x8980 */ - __IO uint32_t TARGET_ROOT19_SET; /**< Target Register, offset: 0x8984 */ - __IO uint32_t TARGET_ROOT19_CLR; /**< Target Register, offset: 0x8988 */ - __IO uint32_t TARGET_ROOT19_TOG; /**< Target Register, offset: 0x898C */ - uint8_t RESERVED_40[16]; - __IO uint32_t POST19; /**< Post Divider Register, offset: 0x89A0 */ - __IO uint32_t POST_ROOT19_SET; /**< Post Divider Register, offset: 0x89A4 */ - __IO uint32_t POST_ROOT19_CLR; /**< Post Divider Register, offset: 0x89A8 */ - __IO uint32_t POST_ROOT19_TOG; /**< Post Divider Register, offset: 0x89AC */ - __IO uint32_t PRE19; /**< Pre Divider Register, offset: 0x89B0 */ - __IO uint32_t PRE_ROOT19_SET; /**< Pre Divider Register, offset: 0x89B4 */ - __IO uint32_t PRE_ROOT19_CLR; /**< Pre Divider Register, offset: 0x89B8 */ - __IO uint32_t PRE_ROOT19_TOG; /**< Pre Divider Register, offset: 0x89BC */ - uint8_t RESERVED_41[48]; - __IO uint32_t ACCESS_CTRL19; /**< Access Control Register, offset: 0x89F0 */ - __IO uint32_t ACCESS_CTRL19_ROOT_SET; /**< Access Control Register, offset: 0x89F4 */ - __IO uint32_t ACCESS_CTRL19_ROOT_CLR; /**< Access Control Register, offset: 0x89F8 */ - __IO uint32_t ACCESS_CTRL19_ROOT_TOG; /**< Access Control Register, offset: 0x89FC */ - __IO uint32_t TARGET_ROOT20; /**< Target Register, offset: 0x8A00 */ - __IO uint32_t TARGET_ROOT20_SET; /**< Target Register, offset: 0x8A04 */ - __IO uint32_t TARGET_ROOT20_CLR; /**< Target Register, offset: 0x8A08 */ - __IO uint32_t TARGET_ROOT20_TOG; /**< Target Register, offset: 0x8A0C */ - uint8_t RESERVED_42[16]; - __IO uint32_t POST20; /**< Post Divider Register, offset: 0x8A20 */ - __IO uint32_t POST_ROOT20_SET; /**< Post Divider Register, offset: 0x8A24 */ - __IO uint32_t POST_ROOT20_CLR; /**< Post Divider Register, offset: 0x8A28 */ - __IO uint32_t POST_ROOT20_TOG; /**< Post Divider Register, offset: 0x8A2C */ - __IO uint32_t PRE20; /**< Pre Divider Register, offset: 0x8A30 */ - __IO uint32_t PRE_ROOT20_SET; /**< Pre Divider Register, offset: 0x8A34 */ - __IO uint32_t PRE_ROOT20_CLR; /**< Pre Divider Register, offset: 0x8A38 */ - __IO uint32_t PRE_ROOT20_TOG; /**< Pre Divider Register, offset: 0x8A3C */ - uint8_t RESERVED_43[48]; - __IO uint32_t ACCESS_CTRL20; /**< Access Control Register, offset: 0x8A70 */ - __IO uint32_t ACCESS_CTRL20_ROOT_SET; /**< Access Control Register, offset: 0x8A74 */ - __IO uint32_t ACCESS_CTRL20_ROOT_CLR; /**< Access Control Register, offset: 0x8A78 */ - __IO uint32_t ACCESS_CTRL20_ROOT_TOG; /**< Access Control Register, offset: 0x8A7C */ - __IO uint32_t TARGET_ROOT21; /**< Target Register, offset: 0x8A80 */ - __IO uint32_t TARGET_ROOT21_SET; /**< Target Register, offset: 0x8A84 */ - __IO uint32_t TARGET_ROOT21_CLR; /**< Target Register, offset: 0x8A88 */ - __IO uint32_t TARGET_ROOT21_TOG; /**< Target Register, offset: 0x8A8C */ - uint8_t RESERVED_44[16]; - __IO uint32_t POST21; /**< Post Divider Register, offset: 0x8AA0 */ - __IO uint32_t POST_ROOT21_SET; /**< Post Divider Register, offset: 0x8AA4 */ - __IO uint32_t POST_ROOT21_CLR; /**< Post Divider Register, offset: 0x8AA8 */ - __IO uint32_t POST_ROOT21_TOG; /**< Post Divider Register, offset: 0x8AAC */ - __IO uint32_t PRE21; /**< Pre Divider Register, offset: 0x8AB0 */ - __IO uint32_t PRE_ROOT21_SET; /**< Pre Divider Register, offset: 0x8AB4 */ - __IO uint32_t PRE_ROOT21_CLR; /**< Pre Divider Register, offset: 0x8AB8 */ - __IO uint32_t PRE_ROOT21_TOG; /**< Pre Divider Register, offset: 0x8ABC */ - uint8_t RESERVED_45[48]; - __IO uint32_t ACCESS_CTRL21; /**< Access Control Register, offset: 0x8AF0 */ - __IO uint32_t ACCESS_CTRL21_ROOT_SET; /**< Access Control Register, offset: 0x8AF4 */ - __IO uint32_t ACCESS_CTRL21_ROOT_CLR; /**< Access Control Register, offset: 0x8AF8 */ - __IO uint32_t ACCESS_CTRL21_ROOT_TOG; /**< Access Control Register, offset: 0x8AFC */ - __IO uint32_t TARGET_ROOT22; /**< Target Register, offset: 0x8B00 */ - __IO uint32_t TARGET_ROOT22_SET; /**< Target Register, offset: 0x8B04 */ - __IO uint32_t TARGET_ROOT22_CLR; /**< Target Register, offset: 0x8B08 */ - __IO uint32_t TARGET_ROOT22_TOG; /**< Target Register, offset: 0x8B0C */ - uint8_t RESERVED_46[16]; - __IO uint32_t POST22; /**< Post Divider Register, offset: 0x8B20 */ - __IO uint32_t POST_ROOT22_SET; /**< Post Divider Register, offset: 0x8B24 */ - __IO uint32_t POST_ROOT22_CLR; /**< Post Divider Register, offset: 0x8B28 */ - __IO uint32_t POST_ROOT22_TOG; /**< Post Divider Register, offset: 0x8B2C */ - __IO uint32_t PRE22; /**< Pre Divider Register, offset: 0x8B30 */ - __IO uint32_t PRE_ROOT22_SET; /**< Pre Divider Register, offset: 0x8B34 */ - __IO uint32_t PRE_ROOT22_CLR; /**< Pre Divider Register, offset: 0x8B38 */ - __IO uint32_t PRE_ROOT22_TOG; /**< Pre Divider Register, offset: 0x8B3C */ - uint8_t RESERVED_47[48]; - __IO uint32_t ACCESS_CTRL22; /**< Access Control Register, offset: 0x8B70 */ - __IO uint32_t ACCESS_CTRL22_ROOT_SET; /**< Access Control Register, offset: 0x8B74 */ - __IO uint32_t ACCESS_CTRL22_ROOT_CLR; /**< Access Control Register, offset: 0x8B78 */ - __IO uint32_t ACCESS_CTRL22_ROOT_TOG; /**< Access Control Register, offset: 0x8B7C */ - __IO uint32_t TARGET_ROOT23; /**< Target Register, offset: 0x8B80 */ - __IO uint32_t TARGET_ROOT23_SET; /**< Target Register, offset: 0x8B84 */ - __IO uint32_t TARGET_ROOT23_CLR; /**< Target Register, offset: 0x8B88 */ - __IO uint32_t TARGET_ROOT23_TOG; /**< Target Register, offset: 0x8B8C */ - uint8_t RESERVED_48[16]; - __IO uint32_t POST23; /**< Post Divider Register, offset: 0x8BA0 */ - __IO uint32_t POST_ROOT23_SET; /**< Post Divider Register, offset: 0x8BA4 */ - __IO uint32_t POST_ROOT23_CLR; /**< Post Divider Register, offset: 0x8BA8 */ - __IO uint32_t POST_ROOT23_TOG; /**< Post Divider Register, offset: 0x8BAC */ - __IO uint32_t PRE23; /**< Pre Divider Register, offset: 0x8BB0 */ - __IO uint32_t PRE_ROOT23_SET; /**< Pre Divider Register, offset: 0x8BB4 */ - __IO uint32_t PRE_ROOT23_CLR; /**< Pre Divider Register, offset: 0x8BB8 */ - __IO uint32_t PRE_ROOT23_TOG; /**< Pre Divider Register, offset: 0x8BBC */ - uint8_t RESERVED_49[48]; - __IO uint32_t ACCESS_CTRL23; /**< Access Control Register, offset: 0x8BF0 */ - __IO uint32_t ACCESS_CTRL23_ROOT_SET; /**< Access Control Register, offset: 0x8BF4 */ - __IO uint32_t ACCESS_CTRL23_ROOT_CLR; /**< Access Control Register, offset: 0x8BF8 */ - __IO uint32_t ACCESS_CTRL23_ROOT_TOG; /**< Access Control Register, offset: 0x8BFC */ - __IO uint32_t TARGET_ROOT24; /**< Target Register, offset: 0x8C00 */ - __IO uint32_t TARGET_ROOT24_SET; /**< Target Register, offset: 0x8C04 */ - __IO uint32_t TARGET_ROOT24_CLR; /**< Target Register, offset: 0x8C08 */ - __IO uint32_t TARGET_ROOT24_TOG; /**< Target Register, offset: 0x8C0C */ - uint8_t RESERVED_50[16]; - __IO uint32_t POST24; /**< Post Divider Register, offset: 0x8C20 */ - __IO uint32_t POST_ROOT24_SET; /**< Post Divider Register, offset: 0x8C24 */ - __IO uint32_t POST_ROOT24_CLR; /**< Post Divider Register, offset: 0x8C28 */ - __IO uint32_t POST_ROOT24_TOG; /**< Post Divider Register, offset: 0x8C2C */ - __IO uint32_t PRE24; /**< Pre Divider Register, offset: 0x8C30 */ - __IO uint32_t PRE_ROOT24_SET; /**< Pre Divider Register, offset: 0x8C34 */ - __IO uint32_t PRE_ROOT24_CLR; /**< Pre Divider Register, offset: 0x8C38 */ - __IO uint32_t PRE_ROOT24_TOG; /**< Pre Divider Register, offset: 0x8C3C */ - uint8_t RESERVED_51[48]; - __IO uint32_t ACCESS_CTRL24; /**< Access Control Register, offset: 0x8C70 */ - __IO uint32_t ACCESS_CTRL24_ROOT_SET; /**< Access Control Register, offset: 0x8C74 */ - __IO uint32_t ACCESS_CTRL24_ROOT_CLR; /**< Access Control Register, offset: 0x8C78 */ - __IO uint32_t ACCESS_CTRL24_ROOT_TOG; /**< Access Control Register, offset: 0x8C7C */ - __IO uint32_t TARGET_ROOT25; /**< Target Register, offset: 0x8C80 */ - __IO uint32_t TARGET_ROOT25_SET; /**< Target Register, offset: 0x8C84 */ - __IO uint32_t TARGET_ROOT25_CLR; /**< Target Register, offset: 0x8C88 */ - __IO uint32_t TARGET_ROOT25_TOG; /**< Target Register, offset: 0x8C8C */ - uint8_t RESERVED_52[16]; - __IO uint32_t POST25; /**< Post Divider Register, offset: 0x8CA0 */ - __IO uint32_t POST_ROOT25_SET; /**< Post Divider Register, offset: 0x8CA4 */ - __IO uint32_t POST_ROOT25_CLR; /**< Post Divider Register, offset: 0x8CA8 */ - __IO uint32_t POST_ROOT25_TOG; /**< Post Divider Register, offset: 0x8CAC */ - __IO uint32_t PRE25; /**< Pre Divider Register, offset: 0x8CB0 */ - __IO uint32_t PRE_ROOT25_SET; /**< Pre Divider Register, offset: 0x8CB4 */ - __IO uint32_t PRE_ROOT25_CLR; /**< Pre Divider Register, offset: 0x8CB8 */ - __IO uint32_t PRE_ROOT25_TOG; /**< Pre Divider Register, offset: 0x8CBC */ - uint8_t RESERVED_53[48]; - __IO uint32_t ACCESS_CTRL25; /**< Access Control Register, offset: 0x8CF0 */ - __IO uint32_t ACCESS_CTRL25_ROOT_SET; /**< Access Control Register, offset: 0x8CF4 */ - __IO uint32_t ACCESS_CTRL25_ROOT_CLR; /**< Access Control Register, offset: 0x8CF8 */ - __IO uint32_t ACCESS_CTRL25_ROOT_TOG; /**< Access Control Register, offset: 0x8CFC */ - __IO uint32_t TARGET_ROOT26; /**< Target Register, offset: 0x8D00 */ - __IO uint32_t TARGET_ROOT26_SET; /**< Target Register, offset: 0x8D04 */ - __IO uint32_t TARGET_ROOT26_CLR; /**< Target Register, offset: 0x8D08 */ - __IO uint32_t TARGET_ROOT26_TOG; /**< Target Register, offset: 0x8D0C */ - uint8_t RESERVED_54[16]; - __IO uint32_t POST26; /**< Post Divider Register, offset: 0x8D20 */ - __IO uint32_t POST_ROOT26_SET; /**< Post Divider Register, offset: 0x8D24 */ - __IO uint32_t POST_ROOT26_CLR; /**< Post Divider Register, offset: 0x8D28 */ - __IO uint32_t POST_ROOT26_TOG; /**< Post Divider Register, offset: 0x8D2C */ - __IO uint32_t PRE26; /**< Pre Divider Register, offset: 0x8D30 */ - __IO uint32_t PRE_ROOT26_SET; /**< Pre Divider Register, offset: 0x8D34 */ - __IO uint32_t PRE_ROOT26_CLR; /**< Pre Divider Register, offset: 0x8D38 */ - __IO uint32_t PRE_ROOT26_TOG; /**< Pre Divider Register, offset: 0x8D3C */ - uint8_t RESERVED_55[48]; - __IO uint32_t ACCESS_CTRL26; /**< Access Control Register, offset: 0x8D70 */ - __IO uint32_t ACCESS_CTRL26_ROOT_SET; /**< Access Control Register, offset: 0x8D74 */ - __IO uint32_t ACCESS_CTRL26_ROOT_CLR; /**< Access Control Register, offset: 0x8D78 */ - __IO uint32_t ACCESS_CTRL26_ROOT_TOG; /**< Access Control Register, offset: 0x8D7C */ - __IO uint32_t TARGET_ROOT27; /**< Target Register, offset: 0x8D80 */ - __IO uint32_t TARGET_ROOT27_SET; /**< Target Register, offset: 0x8D84 */ - __IO uint32_t TARGET_ROOT27_CLR; /**< Target Register, offset: 0x8D88 */ - __IO uint32_t TARGET_ROOT27_TOG; /**< Target Register, offset: 0x8D8C */ - uint8_t RESERVED_56[16]; - __IO uint32_t POST27; /**< Post Divider Register, offset: 0x8DA0 */ - __IO uint32_t POST_ROOT27_SET; /**< Post Divider Register, offset: 0x8DA4 */ - __IO uint32_t POST_ROOT27_CLR; /**< Post Divider Register, offset: 0x8DA8 */ - __IO uint32_t POST_ROOT27_TOG; /**< Post Divider Register, offset: 0x8DAC */ - __IO uint32_t PRE27; /**< Pre Divider Register, offset: 0x8DB0 */ - __IO uint32_t PRE_ROOT27_SET; /**< Pre Divider Register, offset: 0x8DB4 */ - __IO uint32_t PRE_ROOT27_CLR; /**< Pre Divider Register, offset: 0x8DB8 */ - __IO uint32_t PRE_ROOT27_TOG; /**< Pre Divider Register, offset: 0x8DBC */ - uint8_t RESERVED_57[48]; - __IO uint32_t ACCESS_CTRL27; /**< Access Control Register, offset: 0x8DF0 */ - __IO uint32_t ACCESS_CTRL27_ROOT_SET; /**< Access Control Register, offset: 0x8DF4 */ - __IO uint32_t ACCESS_CTRL27_ROOT_CLR; /**< Access Control Register, offset: 0x8DF8 */ - __IO uint32_t ACCESS_CTRL27_ROOT_TOG; /**< Access Control Register, offset: 0x8DFC */ - __IO uint32_t TARGET_ROOT28; /**< Target Register, offset: 0x8E00 */ - __IO uint32_t TARGET_ROOT28_SET; /**< Target Register, offset: 0x8E04 */ - __IO uint32_t TARGET_ROOT28_CLR; /**< Target Register, offset: 0x8E08 */ - __IO uint32_t TARGET_ROOT28_TOG; /**< Target Register, offset: 0x8E0C */ - uint8_t RESERVED_58[16]; - __IO uint32_t POST28; /**< Post Divider Register, offset: 0x8E20 */ - __IO uint32_t POST_ROOT28_SET; /**< Post Divider Register, offset: 0x8E24 */ - __IO uint32_t POST_ROOT28_CLR; /**< Post Divider Register, offset: 0x8E28 */ - __IO uint32_t POST_ROOT28_TOG; /**< Post Divider Register, offset: 0x8E2C */ - __IO uint32_t PRE28; /**< Pre Divider Register, offset: 0x8E30 */ - __IO uint32_t PRE_ROOT28_SET; /**< Pre Divider Register, offset: 0x8E34 */ - __IO uint32_t PRE_ROOT28_CLR; /**< Pre Divider Register, offset: 0x8E38 */ - __IO uint32_t PRE_ROOT28_TOG; /**< Pre Divider Register, offset: 0x8E3C */ - uint8_t RESERVED_59[48]; - __IO uint32_t ACCESS_CTRL28; /**< Access Control Register, offset: 0x8E70 */ - __IO uint32_t ACCESS_CTRL28_ROOT_SET; /**< Access Control Register, offset: 0x8E74 */ - __IO uint32_t ACCESS_CTRL28_ROOT_CLR; /**< Access Control Register, offset: 0x8E78 */ - __IO uint32_t ACCESS_CTRL28_ROOT_TOG; /**< Access Control Register, offset: 0x8E7C */ - __IO uint32_t TARGET_ROOT29; /**< Target Register, offset: 0x8E80 */ - __IO uint32_t TARGET_ROOT29_SET; /**< Target Register, offset: 0x8E84 */ - __IO uint32_t TARGET_ROOT29_CLR; /**< Target Register, offset: 0x8E88 */ - __IO uint32_t TARGET_ROOT29_TOG; /**< Target Register, offset: 0x8E8C */ - uint8_t RESERVED_60[16]; - __IO uint32_t POST29; /**< Post Divider Register, offset: 0x8EA0 */ - __IO uint32_t POST_ROOT29_SET; /**< Post Divider Register, offset: 0x8EA4 */ - __IO uint32_t POST_ROOT29_CLR; /**< Post Divider Register, offset: 0x8EA8 */ - __IO uint32_t POST_ROOT29_TOG; /**< Post Divider Register, offset: 0x8EAC */ - __IO uint32_t PRE29; /**< Pre Divider Register, offset: 0x8EB0 */ - __IO uint32_t PRE_ROOT29_SET; /**< Pre Divider Register, offset: 0x8EB4 */ - __IO uint32_t PRE_ROOT29_CLR; /**< Pre Divider Register, offset: 0x8EB8 */ - __IO uint32_t PRE_ROOT29_TOG; /**< Pre Divider Register, offset: 0x8EBC */ - uint8_t RESERVED_61[48]; - __IO uint32_t ACCESS_CTRL29; /**< Access Control Register, offset: 0x8EF0 */ - __IO uint32_t ACCESS_CTRL29_ROOT_SET; /**< Access Control Register, offset: 0x8EF4 */ - __IO uint32_t ACCESS_CTRL29_ROOT_CLR; /**< Access Control Register, offset: 0x8EF8 */ - __IO uint32_t ACCESS_CTRL29_ROOT_TOG; /**< Access Control Register, offset: 0x8EFC */ - __IO uint32_t TARGET_ROOT30; /**< Target Register, offset: 0x8F00 */ - __IO uint32_t TARGET_ROOT30_SET; /**< Target Register, offset: 0x8F04 */ - __IO uint32_t TARGET_ROOT30_CLR; /**< Target Register, offset: 0x8F08 */ - __IO uint32_t TARGET_ROOT30_TOG; /**< Target Register, offset: 0x8F0C */ - uint8_t RESERVED_62[16]; - __IO uint32_t POST30; /**< Post Divider Register, offset: 0x8F20 */ - __IO uint32_t POST_ROOT30_SET; /**< Post Divider Register, offset: 0x8F24 */ - __IO uint32_t POST_ROOT30_CLR; /**< Post Divider Register, offset: 0x8F28 */ - __IO uint32_t POST_ROOT30_TOG; /**< Post Divider Register, offset: 0x8F2C */ - __IO uint32_t PRE30; /**< Pre Divider Register, offset: 0x8F30 */ - __IO uint32_t PRE_ROOT30_SET; /**< Pre Divider Register, offset: 0x8F34 */ - __IO uint32_t PRE_ROOT30_CLR; /**< Pre Divider Register, offset: 0x8F38 */ - __IO uint32_t PRE_ROOT30_TOG; /**< Pre Divider Register, offset: 0x8F3C */ - uint8_t RESERVED_63[48]; - __IO uint32_t ACCESS_CTRL30; /**< Access Control Register, offset: 0x8F70 */ - __IO uint32_t ACCESS_CTRL30_ROOT_SET; /**< Access Control Register, offset: 0x8F74 */ - __IO uint32_t ACCESS_CTRL30_ROOT_CLR; /**< Access Control Register, offset: 0x8F78 */ - __IO uint32_t ACCESS_CTRL30_ROOT_TOG; /**< Access Control Register, offset: 0x8F7C */ - __IO uint32_t TARGET_ROOT31; /**< Target Register, offset: 0x8F80 */ - __IO uint32_t TARGET_ROOT31_SET; /**< Target Register, offset: 0x8F84 */ - __IO uint32_t TARGET_ROOT31_CLR; /**< Target Register, offset: 0x8F88 */ - __IO uint32_t TARGET_ROOT31_TOG; /**< Target Register, offset: 0x8F8C */ - uint8_t RESERVED_64[16]; - __IO uint32_t POST31; /**< Post Divider Register, offset: 0x8FA0 */ - __IO uint32_t POST_ROOT31_SET; /**< Post Divider Register, offset: 0x8FA4 */ - __IO uint32_t POST_ROOT31_CLR; /**< Post Divider Register, offset: 0x8FA8 */ - __IO uint32_t POST_ROOT31_TOG; /**< Post Divider Register, offset: 0x8FAC */ - __IO uint32_t PRE31; /**< Pre Divider Register, offset: 0x8FB0 */ - __IO uint32_t PRE_ROOT31_SET; /**< Pre Divider Register, offset: 0x8FB4 */ - __IO uint32_t PRE_ROOT31_CLR; /**< Pre Divider Register, offset: 0x8FB8 */ - __IO uint32_t PRE_ROOT31_TOG; /**< Pre Divider Register, offset: 0x8FBC */ - uint8_t RESERVED_65[48]; - __IO uint32_t ACCESS_CTRL31; /**< Access Control Register, offset: 0x8FF0 */ - __IO uint32_t ACCESS_CTRL31_ROOT_SET; /**< Access Control Register, offset: 0x8FF4 */ - __IO uint32_t ACCESS_CTRL31_ROOT_CLR; /**< Access Control Register, offset: 0x8FF8 */ - __IO uint32_t ACCESS_CTRL31_ROOT_TOG; /**< Access Control Register, offset: 0x8FFC */ - __IO uint32_t TARGET_ROOT32; /**< Target Register, offset: 0x9000 */ - __IO uint32_t TARGET_ROOT32_SET; /**< Target Register, offset: 0x9004 */ - __IO uint32_t TARGET_ROOT32_CLR; /**< Target Register, offset: 0x9008 */ - __IO uint32_t TARGET_ROOT32_TOG; /**< Target Register, offset: 0x900C */ - uint8_t RESERVED_66[16]; - __IO uint32_t POST32; /**< Post Divider Register, offset: 0x9020 */ - __IO uint32_t POST_ROOT32_SET; /**< Post Divider Register, offset: 0x9024 */ - __IO uint32_t POST_ROOT32_CLR; /**< Post Divider Register, offset: 0x9028 */ - __IO uint32_t POST_ROOT32_TOG; /**< Post Divider Register, offset: 0x902C */ - __IO uint32_t PRE32; /**< Pre Divider Register, offset: 0x9030 */ - __IO uint32_t PRE_ROOT32_SET; /**< Pre Divider Register, offset: 0x9034 */ - __IO uint32_t PRE_ROOT32_CLR; /**< Pre Divider Register, offset: 0x9038 */ - __IO uint32_t PRE_ROOT32_TOG; /**< Pre Divider Register, offset: 0x903C */ - uint8_t RESERVED_67[48]; - __IO uint32_t ACCESS_CTRL32; /**< Access Control Register, offset: 0x9070 */ - __IO uint32_t ACCESS_CTRL32_ROOT_SET; /**< Access Control Register, offset: 0x9074 */ - __IO uint32_t ACCESS_CTRL32_ROOT_CLR; /**< Access Control Register, offset: 0x9078 */ - __IO uint32_t ACCESS_CTRL32_ROOT_TOG; /**< Access Control Register, offset: 0x907C */ - __IO uint32_t TARGET_ROOT33; /**< Target Register, offset: 0x9080 */ - __IO uint32_t TARGET_ROOT33_SET; /**< Target Register, offset: 0x9084 */ - __IO uint32_t TARGET_ROOT33_CLR; /**< Target Register, offset: 0x9088 */ - __IO uint32_t TARGET_ROOT33_TOG; /**< Target Register, offset: 0x908C */ - uint8_t RESERVED_68[16]; - __IO uint32_t POST33; /**< Post Divider Register, offset: 0x90A0 */ - __IO uint32_t POST_ROOT33_SET; /**< Post Divider Register, offset: 0x90A4 */ - __IO uint32_t POST_ROOT33_CLR; /**< Post Divider Register, offset: 0x90A8 */ - __IO uint32_t POST_ROOT33_TOG; /**< Post Divider Register, offset: 0x90AC */ - __IO uint32_t PRE33; /**< Pre Divider Register, offset: 0x90B0 */ - __IO uint32_t PRE_ROOT33_SET; /**< Pre Divider Register, offset: 0x90B4 */ - __IO uint32_t PRE_ROOT33_CLR; /**< Pre Divider Register, offset: 0x90B8 */ - __IO uint32_t PRE_ROOT33_TOG; /**< Pre Divider Register, offset: 0x90BC */ - uint8_t RESERVED_69[48]; - __IO uint32_t ACCESS_CTRL33; /**< Access Control Register, offset: 0x90F0 */ - __IO uint32_t ACCESS_CTRL33_ROOT_SET; /**< Access Control Register, offset: 0x90F4 */ - __IO uint32_t ACCESS_CTRL33_ROOT_CLR; /**< Access Control Register, offset: 0x90F8 */ - __IO uint32_t ACCESS_CTRL33_ROOT_TOG; /**< Access Control Register, offset: 0x90FC */ - __IO uint32_t TARGET_ROOT34; /**< Target Register, offset: 0x9100 */ - __IO uint32_t TARGET_ROOT34_SET; /**< Target Register, offset: 0x9104 */ - __IO uint32_t TARGET_ROOT34_CLR; /**< Target Register, offset: 0x9108 */ - __IO uint32_t TARGET_ROOT34_TOG; /**< Target Register, offset: 0x910C */ - uint8_t RESERVED_70[16]; - __IO uint32_t POST34; /**< Post Divider Register, offset: 0x9120 */ - __IO uint32_t POST_ROOT34_SET; /**< Post Divider Register, offset: 0x9124 */ - __IO uint32_t POST_ROOT34_CLR; /**< Post Divider Register, offset: 0x9128 */ - __IO uint32_t POST_ROOT34_TOG; /**< Post Divider Register, offset: 0x912C */ - __IO uint32_t PRE34; /**< Pre Divider Register, offset: 0x9130 */ - __IO uint32_t PRE_ROOT34_SET; /**< Pre Divider Register, offset: 0x9134 */ - __IO uint32_t PRE_ROOT34_CLR; /**< Pre Divider Register, offset: 0x9138 */ - __IO uint32_t PRE_ROOT34_TOG; /**< Pre Divider Register, offset: 0x913C */ - uint8_t RESERVED_71[48]; - __IO uint32_t ACCESS_CTRL34; /**< Access Control Register, offset: 0x9170 */ - __IO uint32_t ACCESS_CTRL34_ROOT_SET; /**< Access Control Register, offset: 0x9174 */ - __IO uint32_t ACCESS_CTRL34_ROOT_CLR; /**< Access Control Register, offset: 0x9178 */ - __IO uint32_t ACCESS_CTRL34_ROOT_TOG; /**< Access Control Register, offset: 0x917C */ - __IO uint32_t TARGET_ROOT35; /**< Target Register, offset: 0x9180 */ - __IO uint32_t TARGET_ROOT35_SET; /**< Target Register, offset: 0x9184 */ - __IO uint32_t TARGET_ROOT35_CLR; /**< Target Register, offset: 0x9188 */ - __IO uint32_t TARGET_ROOT35_TOG; /**< Target Register, offset: 0x918C */ - uint8_t RESERVED_72[16]; - __IO uint32_t POST35; /**< Post Divider Register, offset: 0x91A0 */ - __IO uint32_t POST_ROOT35_SET; /**< Post Divider Register, offset: 0x91A4 */ - __IO uint32_t POST_ROOT35_CLR; /**< Post Divider Register, offset: 0x91A8 */ - __IO uint32_t POST_ROOT35_TOG; /**< Post Divider Register, offset: 0x91AC */ - __IO uint32_t PRE35; /**< Pre Divider Register, offset: 0x91B0 */ - __IO uint32_t PRE_ROOT35_SET; /**< Pre Divider Register, offset: 0x91B4 */ - __IO uint32_t PRE_ROOT35_CLR; /**< Pre Divider Register, offset: 0x91B8 */ - __IO uint32_t PRE_ROOT35_TOG; /**< Pre Divider Register, offset: 0x91BC */ - uint8_t RESERVED_73[48]; - __IO uint32_t ACCESS_CTRL35; /**< Access Control Register, offset: 0x91F0 */ - __IO uint32_t ACCESS_CTRL35_ROOT_SET; /**< Access Control Register, offset: 0x91F4 */ - __IO uint32_t ACCESS_CTRL35_ROOT_CLR; /**< Access Control Register, offset: 0x91F8 */ - __IO uint32_t ACCESS_CTRL35_ROOT_TOG; /**< Access Control Register, offset: 0x91FC */ - __IO uint32_t TARGET_ROOT36; /**< Target Register, offset: 0x9200 */ - __IO uint32_t TARGET_ROOT36_SET; /**< Target Register, offset: 0x9204 */ - __IO uint32_t TARGET_ROOT36_CLR; /**< Target Register, offset: 0x9208 */ - __IO uint32_t TARGET_ROOT36_TOG; /**< Target Register, offset: 0x920C */ - uint8_t RESERVED_74[16]; - __IO uint32_t POST36; /**< Post Divider Register, offset: 0x9220 */ - __IO uint32_t POST_ROOT36_SET; /**< Post Divider Register, offset: 0x9224 */ - __IO uint32_t POST_ROOT36_CLR; /**< Post Divider Register, offset: 0x9228 */ - __IO uint32_t POST_ROOT36_TOG; /**< Post Divider Register, offset: 0x922C */ - __IO uint32_t PRE36; /**< Pre Divider Register, offset: 0x9230 */ - __IO uint32_t PRE_ROOT36_SET; /**< Pre Divider Register, offset: 0x9234 */ - __IO uint32_t PRE_ROOT36_CLR; /**< Pre Divider Register, offset: 0x9238 */ - __IO uint32_t PRE_ROOT36_TOG; /**< Pre Divider Register, offset: 0x923C */ - uint8_t RESERVED_75[48]; - __IO uint32_t ACCESS_CTRL36; /**< Access Control Register, offset: 0x9270 */ - __IO uint32_t ACCESS_CTRL36_ROOT_SET; /**< Access Control Register, offset: 0x9274 */ - __IO uint32_t ACCESS_CTRL36_ROOT_CLR; /**< Access Control Register, offset: 0x9278 */ - __IO uint32_t ACCESS_CTRL36_ROOT_TOG; /**< Access Control Register, offset: 0x927C */ - __IO uint32_t TARGET_ROOT37; /**< Target Register, offset: 0x9280 */ - __IO uint32_t TARGET_ROOT37_SET; /**< Target Register, offset: 0x9284 */ - __IO uint32_t TARGET_ROOT37_CLR; /**< Target Register, offset: 0x9288 */ - __IO uint32_t TARGET_ROOT37_TOG; /**< Target Register, offset: 0x928C */ - uint8_t RESERVED_76[16]; - __IO uint32_t POST37; /**< Post Divider Register, offset: 0x92A0 */ - __IO uint32_t POST_ROOT37_SET; /**< Post Divider Register, offset: 0x92A4 */ - __IO uint32_t POST_ROOT37_CLR; /**< Post Divider Register, offset: 0x92A8 */ - __IO uint32_t POST_ROOT37_TOG; /**< Post Divider Register, offset: 0x92AC */ - __IO uint32_t PRE37; /**< Pre Divider Register, offset: 0x92B0 */ - __IO uint32_t PRE_ROOT37_SET; /**< Pre Divider Register, offset: 0x92B4 */ - __IO uint32_t PRE_ROOT37_CLR; /**< Pre Divider Register, offset: 0x92B8 */ - __IO uint32_t PRE_ROOT37_TOG; /**< Pre Divider Register, offset: 0x92BC */ - uint8_t RESERVED_77[48]; - __IO uint32_t ACCESS_CTRL37; /**< Access Control Register, offset: 0x92F0 */ - __IO uint32_t ACCESS_CTRL37_ROOT_SET; /**< Access Control Register, offset: 0x92F4 */ - __IO uint32_t ACCESS_CTRL37_ROOT_CLR; /**< Access Control Register, offset: 0x92F8 */ - __IO uint32_t ACCESS_CTRL37_ROOT_TOG; /**< Access Control Register, offset: 0x92FC */ - __IO uint32_t TARGET_ROOT38; /**< Target Register, offset: 0x9300 */ - __IO uint32_t TARGET_ROOT38_SET; /**< Target Register, offset: 0x9304 */ - __IO uint32_t TARGET_ROOT38_CLR; /**< Target Register, offset: 0x9308 */ - __IO uint32_t TARGET_ROOT38_TOG; /**< Target Register, offset: 0x930C */ - uint8_t RESERVED_78[16]; - __IO uint32_t POST38; /**< Post Divider Register, offset: 0x9320 */ - __IO uint32_t POST_ROOT38_SET; /**< Post Divider Register, offset: 0x9324 */ - __IO uint32_t POST_ROOT38_CLR; /**< Post Divider Register, offset: 0x9328 */ - __IO uint32_t POST_ROOT38_TOG; /**< Post Divider Register, offset: 0x932C */ - __IO uint32_t PRE38; /**< Pre Divider Register, offset: 0x9330 */ - __IO uint32_t PRE_ROOT38_SET; /**< Pre Divider Register, offset: 0x9334 */ - __IO uint32_t PRE_ROOT38_CLR; /**< Pre Divider Register, offset: 0x9338 */ - __IO uint32_t PRE_ROOT38_TOG; /**< Pre Divider Register, offset: 0x933C */ - uint8_t RESERVED_79[48]; - __IO uint32_t ACCESS_CTRL38; /**< Access Control Register, offset: 0x9370 */ - __IO uint32_t ACCESS_CTRL38_ROOT_SET; /**< Access Control Register, offset: 0x9374 */ - __IO uint32_t ACCESS_CTRL38_ROOT_CLR; /**< Access Control Register, offset: 0x9378 */ - __IO uint32_t ACCESS_CTRL38_ROOT_TOG; /**< Access Control Register, offset: 0x937C */ - __IO uint32_t TARGET_ROOT39; /**< Target Register, offset: 0x9380 */ - __IO uint32_t TARGET_ROOT39_SET; /**< Target Register, offset: 0x9384 */ - __IO uint32_t TARGET_ROOT39_CLR; /**< Target Register, offset: 0x9388 */ - __IO uint32_t TARGET_ROOT39_TOG; /**< Target Register, offset: 0x938C */ - uint8_t RESERVED_80[16]; - __IO uint32_t POST39; /**< Post Divider Register, offset: 0x93A0 */ - __IO uint32_t POST_ROOT39_SET; /**< Post Divider Register, offset: 0x93A4 */ - __IO uint32_t POST_ROOT39_CLR; /**< Post Divider Register, offset: 0x93A8 */ - __IO uint32_t POST_ROOT39_TOG; /**< Post Divider Register, offset: 0x93AC */ - __IO uint32_t PRE39; /**< Pre Divider Register, offset: 0x93B0 */ - __IO uint32_t PRE_ROOT39_SET; /**< Pre Divider Register, offset: 0x93B4 */ - __IO uint32_t PRE_ROOT39_CLR; /**< Pre Divider Register, offset: 0x93B8 */ - __IO uint32_t PRE_ROOT39_TOG; /**< Pre Divider Register, offset: 0x93BC */ - uint8_t RESERVED_81[48]; - __IO uint32_t ACCESS_CTRL39; /**< Access Control Register, offset: 0x93F0 */ - __IO uint32_t ACCESS_CTRL39_ROOT_SET; /**< Access Control Register, offset: 0x93F4 */ - __IO uint32_t ACCESS_CTRL39_ROOT_CLR; /**< Access Control Register, offset: 0x93F8 */ - __IO uint32_t ACCESS_CTRL39_ROOT_TOG; /**< Access Control Register, offset: 0x93FC */ - __IO uint32_t TARGET_ROOT40; /**< Target Register, offset: 0x9400 */ - __IO uint32_t TARGET_ROOT40_SET; /**< Target Register, offset: 0x9404 */ - __IO uint32_t TARGET_ROOT40_CLR; /**< Target Register, offset: 0x9408 */ - __IO uint32_t TARGET_ROOT40_TOG; /**< Target Register, offset: 0x940C */ - uint8_t RESERVED_82[16]; - __IO uint32_t POST40; /**< Post Divider Register, offset: 0x9420 */ - __IO uint32_t POST_ROOT40_SET; /**< Post Divider Register, offset: 0x9424 */ - __IO uint32_t POST_ROOT40_CLR; /**< Post Divider Register, offset: 0x9428 */ - __IO uint32_t POST_ROOT40_TOG; /**< Post Divider Register, offset: 0x942C */ - __IO uint32_t PRE40; /**< Pre Divider Register, offset: 0x9430 */ - __IO uint32_t PRE_ROOT40_SET; /**< Pre Divider Register, offset: 0x9434 */ - __IO uint32_t PRE_ROOT40_CLR; /**< Pre Divider Register, offset: 0x9438 */ - __IO uint32_t PRE_ROOT40_TOG; /**< Pre Divider Register, offset: 0x943C */ - uint8_t RESERVED_83[48]; - __IO uint32_t ACCESS_CTRL40; /**< Access Control Register, offset: 0x9470 */ - __IO uint32_t ACCESS_CTRL40_ROOT_SET; /**< Access Control Register, offset: 0x9474 */ - __IO uint32_t ACCESS_CTRL40_ROOT_CLR; /**< Access Control Register, offset: 0x9478 */ - __IO uint32_t ACCESS_CTRL40_ROOT_TOG; /**< Access Control Register, offset: 0x947C */ - __IO uint32_t TARGET_ROOT41; /**< Target Register, offset: 0x9480 */ - __IO uint32_t TARGET_ROOT41_SET; /**< Target Register, offset: 0x9484 */ - __IO uint32_t TARGET_ROOT41_CLR; /**< Target Register, offset: 0x9488 */ - __IO uint32_t TARGET_ROOT41_TOG; /**< Target Register, offset: 0x948C */ - uint8_t RESERVED_84[16]; - __IO uint32_t POST41; /**< Post Divider Register, offset: 0x94A0 */ - __IO uint32_t POST_ROOT41_SET; /**< Post Divider Register, offset: 0x94A4 */ - __IO uint32_t POST_ROOT41_CLR; /**< Post Divider Register, offset: 0x94A8 */ - __IO uint32_t POST_ROOT41_TOG; /**< Post Divider Register, offset: 0x94AC */ - __IO uint32_t PRE41; /**< Pre Divider Register, offset: 0x94B0 */ - __IO uint32_t PRE_ROOT41_SET; /**< Pre Divider Register, offset: 0x94B4 */ - __IO uint32_t PRE_ROOT41_CLR; /**< Pre Divider Register, offset: 0x94B8 */ - __IO uint32_t PRE_ROOT41_TOG; /**< Pre Divider Register, offset: 0x94BC */ - uint8_t RESERVED_85[48]; - __IO uint32_t ACCESS_CTRL41; /**< Access Control Register, offset: 0x94F0 */ - __IO uint32_t ACCESS_CTRL41_ROOT_SET; /**< Access Control Register, offset: 0x94F4 */ - __IO uint32_t ACCESS_CTRL41_ROOT_CLR; /**< Access Control Register, offset: 0x94F8 */ - __IO uint32_t ACCESS_CTRL41_ROOT_TOG; /**< Access Control Register, offset: 0x94FC */ - __IO uint32_t TARGET_ROOT42; /**< Target Register, offset: 0x9500 */ - __IO uint32_t TARGET_ROOT42_SET; /**< Target Register, offset: 0x9504 */ - __IO uint32_t TARGET_ROOT42_CLR; /**< Target Register, offset: 0x9508 */ - __IO uint32_t TARGET_ROOT42_TOG; /**< Target Register, offset: 0x950C */ - uint8_t RESERVED_86[16]; - __IO uint32_t POST42; /**< Post Divider Register, offset: 0x9520 */ - __IO uint32_t POST_ROOT42_SET; /**< Post Divider Register, offset: 0x9524 */ - __IO uint32_t POST_ROOT42_CLR; /**< Post Divider Register, offset: 0x9528 */ - __IO uint32_t POST_ROOT42_TOG; /**< Post Divider Register, offset: 0x952C */ - __IO uint32_t PRE42; /**< Pre Divider Register, offset: 0x9530 */ - __IO uint32_t PRE_ROOT42_SET; /**< Pre Divider Register, offset: 0x9534 */ - __IO uint32_t PRE_ROOT42_CLR; /**< Pre Divider Register, offset: 0x9538 */ - __IO uint32_t PRE_ROOT42_TOG; /**< Pre Divider Register, offset: 0x953C */ - uint8_t RESERVED_87[48]; - __IO uint32_t ACCESS_CTRL42; /**< Access Control Register, offset: 0x9570 */ - __IO uint32_t ACCESS_CTRL42_ROOT_SET; /**< Access Control Register, offset: 0x9574 */ - __IO uint32_t ACCESS_CTRL42_ROOT_CLR; /**< Access Control Register, offset: 0x9578 */ - __IO uint32_t ACCESS_CTRL42_ROOT_TOG; /**< Access Control Register, offset: 0x957C */ - __IO uint32_t TARGET_ROOT43; /**< Target Register, offset: 0x9580 */ - __IO uint32_t TARGET_ROOT43_SET; /**< Target Register, offset: 0x9584 */ - __IO uint32_t TARGET_ROOT43_CLR; /**< Target Register, offset: 0x9588 */ - __IO uint32_t TARGET_ROOT43_TOG; /**< Target Register, offset: 0x958C */ - uint8_t RESERVED_88[16]; - __IO uint32_t POST43; /**< Post Divider Register, offset: 0x95A0 */ - __IO uint32_t POST_ROOT43_SET; /**< Post Divider Register, offset: 0x95A4 */ - __IO uint32_t POST_ROOT43_CLR; /**< Post Divider Register, offset: 0x95A8 */ - __IO uint32_t POST_ROOT43_TOG; /**< Post Divider Register, offset: 0x95AC */ - __IO uint32_t PRE43; /**< Pre Divider Register, offset: 0x95B0 */ - __IO uint32_t PRE_ROOT43_SET; /**< Pre Divider Register, offset: 0x95B4 */ - __IO uint32_t PRE_ROOT43_CLR; /**< Pre Divider Register, offset: 0x95B8 */ - __IO uint32_t PRE_ROOT43_TOG; /**< Pre Divider Register, offset: 0x95BC */ - uint8_t RESERVED_89[48]; - __IO uint32_t ACCESS_CTRL43; /**< Access Control Register, offset: 0x95F0 */ - __IO uint32_t ACCESS_CTRL43_ROOT_SET; /**< Access Control Register, offset: 0x95F4 */ - __IO uint32_t ACCESS_CTRL43_ROOT_CLR; /**< Access Control Register, offset: 0x95F8 */ - __IO uint32_t ACCESS_CTRL43_ROOT_TOG; /**< Access Control Register, offset: 0x95FC */ - __IO uint32_t TARGET_ROOT44; /**< Target Register, offset: 0x9600 */ - __IO uint32_t TARGET_ROOT44_SET; /**< Target Register, offset: 0x9604 */ - __IO uint32_t TARGET_ROOT44_CLR; /**< Target Register, offset: 0x9608 */ - __IO uint32_t TARGET_ROOT44_TOG; /**< Target Register, offset: 0x960C */ - uint8_t RESERVED_90[16]; - __IO uint32_t POST44; /**< Post Divider Register, offset: 0x9620 */ - __IO uint32_t POST_ROOT44_SET; /**< Post Divider Register, offset: 0x9624 */ - __IO uint32_t POST_ROOT44_CLR; /**< Post Divider Register, offset: 0x9628 */ - __IO uint32_t POST_ROOT44_TOG; /**< Post Divider Register, offset: 0x962C */ - __IO uint32_t PRE44; /**< Pre Divider Register, offset: 0x9630 */ - __IO uint32_t PRE_ROOT44_SET; /**< Pre Divider Register, offset: 0x9634 */ - __IO uint32_t PRE_ROOT44_CLR; /**< Pre Divider Register, offset: 0x9638 */ - __IO uint32_t PRE_ROOT44_TOG; /**< Pre Divider Register, offset: 0x963C */ - uint8_t RESERVED_91[48]; - __IO uint32_t ACCESS_CTRL44; /**< Access Control Register, offset: 0x9670 */ - __IO uint32_t ACCESS_CTRL44_ROOT_SET; /**< Access Control Register, offset: 0x9674 */ - __IO uint32_t ACCESS_CTRL44_ROOT_CLR; /**< Access Control Register, offset: 0x9678 */ - __IO uint32_t ACCESS_CTRL44_ROOT_TOG; /**< Access Control Register, offset: 0x967C */ - __IO uint32_t TARGET_ROOT45; /**< Target Register, offset: 0x9680 */ - __IO uint32_t TARGET_ROOT45_SET; /**< Target Register, offset: 0x9684 */ - __IO uint32_t TARGET_ROOT45_CLR; /**< Target Register, offset: 0x9688 */ - __IO uint32_t TARGET_ROOT45_TOG; /**< Target Register, offset: 0x968C */ - uint8_t RESERVED_92[16]; - __IO uint32_t POST45; /**< Post Divider Register, offset: 0x96A0 */ - __IO uint32_t POST_ROOT45_SET; /**< Post Divider Register, offset: 0x96A4 */ - __IO uint32_t POST_ROOT45_CLR; /**< Post Divider Register, offset: 0x96A8 */ - __IO uint32_t POST_ROOT45_TOG; /**< Post Divider Register, offset: 0x96AC */ - __IO uint32_t PRE45; /**< Pre Divider Register, offset: 0x96B0 */ - __IO uint32_t PRE_ROOT45_SET; /**< Pre Divider Register, offset: 0x96B4 */ - __IO uint32_t PRE_ROOT45_CLR; /**< Pre Divider Register, offset: 0x96B8 */ - __IO uint32_t PRE_ROOT45_TOG; /**< Pre Divider Register, offset: 0x96BC */ - uint8_t RESERVED_93[48]; - __IO uint32_t ACCESS_CTRL45; /**< Access Control Register, offset: 0x96F0 */ - __IO uint32_t ACCESS_CTRL45_ROOT_SET; /**< Access Control Register, offset: 0x96F4 */ - __IO uint32_t ACCESS_CTRL45_ROOT_CLR; /**< Access Control Register, offset: 0x96F8 */ - __IO uint32_t ACCESS_CTRL45_ROOT_TOG; /**< Access Control Register, offset: 0x96FC */ - __IO uint32_t TARGET_ROOT46; /**< Target Register, offset: 0x9700 */ - __IO uint32_t TARGET_ROOT46_SET; /**< Target Register, offset: 0x9704 */ - __IO uint32_t TARGET_ROOT46_CLR; /**< Target Register, offset: 0x9708 */ - __IO uint32_t TARGET_ROOT46_TOG; /**< Target Register, offset: 0x970C */ - uint8_t RESERVED_94[16]; - __IO uint32_t POST46; /**< Post Divider Register, offset: 0x9720 */ - __IO uint32_t POST_ROOT46_SET; /**< Post Divider Register, offset: 0x9724 */ - __IO uint32_t POST_ROOT46_CLR; /**< Post Divider Register, offset: 0x9728 */ - __IO uint32_t POST_ROOT46_TOG; /**< Post Divider Register, offset: 0x972C */ - __IO uint32_t PRE46; /**< Pre Divider Register, offset: 0x9730 */ - __IO uint32_t PRE_ROOT46_SET; /**< Pre Divider Register, offset: 0x9734 */ - __IO uint32_t PRE_ROOT46_CLR; /**< Pre Divider Register, offset: 0x9738 */ - __IO uint32_t PRE_ROOT46_TOG; /**< Pre Divider Register, offset: 0x973C */ - uint8_t RESERVED_95[48]; - __IO uint32_t ACCESS_CTRL46; /**< Access Control Register, offset: 0x9770 */ - __IO uint32_t ACCESS_CTRL46_ROOT_SET; /**< Access Control Register, offset: 0x9774 */ - __IO uint32_t ACCESS_CTRL46_ROOT_CLR; /**< Access Control Register, offset: 0x9778 */ - __IO uint32_t ACCESS_CTRL46_ROOT_TOG; /**< Access Control Register, offset: 0x977C */ - __IO uint32_t TARGET_ROOT47; /**< Target Register, offset: 0x9780 */ - __IO uint32_t TARGET_ROOT47_SET; /**< Target Register, offset: 0x9784 */ - __IO uint32_t TARGET_ROOT47_CLR; /**< Target Register, offset: 0x9788 */ - __IO uint32_t TARGET_ROOT47_TOG; /**< Target Register, offset: 0x978C */ - uint8_t RESERVED_96[16]; - __IO uint32_t POST47; /**< Post Divider Register, offset: 0x97A0 */ - __IO uint32_t POST_ROOT47_SET; /**< Post Divider Register, offset: 0x97A4 */ - __IO uint32_t POST_ROOT47_CLR; /**< Post Divider Register, offset: 0x97A8 */ - __IO uint32_t POST_ROOT47_TOG; /**< Post Divider Register, offset: 0x97AC */ - __IO uint32_t PRE47; /**< Pre Divider Register, offset: 0x97B0 */ - __IO uint32_t PRE_ROOT47_SET; /**< Pre Divider Register, offset: 0x97B4 */ - __IO uint32_t PRE_ROOT47_CLR; /**< Pre Divider Register, offset: 0x97B8 */ - __IO uint32_t PRE_ROOT47_TOG; /**< Pre Divider Register, offset: 0x97BC */ - uint8_t RESERVED_97[48]; - __IO uint32_t ACCESS_CTRL47; /**< Access Control Register, offset: 0x97F0 */ - __IO uint32_t ACCESS_CTRL47_ROOT_SET; /**< Access Control Register, offset: 0x97F4 */ - __IO uint32_t ACCESS_CTRL47_ROOT_CLR; /**< Access Control Register, offset: 0x97F8 */ - __IO uint32_t ACCESS_CTRL47_ROOT_TOG; /**< Access Control Register, offset: 0x97FC */ - __IO uint32_t TARGET_ROOT48; /**< Target Register, offset: 0x9800 */ - __IO uint32_t TARGET_ROOT48_SET; /**< Target Register, offset: 0x9804 */ - __IO uint32_t TARGET_ROOT48_CLR; /**< Target Register, offset: 0x9808 */ - __IO uint32_t TARGET_ROOT48_TOG; /**< Target Register, offset: 0x980C */ - uint8_t RESERVED_98[16]; - __IO uint32_t POST48; /**< Post Divider Register, offset: 0x9820 */ - __IO uint32_t POST_ROOT48_SET; /**< Post Divider Register, offset: 0x9824 */ - __IO uint32_t POST_ROOT48_CLR; /**< Post Divider Register, offset: 0x9828 */ - __IO uint32_t POST_ROOT48_TOG; /**< Post Divider Register, offset: 0x982C */ - __IO uint32_t PRE48; /**< Pre Divider Register, offset: 0x9830 */ - __IO uint32_t PRE_ROOT48_SET; /**< Pre Divider Register, offset: 0x9834 */ - __IO uint32_t PRE_ROOT48_CLR; /**< Pre Divider Register, offset: 0x9838 */ - __IO uint32_t PRE_ROOT48_TOG; /**< Pre Divider Register, offset: 0x983C */ - uint8_t RESERVED_99[48]; - __IO uint32_t ACCESS_CTRL48; /**< Access Control Register, offset: 0x9870 */ - __IO uint32_t ACCESS_CTRL48_ROOT_SET; /**< Access Control Register, offset: 0x9874 */ - __IO uint32_t ACCESS_CTRL48_ROOT_CLR; /**< Access Control Register, offset: 0x9878 */ - __IO uint32_t ACCESS_CTRL48_ROOT_TOG; /**< Access Control Register, offset: 0x987C */ - __IO uint32_t TARGET_ROOT49; /**< Target Register, offset: 0x9880 */ - __IO uint32_t TARGET_ROOT49_SET; /**< Target Register, offset: 0x9884 */ - __IO uint32_t TARGET_ROOT49_CLR; /**< Target Register, offset: 0x9888 */ - __IO uint32_t TARGET_ROOT49_TOG; /**< Target Register, offset: 0x988C */ - uint8_t RESERVED_100[16]; - __IO uint32_t POST49; /**< Post Divider Register, offset: 0x98A0 */ - __IO uint32_t POST_ROOT49_SET; /**< Post Divider Register, offset: 0x98A4 */ - __IO uint32_t POST_ROOT49_CLR; /**< Post Divider Register, offset: 0x98A8 */ - __IO uint32_t POST_ROOT49_TOG; /**< Post Divider Register, offset: 0x98AC */ - __IO uint32_t PRE49; /**< Pre Divider Register, offset: 0x98B0 */ - __IO uint32_t PRE_ROOT49_SET; /**< Pre Divider Register, offset: 0x98B4 */ - __IO uint32_t PRE_ROOT49_CLR; /**< Pre Divider Register, offset: 0x98B8 */ - __IO uint32_t PRE_ROOT49_TOG; /**< Pre Divider Register, offset: 0x98BC */ - uint8_t RESERVED_101[48]; - __IO uint32_t ACCESS_CTRL49; /**< Access Control Register, offset: 0x98F0 */ - __IO uint32_t ACCESS_CTRL49_ROOT_SET; /**< Access Control Register, offset: 0x98F4 */ - __IO uint32_t ACCESS_CTRL49_ROOT_CLR; /**< Access Control Register, offset: 0x98F8 */ - __IO uint32_t ACCESS_CTRL49_ROOT_TOG; /**< Access Control Register, offset: 0x98FC */ - __IO uint32_t TARGET_ROOT50; /**< Target Register, offset: 0x9900 */ - __IO uint32_t TARGET_ROOT50_SET; /**< Target Register, offset: 0x9904 */ - __IO uint32_t TARGET_ROOT50_CLR; /**< Target Register, offset: 0x9908 */ - __IO uint32_t TARGET_ROOT50_TOG; /**< Target Register, offset: 0x990C */ - uint8_t RESERVED_102[16]; - __IO uint32_t POST50; /**< Post Divider Register, offset: 0x9920 */ - __IO uint32_t POST_ROOT50_SET; /**< Post Divider Register, offset: 0x9924 */ - __IO uint32_t POST_ROOT50_CLR; /**< Post Divider Register, offset: 0x9928 */ - __IO uint32_t POST_ROOT50_TOG; /**< Post Divider Register, offset: 0x992C */ - __IO uint32_t PRE50; /**< Pre Divider Register, offset: 0x9930 */ - __IO uint32_t PRE_ROOT50_SET; /**< Pre Divider Register, offset: 0x9934 */ - __IO uint32_t PRE_ROOT50_CLR; /**< Pre Divider Register, offset: 0x9938 */ - __IO uint32_t PRE_ROOT50_TOG; /**< Pre Divider Register, offset: 0x993C */ - uint8_t RESERVED_103[48]; - __IO uint32_t ACCESS_CTRL50; /**< Access Control Register, offset: 0x9970 */ - __IO uint32_t ACCESS_CTRL50_ROOT_SET; /**< Access Control Register, offset: 0x9974 */ - __IO uint32_t ACCESS_CTRL50_ROOT_CLR; /**< Access Control Register, offset: 0x9978 */ - __IO uint32_t ACCESS_CTRL50_ROOT_TOG; /**< Access Control Register, offset: 0x997C */ - __IO uint32_t TARGET_ROOT51; /**< Target Register, offset: 0x9980 */ - __IO uint32_t TARGET_ROOT51_SET; /**< Target Register, offset: 0x9984 */ - __IO uint32_t TARGET_ROOT51_CLR; /**< Target Register, offset: 0x9988 */ - __IO uint32_t TARGET_ROOT51_TOG; /**< Target Register, offset: 0x998C */ - uint8_t RESERVED_104[16]; - __IO uint32_t POST51; /**< Post Divider Register, offset: 0x99A0 */ - __IO uint32_t POST_ROOT51_SET; /**< Post Divider Register, offset: 0x99A4 */ - __IO uint32_t POST_ROOT51_CLR; /**< Post Divider Register, offset: 0x99A8 */ - __IO uint32_t POST_ROOT51_TOG; /**< Post Divider Register, offset: 0x99AC */ - __IO uint32_t PRE51; /**< Pre Divider Register, offset: 0x99B0 */ - __IO uint32_t PRE_ROOT51_SET; /**< Pre Divider Register, offset: 0x99B4 */ - __IO uint32_t PRE_ROOT51_CLR; /**< Pre Divider Register, offset: 0x99B8 */ - __IO uint32_t PRE_ROOT51_TOG; /**< Pre Divider Register, offset: 0x99BC */ - uint8_t RESERVED_105[48]; - __IO uint32_t ACCESS_CTRL51; /**< Access Control Register, offset: 0x99F0 */ - __IO uint32_t ACCESS_CTRL51_ROOT_SET; /**< Access Control Register, offset: 0x99F4 */ - __IO uint32_t ACCESS_CTRL51_ROOT_CLR; /**< Access Control Register, offset: 0x99F8 */ - __IO uint32_t ACCESS_CTRL51_ROOT_TOG; /**< Access Control Register, offset: 0x99FC */ - __IO uint32_t TARGET_ROOT52; /**< Target Register, offset: 0x9A00 */ - __IO uint32_t TARGET_ROOT52_SET; /**< Target Register, offset: 0x9A04 */ - __IO uint32_t TARGET_ROOT52_CLR; /**< Target Register, offset: 0x9A08 */ - __IO uint32_t TARGET_ROOT52_TOG; /**< Target Register, offset: 0x9A0C */ - uint8_t RESERVED_106[16]; - __IO uint32_t POST52; /**< Post Divider Register, offset: 0x9A20 */ - __IO uint32_t POST_ROOT52_SET; /**< Post Divider Register, offset: 0x9A24 */ - __IO uint32_t POST_ROOT52_CLR; /**< Post Divider Register, offset: 0x9A28 */ - __IO uint32_t POST_ROOT52_TOG; /**< Post Divider Register, offset: 0x9A2C */ - __IO uint32_t PRE52; /**< Pre Divider Register, offset: 0x9A30 */ - __IO uint32_t PRE_ROOT52_SET; /**< Pre Divider Register, offset: 0x9A34 */ - __IO uint32_t PRE_ROOT52_CLR; /**< Pre Divider Register, offset: 0x9A38 */ - __IO uint32_t PRE_ROOT52_TOG; /**< Pre Divider Register, offset: 0x9A3C */ - uint8_t RESERVED_107[48]; - __IO uint32_t ACCESS_CTRL52; /**< Access Control Register, offset: 0x9A70 */ - __IO uint32_t ACCESS_CTRL52_ROOT_SET; /**< Access Control Register, offset: 0x9A74 */ - __IO uint32_t ACCESS_CTRL52_ROOT_CLR; /**< Access Control Register, offset: 0x9A78 */ - __IO uint32_t ACCESS_CTRL52_ROOT_TOG; /**< Access Control Register, offset: 0x9A7C */ - __IO uint32_t TARGET_ROOT53; /**< Target Register, offset: 0x9A80 */ - __IO uint32_t TARGET_ROOT53_SET; /**< Target Register, offset: 0x9A84 */ - __IO uint32_t TARGET_ROOT53_CLR; /**< Target Register, offset: 0x9A88 */ - __IO uint32_t TARGET_ROOT53_TOG; /**< Target Register, offset: 0x9A8C */ - uint8_t RESERVED_108[16]; - __IO uint32_t POST53; /**< Post Divider Register, offset: 0x9AA0 */ - __IO uint32_t POST_ROOT53_SET; /**< Post Divider Register, offset: 0x9AA4 */ - __IO uint32_t POST_ROOT53_CLR; /**< Post Divider Register, offset: 0x9AA8 */ - __IO uint32_t POST_ROOT53_TOG; /**< Post Divider Register, offset: 0x9AAC */ - __IO uint32_t PRE53; /**< Pre Divider Register, offset: 0x9AB0 */ - __IO uint32_t PRE_ROOT53_SET; /**< Pre Divider Register, offset: 0x9AB4 */ - __IO uint32_t PRE_ROOT53_CLR; /**< Pre Divider Register, offset: 0x9AB8 */ - __IO uint32_t PRE_ROOT53_TOG; /**< Pre Divider Register, offset: 0x9ABC */ - uint8_t RESERVED_109[48]; - __IO uint32_t ACCESS_CTRL53; /**< Access Control Register, offset: 0x9AF0 */ - __IO uint32_t ACCESS_CTRL53_ROOT_SET; /**< Access Control Register, offset: 0x9AF4 */ - __IO uint32_t ACCESS_CTRL53_ROOT_CLR; /**< Access Control Register, offset: 0x9AF8 */ - __IO uint32_t ACCESS_CTRL53_ROOT_TOG; /**< Access Control Register, offset: 0x9AFC */ - __IO uint32_t TARGET_ROOT54; /**< Target Register, offset: 0x9B00 */ - __IO uint32_t TARGET_ROOT54_SET; /**< Target Register, offset: 0x9B04 */ - __IO uint32_t TARGET_ROOT54_CLR; /**< Target Register, offset: 0x9B08 */ - __IO uint32_t TARGET_ROOT54_TOG; /**< Target Register, offset: 0x9B0C */ - uint8_t RESERVED_110[16]; - __IO uint32_t POST54; /**< Post Divider Register, offset: 0x9B20 */ - __IO uint32_t POST_ROOT54_SET; /**< Post Divider Register, offset: 0x9B24 */ - __IO uint32_t POST_ROOT54_CLR; /**< Post Divider Register, offset: 0x9B28 */ - __IO uint32_t POST_ROOT54_TOG; /**< Post Divider Register, offset: 0x9B2C */ - __IO uint32_t PRE54; /**< Pre Divider Register, offset: 0x9B30 */ - __IO uint32_t PRE_ROOT54_SET; /**< Pre Divider Register, offset: 0x9B34 */ - __IO uint32_t PRE_ROOT54_CLR; /**< Pre Divider Register, offset: 0x9B38 */ - __IO uint32_t PRE_ROOT54_TOG; /**< Pre Divider Register, offset: 0x9B3C */ - uint8_t RESERVED_111[48]; - __IO uint32_t ACCESS_CTRL54; /**< Access Control Register, offset: 0x9B70 */ - __IO uint32_t ACCESS_CTRL54_ROOT_SET; /**< Access Control Register, offset: 0x9B74 */ - __IO uint32_t ACCESS_CTRL54_ROOT_CLR; /**< Access Control Register, offset: 0x9B78 */ - __IO uint32_t ACCESS_CTRL54_ROOT_TOG; /**< Access Control Register, offset: 0x9B7C */ - __IO uint32_t TARGET_ROOT55; /**< Target Register, offset: 0x9B80 */ - __IO uint32_t TARGET_ROOT55_SET; /**< Target Register, offset: 0x9B84 */ - __IO uint32_t TARGET_ROOT55_CLR; /**< Target Register, offset: 0x9B88 */ - __IO uint32_t TARGET_ROOT55_TOG; /**< Target Register, offset: 0x9B8C */ - uint8_t RESERVED_112[16]; - __IO uint32_t POST55; /**< Post Divider Register, offset: 0x9BA0 */ - __IO uint32_t POST_ROOT55_SET; /**< Post Divider Register, offset: 0x9BA4 */ - __IO uint32_t POST_ROOT55_CLR; /**< Post Divider Register, offset: 0x9BA8 */ - __IO uint32_t POST_ROOT55_TOG; /**< Post Divider Register, offset: 0x9BAC */ - __IO uint32_t PRE55; /**< Pre Divider Register, offset: 0x9BB0 */ - __IO uint32_t PRE_ROOT55_SET; /**< Pre Divider Register, offset: 0x9BB4 */ - __IO uint32_t PRE_ROOT55_CLR; /**< Pre Divider Register, offset: 0x9BB8 */ - __IO uint32_t PRE_ROOT55_TOG; /**< Pre Divider Register, offset: 0x9BBC */ - uint8_t RESERVED_113[48]; - __IO uint32_t ACCESS_CTRL55; /**< Access Control Register, offset: 0x9BF0 */ - __IO uint32_t ACCESS_CTRL55_ROOT_SET; /**< Access Control Register, offset: 0x9BF4 */ - __IO uint32_t ACCESS_CTRL55_ROOT_CLR; /**< Access Control Register, offset: 0x9BF8 */ - __IO uint32_t ACCESS_CTRL55_ROOT_TOG; /**< Access Control Register, offset: 0x9BFC */ - __IO uint32_t TARGET_ROOT56; /**< Target Register, offset: 0x9C00 */ - __IO uint32_t TARGET_ROOT56_SET; /**< Target Register, offset: 0x9C04 */ - __IO uint32_t TARGET_ROOT56_CLR; /**< Target Register, offset: 0x9C08 */ - __IO uint32_t TARGET_ROOT56_TOG; /**< Target Register, offset: 0x9C0C */ - uint8_t RESERVED_114[16]; - __IO uint32_t POST56; /**< Post Divider Register, offset: 0x9C20 */ - __IO uint32_t POST_ROOT56_SET; /**< Post Divider Register, offset: 0x9C24 */ - __IO uint32_t POST_ROOT56_CLR; /**< Post Divider Register, offset: 0x9C28 */ - __IO uint32_t POST_ROOT56_TOG; /**< Post Divider Register, offset: 0x9C2C */ - __IO uint32_t PRE56; /**< Pre Divider Register, offset: 0x9C30 */ - __IO uint32_t PRE_ROOT56_SET; /**< Pre Divider Register, offset: 0x9C34 */ - __IO uint32_t PRE_ROOT56_CLR; /**< Pre Divider Register, offset: 0x9C38 */ - __IO uint32_t PRE_ROOT56_TOG; /**< Pre Divider Register, offset: 0x9C3C */ - uint8_t RESERVED_115[48]; - __IO uint32_t ACCESS_CTRL56; /**< Access Control Register, offset: 0x9C70 */ - __IO uint32_t ACCESS_CTRL56_ROOT_SET; /**< Access Control Register, offset: 0x9C74 */ - __IO uint32_t ACCESS_CTRL56_ROOT_CLR; /**< Access Control Register, offset: 0x9C78 */ - __IO uint32_t ACCESS_CTRL56_ROOT_TOG; /**< Access Control Register, offset: 0x9C7C */ - __IO uint32_t TARGET_ROOT57; /**< Target Register, offset: 0x9C80 */ - __IO uint32_t TARGET_ROOT57_SET; /**< Target Register, offset: 0x9C84 */ - __IO uint32_t TARGET_ROOT57_CLR; /**< Target Register, offset: 0x9C88 */ - __IO uint32_t TARGET_ROOT57_TOG; /**< Target Register, offset: 0x9C8C */ - uint8_t RESERVED_116[16]; - __IO uint32_t POST57; /**< Post Divider Register, offset: 0x9CA0 */ - __IO uint32_t POST_ROOT57_SET; /**< Post Divider Register, offset: 0x9CA4 */ - __IO uint32_t POST_ROOT57_CLR; /**< Post Divider Register, offset: 0x9CA8 */ - __IO uint32_t POST_ROOT57_TOG; /**< Post Divider Register, offset: 0x9CAC */ - __IO uint32_t PRE57; /**< Pre Divider Register, offset: 0x9CB0 */ - __IO uint32_t PRE_ROOT57_SET; /**< Pre Divider Register, offset: 0x9CB4 */ - __IO uint32_t PRE_ROOT57_CLR; /**< Pre Divider Register, offset: 0x9CB8 */ - __IO uint32_t PRE_ROOT57_TOG; /**< Pre Divider Register, offset: 0x9CBC */ - uint8_t RESERVED_117[48]; - __IO uint32_t ACCESS_CTRL57; /**< Access Control Register, offset: 0x9CF0 */ - __IO uint32_t ACCESS_CTRL57_ROOT_SET; /**< Access Control Register, offset: 0x9CF4 */ - __IO uint32_t ACCESS_CTRL57_ROOT_CLR; /**< Access Control Register, offset: 0x9CF8 */ - __IO uint32_t ACCESS_CTRL57_ROOT_TOG; /**< Access Control Register, offset: 0x9CFC */ - __IO uint32_t TARGET_ROOT58; /**< Target Register, offset: 0x9D00 */ - __IO uint32_t TARGET_ROOT58_SET; /**< Target Register, offset: 0x9D04 */ - __IO uint32_t TARGET_ROOT58_CLR; /**< Target Register, offset: 0x9D08 */ - __IO uint32_t TARGET_ROOT58_TOG; /**< Target Register, offset: 0x9D0C */ - uint8_t RESERVED_118[16]; - __IO uint32_t POST58; /**< Post Divider Register, offset: 0x9D20 */ - __IO uint32_t POST_ROOT58_SET; /**< Post Divider Register, offset: 0x9D24 */ - __IO uint32_t POST_ROOT58_CLR; /**< Post Divider Register, offset: 0x9D28 */ - __IO uint32_t POST_ROOT58_TOG; /**< Post Divider Register, offset: 0x9D2C */ - __IO uint32_t PRE58; /**< Pre Divider Register, offset: 0x9D30 */ - __IO uint32_t PRE_ROOT58_SET; /**< Pre Divider Register, offset: 0x9D34 */ - __IO uint32_t PRE_ROOT58_CLR; /**< Pre Divider Register, offset: 0x9D38 */ - __IO uint32_t PRE_ROOT58_TOG; /**< Pre Divider Register, offset: 0x9D3C */ - uint8_t RESERVED_119[48]; - __IO uint32_t ACCESS_CTRL58; /**< Access Control Register, offset: 0x9D70 */ - __IO uint32_t ACCESS_CTRL58_ROOT_SET; /**< Access Control Register, offset: 0x9D74 */ - __IO uint32_t ACCESS_CTRL58_ROOT_CLR; /**< Access Control Register, offset: 0x9D78 */ - __IO uint32_t ACCESS_CTRL58_ROOT_TOG; /**< Access Control Register, offset: 0x9D7C */ - __IO uint32_t TARGET_ROOT59; /**< Target Register, offset: 0x9D80 */ - __IO uint32_t TARGET_ROOT59_SET; /**< Target Register, offset: 0x9D84 */ - __IO uint32_t TARGET_ROOT59_CLR; /**< Target Register, offset: 0x9D88 */ - __IO uint32_t TARGET_ROOT59_TOG; /**< Target Register, offset: 0x9D8C */ - uint8_t RESERVED_120[16]; - __IO uint32_t POST59; /**< Post Divider Register, offset: 0x9DA0 */ - __IO uint32_t POST_ROOT59_SET; /**< Post Divider Register, offset: 0x9DA4 */ - __IO uint32_t POST_ROOT59_CLR; /**< Post Divider Register, offset: 0x9DA8 */ - __IO uint32_t POST_ROOT59_TOG; /**< Post Divider Register, offset: 0x9DAC */ - __IO uint32_t PRE59; /**< Pre Divider Register, offset: 0x9DB0 */ - __IO uint32_t PRE_ROOT59_SET; /**< Pre Divider Register, offset: 0x9DB4 */ - __IO uint32_t PRE_ROOT59_CLR; /**< Pre Divider Register, offset: 0x9DB8 */ - __IO uint32_t PRE_ROOT59_TOG; /**< Pre Divider Register, offset: 0x9DBC */ - uint8_t RESERVED_121[48]; - __IO uint32_t ACCESS_CTRL59; /**< Access Control Register, offset: 0x9DF0 */ - __IO uint32_t ACCESS_CTRL59_ROOT_SET; /**< Access Control Register, offset: 0x9DF4 */ - __IO uint32_t ACCESS_CTRL59_ROOT_CLR; /**< Access Control Register, offset: 0x9DF8 */ - __IO uint32_t ACCESS_CTRL59_ROOT_TOG; /**< Access Control Register, offset: 0x9DFC */ - __IO uint32_t TARGET_ROOT60; /**< Target Register, offset: 0x9E00 */ - __IO uint32_t TARGET_ROOT60_SET; /**< Target Register, offset: 0x9E04 */ - __IO uint32_t TARGET_ROOT60_CLR; /**< Target Register, offset: 0x9E08 */ - __IO uint32_t TARGET_ROOT60_TOG; /**< Target Register, offset: 0x9E0C */ - uint8_t RESERVED_122[16]; - __IO uint32_t POST60; /**< Post Divider Register, offset: 0x9E20 */ - __IO uint32_t POST_ROOT60_SET; /**< Post Divider Register, offset: 0x9E24 */ - __IO uint32_t POST_ROOT60_CLR; /**< Post Divider Register, offset: 0x9E28 */ - __IO uint32_t POST_ROOT60_TOG; /**< Post Divider Register, offset: 0x9E2C */ - __IO uint32_t PRE60; /**< Pre Divider Register, offset: 0x9E30 */ - __IO uint32_t PRE_ROOT60_SET; /**< Pre Divider Register, offset: 0x9E34 */ - __IO uint32_t PRE_ROOT60_CLR; /**< Pre Divider Register, offset: 0x9E38 */ - __IO uint32_t PRE_ROOT60_TOG; /**< Pre Divider Register, offset: 0x9E3C */ - uint8_t RESERVED_123[48]; - __IO uint32_t ACCESS_CTRL60; /**< Access Control Register, offset: 0x9E70 */ - __IO uint32_t ACCESS_CTRL60_ROOT_SET; /**< Access Control Register, offset: 0x9E74 */ - __IO uint32_t ACCESS_CTRL60_ROOT_CLR; /**< Access Control Register, offset: 0x9E78 */ - __IO uint32_t ACCESS_CTRL60_ROOT_TOG; /**< Access Control Register, offset: 0x9E7C */ - __IO uint32_t TARGET_ROOT61; /**< Target Register, offset: 0x9E80 */ - __IO uint32_t TARGET_ROOT61_SET; /**< Target Register, offset: 0x9E84 */ - __IO uint32_t TARGET_ROOT61_CLR; /**< Target Register, offset: 0x9E88 */ - __IO uint32_t TARGET_ROOT61_TOG; /**< Target Register, offset: 0x9E8C */ - uint8_t RESERVED_124[16]; - __IO uint32_t POST61; /**< Post Divider Register, offset: 0x9EA0 */ - __IO uint32_t POST_ROOT61_SET; /**< Post Divider Register, offset: 0x9EA4 */ - __IO uint32_t POST_ROOT61_CLR; /**< Post Divider Register, offset: 0x9EA8 */ - __IO uint32_t POST_ROOT61_TOG; /**< Post Divider Register, offset: 0x9EAC */ - __IO uint32_t PRE61; /**< Pre Divider Register, offset: 0x9EB0 */ - __IO uint32_t PRE_ROOT61_SET; /**< Pre Divider Register, offset: 0x9EB4 */ - __IO uint32_t PRE_ROOT61_CLR; /**< Pre Divider Register, offset: 0x9EB8 */ - __IO uint32_t PRE_ROOT61_TOG; /**< Pre Divider Register, offset: 0x9EBC */ - uint8_t RESERVED_125[48]; - __IO uint32_t ACCESS_CTRL61; /**< Access Control Register, offset: 0x9EF0 */ - __IO uint32_t ACCESS_CTRL61_ROOT_SET; /**< Access Control Register, offset: 0x9EF4 */ - __IO uint32_t ACCESS_CTRL61_ROOT_CLR; /**< Access Control Register, offset: 0x9EF8 */ - __IO uint32_t ACCESS_CTRL61_ROOT_TOG; /**< Access Control Register, offset: 0x9EFC */ - __IO uint32_t TARGET_ROOT62; /**< Target Register, offset: 0x9F00 */ - __IO uint32_t TARGET_ROOT62_SET; /**< Target Register, offset: 0x9F04 */ - __IO uint32_t TARGET_ROOT62_CLR; /**< Target Register, offset: 0x9F08 */ - __IO uint32_t TARGET_ROOT62_TOG; /**< Target Register, offset: 0x9F0C */ - uint8_t RESERVED_126[16]; - __IO uint32_t POST62; /**< Post Divider Register, offset: 0x9F20 */ - __IO uint32_t POST_ROOT62_SET; /**< Post Divider Register, offset: 0x9F24 */ - __IO uint32_t POST_ROOT62_CLR; /**< Post Divider Register, offset: 0x9F28 */ - __IO uint32_t POST_ROOT62_TOG; /**< Post Divider Register, offset: 0x9F2C */ - __IO uint32_t PRE62; /**< Pre Divider Register, offset: 0x9F30 */ - __IO uint32_t PRE_ROOT62_SET; /**< Pre Divider Register, offset: 0x9F34 */ - __IO uint32_t PRE_ROOT62_CLR; /**< Pre Divider Register, offset: 0x9F38 */ - __IO uint32_t PRE_ROOT62_TOG; /**< Pre Divider Register, offset: 0x9F3C */ - uint8_t RESERVED_127[48]; - __IO uint32_t ACCESS_CTRL62; /**< Access Control Register, offset: 0x9F70 */ - __IO uint32_t ACCESS_CTRL62_ROOT_SET; /**< Access Control Register, offset: 0x9F74 */ - __IO uint32_t ACCESS_CTRL62_ROOT_CLR; /**< Access Control Register, offset: 0x9F78 */ - __IO uint32_t ACCESS_CTRL62_ROOT_TOG; /**< Access Control Register, offset: 0x9F7C */ - __IO uint32_t TARGET_ROOT63; /**< Target Register, offset: 0x9F80 */ - __IO uint32_t TARGET_ROOT63_SET; /**< Target Register, offset: 0x9F84 */ - __IO uint32_t TARGET_ROOT63_CLR; /**< Target Register, offset: 0x9F88 */ - __IO uint32_t TARGET_ROOT63_TOG; /**< Target Register, offset: 0x9F8C */ - uint8_t RESERVED_128[16]; - __IO uint32_t POST63; /**< Post Divider Register, offset: 0x9FA0 */ - __IO uint32_t POST_ROOT63_SET; /**< Post Divider Register, offset: 0x9FA4 */ - __IO uint32_t POST_ROOT63_CLR; /**< Post Divider Register, offset: 0x9FA8 */ - __IO uint32_t POST_ROOT63_TOG; /**< Post Divider Register, offset: 0x9FAC */ - __IO uint32_t PRE63; /**< Pre Divider Register, offset: 0x9FB0 */ - __IO uint32_t PRE_ROOT63_SET; /**< Pre Divider Register, offset: 0x9FB4 */ - __IO uint32_t PRE_ROOT63_CLR; /**< Pre Divider Register, offset: 0x9FB8 */ - __IO uint32_t PRE_ROOT63_TOG; /**< Pre Divider Register, offset: 0x9FBC */ - uint8_t RESERVED_129[48]; - __IO uint32_t ACCESS_CTRL63; /**< Access Control Register, offset: 0x9FF0 */ - __IO uint32_t ACCESS_CTRL63_ROOT_SET; /**< Access Control Register, offset: 0x9FF4 */ - __IO uint32_t ACCESS_CTRL63_ROOT_CLR; /**< Access Control Register, offset: 0x9FF8 */ - __IO uint32_t ACCESS_CTRL63_ROOT_TOG; /**< Access Control Register, offset: 0x9FFC */ - __IO uint32_t TARGET_ROOT64; /**< Target Register, offset: 0xA000 */ - __IO uint32_t TARGET_ROOT64_SET; /**< Target Register, offset: 0xA004 */ - __IO uint32_t TARGET_ROOT64_CLR; /**< Target Register, offset: 0xA008 */ - __IO uint32_t TARGET_ROOT64_TOG; /**< Target Register, offset: 0xA00C */ - uint8_t RESERVED_130[16]; - __IO uint32_t POST64; /**< Post Divider Register, offset: 0xA020 */ - __IO uint32_t POST_ROOT64_SET; /**< Post Divider Register, offset: 0xA024 */ - __IO uint32_t POST_ROOT64_CLR; /**< Post Divider Register, offset: 0xA028 */ - __IO uint32_t POST_ROOT64_TOG; /**< Post Divider Register, offset: 0xA02C */ - __IO uint32_t PRE64; /**< Pre Divider Register, offset: 0xA030 */ - __IO uint32_t PRE_ROOT64_SET; /**< Pre Divider Register, offset: 0xA034 */ - __IO uint32_t PRE_ROOT64_CLR; /**< Pre Divider Register, offset: 0xA038 */ - __IO uint32_t PRE_ROOT64_TOG; /**< Pre Divider Register, offset: 0xA03C */ - uint8_t RESERVED_131[48]; - __IO uint32_t ACCESS_CTRL64; /**< Access Control Register, offset: 0xA070 */ - __IO uint32_t ACCESS_CTRL64_ROOT_SET; /**< Access Control Register, offset: 0xA074 */ - __IO uint32_t ACCESS_CTRL64_ROOT_CLR; /**< Access Control Register, offset: 0xA078 */ - __IO uint32_t ACCESS_CTRL64_ROOT_TOG; /**< Access Control Register, offset: 0xA07C */ - __IO uint32_t TARGET_ROOT65; /**< Target Register, offset: 0xA080 */ - __IO uint32_t TARGET_ROOT65_SET; /**< Target Register, offset: 0xA084 */ - __IO uint32_t TARGET_ROOT65_CLR; /**< Target Register, offset: 0xA088 */ - __IO uint32_t TARGET_ROOT65_TOG; /**< Target Register, offset: 0xA08C */ - uint8_t RESERVED_132[16]; - __IO uint32_t POST65; /**< Post Divider Register, offset: 0xA0A0 */ - __IO uint32_t POST_ROOT65_SET; /**< Post Divider Register, offset: 0xA0A4 */ - __IO uint32_t POST_ROOT65_CLR; /**< Post Divider Register, offset: 0xA0A8 */ - __IO uint32_t POST_ROOT65_TOG; /**< Post Divider Register, offset: 0xA0AC */ - __IO uint32_t PRE65; /**< Pre Divider Register, offset: 0xA0B0 */ - __IO uint32_t PRE_ROOT65_SET; /**< Pre Divider Register, offset: 0xA0B4 */ - __IO uint32_t PRE_ROOT65_CLR; /**< Pre Divider Register, offset: 0xA0B8 */ - __IO uint32_t PRE_ROOT65_TOG; /**< Pre Divider Register, offset: 0xA0BC */ - uint8_t RESERVED_133[48]; - __IO uint32_t ACCESS_CTRL65; /**< Access Control Register, offset: 0xA0F0 */ - __IO uint32_t ACCESS_CTRL65_ROOT_SET; /**< Access Control Register, offset: 0xA0F4 */ - __IO uint32_t ACCESS_CTRL65_ROOT_CLR; /**< Access Control Register, offset: 0xA0F8 */ - __IO uint32_t ACCESS_CTRL65_ROOT_TOG; /**< Access Control Register, offset: 0xA0FC */ - __IO uint32_t TARGET_ROOT66; /**< Target Register, offset: 0xA100 */ - __IO uint32_t TARGET_ROOT66_SET; /**< Target Register, offset: 0xA104 */ - __IO uint32_t TARGET_ROOT66_CLR; /**< Target Register, offset: 0xA108 */ - __IO uint32_t TARGET_ROOT66_TOG; /**< Target Register, offset: 0xA10C */ - uint8_t RESERVED_134[16]; - __IO uint32_t POST66; /**< Post Divider Register, offset: 0xA120 */ - __IO uint32_t POST_ROOT66_SET; /**< Post Divider Register, offset: 0xA124 */ - __IO uint32_t POST_ROOT66_CLR; /**< Post Divider Register, offset: 0xA128 */ - __IO uint32_t POST_ROOT66_TOG; /**< Post Divider Register, offset: 0xA12C */ - __IO uint32_t PRE66; /**< Pre Divider Register, offset: 0xA130 */ - __IO uint32_t PRE_ROOT66_SET; /**< Pre Divider Register, offset: 0xA134 */ - __IO uint32_t PRE_ROOT66_CLR; /**< Pre Divider Register, offset: 0xA138 */ - __IO uint32_t PRE_ROOT66_TOG; /**< Pre Divider Register, offset: 0xA13C */ - uint8_t RESERVED_135[48]; - __IO uint32_t ACCESS_CTRL66; /**< Access Control Register, offset: 0xA170 */ - __IO uint32_t ACCESS_CTRL66_ROOT_SET; /**< Access Control Register, offset: 0xA174 */ - __IO uint32_t ACCESS_CTRL66_ROOT_CLR; /**< Access Control Register, offset: 0xA178 */ - __IO uint32_t ACCESS_CTRL66_ROOT_TOG; /**< Access Control Register, offset: 0xA17C */ - __IO uint32_t TARGET_ROOT67; /**< Target Register, offset: 0xA180 */ - __IO uint32_t TARGET_ROOT67_SET; /**< Target Register, offset: 0xA184 */ - __IO uint32_t TARGET_ROOT67_CLR; /**< Target Register, offset: 0xA188 */ - __IO uint32_t TARGET_ROOT67_TOG; /**< Target Register, offset: 0xA18C */ - uint8_t RESERVED_136[16]; - __IO uint32_t POST67; /**< Post Divider Register, offset: 0xA1A0 */ - __IO uint32_t POST_ROOT67_SET; /**< Post Divider Register, offset: 0xA1A4 */ - __IO uint32_t POST_ROOT67_CLR; /**< Post Divider Register, offset: 0xA1A8 */ - __IO uint32_t POST_ROOT67_TOG; /**< Post Divider Register, offset: 0xA1AC */ - __IO uint32_t PRE67; /**< Pre Divider Register, offset: 0xA1B0 */ - __IO uint32_t PRE_ROOT67_SET; /**< Pre Divider Register, offset: 0xA1B4 */ - __IO uint32_t PRE_ROOT67_CLR; /**< Pre Divider Register, offset: 0xA1B8 */ - __IO uint32_t PRE_ROOT67_TOG; /**< Pre Divider Register, offset: 0xA1BC */ - uint8_t RESERVED_137[48]; - __IO uint32_t ACCESS_CTRL67; /**< Access Control Register, offset: 0xA1F0 */ - __IO uint32_t ACCESS_CTRL67_ROOT_SET; /**< Access Control Register, offset: 0xA1F4 */ - __IO uint32_t ACCESS_CTRL67_ROOT_CLR; /**< Access Control Register, offset: 0xA1F8 */ - __IO uint32_t ACCESS_CTRL67_ROOT_TOG; /**< Access Control Register, offset: 0xA1FC */ - __IO uint32_t TARGET_ROOT68; /**< Target Register, offset: 0xA200 */ - __IO uint32_t TARGET_ROOT68_SET; /**< Target Register, offset: 0xA204 */ - __IO uint32_t TARGET_ROOT68_CLR; /**< Target Register, offset: 0xA208 */ - __IO uint32_t TARGET_ROOT68_TOG; /**< Target Register, offset: 0xA20C */ - uint8_t RESERVED_138[16]; - __IO uint32_t POST68; /**< Post Divider Register, offset: 0xA220 */ - __IO uint32_t POST_ROOT68_SET; /**< Post Divider Register, offset: 0xA224 */ - __IO uint32_t POST_ROOT68_CLR; /**< Post Divider Register, offset: 0xA228 */ - __IO uint32_t POST_ROOT68_TOG; /**< Post Divider Register, offset: 0xA22C */ - __IO uint32_t PRE68; /**< Pre Divider Register, offset: 0xA230 */ - __IO uint32_t PRE_ROOT68_SET; /**< Pre Divider Register, offset: 0xA234 */ - __IO uint32_t PRE_ROOT68_CLR; /**< Pre Divider Register, offset: 0xA238 */ - __IO uint32_t PRE_ROOT68_TOG; /**< Pre Divider Register, offset: 0xA23C */ - uint8_t RESERVED_139[48]; - __IO uint32_t ACCESS_CTRL68; /**< Access Control Register, offset: 0xA270 */ - __IO uint32_t ACCESS_CTRL68_ROOT_SET; /**< Access Control Register, offset: 0xA274 */ - __IO uint32_t ACCESS_CTRL68_ROOT_CLR; /**< Access Control Register, offset: 0xA278 */ - __IO uint32_t ACCESS_CTRL68_ROOT_TOG; /**< Access Control Register, offset: 0xA27C */ - __IO uint32_t TARGET_ROOT69; /**< Target Register, offset: 0xA280 */ - __IO uint32_t TARGET_ROOT69_SET; /**< Target Register, offset: 0xA284 */ - __IO uint32_t TARGET_ROOT69_CLR; /**< Target Register, offset: 0xA288 */ - __IO uint32_t TARGET_ROOT69_TOG; /**< Target Register, offset: 0xA28C */ - uint8_t RESERVED_140[16]; - __IO uint32_t POST69; /**< Post Divider Register, offset: 0xA2A0 */ - __IO uint32_t POST_ROOT69_SET; /**< Post Divider Register, offset: 0xA2A4 */ - __IO uint32_t POST_ROOT69_CLR; /**< Post Divider Register, offset: 0xA2A8 */ - __IO uint32_t POST_ROOT69_TOG; /**< Post Divider Register, offset: 0xA2AC */ - __IO uint32_t PRE69; /**< Pre Divider Register, offset: 0xA2B0 */ - __IO uint32_t PRE_ROOT69_SET; /**< Pre Divider Register, offset: 0xA2B4 */ - __IO uint32_t PRE_ROOT69_CLR; /**< Pre Divider Register, offset: 0xA2B8 */ - __IO uint32_t PRE_ROOT69_TOG; /**< Pre Divider Register, offset: 0xA2BC */ - uint8_t RESERVED_141[48]; - __IO uint32_t ACCESS_CTRL69; /**< Access Control Register, offset: 0xA2F0 */ - __IO uint32_t ACCESS_CTRL69_ROOT_SET; /**< Access Control Register, offset: 0xA2F4 */ - __IO uint32_t ACCESS_CTRL69_ROOT_CLR; /**< Access Control Register, offset: 0xA2F8 */ - __IO uint32_t ACCESS_CTRL69_ROOT_TOG; /**< Access Control Register, offset: 0xA2FC */ - __IO uint32_t TARGET_ROOT70; /**< Target Register, offset: 0xA300 */ - __IO uint32_t TARGET_ROOT70_SET; /**< Target Register, offset: 0xA304 */ - __IO uint32_t TARGET_ROOT70_CLR; /**< Target Register, offset: 0xA308 */ - __IO uint32_t TARGET_ROOT70_TOG; /**< Target Register, offset: 0xA30C */ - uint8_t RESERVED_142[16]; - __IO uint32_t POST70; /**< Post Divider Register, offset: 0xA320 */ - __IO uint32_t POST_ROOT70_SET; /**< Post Divider Register, offset: 0xA324 */ - __IO uint32_t POST_ROOT70_CLR; /**< Post Divider Register, offset: 0xA328 */ - __IO uint32_t POST_ROOT70_TOG; /**< Post Divider Register, offset: 0xA32C */ - __IO uint32_t PRE70; /**< Pre Divider Register, offset: 0xA330 */ - __IO uint32_t PRE_ROOT70_SET; /**< Pre Divider Register, offset: 0xA334 */ - __IO uint32_t PRE_ROOT70_CLR; /**< Pre Divider Register, offset: 0xA338 */ - __IO uint32_t PRE_ROOT70_TOG; /**< Pre Divider Register, offset: 0xA33C */ - uint8_t RESERVED_143[48]; - __IO uint32_t ACCESS_CTRL70; /**< Access Control Register, offset: 0xA370 */ - __IO uint32_t ACCESS_CTRL70_ROOT_SET; /**< Access Control Register, offset: 0xA374 */ - __IO uint32_t ACCESS_CTRL70_ROOT_CLR; /**< Access Control Register, offset: 0xA378 */ - __IO uint32_t ACCESS_CTRL70_ROOT_TOG; /**< Access Control Register, offset: 0xA37C */ - __IO uint32_t TARGET_ROOT71; /**< Target Register, offset: 0xA380 */ - __IO uint32_t TARGET_ROOT71_SET; /**< Target Register, offset: 0xA384 */ - __IO uint32_t TARGET_ROOT71_CLR; /**< Target Register, offset: 0xA388 */ - __IO uint32_t TARGET_ROOT71_TOG; /**< Target Register, offset: 0xA38C */ - uint8_t RESERVED_144[16]; - __IO uint32_t POST71; /**< Post Divider Register, offset: 0xA3A0 */ - __IO uint32_t POST_ROOT71_SET; /**< Post Divider Register, offset: 0xA3A4 */ - __IO uint32_t POST_ROOT71_CLR; /**< Post Divider Register, offset: 0xA3A8 */ - __IO uint32_t POST_ROOT71_TOG; /**< Post Divider Register, offset: 0xA3AC */ - __IO uint32_t PRE71; /**< Pre Divider Register, offset: 0xA3B0 */ - __IO uint32_t PRE_ROOT71_SET; /**< Pre Divider Register, offset: 0xA3B4 */ - __IO uint32_t PRE_ROOT71_CLR; /**< Pre Divider Register, offset: 0xA3B8 */ - __IO uint32_t PRE_ROOT71_TOG; /**< Pre Divider Register, offset: 0xA3BC */ - uint8_t RESERVED_145[48]; - __IO uint32_t ACCESS_CTRL71; /**< Access Control Register, offset: 0xA3F0 */ - __IO uint32_t ACCESS_CTRL71_ROOT_SET; /**< Access Control Register, offset: 0xA3F4 */ - __IO uint32_t ACCESS_CTRL71_ROOT_CLR; /**< Access Control Register, offset: 0xA3F8 */ - __IO uint32_t ACCESS_CTRL71_ROOT_TOG; /**< Access Control Register, offset: 0xA3FC */ - __IO uint32_t TARGET_ROOT72; /**< Target Register, offset: 0xA400 */ - __IO uint32_t TARGET_ROOT72_SET; /**< Target Register, offset: 0xA404 */ - __IO uint32_t TARGET_ROOT72_CLR; /**< Target Register, offset: 0xA408 */ - __IO uint32_t TARGET_ROOT72_TOG; /**< Target Register, offset: 0xA40C */ - uint8_t RESERVED_146[16]; - __IO uint32_t POST72; /**< Post Divider Register, offset: 0xA420 */ - __IO uint32_t POST_ROOT72_SET; /**< Post Divider Register, offset: 0xA424 */ - __IO uint32_t POST_ROOT72_CLR; /**< Post Divider Register, offset: 0xA428 */ - __IO uint32_t POST_ROOT72_TOG; /**< Post Divider Register, offset: 0xA42C */ - __IO uint32_t PRE72; /**< Pre Divider Register, offset: 0xA430 */ - __IO uint32_t PRE_ROOT72_SET; /**< Pre Divider Register, offset: 0xA434 */ - __IO uint32_t PRE_ROOT72_CLR; /**< Pre Divider Register, offset: 0xA438 */ - __IO uint32_t PRE_ROOT72_TOG; /**< Pre Divider Register, offset: 0xA43C */ - uint8_t RESERVED_147[48]; - __IO uint32_t ACCESS_CTRL72; /**< Access Control Register, offset: 0xA470 */ - __IO uint32_t ACCESS_CTRL72_ROOT_SET; /**< Access Control Register, offset: 0xA474 */ - __IO uint32_t ACCESS_CTRL72_ROOT_CLR; /**< Access Control Register, offset: 0xA478 */ - __IO uint32_t ACCESS_CTRL72_ROOT_TOG; /**< Access Control Register, offset: 0xA47C */ - __IO uint32_t TARGET_ROOT73; /**< Target Register, offset: 0xA480 */ - __IO uint32_t TARGET_ROOT73_SET; /**< Target Register, offset: 0xA484 */ - __IO uint32_t TARGET_ROOT73_CLR; /**< Target Register, offset: 0xA488 */ - __IO uint32_t TARGET_ROOT73_TOG; /**< Target Register, offset: 0xA48C */ - uint8_t RESERVED_148[16]; - __IO uint32_t POST73; /**< Post Divider Register, offset: 0xA4A0 */ - __IO uint32_t POST_ROOT73_SET; /**< Post Divider Register, offset: 0xA4A4 */ - __IO uint32_t POST_ROOT73_CLR; /**< Post Divider Register, offset: 0xA4A8 */ - __IO uint32_t POST_ROOT73_TOG; /**< Post Divider Register, offset: 0xA4AC */ - __IO uint32_t PRE73; /**< Pre Divider Register, offset: 0xA4B0 */ - __IO uint32_t PRE_ROOT73_SET; /**< Pre Divider Register, offset: 0xA4B4 */ - __IO uint32_t PRE_ROOT73_CLR; /**< Pre Divider Register, offset: 0xA4B8 */ - __IO uint32_t PRE_ROOT73_TOG; /**< Pre Divider Register, offset: 0xA4BC */ - uint8_t RESERVED_149[48]; - __IO uint32_t ACCESS_CTRL73; /**< Access Control Register, offset: 0xA4F0 */ - __IO uint32_t ACCESS_CTRL73_ROOT_SET; /**< Access Control Register, offset: 0xA4F4 */ - __IO uint32_t ACCESS_CTRL73_ROOT_CLR; /**< Access Control Register, offset: 0xA4F8 */ - __IO uint32_t ACCESS_CTRL73_ROOT_TOG; /**< Access Control Register, offset: 0xA4FC */ - __IO uint32_t TARGET_ROOT74; /**< Target Register, offset: 0xA500 */ - __IO uint32_t TARGET_ROOT74_SET; /**< Target Register, offset: 0xA504 */ - __IO uint32_t TARGET_ROOT74_CLR; /**< Target Register, offset: 0xA508 */ - __IO uint32_t TARGET_ROOT74_TOG; /**< Target Register, offset: 0xA50C */ - uint8_t RESERVED_150[16]; - __IO uint32_t POST74; /**< Post Divider Register, offset: 0xA520 */ - __IO uint32_t POST_ROOT74_SET; /**< Post Divider Register, offset: 0xA524 */ - __IO uint32_t POST_ROOT74_CLR; /**< Post Divider Register, offset: 0xA528 */ - __IO uint32_t POST_ROOT74_TOG; /**< Post Divider Register, offset: 0xA52C */ - __IO uint32_t PRE74; /**< Pre Divider Register, offset: 0xA530 */ - __IO uint32_t PRE_ROOT74_SET; /**< Pre Divider Register, offset: 0xA534 */ - __IO uint32_t PRE_ROOT74_CLR; /**< Pre Divider Register, offset: 0xA538 */ - __IO uint32_t PRE_ROOT74_TOG; /**< Pre Divider Register, offset: 0xA53C */ - uint8_t RESERVED_151[48]; - __IO uint32_t ACCESS_CTRL74; /**< Access Control Register, offset: 0xA570 */ - __IO uint32_t ACCESS_CTRL74_ROOT_SET; /**< Access Control Register, offset: 0xA574 */ - __IO uint32_t ACCESS_CTRL74_ROOT_CLR; /**< Access Control Register, offset: 0xA578 */ - __IO uint32_t ACCESS_CTRL74_ROOT_TOG; /**< Access Control Register, offset: 0xA57C */ - __IO uint32_t TARGET_ROOT75; /**< Target Register, offset: 0xA580 */ - __IO uint32_t TARGET_ROOT75_SET; /**< Target Register, offset: 0xA584 */ - __IO uint32_t TARGET_ROOT75_CLR; /**< Target Register, offset: 0xA588 */ - __IO uint32_t TARGET_ROOT75_TOG; /**< Target Register, offset: 0xA58C */ - uint8_t RESERVED_152[16]; - __IO uint32_t POST75; /**< Post Divider Register, offset: 0xA5A0 */ - __IO uint32_t POST_ROOT75_SET; /**< Post Divider Register, offset: 0xA5A4 */ - __IO uint32_t POST_ROOT75_CLR; /**< Post Divider Register, offset: 0xA5A8 */ - __IO uint32_t POST_ROOT75_TOG; /**< Post Divider Register, offset: 0xA5AC */ - __IO uint32_t PRE75; /**< Pre Divider Register, offset: 0xA5B0 */ - __IO uint32_t PRE_ROOT75_SET; /**< Pre Divider Register, offset: 0xA5B4 */ - __IO uint32_t PRE_ROOT75_CLR; /**< Pre Divider Register, offset: 0xA5B8 */ - __IO uint32_t PRE_ROOT75_TOG; /**< Pre Divider Register, offset: 0xA5BC */ - uint8_t RESERVED_153[48]; - __IO uint32_t ACCESS_CTRL75; /**< Access Control Register, offset: 0xA5F0 */ - __IO uint32_t ACCESS_CTRL75_ROOT_SET; /**< Access Control Register, offset: 0xA5F4 */ - __IO uint32_t ACCESS_CTRL75_ROOT_CLR; /**< Access Control Register, offset: 0xA5F8 */ - __IO uint32_t ACCESS_CTRL75_ROOT_TOG; /**< Access Control Register, offset: 0xA5FC */ - __IO uint32_t TARGET_ROOT76; /**< Target Register, offset: 0xA600 */ - __IO uint32_t TARGET_ROOT76_SET; /**< Target Register, offset: 0xA604 */ - __IO uint32_t TARGET_ROOT76_CLR; /**< Target Register, offset: 0xA608 */ - __IO uint32_t TARGET_ROOT76_TOG; /**< Target Register, offset: 0xA60C */ - uint8_t RESERVED_154[16]; - __IO uint32_t POST76; /**< Post Divider Register, offset: 0xA620 */ - __IO uint32_t POST_ROOT76_SET; /**< Post Divider Register, offset: 0xA624 */ - __IO uint32_t POST_ROOT76_CLR; /**< Post Divider Register, offset: 0xA628 */ - __IO uint32_t POST_ROOT76_TOG; /**< Post Divider Register, offset: 0xA62C */ - __IO uint32_t PRE76; /**< Pre Divider Register, offset: 0xA630 */ - __IO uint32_t PRE_ROOT76_SET; /**< Pre Divider Register, offset: 0xA634 */ - __IO uint32_t PRE_ROOT76_CLR; /**< Pre Divider Register, offset: 0xA638 */ - __IO uint32_t PRE_ROOT76_TOG; /**< Pre Divider Register, offset: 0xA63C */ - uint8_t RESERVED_155[48]; - __IO uint32_t ACCESS_CTRL76; /**< Access Control Register, offset: 0xA670 */ - __IO uint32_t ACCESS_CTRL76_ROOT_SET; /**< Access Control Register, offset: 0xA674 */ - __IO uint32_t ACCESS_CTRL76_ROOT_CLR; /**< Access Control Register, offset: 0xA678 */ - __IO uint32_t ACCESS_CTRL76_ROOT_TOG; /**< Access Control Register, offset: 0xA67C */ - __IO uint32_t TARGET_ROOT77; /**< Target Register, offset: 0xA680 */ - __IO uint32_t TARGET_ROOT77_SET; /**< Target Register, offset: 0xA684 */ - __IO uint32_t TARGET_ROOT77_CLR; /**< Target Register, offset: 0xA688 */ - __IO uint32_t TARGET_ROOT77_TOG; /**< Target Register, offset: 0xA68C */ - uint8_t RESERVED_156[16]; - __IO uint32_t POST77; /**< Post Divider Register, offset: 0xA6A0 */ - __IO uint32_t POST_ROOT77_SET; /**< Post Divider Register, offset: 0xA6A4 */ - __IO uint32_t POST_ROOT77_CLR; /**< Post Divider Register, offset: 0xA6A8 */ - __IO uint32_t POST_ROOT77_TOG; /**< Post Divider Register, offset: 0xA6AC */ - __IO uint32_t PRE77; /**< Pre Divider Register, offset: 0xA6B0 */ - __IO uint32_t PRE_ROOT77_SET; /**< Pre Divider Register, offset: 0xA6B4 */ - __IO uint32_t PRE_ROOT77_CLR; /**< Pre Divider Register, offset: 0xA6B8 */ - __IO uint32_t PRE_ROOT77_TOG; /**< Pre Divider Register, offset: 0xA6BC */ - uint8_t RESERVED_157[48]; - __IO uint32_t ACCESS_CTRL77; /**< Access Control Register, offset: 0xA6F0 */ - __IO uint32_t ACCESS_CTRL77_ROOT_SET; /**< Access Control Register, offset: 0xA6F4 */ - __IO uint32_t ACCESS_CTRL77_ROOT_CLR; /**< Access Control Register, offset: 0xA6F8 */ - __IO uint32_t ACCESS_CTRL77_ROOT_TOG; /**< Access Control Register, offset: 0xA6FC */ - __IO uint32_t TARGET_ROOT78; /**< Target Register, offset: 0xA700 */ - __IO uint32_t TARGET_ROOT78_SET; /**< Target Register, offset: 0xA704 */ - __IO uint32_t TARGET_ROOT78_CLR; /**< Target Register, offset: 0xA708 */ - __IO uint32_t TARGET_ROOT78_TOG; /**< Target Register, offset: 0xA70C */ - uint8_t RESERVED_158[16]; - __IO uint32_t POST78; /**< Post Divider Register, offset: 0xA720 */ - __IO uint32_t POST_ROOT78_SET; /**< Post Divider Register, offset: 0xA724 */ - __IO uint32_t POST_ROOT78_CLR; /**< Post Divider Register, offset: 0xA728 */ - __IO uint32_t POST_ROOT78_TOG; /**< Post Divider Register, offset: 0xA72C */ - __IO uint32_t PRE78; /**< Pre Divider Register, offset: 0xA730 */ - __IO uint32_t PRE_ROOT78_SET; /**< Pre Divider Register, offset: 0xA734 */ - __IO uint32_t PRE_ROOT78_CLR; /**< Pre Divider Register, offset: 0xA738 */ - __IO uint32_t PRE_ROOT78_TOG; /**< Pre Divider Register, offset: 0xA73C */ - uint8_t RESERVED_159[48]; - __IO uint32_t ACCESS_CTRL78; /**< Access Control Register, offset: 0xA770 */ - __IO uint32_t ACCESS_CTRL78_ROOT_SET; /**< Access Control Register, offset: 0xA774 */ - __IO uint32_t ACCESS_CTRL78_ROOT_CLR; /**< Access Control Register, offset: 0xA778 */ - __IO uint32_t ACCESS_CTRL78_ROOT_TOG; /**< Access Control Register, offset: 0xA77C */ - __IO uint32_t TARGET_ROOT79; /**< Target Register, offset: 0xA780 */ - __IO uint32_t TARGET_ROOT79_SET; /**< Target Register, offset: 0xA784 */ - __IO uint32_t TARGET_ROOT79_CLR; /**< Target Register, offset: 0xA788 */ - __IO uint32_t TARGET_ROOT79_TOG; /**< Target Register, offset: 0xA78C */ - uint8_t RESERVED_160[16]; - __IO uint32_t POST79; /**< Post Divider Register, offset: 0xA7A0 */ - __IO uint32_t POST_ROOT79_SET; /**< Post Divider Register, offset: 0xA7A4 */ - __IO uint32_t POST_ROOT79_CLR; /**< Post Divider Register, offset: 0xA7A8 */ - __IO uint32_t POST_ROOT79_TOG; /**< Post Divider Register, offset: 0xA7AC */ - __IO uint32_t PRE79; /**< Pre Divider Register, offset: 0xA7B0 */ - __IO uint32_t PRE_ROOT79_SET; /**< Pre Divider Register, offset: 0xA7B4 */ - __IO uint32_t PRE_ROOT79_CLR; /**< Pre Divider Register, offset: 0xA7B8 */ - __IO uint32_t PRE_ROOT79_TOG; /**< Pre Divider Register, offset: 0xA7BC */ - uint8_t RESERVED_161[48]; - __IO uint32_t ACCESS_CTRL79; /**< Access Control Register, offset: 0xA7F0 */ - __IO uint32_t ACCESS_CTRL79_ROOT_SET; /**< Access Control Register, offset: 0xA7F4 */ - __IO uint32_t ACCESS_CTRL79_ROOT_CLR; /**< Access Control Register, offset: 0xA7F8 */ - __IO uint32_t ACCESS_CTRL79_ROOT_TOG; /**< Access Control Register, offset: 0xA7FC */ - __IO uint32_t TARGET_ROOT80; /**< Target Register, offset: 0xA800 */ - __IO uint32_t TARGET_ROOT80_SET; /**< Target Register, offset: 0xA804 */ - __IO uint32_t TARGET_ROOT80_CLR; /**< Target Register, offset: 0xA808 */ - __IO uint32_t TARGET_ROOT80_TOG; /**< Target Register, offset: 0xA80C */ - uint8_t RESERVED_162[16]; - __IO uint32_t POST80; /**< Post Divider Register, offset: 0xA820 */ - __IO uint32_t POST_ROOT80_SET; /**< Post Divider Register, offset: 0xA824 */ - __IO uint32_t POST_ROOT80_CLR; /**< Post Divider Register, offset: 0xA828 */ - __IO uint32_t POST_ROOT80_TOG; /**< Post Divider Register, offset: 0xA82C */ - __IO uint32_t PRE80; /**< Pre Divider Register, offset: 0xA830 */ - __IO uint32_t PRE_ROOT80_SET; /**< Pre Divider Register, offset: 0xA834 */ - __IO uint32_t PRE_ROOT80_CLR; /**< Pre Divider Register, offset: 0xA838 */ - __IO uint32_t PRE_ROOT80_TOG; /**< Pre Divider Register, offset: 0xA83C */ - uint8_t RESERVED_163[48]; - __IO uint32_t ACCESS_CTRL80; /**< Access Control Register, offset: 0xA870 */ - __IO uint32_t ACCESS_CTRL80_ROOT_SET; /**< Access Control Register, offset: 0xA874 */ - __IO uint32_t ACCESS_CTRL80_ROOT_CLR; /**< Access Control Register, offset: 0xA878 */ - __IO uint32_t ACCESS_CTRL80_ROOT_TOG; /**< Access Control Register, offset: 0xA87C */ - __IO uint32_t TARGET_ROOT81; /**< Target Register, offset: 0xA880 */ - __IO uint32_t TARGET_ROOT81_SET; /**< Target Register, offset: 0xA884 */ - __IO uint32_t TARGET_ROOT81_CLR; /**< Target Register, offset: 0xA888 */ - __IO uint32_t TARGET_ROOT81_TOG; /**< Target Register, offset: 0xA88C */ - uint8_t RESERVED_164[16]; - __IO uint32_t POST81; /**< Post Divider Register, offset: 0xA8A0 */ - __IO uint32_t POST_ROOT81_SET; /**< Post Divider Register, offset: 0xA8A4 */ - __IO uint32_t POST_ROOT81_CLR; /**< Post Divider Register, offset: 0xA8A8 */ - __IO uint32_t POST_ROOT81_TOG; /**< Post Divider Register, offset: 0xA8AC */ - __IO uint32_t PRE81; /**< Pre Divider Register, offset: 0xA8B0 */ - __IO uint32_t PRE_ROOT81_SET; /**< Pre Divider Register, offset: 0xA8B4 */ - __IO uint32_t PRE_ROOT81_CLR; /**< Pre Divider Register, offset: 0xA8B8 */ - __IO uint32_t PRE_ROOT81_TOG; /**< Pre Divider Register, offset: 0xA8BC */ - uint8_t RESERVED_165[48]; - __IO uint32_t ACCESS_CTRL81; /**< Access Control Register, offset: 0xA8F0 */ - __IO uint32_t ACCESS_CTRL81_ROOT_SET; /**< Access Control Register, offset: 0xA8F4 */ - __IO uint32_t ACCESS_CTRL81_ROOT_CLR; /**< Access Control Register, offset: 0xA8F8 */ - __IO uint32_t ACCESS_CTRL81_ROOT_TOG; /**< Access Control Register, offset: 0xA8FC */ - __IO uint32_t TARGET_ROOT82; /**< Target Register, offset: 0xA900 */ - __IO uint32_t TARGET_ROOT82_SET; /**< Target Register, offset: 0xA904 */ - __IO uint32_t TARGET_ROOT82_CLR; /**< Target Register, offset: 0xA908 */ - __IO uint32_t TARGET_ROOT82_TOG; /**< Target Register, offset: 0xA90C */ - uint8_t RESERVED_166[16]; - __IO uint32_t POST82; /**< Post Divider Register, offset: 0xA920 */ - __IO uint32_t POST_ROOT82_SET; /**< Post Divider Register, offset: 0xA924 */ - __IO uint32_t POST_ROOT82_CLR; /**< Post Divider Register, offset: 0xA928 */ - __IO uint32_t POST_ROOT82_TOG; /**< Post Divider Register, offset: 0xA92C */ - __IO uint32_t PRE82; /**< Pre Divider Register, offset: 0xA930 */ - __IO uint32_t PRE_ROOT82_SET; /**< Pre Divider Register, offset: 0xA934 */ - __IO uint32_t PRE_ROOT82_CLR; /**< Pre Divider Register, offset: 0xA938 */ - __IO uint32_t PRE_ROOT82_TOG; /**< Pre Divider Register, offset: 0xA93C */ - uint8_t RESERVED_167[48]; - __IO uint32_t ACCESS_CTRL82; /**< Access Control Register, offset: 0xA970 */ - __IO uint32_t ACCESS_CTRL82_ROOT_SET; /**< Access Control Register, offset: 0xA974 */ - __IO uint32_t ACCESS_CTRL82_ROOT_CLR; /**< Access Control Register, offset: 0xA978 */ - __IO uint32_t ACCESS_CTRL82_ROOT_TOG; /**< Access Control Register, offset: 0xA97C */ - __IO uint32_t TARGET_ROOT83; /**< Target Register, offset: 0xA980 */ - __IO uint32_t TARGET_ROOT83_SET; /**< Target Register, offset: 0xA984 */ - __IO uint32_t TARGET_ROOT83_CLR; /**< Target Register, offset: 0xA988 */ - __IO uint32_t TARGET_ROOT83_TOG; /**< Target Register, offset: 0xA98C */ - uint8_t RESERVED_168[16]; - __IO uint32_t POST83; /**< Post Divider Register, offset: 0xA9A0 */ - __IO uint32_t POST_ROOT83_SET; /**< Post Divider Register, offset: 0xA9A4 */ - __IO uint32_t POST_ROOT83_CLR; /**< Post Divider Register, offset: 0xA9A8 */ - __IO uint32_t POST_ROOT83_TOG; /**< Post Divider Register, offset: 0xA9AC */ - __IO uint32_t PRE83; /**< Pre Divider Register, offset: 0xA9B0 */ - __IO uint32_t PRE_ROOT83_SET; /**< Pre Divider Register, offset: 0xA9B4 */ - __IO uint32_t PRE_ROOT83_CLR; /**< Pre Divider Register, offset: 0xA9B8 */ - __IO uint32_t PRE_ROOT83_TOG; /**< Pre Divider Register, offset: 0xA9BC */ - uint8_t RESERVED_169[48]; - __IO uint32_t ACCESS_CTRL83; /**< Access Control Register, offset: 0xA9F0 */ - __IO uint32_t ACCESS_CTRL83_ROOT_SET; /**< Access Control Register, offset: 0xA9F4 */ - __IO uint32_t ACCESS_CTRL83_ROOT_CLR; /**< Access Control Register, offset: 0xA9F8 */ - __IO uint32_t ACCESS_CTRL83_ROOT_TOG; /**< Access Control Register, offset: 0xA9FC */ - __IO uint32_t TARGET_ROOT84; /**< Target Register, offset: 0xAA00 */ - __IO uint32_t TARGET_ROOT84_SET; /**< Target Register, offset: 0xAA04 */ - __IO uint32_t TARGET_ROOT84_CLR; /**< Target Register, offset: 0xAA08 */ - __IO uint32_t TARGET_ROOT84_TOG; /**< Target Register, offset: 0xAA0C */ - uint8_t RESERVED_170[16]; - __IO uint32_t POST84; /**< Post Divider Register, offset: 0xAA20 */ - __IO uint32_t POST_ROOT84_SET; /**< Post Divider Register, offset: 0xAA24 */ - __IO uint32_t POST_ROOT84_CLR; /**< Post Divider Register, offset: 0xAA28 */ - __IO uint32_t POST_ROOT84_TOG; /**< Post Divider Register, offset: 0xAA2C */ - __IO uint32_t PRE84; /**< Pre Divider Register, offset: 0xAA30 */ - __IO uint32_t PRE_ROOT84_SET; /**< Pre Divider Register, offset: 0xAA34 */ - __IO uint32_t PRE_ROOT84_CLR; /**< Pre Divider Register, offset: 0xAA38 */ - __IO uint32_t PRE_ROOT84_TOG; /**< Pre Divider Register, offset: 0xAA3C */ - uint8_t RESERVED_171[48]; - __IO uint32_t ACCESS_CTRL84; /**< Access Control Register, offset: 0xAA70 */ - __IO uint32_t ACCESS_CTRL84_ROOT_SET; /**< Access Control Register, offset: 0xAA74 */ - __IO uint32_t ACCESS_CTRL84_ROOT_CLR; /**< Access Control Register, offset: 0xAA78 */ - __IO uint32_t ACCESS_CTRL84_ROOT_TOG; /**< Access Control Register, offset: 0xAA7C */ - __IO uint32_t TARGET_ROOT85; /**< Target Register, offset: 0xAA80 */ - __IO uint32_t TARGET_ROOT85_SET; /**< Target Register, offset: 0xAA84 */ - __IO uint32_t TARGET_ROOT85_CLR; /**< Target Register, offset: 0xAA88 */ - __IO uint32_t TARGET_ROOT85_TOG; /**< Target Register, offset: 0xAA8C */ - uint8_t RESERVED_172[16]; - __IO uint32_t POST85; /**< Post Divider Register, offset: 0xAAA0 */ - __IO uint32_t POST_ROOT85_SET; /**< Post Divider Register, offset: 0xAAA4 */ - __IO uint32_t POST_ROOT85_CLR; /**< Post Divider Register, offset: 0xAAA8 */ - __IO uint32_t POST_ROOT85_TOG; /**< Post Divider Register, offset: 0xAAAC */ - __IO uint32_t PRE85; /**< Pre Divider Register, offset: 0xAAB0 */ - __IO uint32_t PRE_ROOT85_SET; /**< Pre Divider Register, offset: 0xAAB4 */ - __IO uint32_t PRE_ROOT85_CLR; /**< Pre Divider Register, offset: 0xAAB8 */ - __IO uint32_t PRE_ROOT85_TOG; /**< Pre Divider Register, offset: 0xAABC */ - uint8_t RESERVED_173[48]; - __IO uint32_t ACCESS_CTRL85; /**< Access Control Register, offset: 0xAAF0 */ - __IO uint32_t ACCESS_CTRL85_ROOT_SET; /**< Access Control Register, offset: 0xAAF4 */ - __IO uint32_t ACCESS_CTRL85_ROOT_CLR; /**< Access Control Register, offset: 0xAAF8 */ - __IO uint32_t ACCESS_CTRL85_ROOT_TOG; /**< Access Control Register, offset: 0xAAFC */ - __IO uint32_t TARGET_ROOT86; /**< Target Register, offset: 0xAB00 */ - __IO uint32_t TARGET_ROOT86_SET; /**< Target Register, offset: 0xAB04 */ - __IO uint32_t TARGET_ROOT86_CLR; /**< Target Register, offset: 0xAB08 */ - __IO uint32_t TARGET_ROOT86_TOG; /**< Target Register, offset: 0xAB0C */ - uint8_t RESERVED_174[16]; - __IO uint32_t POST86; /**< Post Divider Register, offset: 0xAB20 */ - __IO uint32_t POST_ROOT86_SET; /**< Post Divider Register, offset: 0xAB24 */ - __IO uint32_t POST_ROOT86_CLR; /**< Post Divider Register, offset: 0xAB28 */ - __IO uint32_t POST_ROOT86_TOG; /**< Post Divider Register, offset: 0xAB2C */ - __IO uint32_t PRE86; /**< Pre Divider Register, offset: 0xAB30 */ - __IO uint32_t PRE_ROOT86_SET; /**< Pre Divider Register, offset: 0xAB34 */ - __IO uint32_t PRE_ROOT86_CLR; /**< Pre Divider Register, offset: 0xAB38 */ - __IO uint32_t PRE_ROOT86_TOG; /**< Pre Divider Register, offset: 0xAB3C */ - uint8_t RESERVED_175[48]; - __IO uint32_t ACCESS_CTRL86; /**< Access Control Register, offset: 0xAB70 */ - __IO uint32_t ACCESS_CTRL86_ROOT_SET; /**< Access Control Register, offset: 0xAB74 */ - __IO uint32_t ACCESS_CTRL86_ROOT_CLR; /**< Access Control Register, offset: 0xAB78 */ - __IO uint32_t ACCESS_CTRL86_ROOT_TOG; /**< Access Control Register, offset: 0xAB7C */ - __IO uint32_t TARGET_ROOT87; /**< Target Register, offset: 0xAB80 */ - __IO uint32_t TARGET_ROOT87_SET; /**< Target Register, offset: 0xAB84 */ - __IO uint32_t TARGET_ROOT87_CLR; /**< Target Register, offset: 0xAB88 */ - __IO uint32_t TARGET_ROOT87_TOG; /**< Target Register, offset: 0xAB8C */ - uint8_t RESERVED_176[16]; - __IO uint32_t POST87; /**< Post Divider Register, offset: 0xABA0 */ - __IO uint32_t POST_ROOT87_SET; /**< Post Divider Register, offset: 0xABA4 */ - __IO uint32_t POST_ROOT87_CLR; /**< Post Divider Register, offset: 0xABA8 */ - __IO uint32_t POST_ROOT87_TOG; /**< Post Divider Register, offset: 0xABAC */ - __IO uint32_t PRE87; /**< Pre Divider Register, offset: 0xABB0 */ - __IO uint32_t PRE_ROOT87_SET; /**< Pre Divider Register, offset: 0xABB4 */ - __IO uint32_t PRE_ROOT87_CLR; /**< Pre Divider Register, offset: 0xABB8 */ - __IO uint32_t PRE_ROOT87_TOG; /**< Pre Divider Register, offset: 0xABBC */ - uint8_t RESERVED_177[48]; - __IO uint32_t ACCESS_CTRL87; /**< Access Control Register, offset: 0xABF0 */ - __IO uint32_t ACCESS_CTRL87_ROOT_SET; /**< Access Control Register, offset: 0xABF4 */ - __IO uint32_t ACCESS_CTRL87_ROOT_CLR; /**< Access Control Register, offset: 0xABF8 */ - __IO uint32_t ACCESS_CTRL87_ROOT_TOG; /**< Access Control Register, offset: 0xABFC */ - __IO uint32_t TARGET_ROOT88; /**< Target Register, offset: 0xAC00 */ - __IO uint32_t TARGET_ROOT88_SET; /**< Target Register, offset: 0xAC04 */ - __IO uint32_t TARGET_ROOT88_CLR; /**< Target Register, offset: 0xAC08 */ - __IO uint32_t TARGET_ROOT88_TOG; /**< Target Register, offset: 0xAC0C */ - uint8_t RESERVED_178[16]; - __IO uint32_t POST88; /**< Post Divider Register, offset: 0xAC20 */ - __IO uint32_t POST_ROOT88_SET; /**< Post Divider Register, offset: 0xAC24 */ - __IO uint32_t POST_ROOT88_CLR; /**< Post Divider Register, offset: 0xAC28 */ - __IO uint32_t POST_ROOT88_TOG; /**< Post Divider Register, offset: 0xAC2C */ - __IO uint32_t PRE88; /**< Pre Divider Register, offset: 0xAC30 */ - __IO uint32_t PRE_ROOT88_SET; /**< Pre Divider Register, offset: 0xAC34 */ - __IO uint32_t PRE_ROOT88_CLR; /**< Pre Divider Register, offset: 0xAC38 */ - __IO uint32_t PRE_ROOT88_TOG; /**< Pre Divider Register, offset: 0xAC3C */ - uint8_t RESERVED_179[48]; - __IO uint32_t ACCESS_CTRL88; /**< Access Control Register, offset: 0xAC70 */ - __IO uint32_t ACCESS_CTRL88_ROOT_SET; /**< Access Control Register, offset: 0xAC74 */ - __IO uint32_t ACCESS_CTRL88_ROOT_CLR; /**< Access Control Register, offset: 0xAC78 */ - __IO uint32_t ACCESS_CTRL88_ROOT_TOG; /**< Access Control Register, offset: 0xAC7C */ - __IO uint32_t TARGET_ROOT89; /**< Target Register, offset: 0xAC80 */ - __IO uint32_t TARGET_ROOT89_SET; /**< Target Register, offset: 0xAC84 */ - __IO uint32_t TARGET_ROOT89_CLR; /**< Target Register, offset: 0xAC88 */ - __IO uint32_t TARGET_ROOT89_TOG; /**< Target Register, offset: 0xAC8C */ - uint8_t RESERVED_180[16]; - __IO uint32_t POST89; /**< Post Divider Register, offset: 0xACA0 */ - __IO uint32_t POST_ROOT89_SET; /**< Post Divider Register, offset: 0xACA4 */ - __IO uint32_t POST_ROOT89_CLR; /**< Post Divider Register, offset: 0xACA8 */ - __IO uint32_t POST_ROOT89_TOG; /**< Post Divider Register, offset: 0xACAC */ - __IO uint32_t PRE89; /**< Pre Divider Register, offset: 0xACB0 */ - __IO uint32_t PRE_ROOT89_SET; /**< Pre Divider Register, offset: 0xACB4 */ - __IO uint32_t PRE_ROOT89_CLR; /**< Pre Divider Register, offset: 0xACB8 */ - __IO uint32_t PRE_ROOT89_TOG; /**< Pre Divider Register, offset: 0xACBC */ - uint8_t RESERVED_181[48]; - __IO uint32_t ACCESS_CTRL89; /**< Access Control Register, offset: 0xACF0 */ - __IO uint32_t ACCESS_CTRL89_ROOT_SET; /**< Access Control Register, offset: 0xACF4 */ - __IO uint32_t ACCESS_CTRL89_ROOT_CLR; /**< Access Control Register, offset: 0xACF8 */ - __IO uint32_t ACCESS_CTRL89_ROOT_TOG; /**< Access Control Register, offset: 0xACFC */ - __IO uint32_t TARGET_ROOT90; /**< Target Register, offset: 0xAD00 */ - __IO uint32_t TARGET_ROOT90_SET; /**< Target Register, offset: 0xAD04 */ - __IO uint32_t TARGET_ROOT90_CLR; /**< Target Register, offset: 0xAD08 */ - __IO uint32_t TARGET_ROOT90_TOG; /**< Target Register, offset: 0xAD0C */ - uint8_t RESERVED_182[16]; - __IO uint32_t POST90; /**< Post Divider Register, offset: 0xAD20 */ - __IO uint32_t POST_ROOT90_SET; /**< Post Divider Register, offset: 0xAD24 */ - __IO uint32_t POST_ROOT90_CLR; /**< Post Divider Register, offset: 0xAD28 */ - __IO uint32_t POST_ROOT90_TOG; /**< Post Divider Register, offset: 0xAD2C */ - __IO uint32_t PRE90; /**< Pre Divider Register, offset: 0xAD30 */ - __IO uint32_t PRE_ROOT90_SET; /**< Pre Divider Register, offset: 0xAD34 */ - __IO uint32_t PRE_ROOT90_CLR; /**< Pre Divider Register, offset: 0xAD38 */ - __IO uint32_t PRE_ROOT90_TOG; /**< Pre Divider Register, offset: 0xAD3C */ - uint8_t RESERVED_183[48]; - __IO uint32_t ACCESS_CTRL90; /**< Access Control Register, offset: 0xAD70 */ - __IO uint32_t ACCESS_CTRL90_ROOT_SET; /**< Access Control Register, offset: 0xAD74 */ - __IO uint32_t ACCESS_CTRL90_ROOT_CLR; /**< Access Control Register, offset: 0xAD78 */ - __IO uint32_t ACCESS_CTRL90_ROOT_TOG; /**< Access Control Register, offset: 0xAD7C */ - __IO uint32_t TARGET_ROOT91; /**< Target Register, offset: 0xAD80 */ - __IO uint32_t TARGET_ROOT91_SET; /**< Target Register, offset: 0xAD84 */ - __IO uint32_t TARGET_ROOT91_CLR; /**< Target Register, offset: 0xAD88 */ - __IO uint32_t TARGET_ROOT91_TOG; /**< Target Register, offset: 0xAD8C */ - uint8_t RESERVED_184[16]; - __IO uint32_t POST91; /**< Post Divider Register, offset: 0xADA0 */ - __IO uint32_t POST_ROOT91_SET; /**< Post Divider Register, offset: 0xADA4 */ - __IO uint32_t POST_ROOT91_CLR; /**< Post Divider Register, offset: 0xADA8 */ - __IO uint32_t POST_ROOT91_TOG; /**< Post Divider Register, offset: 0xADAC */ - __IO uint32_t PRE91; /**< Pre Divider Register, offset: 0xADB0 */ - __IO uint32_t PRE_ROOT91_SET; /**< Pre Divider Register, offset: 0xADB4 */ - __IO uint32_t PRE_ROOT91_CLR; /**< Pre Divider Register, offset: 0xADB8 */ - __IO uint32_t PRE_ROOT91_TOG; /**< Pre Divider Register, offset: 0xADBC */ - uint8_t RESERVED_185[48]; - __IO uint32_t ACCESS_CTRL91; /**< Access Control Register, offset: 0xADF0 */ - __IO uint32_t ACCESS_CTRL91_ROOT_SET; /**< Access Control Register, offset: 0xADF4 */ - __IO uint32_t ACCESS_CTRL91_ROOT_CLR; /**< Access Control Register, offset: 0xADF8 */ - __IO uint32_t ACCESS_CTRL91_ROOT_TOG; /**< Access Control Register, offset: 0xADFC */ - __IO uint32_t TARGET_ROOT92; /**< Target Register, offset: 0xAE00 */ - __IO uint32_t TARGET_ROOT92_SET; /**< Target Register, offset: 0xAE04 */ - __IO uint32_t TARGET_ROOT92_CLR; /**< Target Register, offset: 0xAE08 */ - __IO uint32_t TARGET_ROOT92_TOG; /**< Target Register, offset: 0xAE0C */ - uint8_t RESERVED_186[16]; - __IO uint32_t POST92; /**< Post Divider Register, offset: 0xAE20 */ - __IO uint32_t POST_ROOT92_SET; /**< Post Divider Register, offset: 0xAE24 */ - __IO uint32_t POST_ROOT92_CLR; /**< Post Divider Register, offset: 0xAE28 */ - __IO uint32_t POST_ROOT92_TOG; /**< Post Divider Register, offset: 0xAE2C */ - __IO uint32_t PRE92; /**< Pre Divider Register, offset: 0xAE30 */ - __IO uint32_t PRE_ROOT92_SET; /**< Pre Divider Register, offset: 0xAE34 */ - __IO uint32_t PRE_ROOT92_CLR; /**< Pre Divider Register, offset: 0xAE38 */ - __IO uint32_t PRE_ROOT92_TOG; /**< Pre Divider Register, offset: 0xAE3C */ - uint8_t RESERVED_187[48]; - __IO uint32_t ACCESS_CTRL92; /**< Access Control Register, offset: 0xAE70 */ - __IO uint32_t ACCESS_CTRL92_ROOT_SET; /**< Access Control Register, offset: 0xAE74 */ - __IO uint32_t ACCESS_CTRL92_ROOT_CLR; /**< Access Control Register, offset: 0xAE78 */ - __IO uint32_t ACCESS_CTRL92_ROOT_TOG; /**< Access Control Register, offset: 0xAE7C */ - __IO uint32_t TARGET_ROOT93; /**< Target Register, offset: 0xAE80 */ - __IO uint32_t TARGET_ROOT93_SET; /**< Target Register, offset: 0xAE84 */ - __IO uint32_t TARGET_ROOT93_CLR; /**< Target Register, offset: 0xAE88 */ - __IO uint32_t TARGET_ROOT93_TOG; /**< Target Register, offset: 0xAE8C */ - uint8_t RESERVED_188[16]; - __IO uint32_t POST93; /**< Post Divider Register, offset: 0xAEA0 */ - __IO uint32_t POST_ROOT93_SET; /**< Post Divider Register, offset: 0xAEA4 */ - __IO uint32_t POST_ROOT93_CLR; /**< Post Divider Register, offset: 0xAEA8 */ - __IO uint32_t POST_ROOT93_TOG; /**< Post Divider Register, offset: 0xAEAC */ - __IO uint32_t PRE93; /**< Pre Divider Register, offset: 0xAEB0 */ - __IO uint32_t PRE_ROOT93_SET; /**< Pre Divider Register, offset: 0xAEB4 */ - __IO uint32_t PRE_ROOT93_CLR; /**< Pre Divider Register, offset: 0xAEB8 */ - __IO uint32_t PRE_ROOT93_TOG; /**< Pre Divider Register, offset: 0xAEBC */ - uint8_t RESERVED_189[48]; - __IO uint32_t ACCESS_CTRL93; /**< Access Control Register, offset: 0xAEF0 */ - __IO uint32_t ACCESS_CTRL93_ROOT_SET; /**< Access Control Register, offset: 0xAEF4 */ - __IO uint32_t ACCESS_CTRL93_ROOT_CLR; /**< Access Control Register, offset: 0xAEF8 */ - __IO uint32_t ACCESS_CTRL93_ROOT_TOG; /**< Access Control Register, offset: 0xAEFC */ - __IO uint32_t TARGET_ROOT94; /**< Target Register, offset: 0xAF00 */ - __IO uint32_t TARGET_ROOT94_SET; /**< Target Register, offset: 0xAF04 */ - __IO uint32_t TARGET_ROOT94_CLR; /**< Target Register, offset: 0xAF08 */ - __IO uint32_t TARGET_ROOT94_TOG; /**< Target Register, offset: 0xAF0C */ - uint8_t RESERVED_190[16]; - __IO uint32_t POST94; /**< Post Divider Register, offset: 0xAF20 */ - __IO uint32_t POST_ROOT94_SET; /**< Post Divider Register, offset: 0xAF24 */ - __IO uint32_t POST_ROOT94_CLR; /**< Post Divider Register, offset: 0xAF28 */ - __IO uint32_t POST_ROOT94_TOG; /**< Post Divider Register, offset: 0xAF2C */ - __IO uint32_t PRE94; /**< Pre Divider Register, offset: 0xAF30 */ - __IO uint32_t PRE_ROOT94_SET; /**< Pre Divider Register, offset: 0xAF34 */ - __IO uint32_t PRE_ROOT94_CLR; /**< Pre Divider Register, offset: 0xAF38 */ - __IO uint32_t PRE_ROOT94_TOG; /**< Pre Divider Register, offset: 0xAF3C */ - uint8_t RESERVED_191[48]; - __IO uint32_t ACCESS_CTRL94; /**< Access Control Register, offset: 0xAF70 */ - __IO uint32_t ACCESS_CTRL94_ROOT_SET; /**< Access Control Register, offset: 0xAF74 */ - __IO uint32_t ACCESS_CTRL94_ROOT_CLR; /**< Access Control Register, offset: 0xAF78 */ - __IO uint32_t ACCESS_CTRL94_ROOT_TOG; /**< Access Control Register, offset: 0xAF7C */ - __IO uint32_t TARGET_ROOT95; /**< Target Register, offset: 0xAF80 */ - __IO uint32_t TARGET_ROOT95_SET; /**< Target Register, offset: 0xAF84 */ - __IO uint32_t TARGET_ROOT95_CLR; /**< Target Register, offset: 0xAF88 */ - __IO uint32_t TARGET_ROOT95_TOG; /**< Target Register, offset: 0xAF8C */ - uint8_t RESERVED_192[16]; - __IO uint32_t POST95; /**< Post Divider Register, offset: 0xAFA0 */ - __IO uint32_t POST_ROOT95_SET; /**< Post Divider Register, offset: 0xAFA4 */ - __IO uint32_t POST_ROOT95_CLR; /**< Post Divider Register, offset: 0xAFA8 */ - __IO uint32_t POST_ROOT95_TOG; /**< Post Divider Register, offset: 0xAFAC */ - __IO uint32_t PRE95; /**< Pre Divider Register, offset: 0xAFB0 */ - __IO uint32_t PRE_ROOT95_SET; /**< Pre Divider Register, offset: 0xAFB4 */ - __IO uint32_t PRE_ROOT95_CLR; /**< Pre Divider Register, offset: 0xAFB8 */ - __IO uint32_t PRE_ROOT95_TOG; /**< Pre Divider Register, offset: 0xAFBC */ - uint8_t RESERVED_193[48]; - __IO uint32_t ACCESS_CTRL95; /**< Access Control Register, offset: 0xAFF0 */ - __IO uint32_t ACCESS_CTRL95_ROOT_SET; /**< Access Control Register, offset: 0xAFF4 */ - __IO uint32_t ACCESS_CTRL95_ROOT_CLR; /**< Access Control Register, offset: 0xAFF8 */ - __IO uint32_t ACCESS_CTRL95_ROOT_TOG; /**< Access Control Register, offset: 0xAFFC */ - __IO uint32_t TARGET_ROOT96; /**< Target Register, offset: 0xB000 */ - __IO uint32_t TARGET_ROOT96_SET; /**< Target Register, offset: 0xB004 */ - __IO uint32_t TARGET_ROOT96_CLR; /**< Target Register, offset: 0xB008 */ - __IO uint32_t TARGET_ROOT96_TOG; /**< Target Register, offset: 0xB00C */ - uint8_t RESERVED_194[16]; - __IO uint32_t POST96; /**< Post Divider Register, offset: 0xB020 */ - __IO uint32_t POST_ROOT96_SET; /**< Post Divider Register, offset: 0xB024 */ - __IO uint32_t POST_ROOT96_CLR; /**< Post Divider Register, offset: 0xB028 */ - __IO uint32_t POST_ROOT96_TOG; /**< Post Divider Register, offset: 0xB02C */ - __IO uint32_t PRE96; /**< Pre Divider Register, offset: 0xB030 */ - __IO uint32_t PRE_ROOT96_SET; /**< Pre Divider Register, offset: 0xB034 */ - __IO uint32_t PRE_ROOT96_CLR; /**< Pre Divider Register, offset: 0xB038 */ - __IO uint32_t PRE_ROOT96_TOG; /**< Pre Divider Register, offset: 0xB03C */ - uint8_t RESERVED_195[48]; - __IO uint32_t ACCESS_CTRL96; /**< Access Control Register, offset: 0xB070 */ - __IO uint32_t ACCESS_CTRL96_ROOT_SET; /**< Access Control Register, offset: 0xB074 */ - __IO uint32_t ACCESS_CTRL96_ROOT_CLR; /**< Access Control Register, offset: 0xB078 */ - __IO uint32_t ACCESS_CTRL96_ROOT_TOG; /**< Access Control Register, offset: 0xB07C */ - __IO uint32_t TARGET_ROOT97; /**< Target Register, offset: 0xB080 */ - __IO uint32_t TARGET_ROOT97_SET; /**< Target Register, offset: 0xB084 */ - __IO uint32_t TARGET_ROOT97_CLR; /**< Target Register, offset: 0xB088 */ - __IO uint32_t TARGET_ROOT97_TOG; /**< Target Register, offset: 0xB08C */ - uint8_t RESERVED_196[16]; - __IO uint32_t POST97; /**< Post Divider Register, offset: 0xB0A0 */ - __IO uint32_t POST_ROOT97_SET; /**< Post Divider Register, offset: 0xB0A4 */ - __IO uint32_t POST_ROOT97_CLR; /**< Post Divider Register, offset: 0xB0A8 */ - __IO uint32_t POST_ROOT97_TOG; /**< Post Divider Register, offset: 0xB0AC */ - __IO uint32_t PRE97; /**< Pre Divider Register, offset: 0xB0B0 */ - __IO uint32_t PRE_ROOT97_SET; /**< Pre Divider Register, offset: 0xB0B4 */ - __IO uint32_t PRE_ROOT97_CLR; /**< Pre Divider Register, offset: 0xB0B8 */ - __IO uint32_t PRE_ROOT97_TOG; /**< Pre Divider Register, offset: 0xB0BC */ - uint8_t RESERVED_197[48]; - __IO uint32_t ACCESS_CTRL97; /**< Access Control Register, offset: 0xB0F0 */ - __IO uint32_t ACCESS_CTRL97_ROOT_SET; /**< Access Control Register, offset: 0xB0F4 */ - __IO uint32_t ACCESS_CTRL97_ROOT_CLR; /**< Access Control Register, offset: 0xB0F8 */ - __IO uint32_t ACCESS_CTRL97_ROOT_TOG; /**< Access Control Register, offset: 0xB0FC */ - __IO uint32_t TARGET_ROOT98; /**< Target Register, offset: 0xB100 */ - __IO uint32_t TARGET_ROOT98_SET; /**< Target Register, offset: 0xB104 */ - __IO uint32_t TARGET_ROOT98_CLR; /**< Target Register, offset: 0xB108 */ - __IO uint32_t TARGET_ROOT98_TOG; /**< Target Register, offset: 0xB10C */ - uint8_t RESERVED_198[16]; - __IO uint32_t POST98; /**< Post Divider Register, offset: 0xB120 */ - __IO uint32_t POST_ROOT98_SET; /**< Post Divider Register, offset: 0xB124 */ - __IO uint32_t POST_ROOT98_CLR; /**< Post Divider Register, offset: 0xB128 */ - __IO uint32_t POST_ROOT98_TOG; /**< Post Divider Register, offset: 0xB12C */ - __IO uint32_t PRE98; /**< Pre Divider Register, offset: 0xB130 */ - __IO uint32_t PRE_ROOT98_SET; /**< Pre Divider Register, offset: 0xB134 */ - __IO uint32_t PRE_ROOT98_CLR; /**< Pre Divider Register, offset: 0xB138 */ - __IO uint32_t PRE_ROOT98_TOG; /**< Pre Divider Register, offset: 0xB13C */ - uint8_t RESERVED_199[48]; - __IO uint32_t ACCESS_CTRL98; /**< Access Control Register, offset: 0xB170 */ - __IO uint32_t ACCESS_CTRL98_ROOT_SET; /**< Access Control Register, offset: 0xB174 */ - __IO uint32_t ACCESS_CTRL98_ROOT_CLR; /**< Access Control Register, offset: 0xB178 */ - __IO uint32_t ACCESS_CTRL98_ROOT_TOG; /**< Access Control Register, offset: 0xB17C */ - __IO uint32_t TARGET_ROOT99; /**< Target Register, offset: 0xB180 */ - __IO uint32_t TARGET_ROOT99_SET; /**< Target Register, offset: 0xB184 */ - __IO uint32_t TARGET_ROOT99_CLR; /**< Target Register, offset: 0xB188 */ - __IO uint32_t TARGET_ROOT99_TOG; /**< Target Register, offset: 0xB18C */ - uint8_t RESERVED_200[16]; - __IO uint32_t POST99; /**< Post Divider Register, offset: 0xB1A0 */ - __IO uint32_t POST_ROOT99_SET; /**< Post Divider Register, offset: 0xB1A4 */ - __IO uint32_t POST_ROOT99_CLR; /**< Post Divider Register, offset: 0xB1A8 */ - __IO uint32_t POST_ROOT99_TOG; /**< Post Divider Register, offset: 0xB1AC */ - __IO uint32_t PRE99; /**< Pre Divider Register, offset: 0xB1B0 */ - __IO uint32_t PRE_ROOT99_SET; /**< Pre Divider Register, offset: 0xB1B4 */ - __IO uint32_t PRE_ROOT99_CLR; /**< Pre Divider Register, offset: 0xB1B8 */ - __IO uint32_t PRE_ROOT99_TOG; /**< Pre Divider Register, offset: 0xB1BC */ - uint8_t RESERVED_201[48]; - __IO uint32_t ACCESS_CTRL99; /**< Access Control Register, offset: 0xB1F0 */ - __IO uint32_t ACCESS_CTRL99_ROOT_SET; /**< Access Control Register, offset: 0xB1F4 */ - __IO uint32_t ACCESS_CTRL99_ROOT_CLR; /**< Access Control Register, offset: 0xB1F8 */ - __IO uint32_t ACCESS_CTRL99_ROOT_TOG; /**< Access Control Register, offset: 0xB1FC */ - __IO uint32_t TARGET_ROOT100; /**< Target Register, offset: 0xB200 */ - __IO uint32_t TARGET_ROOT100_SET; /**< Target Register, offset: 0xB204 */ - __IO uint32_t TARGET_ROOT100_CLR; /**< Target Register, offset: 0xB208 */ - __IO uint32_t TARGET_ROOT100_TOG; /**< Target Register, offset: 0xB20C */ - uint8_t RESERVED_202[16]; - __IO uint32_t POST100; /**< Post Divider Register, offset: 0xB220 */ - __IO uint32_t POST_ROOT100_SET; /**< Post Divider Register, offset: 0xB224 */ - __IO uint32_t POST_ROOT100_CLR; /**< Post Divider Register, offset: 0xB228 */ - __IO uint32_t POST_ROOT100_TOG; /**< Post Divider Register, offset: 0xB22C */ - __IO uint32_t PRE100; /**< Pre Divider Register, offset: 0xB230 */ - __IO uint32_t PRE_ROOT100_SET; /**< Pre Divider Register, offset: 0xB234 */ - __IO uint32_t PRE_ROOT100_CLR; /**< Pre Divider Register, offset: 0xB238 */ - __IO uint32_t PRE_ROOT100_TOG; /**< Pre Divider Register, offset: 0xB23C */ - uint8_t RESERVED_203[48]; - __IO uint32_t ACCESS_CTRL100; /**< Access Control Register, offset: 0xB270 */ - __IO uint32_t ACCESS_CTRL100_ROOT_SET; /**< Access Control Register, offset: 0xB274 */ - __IO uint32_t ACCESS_CTRL100_ROOT_CLR; /**< Access Control Register, offset: 0xB278 */ - __IO uint32_t ACCESS_CTRL100_ROOT_TOG; /**< Access Control Register, offset: 0xB27C */ - __IO uint32_t TARGET_ROOT101; /**< Target Register, offset: 0xB280 */ - __IO uint32_t TARGET_ROOT101_SET; /**< Target Register, offset: 0xB284 */ - __IO uint32_t TARGET_ROOT101_CLR; /**< Target Register, offset: 0xB288 */ - __IO uint32_t TARGET_ROOT101_TOG; /**< Target Register, offset: 0xB28C */ - uint8_t RESERVED_204[16]; - __IO uint32_t POST101; /**< Post Divider Register, offset: 0xB2A0 */ - __IO uint32_t POST_ROOT101_SET; /**< Post Divider Register, offset: 0xB2A4 */ - __IO uint32_t POST_ROOT101_CLR; /**< Post Divider Register, offset: 0xB2A8 */ - __IO uint32_t POST_ROOT101_TOG; /**< Post Divider Register, offset: 0xB2AC */ - __IO uint32_t PRE101; /**< Pre Divider Register, offset: 0xB2B0 */ - __IO uint32_t PRE_ROOT101_SET; /**< Pre Divider Register, offset: 0xB2B4 */ - __IO uint32_t PRE_ROOT101_CLR; /**< Pre Divider Register, offset: 0xB2B8 */ - __IO uint32_t PRE_ROOT101_TOG; /**< Pre Divider Register, offset: 0xB2BC */ - uint8_t RESERVED_205[48]; - __IO uint32_t ACCESS_CTRL101; /**< Access Control Register, offset: 0xB2F0 */ - __IO uint32_t ACCESS_CTRL101_ROOT_SET; /**< Access Control Register, offset: 0xB2F4 */ - __IO uint32_t ACCESS_CTRL101_ROOT_CLR; /**< Access Control Register, offset: 0xB2F8 */ - __IO uint32_t ACCESS_CTRL101_ROOT_TOG; /**< Access Control Register, offset: 0xB2FC */ - __IO uint32_t TARGET_ROOT102; /**< Target Register, offset: 0xB300 */ - __IO uint32_t TARGET_ROOT102_SET; /**< Target Register, offset: 0xB304 */ - __IO uint32_t TARGET_ROOT102_CLR; /**< Target Register, offset: 0xB308 */ - __IO uint32_t TARGET_ROOT102_TOG; /**< Target Register, offset: 0xB30C */ - uint8_t RESERVED_206[16]; - __IO uint32_t POST102; /**< Post Divider Register, offset: 0xB320 */ - __IO uint32_t POST_ROOT102_SET; /**< Post Divider Register, offset: 0xB324 */ - __IO uint32_t POST_ROOT102_CLR; /**< Post Divider Register, offset: 0xB328 */ - __IO uint32_t POST_ROOT102_TOG; /**< Post Divider Register, offset: 0xB32C */ - __IO uint32_t PRE102; /**< Pre Divider Register, offset: 0xB330 */ - __IO uint32_t PRE_ROOT102_SET; /**< Pre Divider Register, offset: 0xB334 */ - __IO uint32_t PRE_ROOT102_CLR; /**< Pre Divider Register, offset: 0xB338 */ - __IO uint32_t PRE_ROOT102_TOG; /**< Pre Divider Register, offset: 0xB33C */ - uint8_t RESERVED_207[48]; - __IO uint32_t ACCESS_CTRL102; /**< Access Control Register, offset: 0xB370 */ - __IO uint32_t ACCESS_CTRL102_ROOT_SET; /**< Access Control Register, offset: 0xB374 */ - __IO uint32_t ACCESS_CTRL102_ROOT_CLR; /**< Access Control Register, offset: 0xB378 */ - __IO uint32_t ACCESS_CTRL102_ROOT_TOG; /**< Access Control Register, offset: 0xB37C */ - __IO uint32_t TARGET_ROOT103; /**< Target Register, offset: 0xB380 */ - __IO uint32_t TARGET_ROOT103_SET; /**< Target Register, offset: 0xB384 */ - __IO uint32_t TARGET_ROOT103_CLR; /**< Target Register, offset: 0xB388 */ - __IO uint32_t TARGET_ROOT103_TOG; /**< Target Register, offset: 0xB38C */ - uint8_t RESERVED_208[16]; - __IO uint32_t POST103; /**< Post Divider Register, offset: 0xB3A0 */ - __IO uint32_t POST_ROOT103_SET; /**< Post Divider Register, offset: 0xB3A4 */ - __IO uint32_t POST_ROOT103_CLR; /**< Post Divider Register, offset: 0xB3A8 */ - __IO uint32_t POST_ROOT103_TOG; /**< Post Divider Register, offset: 0xB3AC */ - __IO uint32_t PRE103; /**< Pre Divider Register, offset: 0xB3B0 */ - __IO uint32_t PRE_ROOT103_SET; /**< Pre Divider Register, offset: 0xB3B4 */ - __IO uint32_t PRE_ROOT103_CLR; /**< Pre Divider Register, offset: 0xB3B8 */ - __IO uint32_t PRE_ROOT103_TOG; /**< Pre Divider Register, offset: 0xB3BC */ - uint8_t RESERVED_209[48]; - __IO uint32_t ACCESS_CTRL103; /**< Access Control Register, offset: 0xB3F0 */ - __IO uint32_t ACCESS_CTRL103_ROOT_SET; /**< Access Control Register, offset: 0xB3F4 */ - __IO uint32_t ACCESS_CTRL103_ROOT_CLR; /**< Access Control Register, offset: 0xB3F8 */ - __IO uint32_t ACCESS_CTRL103_ROOT_TOG; /**< Access Control Register, offset: 0xB3FC */ - __IO uint32_t TARGET_ROOT104; /**< Target Register, offset: 0xB400 */ - __IO uint32_t TARGET_ROOT104_SET; /**< Target Register, offset: 0xB404 */ - __IO uint32_t TARGET_ROOT104_CLR; /**< Target Register, offset: 0xB408 */ - __IO uint32_t TARGET_ROOT104_TOG; /**< Target Register, offset: 0xB40C */ - uint8_t RESERVED_210[16]; - __IO uint32_t POST104; /**< Post Divider Register, offset: 0xB420 */ - __IO uint32_t POST_ROOT104_SET; /**< Post Divider Register, offset: 0xB424 */ - __IO uint32_t POST_ROOT104_CLR; /**< Post Divider Register, offset: 0xB428 */ - __IO uint32_t POST_ROOT104_TOG; /**< Post Divider Register, offset: 0xB42C */ - __IO uint32_t PRE104; /**< Pre Divider Register, offset: 0xB430 */ - __IO uint32_t PRE_ROOT104_SET; /**< Pre Divider Register, offset: 0xB434 */ - __IO uint32_t PRE_ROOT104_CLR; /**< Pre Divider Register, offset: 0xB438 */ - __IO uint32_t PRE_ROOT104_TOG; /**< Pre Divider Register, offset: 0xB43C */ - uint8_t RESERVED_211[48]; - __IO uint32_t ACCESS_CTRL104; /**< Access Control Register, offset: 0xB470 */ - __IO uint32_t ACCESS_CTRL104_ROOT_SET; /**< Access Control Register, offset: 0xB474 */ - __IO uint32_t ACCESS_CTRL104_ROOT_CLR; /**< Access Control Register, offset: 0xB478 */ - __IO uint32_t ACCESS_CTRL104_ROOT_TOG; /**< Access Control Register, offset: 0xB47C */ - __IO uint32_t TARGET_ROOT105; /**< Target Register, offset: 0xB480 */ - __IO uint32_t TARGET_ROOT105_SET; /**< Target Register, offset: 0xB484 */ - __IO uint32_t TARGET_ROOT105_CLR; /**< Target Register, offset: 0xB488 */ - __IO uint32_t TARGET_ROOT105_TOG; /**< Target Register, offset: 0xB48C */ - uint8_t RESERVED_212[16]; - __IO uint32_t POST105; /**< Post Divider Register, offset: 0xB4A0 */ - __IO uint32_t POST_ROOT105_SET; /**< Post Divider Register, offset: 0xB4A4 */ - __IO uint32_t POST_ROOT105_CLR; /**< Post Divider Register, offset: 0xB4A8 */ - __IO uint32_t POST_ROOT105_TOG; /**< Post Divider Register, offset: 0xB4AC */ - __IO uint32_t PRE105; /**< Pre Divider Register, offset: 0xB4B0 */ - __IO uint32_t PRE_ROOT105_SET; /**< Pre Divider Register, offset: 0xB4B4 */ - __IO uint32_t PRE_ROOT105_CLR; /**< Pre Divider Register, offset: 0xB4B8 */ - __IO uint32_t PRE_ROOT105_TOG; /**< Pre Divider Register, offset: 0xB4BC */ - uint8_t RESERVED_213[48]; - __IO uint32_t ACCESS_CTRL105; /**< Access Control Register, offset: 0xB4F0 */ - __IO uint32_t ACCESS_CTRL105_ROOT_SET; /**< Access Control Register, offset: 0xB4F4 */ - __IO uint32_t ACCESS_CTRL105_ROOT_CLR; /**< Access Control Register, offset: 0xB4F8 */ - __IO uint32_t ACCESS_CTRL105_ROOT_TOG; /**< Access Control Register, offset: 0xB4FC */ - __IO uint32_t TARGET_ROOT106; /**< Target Register, offset: 0xB500 */ - __IO uint32_t TARGET_ROOT106_SET; /**< Target Register, offset: 0xB504 */ - __IO uint32_t TARGET_ROOT106_CLR; /**< Target Register, offset: 0xB508 */ - __IO uint32_t TARGET_ROOT106_TOG; /**< Target Register, offset: 0xB50C */ - uint8_t RESERVED_214[16]; - __IO uint32_t POST106; /**< Post Divider Register, offset: 0xB520 */ - __IO uint32_t POST_ROOT106_SET; /**< Post Divider Register, offset: 0xB524 */ - __IO uint32_t POST_ROOT106_CLR; /**< Post Divider Register, offset: 0xB528 */ - __IO uint32_t POST_ROOT106_TOG; /**< Post Divider Register, offset: 0xB52C */ - __IO uint32_t PRE106; /**< Pre Divider Register, offset: 0xB530 */ - __IO uint32_t PRE_ROOT106_SET; /**< Pre Divider Register, offset: 0xB534 */ - __IO uint32_t PRE_ROOT106_CLR; /**< Pre Divider Register, offset: 0xB538 */ - __IO uint32_t PRE_ROOT106_TOG; /**< Pre Divider Register, offset: 0xB53C */ - uint8_t RESERVED_215[48]; - __IO uint32_t ACCESS_CTRL106; /**< Access Control Register, offset: 0xB570 */ - __IO uint32_t ACCESS_CTRL106_ROOT_SET; /**< Access Control Register, offset: 0xB574 */ - __IO uint32_t ACCESS_CTRL106_ROOT_CLR; /**< Access Control Register, offset: 0xB578 */ - __IO uint32_t ACCESS_CTRL106_ROOT_TOG; /**< Access Control Register, offset: 0xB57C */ - __IO uint32_t TARGET_ROOT107; /**< Target Register, offset: 0xB580 */ - __IO uint32_t TARGET_ROOT107_SET; /**< Target Register, offset: 0xB584 */ - __IO uint32_t TARGET_ROOT107_CLR; /**< Target Register, offset: 0xB588 */ - __IO uint32_t TARGET_ROOT107_TOG; /**< Target Register, offset: 0xB58C */ - uint8_t RESERVED_216[16]; - __IO uint32_t POST107; /**< Post Divider Register, offset: 0xB5A0 */ - __IO uint32_t POST_ROOT107_SET; /**< Post Divider Register, offset: 0xB5A4 */ - __IO uint32_t POST_ROOT107_CLR; /**< Post Divider Register, offset: 0xB5A8 */ - __IO uint32_t POST_ROOT107_TOG; /**< Post Divider Register, offset: 0xB5AC */ - __IO uint32_t PRE107; /**< Pre Divider Register, offset: 0xB5B0 */ - __IO uint32_t PRE_ROOT107_SET; /**< Pre Divider Register, offset: 0xB5B4 */ - __IO uint32_t PRE_ROOT107_CLR; /**< Pre Divider Register, offset: 0xB5B8 */ - __IO uint32_t PRE_ROOT107_TOG; /**< Pre Divider Register, offset: 0xB5BC */ - uint8_t RESERVED_217[48]; - __IO uint32_t ACCESS_CTRL107; /**< Access Control Register, offset: 0xB5F0 */ - __IO uint32_t ACCESS_CTRL107_ROOT_SET; /**< Access Control Register, offset: 0xB5F4 */ - __IO uint32_t ACCESS_CTRL107_ROOT_CLR; /**< Access Control Register, offset: 0xB5F8 */ - __IO uint32_t ACCESS_CTRL107_ROOT_TOG; /**< Access Control Register, offset: 0xB5FC */ - __IO uint32_t TARGET_ROOT108; /**< Target Register, offset: 0xB600 */ - __IO uint32_t TARGET_ROOT108_SET; /**< Target Register, offset: 0xB604 */ - __IO uint32_t TARGET_ROOT108_CLR; /**< Target Register, offset: 0xB608 */ - __IO uint32_t TARGET_ROOT108_TOG; /**< Target Register, offset: 0xB60C */ - uint8_t RESERVED_218[16]; - __IO uint32_t POST108; /**< Post Divider Register, offset: 0xB620 */ - __IO uint32_t POST_ROOT108_SET; /**< Post Divider Register, offset: 0xB624 */ - __IO uint32_t POST_ROOT108_CLR; /**< Post Divider Register, offset: 0xB628 */ - __IO uint32_t POST_ROOT108_TOG; /**< Post Divider Register, offset: 0xB62C */ - __IO uint32_t PRE108; /**< Pre Divider Register, offset: 0xB630 */ - __IO uint32_t PRE_ROOT108_SET; /**< Pre Divider Register, offset: 0xB634 */ - __IO uint32_t PRE_ROOT108_CLR; /**< Pre Divider Register, offset: 0xB638 */ - __IO uint32_t PRE_ROOT108_TOG; /**< Pre Divider Register, offset: 0xB63C */ - uint8_t RESERVED_219[48]; - __IO uint32_t ACCESS_CTRL108; /**< Access Control Register, offset: 0xB670 */ - __IO uint32_t ACCESS_CTRL108_ROOT_SET; /**< Access Control Register, offset: 0xB674 */ - __IO uint32_t ACCESS_CTRL108_ROOT_CLR; /**< Access Control Register, offset: 0xB678 */ - __IO uint32_t ACCESS_CTRL108_ROOT_TOG; /**< Access Control Register, offset: 0xB67C */ - __IO uint32_t TARGET_ROOT109; /**< Target Register, offset: 0xB680 */ - __IO uint32_t TARGET_ROOT109_SET; /**< Target Register, offset: 0xB684 */ - __IO uint32_t TARGET_ROOT109_CLR; /**< Target Register, offset: 0xB688 */ - __IO uint32_t TARGET_ROOT109_TOG; /**< Target Register, offset: 0xB68C */ - uint8_t RESERVED_220[16]; - __IO uint32_t POST109; /**< Post Divider Register, offset: 0xB6A0 */ - __IO uint32_t POST_ROOT109_SET; /**< Post Divider Register, offset: 0xB6A4 */ - __IO uint32_t POST_ROOT109_CLR; /**< Post Divider Register, offset: 0xB6A8 */ - __IO uint32_t POST_ROOT109_TOG; /**< Post Divider Register, offset: 0xB6AC */ - __IO uint32_t PRE109; /**< Pre Divider Register, offset: 0xB6B0 */ - __IO uint32_t PRE_ROOT109_SET; /**< Pre Divider Register, offset: 0xB6B4 */ - __IO uint32_t PRE_ROOT109_CLR; /**< Pre Divider Register, offset: 0xB6B8 */ - __IO uint32_t PRE_ROOT109_TOG; /**< Pre Divider Register, offset: 0xB6BC */ - uint8_t RESERVED_221[48]; - __IO uint32_t ACCESS_CTRL109; /**< Access Control Register, offset: 0xB6F0 */ - __IO uint32_t ACCESS_CTRL109_ROOT_SET; /**< Access Control Register, offset: 0xB6F4 */ - __IO uint32_t ACCESS_CTRL109_ROOT_CLR; /**< Access Control Register, offset: 0xB6F8 */ - __IO uint32_t ACCESS_CTRL109_ROOT_TOG; /**< Access Control Register, offset: 0xB6FC */ - __IO uint32_t TARGET_ROOT110; /**< Target Register, offset: 0xB700 */ - __IO uint32_t TARGET_ROOT110_SET; /**< Target Register, offset: 0xB704 */ - __IO uint32_t TARGET_ROOT110_CLR; /**< Target Register, offset: 0xB708 */ - __IO uint32_t TARGET_ROOT110_TOG; /**< Target Register, offset: 0xB70C */ - uint8_t RESERVED_222[16]; - __IO uint32_t POST110; /**< Post Divider Register, offset: 0xB720 */ - __IO uint32_t POST_ROOT110_SET; /**< Post Divider Register, offset: 0xB724 */ - __IO uint32_t POST_ROOT110_CLR; /**< Post Divider Register, offset: 0xB728 */ - __IO uint32_t POST_ROOT110_TOG; /**< Post Divider Register, offset: 0xB72C */ - __IO uint32_t PRE110; /**< Pre Divider Register, offset: 0xB730 */ - __IO uint32_t PRE_ROOT110_SET; /**< Pre Divider Register, offset: 0xB734 */ - __IO uint32_t PRE_ROOT110_CLR; /**< Pre Divider Register, offset: 0xB738 */ - __IO uint32_t PRE_ROOT110_TOG; /**< Pre Divider Register, offset: 0xB73C */ - uint8_t RESERVED_223[48]; - __IO uint32_t ACCESS_CTRL110; /**< Access Control Register, offset: 0xB770 */ - __IO uint32_t ACCESS_CTRL110_ROOT_SET; /**< Access Control Register, offset: 0xB774 */ - __IO uint32_t ACCESS_CTRL110_ROOT_CLR; /**< Access Control Register, offset: 0xB778 */ - __IO uint32_t ACCESS_CTRL110_ROOT_TOG; /**< Access Control Register, offset: 0xB77C */ - __IO uint32_t TARGET_ROOT111; /**< Target Register, offset: 0xB780 */ - __IO uint32_t TARGET_ROOT111_SET; /**< Target Register, offset: 0xB784 */ - __IO uint32_t TARGET_ROOT111_CLR; /**< Target Register, offset: 0xB788 */ - __IO uint32_t TARGET_ROOT111_TOG; /**< Target Register, offset: 0xB78C */ - uint8_t RESERVED_224[16]; - __IO uint32_t POST111; /**< Post Divider Register, offset: 0xB7A0 */ - __IO uint32_t POST_ROOT111_SET; /**< Post Divider Register, offset: 0xB7A4 */ - __IO uint32_t POST_ROOT111_CLR; /**< Post Divider Register, offset: 0xB7A8 */ - __IO uint32_t POST_ROOT111_TOG; /**< Post Divider Register, offset: 0xB7AC */ - __IO uint32_t PRE111; /**< Pre Divider Register, offset: 0xB7B0 */ - __IO uint32_t PRE_ROOT111_SET; /**< Pre Divider Register, offset: 0xB7B4 */ - __IO uint32_t PRE_ROOT111_CLR; /**< Pre Divider Register, offset: 0xB7B8 */ - __IO uint32_t PRE_ROOT111_TOG; /**< Pre Divider Register, offset: 0xB7BC */ - uint8_t RESERVED_225[48]; - __IO uint32_t ACCESS_CTRL111; /**< Access Control Register, offset: 0xB7F0 */ - __IO uint32_t ACCESS_CTRL111_ROOT_SET; /**< Access Control Register, offset: 0xB7F4 */ - __IO uint32_t ACCESS_CTRL111_ROOT_CLR; /**< Access Control Register, offset: 0xB7F8 */ - __IO uint32_t ACCESS_CTRL111_ROOT_TOG; /**< Access Control Register, offset: 0xB7FC */ - __IO uint32_t TARGET_ROOT112; /**< Target Register, offset: 0xB800 */ - __IO uint32_t TARGET_ROOT112_SET; /**< Target Register, offset: 0xB804 */ - __IO uint32_t TARGET_ROOT112_CLR; /**< Target Register, offset: 0xB808 */ - __IO uint32_t TARGET_ROOT112_TOG; /**< Target Register, offset: 0xB80C */ - uint8_t RESERVED_226[16]; - __IO uint32_t POST112; /**< Post Divider Register, offset: 0xB820 */ - __IO uint32_t POST_ROOT112_SET; /**< Post Divider Register, offset: 0xB824 */ - __IO uint32_t POST_ROOT112_CLR; /**< Post Divider Register, offset: 0xB828 */ - __IO uint32_t POST_ROOT112_TOG; /**< Post Divider Register, offset: 0xB82C */ - __IO uint32_t PRE112; /**< Pre Divider Register, offset: 0xB830 */ - __IO uint32_t PRE_ROOT112_SET; /**< Pre Divider Register, offset: 0xB834 */ - __IO uint32_t PRE_ROOT112_CLR; /**< Pre Divider Register, offset: 0xB838 */ - __IO uint32_t PRE_ROOT112_TOG; /**< Pre Divider Register, offset: 0xB83C */ - uint8_t RESERVED_227[48]; - __IO uint32_t ACCESS_CTRL112; /**< Access Control Register, offset: 0xB870 */ - __IO uint32_t ACCESS_CTRL112_ROOT_SET; /**< Access Control Register, offset: 0xB874 */ - __IO uint32_t ACCESS_CTRL112_ROOT_CLR; /**< Access Control Register, offset: 0xB878 */ - __IO uint32_t ACCESS_CTRL112_ROOT_TOG; /**< Access Control Register, offset: 0xB87C */ - __IO uint32_t TARGET_ROOT113; /**< Target Register, offset: 0xB880 */ - __IO uint32_t TARGET_ROOT113_SET; /**< Target Register, offset: 0xB884 */ - __IO uint32_t TARGET_ROOT113_CLR; /**< Target Register, offset: 0xB888 */ - __IO uint32_t TARGET_ROOT113_TOG; /**< Target Register, offset: 0xB88C */ - uint8_t RESERVED_228[16]; - __IO uint32_t POST113; /**< Post Divider Register, offset: 0xB8A0 */ - __IO uint32_t POST_ROOT113_SET; /**< Post Divider Register, offset: 0xB8A4 */ - __IO uint32_t POST_ROOT113_CLR; /**< Post Divider Register, offset: 0xB8A8 */ - __IO uint32_t POST_ROOT113_TOG; /**< Post Divider Register, offset: 0xB8AC */ - __IO uint32_t PRE113; /**< Pre Divider Register, offset: 0xB8B0 */ - __IO uint32_t PRE_ROOT113_SET; /**< Pre Divider Register, offset: 0xB8B4 */ - __IO uint32_t PRE_ROOT113_CLR; /**< Pre Divider Register, offset: 0xB8B8 */ - __IO uint32_t PRE_ROOT113_TOG; /**< Pre Divider Register, offset: 0xB8BC */ - uint8_t RESERVED_229[48]; - __IO uint32_t ACCESS_CTRL113; /**< Access Control Register, offset: 0xB8F0 */ - __IO uint32_t ACCESS_CTRL113_ROOT_SET; /**< Access Control Register, offset: 0xB8F4 */ - __IO uint32_t ACCESS_CTRL113_ROOT_CLR; /**< Access Control Register, offset: 0xB8F8 */ - __IO uint32_t ACCESS_CTRL113_ROOT_TOG; /**< Access Control Register, offset: 0xB8FC */ - __IO uint32_t TARGET_ROOT114; /**< Target Register, offset: 0xB900 */ - __IO uint32_t TARGET_ROOT114_SET; /**< Target Register, offset: 0xB904 */ - __IO uint32_t TARGET_ROOT114_CLR; /**< Target Register, offset: 0xB908 */ - __IO uint32_t TARGET_ROOT114_TOG; /**< Target Register, offset: 0xB90C */ - uint8_t RESERVED_230[16]; - __IO uint32_t POST114; /**< Post Divider Register, offset: 0xB920 */ - __IO uint32_t POST_ROOT114_SET; /**< Post Divider Register, offset: 0xB924 */ - __IO uint32_t POST_ROOT114_CLR; /**< Post Divider Register, offset: 0xB928 */ - __IO uint32_t POST_ROOT114_TOG; /**< Post Divider Register, offset: 0xB92C */ - __IO uint32_t PRE114; /**< Pre Divider Register, offset: 0xB930 */ - __IO uint32_t PRE_ROOT114_SET; /**< Pre Divider Register, offset: 0xB934 */ - __IO uint32_t PRE_ROOT114_CLR; /**< Pre Divider Register, offset: 0xB938 */ - __IO uint32_t PRE_ROOT114_TOG; /**< Pre Divider Register, offset: 0xB93C */ - uint8_t RESERVED_231[48]; - __IO uint32_t ACCESS_CTRL114; /**< Access Control Register, offset: 0xB970 */ - __IO uint32_t ACCESS_CTRL114_ROOT_SET; /**< Access Control Register, offset: 0xB974 */ - __IO uint32_t ACCESS_CTRL114_ROOT_CLR; /**< Access Control Register, offset: 0xB978 */ - __IO uint32_t ACCESS_CTRL114_ROOT_TOG; /**< Access Control Register, offset: 0xB97C */ - __IO uint32_t TARGET_ROOT115; /**< Target Register, offset: 0xB980 */ - __IO uint32_t TARGET_ROOT115_SET; /**< Target Register, offset: 0xB984 */ - __IO uint32_t TARGET_ROOT115_CLR; /**< Target Register, offset: 0xB988 */ - __IO uint32_t TARGET_ROOT115_TOG; /**< Target Register, offset: 0xB98C */ - uint8_t RESERVED_232[16]; - __IO uint32_t POST115; /**< Post Divider Register, offset: 0xB9A0 */ - __IO uint32_t POST_ROOT115_SET; /**< Post Divider Register, offset: 0xB9A4 */ - __IO uint32_t POST_ROOT115_CLR; /**< Post Divider Register, offset: 0xB9A8 */ - __IO uint32_t POST_ROOT115_TOG; /**< Post Divider Register, offset: 0xB9AC */ - __IO uint32_t PRE115; /**< Pre Divider Register, offset: 0xB9B0 */ - __IO uint32_t PRE_ROOT115_SET; /**< Pre Divider Register, offset: 0xB9B4 */ - __IO uint32_t PRE_ROOT115_CLR; /**< Pre Divider Register, offset: 0xB9B8 */ - __IO uint32_t PRE_ROOT115_TOG; /**< Pre Divider Register, offset: 0xB9BC */ - uint8_t RESERVED_233[48]; - __IO uint32_t ACCESS_CTRL115; /**< Access Control Register, offset: 0xB9F0 */ - __IO uint32_t ACCESS_CTRL115_ROOT_SET; /**< Access Control Register, offset: 0xB9F4 */ - __IO uint32_t ACCESS_CTRL115_ROOT_CLR; /**< Access Control Register, offset: 0xB9F8 */ - __IO uint32_t ACCESS_CTRL115_ROOT_TOG; /**< Access Control Register, offset: 0xB9FC */ - __IO uint32_t TARGET_ROOT116; /**< Target Register, offset: 0xBA00 */ - __IO uint32_t TARGET_ROOT116_SET; /**< Target Register, offset: 0xBA04 */ - __IO uint32_t TARGET_ROOT116_CLR; /**< Target Register, offset: 0xBA08 */ - __IO uint32_t TARGET_ROOT116_TOG; /**< Target Register, offset: 0xBA0C */ - uint8_t RESERVED_234[16]; - __IO uint32_t POST116; /**< Post Divider Register, offset: 0xBA20 */ - __IO uint32_t POST_ROOT116_SET; /**< Post Divider Register, offset: 0xBA24 */ - __IO uint32_t POST_ROOT116_CLR; /**< Post Divider Register, offset: 0xBA28 */ - __IO uint32_t POST_ROOT116_TOG; /**< Post Divider Register, offset: 0xBA2C */ - __IO uint32_t PRE116; /**< Pre Divider Register, offset: 0xBA30 */ - __IO uint32_t PRE_ROOT116_SET; /**< Pre Divider Register, offset: 0xBA34 */ - __IO uint32_t PRE_ROOT116_CLR; /**< Pre Divider Register, offset: 0xBA38 */ - __IO uint32_t PRE_ROOT116_TOG; /**< Pre Divider Register, offset: 0xBA3C */ - uint8_t RESERVED_235[48]; - __IO uint32_t ACCESS_CTRL116; /**< Access Control Register, offset: 0xBA70 */ - __IO uint32_t ACCESS_CTRL116_ROOT_SET; /**< Access Control Register, offset: 0xBA74 */ - __IO uint32_t ACCESS_CTRL116_ROOT_CLR; /**< Access Control Register, offset: 0xBA78 */ - __IO uint32_t ACCESS_CTRL116_ROOT_TOG; /**< Access Control Register, offset: 0xBA7C */ - __IO uint32_t TARGET_ROOT117; /**< Target Register, offset: 0xBA80 */ - __IO uint32_t TARGET_ROOT117_SET; /**< Target Register, offset: 0xBA84 */ - __IO uint32_t TARGET_ROOT117_CLR; /**< Target Register, offset: 0xBA88 */ - __IO uint32_t TARGET_ROOT117_TOG; /**< Target Register, offset: 0xBA8C */ - uint8_t RESERVED_236[16]; - __IO uint32_t POST117; /**< Post Divider Register, offset: 0xBAA0 */ - __IO uint32_t POST_ROOT117_SET; /**< Post Divider Register, offset: 0xBAA4 */ - __IO uint32_t POST_ROOT117_CLR; /**< Post Divider Register, offset: 0xBAA8 */ - __IO uint32_t POST_ROOT117_TOG; /**< Post Divider Register, offset: 0xBAAC */ - __IO uint32_t PRE117; /**< Pre Divider Register, offset: 0xBAB0 */ - __IO uint32_t PRE_ROOT117_SET; /**< Pre Divider Register, offset: 0xBAB4 */ - __IO uint32_t PRE_ROOT117_CLR; /**< Pre Divider Register, offset: 0xBAB8 */ - __IO uint32_t PRE_ROOT117_TOG; /**< Pre Divider Register, offset: 0xBABC */ - uint8_t RESERVED_237[48]; - __IO uint32_t ACCESS_CTRL117; /**< Access Control Register, offset: 0xBAF0 */ - __IO uint32_t ACCESS_CTRL117_ROOT_SET; /**< Access Control Register, offset: 0xBAF4 */ - __IO uint32_t ACCESS_CTRL117_ROOT_CLR; /**< Access Control Register, offset: 0xBAF8 */ - __IO uint32_t ACCESS_CTRL117_ROOT_TOG; /**< Access Control Register, offset: 0xBAFC */ - __IO uint32_t TARGET_ROOT118; /**< Target Register, offset: 0xBB00 */ - __IO uint32_t TARGET_ROOT118_SET; /**< Target Register, offset: 0xBB04 */ - __IO uint32_t TARGET_ROOT118_CLR; /**< Target Register, offset: 0xBB08 */ - __IO uint32_t TARGET_ROOT118_TOG; /**< Target Register, offset: 0xBB0C */ - uint8_t RESERVED_238[16]; - __IO uint32_t POST118; /**< Post Divider Register, offset: 0xBB20 */ - __IO uint32_t POST_ROOT118_SET; /**< Post Divider Register, offset: 0xBB24 */ - __IO uint32_t POST_ROOT118_CLR; /**< Post Divider Register, offset: 0xBB28 */ - __IO uint32_t POST_ROOT118_TOG; /**< Post Divider Register, offset: 0xBB2C */ - __IO uint32_t PRE118; /**< Pre Divider Register, offset: 0xBB30 */ - __IO uint32_t PRE_ROOT118_SET; /**< Pre Divider Register, offset: 0xBB34 */ - __IO uint32_t PRE_ROOT118_CLR; /**< Pre Divider Register, offset: 0xBB38 */ - __IO uint32_t PRE_ROOT118_TOG; /**< Pre Divider Register, offset: 0xBB3C */ - uint8_t RESERVED_239[48]; - __IO uint32_t ACCESS_CTRL118; /**< Access Control Register, offset: 0xBB70 */ - __IO uint32_t ACCESS_CTRL118_ROOT_SET; /**< Access Control Register, offset: 0xBB74 */ - __IO uint32_t ACCESS_CTRL118_ROOT_CLR; /**< Access Control Register, offset: 0xBB78 */ - __IO uint32_t ACCESS_CTRL118_ROOT_TOG; /**< Access Control Register, offset: 0xBB7C */ - __IO uint32_t TARGET_ROOT119; /**< Target Register, offset: 0xBB80 */ - __IO uint32_t TARGET_ROOT119_SET; /**< Target Register, offset: 0xBB84 */ - __IO uint32_t TARGET_ROOT119_CLR; /**< Target Register, offset: 0xBB88 */ - __IO uint32_t TARGET_ROOT119_TOG; /**< Target Register, offset: 0xBB8C */ - uint8_t RESERVED_240[16]; - __IO uint32_t POST119; /**< Post Divider Register, offset: 0xBBA0 */ - __IO uint32_t POST_ROOT119_SET; /**< Post Divider Register, offset: 0xBBA4 */ - __IO uint32_t POST_ROOT119_CLR; /**< Post Divider Register, offset: 0xBBA8 */ - __IO uint32_t POST_ROOT119_TOG; /**< Post Divider Register, offset: 0xBBAC */ - __IO uint32_t PRE119; /**< Pre Divider Register, offset: 0xBBB0 */ - __IO uint32_t PRE_ROOT119_SET; /**< Pre Divider Register, offset: 0xBBB4 */ - __IO uint32_t PRE_ROOT119_CLR; /**< Pre Divider Register, offset: 0xBBB8 */ - __IO uint32_t PRE_ROOT119_TOG; /**< Pre Divider Register, offset: 0xBBBC */ - uint8_t RESERVED_241[48]; - __IO uint32_t ACCESS_CTRL119; /**< Access Control Register, offset: 0xBBF0 */ - __IO uint32_t ACCESS_CTRL119_ROOT_SET; /**< Access Control Register, offset: 0xBBF4 */ - __IO uint32_t ACCESS_CTRL119_ROOT_CLR; /**< Access Control Register, offset: 0xBBF8 */ - __IO uint32_t ACCESS_CTRL119_ROOT_TOG; /**< Access Control Register, offset: 0xBBFC */ - __IO uint32_t TARGET_ROOT120; /**< Target Register, offset: 0xBC00 */ - __IO uint32_t TARGET_ROOT120_SET; /**< Target Register, offset: 0xBC04 */ - __IO uint32_t TARGET_ROOT120_CLR; /**< Target Register, offset: 0xBC08 */ - __IO uint32_t TARGET_ROOT120_TOG; /**< Target Register, offset: 0xBC0C */ - uint8_t RESERVED_242[16]; - __IO uint32_t POST120; /**< Post Divider Register, offset: 0xBC20 */ - __IO uint32_t POST_ROOT120_SET; /**< Post Divider Register, offset: 0xBC24 */ - __IO uint32_t POST_ROOT120_CLR; /**< Post Divider Register, offset: 0xBC28 */ - __IO uint32_t POST_ROOT120_TOG; /**< Post Divider Register, offset: 0xBC2C */ - __IO uint32_t PRE120; /**< Pre Divider Register, offset: 0xBC30 */ - __IO uint32_t PRE_ROOT120_SET; /**< Pre Divider Register, offset: 0xBC34 */ - __IO uint32_t PRE_ROOT120_CLR; /**< Pre Divider Register, offset: 0xBC38 */ - __IO uint32_t PRE_ROOT120_TOG; /**< Pre Divider Register, offset: 0xBC3C */ - uint8_t RESERVED_243[48]; - __IO uint32_t ACCESS_CTRL120; /**< Access Control Register, offset: 0xBC70 */ - __IO uint32_t ACCESS_CTRL120_ROOT_SET; /**< Access Control Register, offset: 0xBC74 */ - __IO uint32_t ACCESS_CTRL120_ROOT_CLR; /**< Access Control Register, offset: 0xBC78 */ - __IO uint32_t ACCESS_CTRL120_ROOT_TOG; /**< Access Control Register, offset: 0xBC7C */ + uint8_t RESERVED_0[2032]; + struct { /* offset: 0x800, array step: 0x10 */ + __IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */ + __IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */ + __IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */ + __IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */ + } PLL_CTRL[33]; + uint8_t RESERVED_1[13808]; + struct { /* offset: 0x4000, array step: 0x10 */ + __IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */ + __IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */ + __IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */ + __IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */ + } CCGR[191]; + uint8_t RESERVED_2[13328]; + struct { /* offset: 0x8000, array step: 0x80 */ + __IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */ + __IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */ + __IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */ + __IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */ + __IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */ + __IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */ + __IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */ + __IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */ + __IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */ + __IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */ + __IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */ + __IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */ + __IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */ + __IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */ + __IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */ + __IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */ + uint8_t RESERVED_0[48]; + __IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */ + __IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */ + __IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */ + __IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */ + } ACCESS_CTRL_ROOT_TOG[125]; } CCM_Type, *CCM_MemMapPtr; - /* ---------------------------------------------------------------------------- -- CCM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -7013,2844 +4588,38 @@ typedef struct { #define CCM_GPR0_SET_REG(base) ((base)->GPR0_SET) #define CCM_GPR0_CLR_REG(base) ((base)->GPR0_CLR) #define CCM_GPR0_TOG_REG(base) ((base)->GPR0_TOG) -#define CCM_PLL_CTRL0_REG(base) ((base)->PLL_CTRL0) -#define CCM_PLL_CTRL0_SET_REG(base) ((base)->PLL_CTRL0_SET) -#define CCM_PLL_CTRL0_CLR_REG(base) ((base)->PLL_CTRL0_CLR) -#define CCM_PLL_CTRL0_TOG_REG(base) ((base)->PLL_CTRL0_TOG) -#define CCM_PLL_CTRL1_REG(base) ((base)->PLL_CTRL1) -#define CCM_PLL_CTRL1_SET_REG(base) ((base)->PLL_CTRL1_SET) -#define CCM_PLL_CTRL1_CLR_REG(base) ((base)->PLL_CTRL1_CLR) -#define CCM_PLL_CTRL1_TOG_REG(base) ((base)->PLL_CTRL1_TOG) -#define CCM_PLL_CTRL2_REG(base) ((base)->PLL_CTRL2) -#define CCM_PLL_CTRL2_SET_REG(base) ((base)->PLL_CTRL2_SET) -#define CCM_PLL_CTRL2_CLR_REG(base) ((base)->PLL_CTRL2_CLR) -#define CCM_PLL_CTRL2_TOG_REG(base) ((base)->PLL_CTRL2_TOG) -#define CCM_PLL_CTRL3_REG(base) ((base)->PLL_CTRL3) -#define CCM_PLL_CTRL3_SET_REG(base) ((base)->PLL_CTRL3_SET) -#define CCM_PLL_CTRL3_CLR_REG(base) ((base)->PLL_CTRL3_CLR) -#define CCM_PLL_CTRL3_TOG_REG(base) ((base)->PLL_CTRL3_TOG) -#define CCM_PLL_CTRL4_REG(base) ((base)->PLL_CTRL4) -#define CCM_PLL_CTRL4_SET_REG(base) ((base)->PLL_CTRL4_SET) -#define CCM_PLL_CTRL4_CLR_REG(base) ((base)->PLL_CTRL4_CLR) -#define CCM_PLL_CTRL4_TOG_REG(base) ((base)->PLL_CTRL4_TOG) -#define CCM_PLL_CTRL5_REG(base) ((base)->PLL_CTRL5) -#define CCM_PLL_CTRL5_SET_REG(base) ((base)->PLL_CTRL5_SET) -#define CCM_PLL_CTRL5_CLR_REG(base) ((base)->PLL_CTRL5_CLR) -#define CCM_PLL_CTRL5_TOG_REG(base) ((base)->PLL_CTRL5_TOG) -#define CCM_PLL_CTRL6_REG(base) ((base)->PLL_CTRL6) -#define CCM_PLL_CTRL6_SET_REG(base) ((base)->PLL_CTRL6_SET) -#define CCM_PLL_CTRL6_CLR_REG(base) ((base)->PLL_CTRL6_CLR) -#define CCM_PLL_CTRL6_TOG_REG(base) ((base)->PLL_CTRL6_TOG) -#define CCM_PLL_CTRL7_REG(base) ((base)->PLL_CTRL7) -#define CCM_PLL_CTRL7_SET_REG(base) ((base)->PLL_CTRL7_SET) -#define CCM_PLL_CTRL7_CLR_REG(base) ((base)->PLL_CTRL7_CLR) -#define CCM_PLL_CTRL7_TOG_REG(base) ((base)->PLL_CTRL7_TOG) -#define CCM_PLL_CTRL8_REG(base) ((base)->PLL_CTRL8) -#define CCM_PLL_CTRL8_SET_REG(base) ((base)->PLL_CTRL8_SET) -#define CCM_PLL_CTRL8_CLR_REG(base) ((base)->PLL_CTRL8_CLR) -#define CCM_PLL_CTRL8_TOG_REG(base) ((base)->PLL_CTRL8_TOG) -#define CCM_PLL_CTRL9_REG(base) ((base)->PLL_CTRL9) -#define CCM_PLL_CTRL9_SET_REG(base) ((base)->PLL_CTRL9_SET) -#define CCM_PLL_CTRL9_CLR_REG(base) ((base)->PLL_CTRL9_CLR) -#define CCM_PLL_CTRL9_TOG_REG(base) ((base)->PLL_CTRL9_TOG) -#define CCM_PLL_CTRL10_REG(base) ((base)->PLL_CTRL10) -#define CCM_PLL_CTRL10_SET_REG(base) ((base)->PLL_CTRL10_SET) -#define CCM_PLL_CTRL10_CLR_REG(base) ((base)->PLL_CTRL10_CLR) -#define CCM_PLL_CTRL10_TOG_REG(base) ((base)->PLL_CTRL10_TOG) -#define CCM_PLL_CTRL11_REG(base) ((base)->PLL_CTRL11) -#define CCM_PLL_CTRL11_SET_REG(base) ((base)->PLL_CTRL11_SET) -#define CCM_PLL_CTRL11_CLR_REG(base) ((base)->PLL_CTRL11_CLR) -#define CCM_PLL_CTRL11_TOG_REG(base) ((base)->PLL_CTRL11_TOG) -#define CCM_PLL_CTRL12_REG(base) ((base)->PLL_CTRL12) -#define CCM_PLL_CTRL12_SET_REG(base) ((base)->PLL_CTRL12_SET) -#define CCM_PLL_CTRL12_CLR_REG(base) ((base)->PLL_CTRL12_CLR) -#define CCM_PLL_CTRL12_TOG_REG(base) ((base)->PLL_CTRL12_TOG) -#define CCM_PLL_CTRL13_REG(base) ((base)->PLL_CTRL13) -#define CCM_PLL_CTRL13_SET_REG(base) ((base)->PLL_CTRL13_SET) -#define CCM_PLL_CTRL13_CLR_REG(base) ((base)->PLL_CTRL13_CLR) -#define CCM_PLL_CTRL13_TOG_REG(base) ((base)->PLL_CTRL13_TOG) -#define CCM_PLL_CTRL14_REG(base) ((base)->PLL_CTRL14) -#define CCM_PLL_CTRL14_SET_REG(base) ((base)->PLL_CTRL14_SET) -#define CCM_PLL_CTRL14_CLR_REG(base) ((base)->PLL_CTRL14_CLR) -#define CCM_PLL_CTRL14_TOG_REG(base) ((base)->PLL_CTRL14_TOG) -#define CCM_PLL_CTRL15_REG(base) ((base)->PLL_CTRL15) -#define CCM_PLL_CTRL15_SET_REG(base) ((base)->PLL_CTRL15_SET) -#define CCM_PLL_CTRL15_CLR_REG(base) ((base)->PLL_CTRL15_CLR) -#define CCM_PLL_CTRL15_TOG_REG(base) ((base)->PLL_CTRL15_TOG) -#define CCM_PLL_CTRL16_REG(base) ((base)->PLL_CTRL16) -#define CCM_PLL_CTRL16_SET_REG(base) ((base)->PLL_CTRL16_SET) -#define CCM_PLL_CTRL16_CLR_REG(base) ((base)->PLL_CTRL16_CLR) -#define CCM_PLL_CTRL16_TOG_REG(base) ((base)->PLL_CTRL16_TOG) -#define CCM_PLL_CTRL17_REG(base) ((base)->PLL_CTRL17) -#define CCM_PLL_CTRL17_SET_REG(base) ((base)->PLL_CTRL17_SET) -#define CCM_PLL_CTRL17_CLR_REG(base) ((base)->PLL_CTRL17_CLR) -#define CCM_PLL_CTRL17_TOG_REG(base) ((base)->PLL_CTRL17_TOG) -#define CCM_PLL_CTRL18_REG(base) ((base)->PLL_CTRL18) -#define CCM_PLL_CTRL18_SET_REG(base) ((base)->PLL_CTRL18_SET) -#define CCM_PLL_CTRL18_CLR_REG(base) ((base)->PLL_CTRL18_CLR) -#define CCM_PLL_CTRL18_TOG_REG(base) ((base)->PLL_CTRL18_TOG) -#define CCM_PLL_CTRL19_REG(base) ((base)->PLL_CTRL19) -#define CCM_PLL_CTRL19_SET_REG(base) ((base)->PLL_CTRL19_SET) -#define CCM_PLL_CTRL19_CLR_REG(base) ((base)->PLL_CTRL19_CLR) -#define CCM_PLL_CTRL19_TOG_REG(base) ((base)->PLL_CTRL19_TOG) -#define CCM_PLL_CTRL20_REG(base) ((base)->PLL_CTRL20) -#define CCM_PLL_CTRL20_SET_REG(base) ((base)->PLL_CTRL20_SET) -#define CCM_PLL_CTRL20_CLR_REG(base) ((base)->PLL_CTRL20_CLR) -#define CCM_PLL_CTRL20_TOG_REG(base) ((base)->PLL_CTRL20_TOG) -#define CCM_PLL_CTRL21_REG(base) ((base)->PLL_CTRL21) -#define CCM_PLL_CTRL21_SET_REG(base) ((base)->PLL_CTRL21_SET) -#define CCM_PLL_CTRL21_CLR_REG(base) ((base)->PLL_CTRL21_CLR) -#define CCM_PLL_CTRL21_TOG_REG(base) ((base)->PLL_CTRL21_TOG) -#define CCM_PLL_CTRL22_REG(base) ((base)->PLL_CTRL22) -#define CCM_PLL_CTRL22_SET_REG(base) ((base)->PLL_CTRL22_SET) -#define CCM_PLL_CTRL22_CLR_REG(base) ((base)->PLL_CTRL22_CLR) -#define CCM_PLL_CTRL22_TOG_REG(base) ((base)->PLL_CTRL22_TOG) -#define CCM_PLL_CTRL23_REG(base) ((base)->PLL_CTRL23) -#define CCM_PLL_CTRL23_SET_REG(base) ((base)->PLL_CTRL23_SET) -#define CCM_PLL_CTRL23_CLR_REG(base) ((base)->PLL_CTRL23_CLR) -#define CCM_PLL_CTRL23_TOG_REG(base) ((base)->PLL_CTRL23_TOG) -#define CCM_PLL_CTRL24_REG(base) ((base)->PLL_CTRL24) -#define CCM_PLL_CTRL24_SET_REG(base) ((base)->PLL_CTRL24_SET) -#define CCM_PLL_CTRL24_CLR_REG(base) ((base)->PLL_CTRL24_CLR) -#define CCM_PLL_CTRL24_TOG_REG(base) ((base)->PLL_CTRL24_TOG) -#define CCM_PLL_CTRL25_REG(base) ((base)->PLL_CTRL25) -#define CCM_PLL_CTRL25_SET_REG(base) ((base)->PLL_CTRL25_SET) -#define CCM_PLL_CTRL25_CLR_REG(base) ((base)->PLL_CTRL25_CLR) -#define CCM_PLL_CTRL25_TOG_REG(base) ((base)->PLL_CTRL25_TOG) -#define CCM_PLL_CTRL26_REG(base) ((base)->PLL_CTRL26) -#define CCM_PLL_CTRL26_SET_REG(base) ((base)->PLL_CTRL26_SET) -#define CCM_PLL_CTRL26_CLR_REG(base) ((base)->PLL_CTRL26_CLR) -#define CCM_PLL_CTRL26_TOG_REG(base) ((base)->PLL_CTRL26_TOG) -#define CCM_PLL_CTRL27_REG(base) ((base)->PLL_CTRL27) -#define CCM_PLL_CTRL27_SET_REG(base) ((base)->PLL_CTRL27_SET) -#define CCM_PLL_CTRL27_CLR_REG(base) ((base)->PLL_CTRL27_CLR) -#define CCM_PLL_CTRL27_TOG_REG(base) ((base)->PLL_CTRL27_TOG) -#define CCM_PLL_CTRL28_REG(base) ((base)->PLL_CTRL28) -#define CCM_PLL_CTRL28_SET_REG(base) ((base)->PLL_CTRL28_SET) -#define CCM_PLL_CTRL28_CLR_REG(base) ((base)->PLL_CTRL28_CLR) -#define CCM_PLL_CTRL28_TOG_REG(base) ((base)->PLL_CTRL28_TOG) -#define CCM_PLL_CTRL29_REG(base) ((base)->PLL_CTRL29) -#define CCM_PLL_CTRL29_SET_REG(base) ((base)->PLL_CTRL29_SET) -#define CCM_PLL_CTRL29_CLR_REG(base) ((base)->PLL_CTRL29_CLR) -#define CCM_PLL_CTRL29_TOG_REG(base) ((base)->PLL_CTRL29_TOG) -#define CCM_PLL_CTRL30_REG(base) ((base)->PLL_CTRL30) -#define CCM_PLL_CTRL30_SET_REG(base) ((base)->PLL_CTRL30_SET) -#define CCM_PLL_CTRL30_CLR_REG(base) ((base)->PLL_CTRL30_CLR) -#define CCM_PLL_CTRL30_TOG_REG(base) ((base)->PLL_CTRL30_TOG) -#define CCM_PLL_CTRL31_REG(base) ((base)->PLL_CTRL31) -#define CCM_PLL_CTRL31_SET_REG(base) ((base)->PLL_CTRL31_SET) -#define CCM_PLL_CTRL31_CLR_REG(base) ((base)->PLL_CTRL31_CLR) -#define CCM_PLL_CTRL31_TOG_REG(base) ((base)->PLL_CTRL31_TOG) -#define CCM_PLL_CTRL32_REG(base) ((base)->PLL_CTRL32) -#define CCM_PLL_CTRL32_SET_REG(base) ((base)->PLL_CTRL32_SET) -#define CCM_PLL_CTRL32_CLR_REG(base) ((base)->PLL_CTRL32_CLR) -#define CCM_PLL_CTRL32_TOG_REG(base) ((base)->PLL_CTRL32_TOG) -#define CCM_CCGR0_REG(base) ((base)->CCGR0) -#define CCM_CCGR0_SET_REG(base) ((base)->CCGR0_SET) -#define CCM_CCGR0_CLR_REG(base) ((base)->CCGR0_CLR) -#define CCM_CCGR0_TOG_REG(base) ((base)->CCGR0_TOG) -#define CCM_CCGR1_REG(base) ((base)->CCGR1) -#define CCM_CCGR1_SET_REG(base) ((base)->CCGR1_SET) -#define CCM_CCGR1_CLR_REG(base) ((base)->CCGR1_CLR) -#define CCM_CCGR1_TOG_REG(base) ((base)->CCGR1_TOG) -#define CCM_CCGR2_REG(base) ((base)->CCGR2) -#define CCM_CCGR2_SET_REG(base) ((base)->CCGR2_SET) -#define CCM_CCGR2_CLR_REG(base) ((base)->CCGR2_CLR) -#define CCM_CCGR2_TOG_REG(base) ((base)->CCGR2_TOG) -#define CCM_CCGR3_REG(base) ((base)->CCGR3) -#define CCM_CCGR3_SET_REG(base) ((base)->CCGR3_SET) -#define CCM_CCGR3_CLR_REG(base) ((base)->CCGR3_CLR) -#define CCM_CCGR3_TOG_REG(base) ((base)->CCGR3_TOG) -#define CCM_CCGR4_REG(base) ((base)->CCGR4) -#define CCM_CCGR4_SET_REG(base) ((base)->CCGR4_SET) -#define CCM_CCGR4_CLR_REG(base) ((base)->CCGR4_CLR) -#define CCM_CCGR4_TOG_REG(base) ((base)->CCGR4_TOG) -#define CCM_CCGR5_REG(base) ((base)->CCGR5) -#define CCM_CCGR5_SET_REG(base) ((base)->CCGR5_SET) -#define CCM_CCGR5_CLR_REG(base) ((base)->CCGR5_CLR) -#define CCM_CCGR5_TOG_REG(base) ((base)->CCGR5_TOG) -#define CCM_CCGR6_REG(base) ((base)->CCGR6) -#define CCM_CCGR6_SET_REG(base) ((base)->CCGR6_SET) -#define CCM_CCGR6_CLR_REG(base) ((base)->CCGR6_CLR) -#define CCM_CCGR6_TOG_REG(base) ((base)->CCGR6_TOG) -#define CCM_CCGR7_REG(base) ((base)->CCGR7) -#define CCM_CCGR7_SET_REG(base) ((base)->CCGR7_SET) -#define CCM_CCGR7_CLR_REG(base) ((base)->CCGR7_CLR) -#define CCM_CCGR7_TOG_REG(base) ((base)->CCGR7_TOG) -#define CCM_CCGR8_REG(base) ((base)->CCGR8) -#define CCM_CCGR8_SET_REG(base) ((base)->CCGR8_SET) -#define CCM_CCGR8_CLR_REG(base) ((base)->CCGR8_CLR) -#define CCM_CCGR8_TOG_REG(base) ((base)->CCGR8_TOG) -#define CCM_CCGR9_REG(base) ((base)->CCGR9) -#define CCM_CCGR9_SET_REG(base) ((base)->CCGR9_SET) -#define CCM_CCGR9_CLR_REG(base) ((base)->CCGR9_CLR) -#define CCM_CCGR9_TOG_REG(base) ((base)->CCGR9_TOG) -#define CCM_CCGR10_REG(base) ((base)->CCGR10) -#define CCM_CCGR10_SET_REG(base) ((base)->CCGR10_SET) -#define CCM_CCGR10_CLR_REG(base) ((base)->CCGR10_CLR) -#define CCM_CCGR10_TOG_REG(base) ((base)->CCGR10_TOG) -#define CCM_CCGR11_REG(base) ((base)->CCGR11) -#define CCM_CCGR11_SET_REG(base) ((base)->CCGR11_SET) -#define CCM_CCGR11_CLR_REG(base) ((base)->CCGR11_CLR) -#define CCM_CCGR11_TOG_REG(base) ((base)->CCGR11_TOG) -#define CCM_CCGR12_REG(base) ((base)->CCGR12) -#define CCM_CCGR12_SET_REG(base) ((base)->CCGR12_SET) -#define CCM_CCGR12_CLR_REG(base) ((base)->CCGR12_CLR) -#define CCM_CCGR12_TOG_REG(base) ((base)->CCGR12_TOG) -#define CCM_CCGR13_REG(base) ((base)->CCGR13) -#define CCM_CCGR13_SET_REG(base) ((base)->CCGR13_SET) -#define CCM_CCGR13_CLR_REG(base) ((base)->CCGR13_CLR) -#define CCM_CCGR13_TOG_REG(base) ((base)->CCGR13_TOG) -#define CCM_CCGR14_REG(base) ((base)->CCGR14) -#define CCM_CCGR14_SET_REG(base) ((base)->CCGR14_SET) -#define CCM_CCGR14_CLR_REG(base) ((base)->CCGR14_CLR) -#define CCM_CCGR14_TOG_REG(base) ((base)->CCGR14_TOG) -#define CCM_CCGR15_REG(base) ((base)->CCGR15) -#define CCM_CCGR15_SET_REG(base) ((base)->CCGR15_SET) -#define CCM_CCGR15_CLR_REG(base) ((base)->CCGR15_CLR) -#define CCM_CCGR15_TOG_REG(base) ((base)->CCGR15_TOG) -#define CCM_CCGR16_REG(base) ((base)->CCGR16) -#define CCM_CCGR16_SET_REG(base) ((base)->CCGR16_SET) -#define CCM_CCGR16_CLR_REG(base) ((base)->CCGR16_CLR) -#define CCM_CCGR16_TOG_REG(base) ((base)->CCGR16_TOG) -#define CCM_CCGR17_REG(base) ((base)->CCGR17) -#define CCM_CCGR17_SET_REG(base) ((base)->CCGR17_SET) -#define CCM_CCGR17_CLR_REG(base) ((base)->CCGR17_CLR) -#define CCM_CCGR17_TOG_REG(base) ((base)->CCGR17_TOG) -#define CCM_CCGR18_REG(base) ((base)->CCGR18) -#define CCM_CCGR18_SET_REG(base) ((base)->CCGR18_SET) -#define CCM_CCGR18_CLR_REG(base) ((base)->CCGR18_CLR) -#define CCM_CCGR18_TOG_REG(base) ((base)->CCGR18_TOG) -#define CCM_CCGR19_REG(base) ((base)->CCGR19) -#define CCM_CCGR19_SET_REG(base) ((base)->CCGR19_SET) -#define CCM_CCGR19_CLR_REG(base) ((base)->CCGR19_CLR) -#define CCM_CCGR19_TOG_REG(base) ((base)->CCGR19_TOG) -#define CCM_CCGR20_REG(base) ((base)->CCGR20) -#define CCM_CCGR20_SET_REG(base) ((base)->CCGR20_SET) -#define CCM_CCGR20_CLR_REG(base) ((base)->CCGR20_CLR) -#define CCM_CCGR20_TOG_REG(base) ((base)->CCGR20_TOG) -#define CCM_CCGR21_REG(base) ((base)->CCGR21) -#define CCM_CCGR21_SET_REG(base) ((base)->CCGR21_SET) -#define CCM_CCGR21_CLR_REG(base) ((base)->CCGR21_CLR) -#define CCM_CCGR21_TOG_REG(base) ((base)->CCGR21_TOG) -#define CCM_CCGR22_REG(base) ((base)->CCGR22) -#define CCM_CCGR22_SET_REG(base) ((base)->CCGR22_SET) -#define CCM_CCGR22_CLR_REG(base) ((base)->CCGR22_CLR) -#define CCM_CCGR22_TOG_REG(base) ((base)->CCGR22_TOG) -#define CCM_CCGR23_REG(base) ((base)->CCGR23) -#define CCM_CCGR23_SET_REG(base) ((base)->CCGR23_SET) -#define CCM_CCGR23_CLR_REG(base) ((base)->CCGR23_CLR) -#define CCM_CCGR23_TOG_REG(base) ((base)->CCGR23_TOG) -#define CCM_CCGR24_REG(base) ((base)->CCGR24) -#define CCM_CCGR24_SET_REG(base) ((base)->CCGR24_SET) -#define CCM_CCGR24_CLR_REG(base) ((base)->CCGR24_CLR) -#define CCM_CCGR24_TOG_REG(base) ((base)->CCGR24_TOG) -#define CCM_CCGR25_REG(base) ((base)->CCGR25) -#define CCM_CCGR25_SET_REG(base) ((base)->CCGR25_SET) -#define CCM_CCGR25_CLR_REG(base) ((base)->CCGR25_CLR) -#define CCM_CCGR25_TOG_REG(base) ((base)->CCGR25_TOG) -#define CCM_CCGR26_REG(base) ((base)->CCGR26) -#define CCM_CCGR26_SET_REG(base) ((base)->CCGR26_SET) -#define CCM_CCGR26_CLR_REG(base) ((base)->CCGR26_CLR) -#define CCM_CCGR26_TOG_REG(base) ((base)->CCGR26_TOG) -#define CCM_CCGR27_REG(base) ((base)->CCGR27) -#define CCM_CCGR27_SET_REG(base) ((base)->CCGR27_SET) -#define CCM_CCGR27_CLR_REG(base) ((base)->CCGR27_CLR) -#define CCM_CCGR27_TOG_REG(base) ((base)->CCGR27_TOG) -#define CCM_CCGR28_REG(base) ((base)->CCGR28) -#define CCM_CCGR28_SET_REG(base) ((base)->CCGR28_SET) -#define CCM_CCGR28_CLR_REG(base) ((base)->CCGR28_CLR) -#define CCM_CCGR28_TOG_REG(base) ((base)->CCGR28_TOG) -#define CCM_CCGR29_REG(base) ((base)->CCGR29) -#define CCM_CCGR29_SET_REG(base) ((base)->CCGR29_SET) -#define CCM_CCGR29_CLR_REG(base) ((base)->CCGR29_CLR) -#define CCM_CCGR29_TOG_REG(base) ((base)->CCGR29_TOG) -#define CCM_CCGR30_REG(base) ((base)->CCGR30) -#define CCM_CCGR30_SET_REG(base) ((base)->CCGR30_SET) -#define CCM_CCGR30_CLR_REG(base) ((base)->CCGR30_CLR) -#define CCM_CCGR30_TOG_REG(base) ((base)->CCGR30_TOG) -#define CCM_CCGR31_REG(base) ((base)->CCGR31) -#define CCM_CCGR31_SET_REG(base) ((base)->CCGR31_SET) -#define CCM_CCGR31_CLR_REG(base) ((base)->CCGR31_CLR) -#define CCM_CCGR31_TOG_REG(base) ((base)->CCGR31_TOG) -#define CCM_CCGR32_REG(base) ((base)->CCGR32) -#define CCM_CCGR32_SET_REG(base) ((base)->CCGR32_SET) -#define CCM_CCGR32_CLR_REG(base) ((base)->CCGR32_CLR) -#define CCM_CCGR32_TOG_REG(base) ((base)->CCGR32_TOG) -#define CCM_CCGR33_REG(base) ((base)->CCGR33) -#define CCM_CCGR33_SET_REG(base) ((base)->CCGR33_SET) -#define CCM_CCGR33_CLR_REG(base) ((base)->CCGR33_CLR) -#define CCM_CCGR33_TOG_REG(base) ((base)->CCGR33_TOG) -#define CCM_CCGR34_REG(base) ((base)->CCGR34) -#define CCM_CCGR34_SET_REG(base) ((base)->CCGR34_SET) -#define CCM_CCGR34_CLR_REG(base) ((base)->CCGR34_CLR) -#define CCM_CCGR34_TOG_REG(base) ((base)->CCGR34_TOG) -#define CCM_CCGR35_REG(base) ((base)->CCGR35) -#define CCM_CCGR35_SET_REG(base) ((base)->CCGR35_SET) -#define CCM_CCGR35_CLR_REG(base) ((base)->CCGR35_CLR) -#define CCM_CCGR35_TOG_REG(base) ((base)->CCGR35_TOG) -#define CCM_CCGR36_REG(base) ((base)->CCGR36) -#define CCM_CCGR36_SET_REG(base) ((base)->CCGR36_SET) -#define CCM_CCGR36_CLR_REG(base) ((base)->CCGR36_CLR) -#define CCM_CCGR36_TOG_REG(base) ((base)->CCGR36_TOG) -#define CCM_CCGR37_REG(base) ((base)->CCGR37) -#define CCM_CCGR37_SET_REG(base) ((base)->CCGR37_SET) -#define CCM_CCGR37_CLR_REG(base) ((base)->CCGR37_CLR) -#define CCM_CCGR37_TOG_REG(base) ((base)->CCGR37_TOG) -#define CCM_CCGR38_REG(base) ((base)->CCGR38) -#define CCM_CCGR38_SET_REG(base) ((base)->CCGR38_SET) -#define CCM_CCGR38_CLR_REG(base) ((base)->CCGR38_CLR) -#define CCM_CCGR38_TOG_REG(base) ((base)->CCGR38_TOG) -#define CCM_CCGR39_REG(base) ((base)->CCGR39) -#define CCM_CCGR39_SET_REG(base) ((base)->CCGR39_SET) -#define CCM_CCGR39_CLR_REG(base) ((base)->CCGR39_CLR) -#define CCM_CCGR39_TOG_REG(base) ((base)->CCGR39_TOG) -#define CCM_CCGR40_REG(base) ((base)->CCGR40) -#define CCM_CCGR40_SET_REG(base) ((base)->CCGR40_SET) -#define CCM_CCGR40_CLR_REG(base) ((base)->CCGR40_CLR) -#define CCM_CCGR40_TOG_REG(base) ((base)->CCGR40_TOG) -#define CCM_CCGR41_REG(base) ((base)->CCGR41) -#define CCM_CCGR41_SET_REG(base) ((base)->CCGR41_SET) -#define CCM_CCGR41_CLR_REG(base) ((base)->CCGR41_CLR) -#define CCM_CCGR41_TOG_REG(base) ((base)->CCGR41_TOG) -#define CCM_CCGR42_REG(base) ((base)->CCGR42) -#define CCM_CCGR42_SET_REG(base) ((base)->CCGR42_SET) -#define CCM_CCGR42_CLR_REG(base) ((base)->CCGR42_CLR) -#define CCM_CCGR42_TOG_REG(base) ((base)->CCGR42_TOG) -#define CCM_CCGR43_REG(base) ((base)->CCGR43) -#define CCM_CCGR43_SET_REG(base) ((base)->CCGR43_SET) -#define CCM_CCGR43_CLR_REG(base) ((base)->CCGR43_CLR) -#define CCM_CCGR43_TOG_REG(base) ((base)->CCGR43_TOG) -#define CCM_CCGR44_REG(base) ((base)->CCGR44) -#define CCM_CCGR44_SET_REG(base) ((base)->CCGR44_SET) -#define CCM_CCGR44_CLR_REG(base) ((base)->CCGR44_CLR) -#define CCM_CCGR44_TOG_REG(base) ((base)->CCGR44_TOG) -#define CCM_CCGR45_REG(base) ((base)->CCGR45) -#define CCM_CCGR45_SET_REG(base) ((base)->CCGR45_SET) -#define CCM_CCGR45_CLR_REG(base) ((base)->CCGR45_CLR) -#define CCM_CCGR45_TOG_REG(base) ((base)->CCGR45_TOG) -#define CCM_CCGR46_REG(base) ((base)->CCGR46) -#define CCM_CCGR46_SET_REG(base) ((base)->CCGR46_SET) -#define CCM_CCGR46_CLR_REG(base) ((base)->CCGR46_CLR) -#define CCM_CCGR46_TOG_REG(base) ((base)->CCGR46_TOG) -#define CCM_CCGR47_REG(base) ((base)->CCGR47) -#define CCM_CCGR47_SET_REG(base) ((base)->CCGR47_SET) -#define CCM_CCGR47_CLR_REG(base) ((base)->CCGR47_CLR) -#define CCM_CCGR47_TOG_REG(base) ((base)->CCGR47_TOG) -#define CCM_CCGR48_REG(base) ((base)->CCGR48) -#define CCM_CCGR48_SET_REG(base) ((base)->CCGR48_SET) -#define CCM_CCGR48_CLR_REG(base) ((base)->CCGR48_CLR) -#define CCM_CCGR48_TOG_REG(base) ((base)->CCGR48_TOG) -#define CCM_CCGR49_REG(base) ((base)->CCGR49) -#define CCM_CCGR49_SET_REG(base) ((base)->CCGR49_SET) -#define CCM_CCGR49_CLR_REG(base) ((base)->CCGR49_CLR) -#define CCM_CCGR49_TOG_REG(base) ((base)->CCGR49_TOG) -#define CCM_CCGR50_REG(base) ((base)->CCGR50) -#define CCM_CCGR50_SET_REG(base) ((base)->CCGR50_SET) -#define CCM_CCGR50_CLR_REG(base) ((base)->CCGR50_CLR) -#define CCM_CCGR50_TOG_REG(base) ((base)->CCGR50_TOG) -#define CCM_CCGR51_REG(base) ((base)->CCGR51) -#define CCM_CCGR51_SET_REG(base) ((base)->CCGR51_SET) -#define CCM_CCGR51_CLR_REG(base) ((base)->CCGR51_CLR) -#define CCM_CCGR51_TOG_REG(base) ((base)->CCGR51_TOG) -#define CCM_CCGR52_REG(base) ((base)->CCGR52) -#define CCM_CCGR52_SET_REG(base) ((base)->CCGR52_SET) -#define CCM_CCGR52_CLR_REG(base) ((base)->CCGR52_CLR) -#define CCM_CCGR52_TOG_REG(base) ((base)->CCGR52_TOG) -#define CCM_CCGR53_REG(base) ((base)->CCGR53) -#define CCM_CCGR53_SET_REG(base) ((base)->CCGR53_SET) -#define CCM_CCGR53_CLR_REG(base) ((base)->CCGR53_CLR) -#define CCM_CCGR53_TOG_REG(base) ((base)->CCGR53_TOG) -#define CCM_CCGR54_REG(base) ((base)->CCGR54) -#define CCM_CCGR54_SET_REG(base) ((base)->CCGR54_SET) -#define CCM_CCGR54_CLR_REG(base) ((base)->CCGR54_CLR) -#define CCM_CCGR54_TOG_REG(base) ((base)->CCGR54_TOG) -#define CCM_CCGR55_REG(base) ((base)->CCGR55) -#define CCM_CCGR55_SET_REG(base) ((base)->CCGR55_SET) -#define CCM_CCGR55_CLR_REG(base) ((base)->CCGR55_CLR) -#define CCM_CCGR55_TOG_REG(base) ((base)->CCGR55_TOG) -#define CCM_CCGR56_REG(base) ((base)->CCGR56) -#define CCM_CCGR56_SET_REG(base) ((base)->CCGR56_SET) -#define CCM_CCGR56_CLR_REG(base) ((base)->CCGR56_CLR) -#define CCM_CCGR56_TOG_REG(base) ((base)->CCGR56_TOG) -#define CCM_CCGR57_REG(base) ((base)->CCGR57) -#define CCM_CCGR57_SET_REG(base) ((base)->CCGR57_SET) -#define CCM_CCGR57_CLR_REG(base) ((base)->CCGR57_CLR) -#define CCM_CCGR57_TOG_REG(base) ((base)->CCGR57_TOG) -#define CCM_CCGR58_REG(base) ((base)->CCGR58) -#define CCM_CCGR58_SET_REG(base) ((base)->CCGR58_SET) -#define CCM_CCGR58_CLR_REG(base) ((base)->CCGR58_CLR) -#define CCM_CCGR58_TOG_REG(base) ((base)->CCGR58_TOG) -#define CCM_CCGR59_REG(base) ((base)->CCGR59) -#define CCM_CCGR59_SET_REG(base) ((base)->CCGR59_SET) -#define CCM_CCGR59_CLR_REG(base) ((base)->CCGR59_CLR) -#define CCM_CCGR59_TOG_REG(base) ((base)->CCGR59_TOG) -#define CCM_CCGR60_REG(base) ((base)->CCGR60) -#define CCM_CCGR60_SET_REG(base) ((base)->CCGR60_SET) -#define CCM_CCGR60_CLR_REG(base) ((base)->CCGR60_CLR) -#define CCM_CCGR60_TOG_REG(base) ((base)->CCGR60_TOG) -#define CCM_CCGR61_REG(base) ((base)->CCGR61) -#define CCM_CCGR61_SET_REG(base) ((base)->CCGR61_SET) -#define CCM_CCGR61_CLR_REG(base) ((base)->CCGR61_CLR) -#define CCM_CCGR61_TOG_REG(base) ((base)->CCGR61_TOG) -#define CCM_CCGR62_REG(base) ((base)->CCGR62) -#define CCM_CCGR62_SET_REG(base) ((base)->CCGR62_SET) -#define CCM_CCGR62_CLR_REG(base) ((base)->CCGR62_CLR) -#define CCM_CCGR62_TOG_REG(base) ((base)->CCGR62_TOG) -#define CCM_CCGR63_REG(base) ((base)->CCGR63) -#define CCM_CCGR63_SET_REG(base) ((base)->CCGR63_SET) -#define CCM_CCGR63_CLR_REG(base) ((base)->CCGR63_CLR) -#define CCM_CCGR63_TOG_REG(base) ((base)->CCGR63_TOG) -#define CCM_CCGR64_REG(base) ((base)->CCGR64) -#define CCM_CCGR64_SET_REG(base) ((base)->CCGR64_SET) -#define CCM_CCGR64_CLR_REG(base) ((base)->CCGR64_CLR) -#define CCM_CCGR64_TOG_REG(base) ((base)->CCGR64_TOG) -#define CCM_CCGR65_REG(base) ((base)->CCGR65) -#define CCM_CCGR65_SET_REG(base) ((base)->CCGR65_SET) -#define CCM_CCGR65_CLR_REG(base) ((base)->CCGR65_CLR) -#define CCM_CCGR65_TOG_REG(base) ((base)->CCGR65_TOG) -#define CCM_CCGR66_REG(base) ((base)->CCGR66) -#define CCM_CCGR66_SET_REG(base) ((base)->CCGR66_SET) -#define CCM_CCGR66_CLR_REG(base) ((base)->CCGR66_CLR) -#define CCM_CCGR66_TOG_REG(base) ((base)->CCGR66_TOG) -#define CCM_CCGR67_REG(base) ((base)->CCGR67) -#define CCM_CCGR67_SET_REG(base) ((base)->CCGR67_SET) -#define CCM_CCGR67_CLR_REG(base) ((base)->CCGR67_CLR) -#define CCM_CCGR67_TOG_REG(base) ((base)->CCGR67_TOG) -#define CCM_CCGR68_REG(base) ((base)->CCGR68) -#define CCM_CCGR68_SET_REG(base) ((base)->CCGR68_SET) -#define CCM_CCGR68_CLR_REG(base) ((base)->CCGR68_CLR) -#define CCM_CCGR68_TOG_REG(base) ((base)->CCGR68_TOG) -#define CCM_CCGR69_REG(base) ((base)->CCGR69) -#define CCM_CCGR69_SET_REG(base) ((base)->CCGR69_SET) -#define CCM_CCGR69_CLR_REG(base) ((base)->CCGR69_CLR) -#define CCM_CCGR69_TOG_REG(base) ((base)->CCGR69_TOG) -#define CCM_CCGR70_REG(base) ((base)->CCGR70) -#define CCM_CCGR70_SET_REG(base) ((base)->CCGR70_SET) -#define CCM_CCGR70_CLR_REG(base) ((base)->CCGR70_CLR) -#define CCM_CCGR70_TOG_REG(base) ((base)->CCGR70_TOG) -#define CCM_CCGR71_REG(base) ((base)->CCGR71) -#define CCM_CCGR71_SET_REG(base) ((base)->CCGR71_SET) -#define CCM_CCGR71_CLR_REG(base) ((base)->CCGR71_CLR) -#define CCM_CCGR71_TOG_REG(base) ((base)->CCGR71_TOG) -#define CCM_CCGR72_REG(base) ((base)->CCGR72) -#define CCM_CCGR72_SET_REG(base) ((base)->CCGR72_SET) -#define CCM_CCGR72_CLR_REG(base) ((base)->CCGR72_CLR) -#define CCM_CCGR72_TOG_REG(base) ((base)->CCGR72_TOG) -#define CCM_CCGR73_REG(base) ((base)->CCGR73) -#define CCM_CCGR73_SET_REG(base) ((base)->CCGR73_SET) -#define CCM_CCGR73_CLR_REG(base) ((base)->CCGR73_CLR) -#define CCM_CCGR73_TOG_REG(base) ((base)->CCGR73_TOG) -#define CCM_CCGR74_REG(base) ((base)->CCGR74) -#define CCM_CCGR74_SET_REG(base) ((base)->CCGR74_SET) -#define CCM_CCGR74_CLR_REG(base) ((base)->CCGR74_CLR) -#define CCM_CCGR74_TOG_REG(base) ((base)->CCGR74_TOG) -#define CCM_CCGR75_REG(base) ((base)->CCGR75) -#define CCM_CCGR75_SET_REG(base) ((base)->CCGR75_SET) -#define CCM_CCGR75_CLR_REG(base) ((base)->CCGR75_CLR) -#define CCM_CCGR75_TOG_REG(base) ((base)->CCGR75_TOG) -#define CCM_CCGR76_REG(base) ((base)->CCGR76) -#define CCM_CCGR76_SET_REG(base) ((base)->CCGR76_SET) -#define CCM_CCGR76_CLR_REG(base) ((base)->CCGR76_CLR) -#define CCM_CCGR76_TOG_REG(base) ((base)->CCGR76_TOG) -#define CCM_CCGR77_REG(base) ((base)->CCGR77) -#define CCM_CCGR77_SET_REG(base) ((base)->CCGR77_SET) -#define CCM_CCGR77_CLR_REG(base) ((base)->CCGR77_CLR) -#define CCM_CCGR77_TOG_REG(base) ((base)->CCGR77_TOG) -#define CCM_CCGR78_REG(base) ((base)->CCGR78) -#define CCM_CCGR78_SET_REG(base) ((base)->CCGR78_SET) -#define CCM_CCGR78_CLR_REG(base) ((base)->CCGR78_CLR) -#define CCM_CCGR78_TOG_REG(base) ((base)->CCGR78_TOG) -#define CCM_CCGR79_REG(base) ((base)->CCGR79) -#define CCM_CCGR79_SET_REG(base) ((base)->CCGR79_SET) -#define CCM_CCGR79_CLR_REG(base) ((base)->CCGR79_CLR) -#define CCM_CCGR79_TOG_REG(base) ((base)->CCGR79_TOG) -#define CCM_CCGR80_REG(base) ((base)->CCGR80) -#define CCM_CCGR80_SET_REG(base) ((base)->CCGR80_SET) -#define CCM_CCGR80_CLR_REG(base) ((base)->CCGR80_CLR) -#define CCM_CCGR80_TOG_REG(base) ((base)->CCGR80_TOG) -#define CCM_CCGR81_REG(base) ((base)->CCGR81) -#define CCM_CCGR81_SET_REG(base) ((base)->CCGR81_SET) -#define CCM_CCGR81_CLR_REG(base) ((base)->CCGR81_CLR) -#define CCM_CCGR81_TOG_REG(base) ((base)->CCGR81_TOG) -#define CCM_CCGR82_REG(base) ((base)->CCGR82) -#define CCM_CCGR82_SET_REG(base) ((base)->CCGR82_SET) -#define CCM_CCGR82_CLR_REG(base) ((base)->CCGR82_CLR) -#define CCM_CCGR82_TOG_REG(base) ((base)->CCGR82_TOG) -#define CCM_CCGR83_REG(base) ((base)->CCGR83) -#define CCM_CCGR83_SET_REG(base) ((base)->CCGR83_SET) -#define CCM_CCGR83_CLR_REG(base) ((base)->CCGR83_CLR) -#define CCM_CCGR83_TOG_REG(base) ((base)->CCGR83_TOG) -#define CCM_CCGR84_REG(base) ((base)->CCGR84) -#define CCM_CCGR84_SET_REG(base) ((base)->CCGR84_SET) -#define CCM_CCGR84_CLR_REG(base) ((base)->CCGR84_CLR) -#define CCM_CCGR84_TOG_REG(base) ((base)->CCGR84_TOG) -#define CCM_CCGR85_REG(base) ((base)->CCGR85) -#define CCM_CCGR85_SET_REG(base) ((base)->CCGR85_SET) -#define CCM_CCGR85_CLR_REG(base) ((base)->CCGR85_CLR) -#define CCM_CCGR85_TOG_REG(base) ((base)->CCGR85_TOG) -#define CCM_CCGR86_REG(base) ((base)->CCGR86) -#define CCM_CCGR86_SET_REG(base) ((base)->CCGR86_SET) -#define CCM_CCGR86_CLR_REG(base) ((base)->CCGR86_CLR) -#define CCM_CCGR86_TOG_REG(base) ((base)->CCGR86_TOG) -#define CCM_CCGR87_REG(base) ((base)->CCGR87) -#define CCM_CCGR87_SET_REG(base) ((base)->CCGR87_SET) -#define CCM_CCGR87_CLR_REG(base) ((base)->CCGR87_CLR) -#define CCM_CCGR87_TOG_REG(base) ((base)->CCGR87_TOG) -#define CCM_CCGR88_REG(base) ((base)->CCGR88) -#define CCM_CCGR88_SET_REG(base) ((base)->CCGR88_SET) -#define CCM_CCGR88_CLR_REG(base) ((base)->CCGR88_CLR) -#define CCM_CCGR88_TOG_REG(base) ((base)->CCGR88_TOG) -#define CCM_CCGR89_REG(base) ((base)->CCGR89) -#define CCM_CCGR89_SET_REG(base) ((base)->CCGR89_SET) -#define CCM_CCGR89_CLR_REG(base) ((base)->CCGR89_CLR) -#define CCM_CCGR89_TOG_REG(base) ((base)->CCGR89_TOG) -#define CCM_CCGR90_REG(base) ((base)->CCGR90) -#define CCM_CCGR90_SET_REG(base) ((base)->CCGR90_SET) -#define CCM_CCGR90_CLR_REG(base) ((base)->CCGR90_CLR) -#define CCM_CCGR90_TOG_REG(base) ((base)->CCGR90_TOG) -#define CCM_CCGR91_REG(base) ((base)->CCGR91) -#define CCM_CCGR91_SET_REG(base) ((base)->CCGR91_SET) -#define CCM_CCGR91_CLR_REG(base) ((base)->CCGR91_CLR) -#define CCM_CCGR91_TOG_REG(base) ((base)->CCGR91_TOG) -#define CCM_CCGR92_REG(base) ((base)->CCGR92) -#define CCM_CCGR92_SET_REG(base) ((base)->CCGR92_SET) -#define CCM_CCGR92_CLR_REG(base) ((base)->CCGR92_CLR) -#define CCM_CCGR92_TOG_REG(base) ((base)->CCGR92_TOG) -#define CCM_CCGR93_REG(base) ((base)->CCGR93) -#define CCM_CCGR93_SET_REG(base) ((base)->CCGR93_SET) -#define CCM_CCGR93_CLR_REG(base) ((base)->CCGR93_CLR) -#define CCM_CCGR93_TOG_REG(base) ((base)->CCGR93_TOG) -#define CCM_CCGR94_REG(base) ((base)->CCGR94) -#define CCM_CCGR94_SET_REG(base) ((base)->CCGR94_SET) -#define CCM_CCGR94_CLR_REG(base) ((base)->CCGR94_CLR) -#define CCM_CCGR94_TOG_REG(base) ((base)->CCGR94_TOG) -#define CCM_CCGR95_REG(base) ((base)->CCGR95) -#define CCM_CCGR95_SET_REG(base) ((base)->CCGR95_SET) -#define CCM_CCGR95_CLR_REG(base) ((base)->CCGR95_CLR) -#define CCM_CCGR95_TOG_REG(base) ((base)->CCGR95_TOG) -#define CCM_CCGR96_REG(base) ((base)->CCGR96) -#define CCM_CCGR96_SET_REG(base) ((base)->CCGR96_SET) -#define CCM_CCGR96_CLR_REG(base) ((base)->CCGR96_CLR) -#define CCM_CCGR96_TOG_REG(base) ((base)->CCGR96_TOG) -#define CCM_CCGR97_REG(base) ((base)->CCGR97) -#define CCM_CCGR97_SET_REG(base) ((base)->CCGR97_SET) -#define CCM_CCGR97_CLR_REG(base) ((base)->CCGR97_CLR) -#define CCM_CCGR97_TOG_REG(base) ((base)->CCGR97_TOG) -#define CCM_CCGR98_REG(base) ((base)->CCGR98) -#define CCM_CCGR98_SET_REG(base) ((base)->CCGR98_SET) -#define CCM_CCGR98_CLR_REG(base) ((base)->CCGR98_CLR) -#define CCM_CCGR98_TOG_REG(base) ((base)->CCGR98_TOG) -#define CCM_CCGR99_REG(base) ((base)->CCGR99) -#define CCM_CCGR99_SET_REG(base) ((base)->CCGR99_SET) -#define CCM_CCGR99_CLR_REG(base) ((base)->CCGR99_CLR) -#define CCM_CCGR99_TOG_REG(base) ((base)->CCGR99_TOG) -#define CCM_CCGR100_REG(base) ((base)->CCGR100) -#define CCM_CCGR100_SET_REG(base) ((base)->CCGR100_SET) -#define CCM_CCGR100_CLR_REG(base) ((base)->CCGR100_CLR) -#define CCM_CCGR100_TOG_REG(base) ((base)->CCGR100_TOG) -#define CCM_CCGR101_REG(base) ((base)->CCGR101) -#define CCM_CCGR101_SET_REG(base) ((base)->CCGR101_SET) -#define CCM_CCGR101_CLR_REG(base) ((base)->CCGR101_CLR) -#define CCM_CCGR101_TOG_REG(base) ((base)->CCGR101_TOG) -#define CCM_CCGR102_REG(base) ((base)->CCGR102) -#define CCM_CCGR102_SET_REG(base) ((base)->CCGR102_SET) -#define CCM_CCGR102_CLR_REG(base) ((base)->CCGR102_CLR) -#define CCM_CCGR102_TOG_REG(base) ((base)->CCGR102_TOG) -#define CCM_CCGR103_REG(base) ((base)->CCGR103) -#define CCM_CCGR103_SET_REG(base) ((base)->CCGR103_SET) -#define CCM_CCGR103_CLR_REG(base) ((base)->CCGR103_CLR) -#define CCM_CCGR103_TOG_REG(base) ((base)->CCGR103_TOG) -#define CCM_CCGR104_REG(base) ((base)->CCGR104) -#define CCM_CCGR104_SET_REG(base) ((base)->CCGR104_SET) -#define CCM_CCGR104_CLR_REG(base) ((base)->CCGR104_CLR) -#define CCM_CCGR104_TOG_REG(base) ((base)->CCGR104_TOG) -#define CCM_CCGR105_REG(base) ((base)->CCGR105) -#define CCM_CCGR105_SET_REG(base) ((base)->CCGR105_SET) -#define CCM_CCGR105_CLR_REG(base) ((base)->CCGR105_CLR) -#define CCM_CCGR105_TOG_REG(base) ((base)->CCGR105_TOG) -#define CCM_CCGR106_REG(base) ((base)->CCGR106) -#define CCM_CCGR106_SET_REG(base) ((base)->CCGR106_SET) -#define CCM_CCGR106_CLR_REG(base) ((base)->CCGR106_CLR) -#define CCM_CCGR106_TOG_REG(base) ((base)->CCGR106_TOG) -#define CCM_CCGR107_REG(base) ((base)->CCGR107) -#define CCM_CCGR107_SET_REG(base) ((base)->CCGR107_SET) -#define CCM_CCGR107_CLR_REG(base) ((base)->CCGR107_CLR) -#define CCM_CCGR107_TOG_REG(base) ((base)->CCGR107_TOG) -#define CCM_CCGR108_REG(base) ((base)->CCGR108) -#define CCM_CCGR108_SET_REG(base) ((base)->CCGR108_SET) -#define CCM_CCGR108_CLR_REG(base) ((base)->CCGR108_CLR) -#define CCM_CCGR108_TOG_REG(base) ((base)->CCGR108_TOG) -#define CCM_CCGR109_REG(base) ((base)->CCGR109) -#define CCM_CCGR109_SET_REG(base) ((base)->CCGR109_SET) -#define CCM_CCGR109_CLR_REG(base) ((base)->CCGR109_CLR) -#define CCM_CCGR109_TOG_REG(base) ((base)->CCGR109_TOG) -#define CCM_CCGR110_REG(base) ((base)->CCGR110) -#define CCM_CCGR110_SET_REG(base) ((base)->CCGR110_SET) -#define CCM_CCGR110_CLR_REG(base) ((base)->CCGR110_CLR) -#define CCM_CCGR110_TOG_REG(base) ((base)->CCGR110_TOG) -#define CCM_CCGR111_REG(base) ((base)->CCGR111) -#define CCM_CCGR111_SET_REG(base) ((base)->CCGR111_SET) -#define CCM_CCGR111_CLR_REG(base) ((base)->CCGR111_CLR) -#define CCM_CCGR111_TOG_REG(base) ((base)->CCGR111_TOG) -#define CCM_CCGR112_REG(base) ((base)->CCGR112) -#define CCM_CCGR112_SET_REG(base) ((base)->CCGR112_SET) -#define CCM_CCGR112_CLR_REG(base) ((base)->CCGR112_CLR) -#define CCM_CCGR112_TOG_REG(base) ((base)->CCGR112_TOG) -#define CCM_CCGR113_REG(base) ((base)->CCGR113) -#define CCM_CCGR113_SET_REG(base) ((base)->CCGR113_SET) -#define CCM_CCGR113_CLR_REG(base) ((base)->CCGR113_CLR) -#define CCM_CCGR113_TOG_REG(base) ((base)->CCGR113_TOG) -#define CCM_CCGR114_REG(base) ((base)->CCGR114) -#define CCM_CCGR114_SET_REG(base) ((base)->CCGR114_SET) -#define CCM_CCGR114_CLR_REG(base) ((base)->CCGR114_CLR) -#define CCM_CCGR114_TOG_REG(base) ((base)->CCGR114_TOG) -#define CCM_CCGR115_REG(base) ((base)->CCGR115) -#define CCM_CCGR115_SET_REG(base) ((base)->CCGR115_SET) -#define CCM_CCGR115_CLR_REG(base) ((base)->CCGR115_CLR) -#define CCM_CCGR115_TOG_REG(base) ((base)->CCGR115_TOG) -#define CCM_CCGR116_REG(base) ((base)->CCGR116) -#define CCM_CCGR116_SET_REG(base) ((base)->CCGR116_SET) -#define CCM_CCGR116_CLR_REG(base) ((base)->CCGR116_CLR) -#define CCM_CCGR116_TOG_REG(base) ((base)->CCGR116_TOG) -#define CCM_CCGR117_REG(base) ((base)->CCGR117) -#define CCM_CCGR117_SET_REG(base) ((base)->CCGR117_SET) -#define CCM_CCGR117_CLR_REG(base) ((base)->CCGR117_CLR) -#define CCM_CCGR117_TOG_REG(base) ((base)->CCGR117_TOG) -#define CCM_CCGR118_REG(base) ((base)->CCGR118) -#define CCM_CCGR118_SET_REG(base) ((base)->CCGR118_SET) -#define CCM_CCGR118_CLR_REG(base) ((base)->CCGR118_CLR) -#define CCM_CCGR118_TOG_REG(base) ((base)->CCGR118_TOG) -#define CCM_CCGR119_REG(base) ((base)->CCGR119) -#define CCM_CCGR119_SET_REG(base) ((base)->CCGR119_SET) -#define CCM_CCGR119_CLR_REG(base) ((base)->CCGR119_CLR) -#define CCM_CCGR119_TOG_REG(base) ((base)->CCGR119_TOG) -#define CCM_CCGR120_REG(base) ((base)->CCGR120) -#define CCM_CCGR120_SET_REG(base) ((base)->CCGR120_SET) -#define CCM_CCGR120_CLR_REG(base) ((base)->CCGR120_CLR) -#define CCM_CCGR120_TOG_REG(base) ((base)->CCGR120_TOG) -#define CCM_CCGR121_REG(base) ((base)->CCGR121) -#define CCM_CCGR121_SET_REG(base) ((base)->CCGR121_SET) -#define CCM_CCGR121_CLR_REG(base) ((base)->CCGR121_CLR) -#define CCM_CCGR121_TOG_REG(base) ((base)->CCGR121_TOG) -#define CCM_CCGR122_REG(base) ((base)->CCGR122) -#define CCM_CCGR122_SET_REG(base) ((base)->CCGR122_SET) -#define CCM_CCGR122_CLR_REG(base) ((base)->CCGR122_CLR) -#define CCM_CCGR122_TOG_REG(base) ((base)->CCGR122_TOG) -#define CCM_CCGR123_REG(base) ((base)->CCGR123) -#define CCM_CCGR123_SET_REG(base) ((base)->CCGR123_SET) -#define CCM_CCGR123_CLR_REG(base) ((base)->CCGR123_CLR) -#define CCM_CCGR123_TOG_REG(base) ((base)->CCGR123_TOG) -#define CCM_CCGR124_REG(base) ((base)->CCGR124) -#define CCM_CCGR124_SET_REG(base) ((base)->CCGR124_SET) -#define CCM_CCGR124_CLR_REG(base) ((base)->CCGR124_CLR) -#define CCM_CCGR124_TOG_REG(base) ((base)->CCGR124_TOG) -#define CCM_CCGR125_REG(base) ((base)->CCGR125) -#define CCM_CCGR125_SET_REG(base) ((base)->CCGR125_SET) -#define CCM_CCGR125_CLR_REG(base) ((base)->CCGR125_CLR) -#define CCM_CCGR125_TOG_REG(base) ((base)->CCGR125_TOG) -#define CCM_CCGR126_REG(base) ((base)->CCGR126) -#define CCM_CCGR126_SET_REG(base) ((base)->CCGR126_SET) -#define CCM_CCGR126_CLR_REG(base) ((base)->CCGR126_CLR) -#define CCM_CCGR126_TOG_REG(base) ((base)->CCGR126_TOG) -#define CCM_CCGR127_REG(base) ((base)->CCGR127) -#define CCM_CCGR127_SET_REG(base) ((base)->CCGR127_SET) -#define CCM_CCGR127_CLR_REG(base) ((base)->CCGR127_CLR) -#define CCM_CCGR127_TOG_REG(base) ((base)->CCGR127_TOG) -#define CCM_CCGR128_REG(base) ((base)->CCGR128) -#define CCM_CCGR128_SET_REG(base) ((base)->CCGR128_SET) -#define CCM_CCGR128_CLR_REG(base) ((base)->CCGR128_CLR) -#define CCM_CCGR128_TOG_REG(base) ((base)->CCGR128_TOG) -#define CCM_CCGR129_REG(base) ((base)->CCGR129) -#define CCM_CCGR129_SET_REG(base) ((base)->CCGR129_SET) -#define CCM_CCGR129_CLR_REG(base) ((base)->CCGR129_CLR) -#define CCM_CCGR129_TOG_REG(base) ((base)->CCGR129_TOG) -#define CCM_CCGR130_REG(base) ((base)->CCGR130) -#define CCM_CCGR130_SET_REG(base) ((base)->CCGR130_SET) -#define CCM_CCGR130_CLR_REG(base) ((base)->CCGR130_CLR) -#define CCM_CCGR130_TOG_REG(base) ((base)->CCGR130_TOG) -#define CCM_CCGR131_REG(base) ((base)->CCGR131) -#define CCM_CCGR131_SET_REG(base) ((base)->CCGR131_SET) -#define CCM_CCGR131_CLR_REG(base) ((base)->CCGR131_CLR) -#define CCM_CCGR131_TOG_REG(base) ((base)->CCGR131_TOG) -#define CCM_CCGR132_REG(base) ((base)->CCGR132) -#define CCM_CCGR132_SET_REG(base) ((base)->CCGR132_SET) -#define CCM_CCGR132_CLR_REG(base) ((base)->CCGR132_CLR) -#define CCM_CCGR132_TOG_REG(base) ((base)->CCGR132_TOG) -#define CCM_CCGR133_REG(base) ((base)->CCGR133) -#define CCM_CCGR133_SET_REG(base) ((base)->CCGR133_SET) -#define CCM_CCGR133_CLR_REG(base) ((base)->CCGR133_CLR) -#define CCM_CCGR133_TOG_REG(base) ((base)->CCGR133_TOG) -#define CCM_CCGR134_REG(base) ((base)->CCGR134) -#define CCM_CCGR134_SET_REG(base) ((base)->CCGR134_SET) -#define CCM_CCGR134_CLR_REG(base) ((base)->CCGR134_CLR) -#define CCM_CCGR134_TOG_REG(base) ((base)->CCGR134_TOG) -#define CCM_CCGR135_REG(base) ((base)->CCGR135) -#define CCM_CCGR135_SET_REG(base) ((base)->CCGR135_SET) -#define CCM_CCGR135_CLR_REG(base) ((base)->CCGR135_CLR) -#define CCM_CCGR135_TOG_REG(base) ((base)->CCGR135_TOG) -#define CCM_CCGR136_REG(base) ((base)->CCGR136) -#define CCM_CCGR136_SET_REG(base) ((base)->CCGR136_SET) -#define CCM_CCGR136_CLR_REG(base) ((base)->CCGR136_CLR) -#define CCM_CCGR136_TOG_REG(base) ((base)->CCGR136_TOG) -#define CCM_CCGR137_REG(base) ((base)->CCGR137) -#define CCM_CCGR137_SET_REG(base) ((base)->CCGR137_SET) -#define CCM_CCGR137_CLR_REG(base) ((base)->CCGR137_CLR) -#define CCM_CCGR137_TOG_REG(base) ((base)->CCGR137_TOG) -#define CCM_CCGR138_REG(base) ((base)->CCGR138) -#define CCM_CCGR138_SET_REG(base) ((base)->CCGR138_SET) -#define CCM_CCGR138_CLR_REG(base) ((base)->CCGR138_CLR) -#define CCM_CCGR138_TOG_REG(base) ((base)->CCGR138_TOG) -#define CCM_CCGR139_REG(base) ((base)->CCGR139) -#define CCM_CCGR139_SET_REG(base) ((base)->CCGR139_SET) -#define CCM_CCGR139_CLR_REG(base) ((base)->CCGR139_CLR) -#define CCM_CCGR139_TOG_REG(base) ((base)->CCGR139_TOG) -#define CCM_CCGR140_REG(base) ((base)->CCGR140) -#define CCM_CCGR140_SET_REG(base) ((base)->CCGR140_SET) -#define CCM_CCGR140_CLR_REG(base) ((base)->CCGR140_CLR) -#define CCM_CCGR140_TOG_REG(base) ((base)->CCGR140_TOG) -#define CCM_CCGR141_REG(base) ((base)->CCGR141) -#define CCM_CCGR141_SET_REG(base) ((base)->CCGR141_SET) -#define CCM_CCGR141_CLR_REG(base) ((base)->CCGR141_CLR) -#define CCM_CCGR141_TOG_REG(base) ((base)->CCGR141_TOG) -#define CCM_CCGR142_REG(base) ((base)->CCGR142) -#define CCM_CCGR142_SET_REG(base) ((base)->CCGR142_SET) -#define CCM_CCGR142_CLR_REG(base) ((base)->CCGR142_CLR) -#define CCM_CCGR142_TOG_REG(base) ((base)->CCGR142_TOG) -#define CCM_CCGR143_REG(base) ((base)->CCGR143) -#define CCM_CCGR143_SET_REG(base) ((base)->CCGR143_SET) -#define CCM_CCGR143_CLR_REG(base) ((base)->CCGR143_CLR) -#define CCM_CCGR143_TOG_REG(base) ((base)->CCGR143_TOG) -#define CCM_CCGR144_REG(base) ((base)->CCGR144) -#define CCM_CCGR144_SET_REG(base) ((base)->CCGR144_SET) -#define CCM_CCGR144_CLR_REG(base) ((base)->CCGR144_CLR) -#define CCM_CCGR144_TOG_REG(base) ((base)->CCGR144_TOG) -#define CCM_CCGR145_REG(base) ((base)->CCGR145) -#define CCM_CCGR145_SET_REG(base) ((base)->CCGR145_SET) -#define CCM_CCGR145_CLR_REG(base) ((base)->CCGR145_CLR) -#define CCM_CCGR145_TOG_REG(base) ((base)->CCGR145_TOG) -#define CCM_CCGR146_REG(base) ((base)->CCGR146) -#define CCM_CCGR146_SET_REG(base) ((base)->CCGR146_SET) -#define CCM_CCGR146_CLR_REG(base) ((base)->CCGR146_CLR) -#define CCM_CCGR146_TOG_REG(base) ((base)->CCGR146_TOG) -#define CCM_CCGR147_REG(base) ((base)->CCGR147) -#define CCM_CCGR147_SET_REG(base) ((base)->CCGR147_SET) -#define CCM_CCGR147_CLR_REG(base) ((base)->CCGR147_CLR) -#define CCM_CCGR147_TOG_REG(base) ((base)->CCGR147_TOG) -#define CCM_CCGR148_REG(base) ((base)->CCGR148) -#define CCM_CCGR148_SET_REG(base) ((base)->CCGR148_SET) -#define CCM_CCGR148_CLR_REG(base) ((base)->CCGR148_CLR) -#define CCM_CCGR148_TOG_REG(base) ((base)->CCGR148_TOG) -#define CCM_CCGR149_REG(base) ((base)->CCGR149) -#define CCM_CCGR149_SET_REG(base) ((base)->CCGR149_SET) -#define CCM_CCGR149_CLR_REG(base) ((base)->CCGR149_CLR) -#define CCM_CCGR149_TOG_REG(base) ((base)->CCGR149_TOG) -#define CCM_CCGR150_REG(base) ((base)->CCGR150) -#define CCM_CCGR150_SET_REG(base) ((base)->CCGR150_SET) -#define CCM_CCGR150_CLR_REG(base) ((base)->CCGR150_CLR) -#define CCM_CCGR150_TOG_REG(base) ((base)->CCGR150_TOG) -#define CCM_CCGR151_REG(base) ((base)->CCGR151) -#define CCM_CCGR151_SET_REG(base) ((base)->CCGR151_SET) -#define CCM_CCGR151_CLR_REG(base) ((base)->CCGR151_CLR) -#define CCM_CCGR151_TOG_REG(base) ((base)->CCGR151_TOG) -#define CCM_CCGR152_REG(base) ((base)->CCGR152) -#define CCM_CCGR152_SET_REG(base) ((base)->CCGR152_SET) -#define CCM_CCGR152_CLR_REG(base) ((base)->CCGR152_CLR) -#define CCM_CCGR152_TOG_REG(base) ((base)->CCGR152_TOG) -#define CCM_CCGR153_REG(base) ((base)->CCGR153) -#define CCM_CCGR153_SET_REG(base) ((base)->CCGR153_SET) -#define CCM_CCGR153_CLR_REG(base) ((base)->CCGR153_CLR) -#define CCM_CCGR153_TOG_REG(base) ((base)->CCGR153_TOG) -#define CCM_CCGR154_REG(base) ((base)->CCGR154) -#define CCM_CCGR154_SET_REG(base) ((base)->CCGR154_SET) -#define CCM_CCGR154_CLR_REG(base) ((base)->CCGR154_CLR) -#define CCM_CCGR154_TOG_REG(base) ((base)->CCGR154_TOG) -#define CCM_CCGR155_REG(base) ((base)->CCGR155) -#define CCM_CCGR155_SET_REG(base) ((base)->CCGR155_SET) -#define CCM_CCGR155_CLR_REG(base) ((base)->CCGR155_CLR) -#define CCM_CCGR155_TOG_REG(base) ((base)->CCGR155_TOG) -#define CCM_CCGR156_REG(base) ((base)->CCGR156) -#define CCM_CCGR156_SET_REG(base) ((base)->CCGR156_SET) -#define CCM_CCGR156_CLR_REG(base) ((base)->CCGR156_CLR) -#define CCM_CCGR156_TOG_REG(base) ((base)->CCGR156_TOG) -#define CCM_CCGR157_REG(base) ((base)->CCGR157) -#define CCM_CCGR157_SET_REG(base) ((base)->CCGR157_SET) -#define CCM_CCGR157_CLR_REG(base) ((base)->CCGR157_CLR) -#define CCM_CCGR157_TOG_REG(base) ((base)->CCGR157_TOG) -#define CCM_CCGR158_REG(base) ((base)->CCGR158) -#define CCM_CCGR158_SET_REG(base) ((base)->CCGR158_SET) -#define CCM_CCGR158_CLR_REG(base) ((base)->CCGR158_CLR) -#define CCM_CCGR158_TOG_REG(base) ((base)->CCGR158_TOG) -#define CCM_CCGR159_REG(base) ((base)->CCGR159) -#define CCM_CCGR159_SET_REG(base) ((base)->CCGR159_SET) -#define CCM_CCGR159_CLR_REG(base) ((base)->CCGR159_CLR) -#define CCM_CCGR159_TOG_REG(base) ((base)->CCGR159_TOG) -#define CCM_CCGR160_REG(base) ((base)->CCGR160) -#define CCM_CCGR160_SET_REG(base) ((base)->CCGR160_SET) -#define CCM_CCGR160_CLR_REG(base) ((base)->CCGR160_CLR) -#define CCM_CCGR160_TOG_REG(base) ((base)->CCGR160_TOG) -#define CCM_CCGR161_REG(base) ((base)->CCGR161) -#define CCM_CCGR161_SET_REG(base) ((base)->CCGR161_SET) -#define CCM_CCGR161_CLR_REG(base) ((base)->CCGR161_CLR) -#define CCM_CCGR161_TOG_REG(base) ((base)->CCGR161_TOG) -#define CCM_CCGR162_REG(base) ((base)->CCGR162) -#define CCM_CCGR162_SET_REG(base) ((base)->CCGR162_SET) -#define CCM_CCGR162_CLR_REG(base) ((base)->CCGR162_CLR) -#define CCM_CCGR162_TOG_REG(base) ((base)->CCGR162_TOG) -#define CCM_CCGR163_REG(base) ((base)->CCGR163) -#define CCM_CCGR163_SET_REG(base) ((base)->CCGR163_SET) -#define CCM_CCGR163_CLR_REG(base) ((base)->CCGR163_CLR) -#define CCM_CCGR163_TOG_REG(base) ((base)->CCGR163_TOG) -#define CCM_CCGR164_REG(base) ((base)->CCGR164) -#define CCM_CCGR164_SET_REG(base) ((base)->CCGR164_SET) -#define CCM_CCGR164_CLR_REG(base) ((base)->CCGR164_CLR) -#define CCM_CCGR164_TOG_REG(base) ((base)->CCGR164_TOG) -#define CCM_CCGR165_REG(base) ((base)->CCGR165) -#define CCM_CCGR165_SET_REG(base) ((base)->CCGR165_SET) -#define CCM_CCGR165_CLR_REG(base) ((base)->CCGR165_CLR) -#define CCM_CCGR165_TOG_REG(base) ((base)->CCGR165_TOG) -#define CCM_CCGR166_REG(base) ((base)->CCGR166) -#define CCM_CCGR166_SET_REG(base) ((base)->CCGR166_SET) -#define CCM_CCGR166_CLR_REG(base) ((base)->CCGR166_CLR) -#define CCM_CCGR166_TOG_REG(base) ((base)->CCGR166_TOG) -#define CCM_CCGR167_REG(base) ((base)->CCGR167) -#define CCM_CCGR167_SET_REG(base) ((base)->CCGR167_SET) -#define CCM_CCGR167_CLR_REG(base) ((base)->CCGR167_CLR) -#define CCM_CCGR167_TOG_REG(base) ((base)->CCGR167_TOG) -#define CCM_CCGR168_REG(base) ((base)->CCGR168) -#define CCM_CCGR168_SET_REG(base) ((base)->CCGR168_SET) -#define CCM_CCGR168_CLR_REG(base) ((base)->CCGR168_CLR) -#define CCM_CCGR168_TOG_REG(base) ((base)->CCGR168_TOG) -#define CCM_CCGR169_REG(base) ((base)->CCGR169) -#define CCM_CCGR169_SET_REG(base) ((base)->CCGR169_SET) -#define CCM_CCGR169_CLR_REG(base) ((base)->CCGR169_CLR) -#define CCM_CCGR169_TOG_REG(base) ((base)->CCGR169_TOG) -#define CCM_CCGR170_REG(base) ((base)->CCGR170) -#define CCM_CCGR170_SET_REG(base) ((base)->CCGR170_SET) -#define CCM_CCGR170_CLR_REG(base) ((base)->CCGR170_CLR) -#define CCM_CCGR170_TOG_REG(base) ((base)->CCGR170_TOG) -#define CCM_CCGR171_REG(base) ((base)->CCGR171) -#define CCM_CCGR171_SET_REG(base) ((base)->CCGR171_SET) -#define CCM_CCGR171_CLR_REG(base) ((base)->CCGR171_CLR) -#define CCM_CCGR171_TOG_REG(base) ((base)->CCGR171_TOG) -#define CCM_CCGR172_REG(base) ((base)->CCGR172) -#define CCM_CCGR172_SET_REG(base) ((base)->CCGR172_SET) -#define CCM_CCGR172_CLR_REG(base) ((base)->CCGR172_CLR) -#define CCM_CCGR172_TOG_REG(base) ((base)->CCGR172_TOG) -#define CCM_CCGR173_REG(base) ((base)->CCGR173) -#define CCM_CCGR173_SET_REG(base) ((base)->CCGR173_SET) -#define CCM_CCGR173_CLR_REG(base) ((base)->CCGR173_CLR) -#define CCM_CCGR173_TOG_REG(base) ((base)->CCGR173_TOG) -#define CCM_CCGR174_REG(base) ((base)->CCGR174) -#define CCM_CCGR174_SET_REG(base) ((base)->CCGR174_SET) -#define CCM_CCGR174_CLR_REG(base) ((base)->CCGR174_CLR) -#define CCM_CCGR174_TOG_REG(base) ((base)->CCGR174_TOG) -#define CCM_CCGR175_REG(base) ((base)->CCGR175) -#define CCM_CCGR175_SET_REG(base) ((base)->CCGR175_SET) -#define CCM_CCGR175_CLR_REG(base) ((base)->CCGR175_CLR) -#define CCM_CCGR175_TOG_REG(base) ((base)->CCGR175_TOG) -#define CCM_CCGR176_REG(base) ((base)->CCGR176) -#define CCM_CCGR176_SET_REG(base) ((base)->CCGR176_SET) -#define CCM_CCGR176_CLR_REG(base) ((base)->CCGR176_CLR) -#define CCM_CCGR176_TOG_REG(base) ((base)->CCGR176_TOG) -#define CCM_CCGR177_REG(base) ((base)->CCGR177) -#define CCM_CCGR177_SET_REG(base) ((base)->CCGR177_SET) -#define CCM_CCGR177_CLR_REG(base) ((base)->CCGR177_CLR) -#define CCM_CCGR177_TOG_REG(base) ((base)->CCGR177_TOG) -#define CCM_CCGR178_REG(base) ((base)->CCGR178) -#define CCM_CCGR178_SET_REG(base) ((base)->CCGR178_SET) -#define CCM_CCGR178_CLR_REG(base) ((base)->CCGR178_CLR) -#define CCM_CCGR178_TOG_REG(base) ((base)->CCGR178_TOG) -#define CCM_CCGR179_REG(base) ((base)->CCGR179) -#define CCM_CCGR179_SET_REG(base) ((base)->CCGR179_SET) -#define CCM_CCGR179_CLR_REG(base) ((base)->CCGR179_CLR) -#define CCM_CCGR179_TOG_REG(base) ((base)->CCGR179_TOG) -#define CCM_CCGR180_REG(base) ((base)->CCGR180) -#define CCM_CCGR180_SET_REG(base) ((base)->CCGR180_SET) -#define CCM_CCGR180_CLR_REG(base) ((base)->CCGR180_CLR) -#define CCM_CCGR180_TOG_REG(base) ((base)->CCGR180_TOG) -#define CCM_CCGR181_REG(base) ((base)->CCGR181) -#define CCM_CCGR181_SET_REG(base) ((base)->CCGR181_SET) -#define CCM_CCGR181_CLR_REG(base) ((base)->CCGR181_CLR) -#define CCM_CCGR181_TOG_REG(base) ((base)->CCGR181_TOG) -#define CCM_CCGR182_REG(base) ((base)->CCGR182) -#define CCM_CCGR182_SET_REG(base) ((base)->CCGR182_SET) -#define CCM_CCGR182_CLR_REG(base) ((base)->CCGR182_CLR) -#define CCM_CCGR182_TOG_REG(base) ((base)->CCGR182_TOG) -#define CCM_CCGR183_REG(base) ((base)->CCGR183) -#define CCM_CCGR183_SET_REG(base) ((base)->CCGR183_SET) -#define CCM_CCGR183_CLR_REG(base) ((base)->CCGR183_CLR) -#define CCM_CCGR183_TOG_REG(base) ((base)->CCGR183_TOG) -#define CCM_CCGR184_REG(base) ((base)->CCGR184) -#define CCM_CCGR184_SET_REG(base) ((base)->CCGR184_SET) -#define CCM_CCGR184_CLR_REG(base) ((base)->CCGR184_CLR) -#define CCM_CCGR184_TOG_REG(base) ((base)->CCGR184_TOG) -#define CCM_CCGR185_REG(base) ((base)->CCGR185) -#define CCM_CCGR185_SET_REG(base) ((base)->CCGR185_SET) -#define CCM_CCGR185_CLR_REG(base) ((base)->CCGR185_CLR) -#define CCM_CCGR185_TOG_REG(base) ((base)->CCGR185_TOG) -#define CCM_CCGR186_REG(base) ((base)->CCGR186) -#define CCM_CCGR186_SET_REG(base) ((base)->CCGR186_SET) -#define CCM_CCGR186_CLR_REG(base) ((base)->CCGR186_CLR) -#define CCM_CCGR186_TOG_REG(base) ((base)->CCGR186_TOG) -#define CCM_CCGR187_REG(base) ((base)->CCGR187) -#define CCM_CCGR187_SET_REG(base) ((base)->CCGR187_SET) -#define CCM_CCGR187_CLR_REG(base) ((base)->CCGR187_CLR) -#define CCM_CCGR187_TOG_REG(base) ((base)->CCGR187_TOG) -#define CCM_CCGR188_REG(base) ((base)->CCGR188) -#define CCM_CCGR188_SET_REG(base) ((base)->CCGR188_SET) -#define CCM_CCGR188_CLR_REG(base) ((base)->CCGR188_CLR) -#define CCM_CCGR188_TOG_REG(base) ((base)->CCGR188_TOG) -#define CCM_CCGR189_REG(base) ((base)->CCGR189) -#define CCM_CCGR189_SET_REG(base) ((base)->CCGR189_SET) -#define CCM_CCGR189_CLR_REG(base) ((base)->CCGR189_CLR) -#define CCM_CCGR189_TOG_REG(base) ((base)->CCGR189_TOG) -#define CCM_CCGR190_REG(base) ((base)->CCGR190) -#define CCM_CCGR190_SET_REG(base) ((base)->CCGR190_SET) -#define CCM_CCGR190_CLR_REG(base) ((base)->CCGR190_CLR) -#define CCM_CCGR190_TOG_REG(base) ((base)->CCGR190_TOG) -#define CCM_TARGET_ROOT0_REG(base) ((base)->TARGET_ROOT0) -#define CCM_TARGET_ROOT0_SET_REG(base) ((base)->TARGET_ROOT0_SET) -#define CCM_TARGET_ROOT0_CLR_REG(base) ((base)->TARGET_ROOT0_CLR) -#define CCM_TARGET_ROOT0_TOG_REG(base) ((base)->TARGET_ROOT0_TOG) -#define CCM_POST0_REG(base) ((base)->POST0) -#define CCM_POST_ROOT0_SET_REG(base) ((base)->POST_ROOT0_SET) -#define CCM_POST_ROOT0_CLR_REG(base) ((base)->POST_ROOT0_CLR) -#define CCM_POST_ROOT0_TOG_REG(base) ((base)->POST_ROOT0_TOG) -#define CCM_PRE0_REG(base) ((base)->PRE0) -#define CCM_PRE_ROOT0_SET_REG(base) ((base)->PRE_ROOT0_SET) -#define CCM_PRE_ROOT0_CLR_REG(base) ((base)->PRE_ROOT0_CLR) -#define CCM_PRE_ROOT0_TOG_REG(base) ((base)->PRE_ROOT0_TOG) -#define CCM_ACCESS_CTRL0_REG(base) ((base)->ACCESS_CTRL0) -#define CCM_ACCESS_CTRL0_ROOT_SET_REG(base) ((base)->ACCESS_CTRL0_ROOT_SET) -#define CCM_ACCESS_CTRL0_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL0_ROOT_CLR) -#define CCM_ACCESS_CTRL0_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL0_ROOT_TOG) -#define CCM_TARGET_ROOT1_REG(base) ((base)->TARGET_ROOT1) -#define CCM_TARGET_ROOT1_SET_REG(base) ((base)->TARGET_ROOT1_SET) -#define CCM_TARGET_ROOT1_CLR_REG(base) ((base)->TARGET_ROOT1_CLR) -#define CCM_TARGET_ROOT1_TOG_REG(base) ((base)->TARGET_ROOT1_TOG) -#define CCM_POST1_REG(base) ((base)->POST1) -#define CCM_POST_ROOT1_SET_REG(base) ((base)->POST_ROOT1_SET) -#define CCM_POST_ROOT1_CLR_REG(base) ((base)->POST_ROOT1_CLR) -#define CCM_POST_ROOT1_TOG_REG(base) ((base)->POST_ROOT1_TOG) -#define CCM_PRE1_REG(base) ((base)->PRE1) -#define CCM_PRE_ROOT1_SET_REG(base) ((base)->PRE_ROOT1_SET) -#define CCM_PRE_ROOT1_CLR_REG(base) ((base)->PRE_ROOT1_CLR) -#define CCM_PRE_ROOT1_TOG_REG(base) ((base)->PRE_ROOT1_TOG) -#define CCM_ACCESS_CTRL1_REG(base) ((base)->ACCESS_CTRL1) -#define CCM_ACCESS_CTRL1_ROOT_SET_REG(base) ((base)->ACCESS_CTRL1_ROOT_SET) -#define CCM_ACCESS_CTRL1_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL1_ROOT_CLR) -#define CCM_ACCESS_CTRL1_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL1_ROOT_TOG) -#define CCM_TARGET_ROOT2_REG(base) ((base)->TARGET_ROOT2) -#define CCM_TARGET_ROOT2_SET_REG(base) ((base)->TARGET_ROOT2_SET) -#define CCM_TARGET_ROOT2_CLR_REG(base) ((base)->TARGET_ROOT2_CLR) -#define CCM_TARGET_ROOT2_TOG_REG(base) ((base)->TARGET_ROOT2_TOG) -#define CCM_POST2_REG(base) ((base)->POST2) -#define CCM_POST_ROOT2_SET_REG(base) ((base)->POST_ROOT2_SET) -#define CCM_POST_ROOT2_CLR_REG(base) ((base)->POST_ROOT2_CLR) -#define CCM_POST_ROOT2_TOG_REG(base) ((base)->POST_ROOT2_TOG) -#define CCM_PRE2_REG(base) ((base)->PRE2) -#define CCM_PRE_ROOT2_SET_REG(base) ((base)->PRE_ROOT2_SET) -#define CCM_PRE_ROOT2_CLR_REG(base) ((base)->PRE_ROOT2_CLR) -#define CCM_PRE_ROOT2_TOG_REG(base) ((base)->PRE_ROOT2_TOG) -#define CCM_ACCESS_CTRL2_REG(base) ((base)->ACCESS_CTRL2) -#define CCM_ACCESS_CTRL2_ROOT_SET_REG(base) ((base)->ACCESS_CTRL2_ROOT_SET) -#define CCM_ACCESS_CTRL2_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL2_ROOT_CLR) -#define CCM_ACCESS_CTRL2_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL2_ROOT_TOG) -#define CCM_TARGET_ROOT3_REG(base) ((base)->TARGET_ROOT3) -#define CCM_TARGET_ROOT3_SET_REG(base) ((base)->TARGET_ROOT3_SET) -#define CCM_TARGET_ROOT3_CLR_REG(base) ((base)->TARGET_ROOT3_CLR) -#define CCM_TARGET_ROOT3_TOG_REG(base) ((base)->TARGET_ROOT3_TOG) -#define CCM_POST3_REG(base) ((base)->POST3) -#define CCM_POST_ROOT3_SET_REG(base) ((base)->POST_ROOT3_SET) -#define CCM_POST_ROOT3_CLR_REG(base) ((base)->POST_ROOT3_CLR) -#define CCM_POST_ROOT3_TOG_REG(base) ((base)->POST_ROOT3_TOG) -#define CCM_PRE3_REG(base) ((base)->PRE3) -#define CCM_PRE_ROOT3_SET_REG(base) ((base)->PRE_ROOT3_SET) -#define CCM_PRE_ROOT3_CLR_REG(base) ((base)->PRE_ROOT3_CLR) -#define CCM_PRE_ROOT3_TOG_REG(base) ((base)->PRE_ROOT3_TOG) -#define CCM_ACCESS_CTRL3_REG(base) ((base)->ACCESS_CTRL3) -#define CCM_ACCESS_CTRL3_ROOT_SET_REG(base) ((base)->ACCESS_CTRL3_ROOT_SET) -#define CCM_ACCESS_CTRL3_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL3_ROOT_CLR) -#define CCM_ACCESS_CTRL3_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL3_ROOT_TOG) -#define CCM_TARGET_ROOT4_REG(base) ((base)->TARGET_ROOT4) -#define CCM_TARGET_ROOT4_SET_REG(base) ((base)->TARGET_ROOT4_SET) -#define CCM_TARGET_ROOT4_CLR_REG(base) ((base)->TARGET_ROOT4_CLR) -#define CCM_TARGET_ROOT4_TOG_REG(base) ((base)->TARGET_ROOT4_TOG) -#define CCM_POST4_REG(base) ((base)->POST4) -#define CCM_POST_ROOT4_SET_REG(base) ((base)->POST_ROOT4_SET) -#define CCM_POST_ROOT4_CLR_REG(base) ((base)->POST_ROOT4_CLR) -#define CCM_POST_ROOT4_TOG_REG(base) ((base)->POST_ROOT4_TOG) -#define CCM_PRE4_REG(base) ((base)->PRE4) -#define CCM_PRE_ROOT4_SET_REG(base) ((base)->PRE_ROOT4_SET) -#define CCM_PRE_ROOT4_CLR_REG(base) ((base)->PRE_ROOT4_CLR) -#define CCM_PRE_ROOT4_TOG_REG(base) ((base)->PRE_ROOT4_TOG) -#define CCM_ACCESS_CTRL4_REG(base) ((base)->ACCESS_CTRL4) -#define CCM_ACCESS_CTRL4_ROOT_SET_REG(base) ((base)->ACCESS_CTRL4_ROOT_SET) -#define CCM_ACCESS_CTRL4_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL4_ROOT_CLR) -#define CCM_ACCESS_CTRL4_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL4_ROOT_TOG) -#define CCM_TARGET_ROOT5_REG(base) ((base)->TARGET_ROOT5) -#define CCM_TARGET_ROOT5_SET_REG(base) ((base)->TARGET_ROOT5_SET) -#define CCM_TARGET_ROOT5_CLR_REG(base) ((base)->TARGET_ROOT5_CLR) -#define CCM_TARGET_ROOT5_TOG_REG(base) ((base)->TARGET_ROOT5_TOG) -#define CCM_POST5_REG(base) ((base)->POST5) -#define CCM_POST_ROOT5_SET_REG(base) ((base)->POST_ROOT5_SET) -#define CCM_POST_ROOT5_CLR_REG(base) ((base)->POST_ROOT5_CLR) -#define CCM_POST_ROOT5_TOG_REG(base) ((base)->POST_ROOT5_TOG) -#define CCM_PRE5_REG(base) ((base)->PRE5) -#define CCM_PRE_ROOT5_SET_REG(base) ((base)->PRE_ROOT5_SET) -#define CCM_PRE_ROOT5_CLR_REG(base) ((base)->PRE_ROOT5_CLR) -#define CCM_PRE_ROOT5_TOG_REG(base) ((base)->PRE_ROOT5_TOG) -#define CCM_ACCESS_CTRL5_REG(base) ((base)->ACCESS_CTRL5) -#define CCM_ACCESS_CTRL5_ROOT_SET_REG(base) ((base)->ACCESS_CTRL5_ROOT_SET) -#define CCM_ACCESS_CTRL5_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL5_ROOT_CLR) -#define CCM_ACCESS_CTRL5_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL5_ROOT_TOG) -#define CCM_TARGET_ROOT6_REG(base) ((base)->TARGET_ROOT6) -#define CCM_TARGET_ROOT6_SET_REG(base) ((base)->TARGET_ROOT6_SET) -#define CCM_TARGET_ROOT6_CLR_REG(base) ((base)->TARGET_ROOT6_CLR) -#define CCM_TARGET_ROOT6_TOG_REG(base) ((base)->TARGET_ROOT6_TOG) -#define CCM_POST6_REG(base) ((base)->POST6) -#define CCM_POST_ROOT6_SET_REG(base) ((base)->POST_ROOT6_SET) -#define CCM_POST_ROOT6_CLR_REG(base) ((base)->POST_ROOT6_CLR) -#define CCM_POST_ROOT6_TOG_REG(base) ((base)->POST_ROOT6_TOG) -#define CCM_PRE6_REG(base) ((base)->PRE6) -#define CCM_PRE_ROOT6_SET_REG(base) ((base)->PRE_ROOT6_SET) -#define CCM_PRE_ROOT6_CLR_REG(base) ((base)->PRE_ROOT6_CLR) -#define CCM_PRE_ROOT6_TOG_REG(base) ((base)->PRE_ROOT6_TOG) -#define CCM_ACCESS_CTRL6_REG(base) ((base)->ACCESS_CTRL6) -#define CCM_ACCESS_CTRL6_ROOT_SET_REG(base) ((base)->ACCESS_CTRL6_ROOT_SET) -#define CCM_ACCESS_CTRL6_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL6_ROOT_CLR) -#define CCM_ACCESS_CTRL6_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL6_ROOT_TOG) -#define CCM_TARGET_ROOT7_REG(base) ((base)->TARGET_ROOT7) -#define CCM_TARGET_ROOT7_SET_REG(base) ((base)->TARGET_ROOT7_SET) -#define CCM_TARGET_ROOT7_CLR_REG(base) ((base)->TARGET_ROOT7_CLR) -#define CCM_TARGET_ROOT7_TOG_REG(base) ((base)->TARGET_ROOT7_TOG) -#define CCM_POST7_REG(base) ((base)->POST7) -#define CCM_POST_ROOT7_SET_REG(base) ((base)->POST_ROOT7_SET) -#define CCM_POST_ROOT7_CLR_REG(base) ((base)->POST_ROOT7_CLR) -#define CCM_POST_ROOT7_TOG_REG(base) ((base)->POST_ROOT7_TOG) -#define CCM_PRE7_REG(base) ((base)->PRE7) -#define CCM_PRE_ROOT7_SET_REG(base) ((base)->PRE_ROOT7_SET) -#define CCM_PRE_ROOT7_CLR_REG(base) ((base)->PRE_ROOT7_CLR) -#define CCM_PRE_ROOT7_TOG_REG(base) ((base)->PRE_ROOT7_TOG) -#define CCM_ACCESS_CTRL7_REG(base) ((base)->ACCESS_CTRL7) -#define CCM_ACCESS_CTRL7_ROOT_SET_REG(base) ((base)->ACCESS_CTRL7_ROOT_SET) -#define CCM_ACCESS_CTRL7_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL7_ROOT_CLR) -#define CCM_ACCESS_CTRL7_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL7_ROOT_TOG) -#define CCM_TARGET_ROOT8_REG(base) ((base)->TARGET_ROOT8) -#define CCM_TARGET_ROOT8_SET_REG(base) ((base)->TARGET_ROOT8_SET) -#define CCM_TARGET_ROOT8_CLR_REG(base) ((base)->TARGET_ROOT8_CLR) -#define CCM_TARGET_ROOT8_TOG_REG(base) ((base)->TARGET_ROOT8_TOG) -#define CCM_POST8_REG(base) ((base)->POST8) -#define CCM_POST_ROOT8_SET_REG(base) ((base)->POST_ROOT8_SET) -#define CCM_POST_ROOT8_CLR_REG(base) ((base)->POST_ROOT8_CLR) -#define CCM_POST_ROOT8_TOG_REG(base) ((base)->POST_ROOT8_TOG) -#define CCM_PRE8_REG(base) ((base)->PRE8) -#define CCM_PRE_ROOT8_SET_REG(base) ((base)->PRE_ROOT8_SET) -#define CCM_PRE_ROOT8_CLR_REG(base) ((base)->PRE_ROOT8_CLR) -#define CCM_PRE_ROOT8_TOG_REG(base) ((base)->PRE_ROOT8_TOG) -#define CCM_ACCESS_CTRL8_REG(base) ((base)->ACCESS_CTRL8) -#define CCM_ACCESS_CTRL8_ROOT_SET_REG(base) ((base)->ACCESS_CTRL8_ROOT_SET) -#define CCM_ACCESS_CTRL8_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL8_ROOT_CLR) -#define CCM_ACCESS_CTRL8_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL8_ROOT_TOG) -#define CCM_TARGET_ROOT9_REG(base) ((base)->TARGET_ROOT9) -#define CCM_TARGET_ROOT9_SET_REG(base) ((base)->TARGET_ROOT9_SET) -#define CCM_TARGET_ROOT9_CLR_REG(base) ((base)->TARGET_ROOT9_CLR) -#define CCM_TARGET_ROOT9_TOG_REG(base) ((base)->TARGET_ROOT9_TOG) -#define CCM_POST9_REG(base) ((base)->POST9) -#define CCM_POST_ROOT9_SET_REG(base) ((base)->POST_ROOT9_SET) -#define CCM_POST_ROOT9_CLR_REG(base) ((base)->POST_ROOT9_CLR) -#define CCM_POST_ROOT9_TOG_REG(base) ((base)->POST_ROOT9_TOG) -#define CCM_PRE9_REG(base) ((base)->PRE9) -#define CCM_PRE_ROOT9_SET_REG(base) ((base)->PRE_ROOT9_SET) -#define CCM_PRE_ROOT9_CLR_REG(base) ((base)->PRE_ROOT9_CLR) -#define CCM_PRE_ROOT9_TOG_REG(base) ((base)->PRE_ROOT9_TOG) -#define CCM_ACCESS_CTRL9_REG(base) ((base)->ACCESS_CTRL9) -#define CCM_ACCESS_CTRL9_ROOT_SET_REG(base) ((base)->ACCESS_CTRL9_ROOT_SET) -#define CCM_ACCESS_CTRL9_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL9_ROOT_CLR) -#define CCM_ACCESS_CTRL9_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL9_ROOT_TOG) -#define CCM_TARGET_ROOT10_REG(base) ((base)->TARGET_ROOT10) -#define CCM_TARGET_ROOT10_SET_REG(base) ((base)->TARGET_ROOT10_SET) -#define CCM_TARGET_ROOT10_CLR_REG(base) ((base)->TARGET_ROOT10_CLR) -#define CCM_TARGET_ROOT10_TOG_REG(base) ((base)->TARGET_ROOT10_TOG) -#define CCM_POST10_REG(base) ((base)->POST10) -#define CCM_POST_ROOT10_SET_REG(base) ((base)->POST_ROOT10_SET) -#define CCM_POST_ROOT10_CLR_REG(base) ((base)->POST_ROOT10_CLR) -#define CCM_POST_ROOT10_TOG_REG(base) ((base)->POST_ROOT10_TOG) -#define CCM_PRE10_REG(base) ((base)->PRE10) -#define CCM_PRE_ROOT10_SET_REG(base) ((base)->PRE_ROOT10_SET) -#define CCM_PRE_ROOT10_CLR_REG(base) ((base)->PRE_ROOT10_CLR) -#define CCM_PRE_ROOT10_TOG_REG(base) ((base)->PRE_ROOT10_TOG) -#define CCM_ACCESS_CTRL10_REG(base) ((base)->ACCESS_CTRL10) -#define CCM_ACCESS_CTRL10_ROOT_SET_REG(base) ((base)->ACCESS_CTRL10_ROOT_SET) -#define CCM_ACCESS_CTRL10_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL10_ROOT_CLR) -#define CCM_ACCESS_CTRL10_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL10_ROOT_TOG) -#define CCM_TARGET_ROOT11_REG(base) ((base)->TARGET_ROOT11) -#define CCM_TARGET_ROOT11_SET_REG(base) ((base)->TARGET_ROOT11_SET) -#define CCM_TARGET_ROOT11_CLR_REG(base) ((base)->TARGET_ROOT11_CLR) -#define CCM_TARGET_ROOT11_TOG_REG(base) ((base)->TARGET_ROOT11_TOG) -#define CCM_POST11_REG(base) ((base)->POST11) -#define CCM_POST_ROOT11_SET_REG(base) ((base)->POST_ROOT11_SET) -#define CCM_POST_ROOT11_CLR_REG(base) ((base)->POST_ROOT11_CLR) -#define CCM_POST_ROOT11_TOG_REG(base) ((base)->POST_ROOT11_TOG) -#define CCM_PRE11_REG(base) ((base)->PRE11) -#define CCM_PRE_ROOT11_SET_REG(base) ((base)->PRE_ROOT11_SET) -#define CCM_PRE_ROOT11_CLR_REG(base) ((base)->PRE_ROOT11_CLR) -#define CCM_PRE_ROOT11_TOG_REG(base) ((base)->PRE_ROOT11_TOG) -#define CCM_ACCESS_CTRL11_REG(base) ((base)->ACCESS_CTRL11) -#define CCM_ACCESS_CTRL11_ROOT_SET_REG(base) ((base)->ACCESS_CTRL11_ROOT_SET) -#define CCM_ACCESS_CTRL11_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL11_ROOT_CLR) -#define CCM_ACCESS_CTRL11_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL11_ROOT_TOG) -#define CCM_TARGET_ROOT12_REG(base) ((base)->TARGET_ROOT12) -#define CCM_TARGET_ROOT12_SET_REG(base) ((base)->TARGET_ROOT12_SET) -#define CCM_TARGET_ROOT12_CLR_REG(base) ((base)->TARGET_ROOT12_CLR) -#define CCM_TARGET_ROOT12_TOG_REG(base) ((base)->TARGET_ROOT12_TOG) -#define CCM_POST12_REG(base) ((base)->POST12) -#define CCM_POST_ROOT12_SET_REG(base) ((base)->POST_ROOT12_SET) -#define CCM_POST_ROOT12_CLR_REG(base) ((base)->POST_ROOT12_CLR) -#define CCM_POST_ROOT12_TOG_REG(base) ((base)->POST_ROOT12_TOG) -#define CCM_PRE12_REG(base) ((base)->PRE12) -#define CCM_PRE_ROOT12_SET_REG(base) ((base)->PRE_ROOT12_SET) -#define CCM_PRE_ROOT12_CLR_REG(base) ((base)->PRE_ROOT12_CLR) -#define CCM_PRE_ROOT12_TOG_REG(base) ((base)->PRE_ROOT12_TOG) -#define CCM_ACCESS_CTRL12_REG(base) ((base)->ACCESS_CTRL12) -#define CCM_ACCESS_CTRL12_ROOT_SET_REG(base) ((base)->ACCESS_CTRL12_ROOT_SET) -#define CCM_ACCESS_CTRL12_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL12_ROOT_CLR) -#define CCM_ACCESS_CTRL12_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL12_ROOT_TOG) -#define CCM_TARGET_ROOT13_REG(base) ((base)->TARGET_ROOT13) -#define CCM_TARGET_ROOT13_SET_REG(base) ((base)->TARGET_ROOT13_SET) -#define CCM_TARGET_ROOT13_CLR_REG(base) ((base)->TARGET_ROOT13_CLR) -#define CCM_TARGET_ROOT13_TOG_REG(base) ((base)->TARGET_ROOT13_TOG) -#define CCM_POST13_REG(base) ((base)->POST13) -#define CCM_POST_ROOT13_SET_REG(base) ((base)->POST_ROOT13_SET) -#define CCM_POST_ROOT13_CLR_REG(base) ((base)->POST_ROOT13_CLR) -#define CCM_POST_ROOT13_TOG_REG(base) ((base)->POST_ROOT13_TOG) -#define CCM_PRE13_REG(base) ((base)->PRE13) -#define CCM_PRE_ROOT13_SET_REG(base) ((base)->PRE_ROOT13_SET) -#define CCM_PRE_ROOT13_CLR_REG(base) ((base)->PRE_ROOT13_CLR) -#define CCM_PRE_ROOT13_TOG_REG(base) ((base)->PRE_ROOT13_TOG) -#define CCM_ACCESS_CTRL13_REG(base) ((base)->ACCESS_CTRL13) -#define CCM_ACCESS_CTRL13_ROOT_SET_REG(base) ((base)->ACCESS_CTRL13_ROOT_SET) -#define CCM_ACCESS_CTRL13_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL13_ROOT_CLR) -#define CCM_ACCESS_CTRL13_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL13_ROOT_TOG) -#define CCM_TARGET_ROOT14_REG(base) ((base)->TARGET_ROOT14) -#define CCM_TARGET_ROOT14_SET_REG(base) ((base)->TARGET_ROOT14_SET) -#define CCM_TARGET_ROOT14_CLR_REG(base) ((base)->TARGET_ROOT14_CLR) -#define CCM_TARGET_ROOT14_TOG_REG(base) ((base)->TARGET_ROOT14_TOG) -#define CCM_POST14_REG(base) ((base)->POST14) -#define CCM_POST_ROOT14_SET_REG(base) ((base)->POST_ROOT14_SET) -#define CCM_POST_ROOT14_CLR_REG(base) ((base)->POST_ROOT14_CLR) -#define CCM_POST_ROOT14_TOG_REG(base) ((base)->POST_ROOT14_TOG) -#define CCM_PRE14_REG(base) ((base)->PRE14) -#define CCM_PRE_ROOT14_SET_REG(base) ((base)->PRE_ROOT14_SET) -#define CCM_PRE_ROOT14_CLR_REG(base) ((base)->PRE_ROOT14_CLR) -#define CCM_PRE_ROOT14_TOG_REG(base) ((base)->PRE_ROOT14_TOG) -#define CCM_ACCESS_CTRL14_REG(base) ((base)->ACCESS_CTRL14) -#define CCM_ACCESS_CTRL14_ROOT_SET_REG(base) ((base)->ACCESS_CTRL14_ROOT_SET) -#define CCM_ACCESS_CTRL14_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL14_ROOT_CLR) -#define CCM_ACCESS_CTRL14_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL14_ROOT_TOG) -#define CCM_TARGET_ROOT15_REG(base) ((base)->TARGET_ROOT15) -#define CCM_TARGET_ROOT15_SET_REG(base) ((base)->TARGET_ROOT15_SET) -#define CCM_TARGET_ROOT15_CLR_REG(base) ((base)->TARGET_ROOT15_CLR) -#define CCM_TARGET_ROOT15_TOG_REG(base) ((base)->TARGET_ROOT15_TOG) -#define CCM_POST15_REG(base) ((base)->POST15) -#define CCM_POST_ROOT15_SET_REG(base) ((base)->POST_ROOT15_SET) -#define CCM_POST_ROOT15_CLR_REG(base) ((base)->POST_ROOT15_CLR) -#define CCM_POST_ROOT15_TOG_REG(base) ((base)->POST_ROOT15_TOG) -#define CCM_PRE15_REG(base) ((base)->PRE15) -#define CCM_PRE_ROOT15_SET_REG(base) ((base)->PRE_ROOT15_SET) -#define CCM_PRE_ROOT15_CLR_REG(base) ((base)->PRE_ROOT15_CLR) -#define CCM_PRE_ROOT15_TOG_REG(base) ((base)->PRE_ROOT15_TOG) -#define CCM_ACCESS_CTRL15_REG(base) ((base)->ACCESS_CTRL15) -#define CCM_ACCESS_CTRL15_ROOT_SET_REG(base) ((base)->ACCESS_CTRL15_ROOT_SET) -#define CCM_ACCESS_CTRL15_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL15_ROOT_CLR) -#define CCM_ACCESS_CTRL15_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL15_ROOT_TOG) -#define CCM_TARGET_ROOT16_REG(base) ((base)->TARGET_ROOT16) -#define CCM_TARGET_ROOT16_SET_REG(base) ((base)->TARGET_ROOT16_SET) -#define CCM_TARGET_ROOT16_CLR_REG(base) ((base)->TARGET_ROOT16_CLR) -#define CCM_TARGET_ROOT16_TOG_REG(base) ((base)->TARGET_ROOT16_TOG) -#define CCM_POST16_REG(base) ((base)->POST16) -#define CCM_POST_ROOT16_SET_REG(base) ((base)->POST_ROOT16_SET) -#define CCM_POST_ROOT16_CLR_REG(base) ((base)->POST_ROOT16_CLR) -#define CCM_POST_ROOT16_TOG_REG(base) ((base)->POST_ROOT16_TOG) -#define CCM_PRE16_REG(base) ((base)->PRE16) -#define CCM_PRE_ROOT16_SET_REG(base) ((base)->PRE_ROOT16_SET) -#define CCM_PRE_ROOT16_CLR_REG(base) ((base)->PRE_ROOT16_CLR) -#define CCM_PRE_ROOT16_TOG_REG(base) ((base)->PRE_ROOT16_TOG) -#define CCM_ACCESS_CTRL16_REG(base) ((base)->ACCESS_CTRL16) -#define CCM_ACCESS_CTRL16_ROOT_SET_REG(base) ((base)->ACCESS_CTRL16_ROOT_SET) -#define CCM_ACCESS_CTRL16_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL16_ROOT_CLR) -#define CCM_ACCESS_CTRL16_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL16_ROOT_TOG) -#define CCM_TARGET_ROOT17_REG(base) ((base)->TARGET_ROOT17) -#define CCM_TARGET_ROOT17_SET_REG(base) ((base)->TARGET_ROOT17_SET) -#define CCM_TARGET_ROOT17_CLR_REG(base) ((base)->TARGET_ROOT17_CLR) -#define CCM_TARGET_ROOT17_TOG_REG(base) ((base)->TARGET_ROOT17_TOG) -#define CCM_POST17_REG(base) ((base)->POST17) -#define CCM_POST_ROOT17_SET_REG(base) ((base)->POST_ROOT17_SET) -#define CCM_POST_ROOT17_CLR_REG(base) ((base)->POST_ROOT17_CLR) -#define CCM_POST_ROOT17_TOG_REG(base) ((base)->POST_ROOT17_TOG) -#define CCM_PRE17_REG(base) ((base)->PRE17) -#define CCM_PRE_ROOT17_SET_REG(base) ((base)->PRE_ROOT17_SET) -#define CCM_PRE_ROOT17_CLR_REG(base) ((base)->PRE_ROOT17_CLR) -#define CCM_PRE_ROOT17_TOG_REG(base) ((base)->PRE_ROOT17_TOG) -#define CCM_ACCESS_CTRL17_REG(base) ((base)->ACCESS_CTRL17) -#define CCM_ACCESS_CTRL17_ROOT_SET_REG(base) ((base)->ACCESS_CTRL17_ROOT_SET) -#define CCM_ACCESS_CTRL17_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL17_ROOT_CLR) -#define CCM_ACCESS_CTRL17_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL17_ROOT_TOG) -#define CCM_TARGET_ROOT18_REG(base) ((base)->TARGET_ROOT18) -#define CCM_TARGET_ROOT18_SET_REG(base) ((base)->TARGET_ROOT18_SET) -#define CCM_TARGET_ROOT18_CLR_REG(base) ((base)->TARGET_ROOT18_CLR) -#define CCM_TARGET_ROOT18_TOG_REG(base) ((base)->TARGET_ROOT18_TOG) -#define CCM_POST18_REG(base) ((base)->POST18) -#define CCM_POST_ROOT18_SET_REG(base) ((base)->POST_ROOT18_SET) -#define CCM_POST_ROOT18_CLR_REG(base) ((base)->POST_ROOT18_CLR) -#define CCM_POST_ROOT18_TOG_REG(base) ((base)->POST_ROOT18_TOG) -#define CCM_PRE18_REG(base) ((base)->PRE18) -#define CCM_PRE_ROOT18_SET_REG(base) ((base)->PRE_ROOT18_SET) -#define CCM_PRE_ROOT18_CLR_REG(base) ((base)->PRE_ROOT18_CLR) -#define CCM_PRE_ROOT18_TOG_REG(base) ((base)->PRE_ROOT18_TOG) -#define CCM_ACCESS_CTRL18_REG(base) ((base)->ACCESS_CTRL18) -#define CCM_ACCESS_CTRL18_ROOT_SET_REG(base) ((base)->ACCESS_CTRL18_ROOT_SET) -#define CCM_ACCESS_CTRL18_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL18_ROOT_CLR) -#define CCM_ACCESS_CTRL18_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL18_ROOT_TOG) -#define CCM_TARGET_ROOT19_REG(base) ((base)->TARGET_ROOT19) -#define CCM_TARGET_ROOT19_SET_REG(base) ((base)->TARGET_ROOT19_SET) -#define CCM_TARGET_ROOT19_CLR_REG(base) ((base)->TARGET_ROOT19_CLR) -#define CCM_TARGET_ROOT19_TOG_REG(base) ((base)->TARGET_ROOT19_TOG) -#define CCM_POST19_REG(base) ((base)->POST19) -#define CCM_POST_ROOT19_SET_REG(base) ((base)->POST_ROOT19_SET) -#define CCM_POST_ROOT19_CLR_REG(base) ((base)->POST_ROOT19_CLR) -#define CCM_POST_ROOT19_TOG_REG(base) ((base)->POST_ROOT19_TOG) -#define CCM_PRE19_REG(base) ((base)->PRE19) -#define CCM_PRE_ROOT19_SET_REG(base) ((base)->PRE_ROOT19_SET) -#define CCM_PRE_ROOT19_CLR_REG(base) ((base)->PRE_ROOT19_CLR) -#define CCM_PRE_ROOT19_TOG_REG(base) ((base)->PRE_ROOT19_TOG) -#define CCM_ACCESS_CTRL19_REG(base) ((base)->ACCESS_CTRL19) -#define CCM_ACCESS_CTRL19_ROOT_SET_REG(base) ((base)->ACCESS_CTRL19_ROOT_SET) -#define CCM_ACCESS_CTRL19_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL19_ROOT_CLR) -#define CCM_ACCESS_CTRL19_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL19_ROOT_TOG) -#define CCM_TARGET_ROOT20_REG(base) ((base)->TARGET_ROOT20) -#define CCM_TARGET_ROOT20_SET_REG(base) ((base)->TARGET_ROOT20_SET) -#define CCM_TARGET_ROOT20_CLR_REG(base) ((base)->TARGET_ROOT20_CLR) -#define CCM_TARGET_ROOT20_TOG_REG(base) ((base)->TARGET_ROOT20_TOG) -#define CCM_POST20_REG(base) ((base)->POST20) -#define CCM_POST_ROOT20_SET_REG(base) ((base)->POST_ROOT20_SET) -#define CCM_POST_ROOT20_CLR_REG(base) ((base)->POST_ROOT20_CLR) -#define CCM_POST_ROOT20_TOG_REG(base) ((base)->POST_ROOT20_TOG) -#define CCM_PRE20_REG(base) ((base)->PRE20) -#define CCM_PRE_ROOT20_SET_REG(base) ((base)->PRE_ROOT20_SET) -#define CCM_PRE_ROOT20_CLR_REG(base) ((base)->PRE_ROOT20_CLR) -#define CCM_PRE_ROOT20_TOG_REG(base) ((base)->PRE_ROOT20_TOG) -#define CCM_ACCESS_CTRL20_REG(base) ((base)->ACCESS_CTRL20) -#define CCM_ACCESS_CTRL20_ROOT_SET_REG(base) ((base)->ACCESS_CTRL20_ROOT_SET) -#define CCM_ACCESS_CTRL20_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL20_ROOT_CLR) -#define CCM_ACCESS_CTRL20_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL20_ROOT_TOG) -#define CCM_TARGET_ROOT21_REG(base) ((base)->TARGET_ROOT21) -#define CCM_TARGET_ROOT21_SET_REG(base) ((base)->TARGET_ROOT21_SET) -#define CCM_TARGET_ROOT21_CLR_REG(base) ((base)->TARGET_ROOT21_CLR) -#define CCM_TARGET_ROOT21_TOG_REG(base) ((base)->TARGET_ROOT21_TOG) -#define CCM_POST21_REG(base) ((base)->POST21) -#define CCM_POST_ROOT21_SET_REG(base) ((base)->POST_ROOT21_SET) -#define CCM_POST_ROOT21_CLR_REG(base) ((base)->POST_ROOT21_CLR) -#define CCM_POST_ROOT21_TOG_REG(base) ((base)->POST_ROOT21_TOG) -#define CCM_PRE21_REG(base) ((base)->PRE21) -#define CCM_PRE_ROOT21_SET_REG(base) ((base)->PRE_ROOT21_SET) -#define CCM_PRE_ROOT21_CLR_REG(base) ((base)->PRE_ROOT21_CLR) -#define CCM_PRE_ROOT21_TOG_REG(base) ((base)->PRE_ROOT21_TOG) -#define CCM_ACCESS_CTRL21_REG(base) ((base)->ACCESS_CTRL21) -#define CCM_ACCESS_CTRL21_ROOT_SET_REG(base) ((base)->ACCESS_CTRL21_ROOT_SET) -#define CCM_ACCESS_CTRL21_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL21_ROOT_CLR) -#define CCM_ACCESS_CTRL21_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL21_ROOT_TOG) -#define CCM_TARGET_ROOT22_REG(base) ((base)->TARGET_ROOT22) -#define CCM_TARGET_ROOT22_SET_REG(base) ((base)->TARGET_ROOT22_SET) -#define CCM_TARGET_ROOT22_CLR_REG(base) ((base)->TARGET_ROOT22_CLR) -#define CCM_TARGET_ROOT22_TOG_REG(base) ((base)->TARGET_ROOT22_TOG) -#define CCM_POST22_REG(base) ((base)->POST22) -#define CCM_POST_ROOT22_SET_REG(base) ((base)->POST_ROOT22_SET) -#define CCM_POST_ROOT22_CLR_REG(base) ((base)->POST_ROOT22_CLR) -#define CCM_POST_ROOT22_TOG_REG(base) ((base)->POST_ROOT22_TOG) -#define CCM_PRE22_REG(base) ((base)->PRE22) -#define CCM_PRE_ROOT22_SET_REG(base) ((base)->PRE_ROOT22_SET) -#define CCM_PRE_ROOT22_CLR_REG(base) ((base)->PRE_ROOT22_CLR) -#define CCM_PRE_ROOT22_TOG_REG(base) ((base)->PRE_ROOT22_TOG) -#define CCM_ACCESS_CTRL22_REG(base) ((base)->ACCESS_CTRL22) -#define CCM_ACCESS_CTRL22_ROOT_SET_REG(base) ((base)->ACCESS_CTRL22_ROOT_SET) -#define CCM_ACCESS_CTRL22_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL22_ROOT_CLR) -#define CCM_ACCESS_CTRL22_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL22_ROOT_TOG) -#define CCM_TARGET_ROOT23_REG(base) ((base)->TARGET_ROOT23) -#define CCM_TARGET_ROOT23_SET_REG(base) ((base)->TARGET_ROOT23_SET) -#define CCM_TARGET_ROOT23_CLR_REG(base) ((base)->TARGET_ROOT23_CLR) -#define CCM_TARGET_ROOT23_TOG_REG(base) ((base)->TARGET_ROOT23_TOG) -#define CCM_POST23_REG(base) ((base)->POST23) -#define CCM_POST_ROOT23_SET_REG(base) ((base)->POST_ROOT23_SET) -#define CCM_POST_ROOT23_CLR_REG(base) ((base)->POST_ROOT23_CLR) -#define CCM_POST_ROOT23_TOG_REG(base) ((base)->POST_ROOT23_TOG) -#define CCM_PRE23_REG(base) ((base)->PRE23) -#define CCM_PRE_ROOT23_SET_REG(base) ((base)->PRE_ROOT23_SET) -#define CCM_PRE_ROOT23_CLR_REG(base) ((base)->PRE_ROOT23_CLR) -#define CCM_PRE_ROOT23_TOG_REG(base) ((base)->PRE_ROOT23_TOG) -#define CCM_ACCESS_CTRL23_REG(base) ((base)->ACCESS_CTRL23) -#define CCM_ACCESS_CTRL23_ROOT_SET_REG(base) ((base)->ACCESS_CTRL23_ROOT_SET) -#define CCM_ACCESS_CTRL23_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL23_ROOT_CLR) -#define CCM_ACCESS_CTRL23_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL23_ROOT_TOG) -#define CCM_TARGET_ROOT24_REG(base) ((base)->TARGET_ROOT24) -#define CCM_TARGET_ROOT24_SET_REG(base) ((base)->TARGET_ROOT24_SET) -#define CCM_TARGET_ROOT24_CLR_REG(base) ((base)->TARGET_ROOT24_CLR) -#define CCM_TARGET_ROOT24_TOG_REG(base) ((base)->TARGET_ROOT24_TOG) -#define CCM_POST24_REG(base) ((base)->POST24) -#define CCM_POST_ROOT24_SET_REG(base) ((base)->POST_ROOT24_SET) -#define CCM_POST_ROOT24_CLR_REG(base) ((base)->POST_ROOT24_CLR) -#define CCM_POST_ROOT24_TOG_REG(base) ((base)->POST_ROOT24_TOG) -#define CCM_PRE24_REG(base) ((base)->PRE24) -#define CCM_PRE_ROOT24_SET_REG(base) ((base)->PRE_ROOT24_SET) -#define CCM_PRE_ROOT24_CLR_REG(base) ((base)->PRE_ROOT24_CLR) -#define CCM_PRE_ROOT24_TOG_REG(base) ((base)->PRE_ROOT24_TOG) -#define CCM_ACCESS_CTRL24_REG(base) ((base)->ACCESS_CTRL24) -#define CCM_ACCESS_CTRL24_ROOT_SET_REG(base) ((base)->ACCESS_CTRL24_ROOT_SET) -#define CCM_ACCESS_CTRL24_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL24_ROOT_CLR) -#define CCM_ACCESS_CTRL24_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL24_ROOT_TOG) -#define CCM_TARGET_ROOT25_REG(base) ((base)->TARGET_ROOT25) -#define CCM_TARGET_ROOT25_SET_REG(base) ((base)->TARGET_ROOT25_SET) -#define CCM_TARGET_ROOT25_CLR_REG(base) ((base)->TARGET_ROOT25_CLR) -#define CCM_TARGET_ROOT25_TOG_REG(base) ((base)->TARGET_ROOT25_TOG) -#define CCM_POST25_REG(base) ((base)->POST25) -#define CCM_POST_ROOT25_SET_REG(base) ((base)->POST_ROOT25_SET) -#define CCM_POST_ROOT25_CLR_REG(base) ((base)->POST_ROOT25_CLR) -#define CCM_POST_ROOT25_TOG_REG(base) ((base)->POST_ROOT25_TOG) -#define CCM_PRE25_REG(base) ((base)->PRE25) -#define CCM_PRE_ROOT25_SET_REG(base) ((base)->PRE_ROOT25_SET) -#define CCM_PRE_ROOT25_CLR_REG(base) ((base)->PRE_ROOT25_CLR) -#define CCM_PRE_ROOT25_TOG_REG(base) ((base)->PRE_ROOT25_TOG) -#define CCM_ACCESS_CTRL25_REG(base) ((base)->ACCESS_CTRL25) -#define CCM_ACCESS_CTRL25_ROOT_SET_REG(base) ((base)->ACCESS_CTRL25_ROOT_SET) -#define CCM_ACCESS_CTRL25_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL25_ROOT_CLR) -#define CCM_ACCESS_CTRL25_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL25_ROOT_TOG) -#define CCM_TARGET_ROOT26_REG(base) ((base)->TARGET_ROOT26) -#define CCM_TARGET_ROOT26_SET_REG(base) ((base)->TARGET_ROOT26_SET) -#define CCM_TARGET_ROOT26_CLR_REG(base) ((base)->TARGET_ROOT26_CLR) -#define CCM_TARGET_ROOT26_TOG_REG(base) ((base)->TARGET_ROOT26_TOG) -#define CCM_POST26_REG(base) ((base)->POST26) -#define CCM_POST_ROOT26_SET_REG(base) ((base)->POST_ROOT26_SET) -#define CCM_POST_ROOT26_CLR_REG(base) ((base)->POST_ROOT26_CLR) -#define CCM_POST_ROOT26_TOG_REG(base) ((base)->POST_ROOT26_TOG) -#define CCM_PRE26_REG(base) ((base)->PRE26) -#define CCM_PRE_ROOT26_SET_REG(base) ((base)->PRE_ROOT26_SET) -#define CCM_PRE_ROOT26_CLR_REG(base) ((base)->PRE_ROOT26_CLR) -#define CCM_PRE_ROOT26_TOG_REG(base) ((base)->PRE_ROOT26_TOG) -#define CCM_ACCESS_CTRL26_REG(base) ((base)->ACCESS_CTRL26) -#define CCM_ACCESS_CTRL26_ROOT_SET_REG(base) ((base)->ACCESS_CTRL26_ROOT_SET) -#define CCM_ACCESS_CTRL26_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL26_ROOT_CLR) -#define CCM_ACCESS_CTRL26_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL26_ROOT_TOG) -#define CCM_TARGET_ROOT27_REG(base) ((base)->TARGET_ROOT27) -#define CCM_TARGET_ROOT27_SET_REG(base) ((base)->TARGET_ROOT27_SET) -#define CCM_TARGET_ROOT27_CLR_REG(base) ((base)->TARGET_ROOT27_CLR) -#define CCM_TARGET_ROOT27_TOG_REG(base) ((base)->TARGET_ROOT27_TOG) -#define CCM_POST27_REG(base) ((base)->POST27) -#define CCM_POST_ROOT27_SET_REG(base) ((base)->POST_ROOT27_SET) -#define CCM_POST_ROOT27_CLR_REG(base) ((base)->POST_ROOT27_CLR) -#define CCM_POST_ROOT27_TOG_REG(base) ((base)->POST_ROOT27_TOG) -#define CCM_PRE27_REG(base) ((base)->PRE27) -#define CCM_PRE_ROOT27_SET_REG(base) ((base)->PRE_ROOT27_SET) -#define CCM_PRE_ROOT27_CLR_REG(base) ((base)->PRE_ROOT27_CLR) -#define CCM_PRE_ROOT27_TOG_REG(base) ((base)->PRE_ROOT27_TOG) -#define CCM_ACCESS_CTRL27_REG(base) ((base)->ACCESS_CTRL27) -#define CCM_ACCESS_CTRL27_ROOT_SET_REG(base) ((base)->ACCESS_CTRL27_ROOT_SET) -#define CCM_ACCESS_CTRL27_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL27_ROOT_CLR) -#define CCM_ACCESS_CTRL27_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL27_ROOT_TOG) -#define CCM_TARGET_ROOT28_REG(base) ((base)->TARGET_ROOT28) -#define CCM_TARGET_ROOT28_SET_REG(base) ((base)->TARGET_ROOT28_SET) -#define CCM_TARGET_ROOT28_CLR_REG(base) ((base)->TARGET_ROOT28_CLR) -#define CCM_TARGET_ROOT28_TOG_REG(base) ((base)->TARGET_ROOT28_TOG) -#define CCM_POST28_REG(base) ((base)->POST28) -#define CCM_POST_ROOT28_SET_REG(base) ((base)->POST_ROOT28_SET) -#define CCM_POST_ROOT28_CLR_REG(base) ((base)->POST_ROOT28_CLR) -#define CCM_POST_ROOT28_TOG_REG(base) ((base)->POST_ROOT28_TOG) -#define CCM_PRE28_REG(base) ((base)->PRE28) -#define CCM_PRE_ROOT28_SET_REG(base) ((base)->PRE_ROOT28_SET) -#define CCM_PRE_ROOT28_CLR_REG(base) ((base)->PRE_ROOT28_CLR) -#define CCM_PRE_ROOT28_TOG_REG(base) ((base)->PRE_ROOT28_TOG) -#define CCM_ACCESS_CTRL28_REG(base) ((base)->ACCESS_CTRL28) -#define CCM_ACCESS_CTRL28_ROOT_SET_REG(base) ((base)->ACCESS_CTRL28_ROOT_SET) -#define CCM_ACCESS_CTRL28_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL28_ROOT_CLR) -#define CCM_ACCESS_CTRL28_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL28_ROOT_TOG) -#define CCM_TARGET_ROOT29_REG(base) ((base)->TARGET_ROOT29) -#define CCM_TARGET_ROOT29_SET_REG(base) ((base)->TARGET_ROOT29_SET) -#define CCM_TARGET_ROOT29_CLR_REG(base) ((base)->TARGET_ROOT29_CLR) -#define CCM_TARGET_ROOT29_TOG_REG(base) ((base)->TARGET_ROOT29_TOG) -#define CCM_POST29_REG(base) ((base)->POST29) -#define CCM_POST_ROOT29_SET_REG(base) ((base)->POST_ROOT29_SET) -#define CCM_POST_ROOT29_CLR_REG(base) ((base)->POST_ROOT29_CLR) -#define CCM_POST_ROOT29_TOG_REG(base) ((base)->POST_ROOT29_TOG) -#define CCM_PRE29_REG(base) ((base)->PRE29) -#define CCM_PRE_ROOT29_SET_REG(base) ((base)->PRE_ROOT29_SET) -#define CCM_PRE_ROOT29_CLR_REG(base) ((base)->PRE_ROOT29_CLR) -#define CCM_PRE_ROOT29_TOG_REG(base) ((base)->PRE_ROOT29_TOG) -#define CCM_ACCESS_CTRL29_REG(base) ((base)->ACCESS_CTRL29) -#define CCM_ACCESS_CTRL29_ROOT_SET_REG(base) ((base)->ACCESS_CTRL29_ROOT_SET) -#define CCM_ACCESS_CTRL29_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL29_ROOT_CLR) -#define CCM_ACCESS_CTRL29_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL29_ROOT_TOG) -#define CCM_TARGET_ROOT30_REG(base) ((base)->TARGET_ROOT30) -#define CCM_TARGET_ROOT30_SET_REG(base) ((base)->TARGET_ROOT30_SET) -#define CCM_TARGET_ROOT30_CLR_REG(base) ((base)->TARGET_ROOT30_CLR) -#define CCM_TARGET_ROOT30_TOG_REG(base) ((base)->TARGET_ROOT30_TOG) -#define CCM_POST30_REG(base) ((base)->POST30) -#define CCM_POST_ROOT30_SET_REG(base) ((base)->POST_ROOT30_SET) -#define CCM_POST_ROOT30_CLR_REG(base) ((base)->POST_ROOT30_CLR) -#define CCM_POST_ROOT30_TOG_REG(base) ((base)->POST_ROOT30_TOG) -#define CCM_PRE30_REG(base) ((base)->PRE30) -#define CCM_PRE_ROOT30_SET_REG(base) ((base)->PRE_ROOT30_SET) -#define CCM_PRE_ROOT30_CLR_REG(base) ((base)->PRE_ROOT30_CLR) -#define CCM_PRE_ROOT30_TOG_REG(base) ((base)->PRE_ROOT30_TOG) -#define CCM_ACCESS_CTRL30_REG(base) ((base)->ACCESS_CTRL30) -#define CCM_ACCESS_CTRL30_ROOT_SET_REG(base) ((base)->ACCESS_CTRL30_ROOT_SET) -#define CCM_ACCESS_CTRL30_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL30_ROOT_CLR) -#define CCM_ACCESS_CTRL30_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL30_ROOT_TOG) -#define CCM_TARGET_ROOT31_REG(base) ((base)->TARGET_ROOT31) -#define CCM_TARGET_ROOT31_SET_REG(base) ((base)->TARGET_ROOT31_SET) -#define CCM_TARGET_ROOT31_CLR_REG(base) ((base)->TARGET_ROOT31_CLR) -#define CCM_TARGET_ROOT31_TOG_REG(base) ((base)->TARGET_ROOT31_TOG) -#define CCM_POST31_REG(base) ((base)->POST31) -#define CCM_POST_ROOT31_SET_REG(base) ((base)->POST_ROOT31_SET) -#define CCM_POST_ROOT31_CLR_REG(base) ((base)->POST_ROOT31_CLR) -#define CCM_POST_ROOT31_TOG_REG(base) ((base)->POST_ROOT31_TOG) -#define CCM_PRE31_REG(base) ((base)->PRE31) -#define CCM_PRE_ROOT31_SET_REG(base) ((base)->PRE_ROOT31_SET) -#define CCM_PRE_ROOT31_CLR_REG(base) ((base)->PRE_ROOT31_CLR) -#define CCM_PRE_ROOT31_TOG_REG(base) ((base)->PRE_ROOT31_TOG) -#define CCM_ACCESS_CTRL31_REG(base) ((base)->ACCESS_CTRL31) -#define CCM_ACCESS_CTRL31_ROOT_SET_REG(base) ((base)->ACCESS_CTRL31_ROOT_SET) -#define CCM_ACCESS_CTRL31_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL31_ROOT_CLR) -#define CCM_ACCESS_CTRL31_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL31_ROOT_TOG) -#define CCM_TARGET_ROOT32_REG(base) ((base)->TARGET_ROOT32) -#define CCM_TARGET_ROOT32_SET_REG(base) ((base)->TARGET_ROOT32_SET) -#define CCM_TARGET_ROOT32_CLR_REG(base) ((base)->TARGET_ROOT32_CLR) -#define CCM_TARGET_ROOT32_TOG_REG(base) ((base)->TARGET_ROOT32_TOG) -#define CCM_POST32_REG(base) ((base)->POST32) -#define CCM_POST_ROOT32_SET_REG(base) ((base)->POST_ROOT32_SET) -#define CCM_POST_ROOT32_CLR_REG(base) ((base)->POST_ROOT32_CLR) -#define CCM_POST_ROOT32_TOG_REG(base) ((base)->POST_ROOT32_TOG) -#define CCM_PRE32_REG(base) ((base)->PRE32) -#define CCM_PRE_ROOT32_SET_REG(base) ((base)->PRE_ROOT32_SET) -#define CCM_PRE_ROOT32_CLR_REG(base) ((base)->PRE_ROOT32_CLR) -#define CCM_PRE_ROOT32_TOG_REG(base) ((base)->PRE_ROOT32_TOG) -#define CCM_ACCESS_CTRL32_REG(base) ((base)->ACCESS_CTRL32) -#define CCM_ACCESS_CTRL32_ROOT_SET_REG(base) ((base)->ACCESS_CTRL32_ROOT_SET) -#define CCM_ACCESS_CTRL32_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL32_ROOT_CLR) -#define CCM_ACCESS_CTRL32_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL32_ROOT_TOG) -#define CCM_TARGET_ROOT33_REG(base) ((base)->TARGET_ROOT33) -#define CCM_TARGET_ROOT33_SET_REG(base) ((base)->TARGET_ROOT33_SET) -#define CCM_TARGET_ROOT33_CLR_REG(base) ((base)->TARGET_ROOT33_CLR) -#define CCM_TARGET_ROOT33_TOG_REG(base) ((base)->TARGET_ROOT33_TOG) -#define CCM_POST33_REG(base) ((base)->POST33) -#define CCM_POST_ROOT33_SET_REG(base) ((base)->POST_ROOT33_SET) -#define CCM_POST_ROOT33_CLR_REG(base) ((base)->POST_ROOT33_CLR) -#define CCM_POST_ROOT33_TOG_REG(base) ((base)->POST_ROOT33_TOG) -#define CCM_PRE33_REG(base) ((base)->PRE33) -#define CCM_PRE_ROOT33_SET_REG(base) ((base)->PRE_ROOT33_SET) -#define CCM_PRE_ROOT33_CLR_REG(base) ((base)->PRE_ROOT33_CLR) -#define CCM_PRE_ROOT33_TOG_REG(base) ((base)->PRE_ROOT33_TOG) -#define CCM_ACCESS_CTRL33_REG(base) ((base)->ACCESS_CTRL33) -#define CCM_ACCESS_CTRL33_ROOT_SET_REG(base) ((base)->ACCESS_CTRL33_ROOT_SET) -#define CCM_ACCESS_CTRL33_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL33_ROOT_CLR) -#define CCM_ACCESS_CTRL33_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL33_ROOT_TOG) -#define CCM_TARGET_ROOT34_REG(base) ((base)->TARGET_ROOT34) -#define CCM_TARGET_ROOT34_SET_REG(base) ((base)->TARGET_ROOT34_SET) -#define CCM_TARGET_ROOT34_CLR_REG(base) ((base)->TARGET_ROOT34_CLR) -#define CCM_TARGET_ROOT34_TOG_REG(base) ((base)->TARGET_ROOT34_TOG) -#define CCM_POST34_REG(base) ((base)->POST34) -#define CCM_POST_ROOT34_SET_REG(base) ((base)->POST_ROOT34_SET) -#define CCM_POST_ROOT34_CLR_REG(base) ((base)->POST_ROOT34_CLR) -#define CCM_POST_ROOT34_TOG_REG(base) ((base)->POST_ROOT34_TOG) -#define CCM_PRE34_REG(base) ((base)->PRE34) -#define CCM_PRE_ROOT34_SET_REG(base) ((base)->PRE_ROOT34_SET) -#define CCM_PRE_ROOT34_CLR_REG(base) ((base)->PRE_ROOT34_CLR) -#define CCM_PRE_ROOT34_TOG_REG(base) ((base)->PRE_ROOT34_TOG) -#define CCM_ACCESS_CTRL34_REG(base) ((base)->ACCESS_CTRL34) -#define CCM_ACCESS_CTRL34_ROOT_SET_REG(base) ((base)->ACCESS_CTRL34_ROOT_SET) -#define CCM_ACCESS_CTRL34_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL34_ROOT_CLR) -#define CCM_ACCESS_CTRL34_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL34_ROOT_TOG) -#define CCM_TARGET_ROOT35_REG(base) ((base)->TARGET_ROOT35) -#define CCM_TARGET_ROOT35_SET_REG(base) ((base)->TARGET_ROOT35_SET) -#define CCM_TARGET_ROOT35_CLR_REG(base) ((base)->TARGET_ROOT35_CLR) -#define CCM_TARGET_ROOT35_TOG_REG(base) ((base)->TARGET_ROOT35_TOG) -#define CCM_POST35_REG(base) ((base)->POST35) -#define CCM_POST_ROOT35_SET_REG(base) ((base)->POST_ROOT35_SET) -#define CCM_POST_ROOT35_CLR_REG(base) ((base)->POST_ROOT35_CLR) -#define CCM_POST_ROOT35_TOG_REG(base) ((base)->POST_ROOT35_TOG) -#define CCM_PRE35_REG(base) ((base)->PRE35) -#define CCM_PRE_ROOT35_SET_REG(base) ((base)->PRE_ROOT35_SET) -#define CCM_PRE_ROOT35_CLR_REG(base) ((base)->PRE_ROOT35_CLR) -#define CCM_PRE_ROOT35_TOG_REG(base) ((base)->PRE_ROOT35_TOG) -#define CCM_ACCESS_CTRL35_REG(base) ((base)->ACCESS_CTRL35) -#define CCM_ACCESS_CTRL35_ROOT_SET_REG(base) ((base)->ACCESS_CTRL35_ROOT_SET) -#define CCM_ACCESS_CTRL35_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL35_ROOT_CLR) -#define CCM_ACCESS_CTRL35_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL35_ROOT_TOG) -#define CCM_TARGET_ROOT36_REG(base) ((base)->TARGET_ROOT36) -#define CCM_TARGET_ROOT36_SET_REG(base) ((base)->TARGET_ROOT36_SET) -#define CCM_TARGET_ROOT36_CLR_REG(base) ((base)->TARGET_ROOT36_CLR) -#define CCM_TARGET_ROOT36_TOG_REG(base) ((base)->TARGET_ROOT36_TOG) -#define CCM_POST36_REG(base) ((base)->POST36) -#define CCM_POST_ROOT36_SET_REG(base) ((base)->POST_ROOT36_SET) -#define CCM_POST_ROOT36_CLR_REG(base) ((base)->POST_ROOT36_CLR) -#define CCM_POST_ROOT36_TOG_REG(base) ((base)->POST_ROOT36_TOG) -#define CCM_PRE36_REG(base) ((base)->PRE36) -#define CCM_PRE_ROOT36_SET_REG(base) ((base)->PRE_ROOT36_SET) -#define CCM_PRE_ROOT36_CLR_REG(base) ((base)->PRE_ROOT36_CLR) -#define CCM_PRE_ROOT36_TOG_REG(base) ((base)->PRE_ROOT36_TOG) -#define CCM_ACCESS_CTRL36_REG(base) ((base)->ACCESS_CTRL36) -#define CCM_ACCESS_CTRL36_ROOT_SET_REG(base) ((base)->ACCESS_CTRL36_ROOT_SET) -#define CCM_ACCESS_CTRL36_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL36_ROOT_CLR) -#define CCM_ACCESS_CTRL36_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL36_ROOT_TOG) -#define CCM_TARGET_ROOT37_REG(base) ((base)->TARGET_ROOT37) -#define CCM_TARGET_ROOT37_SET_REG(base) ((base)->TARGET_ROOT37_SET) -#define CCM_TARGET_ROOT37_CLR_REG(base) ((base)->TARGET_ROOT37_CLR) -#define CCM_TARGET_ROOT37_TOG_REG(base) ((base)->TARGET_ROOT37_TOG) -#define CCM_POST37_REG(base) ((base)->POST37) -#define CCM_POST_ROOT37_SET_REG(base) ((base)->POST_ROOT37_SET) -#define CCM_POST_ROOT37_CLR_REG(base) ((base)->POST_ROOT37_CLR) -#define CCM_POST_ROOT37_TOG_REG(base) ((base)->POST_ROOT37_TOG) -#define CCM_PRE37_REG(base) ((base)->PRE37) -#define CCM_PRE_ROOT37_SET_REG(base) ((base)->PRE_ROOT37_SET) -#define CCM_PRE_ROOT37_CLR_REG(base) ((base)->PRE_ROOT37_CLR) -#define CCM_PRE_ROOT37_TOG_REG(base) ((base)->PRE_ROOT37_TOG) -#define CCM_ACCESS_CTRL37_REG(base) ((base)->ACCESS_CTRL37) -#define CCM_ACCESS_CTRL37_ROOT_SET_REG(base) ((base)->ACCESS_CTRL37_ROOT_SET) -#define CCM_ACCESS_CTRL37_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL37_ROOT_CLR) -#define CCM_ACCESS_CTRL37_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL37_ROOT_TOG) -#define CCM_TARGET_ROOT38_REG(base) ((base)->TARGET_ROOT38) -#define CCM_TARGET_ROOT38_SET_REG(base) ((base)->TARGET_ROOT38_SET) -#define CCM_TARGET_ROOT38_CLR_REG(base) ((base)->TARGET_ROOT38_CLR) -#define CCM_TARGET_ROOT38_TOG_REG(base) ((base)->TARGET_ROOT38_TOG) -#define CCM_POST38_REG(base) ((base)->POST38) -#define CCM_POST_ROOT38_SET_REG(base) ((base)->POST_ROOT38_SET) -#define CCM_POST_ROOT38_CLR_REG(base) ((base)->POST_ROOT38_CLR) -#define CCM_POST_ROOT38_TOG_REG(base) ((base)->POST_ROOT38_TOG) -#define CCM_PRE38_REG(base) ((base)->PRE38) -#define CCM_PRE_ROOT38_SET_REG(base) ((base)->PRE_ROOT38_SET) -#define CCM_PRE_ROOT38_CLR_REG(base) ((base)->PRE_ROOT38_CLR) -#define CCM_PRE_ROOT38_TOG_REG(base) ((base)->PRE_ROOT38_TOG) -#define CCM_ACCESS_CTRL38_REG(base) ((base)->ACCESS_CTRL38) -#define CCM_ACCESS_CTRL38_ROOT_SET_REG(base) ((base)->ACCESS_CTRL38_ROOT_SET) -#define CCM_ACCESS_CTRL38_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL38_ROOT_CLR) -#define CCM_ACCESS_CTRL38_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL38_ROOT_TOG) -#define CCM_TARGET_ROOT39_REG(base) ((base)->TARGET_ROOT39) -#define CCM_TARGET_ROOT39_SET_REG(base) ((base)->TARGET_ROOT39_SET) -#define CCM_TARGET_ROOT39_CLR_REG(base) ((base)->TARGET_ROOT39_CLR) -#define CCM_TARGET_ROOT39_TOG_REG(base) ((base)->TARGET_ROOT39_TOG) -#define CCM_POST39_REG(base) ((base)->POST39) -#define CCM_POST_ROOT39_SET_REG(base) ((base)->POST_ROOT39_SET) -#define CCM_POST_ROOT39_CLR_REG(base) ((base)->POST_ROOT39_CLR) -#define CCM_POST_ROOT39_TOG_REG(base) ((base)->POST_ROOT39_TOG) -#define CCM_PRE39_REG(base) ((base)->PRE39) -#define CCM_PRE_ROOT39_SET_REG(base) ((base)->PRE_ROOT39_SET) -#define CCM_PRE_ROOT39_CLR_REG(base) ((base)->PRE_ROOT39_CLR) -#define CCM_PRE_ROOT39_TOG_REG(base) ((base)->PRE_ROOT39_TOG) -#define CCM_ACCESS_CTRL39_REG(base) ((base)->ACCESS_CTRL39) -#define CCM_ACCESS_CTRL39_ROOT_SET_REG(base) ((base)->ACCESS_CTRL39_ROOT_SET) -#define CCM_ACCESS_CTRL39_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL39_ROOT_CLR) -#define CCM_ACCESS_CTRL39_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL39_ROOT_TOG) -#define CCM_TARGET_ROOT40_REG(base) ((base)->TARGET_ROOT40) -#define CCM_TARGET_ROOT40_SET_REG(base) ((base)->TARGET_ROOT40_SET) -#define CCM_TARGET_ROOT40_CLR_REG(base) ((base)->TARGET_ROOT40_CLR) -#define CCM_TARGET_ROOT40_TOG_REG(base) ((base)->TARGET_ROOT40_TOG) -#define CCM_POST40_REG(base) ((base)->POST40) -#define CCM_POST_ROOT40_SET_REG(base) ((base)->POST_ROOT40_SET) -#define CCM_POST_ROOT40_CLR_REG(base) ((base)->POST_ROOT40_CLR) -#define CCM_POST_ROOT40_TOG_REG(base) ((base)->POST_ROOT40_TOG) -#define CCM_PRE40_REG(base) ((base)->PRE40) -#define CCM_PRE_ROOT40_SET_REG(base) ((base)->PRE_ROOT40_SET) -#define CCM_PRE_ROOT40_CLR_REG(base) ((base)->PRE_ROOT40_CLR) -#define CCM_PRE_ROOT40_TOG_REG(base) ((base)->PRE_ROOT40_TOG) -#define CCM_ACCESS_CTRL40_REG(base) ((base)->ACCESS_CTRL40) -#define CCM_ACCESS_CTRL40_ROOT_SET_REG(base) ((base)->ACCESS_CTRL40_ROOT_SET) -#define CCM_ACCESS_CTRL40_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL40_ROOT_CLR) -#define CCM_ACCESS_CTRL40_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL40_ROOT_TOG) -#define CCM_TARGET_ROOT41_REG(base) ((base)->TARGET_ROOT41) -#define CCM_TARGET_ROOT41_SET_REG(base) ((base)->TARGET_ROOT41_SET) -#define CCM_TARGET_ROOT41_CLR_REG(base) ((base)->TARGET_ROOT41_CLR) -#define CCM_TARGET_ROOT41_TOG_REG(base) ((base)->TARGET_ROOT41_TOG) -#define CCM_POST41_REG(base) ((base)->POST41) -#define CCM_POST_ROOT41_SET_REG(base) ((base)->POST_ROOT41_SET) -#define CCM_POST_ROOT41_CLR_REG(base) ((base)->POST_ROOT41_CLR) -#define CCM_POST_ROOT41_TOG_REG(base) ((base)->POST_ROOT41_TOG) -#define CCM_PRE41_REG(base) ((base)->PRE41) -#define CCM_PRE_ROOT41_SET_REG(base) ((base)->PRE_ROOT41_SET) -#define CCM_PRE_ROOT41_CLR_REG(base) ((base)->PRE_ROOT41_CLR) -#define CCM_PRE_ROOT41_TOG_REG(base) ((base)->PRE_ROOT41_TOG) -#define CCM_ACCESS_CTRL41_REG(base) ((base)->ACCESS_CTRL41) -#define CCM_ACCESS_CTRL41_ROOT_SET_REG(base) ((base)->ACCESS_CTRL41_ROOT_SET) -#define CCM_ACCESS_CTRL41_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL41_ROOT_CLR) -#define CCM_ACCESS_CTRL41_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL41_ROOT_TOG) -#define CCM_TARGET_ROOT42_REG(base) ((base)->TARGET_ROOT42) -#define CCM_TARGET_ROOT42_SET_REG(base) ((base)->TARGET_ROOT42_SET) -#define CCM_TARGET_ROOT42_CLR_REG(base) ((base)->TARGET_ROOT42_CLR) -#define CCM_TARGET_ROOT42_TOG_REG(base) ((base)->TARGET_ROOT42_TOG) -#define CCM_POST42_REG(base) ((base)->POST42) -#define CCM_POST_ROOT42_SET_REG(base) ((base)->POST_ROOT42_SET) -#define CCM_POST_ROOT42_CLR_REG(base) ((base)->POST_ROOT42_CLR) -#define CCM_POST_ROOT42_TOG_REG(base) ((base)->POST_ROOT42_TOG) -#define CCM_PRE42_REG(base) ((base)->PRE42) -#define CCM_PRE_ROOT42_SET_REG(base) ((base)->PRE_ROOT42_SET) -#define CCM_PRE_ROOT42_CLR_REG(base) ((base)->PRE_ROOT42_CLR) -#define CCM_PRE_ROOT42_TOG_REG(base) ((base)->PRE_ROOT42_TOG) -#define CCM_ACCESS_CTRL42_REG(base) ((base)->ACCESS_CTRL42) -#define CCM_ACCESS_CTRL42_ROOT_SET_REG(base) ((base)->ACCESS_CTRL42_ROOT_SET) -#define CCM_ACCESS_CTRL42_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL42_ROOT_CLR) -#define CCM_ACCESS_CTRL42_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL42_ROOT_TOG) -#define CCM_TARGET_ROOT43_REG(base) ((base)->TARGET_ROOT43) -#define CCM_TARGET_ROOT43_SET_REG(base) ((base)->TARGET_ROOT43_SET) -#define CCM_TARGET_ROOT43_CLR_REG(base) ((base)->TARGET_ROOT43_CLR) -#define CCM_TARGET_ROOT43_TOG_REG(base) ((base)->TARGET_ROOT43_TOG) -#define CCM_POST43_REG(base) ((base)->POST43) -#define CCM_POST_ROOT43_SET_REG(base) ((base)->POST_ROOT43_SET) -#define CCM_POST_ROOT43_CLR_REG(base) ((base)->POST_ROOT43_CLR) -#define CCM_POST_ROOT43_TOG_REG(base) ((base)->POST_ROOT43_TOG) -#define CCM_PRE43_REG(base) ((base)->PRE43) -#define CCM_PRE_ROOT43_SET_REG(base) ((base)->PRE_ROOT43_SET) -#define CCM_PRE_ROOT43_CLR_REG(base) ((base)->PRE_ROOT43_CLR) -#define CCM_PRE_ROOT43_TOG_REG(base) ((base)->PRE_ROOT43_TOG) -#define CCM_ACCESS_CTRL43_REG(base) ((base)->ACCESS_CTRL43) -#define CCM_ACCESS_CTRL43_ROOT_SET_REG(base) ((base)->ACCESS_CTRL43_ROOT_SET) -#define CCM_ACCESS_CTRL43_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL43_ROOT_CLR) -#define CCM_ACCESS_CTRL43_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL43_ROOT_TOG) -#define CCM_TARGET_ROOT44_REG(base) ((base)->TARGET_ROOT44) -#define CCM_TARGET_ROOT44_SET_REG(base) ((base)->TARGET_ROOT44_SET) -#define CCM_TARGET_ROOT44_CLR_REG(base) ((base)->TARGET_ROOT44_CLR) -#define CCM_TARGET_ROOT44_TOG_REG(base) ((base)->TARGET_ROOT44_TOG) -#define CCM_POST44_REG(base) ((base)->POST44) -#define CCM_POST_ROOT44_SET_REG(base) ((base)->POST_ROOT44_SET) -#define CCM_POST_ROOT44_CLR_REG(base) ((base)->POST_ROOT44_CLR) -#define CCM_POST_ROOT44_TOG_REG(base) ((base)->POST_ROOT44_TOG) -#define CCM_PRE44_REG(base) ((base)->PRE44) -#define CCM_PRE_ROOT44_SET_REG(base) ((base)->PRE_ROOT44_SET) -#define CCM_PRE_ROOT44_CLR_REG(base) ((base)->PRE_ROOT44_CLR) -#define CCM_PRE_ROOT44_TOG_REG(base) ((base)->PRE_ROOT44_TOG) -#define CCM_ACCESS_CTRL44_REG(base) ((base)->ACCESS_CTRL44) -#define CCM_ACCESS_CTRL44_ROOT_SET_REG(base) ((base)->ACCESS_CTRL44_ROOT_SET) -#define CCM_ACCESS_CTRL44_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL44_ROOT_CLR) -#define CCM_ACCESS_CTRL44_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL44_ROOT_TOG) -#define CCM_TARGET_ROOT45_REG(base) ((base)->TARGET_ROOT45) -#define CCM_TARGET_ROOT45_SET_REG(base) ((base)->TARGET_ROOT45_SET) -#define CCM_TARGET_ROOT45_CLR_REG(base) ((base)->TARGET_ROOT45_CLR) -#define CCM_TARGET_ROOT45_TOG_REG(base) ((base)->TARGET_ROOT45_TOG) -#define CCM_POST45_REG(base) ((base)->POST45) -#define CCM_POST_ROOT45_SET_REG(base) ((base)->POST_ROOT45_SET) -#define CCM_POST_ROOT45_CLR_REG(base) ((base)->POST_ROOT45_CLR) -#define CCM_POST_ROOT45_TOG_REG(base) ((base)->POST_ROOT45_TOG) -#define CCM_PRE45_REG(base) ((base)->PRE45) -#define CCM_PRE_ROOT45_SET_REG(base) ((base)->PRE_ROOT45_SET) -#define CCM_PRE_ROOT45_CLR_REG(base) ((base)->PRE_ROOT45_CLR) -#define CCM_PRE_ROOT45_TOG_REG(base) ((base)->PRE_ROOT45_TOG) -#define CCM_ACCESS_CTRL45_REG(base) ((base)->ACCESS_CTRL45) -#define CCM_ACCESS_CTRL45_ROOT_SET_REG(base) ((base)->ACCESS_CTRL45_ROOT_SET) -#define CCM_ACCESS_CTRL45_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL45_ROOT_CLR) -#define CCM_ACCESS_CTRL45_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL45_ROOT_TOG) -#define CCM_TARGET_ROOT46_REG(base) ((base)->TARGET_ROOT46) -#define CCM_TARGET_ROOT46_SET_REG(base) ((base)->TARGET_ROOT46_SET) -#define CCM_TARGET_ROOT46_CLR_REG(base) ((base)->TARGET_ROOT46_CLR) -#define CCM_TARGET_ROOT46_TOG_REG(base) ((base)->TARGET_ROOT46_TOG) -#define CCM_POST46_REG(base) ((base)->POST46) -#define CCM_POST_ROOT46_SET_REG(base) ((base)->POST_ROOT46_SET) -#define CCM_POST_ROOT46_CLR_REG(base) ((base)->POST_ROOT46_CLR) -#define CCM_POST_ROOT46_TOG_REG(base) ((base)->POST_ROOT46_TOG) -#define CCM_PRE46_REG(base) ((base)->PRE46) -#define CCM_PRE_ROOT46_SET_REG(base) ((base)->PRE_ROOT46_SET) -#define CCM_PRE_ROOT46_CLR_REG(base) ((base)->PRE_ROOT46_CLR) -#define CCM_PRE_ROOT46_TOG_REG(base) ((base)->PRE_ROOT46_TOG) -#define CCM_ACCESS_CTRL46_REG(base) ((base)->ACCESS_CTRL46) -#define CCM_ACCESS_CTRL46_ROOT_SET_REG(base) ((base)->ACCESS_CTRL46_ROOT_SET) -#define CCM_ACCESS_CTRL46_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL46_ROOT_CLR) -#define CCM_ACCESS_CTRL46_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL46_ROOT_TOG) -#define CCM_TARGET_ROOT47_REG(base) ((base)->TARGET_ROOT47) -#define CCM_TARGET_ROOT47_SET_REG(base) ((base)->TARGET_ROOT47_SET) -#define CCM_TARGET_ROOT47_CLR_REG(base) ((base)->TARGET_ROOT47_CLR) -#define CCM_TARGET_ROOT47_TOG_REG(base) ((base)->TARGET_ROOT47_TOG) -#define CCM_POST47_REG(base) ((base)->POST47) -#define CCM_POST_ROOT47_SET_REG(base) ((base)->POST_ROOT47_SET) -#define CCM_POST_ROOT47_CLR_REG(base) ((base)->POST_ROOT47_CLR) -#define CCM_POST_ROOT47_TOG_REG(base) ((base)->POST_ROOT47_TOG) -#define CCM_PRE47_REG(base) ((base)->PRE47) -#define CCM_PRE_ROOT47_SET_REG(base) ((base)->PRE_ROOT47_SET) -#define CCM_PRE_ROOT47_CLR_REG(base) ((base)->PRE_ROOT47_CLR) -#define CCM_PRE_ROOT47_TOG_REG(base) ((base)->PRE_ROOT47_TOG) -#define CCM_ACCESS_CTRL47_REG(base) ((base)->ACCESS_CTRL47) -#define CCM_ACCESS_CTRL47_ROOT_SET_REG(base) ((base)->ACCESS_CTRL47_ROOT_SET) -#define CCM_ACCESS_CTRL47_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL47_ROOT_CLR) -#define CCM_ACCESS_CTRL47_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL47_ROOT_TOG) -#define CCM_TARGET_ROOT48_REG(base) ((base)->TARGET_ROOT48) -#define CCM_TARGET_ROOT48_SET_REG(base) ((base)->TARGET_ROOT48_SET) -#define CCM_TARGET_ROOT48_CLR_REG(base) ((base)->TARGET_ROOT48_CLR) -#define CCM_TARGET_ROOT48_TOG_REG(base) ((base)->TARGET_ROOT48_TOG) -#define CCM_POST48_REG(base) ((base)->POST48) -#define CCM_POST_ROOT48_SET_REG(base) ((base)->POST_ROOT48_SET) -#define CCM_POST_ROOT48_CLR_REG(base) ((base)->POST_ROOT48_CLR) -#define CCM_POST_ROOT48_TOG_REG(base) ((base)->POST_ROOT48_TOG) -#define CCM_PRE48_REG(base) ((base)->PRE48) -#define CCM_PRE_ROOT48_SET_REG(base) ((base)->PRE_ROOT48_SET) -#define CCM_PRE_ROOT48_CLR_REG(base) ((base)->PRE_ROOT48_CLR) -#define CCM_PRE_ROOT48_TOG_REG(base) ((base)->PRE_ROOT48_TOG) -#define CCM_ACCESS_CTRL48_REG(base) ((base)->ACCESS_CTRL48) -#define CCM_ACCESS_CTRL48_ROOT_SET_REG(base) ((base)->ACCESS_CTRL48_ROOT_SET) -#define CCM_ACCESS_CTRL48_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL48_ROOT_CLR) -#define CCM_ACCESS_CTRL48_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL48_ROOT_TOG) -#define CCM_TARGET_ROOT49_REG(base) ((base)->TARGET_ROOT49) -#define CCM_TARGET_ROOT49_SET_REG(base) ((base)->TARGET_ROOT49_SET) -#define CCM_TARGET_ROOT49_CLR_REG(base) ((base)->TARGET_ROOT49_CLR) -#define CCM_TARGET_ROOT49_TOG_REG(base) ((base)->TARGET_ROOT49_TOG) -#define CCM_POST49_REG(base) ((base)->POST49) -#define CCM_POST_ROOT49_SET_REG(base) ((base)->POST_ROOT49_SET) -#define CCM_POST_ROOT49_CLR_REG(base) ((base)->POST_ROOT49_CLR) -#define CCM_POST_ROOT49_TOG_REG(base) ((base)->POST_ROOT49_TOG) -#define CCM_PRE49_REG(base) ((base)->PRE49) -#define CCM_PRE_ROOT49_SET_REG(base) ((base)->PRE_ROOT49_SET) -#define CCM_PRE_ROOT49_CLR_REG(base) ((base)->PRE_ROOT49_CLR) -#define CCM_PRE_ROOT49_TOG_REG(base) ((base)->PRE_ROOT49_TOG) -#define CCM_ACCESS_CTRL49_REG(base) ((base)->ACCESS_CTRL49) -#define CCM_ACCESS_CTRL49_ROOT_SET_REG(base) ((base)->ACCESS_CTRL49_ROOT_SET) -#define CCM_ACCESS_CTRL49_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL49_ROOT_CLR) -#define CCM_ACCESS_CTRL49_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL49_ROOT_TOG) -#define CCM_TARGET_ROOT50_REG(base) ((base)->TARGET_ROOT50) -#define CCM_TARGET_ROOT50_SET_REG(base) ((base)->TARGET_ROOT50_SET) -#define CCM_TARGET_ROOT50_CLR_REG(base) ((base)->TARGET_ROOT50_CLR) -#define CCM_TARGET_ROOT50_TOG_REG(base) ((base)->TARGET_ROOT50_TOG) -#define CCM_POST50_REG(base) ((base)->POST50) -#define CCM_POST_ROOT50_SET_REG(base) ((base)->POST_ROOT50_SET) -#define CCM_POST_ROOT50_CLR_REG(base) ((base)->POST_ROOT50_CLR) -#define CCM_POST_ROOT50_TOG_REG(base) ((base)->POST_ROOT50_TOG) -#define CCM_PRE50_REG(base) ((base)->PRE50) -#define CCM_PRE_ROOT50_SET_REG(base) ((base)->PRE_ROOT50_SET) -#define CCM_PRE_ROOT50_CLR_REG(base) ((base)->PRE_ROOT50_CLR) -#define CCM_PRE_ROOT50_TOG_REG(base) ((base)->PRE_ROOT50_TOG) -#define CCM_ACCESS_CTRL50_REG(base) ((base)->ACCESS_CTRL50) -#define CCM_ACCESS_CTRL50_ROOT_SET_REG(base) ((base)->ACCESS_CTRL50_ROOT_SET) -#define CCM_ACCESS_CTRL50_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL50_ROOT_CLR) -#define CCM_ACCESS_CTRL50_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL50_ROOT_TOG) -#define CCM_TARGET_ROOT51_REG(base) ((base)->TARGET_ROOT51) -#define CCM_TARGET_ROOT51_SET_REG(base) ((base)->TARGET_ROOT51_SET) -#define CCM_TARGET_ROOT51_CLR_REG(base) ((base)->TARGET_ROOT51_CLR) -#define CCM_TARGET_ROOT51_TOG_REG(base) ((base)->TARGET_ROOT51_TOG) -#define CCM_POST51_REG(base) ((base)->POST51) -#define CCM_POST_ROOT51_SET_REG(base) ((base)->POST_ROOT51_SET) -#define CCM_POST_ROOT51_CLR_REG(base) ((base)->POST_ROOT51_CLR) -#define CCM_POST_ROOT51_TOG_REG(base) ((base)->POST_ROOT51_TOG) -#define CCM_PRE51_REG(base) ((base)->PRE51) -#define CCM_PRE_ROOT51_SET_REG(base) ((base)->PRE_ROOT51_SET) -#define CCM_PRE_ROOT51_CLR_REG(base) ((base)->PRE_ROOT51_CLR) -#define CCM_PRE_ROOT51_TOG_REG(base) ((base)->PRE_ROOT51_TOG) -#define CCM_ACCESS_CTRL51_REG(base) ((base)->ACCESS_CTRL51) -#define CCM_ACCESS_CTRL51_ROOT_SET_REG(base) ((base)->ACCESS_CTRL51_ROOT_SET) -#define CCM_ACCESS_CTRL51_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL51_ROOT_CLR) -#define CCM_ACCESS_CTRL51_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL51_ROOT_TOG) -#define CCM_TARGET_ROOT52_REG(base) ((base)->TARGET_ROOT52) -#define CCM_TARGET_ROOT52_SET_REG(base) ((base)->TARGET_ROOT52_SET) -#define CCM_TARGET_ROOT52_CLR_REG(base) ((base)->TARGET_ROOT52_CLR) -#define CCM_TARGET_ROOT52_TOG_REG(base) ((base)->TARGET_ROOT52_TOG) -#define CCM_POST52_REG(base) ((base)->POST52) -#define CCM_POST_ROOT52_SET_REG(base) ((base)->POST_ROOT52_SET) -#define CCM_POST_ROOT52_CLR_REG(base) ((base)->POST_ROOT52_CLR) -#define CCM_POST_ROOT52_TOG_REG(base) ((base)->POST_ROOT52_TOG) -#define CCM_PRE52_REG(base) ((base)->PRE52) -#define CCM_PRE_ROOT52_SET_REG(base) ((base)->PRE_ROOT52_SET) -#define CCM_PRE_ROOT52_CLR_REG(base) ((base)->PRE_ROOT52_CLR) -#define CCM_PRE_ROOT52_TOG_REG(base) ((base)->PRE_ROOT52_TOG) -#define CCM_ACCESS_CTRL52_REG(base) ((base)->ACCESS_CTRL52) -#define CCM_ACCESS_CTRL52_ROOT_SET_REG(base) ((base)->ACCESS_CTRL52_ROOT_SET) -#define CCM_ACCESS_CTRL52_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL52_ROOT_CLR) -#define CCM_ACCESS_CTRL52_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL52_ROOT_TOG) -#define CCM_TARGET_ROOT53_REG(base) ((base)->TARGET_ROOT53) -#define CCM_TARGET_ROOT53_SET_REG(base) ((base)->TARGET_ROOT53_SET) -#define CCM_TARGET_ROOT53_CLR_REG(base) ((base)->TARGET_ROOT53_CLR) -#define CCM_TARGET_ROOT53_TOG_REG(base) ((base)->TARGET_ROOT53_TOG) -#define CCM_POST53_REG(base) ((base)->POST53) -#define CCM_POST_ROOT53_SET_REG(base) ((base)->POST_ROOT53_SET) -#define CCM_POST_ROOT53_CLR_REG(base) ((base)->POST_ROOT53_CLR) -#define CCM_POST_ROOT53_TOG_REG(base) ((base)->POST_ROOT53_TOG) -#define CCM_PRE53_REG(base) ((base)->PRE53) -#define CCM_PRE_ROOT53_SET_REG(base) ((base)->PRE_ROOT53_SET) -#define CCM_PRE_ROOT53_CLR_REG(base) ((base)->PRE_ROOT53_CLR) -#define CCM_PRE_ROOT53_TOG_REG(base) ((base)->PRE_ROOT53_TOG) -#define CCM_ACCESS_CTRL53_REG(base) ((base)->ACCESS_CTRL53) -#define CCM_ACCESS_CTRL53_ROOT_SET_REG(base) ((base)->ACCESS_CTRL53_ROOT_SET) -#define CCM_ACCESS_CTRL53_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL53_ROOT_CLR) -#define CCM_ACCESS_CTRL53_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL53_ROOT_TOG) -#define CCM_TARGET_ROOT54_REG(base) ((base)->TARGET_ROOT54) -#define CCM_TARGET_ROOT54_SET_REG(base) ((base)->TARGET_ROOT54_SET) -#define CCM_TARGET_ROOT54_CLR_REG(base) ((base)->TARGET_ROOT54_CLR) -#define CCM_TARGET_ROOT54_TOG_REG(base) ((base)->TARGET_ROOT54_TOG) -#define CCM_POST54_REG(base) ((base)->POST54) -#define CCM_POST_ROOT54_SET_REG(base) ((base)->POST_ROOT54_SET) -#define CCM_POST_ROOT54_CLR_REG(base) ((base)->POST_ROOT54_CLR) -#define CCM_POST_ROOT54_TOG_REG(base) ((base)->POST_ROOT54_TOG) -#define CCM_PRE54_REG(base) ((base)->PRE54) -#define CCM_PRE_ROOT54_SET_REG(base) ((base)->PRE_ROOT54_SET) -#define CCM_PRE_ROOT54_CLR_REG(base) ((base)->PRE_ROOT54_CLR) -#define CCM_PRE_ROOT54_TOG_REG(base) ((base)->PRE_ROOT54_TOG) -#define CCM_ACCESS_CTRL54_REG(base) ((base)->ACCESS_CTRL54) -#define CCM_ACCESS_CTRL54_ROOT_SET_REG(base) ((base)->ACCESS_CTRL54_ROOT_SET) -#define CCM_ACCESS_CTRL54_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL54_ROOT_CLR) -#define CCM_ACCESS_CTRL54_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL54_ROOT_TOG) -#define CCM_TARGET_ROOT55_REG(base) ((base)->TARGET_ROOT55) -#define CCM_TARGET_ROOT55_SET_REG(base) ((base)->TARGET_ROOT55_SET) -#define CCM_TARGET_ROOT55_CLR_REG(base) ((base)->TARGET_ROOT55_CLR) -#define CCM_TARGET_ROOT55_TOG_REG(base) ((base)->TARGET_ROOT55_TOG) -#define CCM_POST55_REG(base) ((base)->POST55) -#define CCM_POST_ROOT55_SET_REG(base) ((base)->POST_ROOT55_SET) -#define CCM_POST_ROOT55_CLR_REG(base) ((base)->POST_ROOT55_CLR) -#define CCM_POST_ROOT55_TOG_REG(base) ((base)->POST_ROOT55_TOG) -#define CCM_PRE55_REG(base) ((base)->PRE55) -#define CCM_PRE_ROOT55_SET_REG(base) ((base)->PRE_ROOT55_SET) -#define CCM_PRE_ROOT55_CLR_REG(base) ((base)->PRE_ROOT55_CLR) -#define CCM_PRE_ROOT55_TOG_REG(base) ((base)->PRE_ROOT55_TOG) -#define CCM_ACCESS_CTRL55_REG(base) ((base)->ACCESS_CTRL55) -#define CCM_ACCESS_CTRL55_ROOT_SET_REG(base) ((base)->ACCESS_CTRL55_ROOT_SET) -#define CCM_ACCESS_CTRL55_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL55_ROOT_CLR) -#define CCM_ACCESS_CTRL55_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL55_ROOT_TOG) -#define CCM_TARGET_ROOT56_REG(base) ((base)->TARGET_ROOT56) -#define CCM_TARGET_ROOT56_SET_REG(base) ((base)->TARGET_ROOT56_SET) -#define CCM_TARGET_ROOT56_CLR_REG(base) ((base)->TARGET_ROOT56_CLR) -#define CCM_TARGET_ROOT56_TOG_REG(base) ((base)->TARGET_ROOT56_TOG) -#define CCM_POST56_REG(base) ((base)->POST56) -#define CCM_POST_ROOT56_SET_REG(base) ((base)->POST_ROOT56_SET) -#define CCM_POST_ROOT56_CLR_REG(base) ((base)->POST_ROOT56_CLR) -#define CCM_POST_ROOT56_TOG_REG(base) ((base)->POST_ROOT56_TOG) -#define CCM_PRE56_REG(base) ((base)->PRE56) -#define CCM_PRE_ROOT56_SET_REG(base) ((base)->PRE_ROOT56_SET) -#define CCM_PRE_ROOT56_CLR_REG(base) ((base)->PRE_ROOT56_CLR) -#define CCM_PRE_ROOT56_TOG_REG(base) ((base)->PRE_ROOT56_TOG) -#define CCM_ACCESS_CTRL56_REG(base) ((base)->ACCESS_CTRL56) -#define CCM_ACCESS_CTRL56_ROOT_SET_REG(base) ((base)->ACCESS_CTRL56_ROOT_SET) -#define CCM_ACCESS_CTRL56_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL56_ROOT_CLR) -#define CCM_ACCESS_CTRL56_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL56_ROOT_TOG) -#define CCM_TARGET_ROOT57_REG(base) ((base)->TARGET_ROOT57) -#define CCM_TARGET_ROOT57_SET_REG(base) ((base)->TARGET_ROOT57_SET) -#define CCM_TARGET_ROOT57_CLR_REG(base) ((base)->TARGET_ROOT57_CLR) -#define CCM_TARGET_ROOT57_TOG_REG(base) ((base)->TARGET_ROOT57_TOG) -#define CCM_POST57_REG(base) ((base)->POST57) -#define CCM_POST_ROOT57_SET_REG(base) ((base)->POST_ROOT57_SET) -#define CCM_POST_ROOT57_CLR_REG(base) ((base)->POST_ROOT57_CLR) -#define CCM_POST_ROOT57_TOG_REG(base) ((base)->POST_ROOT57_TOG) -#define CCM_PRE57_REG(base) ((base)->PRE57) -#define CCM_PRE_ROOT57_SET_REG(base) ((base)->PRE_ROOT57_SET) -#define CCM_PRE_ROOT57_CLR_REG(base) ((base)->PRE_ROOT57_CLR) -#define CCM_PRE_ROOT57_TOG_REG(base) ((base)->PRE_ROOT57_TOG) -#define CCM_ACCESS_CTRL57_REG(base) ((base)->ACCESS_CTRL57) -#define CCM_ACCESS_CTRL57_ROOT_SET_REG(base) ((base)->ACCESS_CTRL57_ROOT_SET) -#define CCM_ACCESS_CTRL57_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL57_ROOT_CLR) -#define CCM_ACCESS_CTRL57_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL57_ROOT_TOG) -#define CCM_TARGET_ROOT58_REG(base) ((base)->TARGET_ROOT58) -#define CCM_TARGET_ROOT58_SET_REG(base) ((base)->TARGET_ROOT58_SET) -#define CCM_TARGET_ROOT58_CLR_REG(base) ((base)->TARGET_ROOT58_CLR) -#define CCM_TARGET_ROOT58_TOG_REG(base) ((base)->TARGET_ROOT58_TOG) -#define CCM_POST58_REG(base) ((base)->POST58) -#define CCM_POST_ROOT58_SET_REG(base) ((base)->POST_ROOT58_SET) -#define CCM_POST_ROOT58_CLR_REG(base) ((base)->POST_ROOT58_CLR) -#define CCM_POST_ROOT58_TOG_REG(base) ((base)->POST_ROOT58_TOG) -#define CCM_PRE58_REG(base) ((base)->PRE58) -#define CCM_PRE_ROOT58_SET_REG(base) ((base)->PRE_ROOT58_SET) -#define CCM_PRE_ROOT58_CLR_REG(base) ((base)->PRE_ROOT58_CLR) -#define CCM_PRE_ROOT58_TOG_REG(base) ((base)->PRE_ROOT58_TOG) -#define CCM_ACCESS_CTRL58_REG(base) ((base)->ACCESS_CTRL58) -#define CCM_ACCESS_CTRL58_ROOT_SET_REG(base) ((base)->ACCESS_CTRL58_ROOT_SET) -#define CCM_ACCESS_CTRL58_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL58_ROOT_CLR) -#define CCM_ACCESS_CTRL58_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL58_ROOT_TOG) -#define CCM_TARGET_ROOT59_REG(base) ((base)->TARGET_ROOT59) -#define CCM_TARGET_ROOT59_SET_REG(base) ((base)->TARGET_ROOT59_SET) -#define CCM_TARGET_ROOT59_CLR_REG(base) ((base)->TARGET_ROOT59_CLR) -#define CCM_TARGET_ROOT59_TOG_REG(base) ((base)->TARGET_ROOT59_TOG) -#define CCM_POST59_REG(base) ((base)->POST59) -#define CCM_POST_ROOT59_SET_REG(base) ((base)->POST_ROOT59_SET) -#define CCM_POST_ROOT59_CLR_REG(base) ((base)->POST_ROOT59_CLR) -#define CCM_POST_ROOT59_TOG_REG(base) ((base)->POST_ROOT59_TOG) -#define CCM_PRE59_REG(base) ((base)->PRE59) -#define CCM_PRE_ROOT59_SET_REG(base) ((base)->PRE_ROOT59_SET) -#define CCM_PRE_ROOT59_CLR_REG(base) ((base)->PRE_ROOT59_CLR) -#define CCM_PRE_ROOT59_TOG_REG(base) ((base)->PRE_ROOT59_TOG) -#define CCM_ACCESS_CTRL59_REG(base) ((base)->ACCESS_CTRL59) -#define CCM_ACCESS_CTRL59_ROOT_SET_REG(base) ((base)->ACCESS_CTRL59_ROOT_SET) -#define CCM_ACCESS_CTRL59_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL59_ROOT_CLR) -#define CCM_ACCESS_CTRL59_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL59_ROOT_TOG) -#define CCM_TARGET_ROOT60_REG(base) ((base)->TARGET_ROOT60) -#define CCM_TARGET_ROOT60_SET_REG(base) ((base)->TARGET_ROOT60_SET) -#define CCM_TARGET_ROOT60_CLR_REG(base) ((base)->TARGET_ROOT60_CLR) -#define CCM_TARGET_ROOT60_TOG_REG(base) ((base)->TARGET_ROOT60_TOG) -#define CCM_POST60_REG(base) ((base)->POST60) -#define CCM_POST_ROOT60_SET_REG(base) ((base)->POST_ROOT60_SET) -#define CCM_POST_ROOT60_CLR_REG(base) ((base)->POST_ROOT60_CLR) -#define CCM_POST_ROOT60_TOG_REG(base) ((base)->POST_ROOT60_TOG) -#define CCM_PRE60_REG(base) ((base)->PRE60) -#define CCM_PRE_ROOT60_SET_REG(base) ((base)->PRE_ROOT60_SET) -#define CCM_PRE_ROOT60_CLR_REG(base) ((base)->PRE_ROOT60_CLR) -#define CCM_PRE_ROOT60_TOG_REG(base) ((base)->PRE_ROOT60_TOG) -#define CCM_ACCESS_CTRL60_REG(base) ((base)->ACCESS_CTRL60) -#define CCM_ACCESS_CTRL60_ROOT_SET_REG(base) ((base)->ACCESS_CTRL60_ROOT_SET) -#define CCM_ACCESS_CTRL60_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL60_ROOT_CLR) -#define CCM_ACCESS_CTRL60_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL60_ROOT_TOG) -#define CCM_TARGET_ROOT61_REG(base) ((base)->TARGET_ROOT61) -#define CCM_TARGET_ROOT61_SET_REG(base) ((base)->TARGET_ROOT61_SET) -#define CCM_TARGET_ROOT61_CLR_REG(base) ((base)->TARGET_ROOT61_CLR) -#define CCM_TARGET_ROOT61_TOG_REG(base) ((base)->TARGET_ROOT61_TOG) -#define CCM_POST61_REG(base) ((base)->POST61) -#define CCM_POST_ROOT61_SET_REG(base) ((base)->POST_ROOT61_SET) -#define CCM_POST_ROOT61_CLR_REG(base) ((base)->POST_ROOT61_CLR) -#define CCM_POST_ROOT61_TOG_REG(base) ((base)->POST_ROOT61_TOG) -#define CCM_PRE61_REG(base) ((base)->PRE61) -#define CCM_PRE_ROOT61_SET_REG(base) ((base)->PRE_ROOT61_SET) -#define CCM_PRE_ROOT61_CLR_REG(base) ((base)->PRE_ROOT61_CLR) -#define CCM_PRE_ROOT61_TOG_REG(base) ((base)->PRE_ROOT61_TOG) -#define CCM_ACCESS_CTRL61_REG(base) ((base)->ACCESS_CTRL61) -#define CCM_ACCESS_CTRL61_ROOT_SET_REG(base) ((base)->ACCESS_CTRL61_ROOT_SET) -#define CCM_ACCESS_CTRL61_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL61_ROOT_CLR) -#define CCM_ACCESS_CTRL61_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL61_ROOT_TOG) -#define CCM_TARGET_ROOT62_REG(base) ((base)->TARGET_ROOT62) -#define CCM_TARGET_ROOT62_SET_REG(base) ((base)->TARGET_ROOT62_SET) -#define CCM_TARGET_ROOT62_CLR_REG(base) ((base)->TARGET_ROOT62_CLR) -#define CCM_TARGET_ROOT62_TOG_REG(base) ((base)->TARGET_ROOT62_TOG) -#define CCM_POST62_REG(base) ((base)->POST62) -#define CCM_POST_ROOT62_SET_REG(base) ((base)->POST_ROOT62_SET) -#define CCM_POST_ROOT62_CLR_REG(base) ((base)->POST_ROOT62_CLR) -#define CCM_POST_ROOT62_TOG_REG(base) ((base)->POST_ROOT62_TOG) -#define CCM_PRE62_REG(base) ((base)->PRE62) -#define CCM_PRE_ROOT62_SET_REG(base) ((base)->PRE_ROOT62_SET) -#define CCM_PRE_ROOT62_CLR_REG(base) ((base)->PRE_ROOT62_CLR) -#define CCM_PRE_ROOT62_TOG_REG(base) ((base)->PRE_ROOT62_TOG) -#define CCM_ACCESS_CTRL62_REG(base) ((base)->ACCESS_CTRL62) -#define CCM_ACCESS_CTRL62_ROOT_SET_REG(base) ((base)->ACCESS_CTRL62_ROOT_SET) -#define CCM_ACCESS_CTRL62_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL62_ROOT_CLR) -#define CCM_ACCESS_CTRL62_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL62_ROOT_TOG) -#define CCM_TARGET_ROOT63_REG(base) ((base)->TARGET_ROOT63) -#define CCM_TARGET_ROOT63_SET_REG(base) ((base)->TARGET_ROOT63_SET) -#define CCM_TARGET_ROOT63_CLR_REG(base) ((base)->TARGET_ROOT63_CLR) -#define CCM_TARGET_ROOT63_TOG_REG(base) ((base)->TARGET_ROOT63_TOG) -#define CCM_POST63_REG(base) ((base)->POST63) -#define CCM_POST_ROOT63_SET_REG(base) ((base)->POST_ROOT63_SET) -#define CCM_POST_ROOT63_CLR_REG(base) ((base)->POST_ROOT63_CLR) -#define CCM_POST_ROOT63_TOG_REG(base) ((base)->POST_ROOT63_TOG) -#define CCM_PRE63_REG(base) ((base)->PRE63) -#define CCM_PRE_ROOT63_SET_REG(base) ((base)->PRE_ROOT63_SET) -#define CCM_PRE_ROOT63_CLR_REG(base) ((base)->PRE_ROOT63_CLR) -#define CCM_PRE_ROOT63_TOG_REG(base) ((base)->PRE_ROOT63_TOG) -#define CCM_ACCESS_CTRL63_REG(base) ((base)->ACCESS_CTRL63) -#define CCM_ACCESS_CTRL63_ROOT_SET_REG(base) ((base)->ACCESS_CTRL63_ROOT_SET) -#define CCM_ACCESS_CTRL63_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL63_ROOT_CLR) -#define CCM_ACCESS_CTRL63_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL63_ROOT_TOG) -#define CCM_TARGET_ROOT64_REG(base) ((base)->TARGET_ROOT64) -#define CCM_TARGET_ROOT64_SET_REG(base) ((base)->TARGET_ROOT64_SET) -#define CCM_TARGET_ROOT64_CLR_REG(base) ((base)->TARGET_ROOT64_CLR) -#define CCM_TARGET_ROOT64_TOG_REG(base) ((base)->TARGET_ROOT64_TOG) -#define CCM_POST64_REG(base) ((base)->POST64) -#define CCM_POST_ROOT64_SET_REG(base) ((base)->POST_ROOT64_SET) -#define CCM_POST_ROOT64_CLR_REG(base) ((base)->POST_ROOT64_CLR) -#define CCM_POST_ROOT64_TOG_REG(base) ((base)->POST_ROOT64_TOG) -#define CCM_PRE64_REG(base) ((base)->PRE64) -#define CCM_PRE_ROOT64_SET_REG(base) ((base)->PRE_ROOT64_SET) -#define CCM_PRE_ROOT64_CLR_REG(base) ((base)->PRE_ROOT64_CLR) -#define CCM_PRE_ROOT64_TOG_REG(base) ((base)->PRE_ROOT64_TOG) -#define CCM_ACCESS_CTRL64_REG(base) ((base)->ACCESS_CTRL64) -#define CCM_ACCESS_CTRL64_ROOT_SET_REG(base) ((base)->ACCESS_CTRL64_ROOT_SET) -#define CCM_ACCESS_CTRL64_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL64_ROOT_CLR) -#define CCM_ACCESS_CTRL64_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL64_ROOT_TOG) -#define CCM_TARGET_ROOT65_REG(base) ((base)->TARGET_ROOT65) -#define CCM_TARGET_ROOT65_SET_REG(base) ((base)->TARGET_ROOT65_SET) -#define CCM_TARGET_ROOT65_CLR_REG(base) ((base)->TARGET_ROOT65_CLR) -#define CCM_TARGET_ROOT65_TOG_REG(base) ((base)->TARGET_ROOT65_TOG) -#define CCM_POST65_REG(base) ((base)->POST65) -#define CCM_POST_ROOT65_SET_REG(base) ((base)->POST_ROOT65_SET) -#define CCM_POST_ROOT65_CLR_REG(base) ((base)->POST_ROOT65_CLR) -#define CCM_POST_ROOT65_TOG_REG(base) ((base)->POST_ROOT65_TOG) -#define CCM_PRE65_REG(base) ((base)->PRE65) -#define CCM_PRE_ROOT65_SET_REG(base) ((base)->PRE_ROOT65_SET) -#define CCM_PRE_ROOT65_CLR_REG(base) ((base)->PRE_ROOT65_CLR) -#define CCM_PRE_ROOT65_TOG_REG(base) ((base)->PRE_ROOT65_TOG) -#define CCM_ACCESS_CTRL65_REG(base) ((base)->ACCESS_CTRL65) -#define CCM_ACCESS_CTRL65_ROOT_SET_REG(base) ((base)->ACCESS_CTRL65_ROOT_SET) -#define CCM_ACCESS_CTRL65_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL65_ROOT_CLR) -#define CCM_ACCESS_CTRL65_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL65_ROOT_TOG) -#define CCM_TARGET_ROOT66_REG(base) ((base)->TARGET_ROOT66) -#define CCM_TARGET_ROOT66_SET_REG(base) ((base)->TARGET_ROOT66_SET) -#define CCM_TARGET_ROOT66_CLR_REG(base) ((base)->TARGET_ROOT66_CLR) -#define CCM_TARGET_ROOT66_TOG_REG(base) ((base)->TARGET_ROOT66_TOG) -#define CCM_POST66_REG(base) ((base)->POST66) -#define CCM_POST_ROOT66_SET_REG(base) ((base)->POST_ROOT66_SET) -#define CCM_POST_ROOT66_CLR_REG(base) ((base)->POST_ROOT66_CLR) -#define CCM_POST_ROOT66_TOG_REG(base) ((base)->POST_ROOT66_TOG) -#define CCM_PRE66_REG(base) ((base)->PRE66) -#define CCM_PRE_ROOT66_SET_REG(base) ((base)->PRE_ROOT66_SET) -#define CCM_PRE_ROOT66_CLR_REG(base) ((base)->PRE_ROOT66_CLR) -#define CCM_PRE_ROOT66_TOG_REG(base) ((base)->PRE_ROOT66_TOG) -#define CCM_ACCESS_CTRL66_REG(base) ((base)->ACCESS_CTRL66) -#define CCM_ACCESS_CTRL66_ROOT_SET_REG(base) ((base)->ACCESS_CTRL66_ROOT_SET) -#define CCM_ACCESS_CTRL66_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL66_ROOT_CLR) -#define CCM_ACCESS_CTRL66_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL66_ROOT_TOG) -#define CCM_TARGET_ROOT67_REG(base) ((base)->TARGET_ROOT67) -#define CCM_TARGET_ROOT67_SET_REG(base) ((base)->TARGET_ROOT67_SET) -#define CCM_TARGET_ROOT67_CLR_REG(base) ((base)->TARGET_ROOT67_CLR) -#define CCM_TARGET_ROOT67_TOG_REG(base) ((base)->TARGET_ROOT67_TOG) -#define CCM_POST67_REG(base) ((base)->POST67) -#define CCM_POST_ROOT67_SET_REG(base) ((base)->POST_ROOT67_SET) -#define CCM_POST_ROOT67_CLR_REG(base) ((base)->POST_ROOT67_CLR) -#define CCM_POST_ROOT67_TOG_REG(base) ((base)->POST_ROOT67_TOG) -#define CCM_PRE67_REG(base) ((base)->PRE67) -#define CCM_PRE_ROOT67_SET_REG(base) ((base)->PRE_ROOT67_SET) -#define CCM_PRE_ROOT67_CLR_REG(base) ((base)->PRE_ROOT67_CLR) -#define CCM_PRE_ROOT67_TOG_REG(base) ((base)->PRE_ROOT67_TOG) -#define CCM_ACCESS_CTRL67_REG(base) ((base)->ACCESS_CTRL67) -#define CCM_ACCESS_CTRL67_ROOT_SET_REG(base) ((base)->ACCESS_CTRL67_ROOT_SET) -#define CCM_ACCESS_CTRL67_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL67_ROOT_CLR) -#define CCM_ACCESS_CTRL67_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL67_ROOT_TOG) -#define CCM_TARGET_ROOT68_REG(base) ((base)->TARGET_ROOT68) -#define CCM_TARGET_ROOT68_SET_REG(base) ((base)->TARGET_ROOT68_SET) -#define CCM_TARGET_ROOT68_CLR_REG(base) ((base)->TARGET_ROOT68_CLR) -#define CCM_TARGET_ROOT68_TOG_REG(base) ((base)->TARGET_ROOT68_TOG) -#define CCM_POST68_REG(base) ((base)->POST68) -#define CCM_POST_ROOT68_SET_REG(base) ((base)->POST_ROOT68_SET) -#define CCM_POST_ROOT68_CLR_REG(base) ((base)->POST_ROOT68_CLR) -#define CCM_POST_ROOT68_TOG_REG(base) ((base)->POST_ROOT68_TOG) -#define CCM_PRE68_REG(base) ((base)->PRE68) -#define CCM_PRE_ROOT68_SET_REG(base) ((base)->PRE_ROOT68_SET) -#define CCM_PRE_ROOT68_CLR_REG(base) ((base)->PRE_ROOT68_CLR) -#define CCM_PRE_ROOT68_TOG_REG(base) ((base)->PRE_ROOT68_TOG) -#define CCM_ACCESS_CTRL68_REG(base) ((base)->ACCESS_CTRL68) -#define CCM_ACCESS_CTRL68_ROOT_SET_REG(base) ((base)->ACCESS_CTRL68_ROOT_SET) -#define CCM_ACCESS_CTRL68_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL68_ROOT_CLR) -#define CCM_ACCESS_CTRL68_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL68_ROOT_TOG) -#define CCM_TARGET_ROOT69_REG(base) ((base)->TARGET_ROOT69) -#define CCM_TARGET_ROOT69_SET_REG(base) ((base)->TARGET_ROOT69_SET) -#define CCM_TARGET_ROOT69_CLR_REG(base) ((base)->TARGET_ROOT69_CLR) -#define CCM_TARGET_ROOT69_TOG_REG(base) ((base)->TARGET_ROOT69_TOG) -#define CCM_POST69_REG(base) ((base)->POST69) -#define CCM_POST_ROOT69_SET_REG(base) ((base)->POST_ROOT69_SET) -#define CCM_POST_ROOT69_CLR_REG(base) ((base)->POST_ROOT69_CLR) -#define CCM_POST_ROOT69_TOG_REG(base) ((base)->POST_ROOT69_TOG) -#define CCM_PRE69_REG(base) ((base)->PRE69) -#define CCM_PRE_ROOT69_SET_REG(base) ((base)->PRE_ROOT69_SET) -#define CCM_PRE_ROOT69_CLR_REG(base) ((base)->PRE_ROOT69_CLR) -#define CCM_PRE_ROOT69_TOG_REG(base) ((base)->PRE_ROOT69_TOG) -#define CCM_ACCESS_CTRL69_REG(base) ((base)->ACCESS_CTRL69) -#define CCM_ACCESS_CTRL69_ROOT_SET_REG(base) ((base)->ACCESS_CTRL69_ROOT_SET) -#define CCM_ACCESS_CTRL69_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL69_ROOT_CLR) -#define CCM_ACCESS_CTRL69_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL69_ROOT_TOG) -#define CCM_TARGET_ROOT70_REG(base) ((base)->TARGET_ROOT70) -#define CCM_TARGET_ROOT70_SET_REG(base) ((base)->TARGET_ROOT70_SET) -#define CCM_TARGET_ROOT70_CLR_REG(base) ((base)->TARGET_ROOT70_CLR) -#define CCM_TARGET_ROOT70_TOG_REG(base) ((base)->TARGET_ROOT70_TOG) -#define CCM_POST70_REG(base) ((base)->POST70) -#define CCM_POST_ROOT70_SET_REG(base) ((base)->POST_ROOT70_SET) -#define CCM_POST_ROOT70_CLR_REG(base) ((base)->POST_ROOT70_CLR) -#define CCM_POST_ROOT70_TOG_REG(base) ((base)->POST_ROOT70_TOG) -#define CCM_PRE70_REG(base) ((base)->PRE70) -#define CCM_PRE_ROOT70_SET_REG(base) ((base)->PRE_ROOT70_SET) -#define CCM_PRE_ROOT70_CLR_REG(base) ((base)->PRE_ROOT70_CLR) -#define CCM_PRE_ROOT70_TOG_REG(base) ((base)->PRE_ROOT70_TOG) -#define CCM_ACCESS_CTRL70_REG(base) ((base)->ACCESS_CTRL70) -#define CCM_ACCESS_CTRL70_ROOT_SET_REG(base) ((base)->ACCESS_CTRL70_ROOT_SET) -#define CCM_ACCESS_CTRL70_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL70_ROOT_CLR) -#define CCM_ACCESS_CTRL70_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL70_ROOT_TOG) -#define CCM_TARGET_ROOT71_REG(base) ((base)->TARGET_ROOT71) -#define CCM_TARGET_ROOT71_SET_REG(base) ((base)->TARGET_ROOT71_SET) -#define CCM_TARGET_ROOT71_CLR_REG(base) ((base)->TARGET_ROOT71_CLR) -#define CCM_TARGET_ROOT71_TOG_REG(base) ((base)->TARGET_ROOT71_TOG) -#define CCM_POST71_REG(base) ((base)->POST71) -#define CCM_POST_ROOT71_SET_REG(base) ((base)->POST_ROOT71_SET) -#define CCM_POST_ROOT71_CLR_REG(base) ((base)->POST_ROOT71_CLR) -#define CCM_POST_ROOT71_TOG_REG(base) ((base)->POST_ROOT71_TOG) -#define CCM_PRE71_REG(base) ((base)->PRE71) -#define CCM_PRE_ROOT71_SET_REG(base) ((base)->PRE_ROOT71_SET) -#define CCM_PRE_ROOT71_CLR_REG(base) ((base)->PRE_ROOT71_CLR) -#define CCM_PRE_ROOT71_TOG_REG(base) ((base)->PRE_ROOT71_TOG) -#define CCM_ACCESS_CTRL71_REG(base) ((base)->ACCESS_CTRL71) -#define CCM_ACCESS_CTRL71_ROOT_SET_REG(base) ((base)->ACCESS_CTRL71_ROOT_SET) -#define CCM_ACCESS_CTRL71_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL71_ROOT_CLR) -#define CCM_ACCESS_CTRL71_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL71_ROOT_TOG) -#define CCM_TARGET_ROOT72_REG(base) ((base)->TARGET_ROOT72) -#define CCM_TARGET_ROOT72_SET_REG(base) ((base)->TARGET_ROOT72_SET) -#define CCM_TARGET_ROOT72_CLR_REG(base) ((base)->TARGET_ROOT72_CLR) -#define CCM_TARGET_ROOT72_TOG_REG(base) ((base)->TARGET_ROOT72_TOG) -#define CCM_POST72_REG(base) ((base)->POST72) -#define CCM_POST_ROOT72_SET_REG(base) ((base)->POST_ROOT72_SET) -#define CCM_POST_ROOT72_CLR_REG(base) ((base)->POST_ROOT72_CLR) -#define CCM_POST_ROOT72_TOG_REG(base) ((base)->POST_ROOT72_TOG) -#define CCM_PRE72_REG(base) ((base)->PRE72) -#define CCM_PRE_ROOT72_SET_REG(base) ((base)->PRE_ROOT72_SET) -#define CCM_PRE_ROOT72_CLR_REG(base) ((base)->PRE_ROOT72_CLR) -#define CCM_PRE_ROOT72_TOG_REG(base) ((base)->PRE_ROOT72_TOG) -#define CCM_ACCESS_CTRL72_REG(base) ((base)->ACCESS_CTRL72) -#define CCM_ACCESS_CTRL72_ROOT_SET_REG(base) ((base)->ACCESS_CTRL72_ROOT_SET) -#define CCM_ACCESS_CTRL72_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL72_ROOT_CLR) -#define CCM_ACCESS_CTRL72_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL72_ROOT_TOG) -#define CCM_TARGET_ROOT73_REG(base) ((base)->TARGET_ROOT73) -#define CCM_TARGET_ROOT73_SET_REG(base) ((base)->TARGET_ROOT73_SET) -#define CCM_TARGET_ROOT73_CLR_REG(base) ((base)->TARGET_ROOT73_CLR) -#define CCM_TARGET_ROOT73_TOG_REG(base) ((base)->TARGET_ROOT73_TOG) -#define CCM_POST73_REG(base) ((base)->POST73) -#define CCM_POST_ROOT73_SET_REG(base) ((base)->POST_ROOT73_SET) -#define CCM_POST_ROOT73_CLR_REG(base) ((base)->POST_ROOT73_CLR) -#define CCM_POST_ROOT73_TOG_REG(base) ((base)->POST_ROOT73_TOG) -#define CCM_PRE73_REG(base) ((base)->PRE73) -#define CCM_PRE_ROOT73_SET_REG(base) ((base)->PRE_ROOT73_SET) -#define CCM_PRE_ROOT73_CLR_REG(base) ((base)->PRE_ROOT73_CLR) -#define CCM_PRE_ROOT73_TOG_REG(base) ((base)->PRE_ROOT73_TOG) -#define CCM_ACCESS_CTRL73_REG(base) ((base)->ACCESS_CTRL73) -#define CCM_ACCESS_CTRL73_ROOT_SET_REG(base) ((base)->ACCESS_CTRL73_ROOT_SET) -#define CCM_ACCESS_CTRL73_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL73_ROOT_CLR) -#define CCM_ACCESS_CTRL73_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL73_ROOT_TOG) -#define CCM_TARGET_ROOT74_REG(base) ((base)->TARGET_ROOT74) -#define CCM_TARGET_ROOT74_SET_REG(base) ((base)->TARGET_ROOT74_SET) -#define CCM_TARGET_ROOT74_CLR_REG(base) ((base)->TARGET_ROOT74_CLR) -#define CCM_TARGET_ROOT74_TOG_REG(base) ((base)->TARGET_ROOT74_TOG) -#define CCM_POST74_REG(base) ((base)->POST74) -#define CCM_POST_ROOT74_SET_REG(base) ((base)->POST_ROOT74_SET) -#define CCM_POST_ROOT74_CLR_REG(base) ((base)->POST_ROOT74_CLR) -#define CCM_POST_ROOT74_TOG_REG(base) ((base)->POST_ROOT74_TOG) -#define CCM_PRE74_REG(base) ((base)->PRE74) -#define CCM_PRE_ROOT74_SET_REG(base) ((base)->PRE_ROOT74_SET) -#define CCM_PRE_ROOT74_CLR_REG(base) ((base)->PRE_ROOT74_CLR) -#define CCM_PRE_ROOT74_TOG_REG(base) ((base)->PRE_ROOT74_TOG) -#define CCM_ACCESS_CTRL74_REG(base) ((base)->ACCESS_CTRL74) -#define CCM_ACCESS_CTRL74_ROOT_SET_REG(base) ((base)->ACCESS_CTRL74_ROOT_SET) -#define CCM_ACCESS_CTRL74_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL74_ROOT_CLR) -#define CCM_ACCESS_CTRL74_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL74_ROOT_TOG) -#define CCM_TARGET_ROOT75_REG(base) ((base)->TARGET_ROOT75) -#define CCM_TARGET_ROOT75_SET_REG(base) ((base)->TARGET_ROOT75_SET) -#define CCM_TARGET_ROOT75_CLR_REG(base) ((base)->TARGET_ROOT75_CLR) -#define CCM_TARGET_ROOT75_TOG_REG(base) ((base)->TARGET_ROOT75_TOG) -#define CCM_POST75_REG(base) ((base)->POST75) -#define CCM_POST_ROOT75_SET_REG(base) ((base)->POST_ROOT75_SET) -#define CCM_POST_ROOT75_CLR_REG(base) ((base)->POST_ROOT75_CLR) -#define CCM_POST_ROOT75_TOG_REG(base) ((base)->POST_ROOT75_TOG) -#define CCM_PRE75_REG(base) ((base)->PRE75) -#define CCM_PRE_ROOT75_SET_REG(base) ((base)->PRE_ROOT75_SET) -#define CCM_PRE_ROOT75_CLR_REG(base) ((base)->PRE_ROOT75_CLR) -#define CCM_PRE_ROOT75_TOG_REG(base) ((base)->PRE_ROOT75_TOG) -#define CCM_ACCESS_CTRL75_REG(base) ((base)->ACCESS_CTRL75) -#define CCM_ACCESS_CTRL75_ROOT_SET_REG(base) ((base)->ACCESS_CTRL75_ROOT_SET) -#define CCM_ACCESS_CTRL75_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL75_ROOT_CLR) -#define CCM_ACCESS_CTRL75_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL75_ROOT_TOG) -#define CCM_TARGET_ROOT76_REG(base) ((base)->TARGET_ROOT76) -#define CCM_TARGET_ROOT76_SET_REG(base) ((base)->TARGET_ROOT76_SET) -#define CCM_TARGET_ROOT76_CLR_REG(base) ((base)->TARGET_ROOT76_CLR) -#define CCM_TARGET_ROOT76_TOG_REG(base) ((base)->TARGET_ROOT76_TOG) -#define CCM_POST76_REG(base) ((base)->POST76) -#define CCM_POST_ROOT76_SET_REG(base) ((base)->POST_ROOT76_SET) -#define CCM_POST_ROOT76_CLR_REG(base) ((base)->POST_ROOT76_CLR) -#define CCM_POST_ROOT76_TOG_REG(base) ((base)->POST_ROOT76_TOG) -#define CCM_PRE76_REG(base) ((base)->PRE76) -#define CCM_PRE_ROOT76_SET_REG(base) ((base)->PRE_ROOT76_SET) -#define CCM_PRE_ROOT76_CLR_REG(base) ((base)->PRE_ROOT76_CLR) -#define CCM_PRE_ROOT76_TOG_REG(base) ((base)->PRE_ROOT76_TOG) -#define CCM_ACCESS_CTRL76_REG(base) ((base)->ACCESS_CTRL76) -#define CCM_ACCESS_CTRL76_ROOT_SET_REG(base) ((base)->ACCESS_CTRL76_ROOT_SET) -#define CCM_ACCESS_CTRL76_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL76_ROOT_CLR) -#define CCM_ACCESS_CTRL76_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL76_ROOT_TOG) -#define CCM_TARGET_ROOT77_REG(base) ((base)->TARGET_ROOT77) -#define CCM_TARGET_ROOT77_SET_REG(base) ((base)->TARGET_ROOT77_SET) -#define CCM_TARGET_ROOT77_CLR_REG(base) ((base)->TARGET_ROOT77_CLR) -#define CCM_TARGET_ROOT77_TOG_REG(base) ((base)->TARGET_ROOT77_TOG) -#define CCM_POST77_REG(base) ((base)->POST77) -#define CCM_POST_ROOT77_SET_REG(base) ((base)->POST_ROOT77_SET) -#define CCM_POST_ROOT77_CLR_REG(base) ((base)->POST_ROOT77_CLR) -#define CCM_POST_ROOT77_TOG_REG(base) ((base)->POST_ROOT77_TOG) -#define CCM_PRE77_REG(base) ((base)->PRE77) -#define CCM_PRE_ROOT77_SET_REG(base) ((base)->PRE_ROOT77_SET) -#define CCM_PRE_ROOT77_CLR_REG(base) ((base)->PRE_ROOT77_CLR) -#define CCM_PRE_ROOT77_TOG_REG(base) ((base)->PRE_ROOT77_TOG) -#define CCM_ACCESS_CTRL77_REG(base) ((base)->ACCESS_CTRL77) -#define CCM_ACCESS_CTRL77_ROOT_SET_REG(base) ((base)->ACCESS_CTRL77_ROOT_SET) -#define CCM_ACCESS_CTRL77_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL77_ROOT_CLR) -#define CCM_ACCESS_CTRL77_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL77_ROOT_TOG) -#define CCM_TARGET_ROOT78_REG(base) ((base)->TARGET_ROOT78) -#define CCM_TARGET_ROOT78_SET_REG(base) ((base)->TARGET_ROOT78_SET) -#define CCM_TARGET_ROOT78_CLR_REG(base) ((base)->TARGET_ROOT78_CLR) -#define CCM_TARGET_ROOT78_TOG_REG(base) ((base)->TARGET_ROOT78_TOG) -#define CCM_POST78_REG(base) ((base)->POST78) -#define CCM_POST_ROOT78_SET_REG(base) ((base)->POST_ROOT78_SET) -#define CCM_POST_ROOT78_CLR_REG(base) ((base)->POST_ROOT78_CLR) -#define CCM_POST_ROOT78_TOG_REG(base) ((base)->POST_ROOT78_TOG) -#define CCM_PRE78_REG(base) ((base)->PRE78) -#define CCM_PRE_ROOT78_SET_REG(base) ((base)->PRE_ROOT78_SET) -#define CCM_PRE_ROOT78_CLR_REG(base) ((base)->PRE_ROOT78_CLR) -#define CCM_PRE_ROOT78_TOG_REG(base) ((base)->PRE_ROOT78_TOG) -#define CCM_ACCESS_CTRL78_REG(base) ((base)->ACCESS_CTRL78) -#define CCM_ACCESS_CTRL78_ROOT_SET_REG(base) ((base)->ACCESS_CTRL78_ROOT_SET) -#define CCM_ACCESS_CTRL78_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL78_ROOT_CLR) -#define CCM_ACCESS_CTRL78_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL78_ROOT_TOG) -#define CCM_TARGET_ROOT79_REG(base) ((base)->TARGET_ROOT79) -#define CCM_TARGET_ROOT79_SET_REG(base) ((base)->TARGET_ROOT79_SET) -#define CCM_TARGET_ROOT79_CLR_REG(base) ((base)->TARGET_ROOT79_CLR) -#define CCM_TARGET_ROOT79_TOG_REG(base) ((base)->TARGET_ROOT79_TOG) -#define CCM_POST79_REG(base) ((base)->POST79) -#define CCM_POST_ROOT79_SET_REG(base) ((base)->POST_ROOT79_SET) -#define CCM_POST_ROOT79_CLR_REG(base) ((base)->POST_ROOT79_CLR) -#define CCM_POST_ROOT79_TOG_REG(base) ((base)->POST_ROOT79_TOG) -#define CCM_PRE79_REG(base) ((base)->PRE79) -#define CCM_PRE_ROOT79_SET_REG(base) ((base)->PRE_ROOT79_SET) -#define CCM_PRE_ROOT79_CLR_REG(base) ((base)->PRE_ROOT79_CLR) -#define CCM_PRE_ROOT79_TOG_REG(base) ((base)->PRE_ROOT79_TOG) -#define CCM_ACCESS_CTRL79_REG(base) ((base)->ACCESS_CTRL79) -#define CCM_ACCESS_CTRL79_ROOT_SET_REG(base) ((base)->ACCESS_CTRL79_ROOT_SET) -#define CCM_ACCESS_CTRL79_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL79_ROOT_CLR) -#define CCM_ACCESS_CTRL79_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL79_ROOT_TOG) -#define CCM_TARGET_ROOT80_REG(base) ((base)->TARGET_ROOT80) -#define CCM_TARGET_ROOT80_SET_REG(base) ((base)->TARGET_ROOT80_SET) -#define CCM_TARGET_ROOT80_CLR_REG(base) ((base)->TARGET_ROOT80_CLR) -#define CCM_TARGET_ROOT80_TOG_REG(base) ((base)->TARGET_ROOT80_TOG) -#define CCM_POST80_REG(base) ((base)->POST80) -#define CCM_POST_ROOT80_SET_REG(base) ((base)->POST_ROOT80_SET) -#define CCM_POST_ROOT80_CLR_REG(base) ((base)->POST_ROOT80_CLR) -#define CCM_POST_ROOT80_TOG_REG(base) ((base)->POST_ROOT80_TOG) -#define CCM_PRE80_REG(base) ((base)->PRE80) -#define CCM_PRE_ROOT80_SET_REG(base) ((base)->PRE_ROOT80_SET) -#define CCM_PRE_ROOT80_CLR_REG(base) ((base)->PRE_ROOT80_CLR) -#define CCM_PRE_ROOT80_TOG_REG(base) ((base)->PRE_ROOT80_TOG) -#define CCM_ACCESS_CTRL80_REG(base) ((base)->ACCESS_CTRL80) -#define CCM_ACCESS_CTRL80_ROOT_SET_REG(base) ((base)->ACCESS_CTRL80_ROOT_SET) -#define CCM_ACCESS_CTRL80_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL80_ROOT_CLR) -#define CCM_ACCESS_CTRL80_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL80_ROOT_TOG) -#define CCM_TARGET_ROOT81_REG(base) ((base)->TARGET_ROOT81) -#define CCM_TARGET_ROOT81_SET_REG(base) ((base)->TARGET_ROOT81_SET) -#define CCM_TARGET_ROOT81_CLR_REG(base) ((base)->TARGET_ROOT81_CLR) -#define CCM_TARGET_ROOT81_TOG_REG(base) ((base)->TARGET_ROOT81_TOG) -#define CCM_POST81_REG(base) ((base)->POST81) -#define CCM_POST_ROOT81_SET_REG(base) ((base)->POST_ROOT81_SET) -#define CCM_POST_ROOT81_CLR_REG(base) ((base)->POST_ROOT81_CLR) -#define CCM_POST_ROOT81_TOG_REG(base) ((base)->POST_ROOT81_TOG) -#define CCM_PRE81_REG(base) ((base)->PRE81) -#define CCM_PRE_ROOT81_SET_REG(base) ((base)->PRE_ROOT81_SET) -#define CCM_PRE_ROOT81_CLR_REG(base) ((base)->PRE_ROOT81_CLR) -#define CCM_PRE_ROOT81_TOG_REG(base) ((base)->PRE_ROOT81_TOG) -#define CCM_ACCESS_CTRL81_REG(base) ((base)->ACCESS_CTRL81) -#define CCM_ACCESS_CTRL81_ROOT_SET_REG(base) ((base)->ACCESS_CTRL81_ROOT_SET) -#define CCM_ACCESS_CTRL81_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL81_ROOT_CLR) -#define CCM_ACCESS_CTRL81_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL81_ROOT_TOG) -#define CCM_TARGET_ROOT82_REG(base) ((base)->TARGET_ROOT82) -#define CCM_TARGET_ROOT82_SET_REG(base) ((base)->TARGET_ROOT82_SET) -#define CCM_TARGET_ROOT82_CLR_REG(base) ((base)->TARGET_ROOT82_CLR) -#define CCM_TARGET_ROOT82_TOG_REG(base) ((base)->TARGET_ROOT82_TOG) -#define CCM_POST82_REG(base) ((base)->POST82) -#define CCM_POST_ROOT82_SET_REG(base) ((base)->POST_ROOT82_SET) -#define CCM_POST_ROOT82_CLR_REG(base) ((base)->POST_ROOT82_CLR) -#define CCM_POST_ROOT82_TOG_REG(base) ((base)->POST_ROOT82_TOG) -#define CCM_PRE82_REG(base) ((base)->PRE82) -#define CCM_PRE_ROOT82_SET_REG(base) ((base)->PRE_ROOT82_SET) -#define CCM_PRE_ROOT82_CLR_REG(base) ((base)->PRE_ROOT82_CLR) -#define CCM_PRE_ROOT82_TOG_REG(base) ((base)->PRE_ROOT82_TOG) -#define CCM_ACCESS_CTRL82_REG(base) ((base)->ACCESS_CTRL82) -#define CCM_ACCESS_CTRL82_ROOT_SET_REG(base) ((base)->ACCESS_CTRL82_ROOT_SET) -#define CCM_ACCESS_CTRL82_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL82_ROOT_CLR) -#define CCM_ACCESS_CTRL82_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL82_ROOT_TOG) -#define CCM_TARGET_ROOT83_REG(base) ((base)->TARGET_ROOT83) -#define CCM_TARGET_ROOT83_SET_REG(base) ((base)->TARGET_ROOT83_SET) -#define CCM_TARGET_ROOT83_CLR_REG(base) ((base)->TARGET_ROOT83_CLR) -#define CCM_TARGET_ROOT83_TOG_REG(base) ((base)->TARGET_ROOT83_TOG) -#define CCM_POST83_REG(base) ((base)->POST83) -#define CCM_POST_ROOT83_SET_REG(base) ((base)->POST_ROOT83_SET) -#define CCM_POST_ROOT83_CLR_REG(base) ((base)->POST_ROOT83_CLR) -#define CCM_POST_ROOT83_TOG_REG(base) ((base)->POST_ROOT83_TOG) -#define CCM_PRE83_REG(base) ((base)->PRE83) -#define CCM_PRE_ROOT83_SET_REG(base) ((base)->PRE_ROOT83_SET) -#define CCM_PRE_ROOT83_CLR_REG(base) ((base)->PRE_ROOT83_CLR) -#define CCM_PRE_ROOT83_TOG_REG(base) ((base)->PRE_ROOT83_TOG) -#define CCM_ACCESS_CTRL83_REG(base) ((base)->ACCESS_CTRL83) -#define CCM_ACCESS_CTRL83_ROOT_SET_REG(base) ((base)->ACCESS_CTRL83_ROOT_SET) -#define CCM_ACCESS_CTRL83_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL83_ROOT_CLR) -#define CCM_ACCESS_CTRL83_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL83_ROOT_TOG) -#define CCM_TARGET_ROOT84_REG(base) ((base)->TARGET_ROOT84) -#define CCM_TARGET_ROOT84_SET_REG(base) ((base)->TARGET_ROOT84_SET) -#define CCM_TARGET_ROOT84_CLR_REG(base) ((base)->TARGET_ROOT84_CLR) -#define CCM_TARGET_ROOT84_TOG_REG(base) ((base)->TARGET_ROOT84_TOG) -#define CCM_POST84_REG(base) ((base)->POST84) -#define CCM_POST_ROOT84_SET_REG(base) ((base)->POST_ROOT84_SET) -#define CCM_POST_ROOT84_CLR_REG(base) ((base)->POST_ROOT84_CLR) -#define CCM_POST_ROOT84_TOG_REG(base) ((base)->POST_ROOT84_TOG) -#define CCM_PRE84_REG(base) ((base)->PRE84) -#define CCM_PRE_ROOT84_SET_REG(base) ((base)->PRE_ROOT84_SET) -#define CCM_PRE_ROOT84_CLR_REG(base) ((base)->PRE_ROOT84_CLR) -#define CCM_PRE_ROOT84_TOG_REG(base) ((base)->PRE_ROOT84_TOG) -#define CCM_ACCESS_CTRL84_REG(base) ((base)->ACCESS_CTRL84) -#define CCM_ACCESS_CTRL84_ROOT_SET_REG(base) ((base)->ACCESS_CTRL84_ROOT_SET) -#define CCM_ACCESS_CTRL84_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL84_ROOT_CLR) -#define CCM_ACCESS_CTRL84_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL84_ROOT_TOG) -#define CCM_TARGET_ROOT85_REG(base) ((base)->TARGET_ROOT85) -#define CCM_TARGET_ROOT85_SET_REG(base) ((base)->TARGET_ROOT85_SET) -#define CCM_TARGET_ROOT85_CLR_REG(base) ((base)->TARGET_ROOT85_CLR) -#define CCM_TARGET_ROOT85_TOG_REG(base) ((base)->TARGET_ROOT85_TOG) -#define CCM_POST85_REG(base) ((base)->POST85) -#define CCM_POST_ROOT85_SET_REG(base) ((base)->POST_ROOT85_SET) -#define CCM_POST_ROOT85_CLR_REG(base) ((base)->POST_ROOT85_CLR) -#define CCM_POST_ROOT85_TOG_REG(base) ((base)->POST_ROOT85_TOG) -#define CCM_PRE85_REG(base) ((base)->PRE85) -#define CCM_PRE_ROOT85_SET_REG(base) ((base)->PRE_ROOT85_SET) -#define CCM_PRE_ROOT85_CLR_REG(base) ((base)->PRE_ROOT85_CLR) -#define CCM_PRE_ROOT85_TOG_REG(base) ((base)->PRE_ROOT85_TOG) -#define CCM_ACCESS_CTRL85_REG(base) ((base)->ACCESS_CTRL85) -#define CCM_ACCESS_CTRL85_ROOT_SET_REG(base) ((base)->ACCESS_CTRL85_ROOT_SET) -#define CCM_ACCESS_CTRL85_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL85_ROOT_CLR) -#define CCM_ACCESS_CTRL85_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL85_ROOT_TOG) -#define CCM_TARGET_ROOT86_REG(base) ((base)->TARGET_ROOT86) -#define CCM_TARGET_ROOT86_SET_REG(base) ((base)->TARGET_ROOT86_SET) -#define CCM_TARGET_ROOT86_CLR_REG(base) ((base)->TARGET_ROOT86_CLR) -#define CCM_TARGET_ROOT86_TOG_REG(base) ((base)->TARGET_ROOT86_TOG) -#define CCM_POST86_REG(base) ((base)->POST86) -#define CCM_POST_ROOT86_SET_REG(base) ((base)->POST_ROOT86_SET) -#define CCM_POST_ROOT86_CLR_REG(base) ((base)->POST_ROOT86_CLR) -#define CCM_POST_ROOT86_TOG_REG(base) ((base)->POST_ROOT86_TOG) -#define CCM_PRE86_REG(base) ((base)->PRE86) -#define CCM_PRE_ROOT86_SET_REG(base) ((base)->PRE_ROOT86_SET) -#define CCM_PRE_ROOT86_CLR_REG(base) ((base)->PRE_ROOT86_CLR) -#define CCM_PRE_ROOT86_TOG_REG(base) ((base)->PRE_ROOT86_TOG) -#define CCM_ACCESS_CTRL86_REG(base) ((base)->ACCESS_CTRL86) -#define CCM_ACCESS_CTRL86_ROOT_SET_REG(base) ((base)->ACCESS_CTRL86_ROOT_SET) -#define CCM_ACCESS_CTRL86_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL86_ROOT_CLR) -#define CCM_ACCESS_CTRL86_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL86_ROOT_TOG) -#define CCM_TARGET_ROOT87_REG(base) ((base)->TARGET_ROOT87) -#define CCM_TARGET_ROOT87_SET_REG(base) ((base)->TARGET_ROOT87_SET) -#define CCM_TARGET_ROOT87_CLR_REG(base) ((base)->TARGET_ROOT87_CLR) -#define CCM_TARGET_ROOT87_TOG_REG(base) ((base)->TARGET_ROOT87_TOG) -#define CCM_POST87_REG(base) ((base)->POST87) -#define CCM_POST_ROOT87_SET_REG(base) ((base)->POST_ROOT87_SET) -#define CCM_POST_ROOT87_CLR_REG(base) ((base)->POST_ROOT87_CLR) -#define CCM_POST_ROOT87_TOG_REG(base) ((base)->POST_ROOT87_TOG) -#define CCM_PRE87_REG(base) ((base)->PRE87) -#define CCM_PRE_ROOT87_SET_REG(base) ((base)->PRE_ROOT87_SET) -#define CCM_PRE_ROOT87_CLR_REG(base) ((base)->PRE_ROOT87_CLR) -#define CCM_PRE_ROOT87_TOG_REG(base) ((base)->PRE_ROOT87_TOG) -#define CCM_ACCESS_CTRL87_REG(base) ((base)->ACCESS_CTRL87) -#define CCM_ACCESS_CTRL87_ROOT_SET_REG(base) ((base)->ACCESS_CTRL87_ROOT_SET) -#define CCM_ACCESS_CTRL87_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL87_ROOT_CLR) -#define CCM_ACCESS_CTRL87_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL87_ROOT_TOG) -#define CCM_TARGET_ROOT88_REG(base) ((base)->TARGET_ROOT88) -#define CCM_TARGET_ROOT88_SET_REG(base) ((base)->TARGET_ROOT88_SET) -#define CCM_TARGET_ROOT88_CLR_REG(base) ((base)->TARGET_ROOT88_CLR) -#define CCM_TARGET_ROOT88_TOG_REG(base) ((base)->TARGET_ROOT88_TOG) -#define CCM_POST88_REG(base) ((base)->POST88) -#define CCM_POST_ROOT88_SET_REG(base) ((base)->POST_ROOT88_SET) -#define CCM_POST_ROOT88_CLR_REG(base) ((base)->POST_ROOT88_CLR) -#define CCM_POST_ROOT88_TOG_REG(base) ((base)->POST_ROOT88_TOG) -#define CCM_PRE88_REG(base) ((base)->PRE88) -#define CCM_PRE_ROOT88_SET_REG(base) ((base)->PRE_ROOT88_SET) -#define CCM_PRE_ROOT88_CLR_REG(base) ((base)->PRE_ROOT88_CLR) -#define CCM_PRE_ROOT88_TOG_REG(base) ((base)->PRE_ROOT88_TOG) -#define CCM_ACCESS_CTRL88_REG(base) ((base)->ACCESS_CTRL88) -#define CCM_ACCESS_CTRL88_ROOT_SET_REG(base) ((base)->ACCESS_CTRL88_ROOT_SET) -#define CCM_ACCESS_CTRL88_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL88_ROOT_CLR) -#define CCM_ACCESS_CTRL88_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL88_ROOT_TOG) -#define CCM_TARGET_ROOT89_REG(base) ((base)->TARGET_ROOT89) -#define CCM_TARGET_ROOT89_SET_REG(base) ((base)->TARGET_ROOT89_SET) -#define CCM_TARGET_ROOT89_CLR_REG(base) ((base)->TARGET_ROOT89_CLR) -#define CCM_TARGET_ROOT89_TOG_REG(base) ((base)->TARGET_ROOT89_TOG) -#define CCM_POST89_REG(base) ((base)->POST89) -#define CCM_POST_ROOT89_SET_REG(base) ((base)->POST_ROOT89_SET) -#define CCM_POST_ROOT89_CLR_REG(base) ((base)->POST_ROOT89_CLR) -#define CCM_POST_ROOT89_TOG_REG(base) ((base)->POST_ROOT89_TOG) -#define CCM_PRE89_REG(base) ((base)->PRE89) -#define CCM_PRE_ROOT89_SET_REG(base) ((base)->PRE_ROOT89_SET) -#define CCM_PRE_ROOT89_CLR_REG(base) ((base)->PRE_ROOT89_CLR) -#define CCM_PRE_ROOT89_TOG_REG(base) ((base)->PRE_ROOT89_TOG) -#define CCM_ACCESS_CTRL89_REG(base) ((base)->ACCESS_CTRL89) -#define CCM_ACCESS_CTRL89_ROOT_SET_REG(base) ((base)->ACCESS_CTRL89_ROOT_SET) -#define CCM_ACCESS_CTRL89_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL89_ROOT_CLR) -#define CCM_ACCESS_CTRL89_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL89_ROOT_TOG) -#define CCM_TARGET_ROOT90_REG(base) ((base)->TARGET_ROOT90) -#define CCM_TARGET_ROOT90_SET_REG(base) ((base)->TARGET_ROOT90_SET) -#define CCM_TARGET_ROOT90_CLR_REG(base) ((base)->TARGET_ROOT90_CLR) -#define CCM_TARGET_ROOT90_TOG_REG(base) ((base)->TARGET_ROOT90_TOG) -#define CCM_POST90_REG(base) ((base)->POST90) -#define CCM_POST_ROOT90_SET_REG(base) ((base)->POST_ROOT90_SET) -#define CCM_POST_ROOT90_CLR_REG(base) ((base)->POST_ROOT90_CLR) -#define CCM_POST_ROOT90_TOG_REG(base) ((base)->POST_ROOT90_TOG) -#define CCM_PRE90_REG(base) ((base)->PRE90) -#define CCM_PRE_ROOT90_SET_REG(base) ((base)->PRE_ROOT90_SET) -#define CCM_PRE_ROOT90_CLR_REG(base) ((base)->PRE_ROOT90_CLR) -#define CCM_PRE_ROOT90_TOG_REG(base) ((base)->PRE_ROOT90_TOG) -#define CCM_ACCESS_CTRL90_REG(base) ((base)->ACCESS_CTRL90) -#define CCM_ACCESS_CTRL90_ROOT_SET_REG(base) ((base)->ACCESS_CTRL90_ROOT_SET) -#define CCM_ACCESS_CTRL90_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL90_ROOT_CLR) -#define CCM_ACCESS_CTRL90_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL90_ROOT_TOG) -#define CCM_TARGET_ROOT91_REG(base) ((base)->TARGET_ROOT91) -#define CCM_TARGET_ROOT91_SET_REG(base) ((base)->TARGET_ROOT91_SET) -#define CCM_TARGET_ROOT91_CLR_REG(base) ((base)->TARGET_ROOT91_CLR) -#define CCM_TARGET_ROOT91_TOG_REG(base) ((base)->TARGET_ROOT91_TOG) -#define CCM_POST91_REG(base) ((base)->POST91) -#define CCM_POST_ROOT91_SET_REG(base) ((base)->POST_ROOT91_SET) -#define CCM_POST_ROOT91_CLR_REG(base) ((base)->POST_ROOT91_CLR) -#define CCM_POST_ROOT91_TOG_REG(base) ((base)->POST_ROOT91_TOG) -#define CCM_PRE91_REG(base) ((base)->PRE91) -#define CCM_PRE_ROOT91_SET_REG(base) ((base)->PRE_ROOT91_SET) -#define CCM_PRE_ROOT91_CLR_REG(base) ((base)->PRE_ROOT91_CLR) -#define CCM_PRE_ROOT91_TOG_REG(base) ((base)->PRE_ROOT91_TOG) -#define CCM_ACCESS_CTRL91_REG(base) ((base)->ACCESS_CTRL91) -#define CCM_ACCESS_CTRL91_ROOT_SET_REG(base) ((base)->ACCESS_CTRL91_ROOT_SET) -#define CCM_ACCESS_CTRL91_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL91_ROOT_CLR) -#define CCM_ACCESS_CTRL91_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL91_ROOT_TOG) -#define CCM_TARGET_ROOT92_REG(base) ((base)->TARGET_ROOT92) -#define CCM_TARGET_ROOT92_SET_REG(base) ((base)->TARGET_ROOT92_SET) -#define CCM_TARGET_ROOT92_CLR_REG(base) ((base)->TARGET_ROOT92_CLR) -#define CCM_TARGET_ROOT92_TOG_REG(base) ((base)->TARGET_ROOT92_TOG) -#define CCM_POST92_REG(base) ((base)->POST92) -#define CCM_POST_ROOT92_SET_REG(base) ((base)->POST_ROOT92_SET) -#define CCM_POST_ROOT92_CLR_REG(base) ((base)->POST_ROOT92_CLR) -#define CCM_POST_ROOT92_TOG_REG(base) ((base)->POST_ROOT92_TOG) -#define CCM_PRE92_REG(base) ((base)->PRE92) -#define CCM_PRE_ROOT92_SET_REG(base) ((base)->PRE_ROOT92_SET) -#define CCM_PRE_ROOT92_CLR_REG(base) ((base)->PRE_ROOT92_CLR) -#define CCM_PRE_ROOT92_TOG_REG(base) ((base)->PRE_ROOT92_TOG) -#define CCM_ACCESS_CTRL92_REG(base) ((base)->ACCESS_CTRL92) -#define CCM_ACCESS_CTRL92_ROOT_SET_REG(base) ((base)->ACCESS_CTRL92_ROOT_SET) -#define CCM_ACCESS_CTRL92_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL92_ROOT_CLR) -#define CCM_ACCESS_CTRL92_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL92_ROOT_TOG) -#define CCM_TARGET_ROOT93_REG(base) ((base)->TARGET_ROOT93) -#define CCM_TARGET_ROOT93_SET_REG(base) ((base)->TARGET_ROOT93_SET) -#define CCM_TARGET_ROOT93_CLR_REG(base) ((base)->TARGET_ROOT93_CLR) -#define CCM_TARGET_ROOT93_TOG_REG(base) ((base)->TARGET_ROOT93_TOG) -#define CCM_POST93_REG(base) ((base)->POST93) -#define CCM_POST_ROOT93_SET_REG(base) ((base)->POST_ROOT93_SET) -#define CCM_POST_ROOT93_CLR_REG(base) ((base)->POST_ROOT93_CLR) -#define CCM_POST_ROOT93_TOG_REG(base) ((base)->POST_ROOT93_TOG) -#define CCM_PRE93_REG(base) ((base)->PRE93) -#define CCM_PRE_ROOT93_SET_REG(base) ((base)->PRE_ROOT93_SET) -#define CCM_PRE_ROOT93_CLR_REG(base) ((base)->PRE_ROOT93_CLR) -#define CCM_PRE_ROOT93_TOG_REG(base) ((base)->PRE_ROOT93_TOG) -#define CCM_ACCESS_CTRL93_REG(base) ((base)->ACCESS_CTRL93) -#define CCM_ACCESS_CTRL93_ROOT_SET_REG(base) ((base)->ACCESS_CTRL93_ROOT_SET) -#define CCM_ACCESS_CTRL93_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL93_ROOT_CLR) -#define CCM_ACCESS_CTRL93_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL93_ROOT_TOG) -#define CCM_TARGET_ROOT94_REG(base) ((base)->TARGET_ROOT94) -#define CCM_TARGET_ROOT94_SET_REG(base) ((base)->TARGET_ROOT94_SET) -#define CCM_TARGET_ROOT94_CLR_REG(base) ((base)->TARGET_ROOT94_CLR) -#define CCM_TARGET_ROOT94_TOG_REG(base) ((base)->TARGET_ROOT94_TOG) -#define CCM_POST94_REG(base) ((base)->POST94) -#define CCM_POST_ROOT94_SET_REG(base) ((base)->POST_ROOT94_SET) -#define CCM_POST_ROOT94_CLR_REG(base) ((base)->POST_ROOT94_CLR) -#define CCM_POST_ROOT94_TOG_REG(base) ((base)->POST_ROOT94_TOG) -#define CCM_PRE94_REG(base) ((base)->PRE94) -#define CCM_PRE_ROOT94_SET_REG(base) ((base)->PRE_ROOT94_SET) -#define CCM_PRE_ROOT94_CLR_REG(base) ((base)->PRE_ROOT94_CLR) -#define CCM_PRE_ROOT94_TOG_REG(base) ((base)->PRE_ROOT94_TOG) -#define CCM_ACCESS_CTRL94_REG(base) ((base)->ACCESS_CTRL94) -#define CCM_ACCESS_CTRL94_ROOT_SET_REG(base) ((base)->ACCESS_CTRL94_ROOT_SET) -#define CCM_ACCESS_CTRL94_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL94_ROOT_CLR) -#define CCM_ACCESS_CTRL94_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL94_ROOT_TOG) -#define CCM_TARGET_ROOT95_REG(base) ((base)->TARGET_ROOT95) -#define CCM_TARGET_ROOT95_SET_REG(base) ((base)->TARGET_ROOT95_SET) -#define CCM_TARGET_ROOT95_CLR_REG(base) ((base)->TARGET_ROOT95_CLR) -#define CCM_TARGET_ROOT95_TOG_REG(base) ((base)->TARGET_ROOT95_TOG) -#define CCM_POST95_REG(base) ((base)->POST95) -#define CCM_POST_ROOT95_SET_REG(base) ((base)->POST_ROOT95_SET) -#define CCM_POST_ROOT95_CLR_REG(base) ((base)->POST_ROOT95_CLR) -#define CCM_POST_ROOT95_TOG_REG(base) ((base)->POST_ROOT95_TOG) -#define CCM_PRE95_REG(base) ((base)->PRE95) -#define CCM_PRE_ROOT95_SET_REG(base) ((base)->PRE_ROOT95_SET) -#define CCM_PRE_ROOT95_CLR_REG(base) ((base)->PRE_ROOT95_CLR) -#define CCM_PRE_ROOT95_TOG_REG(base) ((base)->PRE_ROOT95_TOG) -#define CCM_ACCESS_CTRL95_REG(base) ((base)->ACCESS_CTRL95) -#define CCM_ACCESS_CTRL95_ROOT_SET_REG(base) ((base)->ACCESS_CTRL95_ROOT_SET) -#define CCM_ACCESS_CTRL95_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL95_ROOT_CLR) -#define CCM_ACCESS_CTRL95_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL95_ROOT_TOG) -#define CCM_TARGET_ROOT96_REG(base) ((base)->TARGET_ROOT96) -#define CCM_TARGET_ROOT96_SET_REG(base) ((base)->TARGET_ROOT96_SET) -#define CCM_TARGET_ROOT96_CLR_REG(base) ((base)->TARGET_ROOT96_CLR) -#define CCM_TARGET_ROOT96_TOG_REG(base) ((base)->TARGET_ROOT96_TOG) -#define CCM_POST96_REG(base) ((base)->POST96) -#define CCM_POST_ROOT96_SET_REG(base) ((base)->POST_ROOT96_SET) -#define CCM_POST_ROOT96_CLR_REG(base) ((base)->POST_ROOT96_CLR) -#define CCM_POST_ROOT96_TOG_REG(base) ((base)->POST_ROOT96_TOG) -#define CCM_PRE96_REG(base) ((base)->PRE96) -#define CCM_PRE_ROOT96_SET_REG(base) ((base)->PRE_ROOT96_SET) -#define CCM_PRE_ROOT96_CLR_REG(base) ((base)->PRE_ROOT96_CLR) -#define CCM_PRE_ROOT96_TOG_REG(base) ((base)->PRE_ROOT96_TOG) -#define CCM_ACCESS_CTRL96_REG(base) ((base)->ACCESS_CTRL96) -#define CCM_ACCESS_CTRL96_ROOT_SET_REG(base) ((base)->ACCESS_CTRL96_ROOT_SET) -#define CCM_ACCESS_CTRL96_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL96_ROOT_CLR) -#define CCM_ACCESS_CTRL96_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL96_ROOT_TOG) -#define CCM_TARGET_ROOT97_REG(base) ((base)->TARGET_ROOT97) -#define CCM_TARGET_ROOT97_SET_REG(base) ((base)->TARGET_ROOT97_SET) -#define CCM_TARGET_ROOT97_CLR_REG(base) ((base)->TARGET_ROOT97_CLR) -#define CCM_TARGET_ROOT97_TOG_REG(base) ((base)->TARGET_ROOT97_TOG) -#define CCM_POST97_REG(base) ((base)->POST97) -#define CCM_POST_ROOT97_SET_REG(base) ((base)->POST_ROOT97_SET) -#define CCM_POST_ROOT97_CLR_REG(base) ((base)->POST_ROOT97_CLR) -#define CCM_POST_ROOT97_TOG_REG(base) ((base)->POST_ROOT97_TOG) -#define CCM_PRE97_REG(base) ((base)->PRE97) -#define CCM_PRE_ROOT97_SET_REG(base) ((base)->PRE_ROOT97_SET) -#define CCM_PRE_ROOT97_CLR_REG(base) ((base)->PRE_ROOT97_CLR) -#define CCM_PRE_ROOT97_TOG_REG(base) ((base)->PRE_ROOT97_TOG) -#define CCM_ACCESS_CTRL97_REG(base) ((base)->ACCESS_CTRL97) -#define CCM_ACCESS_CTRL97_ROOT_SET_REG(base) ((base)->ACCESS_CTRL97_ROOT_SET) -#define CCM_ACCESS_CTRL97_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL97_ROOT_CLR) -#define CCM_ACCESS_CTRL97_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL97_ROOT_TOG) -#define CCM_TARGET_ROOT98_REG(base) ((base)->TARGET_ROOT98) -#define CCM_TARGET_ROOT98_SET_REG(base) ((base)->TARGET_ROOT98_SET) -#define CCM_TARGET_ROOT98_CLR_REG(base) ((base)->TARGET_ROOT98_CLR) -#define CCM_TARGET_ROOT98_TOG_REG(base) ((base)->TARGET_ROOT98_TOG) -#define CCM_POST98_REG(base) ((base)->POST98) -#define CCM_POST_ROOT98_SET_REG(base) ((base)->POST_ROOT98_SET) -#define CCM_POST_ROOT98_CLR_REG(base) ((base)->POST_ROOT98_CLR) -#define CCM_POST_ROOT98_TOG_REG(base) ((base)->POST_ROOT98_TOG) -#define CCM_PRE98_REG(base) ((base)->PRE98) -#define CCM_PRE_ROOT98_SET_REG(base) ((base)->PRE_ROOT98_SET) -#define CCM_PRE_ROOT98_CLR_REG(base) ((base)->PRE_ROOT98_CLR) -#define CCM_PRE_ROOT98_TOG_REG(base) ((base)->PRE_ROOT98_TOG) -#define CCM_ACCESS_CTRL98_REG(base) ((base)->ACCESS_CTRL98) -#define CCM_ACCESS_CTRL98_ROOT_SET_REG(base) ((base)->ACCESS_CTRL98_ROOT_SET) -#define CCM_ACCESS_CTRL98_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL98_ROOT_CLR) -#define CCM_ACCESS_CTRL98_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL98_ROOT_TOG) -#define CCM_TARGET_ROOT99_REG(base) ((base)->TARGET_ROOT99) -#define CCM_TARGET_ROOT99_SET_REG(base) ((base)->TARGET_ROOT99_SET) -#define CCM_TARGET_ROOT99_CLR_REG(base) ((base)->TARGET_ROOT99_CLR) -#define CCM_TARGET_ROOT99_TOG_REG(base) ((base)->TARGET_ROOT99_TOG) -#define CCM_POST99_REG(base) ((base)->POST99) -#define CCM_POST_ROOT99_SET_REG(base) ((base)->POST_ROOT99_SET) -#define CCM_POST_ROOT99_CLR_REG(base) ((base)->POST_ROOT99_CLR) -#define CCM_POST_ROOT99_TOG_REG(base) ((base)->POST_ROOT99_TOG) -#define CCM_PRE99_REG(base) ((base)->PRE99) -#define CCM_PRE_ROOT99_SET_REG(base) ((base)->PRE_ROOT99_SET) -#define CCM_PRE_ROOT99_CLR_REG(base) ((base)->PRE_ROOT99_CLR) -#define CCM_PRE_ROOT99_TOG_REG(base) ((base)->PRE_ROOT99_TOG) -#define CCM_ACCESS_CTRL99_REG(base) ((base)->ACCESS_CTRL99) -#define CCM_ACCESS_CTRL99_ROOT_SET_REG(base) ((base)->ACCESS_CTRL99_ROOT_SET) -#define CCM_ACCESS_CTRL99_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL99_ROOT_CLR) -#define CCM_ACCESS_CTRL99_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL99_ROOT_TOG) -#define CCM_TARGET_ROOT100_REG(base) ((base)->TARGET_ROOT100) -#define CCM_TARGET_ROOT100_SET_REG(base) ((base)->TARGET_ROOT100_SET) -#define CCM_TARGET_ROOT100_CLR_REG(base) ((base)->TARGET_ROOT100_CLR) -#define CCM_TARGET_ROOT100_TOG_REG(base) ((base)->TARGET_ROOT100_TOG) -#define CCM_POST100_REG(base) ((base)->POST100) -#define CCM_POST_ROOT100_SET_REG(base) ((base)->POST_ROOT100_SET) -#define CCM_POST_ROOT100_CLR_REG(base) ((base)->POST_ROOT100_CLR) -#define CCM_POST_ROOT100_TOG_REG(base) ((base)->POST_ROOT100_TOG) -#define CCM_PRE100_REG(base) ((base)->PRE100) -#define CCM_PRE_ROOT100_SET_REG(base) ((base)->PRE_ROOT100_SET) -#define CCM_PRE_ROOT100_CLR_REG(base) ((base)->PRE_ROOT100_CLR) -#define CCM_PRE_ROOT100_TOG_REG(base) ((base)->PRE_ROOT100_TOG) -#define CCM_ACCESS_CTRL100_REG(base) ((base)->ACCESS_CTRL100) -#define CCM_ACCESS_CTRL100_ROOT_SET_REG(base) ((base)->ACCESS_CTRL100_ROOT_SET) -#define CCM_ACCESS_CTRL100_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL100_ROOT_CLR) -#define CCM_ACCESS_CTRL100_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL100_ROOT_TOG) -#define CCM_TARGET_ROOT101_REG(base) ((base)->TARGET_ROOT101) -#define CCM_TARGET_ROOT101_SET_REG(base) ((base)->TARGET_ROOT101_SET) -#define CCM_TARGET_ROOT101_CLR_REG(base) ((base)->TARGET_ROOT101_CLR) -#define CCM_TARGET_ROOT101_TOG_REG(base) ((base)->TARGET_ROOT101_TOG) -#define CCM_POST101_REG(base) ((base)->POST101) -#define CCM_POST_ROOT101_SET_REG(base) ((base)->POST_ROOT101_SET) -#define CCM_POST_ROOT101_CLR_REG(base) ((base)->POST_ROOT101_CLR) -#define CCM_POST_ROOT101_TOG_REG(base) ((base)->POST_ROOT101_TOG) -#define CCM_PRE101_REG(base) ((base)->PRE101) -#define CCM_PRE_ROOT101_SET_REG(base) ((base)->PRE_ROOT101_SET) -#define CCM_PRE_ROOT101_CLR_REG(base) ((base)->PRE_ROOT101_CLR) -#define CCM_PRE_ROOT101_TOG_REG(base) ((base)->PRE_ROOT101_TOG) -#define CCM_ACCESS_CTRL101_REG(base) ((base)->ACCESS_CTRL101) -#define CCM_ACCESS_CTRL101_ROOT_SET_REG(base) ((base)->ACCESS_CTRL101_ROOT_SET) -#define CCM_ACCESS_CTRL101_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL101_ROOT_CLR) -#define CCM_ACCESS_CTRL101_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL101_ROOT_TOG) -#define CCM_TARGET_ROOT102_REG(base) ((base)->TARGET_ROOT102) -#define CCM_TARGET_ROOT102_SET_REG(base) ((base)->TARGET_ROOT102_SET) -#define CCM_TARGET_ROOT102_CLR_REG(base) ((base)->TARGET_ROOT102_CLR) -#define CCM_TARGET_ROOT102_TOG_REG(base) ((base)->TARGET_ROOT102_TOG) -#define CCM_POST102_REG(base) ((base)->POST102) -#define CCM_POST_ROOT102_SET_REG(base) ((base)->POST_ROOT102_SET) -#define CCM_POST_ROOT102_CLR_REG(base) ((base)->POST_ROOT102_CLR) -#define CCM_POST_ROOT102_TOG_REG(base) ((base)->POST_ROOT102_TOG) -#define CCM_PRE102_REG(base) ((base)->PRE102) -#define CCM_PRE_ROOT102_SET_REG(base) ((base)->PRE_ROOT102_SET) -#define CCM_PRE_ROOT102_CLR_REG(base) ((base)->PRE_ROOT102_CLR) -#define CCM_PRE_ROOT102_TOG_REG(base) ((base)->PRE_ROOT102_TOG) -#define CCM_ACCESS_CTRL102_REG(base) ((base)->ACCESS_CTRL102) -#define CCM_ACCESS_CTRL102_ROOT_SET_REG(base) ((base)->ACCESS_CTRL102_ROOT_SET) -#define CCM_ACCESS_CTRL102_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL102_ROOT_CLR) -#define CCM_ACCESS_CTRL102_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL102_ROOT_TOG) -#define CCM_TARGET_ROOT103_REG(base) ((base)->TARGET_ROOT103) -#define CCM_TARGET_ROOT103_SET_REG(base) ((base)->TARGET_ROOT103_SET) -#define CCM_TARGET_ROOT103_CLR_REG(base) ((base)->TARGET_ROOT103_CLR) -#define CCM_TARGET_ROOT103_TOG_REG(base) ((base)->TARGET_ROOT103_TOG) -#define CCM_POST103_REG(base) ((base)->POST103) -#define CCM_POST_ROOT103_SET_REG(base) ((base)->POST_ROOT103_SET) -#define CCM_POST_ROOT103_CLR_REG(base) ((base)->POST_ROOT103_CLR) -#define CCM_POST_ROOT103_TOG_REG(base) ((base)->POST_ROOT103_TOG) -#define CCM_PRE103_REG(base) ((base)->PRE103) -#define CCM_PRE_ROOT103_SET_REG(base) ((base)->PRE_ROOT103_SET) -#define CCM_PRE_ROOT103_CLR_REG(base) ((base)->PRE_ROOT103_CLR) -#define CCM_PRE_ROOT103_TOG_REG(base) ((base)->PRE_ROOT103_TOG) -#define CCM_ACCESS_CTRL103_REG(base) ((base)->ACCESS_CTRL103) -#define CCM_ACCESS_CTRL103_ROOT_SET_REG(base) ((base)->ACCESS_CTRL103_ROOT_SET) -#define CCM_ACCESS_CTRL103_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL103_ROOT_CLR) -#define CCM_ACCESS_CTRL103_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL103_ROOT_TOG) -#define CCM_TARGET_ROOT104_REG(base) ((base)->TARGET_ROOT104) -#define CCM_TARGET_ROOT104_SET_REG(base) ((base)->TARGET_ROOT104_SET) -#define CCM_TARGET_ROOT104_CLR_REG(base) ((base)->TARGET_ROOT104_CLR) -#define CCM_TARGET_ROOT104_TOG_REG(base) ((base)->TARGET_ROOT104_TOG) -#define CCM_POST104_REG(base) ((base)->POST104) -#define CCM_POST_ROOT104_SET_REG(base) ((base)->POST_ROOT104_SET) -#define CCM_POST_ROOT104_CLR_REG(base) ((base)->POST_ROOT104_CLR) -#define CCM_POST_ROOT104_TOG_REG(base) ((base)->POST_ROOT104_TOG) -#define CCM_PRE104_REG(base) ((base)->PRE104) -#define CCM_PRE_ROOT104_SET_REG(base) ((base)->PRE_ROOT104_SET) -#define CCM_PRE_ROOT104_CLR_REG(base) ((base)->PRE_ROOT104_CLR) -#define CCM_PRE_ROOT104_TOG_REG(base) ((base)->PRE_ROOT104_TOG) -#define CCM_ACCESS_CTRL104_REG(base) ((base)->ACCESS_CTRL104) -#define CCM_ACCESS_CTRL104_ROOT_SET_REG(base) ((base)->ACCESS_CTRL104_ROOT_SET) -#define CCM_ACCESS_CTRL104_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL104_ROOT_CLR) -#define CCM_ACCESS_CTRL104_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL104_ROOT_TOG) -#define CCM_TARGET_ROOT105_REG(base) ((base)->TARGET_ROOT105) -#define CCM_TARGET_ROOT105_SET_REG(base) ((base)->TARGET_ROOT105_SET) -#define CCM_TARGET_ROOT105_CLR_REG(base) ((base)->TARGET_ROOT105_CLR) -#define CCM_TARGET_ROOT105_TOG_REG(base) ((base)->TARGET_ROOT105_TOG) -#define CCM_POST105_REG(base) ((base)->POST105) -#define CCM_POST_ROOT105_SET_REG(base) ((base)->POST_ROOT105_SET) -#define CCM_POST_ROOT105_CLR_REG(base) ((base)->POST_ROOT105_CLR) -#define CCM_POST_ROOT105_TOG_REG(base) ((base)->POST_ROOT105_TOG) -#define CCM_PRE105_REG(base) ((base)->PRE105) -#define CCM_PRE_ROOT105_SET_REG(base) ((base)->PRE_ROOT105_SET) -#define CCM_PRE_ROOT105_CLR_REG(base) ((base)->PRE_ROOT105_CLR) -#define CCM_PRE_ROOT105_TOG_REG(base) ((base)->PRE_ROOT105_TOG) -#define CCM_ACCESS_CTRL105_REG(base) ((base)->ACCESS_CTRL105) -#define CCM_ACCESS_CTRL105_ROOT_SET_REG(base) ((base)->ACCESS_CTRL105_ROOT_SET) -#define CCM_ACCESS_CTRL105_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL105_ROOT_CLR) -#define CCM_ACCESS_CTRL105_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL105_ROOT_TOG) -#define CCM_TARGET_ROOT106_REG(base) ((base)->TARGET_ROOT106) -#define CCM_TARGET_ROOT106_SET_REG(base) ((base)->TARGET_ROOT106_SET) -#define CCM_TARGET_ROOT106_CLR_REG(base) ((base)->TARGET_ROOT106_CLR) -#define CCM_TARGET_ROOT106_TOG_REG(base) ((base)->TARGET_ROOT106_TOG) -#define CCM_POST106_REG(base) ((base)->POST106) -#define CCM_POST_ROOT106_SET_REG(base) ((base)->POST_ROOT106_SET) -#define CCM_POST_ROOT106_CLR_REG(base) ((base)->POST_ROOT106_CLR) -#define CCM_POST_ROOT106_TOG_REG(base) ((base)->POST_ROOT106_TOG) -#define CCM_PRE106_REG(base) ((base)->PRE106) -#define CCM_PRE_ROOT106_SET_REG(base) ((base)->PRE_ROOT106_SET) -#define CCM_PRE_ROOT106_CLR_REG(base) ((base)->PRE_ROOT106_CLR) -#define CCM_PRE_ROOT106_TOG_REG(base) ((base)->PRE_ROOT106_TOG) -#define CCM_ACCESS_CTRL106_REG(base) ((base)->ACCESS_CTRL106) -#define CCM_ACCESS_CTRL106_ROOT_SET_REG(base) ((base)->ACCESS_CTRL106_ROOT_SET) -#define CCM_ACCESS_CTRL106_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL106_ROOT_CLR) -#define CCM_ACCESS_CTRL106_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL106_ROOT_TOG) -#define CCM_TARGET_ROOT107_REG(base) ((base)->TARGET_ROOT107) -#define CCM_TARGET_ROOT107_SET_REG(base) ((base)->TARGET_ROOT107_SET) -#define CCM_TARGET_ROOT107_CLR_REG(base) ((base)->TARGET_ROOT107_CLR) -#define CCM_TARGET_ROOT107_TOG_REG(base) ((base)->TARGET_ROOT107_TOG) -#define CCM_POST107_REG(base) ((base)->POST107) -#define CCM_POST_ROOT107_SET_REG(base) ((base)->POST_ROOT107_SET) -#define CCM_POST_ROOT107_CLR_REG(base) ((base)->POST_ROOT107_CLR) -#define CCM_POST_ROOT107_TOG_REG(base) ((base)->POST_ROOT107_TOG) -#define CCM_PRE107_REG(base) ((base)->PRE107) -#define CCM_PRE_ROOT107_SET_REG(base) ((base)->PRE_ROOT107_SET) -#define CCM_PRE_ROOT107_CLR_REG(base) ((base)->PRE_ROOT107_CLR) -#define CCM_PRE_ROOT107_TOG_REG(base) ((base)->PRE_ROOT107_TOG) -#define CCM_ACCESS_CTRL107_REG(base) ((base)->ACCESS_CTRL107) -#define CCM_ACCESS_CTRL107_ROOT_SET_REG(base) ((base)->ACCESS_CTRL107_ROOT_SET) -#define CCM_ACCESS_CTRL107_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL107_ROOT_CLR) -#define CCM_ACCESS_CTRL107_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL107_ROOT_TOG) -#define CCM_TARGET_ROOT108_REG(base) ((base)->TARGET_ROOT108) -#define CCM_TARGET_ROOT108_SET_REG(base) ((base)->TARGET_ROOT108_SET) -#define CCM_TARGET_ROOT108_CLR_REG(base) ((base)->TARGET_ROOT108_CLR) -#define CCM_TARGET_ROOT108_TOG_REG(base) ((base)->TARGET_ROOT108_TOG) -#define CCM_POST108_REG(base) ((base)->POST108) -#define CCM_POST_ROOT108_SET_REG(base) ((base)->POST_ROOT108_SET) -#define CCM_POST_ROOT108_CLR_REG(base) ((base)->POST_ROOT108_CLR) -#define CCM_POST_ROOT108_TOG_REG(base) ((base)->POST_ROOT108_TOG) -#define CCM_PRE108_REG(base) ((base)->PRE108) -#define CCM_PRE_ROOT108_SET_REG(base) ((base)->PRE_ROOT108_SET) -#define CCM_PRE_ROOT108_CLR_REG(base) ((base)->PRE_ROOT108_CLR) -#define CCM_PRE_ROOT108_TOG_REG(base) ((base)->PRE_ROOT108_TOG) -#define CCM_ACCESS_CTRL108_REG(base) ((base)->ACCESS_CTRL108) -#define CCM_ACCESS_CTRL108_ROOT_SET_REG(base) ((base)->ACCESS_CTRL108_ROOT_SET) -#define CCM_ACCESS_CTRL108_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL108_ROOT_CLR) -#define CCM_ACCESS_CTRL108_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL108_ROOT_TOG) -#define CCM_TARGET_ROOT109_REG(base) ((base)->TARGET_ROOT109) -#define CCM_TARGET_ROOT109_SET_REG(base) ((base)->TARGET_ROOT109_SET) -#define CCM_TARGET_ROOT109_CLR_REG(base) ((base)->TARGET_ROOT109_CLR) -#define CCM_TARGET_ROOT109_TOG_REG(base) ((base)->TARGET_ROOT109_TOG) -#define CCM_POST109_REG(base) ((base)->POST109) -#define CCM_POST_ROOT109_SET_REG(base) ((base)->POST_ROOT109_SET) -#define CCM_POST_ROOT109_CLR_REG(base) ((base)->POST_ROOT109_CLR) -#define CCM_POST_ROOT109_TOG_REG(base) ((base)->POST_ROOT109_TOG) -#define CCM_PRE109_REG(base) ((base)->PRE109) -#define CCM_PRE_ROOT109_SET_REG(base) ((base)->PRE_ROOT109_SET) -#define CCM_PRE_ROOT109_CLR_REG(base) ((base)->PRE_ROOT109_CLR) -#define CCM_PRE_ROOT109_TOG_REG(base) ((base)->PRE_ROOT109_TOG) -#define CCM_ACCESS_CTRL109_REG(base) ((base)->ACCESS_CTRL109) -#define CCM_ACCESS_CTRL109_ROOT_SET_REG(base) ((base)->ACCESS_CTRL109_ROOT_SET) -#define CCM_ACCESS_CTRL109_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL109_ROOT_CLR) -#define CCM_ACCESS_CTRL109_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL109_ROOT_TOG) -#define CCM_TARGET_ROOT110_REG(base) ((base)->TARGET_ROOT110) -#define CCM_TARGET_ROOT110_SET_REG(base) ((base)->TARGET_ROOT110_SET) -#define CCM_TARGET_ROOT110_CLR_REG(base) ((base)->TARGET_ROOT110_CLR) -#define CCM_TARGET_ROOT110_TOG_REG(base) ((base)->TARGET_ROOT110_TOG) -#define CCM_POST110_REG(base) ((base)->POST110) -#define CCM_POST_ROOT110_SET_REG(base) ((base)->POST_ROOT110_SET) -#define CCM_POST_ROOT110_CLR_REG(base) ((base)->POST_ROOT110_CLR) -#define CCM_POST_ROOT110_TOG_REG(base) ((base)->POST_ROOT110_TOG) -#define CCM_PRE110_REG(base) ((base)->PRE110) -#define CCM_PRE_ROOT110_SET_REG(base) ((base)->PRE_ROOT110_SET) -#define CCM_PRE_ROOT110_CLR_REG(base) ((base)->PRE_ROOT110_CLR) -#define CCM_PRE_ROOT110_TOG_REG(base) ((base)->PRE_ROOT110_TOG) -#define CCM_ACCESS_CTRL110_REG(base) ((base)->ACCESS_CTRL110) -#define CCM_ACCESS_CTRL110_ROOT_SET_REG(base) ((base)->ACCESS_CTRL110_ROOT_SET) -#define CCM_ACCESS_CTRL110_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL110_ROOT_CLR) -#define CCM_ACCESS_CTRL110_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL110_ROOT_TOG) -#define CCM_TARGET_ROOT111_REG(base) ((base)->TARGET_ROOT111) -#define CCM_TARGET_ROOT111_SET_REG(base) ((base)->TARGET_ROOT111_SET) -#define CCM_TARGET_ROOT111_CLR_REG(base) ((base)->TARGET_ROOT111_CLR) -#define CCM_TARGET_ROOT111_TOG_REG(base) ((base)->TARGET_ROOT111_TOG) -#define CCM_POST111_REG(base) ((base)->POST111) -#define CCM_POST_ROOT111_SET_REG(base) ((base)->POST_ROOT111_SET) -#define CCM_POST_ROOT111_CLR_REG(base) ((base)->POST_ROOT111_CLR) -#define CCM_POST_ROOT111_TOG_REG(base) ((base)->POST_ROOT111_TOG) -#define CCM_PRE111_REG(base) ((base)->PRE111) -#define CCM_PRE_ROOT111_SET_REG(base) ((base)->PRE_ROOT111_SET) -#define CCM_PRE_ROOT111_CLR_REG(base) ((base)->PRE_ROOT111_CLR) -#define CCM_PRE_ROOT111_TOG_REG(base) ((base)->PRE_ROOT111_TOG) -#define CCM_ACCESS_CTRL111_REG(base) ((base)->ACCESS_CTRL111) -#define CCM_ACCESS_CTRL111_ROOT_SET_REG(base) ((base)->ACCESS_CTRL111_ROOT_SET) -#define CCM_ACCESS_CTRL111_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL111_ROOT_CLR) -#define CCM_ACCESS_CTRL111_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL111_ROOT_TOG) -#define CCM_TARGET_ROOT112_REG(base) ((base)->TARGET_ROOT112) -#define CCM_TARGET_ROOT112_SET_REG(base) ((base)->TARGET_ROOT112_SET) -#define CCM_TARGET_ROOT112_CLR_REG(base) ((base)->TARGET_ROOT112_CLR) -#define CCM_TARGET_ROOT112_TOG_REG(base) ((base)->TARGET_ROOT112_TOG) -#define CCM_POST112_REG(base) ((base)->POST112) -#define CCM_POST_ROOT112_SET_REG(base) ((base)->POST_ROOT112_SET) -#define CCM_POST_ROOT112_CLR_REG(base) ((base)->POST_ROOT112_CLR) -#define CCM_POST_ROOT112_TOG_REG(base) ((base)->POST_ROOT112_TOG) -#define CCM_PRE112_REG(base) ((base)->PRE112) -#define CCM_PRE_ROOT112_SET_REG(base) ((base)->PRE_ROOT112_SET) -#define CCM_PRE_ROOT112_CLR_REG(base) ((base)->PRE_ROOT112_CLR) -#define CCM_PRE_ROOT112_TOG_REG(base) ((base)->PRE_ROOT112_TOG) -#define CCM_ACCESS_CTRL112_REG(base) ((base)->ACCESS_CTRL112) -#define CCM_ACCESS_CTRL112_ROOT_SET_REG(base) ((base)->ACCESS_CTRL112_ROOT_SET) -#define CCM_ACCESS_CTRL112_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL112_ROOT_CLR) -#define CCM_ACCESS_CTRL112_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL112_ROOT_TOG) -#define CCM_TARGET_ROOT113_REG(base) ((base)->TARGET_ROOT113) -#define CCM_TARGET_ROOT113_SET_REG(base) ((base)->TARGET_ROOT113_SET) -#define CCM_TARGET_ROOT113_CLR_REG(base) ((base)->TARGET_ROOT113_CLR) -#define CCM_TARGET_ROOT113_TOG_REG(base) ((base)->TARGET_ROOT113_TOG) -#define CCM_POST113_REG(base) ((base)->POST113) -#define CCM_POST_ROOT113_SET_REG(base) ((base)->POST_ROOT113_SET) -#define CCM_POST_ROOT113_CLR_REG(base) ((base)->POST_ROOT113_CLR) -#define CCM_POST_ROOT113_TOG_REG(base) ((base)->POST_ROOT113_TOG) -#define CCM_PRE113_REG(base) ((base)->PRE113) -#define CCM_PRE_ROOT113_SET_REG(base) ((base)->PRE_ROOT113_SET) -#define CCM_PRE_ROOT113_CLR_REG(base) ((base)->PRE_ROOT113_CLR) -#define CCM_PRE_ROOT113_TOG_REG(base) ((base)->PRE_ROOT113_TOG) -#define CCM_ACCESS_CTRL113_REG(base) ((base)->ACCESS_CTRL113) -#define CCM_ACCESS_CTRL113_ROOT_SET_REG(base) ((base)->ACCESS_CTRL113_ROOT_SET) -#define CCM_ACCESS_CTRL113_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL113_ROOT_CLR) -#define CCM_ACCESS_CTRL113_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL113_ROOT_TOG) -#define CCM_TARGET_ROOT114_REG(base) ((base)->TARGET_ROOT114) -#define CCM_TARGET_ROOT114_SET_REG(base) ((base)->TARGET_ROOT114_SET) -#define CCM_TARGET_ROOT114_CLR_REG(base) ((base)->TARGET_ROOT114_CLR) -#define CCM_TARGET_ROOT114_TOG_REG(base) ((base)->TARGET_ROOT114_TOG) -#define CCM_POST114_REG(base) ((base)->POST114) -#define CCM_POST_ROOT114_SET_REG(base) ((base)->POST_ROOT114_SET) -#define CCM_POST_ROOT114_CLR_REG(base) ((base)->POST_ROOT114_CLR) -#define CCM_POST_ROOT114_TOG_REG(base) ((base)->POST_ROOT114_TOG) -#define CCM_PRE114_REG(base) ((base)->PRE114) -#define CCM_PRE_ROOT114_SET_REG(base) ((base)->PRE_ROOT114_SET) -#define CCM_PRE_ROOT114_CLR_REG(base) ((base)->PRE_ROOT114_CLR) -#define CCM_PRE_ROOT114_TOG_REG(base) ((base)->PRE_ROOT114_TOG) -#define CCM_ACCESS_CTRL114_REG(base) ((base)->ACCESS_CTRL114) -#define CCM_ACCESS_CTRL114_ROOT_SET_REG(base) ((base)->ACCESS_CTRL114_ROOT_SET) -#define CCM_ACCESS_CTRL114_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL114_ROOT_CLR) -#define CCM_ACCESS_CTRL114_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL114_ROOT_TOG) -#define CCM_TARGET_ROOT115_REG(base) ((base)->TARGET_ROOT115) -#define CCM_TARGET_ROOT115_SET_REG(base) ((base)->TARGET_ROOT115_SET) -#define CCM_TARGET_ROOT115_CLR_REG(base) ((base)->TARGET_ROOT115_CLR) -#define CCM_TARGET_ROOT115_TOG_REG(base) ((base)->TARGET_ROOT115_TOG) -#define CCM_POST115_REG(base) ((base)->POST115) -#define CCM_POST_ROOT115_SET_REG(base) ((base)->POST_ROOT115_SET) -#define CCM_POST_ROOT115_CLR_REG(base) ((base)->POST_ROOT115_CLR) -#define CCM_POST_ROOT115_TOG_REG(base) ((base)->POST_ROOT115_TOG) -#define CCM_PRE115_REG(base) ((base)->PRE115) -#define CCM_PRE_ROOT115_SET_REG(base) ((base)->PRE_ROOT115_SET) -#define CCM_PRE_ROOT115_CLR_REG(base) ((base)->PRE_ROOT115_CLR) -#define CCM_PRE_ROOT115_TOG_REG(base) ((base)->PRE_ROOT115_TOG) -#define CCM_ACCESS_CTRL115_REG(base) ((base)->ACCESS_CTRL115) -#define CCM_ACCESS_CTRL115_ROOT_SET_REG(base) ((base)->ACCESS_CTRL115_ROOT_SET) -#define CCM_ACCESS_CTRL115_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL115_ROOT_CLR) -#define CCM_ACCESS_CTRL115_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL115_ROOT_TOG) -#define CCM_TARGET_ROOT116_REG(base) ((base)->TARGET_ROOT116) -#define CCM_TARGET_ROOT116_SET_REG(base) ((base)->TARGET_ROOT116_SET) -#define CCM_TARGET_ROOT116_CLR_REG(base) ((base)->TARGET_ROOT116_CLR) -#define CCM_TARGET_ROOT116_TOG_REG(base) ((base)->TARGET_ROOT116_TOG) -#define CCM_POST116_REG(base) ((base)->POST116) -#define CCM_POST_ROOT116_SET_REG(base) ((base)->POST_ROOT116_SET) -#define CCM_POST_ROOT116_CLR_REG(base) ((base)->POST_ROOT116_CLR) -#define CCM_POST_ROOT116_TOG_REG(base) ((base)->POST_ROOT116_TOG) -#define CCM_PRE116_REG(base) ((base)->PRE116) -#define CCM_PRE_ROOT116_SET_REG(base) ((base)->PRE_ROOT116_SET) -#define CCM_PRE_ROOT116_CLR_REG(base) ((base)->PRE_ROOT116_CLR) -#define CCM_PRE_ROOT116_TOG_REG(base) ((base)->PRE_ROOT116_TOG) -#define CCM_ACCESS_CTRL116_REG(base) ((base)->ACCESS_CTRL116) -#define CCM_ACCESS_CTRL116_ROOT_SET_REG(base) ((base)->ACCESS_CTRL116_ROOT_SET) -#define CCM_ACCESS_CTRL116_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL116_ROOT_CLR) -#define CCM_ACCESS_CTRL116_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL116_ROOT_TOG) -#define CCM_TARGET_ROOT117_REG(base) ((base)->TARGET_ROOT117) -#define CCM_TARGET_ROOT117_SET_REG(base) ((base)->TARGET_ROOT117_SET) -#define CCM_TARGET_ROOT117_CLR_REG(base) ((base)->TARGET_ROOT117_CLR) -#define CCM_TARGET_ROOT117_TOG_REG(base) ((base)->TARGET_ROOT117_TOG) -#define CCM_POST117_REG(base) ((base)->POST117) -#define CCM_POST_ROOT117_SET_REG(base) ((base)->POST_ROOT117_SET) -#define CCM_POST_ROOT117_CLR_REG(base) ((base)->POST_ROOT117_CLR) -#define CCM_POST_ROOT117_TOG_REG(base) ((base)->POST_ROOT117_TOG) -#define CCM_PRE117_REG(base) ((base)->PRE117) -#define CCM_PRE_ROOT117_SET_REG(base) ((base)->PRE_ROOT117_SET) -#define CCM_PRE_ROOT117_CLR_REG(base) ((base)->PRE_ROOT117_CLR) -#define CCM_PRE_ROOT117_TOG_REG(base) ((base)->PRE_ROOT117_TOG) -#define CCM_ACCESS_CTRL117_REG(base) ((base)->ACCESS_CTRL117) -#define CCM_ACCESS_CTRL117_ROOT_SET_REG(base) ((base)->ACCESS_CTRL117_ROOT_SET) -#define CCM_ACCESS_CTRL117_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL117_ROOT_CLR) -#define CCM_ACCESS_CTRL117_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL117_ROOT_TOG) -#define CCM_TARGET_ROOT118_REG(base) ((base)->TARGET_ROOT118) -#define CCM_TARGET_ROOT118_SET_REG(base) ((base)->TARGET_ROOT118_SET) -#define CCM_TARGET_ROOT118_CLR_REG(base) ((base)->TARGET_ROOT118_CLR) -#define CCM_TARGET_ROOT118_TOG_REG(base) ((base)->TARGET_ROOT118_TOG) -#define CCM_POST118_REG(base) ((base)->POST118) -#define CCM_POST_ROOT118_SET_REG(base) ((base)->POST_ROOT118_SET) -#define CCM_POST_ROOT118_CLR_REG(base) ((base)->POST_ROOT118_CLR) -#define CCM_POST_ROOT118_TOG_REG(base) ((base)->POST_ROOT118_TOG) -#define CCM_PRE118_REG(base) ((base)->PRE118) -#define CCM_PRE_ROOT118_SET_REG(base) ((base)->PRE_ROOT118_SET) -#define CCM_PRE_ROOT118_CLR_REG(base) ((base)->PRE_ROOT118_CLR) -#define CCM_PRE_ROOT118_TOG_REG(base) ((base)->PRE_ROOT118_TOG) -#define CCM_ACCESS_CTRL118_REG(base) ((base)->ACCESS_CTRL118) -#define CCM_ACCESS_CTRL118_ROOT_SET_REG(base) ((base)->ACCESS_CTRL118_ROOT_SET) -#define CCM_ACCESS_CTRL118_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL118_ROOT_CLR) -#define CCM_ACCESS_CTRL118_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL118_ROOT_TOG) -#define CCM_TARGET_ROOT119_REG(base) ((base)->TARGET_ROOT119) -#define CCM_TARGET_ROOT119_SET_REG(base) ((base)->TARGET_ROOT119_SET) -#define CCM_TARGET_ROOT119_CLR_REG(base) ((base)->TARGET_ROOT119_CLR) -#define CCM_TARGET_ROOT119_TOG_REG(base) ((base)->TARGET_ROOT119_TOG) -#define CCM_POST119_REG(base) ((base)->POST119) -#define CCM_POST_ROOT119_SET_REG(base) ((base)->POST_ROOT119_SET) -#define CCM_POST_ROOT119_CLR_REG(base) ((base)->POST_ROOT119_CLR) -#define CCM_POST_ROOT119_TOG_REG(base) ((base)->POST_ROOT119_TOG) -#define CCM_PRE119_REG(base) ((base)->PRE119) -#define CCM_PRE_ROOT119_SET_REG(base) ((base)->PRE_ROOT119_SET) -#define CCM_PRE_ROOT119_CLR_REG(base) ((base)->PRE_ROOT119_CLR) -#define CCM_PRE_ROOT119_TOG_REG(base) ((base)->PRE_ROOT119_TOG) -#define CCM_ACCESS_CTRL119_REG(base) ((base)->ACCESS_CTRL119) -#define CCM_ACCESS_CTRL119_ROOT_SET_REG(base) ((base)->ACCESS_CTRL119_ROOT_SET) -#define CCM_ACCESS_CTRL119_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL119_ROOT_CLR) -#define CCM_ACCESS_CTRL119_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL119_ROOT_TOG) -#define CCM_TARGET_ROOT120_REG(base) ((base)->TARGET_ROOT120) -#define CCM_TARGET_ROOT120_SET_REG(base) ((base)->TARGET_ROOT120_SET) -#define CCM_TARGET_ROOT120_CLR_REG(base) ((base)->TARGET_ROOT120_CLR) -#define CCM_TARGET_ROOT120_TOG_REG(base) ((base)->TARGET_ROOT120_TOG) -#define CCM_POST120_REG(base) ((base)->POST120) -#define CCM_POST_ROOT120_SET_REG(base) ((base)->POST_ROOT120_SET) -#define CCM_POST_ROOT120_CLR_REG(base) ((base)->POST_ROOT120_CLR) -#define CCM_POST_ROOT120_TOG_REG(base) ((base)->POST_ROOT120_TOG) -#define CCM_PRE120_REG(base) ((base)->PRE120) -#define CCM_PRE_ROOT120_SET_REG(base) ((base)->PRE_ROOT120_SET) -#define CCM_PRE_ROOT120_CLR_REG(base) ((base)->PRE_ROOT120_CLR) -#define CCM_PRE_ROOT120_TOG_REG(base) ((base)->PRE_ROOT120_TOG) -#define CCM_ACCESS_CTRL120_REG(base) ((base)->ACCESS_CTRL120) -#define CCM_ACCESS_CTRL120_ROOT_SET_REG(base) ((base)->ACCESS_CTRL120_ROOT_SET) -#define CCM_ACCESS_CTRL120_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL120_ROOT_CLR) -#define CCM_ACCESS_CTRL120_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL120_ROOT_TOG) +#define CCM_PLL_CTRL_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL) +#define CCM_PLL_CTRL_SET_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_SET) +#define CCM_PLL_CTRL_CLR_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_CLR) +#define CCM_PLL_CTRL_TOG_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_TOG) +#define CCM_CCGR_REG(base,index) ((base)->CCGR[index].CCGR) +#define CCM_CCGR_SET_REG(base,index) ((base)->CCGR[index].CCGR_SET) +#define CCM_CCGR_CLR_REG(base,index) ((base)->CCGR[index].CCGR_CLR) +#define CCM_CCGR_TOG_REG(base,index) ((base)->CCGR[index].CCGR_TOG) +#define CCM_TARGET_ROOT_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT) +#define CCM_TARGET_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_SET) +#define CCM_TARGET_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_CLR) +#define CCM_TARGET_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_TOG) +#define CCM_MISC_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC) +#define CCM_MISC_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_SET) +#define CCM_MISC_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_CLR) +#define CCM_MISC_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_TOG) +#define CCM_POST_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST) +#define CCM_POST_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_SET) +#define CCM_POST_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_CLR) +#define CCM_POST_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_TOG) +#define CCM_PRE_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE) +#define CCM_PRE_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_SET) +#define CCM_PRE_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_CLR) +#define CCM_PRE_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_TOG) +#define CCM_ACCESS_CTRL_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL) +#define CCM_ACCESS_CTRL_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_SET) +#define CCM_ACCESS_CTRL_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_CLR) +#define CCM_ACCESS_CTRL_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_TOG) /*! * @} */ /* end of group CCM_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- CCM Register Masks ---------------------------------------------------------------------------- */ @@ -9876,47651 +4645,461 @@ typedef struct { #define CCM_GPR0_TOG_GP0_MASK 0xFFFFFFFFu #define CCM_GPR0_TOG_GP0_SHIFT 0 #define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_TOG_GP0_SHIFT))&CCM_GPR0_TOG_GP0_MASK) -/* PLL_CTRL0 Bit Fields */ -#define CCM_PLL_CTRL0_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL0_CG_SHIFT 0 -#define CCM_PLL_CTRL0_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL0_CG_SHIFT))&CCM_PLL_CTRL0_CG_MASK) -/* PLL_CTRL0_SET Bit Fields */ -#define CCM_PLL_CTRL0_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL0_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL0_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL0_SET_CG_SHIFT))&CCM_PLL_CTRL0_SET_CG_MASK) -/* PLL_CTRL0_CLR Bit Fields */ -#define CCM_PLL_CTRL0_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL0_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL0_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL0_CLR_CG_SHIFT))&CCM_PLL_CTRL0_CLR_CG_MASK) -/* PLL_CTRL0_TOG Bit Fields */ -#define CCM_PLL_CTRL0_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL0_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL0_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL0_TOG_CG_SHIFT))&CCM_PLL_CTRL0_TOG_CG_MASK) -/* PLL_CTRL1 Bit Fields */ -#define CCM_PLL_CTRL1_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL1_CG_SHIFT 0 -#define CCM_PLL_CTRL1_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL1_CG_SHIFT))&CCM_PLL_CTRL1_CG_MASK) -/* PLL_CTRL1_SET Bit Fields */ -#define CCM_PLL_CTRL1_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL1_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL1_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL1_SET_CG_SHIFT))&CCM_PLL_CTRL1_SET_CG_MASK) -/* PLL_CTRL1_CLR Bit Fields */ -#define CCM_PLL_CTRL1_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL1_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL1_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL1_CLR_CG_SHIFT))&CCM_PLL_CTRL1_CLR_CG_MASK) -/* PLL_CTRL1_TOG Bit Fields */ -#define CCM_PLL_CTRL1_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL1_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL1_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL1_TOG_CG_SHIFT))&CCM_PLL_CTRL1_TOG_CG_MASK) -/* PLL_CTRL2 Bit Fields */ -#define CCM_PLL_CTRL2_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL2_CG_SHIFT 0 -#define CCM_PLL_CTRL2_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL2_CG_SHIFT))&CCM_PLL_CTRL2_CG_MASK) -/* PLL_CTRL2_SET Bit Fields */ -#define CCM_PLL_CTRL2_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL2_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL2_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL2_SET_CG_SHIFT))&CCM_PLL_CTRL2_SET_CG_MASK) -/* PLL_CTRL2_CLR Bit Fields */ -#define CCM_PLL_CTRL2_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL2_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL2_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL2_CLR_CG_SHIFT))&CCM_PLL_CTRL2_CLR_CG_MASK) -/* PLL_CTRL2_TOG Bit Fields */ -#define CCM_PLL_CTRL2_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL2_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL2_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL2_TOG_CG_SHIFT))&CCM_PLL_CTRL2_TOG_CG_MASK) -/* PLL_CTRL3 Bit Fields */ -#define CCM_PLL_CTRL3_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL3_CG_SHIFT 0 -#define CCM_PLL_CTRL3_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL3_CG_SHIFT))&CCM_PLL_CTRL3_CG_MASK) -/* PLL_CTRL3_SET Bit Fields */ -#define CCM_PLL_CTRL3_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL3_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL3_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL3_SET_CG_SHIFT))&CCM_PLL_CTRL3_SET_CG_MASK) -/* PLL_CTRL3_CLR Bit Fields */ -#define CCM_PLL_CTRL3_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL3_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL3_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL3_CLR_CG_SHIFT))&CCM_PLL_CTRL3_CLR_CG_MASK) -/* PLL_CTRL3_TOG Bit Fields */ -#define CCM_PLL_CTRL3_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL3_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL3_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL3_TOG_CG_SHIFT))&CCM_PLL_CTRL3_TOG_CG_MASK) -/* PLL_CTRL4 Bit Fields */ -#define CCM_PLL_CTRL4_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL4_CG_SHIFT 0 -#define CCM_PLL_CTRL4_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL4_CG_SHIFT))&CCM_PLL_CTRL4_CG_MASK) -/* PLL_CTRL4_SET Bit Fields */ -#define CCM_PLL_CTRL4_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL4_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL4_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL4_SET_CG_SHIFT))&CCM_PLL_CTRL4_SET_CG_MASK) -/* PLL_CTRL4_CLR Bit Fields */ -#define CCM_PLL_CTRL4_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL4_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL4_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL4_CLR_CG_SHIFT))&CCM_PLL_CTRL4_CLR_CG_MASK) -/* PLL_CTRL4_TOG Bit Fields */ -#define CCM_PLL_CTRL4_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL4_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL4_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL4_TOG_CG_SHIFT))&CCM_PLL_CTRL4_TOG_CG_MASK) -/* PLL_CTRL5 Bit Fields */ -#define CCM_PLL_CTRL5_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL5_CG_SHIFT 0 -#define CCM_PLL_CTRL5_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL5_CG_SHIFT))&CCM_PLL_CTRL5_CG_MASK) -/* PLL_CTRL5_SET Bit Fields */ -#define CCM_PLL_CTRL5_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL5_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL5_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL5_SET_CG_SHIFT))&CCM_PLL_CTRL5_SET_CG_MASK) -/* PLL_CTRL5_CLR Bit Fields */ -#define CCM_PLL_CTRL5_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL5_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL5_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL5_CLR_CG_SHIFT))&CCM_PLL_CTRL5_CLR_CG_MASK) -/* PLL_CTRL5_TOG Bit Fields */ -#define CCM_PLL_CTRL5_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL5_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL5_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL5_TOG_CG_SHIFT))&CCM_PLL_CTRL5_TOG_CG_MASK) -/* PLL_CTRL6 Bit Fields */ -#define CCM_PLL_CTRL6_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL6_CG_SHIFT 0 -#define CCM_PLL_CTRL6_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL6_CG_SHIFT))&CCM_PLL_CTRL6_CG_MASK) -/* PLL_CTRL6_SET Bit Fields */ -#define CCM_PLL_CTRL6_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL6_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL6_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL6_SET_CG_SHIFT))&CCM_PLL_CTRL6_SET_CG_MASK) -/* PLL_CTRL6_CLR Bit Fields */ -#define CCM_PLL_CTRL6_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL6_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL6_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL6_CLR_CG_SHIFT))&CCM_PLL_CTRL6_CLR_CG_MASK) -/* PLL_CTRL6_TOG Bit Fields */ -#define CCM_PLL_CTRL6_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL6_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL6_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL6_TOG_CG_SHIFT))&CCM_PLL_CTRL6_TOG_CG_MASK) -/* PLL_CTRL7 Bit Fields */ -#define CCM_PLL_CTRL7_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL7_CG_SHIFT 0 -#define CCM_PLL_CTRL7_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL7_CG_SHIFT))&CCM_PLL_CTRL7_CG_MASK) -/* PLL_CTRL7_SET Bit Fields */ -#define CCM_PLL_CTRL7_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL7_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL7_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL7_SET_CG_SHIFT))&CCM_PLL_CTRL7_SET_CG_MASK) -/* PLL_CTRL7_CLR Bit Fields */ -#define CCM_PLL_CTRL7_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL7_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL7_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL7_CLR_CG_SHIFT))&CCM_PLL_CTRL7_CLR_CG_MASK) -/* PLL_CTRL7_TOG Bit Fields */ -#define CCM_PLL_CTRL7_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL7_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL7_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL7_TOG_CG_SHIFT))&CCM_PLL_CTRL7_TOG_CG_MASK) -/* PLL_CTRL8 Bit Fields */ -#define CCM_PLL_CTRL8_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL8_CG_SHIFT 0 -#define CCM_PLL_CTRL8_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL8_CG_SHIFT))&CCM_PLL_CTRL8_CG_MASK) -/* PLL_CTRL8_SET Bit Fields */ -#define CCM_PLL_CTRL8_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL8_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL8_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL8_SET_CG_SHIFT))&CCM_PLL_CTRL8_SET_CG_MASK) -/* PLL_CTRL8_CLR Bit Fields */ -#define CCM_PLL_CTRL8_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL8_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL8_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL8_CLR_CG_SHIFT))&CCM_PLL_CTRL8_CLR_CG_MASK) -/* PLL_CTRL8_TOG Bit Fields */ -#define CCM_PLL_CTRL8_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL8_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL8_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL8_TOG_CG_SHIFT))&CCM_PLL_CTRL8_TOG_CG_MASK) -/* PLL_CTRL9 Bit Fields */ -#define CCM_PLL_CTRL9_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL9_CG_SHIFT 0 -#define CCM_PLL_CTRL9_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL9_CG_SHIFT))&CCM_PLL_CTRL9_CG_MASK) -/* PLL_CTRL9_SET Bit Fields */ -#define CCM_PLL_CTRL9_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL9_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL9_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL9_SET_CG_SHIFT))&CCM_PLL_CTRL9_SET_CG_MASK) -/* PLL_CTRL9_CLR Bit Fields */ -#define CCM_PLL_CTRL9_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL9_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL9_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL9_CLR_CG_SHIFT))&CCM_PLL_CTRL9_CLR_CG_MASK) -/* PLL_CTRL9_TOG Bit Fields */ -#define CCM_PLL_CTRL9_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL9_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL9_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL9_TOG_CG_SHIFT))&CCM_PLL_CTRL9_TOG_CG_MASK) -/* PLL_CTRL10 Bit Fields */ -#define CCM_PLL_CTRL10_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL10_CG_SHIFT 0 -#define CCM_PLL_CTRL10_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL10_CG_SHIFT))&CCM_PLL_CTRL10_CG_MASK) -/* PLL_CTRL10_SET Bit Fields */ -#define CCM_PLL_CTRL10_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL10_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL10_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL10_SET_CG_SHIFT))&CCM_PLL_CTRL10_SET_CG_MASK) -/* PLL_CTRL10_CLR Bit Fields */ -#define CCM_PLL_CTRL10_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL10_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL10_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL10_CLR_CG_SHIFT))&CCM_PLL_CTRL10_CLR_CG_MASK) -/* PLL_CTRL10_TOG Bit Fields */ -#define CCM_PLL_CTRL10_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL10_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL10_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL10_TOG_CG_SHIFT))&CCM_PLL_CTRL10_TOG_CG_MASK) -/* PLL_CTRL11 Bit Fields */ -#define CCM_PLL_CTRL11_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL11_CG_SHIFT 0 -#define CCM_PLL_CTRL11_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL11_CG_SHIFT))&CCM_PLL_CTRL11_CG_MASK) -/* PLL_CTRL11_SET Bit Fields */ -#define CCM_PLL_CTRL11_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL11_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL11_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL11_SET_CG_SHIFT))&CCM_PLL_CTRL11_SET_CG_MASK) -/* PLL_CTRL11_CLR Bit Fields */ -#define CCM_PLL_CTRL11_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL11_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL11_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL11_CLR_CG_SHIFT))&CCM_PLL_CTRL11_CLR_CG_MASK) -/* PLL_CTRL11_TOG Bit Fields */ -#define CCM_PLL_CTRL11_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL11_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL11_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL11_TOG_CG_SHIFT))&CCM_PLL_CTRL11_TOG_CG_MASK) -/* PLL_CTRL12 Bit Fields */ -#define CCM_PLL_CTRL12_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL12_CG_SHIFT 0 -#define CCM_PLL_CTRL12_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL12_CG_SHIFT))&CCM_PLL_CTRL12_CG_MASK) -/* PLL_CTRL12_SET Bit Fields */ -#define CCM_PLL_CTRL12_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL12_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL12_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL12_SET_CG_SHIFT))&CCM_PLL_CTRL12_SET_CG_MASK) -/* PLL_CTRL12_CLR Bit Fields */ -#define CCM_PLL_CTRL12_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL12_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL12_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL12_CLR_CG_SHIFT))&CCM_PLL_CTRL12_CLR_CG_MASK) -/* PLL_CTRL12_TOG Bit Fields */ -#define CCM_PLL_CTRL12_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL12_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL12_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL12_TOG_CG_SHIFT))&CCM_PLL_CTRL12_TOG_CG_MASK) -/* PLL_CTRL13 Bit Fields */ -#define CCM_PLL_CTRL13_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL13_CG_SHIFT 0 -#define CCM_PLL_CTRL13_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL13_CG_SHIFT))&CCM_PLL_CTRL13_CG_MASK) -/* PLL_CTRL13_SET Bit Fields */ -#define CCM_PLL_CTRL13_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL13_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL13_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL13_SET_CG_SHIFT))&CCM_PLL_CTRL13_SET_CG_MASK) -/* PLL_CTRL13_CLR Bit Fields */ -#define CCM_PLL_CTRL13_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL13_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL13_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL13_CLR_CG_SHIFT))&CCM_PLL_CTRL13_CLR_CG_MASK) -/* PLL_CTRL13_TOG Bit Fields */ -#define CCM_PLL_CTRL13_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL13_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL13_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL13_TOG_CG_SHIFT))&CCM_PLL_CTRL13_TOG_CG_MASK) -/* PLL_CTRL14 Bit Fields */ -#define CCM_PLL_CTRL14_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL14_CG_SHIFT 0 -#define CCM_PLL_CTRL14_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL14_CG_SHIFT))&CCM_PLL_CTRL14_CG_MASK) -/* PLL_CTRL14_SET Bit Fields */ -#define CCM_PLL_CTRL14_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL14_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL14_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL14_SET_CG_SHIFT))&CCM_PLL_CTRL14_SET_CG_MASK) -/* PLL_CTRL14_CLR Bit Fields */ -#define CCM_PLL_CTRL14_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL14_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL14_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL14_CLR_CG_SHIFT))&CCM_PLL_CTRL14_CLR_CG_MASK) -/* PLL_CTRL14_TOG Bit Fields */ -#define CCM_PLL_CTRL14_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL14_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL14_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL14_TOG_CG_SHIFT))&CCM_PLL_CTRL14_TOG_CG_MASK) -/* PLL_CTRL15 Bit Fields */ -#define CCM_PLL_CTRL15_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL15_CG_SHIFT 0 -#define CCM_PLL_CTRL15_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL15_CG_SHIFT))&CCM_PLL_CTRL15_CG_MASK) -/* PLL_CTRL15_SET Bit Fields */ -#define CCM_PLL_CTRL15_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL15_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL15_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL15_SET_CG_SHIFT))&CCM_PLL_CTRL15_SET_CG_MASK) -/* PLL_CTRL15_CLR Bit Fields */ -#define CCM_PLL_CTRL15_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL15_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL15_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL15_CLR_CG_SHIFT))&CCM_PLL_CTRL15_CLR_CG_MASK) -/* PLL_CTRL15_TOG Bit Fields */ -#define CCM_PLL_CTRL15_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL15_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL15_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL15_TOG_CG_SHIFT))&CCM_PLL_CTRL15_TOG_CG_MASK) -/* PLL_CTRL16 Bit Fields */ -#define CCM_PLL_CTRL16_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL16_CG_SHIFT 0 -#define CCM_PLL_CTRL16_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL16_CG_SHIFT))&CCM_PLL_CTRL16_CG_MASK) -/* PLL_CTRL16_SET Bit Fields */ -#define CCM_PLL_CTRL16_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL16_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL16_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL16_SET_CG_SHIFT))&CCM_PLL_CTRL16_SET_CG_MASK) -/* PLL_CTRL16_CLR Bit Fields */ -#define CCM_PLL_CTRL16_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL16_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL16_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL16_CLR_CG_SHIFT))&CCM_PLL_CTRL16_CLR_CG_MASK) -/* PLL_CTRL16_TOG Bit Fields */ -#define CCM_PLL_CTRL16_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL16_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL16_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL16_TOG_CG_SHIFT))&CCM_PLL_CTRL16_TOG_CG_MASK) -/* PLL_CTRL17 Bit Fields */ -#define CCM_PLL_CTRL17_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL17_CG_SHIFT 0 -#define CCM_PLL_CTRL17_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL17_CG_SHIFT))&CCM_PLL_CTRL17_CG_MASK) -/* PLL_CTRL17_SET Bit Fields */ -#define CCM_PLL_CTRL17_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL17_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL17_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL17_SET_CG_SHIFT))&CCM_PLL_CTRL17_SET_CG_MASK) -/* PLL_CTRL17_CLR Bit Fields */ -#define CCM_PLL_CTRL17_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL17_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL17_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL17_CLR_CG_SHIFT))&CCM_PLL_CTRL17_CLR_CG_MASK) -/* PLL_CTRL17_TOG Bit Fields */ -#define CCM_PLL_CTRL17_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL17_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL17_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL17_TOG_CG_SHIFT))&CCM_PLL_CTRL17_TOG_CG_MASK) -/* PLL_CTRL18 Bit Fields */ -#define CCM_PLL_CTRL18_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL18_CG_SHIFT 0 -#define CCM_PLL_CTRL18_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL18_CG_SHIFT))&CCM_PLL_CTRL18_CG_MASK) -/* PLL_CTRL18_SET Bit Fields */ -#define CCM_PLL_CTRL18_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL18_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL18_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL18_SET_CG_SHIFT))&CCM_PLL_CTRL18_SET_CG_MASK) -/* PLL_CTRL18_CLR Bit Fields */ -#define CCM_PLL_CTRL18_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL18_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL18_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL18_CLR_CG_SHIFT))&CCM_PLL_CTRL18_CLR_CG_MASK) -/* PLL_CTRL18_TOG Bit Fields */ -#define CCM_PLL_CTRL18_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL18_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL18_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL18_TOG_CG_SHIFT))&CCM_PLL_CTRL18_TOG_CG_MASK) -/* PLL_CTRL19 Bit Fields */ -#define CCM_PLL_CTRL19_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL19_CG_SHIFT 0 -#define CCM_PLL_CTRL19_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL19_CG_SHIFT))&CCM_PLL_CTRL19_CG_MASK) -/* PLL_CTRL19_SET Bit Fields */ -#define CCM_PLL_CTRL19_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL19_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL19_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL19_SET_CG_SHIFT))&CCM_PLL_CTRL19_SET_CG_MASK) -/* PLL_CTRL19_CLR Bit Fields */ -#define CCM_PLL_CTRL19_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL19_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL19_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL19_CLR_CG_SHIFT))&CCM_PLL_CTRL19_CLR_CG_MASK) -/* PLL_CTRL19_TOG Bit Fields */ -#define CCM_PLL_CTRL19_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL19_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL19_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL19_TOG_CG_SHIFT))&CCM_PLL_CTRL19_TOG_CG_MASK) -/* PLL_CTRL20 Bit Fields */ -#define CCM_PLL_CTRL20_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL20_CG_SHIFT 0 -#define CCM_PLL_CTRL20_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL20_CG_SHIFT))&CCM_PLL_CTRL20_CG_MASK) -/* PLL_CTRL20_SET Bit Fields */ -#define CCM_PLL_CTRL20_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL20_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL20_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL20_SET_CG_SHIFT))&CCM_PLL_CTRL20_SET_CG_MASK) -/* PLL_CTRL20_CLR Bit Fields */ -#define CCM_PLL_CTRL20_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL20_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL20_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL20_CLR_CG_SHIFT))&CCM_PLL_CTRL20_CLR_CG_MASK) -/* PLL_CTRL20_TOG Bit Fields */ -#define CCM_PLL_CTRL20_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL20_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL20_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL20_TOG_CG_SHIFT))&CCM_PLL_CTRL20_TOG_CG_MASK) -/* PLL_CTRL21 Bit Fields */ -#define CCM_PLL_CTRL21_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL21_CG_SHIFT 0 -#define CCM_PLL_CTRL21_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL21_CG_SHIFT))&CCM_PLL_CTRL21_CG_MASK) -/* PLL_CTRL21_SET Bit Fields */ -#define CCM_PLL_CTRL21_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL21_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL21_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL21_SET_CG_SHIFT))&CCM_PLL_CTRL21_SET_CG_MASK) -/* PLL_CTRL21_CLR Bit Fields */ -#define CCM_PLL_CTRL21_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL21_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL21_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL21_CLR_CG_SHIFT))&CCM_PLL_CTRL21_CLR_CG_MASK) -/* PLL_CTRL21_TOG Bit Fields */ -#define CCM_PLL_CTRL21_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL21_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL21_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL21_TOG_CG_SHIFT))&CCM_PLL_CTRL21_TOG_CG_MASK) -/* PLL_CTRL22 Bit Fields */ -#define CCM_PLL_CTRL22_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL22_CG_SHIFT 0 -#define CCM_PLL_CTRL22_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL22_CG_SHIFT))&CCM_PLL_CTRL22_CG_MASK) -/* PLL_CTRL22_SET Bit Fields */ -#define CCM_PLL_CTRL22_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL22_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL22_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL22_SET_CG_SHIFT))&CCM_PLL_CTRL22_SET_CG_MASK) -/* PLL_CTRL22_CLR Bit Fields */ -#define CCM_PLL_CTRL22_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL22_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL22_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL22_CLR_CG_SHIFT))&CCM_PLL_CTRL22_CLR_CG_MASK) -/* PLL_CTRL22_TOG Bit Fields */ -#define CCM_PLL_CTRL22_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL22_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL22_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL22_TOG_CG_SHIFT))&CCM_PLL_CTRL22_TOG_CG_MASK) -/* PLL_CTRL23 Bit Fields */ -#define CCM_PLL_CTRL23_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL23_CG_SHIFT 0 -#define CCM_PLL_CTRL23_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL23_CG_SHIFT))&CCM_PLL_CTRL23_CG_MASK) -/* PLL_CTRL23_SET Bit Fields */ -#define CCM_PLL_CTRL23_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL23_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL23_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL23_SET_CG_SHIFT))&CCM_PLL_CTRL23_SET_CG_MASK) -/* PLL_CTRL23_CLR Bit Fields */ -#define CCM_PLL_CTRL23_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL23_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL23_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL23_CLR_CG_SHIFT))&CCM_PLL_CTRL23_CLR_CG_MASK) -/* PLL_CTRL23_TOG Bit Fields */ -#define CCM_PLL_CTRL23_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL23_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL23_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL23_TOG_CG_SHIFT))&CCM_PLL_CTRL23_TOG_CG_MASK) -/* PLL_CTRL24 Bit Fields */ -#define CCM_PLL_CTRL24_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL24_CG_SHIFT 0 -#define CCM_PLL_CTRL24_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL24_CG_SHIFT))&CCM_PLL_CTRL24_CG_MASK) -/* PLL_CTRL24_SET Bit Fields */ -#define CCM_PLL_CTRL24_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL24_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL24_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL24_SET_CG_SHIFT))&CCM_PLL_CTRL24_SET_CG_MASK) -/* PLL_CTRL24_CLR Bit Fields */ -#define CCM_PLL_CTRL24_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL24_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL24_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL24_CLR_CG_SHIFT))&CCM_PLL_CTRL24_CLR_CG_MASK) -/* PLL_CTRL24_TOG Bit Fields */ -#define CCM_PLL_CTRL24_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL24_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL24_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL24_TOG_CG_SHIFT))&CCM_PLL_CTRL24_TOG_CG_MASK) -/* PLL_CTRL25 Bit Fields */ -#define CCM_PLL_CTRL25_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL25_CG_SHIFT 0 -#define CCM_PLL_CTRL25_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL25_CG_SHIFT))&CCM_PLL_CTRL25_CG_MASK) -/* PLL_CTRL25_SET Bit Fields */ -#define CCM_PLL_CTRL25_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL25_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL25_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL25_SET_CG_SHIFT))&CCM_PLL_CTRL25_SET_CG_MASK) -/* PLL_CTRL25_CLR Bit Fields */ -#define CCM_PLL_CTRL25_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL25_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL25_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL25_CLR_CG_SHIFT))&CCM_PLL_CTRL25_CLR_CG_MASK) -/* PLL_CTRL25_TOG Bit Fields */ -#define CCM_PLL_CTRL25_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL25_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL25_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL25_TOG_CG_SHIFT))&CCM_PLL_CTRL25_TOG_CG_MASK) -/* PLL_CTRL26 Bit Fields */ -#define CCM_PLL_CTRL26_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL26_CG_SHIFT 0 -#define CCM_PLL_CTRL26_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL26_CG_SHIFT))&CCM_PLL_CTRL26_CG_MASK) -/* PLL_CTRL26_SET Bit Fields */ -#define CCM_PLL_CTRL26_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL26_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL26_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL26_SET_CG_SHIFT))&CCM_PLL_CTRL26_SET_CG_MASK) -/* PLL_CTRL26_CLR Bit Fields */ -#define CCM_PLL_CTRL26_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL26_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL26_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL26_CLR_CG_SHIFT))&CCM_PLL_CTRL26_CLR_CG_MASK) -/* PLL_CTRL26_TOG Bit Fields */ -#define CCM_PLL_CTRL26_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL26_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL26_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL26_TOG_CG_SHIFT))&CCM_PLL_CTRL26_TOG_CG_MASK) -/* PLL_CTRL27 Bit Fields */ -#define CCM_PLL_CTRL27_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL27_CG_SHIFT 0 -#define CCM_PLL_CTRL27_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL27_CG_SHIFT))&CCM_PLL_CTRL27_CG_MASK) -/* PLL_CTRL27_SET Bit Fields */ -#define CCM_PLL_CTRL27_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL27_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL27_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL27_SET_CG_SHIFT))&CCM_PLL_CTRL27_SET_CG_MASK) -/* PLL_CTRL27_CLR Bit Fields */ -#define CCM_PLL_CTRL27_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL27_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL27_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL27_CLR_CG_SHIFT))&CCM_PLL_CTRL27_CLR_CG_MASK) -/* PLL_CTRL27_TOG Bit Fields */ -#define CCM_PLL_CTRL27_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL27_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL27_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL27_TOG_CG_SHIFT))&CCM_PLL_CTRL27_TOG_CG_MASK) -/* PLL_CTRL28 Bit Fields */ -#define CCM_PLL_CTRL28_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL28_CG_SHIFT 0 -#define CCM_PLL_CTRL28_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL28_CG_SHIFT))&CCM_PLL_CTRL28_CG_MASK) -/* PLL_CTRL28_SET Bit Fields */ -#define CCM_PLL_CTRL28_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL28_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL28_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL28_SET_CG_SHIFT))&CCM_PLL_CTRL28_SET_CG_MASK) -/* PLL_CTRL28_CLR Bit Fields */ -#define CCM_PLL_CTRL28_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL28_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL28_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL28_CLR_CG_SHIFT))&CCM_PLL_CTRL28_CLR_CG_MASK) -/* PLL_CTRL28_TOG Bit Fields */ -#define CCM_PLL_CTRL28_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL28_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL28_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL28_TOG_CG_SHIFT))&CCM_PLL_CTRL28_TOG_CG_MASK) -/* PLL_CTRL29 Bit Fields */ -#define CCM_PLL_CTRL29_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL29_CG_SHIFT 0 -#define CCM_PLL_CTRL29_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL29_CG_SHIFT))&CCM_PLL_CTRL29_CG_MASK) -/* PLL_CTRL29_SET Bit Fields */ -#define CCM_PLL_CTRL29_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL29_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL29_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL29_SET_CG_SHIFT))&CCM_PLL_CTRL29_SET_CG_MASK) -/* PLL_CTRL29_CLR Bit Fields */ -#define CCM_PLL_CTRL29_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL29_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL29_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL29_CLR_CG_SHIFT))&CCM_PLL_CTRL29_CLR_CG_MASK) -/* PLL_CTRL29_TOG Bit Fields */ -#define CCM_PLL_CTRL29_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL29_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL29_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL29_TOG_CG_SHIFT))&CCM_PLL_CTRL29_TOG_CG_MASK) -/* PLL_CTRL30 Bit Fields */ -#define CCM_PLL_CTRL30_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL30_CG_SHIFT 0 -#define CCM_PLL_CTRL30_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL30_CG_SHIFT))&CCM_PLL_CTRL30_CG_MASK) -/* PLL_CTRL30_SET Bit Fields */ -#define CCM_PLL_CTRL30_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL30_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL30_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL30_SET_CG_SHIFT))&CCM_PLL_CTRL30_SET_CG_MASK) -/* PLL_CTRL30_CLR Bit Fields */ -#define CCM_PLL_CTRL30_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL30_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL30_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL30_CLR_CG_SHIFT))&CCM_PLL_CTRL30_CLR_CG_MASK) -/* PLL_CTRL30_TOG Bit Fields */ -#define CCM_PLL_CTRL30_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL30_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL30_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL30_TOG_CG_SHIFT))&CCM_PLL_CTRL30_TOG_CG_MASK) -/* PLL_CTRL31 Bit Fields */ -#define CCM_PLL_CTRL31_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL31_CG_SHIFT 0 -#define CCM_PLL_CTRL31_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL31_CG_SHIFT))&CCM_PLL_CTRL31_CG_MASK) -/* PLL_CTRL31_SET Bit Fields */ -#define CCM_PLL_CTRL31_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL31_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL31_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL31_SET_CG_SHIFT))&CCM_PLL_CTRL31_SET_CG_MASK) -/* PLL_CTRL31_CLR Bit Fields */ -#define CCM_PLL_CTRL31_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL31_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL31_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL31_CLR_CG_SHIFT))&CCM_PLL_CTRL31_CLR_CG_MASK) -/* PLL_CTRL31_TOG Bit Fields */ -#define CCM_PLL_CTRL31_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL31_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL31_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL31_TOG_CG_SHIFT))&CCM_PLL_CTRL31_TOG_CG_MASK) -/* PLL_CTRL32 Bit Fields */ -#define CCM_PLL_CTRL32_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL32_CG_SHIFT 0 -#define CCM_PLL_CTRL32_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL32_CG_SHIFT))&CCM_PLL_CTRL32_CG_MASK) -/* PLL_CTRL32_SET Bit Fields */ -#define CCM_PLL_CTRL32_SET_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL32_SET_CG_SHIFT 0 -#define CCM_PLL_CTRL32_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL32_SET_CG_SHIFT))&CCM_PLL_CTRL32_SET_CG_MASK) -/* PLL_CTRL32_CLR Bit Fields */ -#define CCM_PLL_CTRL32_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL32_CLR_CG_SHIFT 0 -#define CCM_PLL_CTRL32_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL32_CLR_CG_SHIFT))&CCM_PLL_CTRL32_CLR_CG_MASK) -/* PLL_CTRL32_TOG Bit Fields */ -#define CCM_PLL_CTRL32_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_PLL_CTRL32_TOG_CG_SHIFT 0 -#define CCM_PLL_CTRL32_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL32_TOG_CG_SHIFT))&CCM_PLL_CTRL32_TOG_CG_MASK) -/* CCGR0 Bit Fields */ -#define CCM_CCGR0_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR0_CG_SHIFT 0 -#define CCM_CCGR0_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG_SHIFT))&CCM_CCGR0_CG_MASK) -/* CCGR0_SET Bit Fields */ -#define CCM_CCGR0_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR0_SET_CG_SHIFT 0 -#define CCM_CCGR0_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_SET_CG_SHIFT))&CCM_CCGR0_SET_CG_MASK) -/* CCGR0_CLR Bit Fields */ -#define CCM_CCGR0_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR0_CLR_CG_SHIFT 0 -#define CCM_CCGR0_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CLR_CG_SHIFT))&CCM_CCGR0_CLR_CG_MASK) -/* CCGR0_TOG Bit Fields */ -#define CCM_CCGR0_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR0_TOG_CG_SHIFT 0 -#define CCM_CCGR0_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_TOG_CG_SHIFT))&CCM_CCGR0_TOG_CG_MASK) -/* CCGR1 Bit Fields */ -#define CCM_CCGR1_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR1_CG_SHIFT 0 -#define CCM_CCGR1_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG_SHIFT))&CCM_CCGR1_CG_MASK) -/* CCGR1_SET Bit Fields */ -#define CCM_CCGR1_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR1_SET_CG_SHIFT 0 -#define CCM_CCGR1_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_SET_CG_SHIFT))&CCM_CCGR1_SET_CG_MASK) -/* CCGR1_CLR Bit Fields */ -#define CCM_CCGR1_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR1_CLR_CG_SHIFT 0 -#define CCM_CCGR1_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CLR_CG_SHIFT))&CCM_CCGR1_CLR_CG_MASK) -/* CCGR1_TOG Bit Fields */ -#define CCM_CCGR1_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR1_TOG_CG_SHIFT 0 -#define CCM_CCGR1_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_TOG_CG_SHIFT))&CCM_CCGR1_TOG_CG_MASK) -/* CCGR2 Bit Fields */ -#define CCM_CCGR2_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR2_CG_SHIFT 0 -#define CCM_CCGR2_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG_SHIFT))&CCM_CCGR2_CG_MASK) -/* CCGR2_SET Bit Fields */ -#define CCM_CCGR2_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR2_SET_CG_SHIFT 0 -#define CCM_CCGR2_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_SET_CG_SHIFT))&CCM_CCGR2_SET_CG_MASK) -/* CCGR2_CLR Bit Fields */ -#define CCM_CCGR2_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR2_CLR_CG_SHIFT 0 -#define CCM_CCGR2_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CLR_CG_SHIFT))&CCM_CCGR2_CLR_CG_MASK) -/* CCGR2_TOG Bit Fields */ -#define CCM_CCGR2_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR2_TOG_CG_SHIFT 0 -#define CCM_CCGR2_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_TOG_CG_SHIFT))&CCM_CCGR2_TOG_CG_MASK) -/* CCGR3 Bit Fields */ -#define CCM_CCGR3_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR3_CG_SHIFT 0 -#define CCM_CCGR3_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG_SHIFT))&CCM_CCGR3_CG_MASK) -/* CCGR3_SET Bit Fields */ -#define CCM_CCGR3_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR3_SET_CG_SHIFT 0 -#define CCM_CCGR3_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_SET_CG_SHIFT))&CCM_CCGR3_SET_CG_MASK) -/* CCGR3_CLR Bit Fields */ -#define CCM_CCGR3_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR3_CLR_CG_SHIFT 0 -#define CCM_CCGR3_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CLR_CG_SHIFT))&CCM_CCGR3_CLR_CG_MASK) -/* CCGR3_TOG Bit Fields */ -#define CCM_CCGR3_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR3_TOG_CG_SHIFT 0 -#define CCM_CCGR3_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_TOG_CG_SHIFT))&CCM_CCGR3_TOG_CG_MASK) -/* CCGR4 Bit Fields */ -#define CCM_CCGR4_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR4_CG_SHIFT 0 -#define CCM_CCGR4_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG_SHIFT))&CCM_CCGR4_CG_MASK) -/* CCGR4_SET Bit Fields */ -#define CCM_CCGR4_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR4_SET_CG_SHIFT 0 -#define CCM_CCGR4_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_SET_CG_SHIFT))&CCM_CCGR4_SET_CG_MASK) -/* CCGR4_CLR Bit Fields */ -#define CCM_CCGR4_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR4_CLR_CG_SHIFT 0 -#define CCM_CCGR4_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CLR_CG_SHIFT))&CCM_CCGR4_CLR_CG_MASK) -/* CCGR4_TOG Bit Fields */ -#define CCM_CCGR4_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR4_TOG_CG_SHIFT 0 -#define CCM_CCGR4_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_TOG_CG_SHIFT))&CCM_CCGR4_TOG_CG_MASK) -/* CCGR5 Bit Fields */ -#define CCM_CCGR5_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR5_CG_SHIFT 0 -#define CCM_CCGR5_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG_SHIFT))&CCM_CCGR5_CG_MASK) -/* CCGR5_SET Bit Fields */ -#define CCM_CCGR5_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR5_SET_CG_SHIFT 0 -#define CCM_CCGR5_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_SET_CG_SHIFT))&CCM_CCGR5_SET_CG_MASK) -/* CCGR5_CLR Bit Fields */ -#define CCM_CCGR5_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR5_CLR_CG_SHIFT 0 -#define CCM_CCGR5_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CLR_CG_SHIFT))&CCM_CCGR5_CLR_CG_MASK) -/* CCGR5_TOG Bit Fields */ -#define CCM_CCGR5_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR5_TOG_CG_SHIFT 0 -#define CCM_CCGR5_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_TOG_CG_SHIFT))&CCM_CCGR5_TOG_CG_MASK) -/* CCGR6 Bit Fields */ -#define CCM_CCGR6_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR6_CG_SHIFT 0 -#define CCM_CCGR6_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG_SHIFT))&CCM_CCGR6_CG_MASK) -/* CCGR6_SET Bit Fields */ -#define CCM_CCGR6_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR6_SET_CG_SHIFT 0 -#define CCM_CCGR6_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_SET_CG_SHIFT))&CCM_CCGR6_SET_CG_MASK) -/* CCGR6_CLR Bit Fields */ -#define CCM_CCGR6_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR6_CLR_CG_SHIFT 0 -#define CCM_CCGR6_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CLR_CG_SHIFT))&CCM_CCGR6_CLR_CG_MASK) -/* CCGR6_TOG Bit Fields */ -#define CCM_CCGR6_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR6_TOG_CG_SHIFT 0 -#define CCM_CCGR6_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_TOG_CG_SHIFT))&CCM_CCGR6_TOG_CG_MASK) -/* CCGR7 Bit Fields */ -#define CCM_CCGR7_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR7_CG_SHIFT 0 -#define CCM_CCGR7_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG_SHIFT))&CCM_CCGR7_CG_MASK) -/* CCGR7_SET Bit Fields */ -#define CCM_CCGR7_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR7_SET_CG_SHIFT 0 -#define CCM_CCGR7_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_SET_CG_SHIFT))&CCM_CCGR7_SET_CG_MASK) -/* CCGR7_CLR Bit Fields */ -#define CCM_CCGR7_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR7_CLR_CG_SHIFT 0 -#define CCM_CCGR7_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CLR_CG_SHIFT))&CCM_CCGR7_CLR_CG_MASK) -/* CCGR7_TOG Bit Fields */ -#define CCM_CCGR7_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR7_TOG_CG_SHIFT 0 -#define CCM_CCGR7_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_TOG_CG_SHIFT))&CCM_CCGR7_TOG_CG_MASK) -/* CCGR8 Bit Fields */ -#define CCM_CCGR8_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR8_CG_SHIFT 0 -#define CCM_CCGR8_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG_SHIFT))&CCM_CCGR8_CG_MASK) -/* CCGR8_SET Bit Fields */ -#define CCM_CCGR8_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR8_SET_CG_SHIFT 0 -#define CCM_CCGR8_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_SET_CG_SHIFT))&CCM_CCGR8_SET_CG_MASK) -/* CCGR8_CLR Bit Fields */ -#define CCM_CCGR8_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR8_CLR_CG_SHIFT 0 -#define CCM_CCGR8_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CLR_CG_SHIFT))&CCM_CCGR8_CLR_CG_MASK) -/* CCGR8_TOG Bit Fields */ -#define CCM_CCGR8_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR8_TOG_CG_SHIFT 0 -#define CCM_CCGR8_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_TOG_CG_SHIFT))&CCM_CCGR8_TOG_CG_MASK) -/* CCGR9 Bit Fields */ -#define CCM_CCGR9_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR9_CG_SHIFT 0 -#define CCM_CCGR9_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG_SHIFT))&CCM_CCGR9_CG_MASK) -/* CCGR9_SET Bit Fields */ -#define CCM_CCGR9_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR9_SET_CG_SHIFT 0 -#define CCM_CCGR9_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_SET_CG_SHIFT))&CCM_CCGR9_SET_CG_MASK) -/* CCGR9_CLR Bit Fields */ -#define CCM_CCGR9_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR9_CLR_CG_SHIFT 0 -#define CCM_CCGR9_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CLR_CG_SHIFT))&CCM_CCGR9_CLR_CG_MASK) -/* CCGR9_TOG Bit Fields */ -#define CCM_CCGR9_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR9_TOG_CG_SHIFT 0 -#define CCM_CCGR9_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_TOG_CG_SHIFT))&CCM_CCGR9_TOG_CG_MASK) -/* CCGR10 Bit Fields */ -#define CCM_CCGR10_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR10_CG_SHIFT 0 -#define CCM_CCGR10_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG_SHIFT))&CCM_CCGR10_CG_MASK) -/* CCGR10_SET Bit Fields */ -#define CCM_CCGR10_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR10_SET_CG_SHIFT 0 -#define CCM_CCGR10_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_SET_CG_SHIFT))&CCM_CCGR10_SET_CG_MASK) -/* CCGR10_CLR Bit Fields */ -#define CCM_CCGR10_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR10_CLR_CG_SHIFT 0 -#define CCM_CCGR10_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CLR_CG_SHIFT))&CCM_CCGR10_CLR_CG_MASK) -/* CCGR10_TOG Bit Fields */ -#define CCM_CCGR10_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR10_TOG_CG_SHIFT 0 -#define CCM_CCGR10_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_TOG_CG_SHIFT))&CCM_CCGR10_TOG_CG_MASK) -/* CCGR11 Bit Fields */ -#define CCM_CCGR11_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR11_CG_SHIFT 0 -#define CCM_CCGR11_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG_SHIFT))&CCM_CCGR11_CG_MASK) -/* CCGR11_SET Bit Fields */ -#define CCM_CCGR11_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR11_SET_CG_SHIFT 0 -#define CCM_CCGR11_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_SET_CG_SHIFT))&CCM_CCGR11_SET_CG_MASK) -/* CCGR11_CLR Bit Fields */ -#define CCM_CCGR11_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR11_CLR_CG_SHIFT 0 -#define CCM_CCGR11_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CLR_CG_SHIFT))&CCM_CCGR11_CLR_CG_MASK) -/* CCGR11_TOG Bit Fields */ -#define CCM_CCGR11_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR11_TOG_CG_SHIFT 0 -#define CCM_CCGR11_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_TOG_CG_SHIFT))&CCM_CCGR11_TOG_CG_MASK) -/* CCGR12 Bit Fields */ -#define CCM_CCGR12_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR12_CG_SHIFT 0 -#define CCM_CCGR12_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR12_CG_SHIFT))&CCM_CCGR12_CG_MASK) -/* CCGR12_SET Bit Fields */ -#define CCM_CCGR12_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR12_SET_CG_SHIFT 0 -#define CCM_CCGR12_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR12_SET_CG_SHIFT))&CCM_CCGR12_SET_CG_MASK) -/* CCGR12_CLR Bit Fields */ -#define CCM_CCGR12_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR12_CLR_CG_SHIFT 0 -#define CCM_CCGR12_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR12_CLR_CG_SHIFT))&CCM_CCGR12_CLR_CG_MASK) -/* CCGR12_TOG Bit Fields */ -#define CCM_CCGR12_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR12_TOG_CG_SHIFT 0 -#define CCM_CCGR12_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR12_TOG_CG_SHIFT))&CCM_CCGR12_TOG_CG_MASK) -/* CCGR13 Bit Fields */ -#define CCM_CCGR13_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR13_CG_SHIFT 0 -#define CCM_CCGR13_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR13_CG_SHIFT))&CCM_CCGR13_CG_MASK) -/* CCGR13_SET Bit Fields */ -#define CCM_CCGR13_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR13_SET_CG_SHIFT 0 -#define CCM_CCGR13_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR13_SET_CG_SHIFT))&CCM_CCGR13_SET_CG_MASK) -/* CCGR13_CLR Bit Fields */ -#define CCM_CCGR13_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR13_CLR_CG_SHIFT 0 -#define CCM_CCGR13_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR13_CLR_CG_SHIFT))&CCM_CCGR13_CLR_CG_MASK) -/* CCGR13_TOG Bit Fields */ -#define CCM_CCGR13_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR13_TOG_CG_SHIFT 0 -#define CCM_CCGR13_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR13_TOG_CG_SHIFT))&CCM_CCGR13_TOG_CG_MASK) -/* CCGR14 Bit Fields */ -#define CCM_CCGR14_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR14_CG_SHIFT 0 -#define CCM_CCGR14_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR14_CG_SHIFT))&CCM_CCGR14_CG_MASK) -/* CCGR14_SET Bit Fields */ -#define CCM_CCGR14_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR14_SET_CG_SHIFT 0 -#define CCM_CCGR14_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR14_SET_CG_SHIFT))&CCM_CCGR14_SET_CG_MASK) -/* CCGR14_CLR Bit Fields */ -#define CCM_CCGR14_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR14_CLR_CG_SHIFT 0 -#define CCM_CCGR14_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR14_CLR_CG_SHIFT))&CCM_CCGR14_CLR_CG_MASK) -/* CCGR14_TOG Bit Fields */ -#define CCM_CCGR14_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR14_TOG_CG_SHIFT 0 -#define CCM_CCGR14_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR14_TOG_CG_SHIFT))&CCM_CCGR14_TOG_CG_MASK) -/* CCGR15 Bit Fields */ -#define CCM_CCGR15_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR15_CG_SHIFT 0 -#define CCM_CCGR15_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR15_CG_SHIFT))&CCM_CCGR15_CG_MASK) -/* CCGR15_SET Bit Fields */ -#define CCM_CCGR15_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR15_SET_CG_SHIFT 0 -#define CCM_CCGR15_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR15_SET_CG_SHIFT))&CCM_CCGR15_SET_CG_MASK) -/* CCGR15_CLR Bit Fields */ -#define CCM_CCGR15_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR15_CLR_CG_SHIFT 0 -#define CCM_CCGR15_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR15_CLR_CG_SHIFT))&CCM_CCGR15_CLR_CG_MASK) -/* CCGR15_TOG Bit Fields */ -#define CCM_CCGR15_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR15_TOG_CG_SHIFT 0 -#define CCM_CCGR15_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR15_TOG_CG_SHIFT))&CCM_CCGR15_TOG_CG_MASK) -/* CCGR16 Bit Fields */ -#define CCM_CCGR16_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR16_CG_SHIFT 0 -#define CCM_CCGR16_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR16_CG_SHIFT))&CCM_CCGR16_CG_MASK) -/* CCGR16_SET Bit Fields */ -#define CCM_CCGR16_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR16_SET_CG_SHIFT 0 -#define CCM_CCGR16_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR16_SET_CG_SHIFT))&CCM_CCGR16_SET_CG_MASK) -/* CCGR16_CLR Bit Fields */ -#define CCM_CCGR16_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR16_CLR_CG_SHIFT 0 -#define CCM_CCGR16_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR16_CLR_CG_SHIFT))&CCM_CCGR16_CLR_CG_MASK) -/* CCGR16_TOG Bit Fields */ -#define CCM_CCGR16_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR16_TOG_CG_SHIFT 0 -#define CCM_CCGR16_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR16_TOG_CG_SHIFT))&CCM_CCGR16_TOG_CG_MASK) -/* CCGR17 Bit Fields */ -#define CCM_CCGR17_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR17_CG_SHIFT 0 -#define CCM_CCGR17_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR17_CG_SHIFT))&CCM_CCGR17_CG_MASK) -/* CCGR17_SET Bit Fields */ -#define CCM_CCGR17_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR17_SET_CG_SHIFT 0 -#define CCM_CCGR17_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR17_SET_CG_SHIFT))&CCM_CCGR17_SET_CG_MASK) -/* CCGR17_CLR Bit Fields */ -#define CCM_CCGR17_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR17_CLR_CG_SHIFT 0 -#define CCM_CCGR17_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR17_CLR_CG_SHIFT))&CCM_CCGR17_CLR_CG_MASK) -/* CCGR17_TOG Bit Fields */ -#define CCM_CCGR17_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR17_TOG_CG_SHIFT 0 -#define CCM_CCGR17_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR17_TOG_CG_SHIFT))&CCM_CCGR17_TOG_CG_MASK) -/* CCGR18 Bit Fields */ -#define CCM_CCGR18_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR18_CG_SHIFT 0 -#define CCM_CCGR18_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR18_CG_SHIFT))&CCM_CCGR18_CG_MASK) -/* CCGR18_SET Bit Fields */ -#define CCM_CCGR18_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR18_SET_CG_SHIFT 0 -#define CCM_CCGR18_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR18_SET_CG_SHIFT))&CCM_CCGR18_SET_CG_MASK) -/* CCGR18_CLR Bit Fields */ -#define CCM_CCGR18_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR18_CLR_CG_SHIFT 0 -#define CCM_CCGR18_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR18_CLR_CG_SHIFT))&CCM_CCGR18_CLR_CG_MASK) -/* CCGR18_TOG Bit Fields */ -#define CCM_CCGR18_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR18_TOG_CG_SHIFT 0 -#define CCM_CCGR18_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR18_TOG_CG_SHIFT))&CCM_CCGR18_TOG_CG_MASK) -/* CCGR19 Bit Fields */ -#define CCM_CCGR19_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR19_CG_SHIFT 0 -#define CCM_CCGR19_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR19_CG_SHIFT))&CCM_CCGR19_CG_MASK) -/* CCGR19_SET Bit Fields */ -#define CCM_CCGR19_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR19_SET_CG_SHIFT 0 -#define CCM_CCGR19_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR19_SET_CG_SHIFT))&CCM_CCGR19_SET_CG_MASK) -/* CCGR19_CLR Bit Fields */ -#define CCM_CCGR19_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR19_CLR_CG_SHIFT 0 -#define CCM_CCGR19_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR19_CLR_CG_SHIFT))&CCM_CCGR19_CLR_CG_MASK) -/* CCGR19_TOG Bit Fields */ -#define CCM_CCGR19_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR19_TOG_CG_SHIFT 0 -#define CCM_CCGR19_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR19_TOG_CG_SHIFT))&CCM_CCGR19_TOG_CG_MASK) -/* CCGR20 Bit Fields */ -#define CCM_CCGR20_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR20_CG_SHIFT 0 -#define CCM_CCGR20_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR20_CG_SHIFT))&CCM_CCGR20_CG_MASK) -/* CCGR20_SET Bit Fields */ -#define CCM_CCGR20_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR20_SET_CG_SHIFT 0 -#define CCM_CCGR20_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR20_SET_CG_SHIFT))&CCM_CCGR20_SET_CG_MASK) -/* CCGR20_CLR Bit Fields */ -#define CCM_CCGR20_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR20_CLR_CG_SHIFT 0 -#define CCM_CCGR20_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR20_CLR_CG_SHIFT))&CCM_CCGR20_CLR_CG_MASK) -/* CCGR20_TOG Bit Fields */ -#define CCM_CCGR20_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR20_TOG_CG_SHIFT 0 -#define CCM_CCGR20_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR20_TOG_CG_SHIFT))&CCM_CCGR20_TOG_CG_MASK) -/* CCGR21 Bit Fields */ -#define CCM_CCGR21_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR21_CG_SHIFT 0 -#define CCM_CCGR21_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR21_CG_SHIFT))&CCM_CCGR21_CG_MASK) -/* CCGR21_SET Bit Fields */ -#define CCM_CCGR21_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR21_SET_CG_SHIFT 0 -#define CCM_CCGR21_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR21_SET_CG_SHIFT))&CCM_CCGR21_SET_CG_MASK) -/* CCGR21_CLR Bit Fields */ -#define CCM_CCGR21_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR21_CLR_CG_SHIFT 0 -#define CCM_CCGR21_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR21_CLR_CG_SHIFT))&CCM_CCGR21_CLR_CG_MASK) -/* CCGR21_TOG Bit Fields */ -#define CCM_CCGR21_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR21_TOG_CG_SHIFT 0 -#define CCM_CCGR21_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR21_TOG_CG_SHIFT))&CCM_CCGR21_TOG_CG_MASK) -/* CCGR22 Bit Fields */ -#define CCM_CCGR22_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR22_CG_SHIFT 0 -#define CCM_CCGR22_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR22_CG_SHIFT))&CCM_CCGR22_CG_MASK) -/* CCGR22_SET Bit Fields */ -#define CCM_CCGR22_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR22_SET_CG_SHIFT 0 -#define CCM_CCGR22_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR22_SET_CG_SHIFT))&CCM_CCGR22_SET_CG_MASK) -/* CCGR22_CLR Bit Fields */ -#define CCM_CCGR22_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR22_CLR_CG_SHIFT 0 -#define CCM_CCGR22_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR22_CLR_CG_SHIFT))&CCM_CCGR22_CLR_CG_MASK) -/* CCGR22_TOG Bit Fields */ -#define CCM_CCGR22_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR22_TOG_CG_SHIFT 0 -#define CCM_CCGR22_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR22_TOG_CG_SHIFT))&CCM_CCGR22_TOG_CG_MASK) -/* CCGR23 Bit Fields */ -#define CCM_CCGR23_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR23_CG_SHIFT 0 -#define CCM_CCGR23_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR23_CG_SHIFT))&CCM_CCGR23_CG_MASK) -/* CCGR23_SET Bit Fields */ -#define CCM_CCGR23_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR23_SET_CG_SHIFT 0 -#define CCM_CCGR23_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR23_SET_CG_SHIFT))&CCM_CCGR23_SET_CG_MASK) -/* CCGR23_CLR Bit Fields */ -#define CCM_CCGR23_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR23_CLR_CG_SHIFT 0 -#define CCM_CCGR23_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR23_CLR_CG_SHIFT))&CCM_CCGR23_CLR_CG_MASK) -/* CCGR23_TOG Bit Fields */ -#define CCM_CCGR23_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR23_TOG_CG_SHIFT 0 -#define CCM_CCGR23_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR23_TOG_CG_SHIFT))&CCM_CCGR23_TOG_CG_MASK) -/* CCGR24 Bit Fields */ -#define CCM_CCGR24_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR24_CG_SHIFT 0 -#define CCM_CCGR24_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR24_CG_SHIFT))&CCM_CCGR24_CG_MASK) -/* CCGR24_SET Bit Fields */ -#define CCM_CCGR24_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR24_SET_CG_SHIFT 0 -#define CCM_CCGR24_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR24_SET_CG_SHIFT))&CCM_CCGR24_SET_CG_MASK) -/* CCGR24_CLR Bit Fields */ -#define CCM_CCGR24_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR24_CLR_CG_SHIFT 0 -#define CCM_CCGR24_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR24_CLR_CG_SHIFT))&CCM_CCGR24_CLR_CG_MASK) -/* CCGR24_TOG Bit Fields */ -#define CCM_CCGR24_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR24_TOG_CG_SHIFT 0 -#define CCM_CCGR24_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR24_TOG_CG_SHIFT))&CCM_CCGR24_TOG_CG_MASK) -/* CCGR25 Bit Fields */ -#define CCM_CCGR25_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR25_CG_SHIFT 0 -#define CCM_CCGR25_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR25_CG_SHIFT))&CCM_CCGR25_CG_MASK) -/* CCGR25_SET Bit Fields */ -#define CCM_CCGR25_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR25_SET_CG_SHIFT 0 -#define CCM_CCGR25_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR25_SET_CG_SHIFT))&CCM_CCGR25_SET_CG_MASK) -/* CCGR25_CLR Bit Fields */ -#define CCM_CCGR25_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR25_CLR_CG_SHIFT 0 -#define CCM_CCGR25_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR25_CLR_CG_SHIFT))&CCM_CCGR25_CLR_CG_MASK) -/* CCGR25_TOG Bit Fields */ -#define CCM_CCGR25_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR25_TOG_CG_SHIFT 0 -#define CCM_CCGR25_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR25_TOG_CG_SHIFT))&CCM_CCGR25_TOG_CG_MASK) -/* CCGR26 Bit Fields */ -#define CCM_CCGR26_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR26_CG_SHIFT 0 -#define CCM_CCGR26_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR26_CG_SHIFT))&CCM_CCGR26_CG_MASK) -/* CCGR26_SET Bit Fields */ -#define CCM_CCGR26_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR26_SET_CG_SHIFT 0 -#define CCM_CCGR26_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR26_SET_CG_SHIFT))&CCM_CCGR26_SET_CG_MASK) -/* CCGR26_CLR Bit Fields */ -#define CCM_CCGR26_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR26_CLR_CG_SHIFT 0 -#define CCM_CCGR26_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR26_CLR_CG_SHIFT))&CCM_CCGR26_CLR_CG_MASK) -/* CCGR26_TOG Bit Fields */ -#define CCM_CCGR26_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR26_TOG_CG_SHIFT 0 -#define CCM_CCGR26_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR26_TOG_CG_SHIFT))&CCM_CCGR26_TOG_CG_MASK) -/* CCGR27 Bit Fields */ -#define CCM_CCGR27_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR27_CG_SHIFT 0 -#define CCM_CCGR27_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR27_CG_SHIFT))&CCM_CCGR27_CG_MASK) -/* CCGR27_SET Bit Fields */ -#define CCM_CCGR27_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR27_SET_CG_SHIFT 0 -#define CCM_CCGR27_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR27_SET_CG_SHIFT))&CCM_CCGR27_SET_CG_MASK) -/* CCGR27_CLR Bit Fields */ -#define CCM_CCGR27_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR27_CLR_CG_SHIFT 0 -#define CCM_CCGR27_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR27_CLR_CG_SHIFT))&CCM_CCGR27_CLR_CG_MASK) -/* CCGR27_TOG Bit Fields */ -#define CCM_CCGR27_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR27_TOG_CG_SHIFT 0 -#define CCM_CCGR27_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR27_TOG_CG_SHIFT))&CCM_CCGR27_TOG_CG_MASK) -/* CCGR28 Bit Fields */ -#define CCM_CCGR28_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR28_CG_SHIFT 0 -#define CCM_CCGR28_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR28_CG_SHIFT))&CCM_CCGR28_CG_MASK) -/* CCGR28_SET Bit Fields */ -#define CCM_CCGR28_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR28_SET_CG_SHIFT 0 -#define CCM_CCGR28_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR28_SET_CG_SHIFT))&CCM_CCGR28_SET_CG_MASK) -/* CCGR28_CLR Bit Fields */ -#define CCM_CCGR28_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR28_CLR_CG_SHIFT 0 -#define CCM_CCGR28_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR28_CLR_CG_SHIFT))&CCM_CCGR28_CLR_CG_MASK) -/* CCGR28_TOG Bit Fields */ -#define CCM_CCGR28_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR28_TOG_CG_SHIFT 0 -#define CCM_CCGR28_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR28_TOG_CG_SHIFT))&CCM_CCGR28_TOG_CG_MASK) -/* CCGR29 Bit Fields */ -#define CCM_CCGR29_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR29_CG_SHIFT 0 -#define CCM_CCGR29_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR29_CG_SHIFT))&CCM_CCGR29_CG_MASK) -/* CCGR29_SET Bit Fields */ -#define CCM_CCGR29_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR29_SET_CG_SHIFT 0 -#define CCM_CCGR29_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR29_SET_CG_SHIFT))&CCM_CCGR29_SET_CG_MASK) -/* CCGR29_CLR Bit Fields */ -#define CCM_CCGR29_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR29_CLR_CG_SHIFT 0 -#define CCM_CCGR29_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR29_CLR_CG_SHIFT))&CCM_CCGR29_CLR_CG_MASK) -/* CCGR29_TOG Bit Fields */ -#define CCM_CCGR29_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR29_TOG_CG_SHIFT 0 -#define CCM_CCGR29_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR29_TOG_CG_SHIFT))&CCM_CCGR29_TOG_CG_MASK) -/* CCGR30 Bit Fields */ -#define CCM_CCGR30_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR30_CG_SHIFT 0 -#define CCM_CCGR30_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR30_CG_SHIFT))&CCM_CCGR30_CG_MASK) -/* CCGR30_SET Bit Fields */ -#define CCM_CCGR30_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR30_SET_CG_SHIFT 0 -#define CCM_CCGR30_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR30_SET_CG_SHIFT))&CCM_CCGR30_SET_CG_MASK) -/* CCGR30_CLR Bit Fields */ -#define CCM_CCGR30_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR30_CLR_CG_SHIFT 0 -#define CCM_CCGR30_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR30_CLR_CG_SHIFT))&CCM_CCGR30_CLR_CG_MASK) -/* CCGR30_TOG Bit Fields */ -#define CCM_CCGR30_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR30_TOG_CG_SHIFT 0 -#define CCM_CCGR30_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR30_TOG_CG_SHIFT))&CCM_CCGR30_TOG_CG_MASK) -/* CCGR31 Bit Fields */ -#define CCM_CCGR31_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR31_CG_SHIFT 0 -#define CCM_CCGR31_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR31_CG_SHIFT))&CCM_CCGR31_CG_MASK) -/* CCGR31_SET Bit Fields */ -#define CCM_CCGR31_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR31_SET_CG_SHIFT 0 -#define CCM_CCGR31_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR31_SET_CG_SHIFT))&CCM_CCGR31_SET_CG_MASK) -/* CCGR31_CLR Bit Fields */ -#define CCM_CCGR31_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR31_CLR_CG_SHIFT 0 -#define CCM_CCGR31_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR31_CLR_CG_SHIFT))&CCM_CCGR31_CLR_CG_MASK) -/* CCGR31_TOG Bit Fields */ -#define CCM_CCGR31_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR31_TOG_CG_SHIFT 0 -#define CCM_CCGR31_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR31_TOG_CG_SHIFT))&CCM_CCGR31_TOG_CG_MASK) -/* CCGR32 Bit Fields */ -#define CCM_CCGR32_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR32_CG_SHIFT 0 -#define CCM_CCGR32_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR32_CG_SHIFT))&CCM_CCGR32_CG_MASK) -/* CCGR32_SET Bit Fields */ -#define CCM_CCGR32_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR32_SET_CG_SHIFT 0 -#define CCM_CCGR32_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR32_SET_CG_SHIFT))&CCM_CCGR32_SET_CG_MASK) -/* CCGR32_CLR Bit Fields */ -#define CCM_CCGR32_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR32_CLR_CG_SHIFT 0 -#define CCM_CCGR32_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR32_CLR_CG_SHIFT))&CCM_CCGR32_CLR_CG_MASK) -/* CCGR32_TOG Bit Fields */ -#define CCM_CCGR32_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR32_TOG_CG_SHIFT 0 -#define CCM_CCGR32_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR32_TOG_CG_SHIFT))&CCM_CCGR32_TOG_CG_MASK) -/* CCGR33 Bit Fields */ -#define CCM_CCGR33_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR33_CG_SHIFT 0 -#define CCM_CCGR33_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR33_CG_SHIFT))&CCM_CCGR33_CG_MASK) -/* CCGR33_SET Bit Fields */ -#define CCM_CCGR33_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR33_SET_CG_SHIFT 0 -#define CCM_CCGR33_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR33_SET_CG_SHIFT))&CCM_CCGR33_SET_CG_MASK) -/* CCGR33_CLR Bit Fields */ -#define CCM_CCGR33_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR33_CLR_CG_SHIFT 0 -#define CCM_CCGR33_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR33_CLR_CG_SHIFT))&CCM_CCGR33_CLR_CG_MASK) -/* CCGR33_TOG Bit Fields */ -#define CCM_CCGR33_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR33_TOG_CG_SHIFT 0 -#define CCM_CCGR33_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR33_TOG_CG_SHIFT))&CCM_CCGR33_TOG_CG_MASK) -/* CCGR34 Bit Fields */ -#define CCM_CCGR34_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR34_CG_SHIFT 0 -#define CCM_CCGR34_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR34_CG_SHIFT))&CCM_CCGR34_CG_MASK) -/* CCGR34_SET Bit Fields */ -#define CCM_CCGR34_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR34_SET_CG_SHIFT 0 -#define CCM_CCGR34_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR34_SET_CG_SHIFT))&CCM_CCGR34_SET_CG_MASK) -/* CCGR34_CLR Bit Fields */ -#define CCM_CCGR34_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR34_CLR_CG_SHIFT 0 -#define CCM_CCGR34_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR34_CLR_CG_SHIFT))&CCM_CCGR34_CLR_CG_MASK) -/* CCGR34_TOG Bit Fields */ -#define CCM_CCGR34_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR34_TOG_CG_SHIFT 0 -#define CCM_CCGR34_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR34_TOG_CG_SHIFT))&CCM_CCGR34_TOG_CG_MASK) -/* CCGR35 Bit Fields */ -#define CCM_CCGR35_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR35_CG_SHIFT 0 -#define CCM_CCGR35_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR35_CG_SHIFT))&CCM_CCGR35_CG_MASK) -/* CCGR35_SET Bit Fields */ -#define CCM_CCGR35_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR35_SET_CG_SHIFT 0 -#define CCM_CCGR35_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR35_SET_CG_SHIFT))&CCM_CCGR35_SET_CG_MASK) -/* CCGR35_CLR Bit Fields */ -#define CCM_CCGR35_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR35_CLR_CG_SHIFT 0 -#define CCM_CCGR35_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR35_CLR_CG_SHIFT))&CCM_CCGR35_CLR_CG_MASK) -/* CCGR35_TOG Bit Fields */ -#define CCM_CCGR35_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR35_TOG_CG_SHIFT 0 -#define CCM_CCGR35_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR35_TOG_CG_SHIFT))&CCM_CCGR35_TOG_CG_MASK) -/* CCGR36 Bit Fields */ -#define CCM_CCGR36_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR36_CG_SHIFT 0 -#define CCM_CCGR36_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR36_CG_SHIFT))&CCM_CCGR36_CG_MASK) -/* CCGR36_SET Bit Fields */ -#define CCM_CCGR36_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR36_SET_CG_SHIFT 0 -#define CCM_CCGR36_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR36_SET_CG_SHIFT))&CCM_CCGR36_SET_CG_MASK) -/* CCGR36_CLR Bit Fields */ -#define CCM_CCGR36_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR36_CLR_CG_SHIFT 0 -#define CCM_CCGR36_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR36_CLR_CG_SHIFT))&CCM_CCGR36_CLR_CG_MASK) -/* CCGR36_TOG Bit Fields */ -#define CCM_CCGR36_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR36_TOG_CG_SHIFT 0 -#define CCM_CCGR36_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR36_TOG_CG_SHIFT))&CCM_CCGR36_TOG_CG_MASK) -/* CCGR37 Bit Fields */ -#define CCM_CCGR37_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR37_CG_SHIFT 0 -#define CCM_CCGR37_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR37_CG_SHIFT))&CCM_CCGR37_CG_MASK) -/* CCGR37_SET Bit Fields */ -#define CCM_CCGR37_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR37_SET_CG_SHIFT 0 -#define CCM_CCGR37_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR37_SET_CG_SHIFT))&CCM_CCGR37_SET_CG_MASK) -/* CCGR37_CLR Bit Fields */ -#define CCM_CCGR37_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR37_CLR_CG_SHIFT 0 -#define CCM_CCGR37_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR37_CLR_CG_SHIFT))&CCM_CCGR37_CLR_CG_MASK) -/* CCGR37_TOG Bit Fields */ -#define CCM_CCGR37_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR37_TOG_CG_SHIFT 0 -#define CCM_CCGR37_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR37_TOG_CG_SHIFT))&CCM_CCGR37_TOG_CG_MASK) -/* CCGR38 Bit Fields */ -#define CCM_CCGR38_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR38_CG_SHIFT 0 -#define CCM_CCGR38_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR38_CG_SHIFT))&CCM_CCGR38_CG_MASK) -/* CCGR38_SET Bit Fields */ -#define CCM_CCGR38_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR38_SET_CG_SHIFT 0 -#define CCM_CCGR38_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR38_SET_CG_SHIFT))&CCM_CCGR38_SET_CG_MASK) -/* CCGR38_CLR Bit Fields */ -#define CCM_CCGR38_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR38_CLR_CG_SHIFT 0 -#define CCM_CCGR38_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR38_CLR_CG_SHIFT))&CCM_CCGR38_CLR_CG_MASK) -/* CCGR38_TOG Bit Fields */ -#define CCM_CCGR38_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR38_TOG_CG_SHIFT 0 -#define CCM_CCGR38_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR38_TOG_CG_SHIFT))&CCM_CCGR38_TOG_CG_MASK) -/* CCGR39 Bit Fields */ -#define CCM_CCGR39_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR39_CG_SHIFT 0 -#define CCM_CCGR39_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR39_CG_SHIFT))&CCM_CCGR39_CG_MASK) -/* CCGR39_SET Bit Fields */ -#define CCM_CCGR39_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR39_SET_CG_SHIFT 0 -#define CCM_CCGR39_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR39_SET_CG_SHIFT))&CCM_CCGR39_SET_CG_MASK) -/* CCGR39_CLR Bit Fields */ -#define CCM_CCGR39_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR39_CLR_CG_SHIFT 0 -#define CCM_CCGR39_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR39_CLR_CG_SHIFT))&CCM_CCGR39_CLR_CG_MASK) -/* CCGR39_TOG Bit Fields */ -#define CCM_CCGR39_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR39_TOG_CG_SHIFT 0 -#define CCM_CCGR39_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR39_TOG_CG_SHIFT))&CCM_CCGR39_TOG_CG_MASK) -/* CCGR40 Bit Fields */ -#define CCM_CCGR40_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR40_CG_SHIFT 0 -#define CCM_CCGR40_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR40_CG_SHIFT))&CCM_CCGR40_CG_MASK) -/* CCGR40_SET Bit Fields */ -#define CCM_CCGR40_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR40_SET_CG_SHIFT 0 -#define CCM_CCGR40_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR40_SET_CG_SHIFT))&CCM_CCGR40_SET_CG_MASK) -/* CCGR40_CLR Bit Fields */ -#define CCM_CCGR40_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR40_CLR_CG_SHIFT 0 -#define CCM_CCGR40_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR40_CLR_CG_SHIFT))&CCM_CCGR40_CLR_CG_MASK) -/* CCGR40_TOG Bit Fields */ -#define CCM_CCGR40_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR40_TOG_CG_SHIFT 0 -#define CCM_CCGR40_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR40_TOG_CG_SHIFT))&CCM_CCGR40_TOG_CG_MASK) -/* CCGR41 Bit Fields */ -#define CCM_CCGR41_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR41_CG_SHIFT 0 -#define CCM_CCGR41_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR41_CG_SHIFT))&CCM_CCGR41_CG_MASK) -/* CCGR41_SET Bit Fields */ -#define CCM_CCGR41_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR41_SET_CG_SHIFT 0 -#define CCM_CCGR41_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR41_SET_CG_SHIFT))&CCM_CCGR41_SET_CG_MASK) -/* CCGR41_CLR Bit Fields */ -#define CCM_CCGR41_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR41_CLR_CG_SHIFT 0 -#define CCM_CCGR41_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR41_CLR_CG_SHIFT))&CCM_CCGR41_CLR_CG_MASK) -/* CCGR41_TOG Bit Fields */ -#define CCM_CCGR41_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR41_TOG_CG_SHIFT 0 -#define CCM_CCGR41_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR41_TOG_CG_SHIFT))&CCM_CCGR41_TOG_CG_MASK) -/* CCGR42 Bit Fields */ -#define CCM_CCGR42_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR42_CG_SHIFT 0 -#define CCM_CCGR42_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR42_CG_SHIFT))&CCM_CCGR42_CG_MASK) -/* CCGR42_SET Bit Fields */ -#define CCM_CCGR42_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR42_SET_CG_SHIFT 0 -#define CCM_CCGR42_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR42_SET_CG_SHIFT))&CCM_CCGR42_SET_CG_MASK) -/* CCGR42_CLR Bit Fields */ -#define CCM_CCGR42_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR42_CLR_CG_SHIFT 0 -#define CCM_CCGR42_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR42_CLR_CG_SHIFT))&CCM_CCGR42_CLR_CG_MASK) -/* CCGR42_TOG Bit Fields */ -#define CCM_CCGR42_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR42_TOG_CG_SHIFT 0 -#define CCM_CCGR42_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR42_TOG_CG_SHIFT))&CCM_CCGR42_TOG_CG_MASK) -/* CCGR43 Bit Fields */ -#define CCM_CCGR43_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR43_CG_SHIFT 0 -#define CCM_CCGR43_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR43_CG_SHIFT))&CCM_CCGR43_CG_MASK) -/* CCGR43_SET Bit Fields */ -#define CCM_CCGR43_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR43_SET_CG_SHIFT 0 -#define CCM_CCGR43_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR43_SET_CG_SHIFT))&CCM_CCGR43_SET_CG_MASK) -/* CCGR43_CLR Bit Fields */ -#define CCM_CCGR43_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR43_CLR_CG_SHIFT 0 -#define CCM_CCGR43_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR43_CLR_CG_SHIFT))&CCM_CCGR43_CLR_CG_MASK) -/* CCGR43_TOG Bit Fields */ -#define CCM_CCGR43_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR43_TOG_CG_SHIFT 0 -#define CCM_CCGR43_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR43_TOG_CG_SHIFT))&CCM_CCGR43_TOG_CG_MASK) -/* CCGR44 Bit Fields */ -#define CCM_CCGR44_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR44_CG_SHIFT 0 -#define CCM_CCGR44_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR44_CG_SHIFT))&CCM_CCGR44_CG_MASK) -/* CCGR44_SET Bit Fields */ -#define CCM_CCGR44_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR44_SET_CG_SHIFT 0 -#define CCM_CCGR44_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR44_SET_CG_SHIFT))&CCM_CCGR44_SET_CG_MASK) -/* CCGR44_CLR Bit Fields */ -#define CCM_CCGR44_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR44_CLR_CG_SHIFT 0 -#define CCM_CCGR44_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR44_CLR_CG_SHIFT))&CCM_CCGR44_CLR_CG_MASK) -/* CCGR44_TOG Bit Fields */ -#define CCM_CCGR44_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR44_TOG_CG_SHIFT 0 -#define CCM_CCGR44_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR44_TOG_CG_SHIFT))&CCM_CCGR44_TOG_CG_MASK) -/* CCGR45 Bit Fields */ -#define CCM_CCGR45_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR45_CG_SHIFT 0 -#define CCM_CCGR45_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR45_CG_SHIFT))&CCM_CCGR45_CG_MASK) -/* CCGR45_SET Bit Fields */ -#define CCM_CCGR45_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR45_SET_CG_SHIFT 0 -#define CCM_CCGR45_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR45_SET_CG_SHIFT))&CCM_CCGR45_SET_CG_MASK) -/* CCGR45_CLR Bit Fields */ -#define CCM_CCGR45_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR45_CLR_CG_SHIFT 0 -#define CCM_CCGR45_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR45_CLR_CG_SHIFT))&CCM_CCGR45_CLR_CG_MASK) -/* CCGR45_TOG Bit Fields */ -#define CCM_CCGR45_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR45_TOG_CG_SHIFT 0 -#define CCM_CCGR45_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR45_TOG_CG_SHIFT))&CCM_CCGR45_TOG_CG_MASK) -/* CCGR46 Bit Fields */ -#define CCM_CCGR46_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR46_CG_SHIFT 0 -#define CCM_CCGR46_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR46_CG_SHIFT))&CCM_CCGR46_CG_MASK) -/* CCGR46_SET Bit Fields */ -#define CCM_CCGR46_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR46_SET_CG_SHIFT 0 -#define CCM_CCGR46_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR46_SET_CG_SHIFT))&CCM_CCGR46_SET_CG_MASK) -/* CCGR46_CLR Bit Fields */ -#define CCM_CCGR46_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR46_CLR_CG_SHIFT 0 -#define CCM_CCGR46_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR46_CLR_CG_SHIFT))&CCM_CCGR46_CLR_CG_MASK) -/* CCGR46_TOG Bit Fields */ -#define CCM_CCGR46_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR46_TOG_CG_SHIFT 0 -#define CCM_CCGR46_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR46_TOG_CG_SHIFT))&CCM_CCGR46_TOG_CG_MASK) -/* CCGR47 Bit Fields */ -#define CCM_CCGR47_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR47_CG_SHIFT 0 -#define CCM_CCGR47_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR47_CG_SHIFT))&CCM_CCGR47_CG_MASK) -/* CCGR47_SET Bit Fields */ -#define CCM_CCGR47_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR47_SET_CG_SHIFT 0 -#define CCM_CCGR47_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR47_SET_CG_SHIFT))&CCM_CCGR47_SET_CG_MASK) -/* CCGR47_CLR Bit Fields */ -#define CCM_CCGR47_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR47_CLR_CG_SHIFT 0 -#define CCM_CCGR47_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR47_CLR_CG_SHIFT))&CCM_CCGR47_CLR_CG_MASK) -/* CCGR47_TOG Bit Fields */ -#define CCM_CCGR47_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR47_TOG_CG_SHIFT 0 -#define CCM_CCGR47_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR47_TOG_CG_SHIFT))&CCM_CCGR47_TOG_CG_MASK) -/* CCGR48 Bit Fields */ -#define CCM_CCGR48_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR48_CG_SHIFT 0 -#define CCM_CCGR48_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR48_CG_SHIFT))&CCM_CCGR48_CG_MASK) -/* CCGR48_SET Bit Fields */ -#define CCM_CCGR48_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR48_SET_CG_SHIFT 0 -#define CCM_CCGR48_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR48_SET_CG_SHIFT))&CCM_CCGR48_SET_CG_MASK) -/* CCGR48_CLR Bit Fields */ -#define CCM_CCGR48_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR48_CLR_CG_SHIFT 0 -#define CCM_CCGR48_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR48_CLR_CG_SHIFT))&CCM_CCGR48_CLR_CG_MASK) -/* CCGR48_TOG Bit Fields */ -#define CCM_CCGR48_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR48_TOG_CG_SHIFT 0 -#define CCM_CCGR48_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR48_TOG_CG_SHIFT))&CCM_CCGR48_TOG_CG_MASK) -/* CCGR49 Bit Fields */ -#define CCM_CCGR49_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR49_CG_SHIFT 0 -#define CCM_CCGR49_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR49_CG_SHIFT))&CCM_CCGR49_CG_MASK) -/* CCGR49_SET Bit Fields */ -#define CCM_CCGR49_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR49_SET_CG_SHIFT 0 -#define CCM_CCGR49_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR49_SET_CG_SHIFT))&CCM_CCGR49_SET_CG_MASK) -/* CCGR49_CLR Bit Fields */ -#define CCM_CCGR49_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR49_CLR_CG_SHIFT 0 -#define CCM_CCGR49_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR49_CLR_CG_SHIFT))&CCM_CCGR49_CLR_CG_MASK) -/* CCGR49_TOG Bit Fields */ -#define CCM_CCGR49_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR49_TOG_CG_SHIFT 0 -#define CCM_CCGR49_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR49_TOG_CG_SHIFT))&CCM_CCGR49_TOG_CG_MASK) -/* CCGR50 Bit Fields */ -#define CCM_CCGR50_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR50_CG_SHIFT 0 -#define CCM_CCGR50_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR50_CG_SHIFT))&CCM_CCGR50_CG_MASK) -/* CCGR50_SET Bit Fields */ -#define CCM_CCGR50_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR50_SET_CG_SHIFT 0 -#define CCM_CCGR50_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR50_SET_CG_SHIFT))&CCM_CCGR50_SET_CG_MASK) -/* CCGR50_CLR Bit Fields */ -#define CCM_CCGR50_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR50_CLR_CG_SHIFT 0 -#define CCM_CCGR50_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR50_CLR_CG_SHIFT))&CCM_CCGR50_CLR_CG_MASK) -/* CCGR50_TOG Bit Fields */ -#define CCM_CCGR50_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR50_TOG_CG_SHIFT 0 -#define CCM_CCGR50_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR50_TOG_CG_SHIFT))&CCM_CCGR50_TOG_CG_MASK) -/* CCGR51 Bit Fields */ -#define CCM_CCGR51_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR51_CG_SHIFT 0 -#define CCM_CCGR51_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR51_CG_SHIFT))&CCM_CCGR51_CG_MASK) -/* CCGR51_SET Bit Fields */ -#define CCM_CCGR51_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR51_SET_CG_SHIFT 0 -#define CCM_CCGR51_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR51_SET_CG_SHIFT))&CCM_CCGR51_SET_CG_MASK) -/* CCGR51_CLR Bit Fields */ -#define CCM_CCGR51_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR51_CLR_CG_SHIFT 0 -#define CCM_CCGR51_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR51_CLR_CG_SHIFT))&CCM_CCGR51_CLR_CG_MASK) -/* CCGR51_TOG Bit Fields */ -#define CCM_CCGR51_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR51_TOG_CG_SHIFT 0 -#define CCM_CCGR51_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR51_TOG_CG_SHIFT))&CCM_CCGR51_TOG_CG_MASK) -/* CCGR52 Bit Fields */ -#define CCM_CCGR52_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR52_CG_SHIFT 0 -#define CCM_CCGR52_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR52_CG_SHIFT))&CCM_CCGR52_CG_MASK) -/* CCGR52_SET Bit Fields */ -#define CCM_CCGR52_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR52_SET_CG_SHIFT 0 -#define CCM_CCGR52_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR52_SET_CG_SHIFT))&CCM_CCGR52_SET_CG_MASK) -/* CCGR52_CLR Bit Fields */ -#define CCM_CCGR52_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR52_CLR_CG_SHIFT 0 -#define CCM_CCGR52_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR52_CLR_CG_SHIFT))&CCM_CCGR52_CLR_CG_MASK) -/* CCGR52_TOG Bit Fields */ -#define CCM_CCGR52_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR52_TOG_CG_SHIFT 0 -#define CCM_CCGR52_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR52_TOG_CG_SHIFT))&CCM_CCGR52_TOG_CG_MASK) -/* CCGR53 Bit Fields */ -#define CCM_CCGR53_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR53_CG_SHIFT 0 -#define CCM_CCGR53_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR53_CG_SHIFT))&CCM_CCGR53_CG_MASK) -/* CCGR53_SET Bit Fields */ -#define CCM_CCGR53_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR53_SET_CG_SHIFT 0 -#define CCM_CCGR53_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR53_SET_CG_SHIFT))&CCM_CCGR53_SET_CG_MASK) -/* CCGR53_CLR Bit Fields */ -#define CCM_CCGR53_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR53_CLR_CG_SHIFT 0 -#define CCM_CCGR53_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR53_CLR_CG_SHIFT))&CCM_CCGR53_CLR_CG_MASK) -/* CCGR53_TOG Bit Fields */ -#define CCM_CCGR53_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR53_TOG_CG_SHIFT 0 -#define CCM_CCGR53_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR53_TOG_CG_SHIFT))&CCM_CCGR53_TOG_CG_MASK) -/* CCGR54 Bit Fields */ -#define CCM_CCGR54_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR54_CG_SHIFT 0 -#define CCM_CCGR54_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR54_CG_SHIFT))&CCM_CCGR54_CG_MASK) -/* CCGR54_SET Bit Fields */ -#define CCM_CCGR54_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR54_SET_CG_SHIFT 0 -#define CCM_CCGR54_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR54_SET_CG_SHIFT))&CCM_CCGR54_SET_CG_MASK) -/* CCGR54_CLR Bit Fields */ -#define CCM_CCGR54_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR54_CLR_CG_SHIFT 0 -#define CCM_CCGR54_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR54_CLR_CG_SHIFT))&CCM_CCGR54_CLR_CG_MASK) -/* CCGR54_TOG Bit Fields */ -#define CCM_CCGR54_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR54_TOG_CG_SHIFT 0 -#define CCM_CCGR54_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR54_TOG_CG_SHIFT))&CCM_CCGR54_TOG_CG_MASK) -/* CCGR55 Bit Fields */ -#define CCM_CCGR55_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR55_CG_SHIFT 0 -#define CCM_CCGR55_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR55_CG_SHIFT))&CCM_CCGR55_CG_MASK) -/* CCGR55_SET Bit Fields */ -#define CCM_CCGR55_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR55_SET_CG_SHIFT 0 -#define CCM_CCGR55_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR55_SET_CG_SHIFT))&CCM_CCGR55_SET_CG_MASK) -/* CCGR55_CLR Bit Fields */ -#define CCM_CCGR55_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR55_CLR_CG_SHIFT 0 -#define CCM_CCGR55_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR55_CLR_CG_SHIFT))&CCM_CCGR55_CLR_CG_MASK) -/* CCGR55_TOG Bit Fields */ -#define CCM_CCGR55_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR55_TOG_CG_SHIFT 0 -#define CCM_CCGR55_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR55_TOG_CG_SHIFT))&CCM_CCGR55_TOG_CG_MASK) -/* CCGR56 Bit Fields */ -#define CCM_CCGR56_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR56_CG_SHIFT 0 -#define CCM_CCGR56_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR56_CG_SHIFT))&CCM_CCGR56_CG_MASK) -/* CCGR56_SET Bit Fields */ -#define CCM_CCGR56_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR56_SET_CG_SHIFT 0 -#define CCM_CCGR56_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR56_SET_CG_SHIFT))&CCM_CCGR56_SET_CG_MASK) -/* CCGR56_CLR Bit Fields */ -#define CCM_CCGR56_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR56_CLR_CG_SHIFT 0 -#define CCM_CCGR56_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR56_CLR_CG_SHIFT))&CCM_CCGR56_CLR_CG_MASK) -/* CCGR56_TOG Bit Fields */ -#define CCM_CCGR56_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR56_TOG_CG_SHIFT 0 -#define CCM_CCGR56_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR56_TOG_CG_SHIFT))&CCM_CCGR56_TOG_CG_MASK) -/* CCGR57 Bit Fields */ -#define CCM_CCGR57_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR57_CG_SHIFT 0 -#define CCM_CCGR57_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR57_CG_SHIFT))&CCM_CCGR57_CG_MASK) -/* CCGR57_SET Bit Fields */ -#define CCM_CCGR57_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR57_SET_CG_SHIFT 0 -#define CCM_CCGR57_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR57_SET_CG_SHIFT))&CCM_CCGR57_SET_CG_MASK) -/* CCGR57_CLR Bit Fields */ -#define CCM_CCGR57_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR57_CLR_CG_SHIFT 0 -#define CCM_CCGR57_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR57_CLR_CG_SHIFT))&CCM_CCGR57_CLR_CG_MASK) -/* CCGR57_TOG Bit Fields */ -#define CCM_CCGR57_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR57_TOG_CG_SHIFT 0 -#define CCM_CCGR57_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR57_TOG_CG_SHIFT))&CCM_CCGR57_TOG_CG_MASK) -/* CCGR58 Bit Fields */ -#define CCM_CCGR58_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR58_CG_SHIFT 0 -#define CCM_CCGR58_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR58_CG_SHIFT))&CCM_CCGR58_CG_MASK) -/* CCGR58_SET Bit Fields */ -#define CCM_CCGR58_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR58_SET_CG_SHIFT 0 -#define CCM_CCGR58_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR58_SET_CG_SHIFT))&CCM_CCGR58_SET_CG_MASK) -/* CCGR58_CLR Bit Fields */ -#define CCM_CCGR58_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR58_CLR_CG_SHIFT 0 -#define CCM_CCGR58_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR58_CLR_CG_SHIFT))&CCM_CCGR58_CLR_CG_MASK) -/* CCGR58_TOG Bit Fields */ -#define CCM_CCGR58_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR58_TOG_CG_SHIFT 0 -#define CCM_CCGR58_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR58_TOG_CG_SHIFT))&CCM_CCGR58_TOG_CG_MASK) -/* CCGR59 Bit Fields */ -#define CCM_CCGR59_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR59_CG_SHIFT 0 -#define CCM_CCGR59_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR59_CG_SHIFT))&CCM_CCGR59_CG_MASK) -/* CCGR59_SET Bit Fields */ -#define CCM_CCGR59_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR59_SET_CG_SHIFT 0 -#define CCM_CCGR59_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR59_SET_CG_SHIFT))&CCM_CCGR59_SET_CG_MASK) -/* CCGR59_CLR Bit Fields */ -#define CCM_CCGR59_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR59_CLR_CG_SHIFT 0 -#define CCM_CCGR59_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR59_CLR_CG_SHIFT))&CCM_CCGR59_CLR_CG_MASK) -/* CCGR59_TOG Bit Fields */ -#define CCM_CCGR59_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR59_TOG_CG_SHIFT 0 -#define CCM_CCGR59_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR59_TOG_CG_SHIFT))&CCM_CCGR59_TOG_CG_MASK) -/* CCGR60 Bit Fields */ -#define CCM_CCGR60_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR60_CG_SHIFT 0 -#define CCM_CCGR60_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR60_CG_SHIFT))&CCM_CCGR60_CG_MASK) -/* CCGR60_SET Bit Fields */ -#define CCM_CCGR60_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR60_SET_CG_SHIFT 0 -#define CCM_CCGR60_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR60_SET_CG_SHIFT))&CCM_CCGR60_SET_CG_MASK) -/* CCGR60_CLR Bit Fields */ -#define CCM_CCGR60_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR60_CLR_CG_SHIFT 0 -#define CCM_CCGR60_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR60_CLR_CG_SHIFT))&CCM_CCGR60_CLR_CG_MASK) -/* CCGR60_TOG Bit Fields */ -#define CCM_CCGR60_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR60_TOG_CG_SHIFT 0 -#define CCM_CCGR60_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR60_TOG_CG_SHIFT))&CCM_CCGR60_TOG_CG_MASK) -/* CCGR61 Bit Fields */ -#define CCM_CCGR61_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR61_CG_SHIFT 0 -#define CCM_CCGR61_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR61_CG_SHIFT))&CCM_CCGR61_CG_MASK) -/* CCGR61_SET Bit Fields */ -#define CCM_CCGR61_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR61_SET_CG_SHIFT 0 -#define CCM_CCGR61_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR61_SET_CG_SHIFT))&CCM_CCGR61_SET_CG_MASK) -/* CCGR61_CLR Bit Fields */ -#define CCM_CCGR61_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR61_CLR_CG_SHIFT 0 -#define CCM_CCGR61_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR61_CLR_CG_SHIFT))&CCM_CCGR61_CLR_CG_MASK) -/* CCGR61_TOG Bit Fields */ -#define CCM_CCGR61_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR61_TOG_CG_SHIFT 0 -#define CCM_CCGR61_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR61_TOG_CG_SHIFT))&CCM_CCGR61_TOG_CG_MASK) -/* CCGR62 Bit Fields */ -#define CCM_CCGR62_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR62_CG_SHIFT 0 -#define CCM_CCGR62_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR62_CG_SHIFT))&CCM_CCGR62_CG_MASK) -/* CCGR62_SET Bit Fields */ -#define CCM_CCGR62_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR62_SET_CG_SHIFT 0 -#define CCM_CCGR62_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR62_SET_CG_SHIFT))&CCM_CCGR62_SET_CG_MASK) -/* CCGR62_CLR Bit Fields */ -#define CCM_CCGR62_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR62_CLR_CG_SHIFT 0 -#define CCM_CCGR62_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR62_CLR_CG_SHIFT))&CCM_CCGR62_CLR_CG_MASK) -/* CCGR62_TOG Bit Fields */ -#define CCM_CCGR62_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR62_TOG_CG_SHIFT 0 -#define CCM_CCGR62_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR62_TOG_CG_SHIFT))&CCM_CCGR62_TOG_CG_MASK) -/* CCGR63 Bit Fields */ -#define CCM_CCGR63_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR63_CG_SHIFT 0 -#define CCM_CCGR63_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR63_CG_SHIFT))&CCM_CCGR63_CG_MASK) -/* CCGR63_SET Bit Fields */ -#define CCM_CCGR63_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR63_SET_CG_SHIFT 0 -#define CCM_CCGR63_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR63_SET_CG_SHIFT))&CCM_CCGR63_SET_CG_MASK) -/* CCGR63_CLR Bit Fields */ -#define CCM_CCGR63_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR63_CLR_CG_SHIFT 0 -#define CCM_CCGR63_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR63_CLR_CG_SHIFT))&CCM_CCGR63_CLR_CG_MASK) -/* CCGR63_TOG Bit Fields */ -#define CCM_CCGR63_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR63_TOG_CG_SHIFT 0 -#define CCM_CCGR63_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR63_TOG_CG_SHIFT))&CCM_CCGR63_TOG_CG_MASK) -/* CCGR64 Bit Fields */ -#define CCM_CCGR64_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR64_CG_SHIFT 0 -#define CCM_CCGR64_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR64_CG_SHIFT))&CCM_CCGR64_CG_MASK) -/* CCGR64_SET Bit Fields */ -#define CCM_CCGR64_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR64_SET_CG_SHIFT 0 -#define CCM_CCGR64_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR64_SET_CG_SHIFT))&CCM_CCGR64_SET_CG_MASK) -/* CCGR64_CLR Bit Fields */ -#define CCM_CCGR64_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR64_CLR_CG_SHIFT 0 -#define CCM_CCGR64_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR64_CLR_CG_SHIFT))&CCM_CCGR64_CLR_CG_MASK) -/* CCGR64_TOG Bit Fields */ -#define CCM_CCGR64_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR64_TOG_CG_SHIFT 0 -#define CCM_CCGR64_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR64_TOG_CG_SHIFT))&CCM_CCGR64_TOG_CG_MASK) -/* CCGR65 Bit Fields */ -#define CCM_CCGR65_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR65_CG_SHIFT 0 -#define CCM_CCGR65_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR65_CG_SHIFT))&CCM_CCGR65_CG_MASK) -/* CCGR65_SET Bit Fields */ -#define CCM_CCGR65_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR65_SET_CG_SHIFT 0 -#define CCM_CCGR65_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR65_SET_CG_SHIFT))&CCM_CCGR65_SET_CG_MASK) -/* CCGR65_CLR Bit Fields */ -#define CCM_CCGR65_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR65_CLR_CG_SHIFT 0 -#define CCM_CCGR65_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR65_CLR_CG_SHIFT))&CCM_CCGR65_CLR_CG_MASK) -/* CCGR65_TOG Bit Fields */ -#define CCM_CCGR65_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR65_TOG_CG_SHIFT 0 -#define CCM_CCGR65_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR65_TOG_CG_SHIFT))&CCM_CCGR65_TOG_CG_MASK) -/* CCGR66 Bit Fields */ -#define CCM_CCGR66_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR66_CG_SHIFT 0 -#define CCM_CCGR66_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR66_CG_SHIFT))&CCM_CCGR66_CG_MASK) -/* CCGR66_SET Bit Fields */ -#define CCM_CCGR66_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR66_SET_CG_SHIFT 0 -#define CCM_CCGR66_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR66_SET_CG_SHIFT))&CCM_CCGR66_SET_CG_MASK) -/* CCGR66_CLR Bit Fields */ -#define CCM_CCGR66_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR66_CLR_CG_SHIFT 0 -#define CCM_CCGR66_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR66_CLR_CG_SHIFT))&CCM_CCGR66_CLR_CG_MASK) -/* CCGR66_TOG Bit Fields */ -#define CCM_CCGR66_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR66_TOG_CG_SHIFT 0 -#define CCM_CCGR66_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR66_TOG_CG_SHIFT))&CCM_CCGR66_TOG_CG_MASK) -/* CCGR67 Bit Fields */ -#define CCM_CCGR67_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR67_CG_SHIFT 0 -#define CCM_CCGR67_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR67_CG_SHIFT))&CCM_CCGR67_CG_MASK) -/* CCGR67_SET Bit Fields */ -#define CCM_CCGR67_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR67_SET_CG_SHIFT 0 -#define CCM_CCGR67_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR67_SET_CG_SHIFT))&CCM_CCGR67_SET_CG_MASK) -/* CCGR67_CLR Bit Fields */ -#define CCM_CCGR67_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR67_CLR_CG_SHIFT 0 -#define CCM_CCGR67_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR67_CLR_CG_SHIFT))&CCM_CCGR67_CLR_CG_MASK) -/* CCGR67_TOG Bit Fields */ -#define CCM_CCGR67_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR67_TOG_CG_SHIFT 0 -#define CCM_CCGR67_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR67_TOG_CG_SHIFT))&CCM_CCGR67_TOG_CG_MASK) -/* CCGR68 Bit Fields */ -#define CCM_CCGR68_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR68_CG_SHIFT 0 -#define CCM_CCGR68_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR68_CG_SHIFT))&CCM_CCGR68_CG_MASK) -/* CCGR68_SET Bit Fields */ -#define CCM_CCGR68_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR68_SET_CG_SHIFT 0 -#define CCM_CCGR68_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR68_SET_CG_SHIFT))&CCM_CCGR68_SET_CG_MASK) -/* CCGR68_CLR Bit Fields */ -#define CCM_CCGR68_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR68_CLR_CG_SHIFT 0 -#define CCM_CCGR68_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR68_CLR_CG_SHIFT))&CCM_CCGR68_CLR_CG_MASK) -/* CCGR68_TOG Bit Fields */ -#define CCM_CCGR68_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR68_TOG_CG_SHIFT 0 -#define CCM_CCGR68_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR68_TOG_CG_SHIFT))&CCM_CCGR68_TOG_CG_MASK) -/* CCGR69 Bit Fields */ -#define CCM_CCGR69_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR69_CG_SHIFT 0 -#define CCM_CCGR69_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR69_CG_SHIFT))&CCM_CCGR69_CG_MASK) -/* CCGR69_SET Bit Fields */ -#define CCM_CCGR69_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR69_SET_CG_SHIFT 0 -#define CCM_CCGR69_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR69_SET_CG_SHIFT))&CCM_CCGR69_SET_CG_MASK) -/* CCGR69_CLR Bit Fields */ -#define CCM_CCGR69_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR69_CLR_CG_SHIFT 0 -#define CCM_CCGR69_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR69_CLR_CG_SHIFT))&CCM_CCGR69_CLR_CG_MASK) -/* CCGR69_TOG Bit Fields */ -#define CCM_CCGR69_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR69_TOG_CG_SHIFT 0 -#define CCM_CCGR69_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR69_TOG_CG_SHIFT))&CCM_CCGR69_TOG_CG_MASK) -/* CCGR70 Bit Fields */ -#define CCM_CCGR70_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR70_CG_SHIFT 0 -#define CCM_CCGR70_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR70_CG_SHIFT))&CCM_CCGR70_CG_MASK) -/* CCGR70_SET Bit Fields */ -#define CCM_CCGR70_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR70_SET_CG_SHIFT 0 -#define CCM_CCGR70_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR70_SET_CG_SHIFT))&CCM_CCGR70_SET_CG_MASK) -/* CCGR70_CLR Bit Fields */ -#define CCM_CCGR70_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR70_CLR_CG_SHIFT 0 -#define CCM_CCGR70_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR70_CLR_CG_SHIFT))&CCM_CCGR70_CLR_CG_MASK) -/* CCGR70_TOG Bit Fields */ -#define CCM_CCGR70_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR70_TOG_CG_SHIFT 0 -#define CCM_CCGR70_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR70_TOG_CG_SHIFT))&CCM_CCGR70_TOG_CG_MASK) -/* CCGR71 Bit Fields */ -#define CCM_CCGR71_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR71_CG_SHIFT 0 -#define CCM_CCGR71_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR71_CG_SHIFT))&CCM_CCGR71_CG_MASK) -/* CCGR71_SET Bit Fields */ -#define CCM_CCGR71_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR71_SET_CG_SHIFT 0 -#define CCM_CCGR71_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR71_SET_CG_SHIFT))&CCM_CCGR71_SET_CG_MASK) -/* CCGR71_CLR Bit Fields */ -#define CCM_CCGR71_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR71_CLR_CG_SHIFT 0 -#define CCM_CCGR71_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR71_CLR_CG_SHIFT))&CCM_CCGR71_CLR_CG_MASK) -/* CCGR71_TOG Bit Fields */ -#define CCM_CCGR71_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR71_TOG_CG_SHIFT 0 -#define CCM_CCGR71_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR71_TOG_CG_SHIFT))&CCM_CCGR71_TOG_CG_MASK) -/* CCGR72 Bit Fields */ -#define CCM_CCGR72_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR72_CG_SHIFT 0 -#define CCM_CCGR72_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR72_CG_SHIFT))&CCM_CCGR72_CG_MASK) -/* CCGR72_SET Bit Fields */ -#define CCM_CCGR72_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR72_SET_CG_SHIFT 0 -#define CCM_CCGR72_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR72_SET_CG_SHIFT))&CCM_CCGR72_SET_CG_MASK) -/* CCGR72_CLR Bit Fields */ -#define CCM_CCGR72_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR72_CLR_CG_SHIFT 0 -#define CCM_CCGR72_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR72_CLR_CG_SHIFT))&CCM_CCGR72_CLR_CG_MASK) -/* CCGR72_TOG Bit Fields */ -#define CCM_CCGR72_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR72_TOG_CG_SHIFT 0 -#define CCM_CCGR72_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR72_TOG_CG_SHIFT))&CCM_CCGR72_TOG_CG_MASK) -/* CCGR73 Bit Fields */ -#define CCM_CCGR73_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR73_CG_SHIFT 0 -#define CCM_CCGR73_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR73_CG_SHIFT))&CCM_CCGR73_CG_MASK) -/* CCGR73_SET Bit Fields */ -#define CCM_CCGR73_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR73_SET_CG_SHIFT 0 -#define CCM_CCGR73_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR73_SET_CG_SHIFT))&CCM_CCGR73_SET_CG_MASK) -/* CCGR73_CLR Bit Fields */ -#define CCM_CCGR73_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR73_CLR_CG_SHIFT 0 -#define CCM_CCGR73_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR73_CLR_CG_SHIFT))&CCM_CCGR73_CLR_CG_MASK) -/* CCGR73_TOG Bit Fields */ -#define CCM_CCGR73_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR73_TOG_CG_SHIFT 0 -#define CCM_CCGR73_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR73_TOG_CG_SHIFT))&CCM_CCGR73_TOG_CG_MASK) -/* CCGR74 Bit Fields */ -#define CCM_CCGR74_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR74_CG_SHIFT 0 -#define CCM_CCGR74_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR74_CG_SHIFT))&CCM_CCGR74_CG_MASK) -/* CCGR74_SET Bit Fields */ -#define CCM_CCGR74_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR74_SET_CG_SHIFT 0 -#define CCM_CCGR74_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR74_SET_CG_SHIFT))&CCM_CCGR74_SET_CG_MASK) -/* CCGR74_CLR Bit Fields */ -#define CCM_CCGR74_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR74_CLR_CG_SHIFT 0 -#define CCM_CCGR74_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR74_CLR_CG_SHIFT))&CCM_CCGR74_CLR_CG_MASK) -/* CCGR74_TOG Bit Fields */ -#define CCM_CCGR74_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR74_TOG_CG_SHIFT 0 -#define CCM_CCGR74_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR74_TOG_CG_SHIFT))&CCM_CCGR74_TOG_CG_MASK) -/* CCGR75 Bit Fields */ -#define CCM_CCGR75_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR75_CG_SHIFT 0 -#define CCM_CCGR75_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR75_CG_SHIFT))&CCM_CCGR75_CG_MASK) -/* CCGR75_SET Bit Fields */ -#define CCM_CCGR75_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR75_SET_CG_SHIFT 0 -#define CCM_CCGR75_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR75_SET_CG_SHIFT))&CCM_CCGR75_SET_CG_MASK) -/* CCGR75_CLR Bit Fields */ -#define CCM_CCGR75_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR75_CLR_CG_SHIFT 0 -#define CCM_CCGR75_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR75_CLR_CG_SHIFT))&CCM_CCGR75_CLR_CG_MASK) -/* CCGR75_TOG Bit Fields */ -#define CCM_CCGR75_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR75_TOG_CG_SHIFT 0 -#define CCM_CCGR75_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR75_TOG_CG_SHIFT))&CCM_CCGR75_TOG_CG_MASK) -/* CCGR76 Bit Fields */ -#define CCM_CCGR76_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR76_CG_SHIFT 0 -#define CCM_CCGR76_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR76_CG_SHIFT))&CCM_CCGR76_CG_MASK) -/* CCGR76_SET Bit Fields */ -#define CCM_CCGR76_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR76_SET_CG_SHIFT 0 -#define CCM_CCGR76_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR76_SET_CG_SHIFT))&CCM_CCGR76_SET_CG_MASK) -/* CCGR76_CLR Bit Fields */ -#define CCM_CCGR76_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR76_CLR_CG_SHIFT 0 -#define CCM_CCGR76_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR76_CLR_CG_SHIFT))&CCM_CCGR76_CLR_CG_MASK) -/* CCGR76_TOG Bit Fields */ -#define CCM_CCGR76_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR76_TOG_CG_SHIFT 0 -#define CCM_CCGR76_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR76_TOG_CG_SHIFT))&CCM_CCGR76_TOG_CG_MASK) -/* CCGR77 Bit Fields */ -#define CCM_CCGR77_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR77_CG_SHIFT 0 -#define CCM_CCGR77_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR77_CG_SHIFT))&CCM_CCGR77_CG_MASK) -/* CCGR77_SET Bit Fields */ -#define CCM_CCGR77_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR77_SET_CG_SHIFT 0 -#define CCM_CCGR77_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR77_SET_CG_SHIFT))&CCM_CCGR77_SET_CG_MASK) -/* CCGR77_CLR Bit Fields */ -#define CCM_CCGR77_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR77_CLR_CG_SHIFT 0 -#define CCM_CCGR77_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR77_CLR_CG_SHIFT))&CCM_CCGR77_CLR_CG_MASK) -/* CCGR77_TOG Bit Fields */ -#define CCM_CCGR77_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR77_TOG_CG_SHIFT 0 -#define CCM_CCGR77_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR77_TOG_CG_SHIFT))&CCM_CCGR77_TOG_CG_MASK) -/* CCGR78 Bit Fields */ -#define CCM_CCGR78_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR78_CG_SHIFT 0 -#define CCM_CCGR78_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR78_CG_SHIFT))&CCM_CCGR78_CG_MASK) -/* CCGR78_SET Bit Fields */ -#define CCM_CCGR78_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR78_SET_CG_SHIFT 0 -#define CCM_CCGR78_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR78_SET_CG_SHIFT))&CCM_CCGR78_SET_CG_MASK) -/* CCGR78_CLR Bit Fields */ -#define CCM_CCGR78_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR78_CLR_CG_SHIFT 0 -#define CCM_CCGR78_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR78_CLR_CG_SHIFT))&CCM_CCGR78_CLR_CG_MASK) -/* CCGR78_TOG Bit Fields */ -#define CCM_CCGR78_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR78_TOG_CG_SHIFT 0 -#define CCM_CCGR78_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR78_TOG_CG_SHIFT))&CCM_CCGR78_TOG_CG_MASK) -/* CCGR79 Bit Fields */ -#define CCM_CCGR79_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR79_CG_SHIFT 0 -#define CCM_CCGR79_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR79_CG_SHIFT))&CCM_CCGR79_CG_MASK) -/* CCGR79_SET Bit Fields */ -#define CCM_CCGR79_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR79_SET_CG_SHIFT 0 -#define CCM_CCGR79_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR79_SET_CG_SHIFT))&CCM_CCGR79_SET_CG_MASK) -/* CCGR79_CLR Bit Fields */ -#define CCM_CCGR79_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR79_CLR_CG_SHIFT 0 -#define CCM_CCGR79_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR79_CLR_CG_SHIFT))&CCM_CCGR79_CLR_CG_MASK) -/* CCGR79_TOG Bit Fields */ -#define CCM_CCGR79_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR79_TOG_CG_SHIFT 0 -#define CCM_CCGR79_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR79_TOG_CG_SHIFT))&CCM_CCGR79_TOG_CG_MASK) -/* CCGR80 Bit Fields */ -#define CCM_CCGR80_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR80_CG_SHIFT 0 -#define CCM_CCGR80_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR80_CG_SHIFT))&CCM_CCGR80_CG_MASK) -/* CCGR80_SET Bit Fields */ -#define CCM_CCGR80_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR80_SET_CG_SHIFT 0 -#define CCM_CCGR80_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR80_SET_CG_SHIFT))&CCM_CCGR80_SET_CG_MASK) -/* CCGR80_CLR Bit Fields */ -#define CCM_CCGR80_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR80_CLR_CG_SHIFT 0 -#define CCM_CCGR80_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR80_CLR_CG_SHIFT))&CCM_CCGR80_CLR_CG_MASK) -/* CCGR80_TOG Bit Fields */ -#define CCM_CCGR80_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR80_TOG_CG_SHIFT 0 -#define CCM_CCGR80_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR80_TOG_CG_SHIFT))&CCM_CCGR80_TOG_CG_MASK) -/* CCGR81 Bit Fields */ -#define CCM_CCGR81_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR81_CG_SHIFT 0 -#define CCM_CCGR81_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR81_CG_SHIFT))&CCM_CCGR81_CG_MASK) -/* CCGR81_SET Bit Fields */ -#define CCM_CCGR81_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR81_SET_CG_SHIFT 0 -#define CCM_CCGR81_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR81_SET_CG_SHIFT))&CCM_CCGR81_SET_CG_MASK) -/* CCGR81_CLR Bit Fields */ -#define CCM_CCGR81_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR81_CLR_CG_SHIFT 0 -#define CCM_CCGR81_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR81_CLR_CG_SHIFT))&CCM_CCGR81_CLR_CG_MASK) -/* CCGR81_TOG Bit Fields */ -#define CCM_CCGR81_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR81_TOG_CG_SHIFT 0 -#define CCM_CCGR81_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR81_TOG_CG_SHIFT))&CCM_CCGR81_TOG_CG_MASK) -/* CCGR82 Bit Fields */ -#define CCM_CCGR82_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR82_CG_SHIFT 0 -#define CCM_CCGR82_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR82_CG_SHIFT))&CCM_CCGR82_CG_MASK) -/* CCGR82_SET Bit Fields */ -#define CCM_CCGR82_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR82_SET_CG_SHIFT 0 -#define CCM_CCGR82_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR82_SET_CG_SHIFT))&CCM_CCGR82_SET_CG_MASK) -/* CCGR82_CLR Bit Fields */ -#define CCM_CCGR82_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR82_CLR_CG_SHIFT 0 -#define CCM_CCGR82_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR82_CLR_CG_SHIFT))&CCM_CCGR82_CLR_CG_MASK) -/* CCGR82_TOG Bit Fields */ -#define CCM_CCGR82_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR82_TOG_CG_SHIFT 0 -#define CCM_CCGR82_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR82_TOG_CG_SHIFT))&CCM_CCGR82_TOG_CG_MASK) -/* CCGR83 Bit Fields */ -#define CCM_CCGR83_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR83_CG_SHIFT 0 -#define CCM_CCGR83_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR83_CG_SHIFT))&CCM_CCGR83_CG_MASK) -/* CCGR83_SET Bit Fields */ -#define CCM_CCGR83_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR83_SET_CG_SHIFT 0 -#define CCM_CCGR83_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR83_SET_CG_SHIFT))&CCM_CCGR83_SET_CG_MASK) -/* CCGR83_CLR Bit Fields */ -#define CCM_CCGR83_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR83_CLR_CG_SHIFT 0 -#define CCM_CCGR83_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR83_CLR_CG_SHIFT))&CCM_CCGR83_CLR_CG_MASK) -/* CCGR83_TOG Bit Fields */ -#define CCM_CCGR83_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR83_TOG_CG_SHIFT 0 -#define CCM_CCGR83_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR83_TOG_CG_SHIFT))&CCM_CCGR83_TOG_CG_MASK) -/* CCGR84 Bit Fields */ -#define CCM_CCGR84_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR84_CG_SHIFT 0 -#define CCM_CCGR84_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR84_CG_SHIFT))&CCM_CCGR84_CG_MASK) -/* CCGR84_SET Bit Fields */ -#define CCM_CCGR84_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR84_SET_CG_SHIFT 0 -#define CCM_CCGR84_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR84_SET_CG_SHIFT))&CCM_CCGR84_SET_CG_MASK) -/* CCGR84_CLR Bit Fields */ -#define CCM_CCGR84_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR84_CLR_CG_SHIFT 0 -#define CCM_CCGR84_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR84_CLR_CG_SHIFT))&CCM_CCGR84_CLR_CG_MASK) -/* CCGR84_TOG Bit Fields */ -#define CCM_CCGR84_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR84_TOG_CG_SHIFT 0 -#define CCM_CCGR84_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR84_TOG_CG_SHIFT))&CCM_CCGR84_TOG_CG_MASK) -/* CCGR85 Bit Fields */ -#define CCM_CCGR85_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR85_CG_SHIFT 0 -#define CCM_CCGR85_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR85_CG_SHIFT))&CCM_CCGR85_CG_MASK) -/* CCGR85_SET Bit Fields */ -#define CCM_CCGR85_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR85_SET_CG_SHIFT 0 -#define CCM_CCGR85_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR85_SET_CG_SHIFT))&CCM_CCGR85_SET_CG_MASK) -/* CCGR85_CLR Bit Fields */ -#define CCM_CCGR85_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR85_CLR_CG_SHIFT 0 -#define CCM_CCGR85_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR85_CLR_CG_SHIFT))&CCM_CCGR85_CLR_CG_MASK) -/* CCGR85_TOG Bit Fields */ -#define CCM_CCGR85_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR85_TOG_CG_SHIFT 0 -#define CCM_CCGR85_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR85_TOG_CG_SHIFT))&CCM_CCGR85_TOG_CG_MASK) -/* CCGR86 Bit Fields */ -#define CCM_CCGR86_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR86_CG_SHIFT 0 -#define CCM_CCGR86_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR86_CG_SHIFT))&CCM_CCGR86_CG_MASK) -/* CCGR86_SET Bit Fields */ -#define CCM_CCGR86_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR86_SET_CG_SHIFT 0 -#define CCM_CCGR86_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR86_SET_CG_SHIFT))&CCM_CCGR86_SET_CG_MASK) -/* CCGR86_CLR Bit Fields */ -#define CCM_CCGR86_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR86_CLR_CG_SHIFT 0 -#define CCM_CCGR86_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR86_CLR_CG_SHIFT))&CCM_CCGR86_CLR_CG_MASK) -/* CCGR86_TOG Bit Fields */ -#define CCM_CCGR86_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR86_TOG_CG_SHIFT 0 -#define CCM_CCGR86_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR86_TOG_CG_SHIFT))&CCM_CCGR86_TOG_CG_MASK) -/* CCGR87 Bit Fields */ -#define CCM_CCGR87_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR87_CG_SHIFT 0 -#define CCM_CCGR87_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR87_CG_SHIFT))&CCM_CCGR87_CG_MASK) -/* CCGR87_SET Bit Fields */ -#define CCM_CCGR87_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR87_SET_CG_SHIFT 0 -#define CCM_CCGR87_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR87_SET_CG_SHIFT))&CCM_CCGR87_SET_CG_MASK) -/* CCGR87_CLR Bit Fields */ -#define CCM_CCGR87_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR87_CLR_CG_SHIFT 0 -#define CCM_CCGR87_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR87_CLR_CG_SHIFT))&CCM_CCGR87_CLR_CG_MASK) -/* CCGR87_TOG Bit Fields */ -#define CCM_CCGR87_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR87_TOG_CG_SHIFT 0 -#define CCM_CCGR87_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR87_TOG_CG_SHIFT))&CCM_CCGR87_TOG_CG_MASK) -/* CCGR88 Bit Fields */ -#define CCM_CCGR88_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR88_CG_SHIFT 0 -#define CCM_CCGR88_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR88_CG_SHIFT))&CCM_CCGR88_CG_MASK) -/* CCGR88_SET Bit Fields */ -#define CCM_CCGR88_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR88_SET_CG_SHIFT 0 -#define CCM_CCGR88_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR88_SET_CG_SHIFT))&CCM_CCGR88_SET_CG_MASK) -/* CCGR88_CLR Bit Fields */ -#define CCM_CCGR88_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR88_CLR_CG_SHIFT 0 -#define CCM_CCGR88_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR88_CLR_CG_SHIFT))&CCM_CCGR88_CLR_CG_MASK) -/* CCGR88_TOG Bit Fields */ -#define CCM_CCGR88_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR88_TOG_CG_SHIFT 0 -#define CCM_CCGR88_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR88_TOG_CG_SHIFT))&CCM_CCGR88_TOG_CG_MASK) -/* CCGR89 Bit Fields */ -#define CCM_CCGR89_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR89_CG_SHIFT 0 -#define CCM_CCGR89_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR89_CG_SHIFT))&CCM_CCGR89_CG_MASK) -/* CCGR89_SET Bit Fields */ -#define CCM_CCGR89_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR89_SET_CG_SHIFT 0 -#define CCM_CCGR89_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR89_SET_CG_SHIFT))&CCM_CCGR89_SET_CG_MASK) -/* CCGR89_CLR Bit Fields */ -#define CCM_CCGR89_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR89_CLR_CG_SHIFT 0 -#define CCM_CCGR89_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR89_CLR_CG_SHIFT))&CCM_CCGR89_CLR_CG_MASK) -/* CCGR89_TOG Bit Fields */ -#define CCM_CCGR89_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR89_TOG_CG_SHIFT 0 -#define CCM_CCGR89_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR89_TOG_CG_SHIFT))&CCM_CCGR89_TOG_CG_MASK) -/* CCGR90 Bit Fields */ -#define CCM_CCGR90_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR90_CG_SHIFT 0 -#define CCM_CCGR90_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR90_CG_SHIFT))&CCM_CCGR90_CG_MASK) -/* CCGR90_SET Bit Fields */ -#define CCM_CCGR90_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR90_SET_CG_SHIFT 0 -#define CCM_CCGR90_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR90_SET_CG_SHIFT))&CCM_CCGR90_SET_CG_MASK) -/* CCGR90_CLR Bit Fields */ -#define CCM_CCGR90_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR90_CLR_CG_SHIFT 0 -#define CCM_CCGR90_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR90_CLR_CG_SHIFT))&CCM_CCGR90_CLR_CG_MASK) -/* CCGR90_TOG Bit Fields */ -#define CCM_CCGR90_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR90_TOG_CG_SHIFT 0 -#define CCM_CCGR90_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR90_TOG_CG_SHIFT))&CCM_CCGR90_TOG_CG_MASK) -/* CCGR91 Bit Fields */ -#define CCM_CCGR91_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR91_CG_SHIFT 0 -#define CCM_CCGR91_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR91_CG_SHIFT))&CCM_CCGR91_CG_MASK) -/* CCGR91_SET Bit Fields */ -#define CCM_CCGR91_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR91_SET_CG_SHIFT 0 -#define CCM_CCGR91_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR91_SET_CG_SHIFT))&CCM_CCGR91_SET_CG_MASK) -/* CCGR91_CLR Bit Fields */ -#define CCM_CCGR91_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR91_CLR_CG_SHIFT 0 -#define CCM_CCGR91_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR91_CLR_CG_SHIFT))&CCM_CCGR91_CLR_CG_MASK) -/* CCGR91_TOG Bit Fields */ -#define CCM_CCGR91_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR91_TOG_CG_SHIFT 0 -#define CCM_CCGR91_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR91_TOG_CG_SHIFT))&CCM_CCGR91_TOG_CG_MASK) -/* CCGR92 Bit Fields */ -#define CCM_CCGR92_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR92_CG_SHIFT 0 -#define CCM_CCGR92_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR92_CG_SHIFT))&CCM_CCGR92_CG_MASK) -/* CCGR92_SET Bit Fields */ -#define CCM_CCGR92_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR92_SET_CG_SHIFT 0 -#define CCM_CCGR92_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR92_SET_CG_SHIFT))&CCM_CCGR92_SET_CG_MASK) -/* CCGR92_CLR Bit Fields */ -#define CCM_CCGR92_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR92_CLR_CG_SHIFT 0 -#define CCM_CCGR92_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR92_CLR_CG_SHIFT))&CCM_CCGR92_CLR_CG_MASK) -/* CCGR92_TOG Bit Fields */ -#define CCM_CCGR92_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR92_TOG_CG_SHIFT 0 -#define CCM_CCGR92_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR92_TOG_CG_SHIFT))&CCM_CCGR92_TOG_CG_MASK) -/* CCGR93 Bit Fields */ -#define CCM_CCGR93_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR93_CG_SHIFT 0 -#define CCM_CCGR93_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR93_CG_SHIFT))&CCM_CCGR93_CG_MASK) -/* CCGR93_SET Bit Fields */ -#define CCM_CCGR93_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR93_SET_CG_SHIFT 0 -#define CCM_CCGR93_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR93_SET_CG_SHIFT))&CCM_CCGR93_SET_CG_MASK) -/* CCGR93_CLR Bit Fields */ -#define CCM_CCGR93_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR93_CLR_CG_SHIFT 0 -#define CCM_CCGR93_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR93_CLR_CG_SHIFT))&CCM_CCGR93_CLR_CG_MASK) -/* CCGR93_TOG Bit Fields */ -#define CCM_CCGR93_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR93_TOG_CG_SHIFT 0 -#define CCM_CCGR93_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR93_TOG_CG_SHIFT))&CCM_CCGR93_TOG_CG_MASK) -/* CCGR94 Bit Fields */ -#define CCM_CCGR94_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR94_CG_SHIFT 0 -#define CCM_CCGR94_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR94_CG_SHIFT))&CCM_CCGR94_CG_MASK) -/* CCGR94_SET Bit Fields */ -#define CCM_CCGR94_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR94_SET_CG_SHIFT 0 -#define CCM_CCGR94_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR94_SET_CG_SHIFT))&CCM_CCGR94_SET_CG_MASK) -/* CCGR94_CLR Bit Fields */ -#define CCM_CCGR94_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR94_CLR_CG_SHIFT 0 -#define CCM_CCGR94_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR94_CLR_CG_SHIFT))&CCM_CCGR94_CLR_CG_MASK) -/* CCGR94_TOG Bit Fields */ -#define CCM_CCGR94_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR94_TOG_CG_SHIFT 0 -#define CCM_CCGR94_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR94_TOG_CG_SHIFT))&CCM_CCGR94_TOG_CG_MASK) -/* CCGR95 Bit Fields */ -#define CCM_CCGR95_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR95_CG_SHIFT 0 -#define CCM_CCGR95_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR95_CG_SHIFT))&CCM_CCGR95_CG_MASK) -/* CCGR95_SET Bit Fields */ -#define CCM_CCGR95_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR95_SET_CG_SHIFT 0 -#define CCM_CCGR95_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR95_SET_CG_SHIFT))&CCM_CCGR95_SET_CG_MASK) -/* CCGR95_CLR Bit Fields */ -#define CCM_CCGR95_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR95_CLR_CG_SHIFT 0 -#define CCM_CCGR95_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR95_CLR_CG_SHIFT))&CCM_CCGR95_CLR_CG_MASK) -/* CCGR95_TOG Bit Fields */ -#define CCM_CCGR95_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR95_TOG_CG_SHIFT 0 -#define CCM_CCGR95_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR95_TOG_CG_SHIFT))&CCM_CCGR95_TOG_CG_MASK) -/* CCGR96 Bit Fields */ -#define CCM_CCGR96_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR96_CG_SHIFT 0 -#define CCM_CCGR96_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR96_CG_SHIFT))&CCM_CCGR96_CG_MASK) -/* CCGR96_SET Bit Fields */ -#define CCM_CCGR96_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR96_SET_CG_SHIFT 0 -#define CCM_CCGR96_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR96_SET_CG_SHIFT))&CCM_CCGR96_SET_CG_MASK) -/* CCGR96_CLR Bit Fields */ -#define CCM_CCGR96_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR96_CLR_CG_SHIFT 0 -#define CCM_CCGR96_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR96_CLR_CG_SHIFT))&CCM_CCGR96_CLR_CG_MASK) -/* CCGR96_TOG Bit Fields */ -#define CCM_CCGR96_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR96_TOG_CG_SHIFT 0 -#define CCM_CCGR96_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR96_TOG_CG_SHIFT))&CCM_CCGR96_TOG_CG_MASK) -/* CCGR97 Bit Fields */ -#define CCM_CCGR97_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR97_CG_SHIFT 0 -#define CCM_CCGR97_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR97_CG_SHIFT))&CCM_CCGR97_CG_MASK) -/* CCGR97_SET Bit Fields */ -#define CCM_CCGR97_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR97_SET_CG_SHIFT 0 -#define CCM_CCGR97_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR97_SET_CG_SHIFT))&CCM_CCGR97_SET_CG_MASK) -/* CCGR97_CLR Bit Fields */ -#define CCM_CCGR97_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR97_CLR_CG_SHIFT 0 -#define CCM_CCGR97_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR97_CLR_CG_SHIFT))&CCM_CCGR97_CLR_CG_MASK) -/* CCGR97_TOG Bit Fields */ -#define CCM_CCGR97_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR97_TOG_CG_SHIFT 0 -#define CCM_CCGR97_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR97_TOG_CG_SHIFT))&CCM_CCGR97_TOG_CG_MASK) -/* CCGR98 Bit Fields */ -#define CCM_CCGR98_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR98_CG_SHIFT 0 -#define CCM_CCGR98_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR98_CG_SHIFT))&CCM_CCGR98_CG_MASK) -/* CCGR98_SET Bit Fields */ -#define CCM_CCGR98_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR98_SET_CG_SHIFT 0 -#define CCM_CCGR98_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR98_SET_CG_SHIFT))&CCM_CCGR98_SET_CG_MASK) -/* CCGR98_CLR Bit Fields */ -#define CCM_CCGR98_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR98_CLR_CG_SHIFT 0 -#define CCM_CCGR98_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR98_CLR_CG_SHIFT))&CCM_CCGR98_CLR_CG_MASK) -/* CCGR98_TOG Bit Fields */ -#define CCM_CCGR98_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR98_TOG_CG_SHIFT 0 -#define CCM_CCGR98_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR98_TOG_CG_SHIFT))&CCM_CCGR98_TOG_CG_MASK) -/* CCGR99 Bit Fields */ -#define CCM_CCGR99_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR99_CG_SHIFT 0 -#define CCM_CCGR99_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR99_CG_SHIFT))&CCM_CCGR99_CG_MASK) -/* CCGR99_SET Bit Fields */ -#define CCM_CCGR99_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR99_SET_CG_SHIFT 0 -#define CCM_CCGR99_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR99_SET_CG_SHIFT))&CCM_CCGR99_SET_CG_MASK) -/* CCGR99_CLR Bit Fields */ -#define CCM_CCGR99_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR99_CLR_CG_SHIFT 0 -#define CCM_CCGR99_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR99_CLR_CG_SHIFT))&CCM_CCGR99_CLR_CG_MASK) -/* CCGR99_TOG Bit Fields */ -#define CCM_CCGR99_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR99_TOG_CG_SHIFT 0 -#define CCM_CCGR99_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR99_TOG_CG_SHIFT))&CCM_CCGR99_TOG_CG_MASK) -/* CCGR100 Bit Fields */ -#define CCM_CCGR100_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR100_CG_SHIFT 0 -#define CCM_CCGR100_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR100_CG_SHIFT))&CCM_CCGR100_CG_MASK) -/* CCGR100_SET Bit Fields */ -#define CCM_CCGR100_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR100_SET_CG_SHIFT 0 -#define CCM_CCGR100_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR100_SET_CG_SHIFT))&CCM_CCGR100_SET_CG_MASK) -/* CCGR100_CLR Bit Fields */ -#define CCM_CCGR100_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR100_CLR_CG_SHIFT 0 -#define CCM_CCGR100_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR100_CLR_CG_SHIFT))&CCM_CCGR100_CLR_CG_MASK) -/* CCGR100_TOG Bit Fields */ -#define CCM_CCGR100_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR100_TOG_CG_SHIFT 0 -#define CCM_CCGR100_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR100_TOG_CG_SHIFT))&CCM_CCGR100_TOG_CG_MASK) -/* CCGR101 Bit Fields */ -#define CCM_CCGR101_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR101_CG_SHIFT 0 -#define CCM_CCGR101_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR101_CG_SHIFT))&CCM_CCGR101_CG_MASK) -/* CCGR101_SET Bit Fields */ -#define CCM_CCGR101_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR101_SET_CG_SHIFT 0 -#define CCM_CCGR101_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR101_SET_CG_SHIFT))&CCM_CCGR101_SET_CG_MASK) -/* CCGR101_CLR Bit Fields */ -#define CCM_CCGR101_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR101_CLR_CG_SHIFT 0 -#define CCM_CCGR101_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR101_CLR_CG_SHIFT))&CCM_CCGR101_CLR_CG_MASK) -/* CCGR101_TOG Bit Fields */ -#define CCM_CCGR101_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR101_TOG_CG_SHIFT 0 -#define CCM_CCGR101_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR101_TOG_CG_SHIFT))&CCM_CCGR101_TOG_CG_MASK) -/* CCGR102 Bit Fields */ -#define CCM_CCGR102_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR102_CG_SHIFT 0 -#define CCM_CCGR102_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR102_CG_SHIFT))&CCM_CCGR102_CG_MASK) -/* CCGR102_SET Bit Fields */ -#define CCM_CCGR102_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR102_SET_CG_SHIFT 0 -#define CCM_CCGR102_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR102_SET_CG_SHIFT))&CCM_CCGR102_SET_CG_MASK) -/* CCGR102_CLR Bit Fields */ -#define CCM_CCGR102_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR102_CLR_CG_SHIFT 0 -#define CCM_CCGR102_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR102_CLR_CG_SHIFT))&CCM_CCGR102_CLR_CG_MASK) -/* CCGR102_TOG Bit Fields */ -#define CCM_CCGR102_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR102_TOG_CG_SHIFT 0 -#define CCM_CCGR102_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR102_TOG_CG_SHIFT))&CCM_CCGR102_TOG_CG_MASK) -/* CCGR103 Bit Fields */ -#define CCM_CCGR103_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR103_CG_SHIFT 0 -#define CCM_CCGR103_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR103_CG_SHIFT))&CCM_CCGR103_CG_MASK) -/* CCGR103_SET Bit Fields */ -#define CCM_CCGR103_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR103_SET_CG_SHIFT 0 -#define CCM_CCGR103_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR103_SET_CG_SHIFT))&CCM_CCGR103_SET_CG_MASK) -/* CCGR103_CLR Bit Fields */ -#define CCM_CCGR103_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR103_CLR_CG_SHIFT 0 -#define CCM_CCGR103_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR103_CLR_CG_SHIFT))&CCM_CCGR103_CLR_CG_MASK) -/* CCGR103_TOG Bit Fields */ -#define CCM_CCGR103_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR103_TOG_CG_SHIFT 0 -#define CCM_CCGR103_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR103_TOG_CG_SHIFT))&CCM_CCGR103_TOG_CG_MASK) -/* CCGR104 Bit Fields */ -#define CCM_CCGR104_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR104_CG_SHIFT 0 -#define CCM_CCGR104_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR104_CG_SHIFT))&CCM_CCGR104_CG_MASK) -/* CCGR104_SET Bit Fields */ -#define CCM_CCGR104_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR104_SET_CG_SHIFT 0 -#define CCM_CCGR104_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR104_SET_CG_SHIFT))&CCM_CCGR104_SET_CG_MASK) -/* CCGR104_CLR Bit Fields */ -#define CCM_CCGR104_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR104_CLR_CG_SHIFT 0 -#define CCM_CCGR104_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR104_CLR_CG_SHIFT))&CCM_CCGR104_CLR_CG_MASK) -/* CCGR104_TOG Bit Fields */ -#define CCM_CCGR104_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR104_TOG_CG_SHIFT 0 -#define CCM_CCGR104_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR104_TOG_CG_SHIFT))&CCM_CCGR104_TOG_CG_MASK) -/* CCGR105 Bit Fields */ -#define CCM_CCGR105_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR105_CG_SHIFT 0 -#define CCM_CCGR105_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR105_CG_SHIFT))&CCM_CCGR105_CG_MASK) -/* CCGR105_SET Bit Fields */ -#define CCM_CCGR105_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR105_SET_CG_SHIFT 0 -#define CCM_CCGR105_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR105_SET_CG_SHIFT))&CCM_CCGR105_SET_CG_MASK) -/* CCGR105_CLR Bit Fields */ -#define CCM_CCGR105_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR105_CLR_CG_SHIFT 0 -#define CCM_CCGR105_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR105_CLR_CG_SHIFT))&CCM_CCGR105_CLR_CG_MASK) -/* CCGR105_TOG Bit Fields */ -#define CCM_CCGR105_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR105_TOG_CG_SHIFT 0 -#define CCM_CCGR105_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR105_TOG_CG_SHIFT))&CCM_CCGR105_TOG_CG_MASK) -/* CCGR106 Bit Fields */ -#define CCM_CCGR106_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR106_CG_SHIFT 0 -#define CCM_CCGR106_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR106_CG_SHIFT))&CCM_CCGR106_CG_MASK) -/* CCGR106_SET Bit Fields */ -#define CCM_CCGR106_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR106_SET_CG_SHIFT 0 -#define CCM_CCGR106_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR106_SET_CG_SHIFT))&CCM_CCGR106_SET_CG_MASK) -/* CCGR106_CLR Bit Fields */ -#define CCM_CCGR106_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR106_CLR_CG_SHIFT 0 -#define CCM_CCGR106_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR106_CLR_CG_SHIFT))&CCM_CCGR106_CLR_CG_MASK) -/* CCGR106_TOG Bit Fields */ -#define CCM_CCGR106_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR106_TOG_CG_SHIFT 0 -#define CCM_CCGR106_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR106_TOG_CG_SHIFT))&CCM_CCGR106_TOG_CG_MASK) -/* CCGR107 Bit Fields */ -#define CCM_CCGR107_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR107_CG_SHIFT 0 -#define CCM_CCGR107_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR107_CG_SHIFT))&CCM_CCGR107_CG_MASK) -/* CCGR107_SET Bit Fields */ -#define CCM_CCGR107_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR107_SET_CG_SHIFT 0 -#define CCM_CCGR107_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR107_SET_CG_SHIFT))&CCM_CCGR107_SET_CG_MASK) -/* CCGR107_CLR Bit Fields */ -#define CCM_CCGR107_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR107_CLR_CG_SHIFT 0 -#define CCM_CCGR107_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR107_CLR_CG_SHIFT))&CCM_CCGR107_CLR_CG_MASK) -/* CCGR107_TOG Bit Fields */ -#define CCM_CCGR107_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR107_TOG_CG_SHIFT 0 -#define CCM_CCGR107_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR107_TOG_CG_SHIFT))&CCM_CCGR107_TOG_CG_MASK) -/* CCGR108 Bit Fields */ -#define CCM_CCGR108_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR108_CG_SHIFT 0 -#define CCM_CCGR108_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR108_CG_SHIFT))&CCM_CCGR108_CG_MASK) -/* CCGR108_SET Bit Fields */ -#define CCM_CCGR108_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR108_SET_CG_SHIFT 0 -#define CCM_CCGR108_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR108_SET_CG_SHIFT))&CCM_CCGR108_SET_CG_MASK) -/* CCGR108_CLR Bit Fields */ -#define CCM_CCGR108_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR108_CLR_CG_SHIFT 0 -#define CCM_CCGR108_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR108_CLR_CG_SHIFT))&CCM_CCGR108_CLR_CG_MASK) -/* CCGR108_TOG Bit Fields */ -#define CCM_CCGR108_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR108_TOG_CG_SHIFT 0 -#define CCM_CCGR108_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR108_TOG_CG_SHIFT))&CCM_CCGR108_TOG_CG_MASK) -/* CCGR109 Bit Fields */ -#define CCM_CCGR109_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR109_CG_SHIFT 0 -#define CCM_CCGR109_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR109_CG_SHIFT))&CCM_CCGR109_CG_MASK) -/* CCGR109_SET Bit Fields */ -#define CCM_CCGR109_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR109_SET_CG_SHIFT 0 -#define CCM_CCGR109_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR109_SET_CG_SHIFT))&CCM_CCGR109_SET_CG_MASK) -/* CCGR109_CLR Bit Fields */ -#define CCM_CCGR109_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR109_CLR_CG_SHIFT 0 -#define CCM_CCGR109_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR109_CLR_CG_SHIFT))&CCM_CCGR109_CLR_CG_MASK) -/* CCGR109_TOG Bit Fields */ -#define CCM_CCGR109_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR109_TOG_CG_SHIFT 0 -#define CCM_CCGR109_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR109_TOG_CG_SHIFT))&CCM_CCGR109_TOG_CG_MASK) -/* CCGR110 Bit Fields */ -#define CCM_CCGR110_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR110_CG_SHIFT 0 -#define CCM_CCGR110_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR110_CG_SHIFT))&CCM_CCGR110_CG_MASK) -/* CCGR110_SET Bit Fields */ -#define CCM_CCGR110_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR110_SET_CG_SHIFT 0 -#define CCM_CCGR110_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR110_SET_CG_SHIFT))&CCM_CCGR110_SET_CG_MASK) -/* CCGR110_CLR Bit Fields */ -#define CCM_CCGR110_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR110_CLR_CG_SHIFT 0 -#define CCM_CCGR110_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR110_CLR_CG_SHIFT))&CCM_CCGR110_CLR_CG_MASK) -/* CCGR110_TOG Bit Fields */ -#define CCM_CCGR110_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR110_TOG_CG_SHIFT 0 -#define CCM_CCGR110_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR110_TOG_CG_SHIFT))&CCM_CCGR110_TOG_CG_MASK) -/* CCGR111 Bit Fields */ -#define CCM_CCGR111_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR111_CG_SHIFT 0 -#define CCM_CCGR111_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR111_CG_SHIFT))&CCM_CCGR111_CG_MASK) -/* CCGR111_SET Bit Fields */ -#define CCM_CCGR111_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR111_SET_CG_SHIFT 0 -#define CCM_CCGR111_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR111_SET_CG_SHIFT))&CCM_CCGR111_SET_CG_MASK) -/* CCGR111_CLR Bit Fields */ -#define CCM_CCGR111_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR111_CLR_CG_SHIFT 0 -#define CCM_CCGR111_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR111_CLR_CG_SHIFT))&CCM_CCGR111_CLR_CG_MASK) -/* CCGR111_TOG Bit Fields */ -#define CCM_CCGR111_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR111_TOG_CG_SHIFT 0 -#define CCM_CCGR111_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR111_TOG_CG_SHIFT))&CCM_CCGR111_TOG_CG_MASK) -/* CCGR112 Bit Fields */ -#define CCM_CCGR112_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR112_CG_SHIFT 0 -#define CCM_CCGR112_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR112_CG_SHIFT))&CCM_CCGR112_CG_MASK) -/* CCGR112_SET Bit Fields */ -#define CCM_CCGR112_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR112_SET_CG_SHIFT 0 -#define CCM_CCGR112_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR112_SET_CG_SHIFT))&CCM_CCGR112_SET_CG_MASK) -/* CCGR112_CLR Bit Fields */ -#define CCM_CCGR112_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR112_CLR_CG_SHIFT 0 -#define CCM_CCGR112_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR112_CLR_CG_SHIFT))&CCM_CCGR112_CLR_CG_MASK) -/* CCGR112_TOG Bit Fields */ -#define CCM_CCGR112_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR112_TOG_CG_SHIFT 0 -#define CCM_CCGR112_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR112_TOG_CG_SHIFT))&CCM_CCGR112_TOG_CG_MASK) -/* CCGR113 Bit Fields */ -#define CCM_CCGR113_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR113_CG_SHIFT 0 -#define CCM_CCGR113_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR113_CG_SHIFT))&CCM_CCGR113_CG_MASK) -/* CCGR113_SET Bit Fields */ -#define CCM_CCGR113_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR113_SET_CG_SHIFT 0 -#define CCM_CCGR113_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR113_SET_CG_SHIFT))&CCM_CCGR113_SET_CG_MASK) -/* CCGR113_CLR Bit Fields */ -#define CCM_CCGR113_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR113_CLR_CG_SHIFT 0 -#define CCM_CCGR113_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR113_CLR_CG_SHIFT))&CCM_CCGR113_CLR_CG_MASK) -/* CCGR113_TOG Bit Fields */ -#define CCM_CCGR113_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR113_TOG_CG_SHIFT 0 -#define CCM_CCGR113_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR113_TOG_CG_SHIFT))&CCM_CCGR113_TOG_CG_MASK) -/* CCGR114 Bit Fields */ -#define CCM_CCGR114_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR114_CG_SHIFT 0 -#define CCM_CCGR114_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR114_CG_SHIFT))&CCM_CCGR114_CG_MASK) -/* CCGR114_SET Bit Fields */ -#define CCM_CCGR114_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR114_SET_CG_SHIFT 0 -#define CCM_CCGR114_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR114_SET_CG_SHIFT))&CCM_CCGR114_SET_CG_MASK) -/* CCGR114_CLR Bit Fields */ -#define CCM_CCGR114_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR114_CLR_CG_SHIFT 0 -#define CCM_CCGR114_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR114_CLR_CG_SHIFT))&CCM_CCGR114_CLR_CG_MASK) -/* CCGR114_TOG Bit Fields */ -#define CCM_CCGR114_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR114_TOG_CG_SHIFT 0 -#define CCM_CCGR114_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR114_TOG_CG_SHIFT))&CCM_CCGR114_TOG_CG_MASK) -/* CCGR115 Bit Fields */ -#define CCM_CCGR115_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR115_CG_SHIFT 0 -#define CCM_CCGR115_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR115_CG_SHIFT))&CCM_CCGR115_CG_MASK) -/* CCGR115_SET Bit Fields */ -#define CCM_CCGR115_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR115_SET_CG_SHIFT 0 -#define CCM_CCGR115_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR115_SET_CG_SHIFT))&CCM_CCGR115_SET_CG_MASK) -/* CCGR115_CLR Bit Fields */ -#define CCM_CCGR115_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR115_CLR_CG_SHIFT 0 -#define CCM_CCGR115_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR115_CLR_CG_SHIFT))&CCM_CCGR115_CLR_CG_MASK) -/* CCGR115_TOG Bit Fields */ -#define CCM_CCGR115_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR115_TOG_CG_SHIFT 0 -#define CCM_CCGR115_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR115_TOG_CG_SHIFT))&CCM_CCGR115_TOG_CG_MASK) -/* CCGR116 Bit Fields */ -#define CCM_CCGR116_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR116_CG_SHIFT 0 -#define CCM_CCGR116_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR116_CG_SHIFT))&CCM_CCGR116_CG_MASK) -/* CCGR116_SET Bit Fields */ -#define CCM_CCGR116_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR116_SET_CG_SHIFT 0 -#define CCM_CCGR116_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR116_SET_CG_SHIFT))&CCM_CCGR116_SET_CG_MASK) -/* CCGR116_CLR Bit Fields */ -#define CCM_CCGR116_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR116_CLR_CG_SHIFT 0 -#define CCM_CCGR116_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR116_CLR_CG_SHIFT))&CCM_CCGR116_CLR_CG_MASK) -/* CCGR116_TOG Bit Fields */ -#define CCM_CCGR116_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR116_TOG_CG_SHIFT 0 -#define CCM_CCGR116_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR116_TOG_CG_SHIFT))&CCM_CCGR116_TOG_CG_MASK) -/* CCGR117 Bit Fields */ -#define CCM_CCGR117_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR117_CG_SHIFT 0 -#define CCM_CCGR117_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR117_CG_SHIFT))&CCM_CCGR117_CG_MASK) -/* CCGR117_SET Bit Fields */ -#define CCM_CCGR117_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR117_SET_CG_SHIFT 0 -#define CCM_CCGR117_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR117_SET_CG_SHIFT))&CCM_CCGR117_SET_CG_MASK) -/* CCGR117_CLR Bit Fields */ -#define CCM_CCGR117_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR117_CLR_CG_SHIFT 0 -#define CCM_CCGR117_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR117_CLR_CG_SHIFT))&CCM_CCGR117_CLR_CG_MASK) -/* CCGR117_TOG Bit Fields */ -#define CCM_CCGR117_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR117_TOG_CG_SHIFT 0 -#define CCM_CCGR117_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR117_TOG_CG_SHIFT))&CCM_CCGR117_TOG_CG_MASK) -/* CCGR118 Bit Fields */ -#define CCM_CCGR118_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR118_CG_SHIFT 0 -#define CCM_CCGR118_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR118_CG_SHIFT))&CCM_CCGR118_CG_MASK) -/* CCGR118_SET Bit Fields */ -#define CCM_CCGR118_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR118_SET_CG_SHIFT 0 -#define CCM_CCGR118_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR118_SET_CG_SHIFT))&CCM_CCGR118_SET_CG_MASK) -/* CCGR118_CLR Bit Fields */ -#define CCM_CCGR118_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR118_CLR_CG_SHIFT 0 -#define CCM_CCGR118_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR118_CLR_CG_SHIFT))&CCM_CCGR118_CLR_CG_MASK) -/* CCGR118_TOG Bit Fields */ -#define CCM_CCGR118_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR118_TOG_CG_SHIFT 0 -#define CCM_CCGR118_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR118_TOG_CG_SHIFT))&CCM_CCGR118_TOG_CG_MASK) -/* CCGR119 Bit Fields */ -#define CCM_CCGR119_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR119_CG_SHIFT 0 -#define CCM_CCGR119_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR119_CG_SHIFT))&CCM_CCGR119_CG_MASK) -/* CCGR119_SET Bit Fields */ -#define CCM_CCGR119_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR119_SET_CG_SHIFT 0 -#define CCM_CCGR119_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR119_SET_CG_SHIFT))&CCM_CCGR119_SET_CG_MASK) -/* CCGR119_CLR Bit Fields */ -#define CCM_CCGR119_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR119_CLR_CG_SHIFT 0 -#define CCM_CCGR119_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR119_CLR_CG_SHIFT))&CCM_CCGR119_CLR_CG_MASK) -/* CCGR119_TOG Bit Fields */ -#define CCM_CCGR119_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR119_TOG_CG_SHIFT 0 -#define CCM_CCGR119_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR119_TOG_CG_SHIFT))&CCM_CCGR119_TOG_CG_MASK) -/* CCGR120 Bit Fields */ -#define CCM_CCGR120_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR120_CG_SHIFT 0 -#define CCM_CCGR120_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR120_CG_SHIFT))&CCM_CCGR120_CG_MASK) -/* CCGR120_SET Bit Fields */ -#define CCM_CCGR120_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR120_SET_CG_SHIFT 0 -#define CCM_CCGR120_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR120_SET_CG_SHIFT))&CCM_CCGR120_SET_CG_MASK) -/* CCGR120_CLR Bit Fields */ -#define CCM_CCGR120_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR120_CLR_CG_SHIFT 0 -#define CCM_CCGR120_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR120_CLR_CG_SHIFT))&CCM_CCGR120_CLR_CG_MASK) -/* CCGR120_TOG Bit Fields */ -#define CCM_CCGR120_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR120_TOG_CG_SHIFT 0 -#define CCM_CCGR120_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR120_TOG_CG_SHIFT))&CCM_CCGR120_TOG_CG_MASK) -/* CCGR121 Bit Fields */ -#define CCM_CCGR121_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR121_CG_SHIFT 0 -#define CCM_CCGR121_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR121_CG_SHIFT))&CCM_CCGR121_CG_MASK) -/* CCGR121_SET Bit Fields */ -#define CCM_CCGR121_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR121_SET_CG_SHIFT 0 -#define CCM_CCGR121_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR121_SET_CG_SHIFT))&CCM_CCGR121_SET_CG_MASK) -/* CCGR121_CLR Bit Fields */ -#define CCM_CCGR121_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR121_CLR_CG_SHIFT 0 -#define CCM_CCGR121_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR121_CLR_CG_SHIFT))&CCM_CCGR121_CLR_CG_MASK) -/* CCGR121_TOG Bit Fields */ -#define CCM_CCGR121_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR121_TOG_CG_SHIFT 0 -#define CCM_CCGR121_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR121_TOG_CG_SHIFT))&CCM_CCGR121_TOG_CG_MASK) -/* CCGR122 Bit Fields */ -#define CCM_CCGR122_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR122_CG_SHIFT 0 -#define CCM_CCGR122_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR122_CG_SHIFT))&CCM_CCGR122_CG_MASK) -/* CCGR122_SET Bit Fields */ -#define CCM_CCGR122_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR122_SET_CG_SHIFT 0 -#define CCM_CCGR122_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR122_SET_CG_SHIFT))&CCM_CCGR122_SET_CG_MASK) -/* CCGR122_CLR Bit Fields */ -#define CCM_CCGR122_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR122_CLR_CG_SHIFT 0 -#define CCM_CCGR122_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR122_CLR_CG_SHIFT))&CCM_CCGR122_CLR_CG_MASK) -/* CCGR122_TOG Bit Fields */ -#define CCM_CCGR122_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR122_TOG_CG_SHIFT 0 -#define CCM_CCGR122_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR122_TOG_CG_SHIFT))&CCM_CCGR122_TOG_CG_MASK) -/* CCGR123 Bit Fields */ -#define CCM_CCGR123_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR123_CG_SHIFT 0 -#define CCM_CCGR123_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR123_CG_SHIFT))&CCM_CCGR123_CG_MASK) -/* CCGR123_SET Bit Fields */ -#define CCM_CCGR123_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR123_SET_CG_SHIFT 0 -#define CCM_CCGR123_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR123_SET_CG_SHIFT))&CCM_CCGR123_SET_CG_MASK) -/* CCGR123_CLR Bit Fields */ -#define CCM_CCGR123_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR123_CLR_CG_SHIFT 0 -#define CCM_CCGR123_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR123_CLR_CG_SHIFT))&CCM_CCGR123_CLR_CG_MASK) -/* CCGR123_TOG Bit Fields */ -#define CCM_CCGR123_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR123_TOG_CG_SHIFT 0 -#define CCM_CCGR123_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR123_TOG_CG_SHIFT))&CCM_CCGR123_TOG_CG_MASK) -/* CCGR124 Bit Fields */ -#define CCM_CCGR124_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR124_CG_SHIFT 0 -#define CCM_CCGR124_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR124_CG_SHIFT))&CCM_CCGR124_CG_MASK) -/* CCGR124_SET Bit Fields */ -#define CCM_CCGR124_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR124_SET_CG_SHIFT 0 -#define CCM_CCGR124_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR124_SET_CG_SHIFT))&CCM_CCGR124_SET_CG_MASK) -/* CCGR124_CLR Bit Fields */ -#define CCM_CCGR124_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR124_CLR_CG_SHIFT 0 -#define CCM_CCGR124_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR124_CLR_CG_SHIFT))&CCM_CCGR124_CLR_CG_MASK) -/* CCGR124_TOG Bit Fields */ -#define CCM_CCGR124_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR124_TOG_CG_SHIFT 0 -#define CCM_CCGR124_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR124_TOG_CG_SHIFT))&CCM_CCGR124_TOG_CG_MASK) -/* CCGR125 Bit Fields */ -#define CCM_CCGR125_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR125_CG_SHIFT 0 -#define CCM_CCGR125_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR125_CG_SHIFT))&CCM_CCGR125_CG_MASK) -/* CCGR125_SET Bit Fields */ -#define CCM_CCGR125_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR125_SET_CG_SHIFT 0 -#define CCM_CCGR125_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR125_SET_CG_SHIFT))&CCM_CCGR125_SET_CG_MASK) -/* CCGR125_CLR Bit Fields */ -#define CCM_CCGR125_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR125_CLR_CG_SHIFT 0 -#define CCM_CCGR125_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR125_CLR_CG_SHIFT))&CCM_CCGR125_CLR_CG_MASK) -/* CCGR125_TOG Bit Fields */ -#define CCM_CCGR125_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR125_TOG_CG_SHIFT 0 -#define CCM_CCGR125_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR125_TOG_CG_SHIFT))&CCM_CCGR125_TOG_CG_MASK) -/* CCGR126 Bit Fields */ -#define CCM_CCGR126_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR126_CG_SHIFT 0 -#define CCM_CCGR126_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR126_CG_SHIFT))&CCM_CCGR126_CG_MASK) -/* CCGR126_SET Bit Fields */ -#define CCM_CCGR126_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR126_SET_CG_SHIFT 0 -#define CCM_CCGR126_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR126_SET_CG_SHIFT))&CCM_CCGR126_SET_CG_MASK) -/* CCGR126_CLR Bit Fields */ -#define CCM_CCGR126_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR126_CLR_CG_SHIFT 0 -#define CCM_CCGR126_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR126_CLR_CG_SHIFT))&CCM_CCGR126_CLR_CG_MASK) -/* CCGR126_TOG Bit Fields */ -#define CCM_CCGR126_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR126_TOG_CG_SHIFT 0 -#define CCM_CCGR126_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR126_TOG_CG_SHIFT))&CCM_CCGR126_TOG_CG_MASK) -/* CCGR127 Bit Fields */ -#define CCM_CCGR127_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR127_CG_SHIFT 0 -#define CCM_CCGR127_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR127_CG_SHIFT))&CCM_CCGR127_CG_MASK) -/* CCGR127_SET Bit Fields */ -#define CCM_CCGR127_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR127_SET_CG_SHIFT 0 -#define CCM_CCGR127_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR127_SET_CG_SHIFT))&CCM_CCGR127_SET_CG_MASK) -/* CCGR127_CLR Bit Fields */ -#define CCM_CCGR127_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR127_CLR_CG_SHIFT 0 -#define CCM_CCGR127_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR127_CLR_CG_SHIFT))&CCM_CCGR127_CLR_CG_MASK) -/* CCGR127_TOG Bit Fields */ -#define CCM_CCGR127_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR127_TOG_CG_SHIFT 0 -#define CCM_CCGR127_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR127_TOG_CG_SHIFT))&CCM_CCGR127_TOG_CG_MASK) -/* CCGR128 Bit Fields */ -#define CCM_CCGR128_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR128_CG_SHIFT 0 -#define CCM_CCGR128_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR128_CG_SHIFT))&CCM_CCGR128_CG_MASK) -/* CCGR128_SET Bit Fields */ -#define CCM_CCGR128_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR128_SET_CG_SHIFT 0 -#define CCM_CCGR128_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR128_SET_CG_SHIFT))&CCM_CCGR128_SET_CG_MASK) -/* CCGR128_CLR Bit Fields */ -#define CCM_CCGR128_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR128_CLR_CG_SHIFT 0 -#define CCM_CCGR128_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR128_CLR_CG_SHIFT))&CCM_CCGR128_CLR_CG_MASK) -/* CCGR128_TOG Bit Fields */ -#define CCM_CCGR128_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR128_TOG_CG_SHIFT 0 -#define CCM_CCGR128_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR128_TOG_CG_SHIFT))&CCM_CCGR128_TOG_CG_MASK) -/* CCGR129 Bit Fields */ -#define CCM_CCGR129_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR129_CG_SHIFT 0 -#define CCM_CCGR129_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR129_CG_SHIFT))&CCM_CCGR129_CG_MASK) -/* CCGR129_SET Bit Fields */ -#define CCM_CCGR129_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR129_SET_CG_SHIFT 0 -#define CCM_CCGR129_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR129_SET_CG_SHIFT))&CCM_CCGR129_SET_CG_MASK) -/* CCGR129_CLR Bit Fields */ -#define CCM_CCGR129_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR129_CLR_CG_SHIFT 0 -#define CCM_CCGR129_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR129_CLR_CG_SHIFT))&CCM_CCGR129_CLR_CG_MASK) -/* CCGR129_TOG Bit Fields */ -#define CCM_CCGR129_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR129_TOG_CG_SHIFT 0 -#define CCM_CCGR129_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR129_TOG_CG_SHIFT))&CCM_CCGR129_TOG_CG_MASK) -/* CCGR130 Bit Fields */ -#define CCM_CCGR130_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR130_CG_SHIFT 0 -#define CCM_CCGR130_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR130_CG_SHIFT))&CCM_CCGR130_CG_MASK) -/* CCGR130_SET Bit Fields */ -#define CCM_CCGR130_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR130_SET_CG_SHIFT 0 -#define CCM_CCGR130_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR130_SET_CG_SHIFT))&CCM_CCGR130_SET_CG_MASK) -/* CCGR130_CLR Bit Fields */ -#define CCM_CCGR130_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR130_CLR_CG_SHIFT 0 -#define CCM_CCGR130_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR130_CLR_CG_SHIFT))&CCM_CCGR130_CLR_CG_MASK) -/* CCGR130_TOG Bit Fields */ -#define CCM_CCGR130_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR130_TOG_CG_SHIFT 0 -#define CCM_CCGR130_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR130_TOG_CG_SHIFT))&CCM_CCGR130_TOG_CG_MASK) -/* CCGR131 Bit Fields */ -#define CCM_CCGR131_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR131_CG_SHIFT 0 -#define CCM_CCGR131_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR131_CG_SHIFT))&CCM_CCGR131_CG_MASK) -/* CCGR131_SET Bit Fields */ -#define CCM_CCGR131_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR131_SET_CG_SHIFT 0 -#define CCM_CCGR131_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR131_SET_CG_SHIFT))&CCM_CCGR131_SET_CG_MASK) -/* CCGR131_CLR Bit Fields */ -#define CCM_CCGR131_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR131_CLR_CG_SHIFT 0 -#define CCM_CCGR131_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR131_CLR_CG_SHIFT))&CCM_CCGR131_CLR_CG_MASK) -/* CCGR131_TOG Bit Fields */ -#define CCM_CCGR131_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR131_TOG_CG_SHIFT 0 -#define CCM_CCGR131_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR131_TOG_CG_SHIFT))&CCM_CCGR131_TOG_CG_MASK) -/* CCGR132 Bit Fields */ -#define CCM_CCGR132_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR132_CG_SHIFT 0 -#define CCM_CCGR132_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR132_CG_SHIFT))&CCM_CCGR132_CG_MASK) -/* CCGR132_SET Bit Fields */ -#define CCM_CCGR132_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR132_SET_CG_SHIFT 0 -#define CCM_CCGR132_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR132_SET_CG_SHIFT))&CCM_CCGR132_SET_CG_MASK) -/* CCGR132_CLR Bit Fields */ -#define CCM_CCGR132_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR132_CLR_CG_SHIFT 0 -#define CCM_CCGR132_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR132_CLR_CG_SHIFT))&CCM_CCGR132_CLR_CG_MASK) -/* CCGR132_TOG Bit Fields */ -#define CCM_CCGR132_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR132_TOG_CG_SHIFT 0 -#define CCM_CCGR132_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR132_TOG_CG_SHIFT))&CCM_CCGR132_TOG_CG_MASK) -/* CCGR133 Bit Fields */ -#define CCM_CCGR133_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR133_CG_SHIFT 0 -#define CCM_CCGR133_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR133_CG_SHIFT))&CCM_CCGR133_CG_MASK) -/* CCGR133_SET Bit Fields */ -#define CCM_CCGR133_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR133_SET_CG_SHIFT 0 -#define CCM_CCGR133_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR133_SET_CG_SHIFT))&CCM_CCGR133_SET_CG_MASK) -/* CCGR133_CLR Bit Fields */ -#define CCM_CCGR133_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR133_CLR_CG_SHIFT 0 -#define CCM_CCGR133_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR133_CLR_CG_SHIFT))&CCM_CCGR133_CLR_CG_MASK) -/* CCGR133_TOG Bit Fields */ -#define CCM_CCGR133_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR133_TOG_CG_SHIFT 0 -#define CCM_CCGR133_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR133_TOG_CG_SHIFT))&CCM_CCGR133_TOG_CG_MASK) -/* CCGR134 Bit Fields */ -#define CCM_CCGR134_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR134_CG_SHIFT 0 -#define CCM_CCGR134_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR134_CG_SHIFT))&CCM_CCGR134_CG_MASK) -/* CCGR134_SET Bit Fields */ -#define CCM_CCGR134_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR134_SET_CG_SHIFT 0 -#define CCM_CCGR134_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR134_SET_CG_SHIFT))&CCM_CCGR134_SET_CG_MASK) -/* CCGR134_CLR Bit Fields */ -#define CCM_CCGR134_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR134_CLR_CG_SHIFT 0 -#define CCM_CCGR134_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR134_CLR_CG_SHIFT))&CCM_CCGR134_CLR_CG_MASK) -/* CCGR134_TOG Bit Fields */ -#define CCM_CCGR134_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR134_TOG_CG_SHIFT 0 -#define CCM_CCGR134_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR134_TOG_CG_SHIFT))&CCM_CCGR134_TOG_CG_MASK) -/* CCGR135 Bit Fields */ -#define CCM_CCGR135_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR135_CG_SHIFT 0 -#define CCM_CCGR135_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR135_CG_SHIFT))&CCM_CCGR135_CG_MASK) -/* CCGR135_SET Bit Fields */ -#define CCM_CCGR135_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR135_SET_CG_SHIFT 0 -#define CCM_CCGR135_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR135_SET_CG_SHIFT))&CCM_CCGR135_SET_CG_MASK) -/* CCGR135_CLR Bit Fields */ -#define CCM_CCGR135_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR135_CLR_CG_SHIFT 0 -#define CCM_CCGR135_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR135_CLR_CG_SHIFT))&CCM_CCGR135_CLR_CG_MASK) -/* CCGR135_TOG Bit Fields */ -#define CCM_CCGR135_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR135_TOG_CG_SHIFT 0 -#define CCM_CCGR135_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR135_TOG_CG_SHIFT))&CCM_CCGR135_TOG_CG_MASK) -/* CCGR136 Bit Fields */ -#define CCM_CCGR136_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR136_CG_SHIFT 0 -#define CCM_CCGR136_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR136_CG_SHIFT))&CCM_CCGR136_CG_MASK) -/* CCGR136_SET Bit Fields */ -#define CCM_CCGR136_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR136_SET_CG_SHIFT 0 -#define CCM_CCGR136_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR136_SET_CG_SHIFT))&CCM_CCGR136_SET_CG_MASK) -/* CCGR136_CLR Bit Fields */ -#define CCM_CCGR136_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR136_CLR_CG_SHIFT 0 -#define CCM_CCGR136_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR136_CLR_CG_SHIFT))&CCM_CCGR136_CLR_CG_MASK) -/* CCGR136_TOG Bit Fields */ -#define CCM_CCGR136_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR136_TOG_CG_SHIFT 0 -#define CCM_CCGR136_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR136_TOG_CG_SHIFT))&CCM_CCGR136_TOG_CG_MASK) -/* CCGR137 Bit Fields */ -#define CCM_CCGR137_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR137_CG_SHIFT 0 -#define CCM_CCGR137_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR137_CG_SHIFT))&CCM_CCGR137_CG_MASK) -/* CCGR137_SET Bit Fields */ -#define CCM_CCGR137_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR137_SET_CG_SHIFT 0 -#define CCM_CCGR137_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR137_SET_CG_SHIFT))&CCM_CCGR137_SET_CG_MASK) -/* CCGR137_CLR Bit Fields */ -#define CCM_CCGR137_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR137_CLR_CG_SHIFT 0 -#define CCM_CCGR137_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR137_CLR_CG_SHIFT))&CCM_CCGR137_CLR_CG_MASK) -/* CCGR137_TOG Bit Fields */ -#define CCM_CCGR137_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR137_TOG_CG_SHIFT 0 -#define CCM_CCGR137_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR137_TOG_CG_SHIFT))&CCM_CCGR137_TOG_CG_MASK) -/* CCGR138 Bit Fields */ -#define CCM_CCGR138_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR138_CG_SHIFT 0 -#define CCM_CCGR138_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR138_CG_SHIFT))&CCM_CCGR138_CG_MASK) -/* CCGR138_SET Bit Fields */ -#define CCM_CCGR138_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR138_SET_CG_SHIFT 0 -#define CCM_CCGR138_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR138_SET_CG_SHIFT))&CCM_CCGR138_SET_CG_MASK) -/* CCGR138_CLR Bit Fields */ -#define CCM_CCGR138_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR138_CLR_CG_SHIFT 0 -#define CCM_CCGR138_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR138_CLR_CG_SHIFT))&CCM_CCGR138_CLR_CG_MASK) -/* CCGR138_TOG Bit Fields */ -#define CCM_CCGR138_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR138_TOG_CG_SHIFT 0 -#define CCM_CCGR138_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR138_TOG_CG_SHIFT))&CCM_CCGR138_TOG_CG_MASK) -/* CCGR139 Bit Fields */ -#define CCM_CCGR139_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR139_CG_SHIFT 0 -#define CCM_CCGR139_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR139_CG_SHIFT))&CCM_CCGR139_CG_MASK) -/* CCGR139_SET Bit Fields */ -#define CCM_CCGR139_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR139_SET_CG_SHIFT 0 -#define CCM_CCGR139_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR139_SET_CG_SHIFT))&CCM_CCGR139_SET_CG_MASK) -/* CCGR139_CLR Bit Fields */ -#define CCM_CCGR139_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR139_CLR_CG_SHIFT 0 -#define CCM_CCGR139_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR139_CLR_CG_SHIFT))&CCM_CCGR139_CLR_CG_MASK) -/* CCGR139_TOG Bit Fields */ -#define CCM_CCGR139_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR139_TOG_CG_SHIFT 0 -#define CCM_CCGR139_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR139_TOG_CG_SHIFT))&CCM_CCGR139_TOG_CG_MASK) -/* CCGR140 Bit Fields */ -#define CCM_CCGR140_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR140_CG_SHIFT 0 -#define CCM_CCGR140_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR140_CG_SHIFT))&CCM_CCGR140_CG_MASK) -/* CCGR140_SET Bit Fields */ -#define CCM_CCGR140_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR140_SET_CG_SHIFT 0 -#define CCM_CCGR140_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR140_SET_CG_SHIFT))&CCM_CCGR140_SET_CG_MASK) -/* CCGR140_CLR Bit Fields */ -#define CCM_CCGR140_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR140_CLR_CG_SHIFT 0 -#define CCM_CCGR140_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR140_CLR_CG_SHIFT))&CCM_CCGR140_CLR_CG_MASK) -/* CCGR140_TOG Bit Fields */ -#define CCM_CCGR140_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR140_TOG_CG_SHIFT 0 -#define CCM_CCGR140_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR140_TOG_CG_SHIFT))&CCM_CCGR140_TOG_CG_MASK) -/* CCGR141 Bit Fields */ -#define CCM_CCGR141_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR141_CG_SHIFT 0 -#define CCM_CCGR141_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR141_CG_SHIFT))&CCM_CCGR141_CG_MASK) -/* CCGR141_SET Bit Fields */ -#define CCM_CCGR141_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR141_SET_CG_SHIFT 0 -#define CCM_CCGR141_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR141_SET_CG_SHIFT))&CCM_CCGR141_SET_CG_MASK) -/* CCGR141_CLR Bit Fields */ -#define CCM_CCGR141_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR141_CLR_CG_SHIFT 0 -#define CCM_CCGR141_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR141_CLR_CG_SHIFT))&CCM_CCGR141_CLR_CG_MASK) -/* CCGR141_TOG Bit Fields */ -#define CCM_CCGR141_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR141_TOG_CG_SHIFT 0 -#define CCM_CCGR141_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR141_TOG_CG_SHIFT))&CCM_CCGR141_TOG_CG_MASK) -/* CCGR142 Bit Fields */ -#define CCM_CCGR142_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR142_CG_SHIFT 0 -#define CCM_CCGR142_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR142_CG_SHIFT))&CCM_CCGR142_CG_MASK) -/* CCGR142_SET Bit Fields */ -#define CCM_CCGR142_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR142_SET_CG_SHIFT 0 -#define CCM_CCGR142_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR142_SET_CG_SHIFT))&CCM_CCGR142_SET_CG_MASK) -/* CCGR142_CLR Bit Fields */ -#define CCM_CCGR142_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR142_CLR_CG_SHIFT 0 -#define CCM_CCGR142_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR142_CLR_CG_SHIFT))&CCM_CCGR142_CLR_CG_MASK) -/* CCGR142_TOG Bit Fields */ -#define CCM_CCGR142_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR142_TOG_CG_SHIFT 0 -#define CCM_CCGR142_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR142_TOG_CG_SHIFT))&CCM_CCGR142_TOG_CG_MASK) -/* CCGR143 Bit Fields */ -#define CCM_CCGR143_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR143_CG_SHIFT 0 -#define CCM_CCGR143_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR143_CG_SHIFT))&CCM_CCGR143_CG_MASK) -/* CCGR143_SET Bit Fields */ -#define CCM_CCGR143_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR143_SET_CG_SHIFT 0 -#define CCM_CCGR143_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR143_SET_CG_SHIFT))&CCM_CCGR143_SET_CG_MASK) -/* CCGR143_CLR Bit Fields */ -#define CCM_CCGR143_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR143_CLR_CG_SHIFT 0 -#define CCM_CCGR143_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR143_CLR_CG_SHIFT))&CCM_CCGR143_CLR_CG_MASK) -/* CCGR143_TOG Bit Fields */ -#define CCM_CCGR143_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR143_TOG_CG_SHIFT 0 -#define CCM_CCGR143_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR143_TOG_CG_SHIFT))&CCM_CCGR143_TOG_CG_MASK) -/* CCGR144 Bit Fields */ -#define CCM_CCGR144_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR144_CG_SHIFT 0 -#define CCM_CCGR144_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR144_CG_SHIFT))&CCM_CCGR144_CG_MASK) -/* CCGR144_SET Bit Fields */ -#define CCM_CCGR144_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR144_SET_CG_SHIFT 0 -#define CCM_CCGR144_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR144_SET_CG_SHIFT))&CCM_CCGR144_SET_CG_MASK) -/* CCGR144_CLR Bit Fields */ -#define CCM_CCGR144_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR144_CLR_CG_SHIFT 0 -#define CCM_CCGR144_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR144_CLR_CG_SHIFT))&CCM_CCGR144_CLR_CG_MASK) -/* CCGR144_TOG Bit Fields */ -#define CCM_CCGR144_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR144_TOG_CG_SHIFT 0 -#define CCM_CCGR144_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR144_TOG_CG_SHIFT))&CCM_CCGR144_TOG_CG_MASK) -/* CCGR145 Bit Fields */ -#define CCM_CCGR145_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR145_CG_SHIFT 0 -#define CCM_CCGR145_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR145_CG_SHIFT))&CCM_CCGR145_CG_MASK) -/* CCGR145_SET Bit Fields */ -#define CCM_CCGR145_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR145_SET_CG_SHIFT 0 -#define CCM_CCGR145_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR145_SET_CG_SHIFT))&CCM_CCGR145_SET_CG_MASK) -/* CCGR145_CLR Bit Fields */ -#define CCM_CCGR145_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR145_CLR_CG_SHIFT 0 -#define CCM_CCGR145_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR145_CLR_CG_SHIFT))&CCM_CCGR145_CLR_CG_MASK) -/* CCGR145_TOG Bit Fields */ -#define CCM_CCGR145_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR145_TOG_CG_SHIFT 0 -#define CCM_CCGR145_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR145_TOG_CG_SHIFT))&CCM_CCGR145_TOG_CG_MASK) -/* CCGR146 Bit Fields */ -#define CCM_CCGR146_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR146_CG_SHIFT 0 -#define CCM_CCGR146_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR146_CG_SHIFT))&CCM_CCGR146_CG_MASK) -/* CCGR146_SET Bit Fields */ -#define CCM_CCGR146_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR146_SET_CG_SHIFT 0 -#define CCM_CCGR146_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR146_SET_CG_SHIFT))&CCM_CCGR146_SET_CG_MASK) -/* CCGR146_CLR Bit Fields */ -#define CCM_CCGR146_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR146_CLR_CG_SHIFT 0 -#define CCM_CCGR146_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR146_CLR_CG_SHIFT))&CCM_CCGR146_CLR_CG_MASK) -/* CCGR146_TOG Bit Fields */ -#define CCM_CCGR146_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR146_TOG_CG_SHIFT 0 -#define CCM_CCGR146_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR146_TOG_CG_SHIFT))&CCM_CCGR146_TOG_CG_MASK) -/* CCGR147 Bit Fields */ -#define CCM_CCGR147_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR147_CG_SHIFT 0 -#define CCM_CCGR147_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR147_CG_SHIFT))&CCM_CCGR147_CG_MASK) -/* CCGR147_SET Bit Fields */ -#define CCM_CCGR147_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR147_SET_CG_SHIFT 0 -#define CCM_CCGR147_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR147_SET_CG_SHIFT))&CCM_CCGR147_SET_CG_MASK) -/* CCGR147_CLR Bit Fields */ -#define CCM_CCGR147_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR147_CLR_CG_SHIFT 0 -#define CCM_CCGR147_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR147_CLR_CG_SHIFT))&CCM_CCGR147_CLR_CG_MASK) -/* CCGR147_TOG Bit Fields */ -#define CCM_CCGR147_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR147_TOG_CG_SHIFT 0 -#define CCM_CCGR147_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR147_TOG_CG_SHIFT))&CCM_CCGR147_TOG_CG_MASK) -/* CCGR148 Bit Fields */ -#define CCM_CCGR148_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR148_CG_SHIFT 0 -#define CCM_CCGR148_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR148_CG_SHIFT))&CCM_CCGR148_CG_MASK) -/* CCGR148_SET Bit Fields */ -#define CCM_CCGR148_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR148_SET_CG_SHIFT 0 -#define CCM_CCGR148_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR148_SET_CG_SHIFT))&CCM_CCGR148_SET_CG_MASK) -/* CCGR148_CLR Bit Fields */ -#define CCM_CCGR148_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR148_CLR_CG_SHIFT 0 -#define CCM_CCGR148_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR148_CLR_CG_SHIFT))&CCM_CCGR148_CLR_CG_MASK) -/* CCGR148_TOG Bit Fields */ -#define CCM_CCGR148_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR148_TOG_CG_SHIFT 0 -#define CCM_CCGR148_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR148_TOG_CG_SHIFT))&CCM_CCGR148_TOG_CG_MASK) -/* CCGR149 Bit Fields */ -#define CCM_CCGR149_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR149_CG_SHIFT 0 -#define CCM_CCGR149_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR149_CG_SHIFT))&CCM_CCGR149_CG_MASK) -/* CCGR149_SET Bit Fields */ -#define CCM_CCGR149_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR149_SET_CG_SHIFT 0 -#define CCM_CCGR149_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR149_SET_CG_SHIFT))&CCM_CCGR149_SET_CG_MASK) -/* CCGR149_CLR Bit Fields */ -#define CCM_CCGR149_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR149_CLR_CG_SHIFT 0 -#define CCM_CCGR149_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR149_CLR_CG_SHIFT))&CCM_CCGR149_CLR_CG_MASK) -/* CCGR149_TOG Bit Fields */ -#define CCM_CCGR149_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR149_TOG_CG_SHIFT 0 -#define CCM_CCGR149_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR149_TOG_CG_SHIFT))&CCM_CCGR149_TOG_CG_MASK) -/* CCGR150 Bit Fields */ -#define CCM_CCGR150_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR150_CG_SHIFT 0 -#define CCM_CCGR150_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR150_CG_SHIFT))&CCM_CCGR150_CG_MASK) -/* CCGR150_SET Bit Fields */ -#define CCM_CCGR150_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR150_SET_CG_SHIFT 0 -#define CCM_CCGR150_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR150_SET_CG_SHIFT))&CCM_CCGR150_SET_CG_MASK) -/* CCGR150_CLR Bit Fields */ -#define CCM_CCGR150_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR150_CLR_CG_SHIFT 0 -#define CCM_CCGR150_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR150_CLR_CG_SHIFT))&CCM_CCGR150_CLR_CG_MASK) -/* CCGR150_TOG Bit Fields */ -#define CCM_CCGR150_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR150_TOG_CG_SHIFT 0 -#define CCM_CCGR150_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR150_TOG_CG_SHIFT))&CCM_CCGR150_TOG_CG_MASK) -/* CCGR151 Bit Fields */ -#define CCM_CCGR151_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR151_CG_SHIFT 0 -#define CCM_CCGR151_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR151_CG_SHIFT))&CCM_CCGR151_CG_MASK) -/* CCGR151_SET Bit Fields */ -#define CCM_CCGR151_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR151_SET_CG_SHIFT 0 -#define CCM_CCGR151_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR151_SET_CG_SHIFT))&CCM_CCGR151_SET_CG_MASK) -/* CCGR151_CLR Bit Fields */ -#define CCM_CCGR151_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR151_CLR_CG_SHIFT 0 -#define CCM_CCGR151_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR151_CLR_CG_SHIFT))&CCM_CCGR151_CLR_CG_MASK) -/* CCGR151_TOG Bit Fields */ -#define CCM_CCGR151_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR151_TOG_CG_SHIFT 0 -#define CCM_CCGR151_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR151_TOG_CG_SHIFT))&CCM_CCGR151_TOG_CG_MASK) -/* CCGR152 Bit Fields */ -#define CCM_CCGR152_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR152_CG_SHIFT 0 -#define CCM_CCGR152_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR152_CG_SHIFT))&CCM_CCGR152_CG_MASK) -/* CCGR152_SET Bit Fields */ -#define CCM_CCGR152_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR152_SET_CG_SHIFT 0 -#define CCM_CCGR152_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR152_SET_CG_SHIFT))&CCM_CCGR152_SET_CG_MASK) -/* CCGR152_CLR Bit Fields */ -#define CCM_CCGR152_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR152_CLR_CG_SHIFT 0 -#define CCM_CCGR152_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR152_CLR_CG_SHIFT))&CCM_CCGR152_CLR_CG_MASK) -/* CCGR152_TOG Bit Fields */ -#define CCM_CCGR152_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR152_TOG_CG_SHIFT 0 -#define CCM_CCGR152_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR152_TOG_CG_SHIFT))&CCM_CCGR152_TOG_CG_MASK) -/* CCGR153 Bit Fields */ -#define CCM_CCGR153_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR153_CG_SHIFT 0 -#define CCM_CCGR153_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR153_CG_SHIFT))&CCM_CCGR153_CG_MASK) -/* CCGR153_SET Bit Fields */ -#define CCM_CCGR153_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR153_SET_CG_SHIFT 0 -#define CCM_CCGR153_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR153_SET_CG_SHIFT))&CCM_CCGR153_SET_CG_MASK) -/* CCGR153_CLR Bit Fields */ -#define CCM_CCGR153_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR153_CLR_CG_SHIFT 0 -#define CCM_CCGR153_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR153_CLR_CG_SHIFT))&CCM_CCGR153_CLR_CG_MASK) -/* CCGR153_TOG Bit Fields */ -#define CCM_CCGR153_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR153_TOG_CG_SHIFT 0 -#define CCM_CCGR153_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR153_TOG_CG_SHIFT))&CCM_CCGR153_TOG_CG_MASK) -/* CCGR154 Bit Fields */ -#define CCM_CCGR154_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR154_CG_SHIFT 0 -#define CCM_CCGR154_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR154_CG_SHIFT))&CCM_CCGR154_CG_MASK) -/* CCGR154_SET Bit Fields */ -#define CCM_CCGR154_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR154_SET_CG_SHIFT 0 -#define CCM_CCGR154_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR154_SET_CG_SHIFT))&CCM_CCGR154_SET_CG_MASK) -/* CCGR154_CLR Bit Fields */ -#define CCM_CCGR154_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR154_CLR_CG_SHIFT 0 -#define CCM_CCGR154_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR154_CLR_CG_SHIFT))&CCM_CCGR154_CLR_CG_MASK) -/* CCGR154_TOG Bit Fields */ -#define CCM_CCGR154_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR154_TOG_CG_SHIFT 0 -#define CCM_CCGR154_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR154_TOG_CG_SHIFT))&CCM_CCGR154_TOG_CG_MASK) -/* CCGR155 Bit Fields */ -#define CCM_CCGR155_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR155_CG_SHIFT 0 -#define CCM_CCGR155_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR155_CG_SHIFT))&CCM_CCGR155_CG_MASK) -/* CCGR155_SET Bit Fields */ -#define CCM_CCGR155_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR155_SET_CG_SHIFT 0 -#define CCM_CCGR155_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR155_SET_CG_SHIFT))&CCM_CCGR155_SET_CG_MASK) -/* CCGR155_CLR Bit Fields */ -#define CCM_CCGR155_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR155_CLR_CG_SHIFT 0 -#define CCM_CCGR155_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR155_CLR_CG_SHIFT))&CCM_CCGR155_CLR_CG_MASK) -/* CCGR155_TOG Bit Fields */ -#define CCM_CCGR155_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR155_TOG_CG_SHIFT 0 -#define CCM_CCGR155_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR155_TOG_CG_SHIFT))&CCM_CCGR155_TOG_CG_MASK) -/* CCGR156 Bit Fields */ -#define CCM_CCGR156_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR156_CG_SHIFT 0 -#define CCM_CCGR156_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR156_CG_SHIFT))&CCM_CCGR156_CG_MASK) -/* CCGR156_SET Bit Fields */ -#define CCM_CCGR156_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR156_SET_CG_SHIFT 0 -#define CCM_CCGR156_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR156_SET_CG_SHIFT))&CCM_CCGR156_SET_CG_MASK) -/* CCGR156_CLR Bit Fields */ -#define CCM_CCGR156_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR156_CLR_CG_SHIFT 0 -#define CCM_CCGR156_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR156_CLR_CG_SHIFT))&CCM_CCGR156_CLR_CG_MASK) -/* CCGR156_TOG Bit Fields */ -#define CCM_CCGR156_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR156_TOG_CG_SHIFT 0 -#define CCM_CCGR156_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR156_TOG_CG_SHIFT))&CCM_CCGR156_TOG_CG_MASK) -/* CCGR157 Bit Fields */ -#define CCM_CCGR157_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR157_CG_SHIFT 0 -#define CCM_CCGR157_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR157_CG_SHIFT))&CCM_CCGR157_CG_MASK) -/* CCGR157_SET Bit Fields */ -#define CCM_CCGR157_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR157_SET_CG_SHIFT 0 -#define CCM_CCGR157_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR157_SET_CG_SHIFT))&CCM_CCGR157_SET_CG_MASK) -/* CCGR157_CLR Bit Fields */ -#define CCM_CCGR157_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR157_CLR_CG_SHIFT 0 -#define CCM_CCGR157_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR157_CLR_CG_SHIFT))&CCM_CCGR157_CLR_CG_MASK) -/* CCGR157_TOG Bit Fields */ -#define CCM_CCGR157_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR157_TOG_CG_SHIFT 0 -#define CCM_CCGR157_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR157_TOG_CG_SHIFT))&CCM_CCGR157_TOG_CG_MASK) -/* CCGR158 Bit Fields */ -#define CCM_CCGR158_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR158_CG_SHIFT 0 -#define CCM_CCGR158_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR158_CG_SHIFT))&CCM_CCGR158_CG_MASK) -/* CCGR158_SET Bit Fields */ -#define CCM_CCGR158_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR158_SET_CG_SHIFT 0 -#define CCM_CCGR158_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR158_SET_CG_SHIFT))&CCM_CCGR158_SET_CG_MASK) -/* CCGR158_CLR Bit Fields */ -#define CCM_CCGR158_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR158_CLR_CG_SHIFT 0 -#define CCM_CCGR158_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR158_CLR_CG_SHIFT))&CCM_CCGR158_CLR_CG_MASK) -/* CCGR158_TOG Bit Fields */ -#define CCM_CCGR158_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR158_TOG_CG_SHIFT 0 -#define CCM_CCGR158_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR158_TOG_CG_SHIFT))&CCM_CCGR158_TOG_CG_MASK) -/* CCGR159 Bit Fields */ -#define CCM_CCGR159_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR159_CG_SHIFT 0 -#define CCM_CCGR159_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR159_CG_SHIFT))&CCM_CCGR159_CG_MASK) -/* CCGR159_SET Bit Fields */ -#define CCM_CCGR159_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR159_SET_CG_SHIFT 0 -#define CCM_CCGR159_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR159_SET_CG_SHIFT))&CCM_CCGR159_SET_CG_MASK) -/* CCGR159_CLR Bit Fields */ -#define CCM_CCGR159_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR159_CLR_CG_SHIFT 0 -#define CCM_CCGR159_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR159_CLR_CG_SHIFT))&CCM_CCGR159_CLR_CG_MASK) -/* CCGR159_TOG Bit Fields */ -#define CCM_CCGR159_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR159_TOG_CG_SHIFT 0 -#define CCM_CCGR159_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR159_TOG_CG_SHIFT))&CCM_CCGR159_TOG_CG_MASK) -/* CCGR160 Bit Fields */ -#define CCM_CCGR160_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR160_CG_SHIFT 0 -#define CCM_CCGR160_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR160_CG_SHIFT))&CCM_CCGR160_CG_MASK) -/* CCGR160_SET Bit Fields */ -#define CCM_CCGR160_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR160_SET_CG_SHIFT 0 -#define CCM_CCGR160_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR160_SET_CG_SHIFT))&CCM_CCGR160_SET_CG_MASK) -/* CCGR160_CLR Bit Fields */ -#define CCM_CCGR160_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR160_CLR_CG_SHIFT 0 -#define CCM_CCGR160_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR160_CLR_CG_SHIFT))&CCM_CCGR160_CLR_CG_MASK) -/* CCGR160_TOG Bit Fields */ -#define CCM_CCGR160_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR160_TOG_CG_SHIFT 0 -#define CCM_CCGR160_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR160_TOG_CG_SHIFT))&CCM_CCGR160_TOG_CG_MASK) -/* CCGR161 Bit Fields */ -#define CCM_CCGR161_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR161_CG_SHIFT 0 -#define CCM_CCGR161_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR161_CG_SHIFT))&CCM_CCGR161_CG_MASK) -/* CCGR161_SET Bit Fields */ -#define CCM_CCGR161_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR161_SET_CG_SHIFT 0 -#define CCM_CCGR161_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR161_SET_CG_SHIFT))&CCM_CCGR161_SET_CG_MASK) -/* CCGR161_CLR Bit Fields */ -#define CCM_CCGR161_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR161_CLR_CG_SHIFT 0 -#define CCM_CCGR161_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR161_CLR_CG_SHIFT))&CCM_CCGR161_CLR_CG_MASK) -/* CCGR161_TOG Bit Fields */ -#define CCM_CCGR161_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR161_TOG_CG_SHIFT 0 -#define CCM_CCGR161_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR161_TOG_CG_SHIFT))&CCM_CCGR161_TOG_CG_MASK) -/* CCGR162 Bit Fields */ -#define CCM_CCGR162_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR162_CG_SHIFT 0 -#define CCM_CCGR162_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR162_CG_SHIFT))&CCM_CCGR162_CG_MASK) -/* CCGR162_SET Bit Fields */ -#define CCM_CCGR162_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR162_SET_CG_SHIFT 0 -#define CCM_CCGR162_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR162_SET_CG_SHIFT))&CCM_CCGR162_SET_CG_MASK) -/* CCGR162_CLR Bit Fields */ -#define CCM_CCGR162_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR162_CLR_CG_SHIFT 0 -#define CCM_CCGR162_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR162_CLR_CG_SHIFT))&CCM_CCGR162_CLR_CG_MASK) -/* CCGR162_TOG Bit Fields */ -#define CCM_CCGR162_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR162_TOG_CG_SHIFT 0 -#define CCM_CCGR162_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR162_TOG_CG_SHIFT))&CCM_CCGR162_TOG_CG_MASK) -/* CCGR163 Bit Fields */ -#define CCM_CCGR163_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR163_CG_SHIFT 0 -#define CCM_CCGR163_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR163_CG_SHIFT))&CCM_CCGR163_CG_MASK) -/* CCGR163_SET Bit Fields */ -#define CCM_CCGR163_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR163_SET_CG_SHIFT 0 -#define CCM_CCGR163_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR163_SET_CG_SHIFT))&CCM_CCGR163_SET_CG_MASK) -/* CCGR163_CLR Bit Fields */ -#define CCM_CCGR163_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR163_CLR_CG_SHIFT 0 -#define CCM_CCGR163_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR163_CLR_CG_SHIFT))&CCM_CCGR163_CLR_CG_MASK) -/* CCGR163_TOG Bit Fields */ -#define CCM_CCGR163_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR163_TOG_CG_SHIFT 0 -#define CCM_CCGR163_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR163_TOG_CG_SHIFT))&CCM_CCGR163_TOG_CG_MASK) -/* CCGR164 Bit Fields */ -#define CCM_CCGR164_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR164_CG_SHIFT 0 -#define CCM_CCGR164_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR164_CG_SHIFT))&CCM_CCGR164_CG_MASK) -/* CCGR164_SET Bit Fields */ -#define CCM_CCGR164_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR164_SET_CG_SHIFT 0 -#define CCM_CCGR164_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR164_SET_CG_SHIFT))&CCM_CCGR164_SET_CG_MASK) -/* CCGR164_CLR Bit Fields */ -#define CCM_CCGR164_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR164_CLR_CG_SHIFT 0 -#define CCM_CCGR164_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR164_CLR_CG_SHIFT))&CCM_CCGR164_CLR_CG_MASK) -/* CCGR164_TOG Bit Fields */ -#define CCM_CCGR164_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR164_TOG_CG_SHIFT 0 -#define CCM_CCGR164_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR164_TOG_CG_SHIFT))&CCM_CCGR164_TOG_CG_MASK) -/* CCGR165 Bit Fields */ -#define CCM_CCGR165_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR165_CG_SHIFT 0 -#define CCM_CCGR165_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR165_CG_SHIFT))&CCM_CCGR165_CG_MASK) -/* CCGR165_SET Bit Fields */ -#define CCM_CCGR165_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR165_SET_CG_SHIFT 0 -#define CCM_CCGR165_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR165_SET_CG_SHIFT))&CCM_CCGR165_SET_CG_MASK) -/* CCGR165_CLR Bit Fields */ -#define CCM_CCGR165_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR165_CLR_CG_SHIFT 0 -#define CCM_CCGR165_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR165_CLR_CG_SHIFT))&CCM_CCGR165_CLR_CG_MASK) -/* CCGR165_TOG Bit Fields */ -#define CCM_CCGR165_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR165_TOG_CG_SHIFT 0 -#define CCM_CCGR165_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR165_TOG_CG_SHIFT))&CCM_CCGR165_TOG_CG_MASK) -/* CCGR166 Bit Fields */ -#define CCM_CCGR166_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR166_CG_SHIFT 0 -#define CCM_CCGR166_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR166_CG_SHIFT))&CCM_CCGR166_CG_MASK) -/* CCGR166_SET Bit Fields */ -#define CCM_CCGR166_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR166_SET_CG_SHIFT 0 -#define CCM_CCGR166_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR166_SET_CG_SHIFT))&CCM_CCGR166_SET_CG_MASK) -/* CCGR166_CLR Bit Fields */ -#define CCM_CCGR166_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR166_CLR_CG_SHIFT 0 -#define CCM_CCGR166_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR166_CLR_CG_SHIFT))&CCM_CCGR166_CLR_CG_MASK) -/* CCGR166_TOG Bit Fields */ -#define CCM_CCGR166_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR166_TOG_CG_SHIFT 0 -#define CCM_CCGR166_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR166_TOG_CG_SHIFT))&CCM_CCGR166_TOG_CG_MASK) -/* CCGR167 Bit Fields */ -#define CCM_CCGR167_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR167_CG_SHIFT 0 -#define CCM_CCGR167_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR167_CG_SHIFT))&CCM_CCGR167_CG_MASK) -/* CCGR167_SET Bit Fields */ -#define CCM_CCGR167_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR167_SET_CG_SHIFT 0 -#define CCM_CCGR167_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR167_SET_CG_SHIFT))&CCM_CCGR167_SET_CG_MASK) -/* CCGR167_CLR Bit Fields */ -#define CCM_CCGR167_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR167_CLR_CG_SHIFT 0 -#define CCM_CCGR167_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR167_CLR_CG_SHIFT))&CCM_CCGR167_CLR_CG_MASK) -/* CCGR167_TOG Bit Fields */ -#define CCM_CCGR167_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR167_TOG_CG_SHIFT 0 -#define CCM_CCGR167_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR167_TOG_CG_SHIFT))&CCM_CCGR167_TOG_CG_MASK) -/* CCGR168 Bit Fields */ -#define CCM_CCGR168_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR168_CG_SHIFT 0 -#define CCM_CCGR168_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR168_CG_SHIFT))&CCM_CCGR168_CG_MASK) -/* CCGR168_SET Bit Fields */ -#define CCM_CCGR168_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR168_SET_CG_SHIFT 0 -#define CCM_CCGR168_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR168_SET_CG_SHIFT))&CCM_CCGR168_SET_CG_MASK) -/* CCGR168_CLR Bit Fields */ -#define CCM_CCGR168_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR168_CLR_CG_SHIFT 0 -#define CCM_CCGR168_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR168_CLR_CG_SHIFT))&CCM_CCGR168_CLR_CG_MASK) -/* CCGR168_TOG Bit Fields */ -#define CCM_CCGR168_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR168_TOG_CG_SHIFT 0 -#define CCM_CCGR168_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR168_TOG_CG_SHIFT))&CCM_CCGR168_TOG_CG_MASK) -/* CCGR169 Bit Fields */ -#define CCM_CCGR169_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR169_CG_SHIFT 0 -#define CCM_CCGR169_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR169_CG_SHIFT))&CCM_CCGR169_CG_MASK) -/* CCGR169_SET Bit Fields */ -#define CCM_CCGR169_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR169_SET_CG_SHIFT 0 -#define CCM_CCGR169_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR169_SET_CG_SHIFT))&CCM_CCGR169_SET_CG_MASK) -/* CCGR169_CLR Bit Fields */ -#define CCM_CCGR169_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR169_CLR_CG_SHIFT 0 -#define CCM_CCGR169_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR169_CLR_CG_SHIFT))&CCM_CCGR169_CLR_CG_MASK) -/* CCGR169_TOG Bit Fields */ -#define CCM_CCGR169_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR169_TOG_CG_SHIFT 0 -#define CCM_CCGR169_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR169_TOG_CG_SHIFT))&CCM_CCGR169_TOG_CG_MASK) -/* CCGR170 Bit Fields */ -#define CCM_CCGR170_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR170_CG_SHIFT 0 -#define CCM_CCGR170_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR170_CG_SHIFT))&CCM_CCGR170_CG_MASK) -/* CCGR170_SET Bit Fields */ -#define CCM_CCGR170_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR170_SET_CG_SHIFT 0 -#define CCM_CCGR170_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR170_SET_CG_SHIFT))&CCM_CCGR170_SET_CG_MASK) -/* CCGR170_CLR Bit Fields */ -#define CCM_CCGR170_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR170_CLR_CG_SHIFT 0 -#define CCM_CCGR170_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR170_CLR_CG_SHIFT))&CCM_CCGR170_CLR_CG_MASK) -/* CCGR170_TOG Bit Fields */ -#define CCM_CCGR170_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR170_TOG_CG_SHIFT 0 -#define CCM_CCGR170_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR170_TOG_CG_SHIFT))&CCM_CCGR170_TOG_CG_MASK) -/* CCGR171 Bit Fields */ -#define CCM_CCGR171_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR171_CG_SHIFT 0 -#define CCM_CCGR171_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR171_CG_SHIFT))&CCM_CCGR171_CG_MASK) -/* CCGR171_SET Bit Fields */ -#define CCM_CCGR171_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR171_SET_CG_SHIFT 0 -#define CCM_CCGR171_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR171_SET_CG_SHIFT))&CCM_CCGR171_SET_CG_MASK) -/* CCGR171_CLR Bit Fields */ -#define CCM_CCGR171_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR171_CLR_CG_SHIFT 0 -#define CCM_CCGR171_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR171_CLR_CG_SHIFT))&CCM_CCGR171_CLR_CG_MASK) -/* CCGR171_TOG Bit Fields */ -#define CCM_CCGR171_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR171_TOG_CG_SHIFT 0 -#define CCM_CCGR171_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR171_TOG_CG_SHIFT))&CCM_CCGR171_TOG_CG_MASK) -/* CCGR172 Bit Fields */ -#define CCM_CCGR172_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR172_CG_SHIFT 0 -#define CCM_CCGR172_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR172_CG_SHIFT))&CCM_CCGR172_CG_MASK) -/* CCGR172_SET Bit Fields */ -#define CCM_CCGR172_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR172_SET_CG_SHIFT 0 -#define CCM_CCGR172_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR172_SET_CG_SHIFT))&CCM_CCGR172_SET_CG_MASK) -/* CCGR172_CLR Bit Fields */ -#define CCM_CCGR172_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR172_CLR_CG_SHIFT 0 -#define CCM_CCGR172_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR172_CLR_CG_SHIFT))&CCM_CCGR172_CLR_CG_MASK) -/* CCGR172_TOG Bit Fields */ -#define CCM_CCGR172_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR172_TOG_CG_SHIFT 0 -#define CCM_CCGR172_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR172_TOG_CG_SHIFT))&CCM_CCGR172_TOG_CG_MASK) -/* CCGR173 Bit Fields */ -#define CCM_CCGR173_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR173_CG_SHIFT 0 -#define CCM_CCGR173_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR173_CG_SHIFT))&CCM_CCGR173_CG_MASK) -/* CCGR173_SET Bit Fields */ -#define CCM_CCGR173_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR173_SET_CG_SHIFT 0 -#define CCM_CCGR173_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR173_SET_CG_SHIFT))&CCM_CCGR173_SET_CG_MASK) -/* CCGR173_CLR Bit Fields */ -#define CCM_CCGR173_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR173_CLR_CG_SHIFT 0 -#define CCM_CCGR173_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR173_CLR_CG_SHIFT))&CCM_CCGR173_CLR_CG_MASK) -/* CCGR173_TOG Bit Fields */ -#define CCM_CCGR173_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR173_TOG_CG_SHIFT 0 -#define CCM_CCGR173_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR173_TOG_CG_SHIFT))&CCM_CCGR173_TOG_CG_MASK) -/* CCGR174 Bit Fields */ -#define CCM_CCGR174_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR174_CG_SHIFT 0 -#define CCM_CCGR174_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR174_CG_SHIFT))&CCM_CCGR174_CG_MASK) -/* CCGR174_SET Bit Fields */ -#define CCM_CCGR174_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR174_SET_CG_SHIFT 0 -#define CCM_CCGR174_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR174_SET_CG_SHIFT))&CCM_CCGR174_SET_CG_MASK) -/* CCGR174_CLR Bit Fields */ -#define CCM_CCGR174_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR174_CLR_CG_SHIFT 0 -#define CCM_CCGR174_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR174_CLR_CG_SHIFT))&CCM_CCGR174_CLR_CG_MASK) -/* CCGR174_TOG Bit Fields */ -#define CCM_CCGR174_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR174_TOG_CG_SHIFT 0 -#define CCM_CCGR174_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR174_TOG_CG_SHIFT))&CCM_CCGR174_TOG_CG_MASK) -/* CCGR175 Bit Fields */ -#define CCM_CCGR175_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR175_CG_SHIFT 0 -#define CCM_CCGR175_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR175_CG_SHIFT))&CCM_CCGR175_CG_MASK) -/* CCGR175_SET Bit Fields */ -#define CCM_CCGR175_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR175_SET_CG_SHIFT 0 -#define CCM_CCGR175_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR175_SET_CG_SHIFT))&CCM_CCGR175_SET_CG_MASK) -/* CCGR175_CLR Bit Fields */ -#define CCM_CCGR175_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR175_CLR_CG_SHIFT 0 -#define CCM_CCGR175_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR175_CLR_CG_SHIFT))&CCM_CCGR175_CLR_CG_MASK) -/* CCGR175_TOG Bit Fields */ -#define CCM_CCGR175_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR175_TOG_CG_SHIFT 0 -#define CCM_CCGR175_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR175_TOG_CG_SHIFT))&CCM_CCGR175_TOG_CG_MASK) -/* CCGR176 Bit Fields */ -#define CCM_CCGR176_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR176_CG_SHIFT 0 -#define CCM_CCGR176_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR176_CG_SHIFT))&CCM_CCGR176_CG_MASK) -/* CCGR176_SET Bit Fields */ -#define CCM_CCGR176_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR176_SET_CG_SHIFT 0 -#define CCM_CCGR176_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR176_SET_CG_SHIFT))&CCM_CCGR176_SET_CG_MASK) -/* CCGR176_CLR Bit Fields */ -#define CCM_CCGR176_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR176_CLR_CG_SHIFT 0 -#define CCM_CCGR176_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR176_CLR_CG_SHIFT))&CCM_CCGR176_CLR_CG_MASK) -/* CCGR176_TOG Bit Fields */ -#define CCM_CCGR176_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR176_TOG_CG_SHIFT 0 -#define CCM_CCGR176_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR176_TOG_CG_SHIFT))&CCM_CCGR176_TOG_CG_MASK) -/* CCGR177 Bit Fields */ -#define CCM_CCGR177_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR177_CG_SHIFT 0 -#define CCM_CCGR177_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR177_CG_SHIFT))&CCM_CCGR177_CG_MASK) -/* CCGR177_SET Bit Fields */ -#define CCM_CCGR177_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR177_SET_CG_SHIFT 0 -#define CCM_CCGR177_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR177_SET_CG_SHIFT))&CCM_CCGR177_SET_CG_MASK) -/* CCGR177_CLR Bit Fields */ -#define CCM_CCGR177_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR177_CLR_CG_SHIFT 0 -#define CCM_CCGR177_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR177_CLR_CG_SHIFT))&CCM_CCGR177_CLR_CG_MASK) -/* CCGR177_TOG Bit Fields */ -#define CCM_CCGR177_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR177_TOG_CG_SHIFT 0 -#define CCM_CCGR177_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR177_TOG_CG_SHIFT))&CCM_CCGR177_TOG_CG_MASK) -/* CCGR178 Bit Fields */ -#define CCM_CCGR178_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR178_CG_SHIFT 0 -#define CCM_CCGR178_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR178_CG_SHIFT))&CCM_CCGR178_CG_MASK) -/* CCGR178_SET Bit Fields */ -#define CCM_CCGR178_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR178_SET_CG_SHIFT 0 -#define CCM_CCGR178_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR178_SET_CG_SHIFT))&CCM_CCGR178_SET_CG_MASK) -/* CCGR178_CLR Bit Fields */ -#define CCM_CCGR178_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR178_CLR_CG_SHIFT 0 -#define CCM_CCGR178_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR178_CLR_CG_SHIFT))&CCM_CCGR178_CLR_CG_MASK) -/* CCGR178_TOG Bit Fields */ -#define CCM_CCGR178_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR178_TOG_CG_SHIFT 0 -#define CCM_CCGR178_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR178_TOG_CG_SHIFT))&CCM_CCGR178_TOG_CG_MASK) -/* CCGR179 Bit Fields */ -#define CCM_CCGR179_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR179_CG_SHIFT 0 -#define CCM_CCGR179_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR179_CG_SHIFT))&CCM_CCGR179_CG_MASK) -/* CCGR179_SET Bit Fields */ -#define CCM_CCGR179_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR179_SET_CG_SHIFT 0 -#define CCM_CCGR179_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR179_SET_CG_SHIFT))&CCM_CCGR179_SET_CG_MASK) -/* CCGR179_CLR Bit Fields */ -#define CCM_CCGR179_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR179_CLR_CG_SHIFT 0 -#define CCM_CCGR179_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR179_CLR_CG_SHIFT))&CCM_CCGR179_CLR_CG_MASK) -/* CCGR179_TOG Bit Fields */ -#define CCM_CCGR179_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR179_TOG_CG_SHIFT 0 -#define CCM_CCGR179_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR179_TOG_CG_SHIFT))&CCM_CCGR179_TOG_CG_MASK) -/* CCGR180 Bit Fields */ -#define CCM_CCGR180_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR180_CG_SHIFT 0 -#define CCM_CCGR180_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR180_CG_SHIFT))&CCM_CCGR180_CG_MASK) -/* CCGR180_SET Bit Fields */ -#define CCM_CCGR180_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR180_SET_CG_SHIFT 0 -#define CCM_CCGR180_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR180_SET_CG_SHIFT))&CCM_CCGR180_SET_CG_MASK) -/* CCGR180_CLR Bit Fields */ -#define CCM_CCGR180_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR180_CLR_CG_SHIFT 0 -#define CCM_CCGR180_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR180_CLR_CG_SHIFT))&CCM_CCGR180_CLR_CG_MASK) -/* CCGR180_TOG Bit Fields */ -#define CCM_CCGR180_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR180_TOG_CG_SHIFT 0 -#define CCM_CCGR180_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR180_TOG_CG_SHIFT))&CCM_CCGR180_TOG_CG_MASK) -/* CCGR181 Bit Fields */ -#define CCM_CCGR181_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR181_CG_SHIFT 0 -#define CCM_CCGR181_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR181_CG_SHIFT))&CCM_CCGR181_CG_MASK) -/* CCGR181_SET Bit Fields */ -#define CCM_CCGR181_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR181_SET_CG_SHIFT 0 -#define CCM_CCGR181_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR181_SET_CG_SHIFT))&CCM_CCGR181_SET_CG_MASK) -/* CCGR181_CLR Bit Fields */ -#define CCM_CCGR181_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR181_CLR_CG_SHIFT 0 -#define CCM_CCGR181_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR181_CLR_CG_SHIFT))&CCM_CCGR181_CLR_CG_MASK) -/* CCGR181_TOG Bit Fields */ -#define CCM_CCGR181_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR181_TOG_CG_SHIFT 0 -#define CCM_CCGR181_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR181_TOG_CG_SHIFT))&CCM_CCGR181_TOG_CG_MASK) -/* CCGR182 Bit Fields */ -#define CCM_CCGR182_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR182_CG_SHIFT 0 -#define CCM_CCGR182_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR182_CG_SHIFT))&CCM_CCGR182_CG_MASK) -/* CCGR182_SET Bit Fields */ -#define CCM_CCGR182_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR182_SET_CG_SHIFT 0 -#define CCM_CCGR182_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR182_SET_CG_SHIFT))&CCM_CCGR182_SET_CG_MASK) -/* CCGR182_CLR Bit Fields */ -#define CCM_CCGR182_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR182_CLR_CG_SHIFT 0 -#define CCM_CCGR182_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR182_CLR_CG_SHIFT))&CCM_CCGR182_CLR_CG_MASK) -/* CCGR182_TOG Bit Fields */ -#define CCM_CCGR182_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR182_TOG_CG_SHIFT 0 -#define CCM_CCGR182_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR182_TOG_CG_SHIFT))&CCM_CCGR182_TOG_CG_MASK) -/* CCGR183 Bit Fields */ -#define CCM_CCGR183_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR183_CG_SHIFT 0 -#define CCM_CCGR183_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR183_CG_SHIFT))&CCM_CCGR183_CG_MASK) -/* CCGR183_SET Bit Fields */ -#define CCM_CCGR183_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR183_SET_CG_SHIFT 0 -#define CCM_CCGR183_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR183_SET_CG_SHIFT))&CCM_CCGR183_SET_CG_MASK) -/* CCGR183_CLR Bit Fields */ -#define CCM_CCGR183_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR183_CLR_CG_SHIFT 0 -#define CCM_CCGR183_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR183_CLR_CG_SHIFT))&CCM_CCGR183_CLR_CG_MASK) -/* CCGR183_TOG Bit Fields */ -#define CCM_CCGR183_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR183_TOG_CG_SHIFT 0 -#define CCM_CCGR183_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR183_TOG_CG_SHIFT))&CCM_CCGR183_TOG_CG_MASK) -/* CCGR184 Bit Fields */ -#define CCM_CCGR184_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR184_CG_SHIFT 0 -#define CCM_CCGR184_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR184_CG_SHIFT))&CCM_CCGR184_CG_MASK) -/* CCGR184_SET Bit Fields */ -#define CCM_CCGR184_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR184_SET_CG_SHIFT 0 -#define CCM_CCGR184_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR184_SET_CG_SHIFT))&CCM_CCGR184_SET_CG_MASK) -/* CCGR184_CLR Bit Fields */ -#define CCM_CCGR184_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR184_CLR_CG_SHIFT 0 -#define CCM_CCGR184_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR184_CLR_CG_SHIFT))&CCM_CCGR184_CLR_CG_MASK) -/* CCGR184_TOG Bit Fields */ -#define CCM_CCGR184_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR184_TOG_CG_SHIFT 0 -#define CCM_CCGR184_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR184_TOG_CG_SHIFT))&CCM_CCGR184_TOG_CG_MASK) -/* CCGR185 Bit Fields */ -#define CCM_CCGR185_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR185_CG_SHIFT 0 -#define CCM_CCGR185_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR185_CG_SHIFT))&CCM_CCGR185_CG_MASK) -/* CCGR185_SET Bit Fields */ -#define CCM_CCGR185_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR185_SET_CG_SHIFT 0 -#define CCM_CCGR185_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR185_SET_CG_SHIFT))&CCM_CCGR185_SET_CG_MASK) -/* CCGR185_CLR Bit Fields */ -#define CCM_CCGR185_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR185_CLR_CG_SHIFT 0 -#define CCM_CCGR185_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR185_CLR_CG_SHIFT))&CCM_CCGR185_CLR_CG_MASK) -/* CCGR185_TOG Bit Fields */ -#define CCM_CCGR185_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR185_TOG_CG_SHIFT 0 -#define CCM_CCGR185_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR185_TOG_CG_SHIFT))&CCM_CCGR185_TOG_CG_MASK) -/* CCGR186 Bit Fields */ -#define CCM_CCGR186_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR186_CG_SHIFT 0 -#define CCM_CCGR186_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR186_CG_SHIFT))&CCM_CCGR186_CG_MASK) -/* CCGR186_SET Bit Fields */ -#define CCM_CCGR186_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR186_SET_CG_SHIFT 0 -#define CCM_CCGR186_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR186_SET_CG_SHIFT))&CCM_CCGR186_SET_CG_MASK) -/* CCGR186_CLR Bit Fields */ -#define CCM_CCGR186_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR186_CLR_CG_SHIFT 0 -#define CCM_CCGR186_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR186_CLR_CG_SHIFT))&CCM_CCGR186_CLR_CG_MASK) -/* CCGR186_TOG Bit Fields */ -#define CCM_CCGR186_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR186_TOG_CG_SHIFT 0 -#define CCM_CCGR186_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR186_TOG_CG_SHIFT))&CCM_CCGR186_TOG_CG_MASK) -/* CCGR187 Bit Fields */ -#define CCM_CCGR187_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR187_CG_SHIFT 0 -#define CCM_CCGR187_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR187_CG_SHIFT))&CCM_CCGR187_CG_MASK) -/* CCGR187_SET Bit Fields */ -#define CCM_CCGR187_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR187_SET_CG_SHIFT 0 -#define CCM_CCGR187_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR187_SET_CG_SHIFT))&CCM_CCGR187_SET_CG_MASK) -/* CCGR187_CLR Bit Fields */ -#define CCM_CCGR187_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR187_CLR_CG_SHIFT 0 -#define CCM_CCGR187_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR187_CLR_CG_SHIFT))&CCM_CCGR187_CLR_CG_MASK) -/* CCGR187_TOG Bit Fields */ -#define CCM_CCGR187_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR187_TOG_CG_SHIFT 0 -#define CCM_CCGR187_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR187_TOG_CG_SHIFT))&CCM_CCGR187_TOG_CG_MASK) -/* CCGR188 Bit Fields */ -#define CCM_CCGR188_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR188_CG_SHIFT 0 -#define CCM_CCGR188_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR188_CG_SHIFT))&CCM_CCGR188_CG_MASK) -/* CCGR188_SET Bit Fields */ -#define CCM_CCGR188_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR188_SET_CG_SHIFT 0 -#define CCM_CCGR188_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR188_SET_CG_SHIFT))&CCM_CCGR188_SET_CG_MASK) -/* CCGR188_CLR Bit Fields */ -#define CCM_CCGR188_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR188_CLR_CG_SHIFT 0 -#define CCM_CCGR188_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR188_CLR_CG_SHIFT))&CCM_CCGR188_CLR_CG_MASK) -/* CCGR188_TOG Bit Fields */ -#define CCM_CCGR188_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR188_TOG_CG_SHIFT 0 -#define CCM_CCGR188_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR188_TOG_CG_SHIFT))&CCM_CCGR188_TOG_CG_MASK) -/* CCGR189 Bit Fields */ -#define CCM_CCGR189_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR189_CG_SHIFT 0 -#define CCM_CCGR189_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR189_CG_SHIFT))&CCM_CCGR189_CG_MASK) -/* CCGR189_SET Bit Fields */ -#define CCM_CCGR189_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR189_SET_CG_SHIFT 0 -#define CCM_CCGR189_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR189_SET_CG_SHIFT))&CCM_CCGR189_SET_CG_MASK) -/* CCGR189_CLR Bit Fields */ -#define CCM_CCGR189_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR189_CLR_CG_SHIFT 0 -#define CCM_CCGR189_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR189_CLR_CG_SHIFT))&CCM_CCGR189_CLR_CG_MASK) -/* CCGR189_TOG Bit Fields */ -#define CCM_CCGR189_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR189_TOG_CG_SHIFT 0 -#define CCM_CCGR189_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR189_TOG_CG_SHIFT))&CCM_CCGR189_TOG_CG_MASK) -/* CCGR190 Bit Fields */ -#define CCM_CCGR190_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR190_CG_SHIFT 0 -#define CCM_CCGR190_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR190_CG_SHIFT))&CCM_CCGR190_CG_MASK) -/* CCGR190_SET Bit Fields */ -#define CCM_CCGR190_SET_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR190_SET_CG_SHIFT 0 -#define CCM_CCGR190_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR190_SET_CG_SHIFT))&CCM_CCGR190_SET_CG_MASK) -/* CCGR190_CLR Bit Fields */ -#define CCM_CCGR190_CLR_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR190_CLR_CG_SHIFT 0 -#define CCM_CCGR190_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR190_CLR_CG_SHIFT))&CCM_CCGR190_CLR_CG_MASK) -/* CCGR190_TOG Bit Fields */ -#define CCM_CCGR190_TOG_CG_MASK 0xFFFFFFFFu -#define CCM_CCGR190_TOG_CG_SHIFT 0 -#define CCM_CCGR190_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR190_TOG_CG_SHIFT))&CCM_CCGR190_TOG_CG_MASK) -/* TARGET_ROOT0 Bit Fields */ -#define CCM_TARGET_ROOT0_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT0_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT0_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_POST_PODF_SHIFT))&CCM_TARGET_ROOT0_POST_PODF_MASK) -#define CCM_TARGET_ROOT0_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT0_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT0_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT0_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT0_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT0_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT0_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT0_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT0_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT0_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT0_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_PRE_PODF_SHIFT))&CCM_TARGET_ROOT0_PRE_PODF_MASK) -#define CCM_TARGET_ROOT0_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT0_MUX_SHIFT 24 -#define CCM_TARGET_ROOT0_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_MUX_SHIFT))&CCM_TARGET_ROOT0_MUX_MASK) -#define CCM_TARGET_ROOT0_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT0_ENABLE_SHIFT 28 -/* TARGET_ROOT0_SET Bit Fields */ -#define CCM_TARGET_ROOT0_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT0_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT0_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT0_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT0_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT0_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT0_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT0_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT0_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT0_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT0_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT0_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT0_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT0_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT0_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT0_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT0_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT0_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT0_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_SET_MUX_SHIFT))&CCM_TARGET_ROOT0_SET_MUX_MASK) -#define CCM_TARGET_ROOT0_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT0_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT0_CLR Bit Fields */ -#define CCM_TARGET_ROOT0_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT0_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT0_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT0_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT0_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT0_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT0_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT0_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT0_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT0_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT0_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT0_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT0_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT0_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT0_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT0_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT0_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT0_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT0_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_CLR_MUX_SHIFT))&CCM_TARGET_ROOT0_CLR_MUX_MASK) -#define CCM_TARGET_ROOT0_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT0_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT0_TOG Bit Fields */ -#define CCM_TARGET_ROOT0_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT0_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT0_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT0_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT0_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT0_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT0_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT0_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT0_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT0_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT0_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT0_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT0_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT0_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT0_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT0_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT0_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT0_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT0_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_TOG_MUX_SHIFT))&CCM_TARGET_ROOT0_TOG_MUX_MASK) -#define CCM_TARGET_ROOT0_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT0_TOG_ENABLE_SHIFT 28 -/* POST0 Bit Fields */ -#define CCM_POST0_POST_PODF_MASK 0x3Fu -#define CCM_POST0_POST_PODF_SHIFT 0 -#define CCM_POST0_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST0_POST_PODF_SHIFT))&CCM_POST0_POST_PODF_MASK) -#define CCM_POST0_BUSY1_MASK 0x80u -#define CCM_POST0_BUSY1_SHIFT 7 -#define CCM_POST0_AUTO_PODF_MASK 0x700u -#define CCM_POST0_AUTO_PODF_SHIFT 8 -#define CCM_POST0_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST0_AUTO_PODF_SHIFT))&CCM_POST0_AUTO_PODF_MASK) -#define CCM_POST0_AUTO_EN_MASK 0x1000u -#define CCM_POST0_AUTO_EN_SHIFT 12 -#define CCM_POST0_SLOW_MASK 0x8000u -#define CCM_POST0_SLOW_SHIFT 15 -#define CCM_POST0_SELECT_MASK 0x10000000u -#define CCM_POST0_SELECT_SHIFT 28 -#define CCM_POST0_BUSY2_MASK 0x80000000u -#define CCM_POST0_BUSY2_SHIFT 31 -/* POST_ROOT0_SET Bit Fields */ -#define CCM_POST_ROOT0_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT0_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT0_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_SET_POST_PODF_SHIFT))&CCM_POST_ROOT0_SET_POST_PODF_MASK) -#define CCM_POST_ROOT0_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT0_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT0_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT0_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT0_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT0_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT0_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT0_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT0_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT0_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT0_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT0_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT0_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT0_SET_BUSY2_SHIFT 31 -/* POST_ROOT0_CLR Bit Fields */ -#define CCM_POST_ROOT0_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT0_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT0_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT0_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT0_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT0_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT0_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT0_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT0_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT0_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT0_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT0_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT0_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT0_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT0_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT0_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT0_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT0_CLR_BUSY2_SHIFT 31 -/* POST_ROOT0_TOG Bit Fields */ -#define CCM_POST_ROOT0_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT0_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT0_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT0_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT0_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT0_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT0_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT0_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT0_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT0_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT0_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT0_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT0_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT0_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT0_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT0_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT0_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT0_TOG_BUSY2_SHIFT 31 -/* PRE0 Bit Fields */ -#define CCM_PRE0_PRE_PODF_B_MASK 0x7u -#define CCM_PRE0_PRE_PODF_B_SHIFT 0 -#define CCM_PRE0_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE0_PRE_PODF_B_SHIFT))&CCM_PRE0_PRE_PODF_B_MASK) -#define CCM_PRE0_BUSY0_MASK 0x8u -#define CCM_PRE0_BUSY0_SHIFT 3 -#define CCM_PRE0_MUX_B_MASK 0x700u -#define CCM_PRE0_MUX_B_SHIFT 8 -#define CCM_PRE0_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE0_MUX_B_SHIFT))&CCM_PRE0_MUX_B_MASK) -#define CCM_PRE0_EN_B_MASK 0x1000u -#define CCM_PRE0_EN_B_SHIFT 12 -#define CCM_PRE0_BUSY1_MASK 0x8000u -#define CCM_PRE0_BUSY1_SHIFT 15 -#define CCM_PRE0_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE0_PRE_PODF_A_SHIFT 16 -#define CCM_PRE0_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE0_PRE_PODF_A_SHIFT))&CCM_PRE0_PRE_PODF_A_MASK) -#define CCM_PRE0_BUSY3_MASK 0x80000u -#define CCM_PRE0_BUSY3_SHIFT 19 -#define CCM_PRE0_MUX_A_MASK 0x7000000u -#define CCM_PRE0_MUX_A_SHIFT 24 -#define CCM_PRE0_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE0_MUX_A_SHIFT))&CCM_PRE0_MUX_A_MASK) -#define CCM_PRE0_EN_A_MASK 0x10000000u -#define CCM_PRE0_EN_A_SHIFT 28 -#define CCM_PRE0_BUSY4_MASK 0x80000000u -#define CCM_PRE0_BUSY4_SHIFT 31 -/* PRE_ROOT0_SET Bit Fields */ -#define CCM_PRE_ROOT0_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT0_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT0_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT0_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT0_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT0_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT0_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT0_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT0_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_SET_MUX_B_SHIFT))&CCM_PRE_ROOT0_SET_MUX_B_MASK) -#define CCM_PRE_ROOT0_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT0_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT0_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT0_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT0_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT0_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT0_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT0_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT0_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT0_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT0_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT0_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT0_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_SET_MUX_A_SHIFT))&CCM_PRE_ROOT0_SET_MUX_A_MASK) -#define CCM_PRE_ROOT0_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT0_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT0_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT0_SET_BUSY4_SHIFT 31 -/* PRE_ROOT0_CLR Bit Fields */ -#define CCM_PRE_ROOT0_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT0_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT0_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT0_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT0_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT0_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT0_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT0_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT0_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT0_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT0_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT0_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT0_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT0_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT0_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT0_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT0_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT0_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT0_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT0_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT0_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT0_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT0_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT0_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT0_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT0_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT0_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT0_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT0_TOG Bit Fields */ -#define CCM_PRE_ROOT0_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT0_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT0_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT0_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT0_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT0_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT0_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT0_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT0_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT0_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT0_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT0_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT0_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT0_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT0_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT0_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT0_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT0_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT0_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT0_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT0_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT0_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT0_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT0_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT0_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT0_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT0_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT0_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL0 Bit Fields */ -#define CCM_ACCESS_CTRL0_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL0_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL0_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL0_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL0_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL0_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL0_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL0_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL0_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL0_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL0_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL0_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL0_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL0_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL0_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL0_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL0_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL0_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL0_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL0_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL0_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL0_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL0_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL0_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL0_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL0_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL0_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL0_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL0_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL0_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL0_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL0_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL0_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL0_LOCK_SHIFT 31 -/* ACCESS_CTRL0_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL0_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL0_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL0_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL0_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL0_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL0_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL0_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL0_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL0_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL0_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL0_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL0_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL0_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL0_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL0_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL0_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT1 Bit Fields */ -#define CCM_TARGET_ROOT1_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT1_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT1_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_POST_PODF_SHIFT))&CCM_TARGET_ROOT1_POST_PODF_MASK) -#define CCM_TARGET_ROOT1_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT1_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT1_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT1_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT1_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT1_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT1_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT1_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT1_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT1_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT1_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_PRE_PODF_SHIFT))&CCM_TARGET_ROOT1_PRE_PODF_MASK) -#define CCM_TARGET_ROOT1_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT1_MUX_SHIFT 24 -#define CCM_TARGET_ROOT1_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_MUX_SHIFT))&CCM_TARGET_ROOT1_MUX_MASK) -#define CCM_TARGET_ROOT1_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT1_ENABLE_SHIFT 28 -/* TARGET_ROOT1_SET Bit Fields */ -#define CCM_TARGET_ROOT1_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT1_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT1_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT1_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT1_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT1_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT1_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT1_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT1_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT1_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT1_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT1_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT1_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT1_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT1_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT1_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT1_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT1_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT1_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_SET_MUX_SHIFT))&CCM_TARGET_ROOT1_SET_MUX_MASK) -#define CCM_TARGET_ROOT1_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT1_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT1_CLR Bit Fields */ -#define CCM_TARGET_ROOT1_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT1_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT1_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT1_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT1_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT1_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT1_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT1_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT1_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT1_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT1_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT1_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT1_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT1_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT1_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT1_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT1_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT1_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT1_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_CLR_MUX_SHIFT))&CCM_TARGET_ROOT1_CLR_MUX_MASK) -#define CCM_TARGET_ROOT1_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT1_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT1_TOG Bit Fields */ -#define CCM_TARGET_ROOT1_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT1_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT1_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT1_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT1_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT1_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT1_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT1_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT1_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT1_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT1_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT1_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT1_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT1_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT1_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT1_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT1_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT1_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT1_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_TOG_MUX_SHIFT))&CCM_TARGET_ROOT1_TOG_MUX_MASK) -#define CCM_TARGET_ROOT1_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT1_TOG_ENABLE_SHIFT 28 -/* POST1 Bit Fields */ -#define CCM_POST1_POST_PODF_MASK 0x3Fu -#define CCM_POST1_POST_PODF_SHIFT 0 -#define CCM_POST1_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST1_POST_PODF_SHIFT))&CCM_POST1_POST_PODF_MASK) -#define CCM_POST1_BUSY1_MASK 0x80u -#define CCM_POST1_BUSY1_SHIFT 7 -#define CCM_POST1_AUTO_PODF_MASK 0x700u -#define CCM_POST1_AUTO_PODF_SHIFT 8 -#define CCM_POST1_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST1_AUTO_PODF_SHIFT))&CCM_POST1_AUTO_PODF_MASK) -#define CCM_POST1_AUTO_EN_MASK 0x1000u -#define CCM_POST1_AUTO_EN_SHIFT 12 -#define CCM_POST1_SLOW_MASK 0x8000u -#define CCM_POST1_SLOW_SHIFT 15 -#define CCM_POST1_SELECT_MASK 0x10000000u -#define CCM_POST1_SELECT_SHIFT 28 -#define CCM_POST1_BUSY2_MASK 0x80000000u -#define CCM_POST1_BUSY2_SHIFT 31 -/* POST_ROOT1_SET Bit Fields */ -#define CCM_POST_ROOT1_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT1_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT1_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_SET_POST_PODF_SHIFT))&CCM_POST_ROOT1_SET_POST_PODF_MASK) -#define CCM_POST_ROOT1_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT1_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT1_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT1_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT1_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT1_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT1_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT1_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT1_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT1_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT1_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT1_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT1_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT1_SET_BUSY2_SHIFT 31 -/* POST_ROOT1_CLR Bit Fields */ -#define CCM_POST_ROOT1_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT1_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT1_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT1_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT1_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT1_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT1_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT1_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT1_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT1_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT1_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT1_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT1_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT1_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT1_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT1_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT1_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT1_CLR_BUSY2_SHIFT 31 -/* POST_ROOT1_TOG Bit Fields */ -#define CCM_POST_ROOT1_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT1_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT1_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT1_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT1_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT1_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT1_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT1_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT1_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT1_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT1_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT1_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT1_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT1_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT1_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT1_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT1_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT1_TOG_BUSY2_SHIFT 31 -/* PRE1 Bit Fields */ -#define CCM_PRE1_PRE_PODF_B_MASK 0x7u -#define CCM_PRE1_PRE_PODF_B_SHIFT 0 -#define CCM_PRE1_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE1_PRE_PODF_B_SHIFT))&CCM_PRE1_PRE_PODF_B_MASK) -#define CCM_PRE1_BUSY0_MASK 0x8u -#define CCM_PRE1_BUSY0_SHIFT 3 -#define CCM_PRE1_MUX_B_MASK 0x700u -#define CCM_PRE1_MUX_B_SHIFT 8 -#define CCM_PRE1_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE1_MUX_B_SHIFT))&CCM_PRE1_MUX_B_MASK) -#define CCM_PRE1_EN_B_MASK 0x1000u -#define CCM_PRE1_EN_B_SHIFT 12 -#define CCM_PRE1_BUSY1_MASK 0x8000u -#define CCM_PRE1_BUSY1_SHIFT 15 -#define CCM_PRE1_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE1_PRE_PODF_A_SHIFT 16 -#define CCM_PRE1_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE1_PRE_PODF_A_SHIFT))&CCM_PRE1_PRE_PODF_A_MASK) -#define CCM_PRE1_BUSY3_MASK 0x80000u -#define CCM_PRE1_BUSY3_SHIFT 19 -#define CCM_PRE1_MUX_A_MASK 0x7000000u -#define CCM_PRE1_MUX_A_SHIFT 24 -#define CCM_PRE1_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE1_MUX_A_SHIFT))&CCM_PRE1_MUX_A_MASK) -#define CCM_PRE1_EN_A_MASK 0x10000000u -#define CCM_PRE1_EN_A_SHIFT 28 -#define CCM_PRE1_BUSY4_MASK 0x80000000u -#define CCM_PRE1_BUSY4_SHIFT 31 -/* PRE_ROOT1_SET Bit Fields */ -#define CCM_PRE_ROOT1_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT1_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT1_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT1_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT1_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT1_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT1_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT1_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT1_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_SET_MUX_B_SHIFT))&CCM_PRE_ROOT1_SET_MUX_B_MASK) -#define CCM_PRE_ROOT1_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT1_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT1_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT1_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT1_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT1_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT1_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT1_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT1_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT1_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT1_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT1_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT1_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_SET_MUX_A_SHIFT))&CCM_PRE_ROOT1_SET_MUX_A_MASK) -#define CCM_PRE_ROOT1_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT1_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT1_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT1_SET_BUSY4_SHIFT 31 -/* PRE_ROOT1_CLR Bit Fields */ -#define CCM_PRE_ROOT1_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT1_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT1_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT1_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT1_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT1_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT1_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT1_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT1_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT1_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT1_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT1_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT1_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT1_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT1_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT1_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT1_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT1_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT1_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT1_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT1_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT1_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT1_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT1_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT1_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT1_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT1_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT1_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT1_TOG Bit Fields */ -#define CCM_PRE_ROOT1_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT1_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT1_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT1_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT1_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT1_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT1_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT1_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT1_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT1_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT1_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT1_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT1_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT1_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT1_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT1_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT1_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT1_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT1_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT1_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT1_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT1_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT1_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT1_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT1_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT1_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT1_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT1_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL1 Bit Fields */ -#define CCM_ACCESS_CTRL1_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL1_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL1_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL1_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL1_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL1_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL1_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL1_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL1_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL1_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL1_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL1_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL1_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL1_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL1_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL1_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL1_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL1_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL1_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL1_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL1_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL1_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL1_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL1_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL1_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL1_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL1_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL1_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL1_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL1_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL1_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL1_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL1_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL1_LOCK_SHIFT 31 -/* ACCESS_CTRL1_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL1_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL1_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL1_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL1_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL1_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL1_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL1_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL1_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL1_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL1_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL1_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL1_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL1_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL1_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL1_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL1_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT2 Bit Fields */ -#define CCM_TARGET_ROOT2_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT2_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT2_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_POST_PODF_SHIFT))&CCM_TARGET_ROOT2_POST_PODF_MASK) -#define CCM_TARGET_ROOT2_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT2_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT2_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT2_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT2_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT2_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT2_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT2_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT2_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT2_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT2_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_PRE_PODF_SHIFT))&CCM_TARGET_ROOT2_PRE_PODF_MASK) -#define CCM_TARGET_ROOT2_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT2_MUX_SHIFT 24 -#define CCM_TARGET_ROOT2_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_MUX_SHIFT))&CCM_TARGET_ROOT2_MUX_MASK) -#define CCM_TARGET_ROOT2_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT2_ENABLE_SHIFT 28 -/* TARGET_ROOT2_SET Bit Fields */ -#define CCM_TARGET_ROOT2_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT2_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT2_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT2_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT2_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT2_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT2_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT2_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT2_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT2_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT2_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT2_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT2_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT2_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT2_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT2_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT2_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT2_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT2_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_SET_MUX_SHIFT))&CCM_TARGET_ROOT2_SET_MUX_MASK) -#define CCM_TARGET_ROOT2_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT2_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT2_CLR Bit Fields */ -#define CCM_TARGET_ROOT2_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT2_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT2_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT2_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT2_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT2_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT2_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT2_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT2_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT2_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT2_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT2_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT2_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT2_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT2_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT2_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT2_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT2_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT2_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_CLR_MUX_SHIFT))&CCM_TARGET_ROOT2_CLR_MUX_MASK) -#define CCM_TARGET_ROOT2_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT2_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT2_TOG Bit Fields */ -#define CCM_TARGET_ROOT2_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT2_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT2_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT2_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT2_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT2_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT2_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT2_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT2_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT2_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT2_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT2_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT2_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT2_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT2_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT2_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT2_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT2_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT2_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_TOG_MUX_SHIFT))&CCM_TARGET_ROOT2_TOG_MUX_MASK) -#define CCM_TARGET_ROOT2_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT2_TOG_ENABLE_SHIFT 28 -/* POST2 Bit Fields */ -#define CCM_POST2_POST_PODF_MASK 0x3Fu -#define CCM_POST2_POST_PODF_SHIFT 0 -#define CCM_POST2_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST2_POST_PODF_SHIFT))&CCM_POST2_POST_PODF_MASK) -#define CCM_POST2_BUSY1_MASK 0x80u -#define CCM_POST2_BUSY1_SHIFT 7 -#define CCM_POST2_AUTO_PODF_MASK 0x700u -#define CCM_POST2_AUTO_PODF_SHIFT 8 -#define CCM_POST2_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST2_AUTO_PODF_SHIFT))&CCM_POST2_AUTO_PODF_MASK) -#define CCM_POST2_AUTO_EN_MASK 0x1000u -#define CCM_POST2_AUTO_EN_SHIFT 12 -#define CCM_POST2_SLOW_MASK 0x8000u -#define CCM_POST2_SLOW_SHIFT 15 -#define CCM_POST2_SELECT_MASK 0x10000000u -#define CCM_POST2_SELECT_SHIFT 28 -#define CCM_POST2_BUSY2_MASK 0x80000000u -#define CCM_POST2_BUSY2_SHIFT 31 -/* POST_ROOT2_SET Bit Fields */ -#define CCM_POST_ROOT2_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT2_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT2_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_SET_POST_PODF_SHIFT))&CCM_POST_ROOT2_SET_POST_PODF_MASK) -#define CCM_POST_ROOT2_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT2_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT2_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT2_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT2_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT2_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT2_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT2_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT2_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT2_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT2_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT2_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT2_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT2_SET_BUSY2_SHIFT 31 -/* POST_ROOT2_CLR Bit Fields */ -#define CCM_POST_ROOT2_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT2_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT2_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT2_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT2_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT2_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT2_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT2_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT2_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT2_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT2_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT2_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT2_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT2_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT2_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT2_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT2_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT2_CLR_BUSY2_SHIFT 31 -/* POST_ROOT2_TOG Bit Fields */ -#define CCM_POST_ROOT2_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT2_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT2_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT2_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT2_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT2_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT2_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT2_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT2_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT2_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT2_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT2_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT2_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT2_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT2_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT2_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT2_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT2_TOG_BUSY2_SHIFT 31 -/* PRE2 Bit Fields */ -#define CCM_PRE2_PRE_PODF_B_MASK 0x7u -#define CCM_PRE2_PRE_PODF_B_SHIFT 0 -#define CCM_PRE2_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE2_PRE_PODF_B_SHIFT))&CCM_PRE2_PRE_PODF_B_MASK) -#define CCM_PRE2_BUSY0_MASK 0x8u -#define CCM_PRE2_BUSY0_SHIFT 3 -#define CCM_PRE2_MUX_B_MASK 0x700u -#define CCM_PRE2_MUX_B_SHIFT 8 -#define CCM_PRE2_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE2_MUX_B_SHIFT))&CCM_PRE2_MUX_B_MASK) -#define CCM_PRE2_EN_B_MASK 0x1000u -#define CCM_PRE2_EN_B_SHIFT 12 -#define CCM_PRE2_BUSY1_MASK 0x8000u -#define CCM_PRE2_BUSY1_SHIFT 15 -#define CCM_PRE2_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE2_PRE_PODF_A_SHIFT 16 -#define CCM_PRE2_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE2_PRE_PODF_A_SHIFT))&CCM_PRE2_PRE_PODF_A_MASK) -#define CCM_PRE2_BUSY3_MASK 0x80000u -#define CCM_PRE2_BUSY3_SHIFT 19 -#define CCM_PRE2_MUX_A_MASK 0x7000000u -#define CCM_PRE2_MUX_A_SHIFT 24 -#define CCM_PRE2_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE2_MUX_A_SHIFT))&CCM_PRE2_MUX_A_MASK) -#define CCM_PRE2_EN_A_MASK 0x10000000u -#define CCM_PRE2_EN_A_SHIFT 28 -#define CCM_PRE2_BUSY4_MASK 0x80000000u -#define CCM_PRE2_BUSY4_SHIFT 31 -/* PRE_ROOT2_SET Bit Fields */ -#define CCM_PRE_ROOT2_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT2_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT2_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT2_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT2_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT2_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT2_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT2_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT2_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_SET_MUX_B_SHIFT))&CCM_PRE_ROOT2_SET_MUX_B_MASK) -#define CCM_PRE_ROOT2_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT2_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT2_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT2_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT2_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT2_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT2_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT2_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT2_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT2_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT2_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT2_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT2_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_SET_MUX_A_SHIFT))&CCM_PRE_ROOT2_SET_MUX_A_MASK) -#define CCM_PRE_ROOT2_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT2_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT2_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT2_SET_BUSY4_SHIFT 31 -/* PRE_ROOT2_CLR Bit Fields */ -#define CCM_PRE_ROOT2_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT2_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT2_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT2_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT2_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT2_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT2_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT2_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT2_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT2_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT2_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT2_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT2_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT2_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT2_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT2_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT2_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT2_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT2_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT2_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT2_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT2_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT2_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT2_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT2_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT2_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT2_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT2_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT2_TOG Bit Fields */ -#define CCM_PRE_ROOT2_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT2_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT2_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT2_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT2_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT2_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT2_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT2_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT2_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT2_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT2_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT2_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT2_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT2_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT2_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT2_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT2_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT2_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT2_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT2_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT2_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT2_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT2_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT2_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT2_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT2_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT2_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT2_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL2 Bit Fields */ -#define CCM_ACCESS_CTRL2_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL2_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL2_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL2_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL2_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL2_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL2_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL2_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL2_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL2_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL2_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL2_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL2_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL2_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL2_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL2_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL2_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL2_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL2_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL2_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL2_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL2_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL2_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL2_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL2_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL2_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL2_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL2_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL2_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL2_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL2_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL2_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL2_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL2_LOCK_SHIFT 31 -/* ACCESS_CTRL2_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL2_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL2_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL2_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL2_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL2_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL2_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL2_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL2_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL2_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL2_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL2_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL2_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL2_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL2_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL2_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL2_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT3 Bit Fields */ -#define CCM_TARGET_ROOT3_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT3_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT3_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_POST_PODF_SHIFT))&CCM_TARGET_ROOT3_POST_PODF_MASK) -#define CCM_TARGET_ROOT3_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT3_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT3_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT3_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT3_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT3_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT3_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT3_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT3_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT3_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT3_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_PRE_PODF_SHIFT))&CCM_TARGET_ROOT3_PRE_PODF_MASK) -#define CCM_TARGET_ROOT3_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT3_MUX_SHIFT 24 -#define CCM_TARGET_ROOT3_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_MUX_SHIFT))&CCM_TARGET_ROOT3_MUX_MASK) -#define CCM_TARGET_ROOT3_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT3_ENABLE_SHIFT 28 -/* TARGET_ROOT3_SET Bit Fields */ -#define CCM_TARGET_ROOT3_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT3_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT3_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT3_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT3_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT3_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT3_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT3_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT3_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT3_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT3_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT3_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT3_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT3_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT3_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT3_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT3_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT3_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT3_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_SET_MUX_SHIFT))&CCM_TARGET_ROOT3_SET_MUX_MASK) -#define CCM_TARGET_ROOT3_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT3_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT3_CLR Bit Fields */ -#define CCM_TARGET_ROOT3_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT3_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT3_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT3_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT3_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT3_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT3_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT3_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT3_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT3_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT3_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT3_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT3_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT3_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT3_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT3_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT3_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT3_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT3_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_CLR_MUX_SHIFT))&CCM_TARGET_ROOT3_CLR_MUX_MASK) -#define CCM_TARGET_ROOT3_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT3_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT3_TOG Bit Fields */ -#define CCM_TARGET_ROOT3_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT3_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT3_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT3_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT3_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT3_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT3_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT3_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT3_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT3_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT3_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT3_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT3_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT3_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT3_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT3_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT3_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT3_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT3_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_TOG_MUX_SHIFT))&CCM_TARGET_ROOT3_TOG_MUX_MASK) -#define CCM_TARGET_ROOT3_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT3_TOG_ENABLE_SHIFT 28 -/* POST3 Bit Fields */ -#define CCM_POST3_POST_PODF_MASK 0x3Fu -#define CCM_POST3_POST_PODF_SHIFT 0 -#define CCM_POST3_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST3_POST_PODF_SHIFT))&CCM_POST3_POST_PODF_MASK) -#define CCM_POST3_BUSY1_MASK 0x80u -#define CCM_POST3_BUSY1_SHIFT 7 -#define CCM_POST3_AUTO_PODF_MASK 0x700u -#define CCM_POST3_AUTO_PODF_SHIFT 8 -#define CCM_POST3_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST3_AUTO_PODF_SHIFT))&CCM_POST3_AUTO_PODF_MASK) -#define CCM_POST3_AUTO_EN_MASK 0x1000u -#define CCM_POST3_AUTO_EN_SHIFT 12 -#define CCM_POST3_SLOW_MASK 0x8000u -#define CCM_POST3_SLOW_SHIFT 15 -#define CCM_POST3_SELECT_MASK 0x10000000u -#define CCM_POST3_SELECT_SHIFT 28 -#define CCM_POST3_BUSY2_MASK 0x80000000u -#define CCM_POST3_BUSY2_SHIFT 31 -/* POST_ROOT3_SET Bit Fields */ -#define CCM_POST_ROOT3_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT3_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT3_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_SET_POST_PODF_SHIFT))&CCM_POST_ROOT3_SET_POST_PODF_MASK) -#define CCM_POST_ROOT3_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT3_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT3_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT3_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT3_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT3_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT3_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT3_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT3_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT3_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT3_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT3_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT3_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT3_SET_BUSY2_SHIFT 31 -/* POST_ROOT3_CLR Bit Fields */ -#define CCM_POST_ROOT3_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT3_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT3_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT3_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT3_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT3_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT3_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT3_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT3_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT3_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT3_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT3_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT3_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT3_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT3_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT3_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT3_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT3_CLR_BUSY2_SHIFT 31 -/* POST_ROOT3_TOG Bit Fields */ -#define CCM_POST_ROOT3_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT3_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT3_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT3_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT3_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT3_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT3_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT3_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT3_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT3_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT3_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT3_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT3_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT3_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT3_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT3_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT3_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT3_TOG_BUSY2_SHIFT 31 -/* PRE3 Bit Fields */ -#define CCM_PRE3_PRE_PODF_B_MASK 0x7u -#define CCM_PRE3_PRE_PODF_B_SHIFT 0 -#define CCM_PRE3_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE3_PRE_PODF_B_SHIFT))&CCM_PRE3_PRE_PODF_B_MASK) -#define CCM_PRE3_BUSY0_MASK 0x8u -#define CCM_PRE3_BUSY0_SHIFT 3 -#define CCM_PRE3_MUX_B_MASK 0x700u -#define CCM_PRE3_MUX_B_SHIFT 8 -#define CCM_PRE3_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE3_MUX_B_SHIFT))&CCM_PRE3_MUX_B_MASK) -#define CCM_PRE3_EN_B_MASK 0x1000u -#define CCM_PRE3_EN_B_SHIFT 12 -#define CCM_PRE3_BUSY1_MASK 0x8000u -#define CCM_PRE3_BUSY1_SHIFT 15 -#define CCM_PRE3_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE3_PRE_PODF_A_SHIFT 16 -#define CCM_PRE3_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE3_PRE_PODF_A_SHIFT))&CCM_PRE3_PRE_PODF_A_MASK) -#define CCM_PRE3_BUSY3_MASK 0x80000u -#define CCM_PRE3_BUSY3_SHIFT 19 -#define CCM_PRE3_MUX_A_MASK 0x7000000u -#define CCM_PRE3_MUX_A_SHIFT 24 -#define CCM_PRE3_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE3_MUX_A_SHIFT))&CCM_PRE3_MUX_A_MASK) -#define CCM_PRE3_EN_A_MASK 0x10000000u -#define CCM_PRE3_EN_A_SHIFT 28 -#define CCM_PRE3_BUSY4_MASK 0x80000000u -#define CCM_PRE3_BUSY4_SHIFT 31 -/* PRE_ROOT3_SET Bit Fields */ -#define CCM_PRE_ROOT3_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT3_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT3_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT3_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT3_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT3_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT3_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT3_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT3_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_SET_MUX_B_SHIFT))&CCM_PRE_ROOT3_SET_MUX_B_MASK) -#define CCM_PRE_ROOT3_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT3_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT3_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT3_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT3_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT3_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT3_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT3_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT3_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT3_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT3_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT3_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT3_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_SET_MUX_A_SHIFT))&CCM_PRE_ROOT3_SET_MUX_A_MASK) -#define CCM_PRE_ROOT3_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT3_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT3_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT3_SET_BUSY4_SHIFT 31 -/* PRE_ROOT3_CLR Bit Fields */ -#define CCM_PRE_ROOT3_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT3_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT3_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT3_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT3_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT3_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT3_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT3_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT3_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT3_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT3_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT3_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT3_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT3_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT3_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT3_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT3_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT3_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT3_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT3_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT3_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT3_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT3_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT3_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT3_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT3_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT3_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT3_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT3_TOG Bit Fields */ -#define CCM_PRE_ROOT3_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT3_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT3_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT3_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT3_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT3_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT3_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT3_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT3_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT3_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT3_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT3_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT3_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT3_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT3_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT3_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT3_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT3_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT3_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT3_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT3_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT3_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT3_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT3_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT3_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT3_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT3_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT3_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL3 Bit Fields */ -#define CCM_ACCESS_CTRL3_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL3_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL3_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL3_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL3_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL3_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL3_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL3_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL3_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL3_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL3_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL3_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL3_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL3_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL3_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL3_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL3_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL3_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL3_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL3_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL3_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL3_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL3_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL3_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL3_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL3_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL3_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL3_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL3_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL3_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL3_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL3_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL3_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL3_LOCK_SHIFT 31 -/* ACCESS_CTRL3_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL3_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL3_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL3_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL3_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL3_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL3_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL3_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL3_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL3_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL3_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL3_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL3_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL3_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL3_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL3_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL3_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT4 Bit Fields */ -#define CCM_TARGET_ROOT4_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT4_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT4_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_POST_PODF_SHIFT))&CCM_TARGET_ROOT4_POST_PODF_MASK) -#define CCM_TARGET_ROOT4_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT4_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT4_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT4_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT4_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT4_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT4_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT4_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT4_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT4_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT4_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_PRE_PODF_SHIFT))&CCM_TARGET_ROOT4_PRE_PODF_MASK) -#define CCM_TARGET_ROOT4_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT4_MUX_SHIFT 24 -#define CCM_TARGET_ROOT4_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_MUX_SHIFT))&CCM_TARGET_ROOT4_MUX_MASK) -#define CCM_TARGET_ROOT4_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT4_ENABLE_SHIFT 28 -/* TARGET_ROOT4_SET Bit Fields */ -#define CCM_TARGET_ROOT4_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT4_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT4_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT4_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT4_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT4_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT4_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT4_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT4_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT4_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT4_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT4_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT4_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT4_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT4_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT4_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT4_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT4_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT4_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_SET_MUX_SHIFT))&CCM_TARGET_ROOT4_SET_MUX_MASK) -#define CCM_TARGET_ROOT4_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT4_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT4_CLR Bit Fields */ -#define CCM_TARGET_ROOT4_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT4_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT4_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT4_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT4_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT4_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT4_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT4_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT4_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT4_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT4_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT4_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT4_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT4_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT4_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT4_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT4_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT4_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT4_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_CLR_MUX_SHIFT))&CCM_TARGET_ROOT4_CLR_MUX_MASK) -#define CCM_TARGET_ROOT4_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT4_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT4_TOG Bit Fields */ -#define CCM_TARGET_ROOT4_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT4_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT4_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT4_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT4_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT4_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT4_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT4_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT4_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT4_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT4_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT4_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT4_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT4_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT4_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT4_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT4_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT4_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT4_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_TOG_MUX_SHIFT))&CCM_TARGET_ROOT4_TOG_MUX_MASK) -#define CCM_TARGET_ROOT4_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT4_TOG_ENABLE_SHIFT 28 -/* POST4 Bit Fields */ -#define CCM_POST4_POST_PODF_MASK 0x3Fu -#define CCM_POST4_POST_PODF_SHIFT 0 -#define CCM_POST4_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST4_POST_PODF_SHIFT))&CCM_POST4_POST_PODF_MASK) -#define CCM_POST4_BUSY1_MASK 0x80u -#define CCM_POST4_BUSY1_SHIFT 7 -#define CCM_POST4_AUTO_PODF_MASK 0x700u -#define CCM_POST4_AUTO_PODF_SHIFT 8 -#define CCM_POST4_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST4_AUTO_PODF_SHIFT))&CCM_POST4_AUTO_PODF_MASK) -#define CCM_POST4_AUTO_EN_MASK 0x1000u -#define CCM_POST4_AUTO_EN_SHIFT 12 -#define CCM_POST4_SLOW_MASK 0x8000u -#define CCM_POST4_SLOW_SHIFT 15 -#define CCM_POST4_SELECT_MASK 0x10000000u -#define CCM_POST4_SELECT_SHIFT 28 -#define CCM_POST4_BUSY2_MASK 0x80000000u -#define CCM_POST4_BUSY2_SHIFT 31 -/* POST_ROOT4_SET Bit Fields */ -#define CCM_POST_ROOT4_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT4_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT4_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_SET_POST_PODF_SHIFT))&CCM_POST_ROOT4_SET_POST_PODF_MASK) -#define CCM_POST_ROOT4_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT4_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT4_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT4_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT4_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT4_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT4_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT4_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT4_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT4_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT4_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT4_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT4_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT4_SET_BUSY2_SHIFT 31 -/* POST_ROOT4_CLR Bit Fields */ -#define CCM_POST_ROOT4_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT4_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT4_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT4_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT4_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT4_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT4_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT4_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT4_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT4_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT4_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT4_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT4_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT4_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT4_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT4_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT4_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT4_CLR_BUSY2_SHIFT 31 -/* POST_ROOT4_TOG Bit Fields */ -#define CCM_POST_ROOT4_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT4_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT4_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT4_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT4_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT4_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT4_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT4_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT4_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT4_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT4_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT4_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT4_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT4_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT4_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT4_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT4_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT4_TOG_BUSY2_SHIFT 31 -/* PRE4 Bit Fields */ -#define CCM_PRE4_PRE_PODF_B_MASK 0x7u -#define CCM_PRE4_PRE_PODF_B_SHIFT 0 -#define CCM_PRE4_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE4_PRE_PODF_B_SHIFT))&CCM_PRE4_PRE_PODF_B_MASK) -#define CCM_PRE4_BUSY0_MASK 0x8u -#define CCM_PRE4_BUSY0_SHIFT 3 -#define CCM_PRE4_MUX_B_MASK 0x700u -#define CCM_PRE4_MUX_B_SHIFT 8 -#define CCM_PRE4_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE4_MUX_B_SHIFT))&CCM_PRE4_MUX_B_MASK) -#define CCM_PRE4_EN_B_MASK 0x1000u -#define CCM_PRE4_EN_B_SHIFT 12 -#define CCM_PRE4_BUSY1_MASK 0x8000u -#define CCM_PRE4_BUSY1_SHIFT 15 -#define CCM_PRE4_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE4_PRE_PODF_A_SHIFT 16 -#define CCM_PRE4_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE4_PRE_PODF_A_SHIFT))&CCM_PRE4_PRE_PODF_A_MASK) -#define CCM_PRE4_BUSY3_MASK 0x80000u -#define CCM_PRE4_BUSY3_SHIFT 19 -#define CCM_PRE4_MUX_A_MASK 0x7000000u -#define CCM_PRE4_MUX_A_SHIFT 24 -#define CCM_PRE4_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE4_MUX_A_SHIFT))&CCM_PRE4_MUX_A_MASK) -#define CCM_PRE4_EN_A_MASK 0x10000000u -#define CCM_PRE4_EN_A_SHIFT 28 -#define CCM_PRE4_BUSY4_MASK 0x80000000u -#define CCM_PRE4_BUSY4_SHIFT 31 -/* PRE_ROOT4_SET Bit Fields */ -#define CCM_PRE_ROOT4_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT4_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT4_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT4_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT4_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT4_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT4_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT4_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT4_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_SET_MUX_B_SHIFT))&CCM_PRE_ROOT4_SET_MUX_B_MASK) -#define CCM_PRE_ROOT4_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT4_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT4_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT4_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT4_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT4_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT4_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT4_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT4_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT4_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT4_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT4_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT4_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_SET_MUX_A_SHIFT))&CCM_PRE_ROOT4_SET_MUX_A_MASK) -#define CCM_PRE_ROOT4_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT4_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT4_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT4_SET_BUSY4_SHIFT 31 -/* PRE_ROOT4_CLR Bit Fields */ -#define CCM_PRE_ROOT4_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT4_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT4_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT4_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT4_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT4_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT4_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT4_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT4_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT4_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT4_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT4_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT4_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT4_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT4_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT4_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT4_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT4_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT4_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT4_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT4_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT4_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT4_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT4_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT4_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT4_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT4_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT4_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT4_TOG Bit Fields */ -#define CCM_PRE_ROOT4_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT4_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT4_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT4_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT4_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT4_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT4_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT4_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT4_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT4_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT4_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT4_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT4_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT4_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT4_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT4_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT4_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT4_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT4_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT4_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT4_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT4_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT4_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT4_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT4_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT4_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT4_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT4_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL4 Bit Fields */ -#define CCM_ACCESS_CTRL4_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL4_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL4_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL4_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL4_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL4_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL4_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL4_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL4_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL4_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL4_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL4_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL4_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL4_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL4_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL4_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL4_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL4_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL4_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL4_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL4_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL4_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL4_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL4_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL4_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL4_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL4_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL4_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL4_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL4_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL4_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL4_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL4_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL4_LOCK_SHIFT 31 -/* ACCESS_CTRL4_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL4_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL4_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL4_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL4_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL4_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL4_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL4_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL4_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL4_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL4_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL4_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL4_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL4_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL4_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL4_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL4_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT5 Bit Fields */ -#define CCM_TARGET_ROOT5_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT5_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT5_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_POST_PODF_SHIFT))&CCM_TARGET_ROOT5_POST_PODF_MASK) -#define CCM_TARGET_ROOT5_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT5_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT5_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT5_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT5_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT5_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT5_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT5_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT5_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT5_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT5_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_PRE_PODF_SHIFT))&CCM_TARGET_ROOT5_PRE_PODF_MASK) -#define CCM_TARGET_ROOT5_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT5_MUX_SHIFT 24 -#define CCM_TARGET_ROOT5_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_MUX_SHIFT))&CCM_TARGET_ROOT5_MUX_MASK) -#define CCM_TARGET_ROOT5_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT5_ENABLE_SHIFT 28 -/* TARGET_ROOT5_SET Bit Fields */ -#define CCM_TARGET_ROOT5_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT5_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT5_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT5_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT5_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT5_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT5_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT5_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT5_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT5_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT5_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT5_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT5_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT5_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT5_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT5_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT5_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT5_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT5_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_SET_MUX_SHIFT))&CCM_TARGET_ROOT5_SET_MUX_MASK) -#define CCM_TARGET_ROOT5_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT5_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT5_CLR Bit Fields */ -#define CCM_TARGET_ROOT5_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT5_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT5_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT5_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT5_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT5_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT5_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT5_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT5_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT5_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT5_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT5_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT5_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT5_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT5_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT5_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT5_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT5_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT5_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_CLR_MUX_SHIFT))&CCM_TARGET_ROOT5_CLR_MUX_MASK) -#define CCM_TARGET_ROOT5_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT5_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT5_TOG Bit Fields */ -#define CCM_TARGET_ROOT5_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT5_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT5_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT5_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT5_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT5_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT5_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT5_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT5_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT5_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT5_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT5_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT5_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT5_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT5_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT5_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT5_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT5_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT5_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_TOG_MUX_SHIFT))&CCM_TARGET_ROOT5_TOG_MUX_MASK) -#define CCM_TARGET_ROOT5_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT5_TOG_ENABLE_SHIFT 28 -/* POST5 Bit Fields */ -#define CCM_POST5_POST_PODF_MASK 0x3Fu -#define CCM_POST5_POST_PODF_SHIFT 0 -#define CCM_POST5_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST5_POST_PODF_SHIFT))&CCM_POST5_POST_PODF_MASK) -#define CCM_POST5_BUSY1_MASK 0x80u -#define CCM_POST5_BUSY1_SHIFT 7 -#define CCM_POST5_AUTO_PODF_MASK 0x700u -#define CCM_POST5_AUTO_PODF_SHIFT 8 -#define CCM_POST5_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST5_AUTO_PODF_SHIFT))&CCM_POST5_AUTO_PODF_MASK) -#define CCM_POST5_AUTO_EN_MASK 0x1000u -#define CCM_POST5_AUTO_EN_SHIFT 12 -#define CCM_POST5_SLOW_MASK 0x8000u -#define CCM_POST5_SLOW_SHIFT 15 -#define CCM_POST5_SELECT_MASK 0x10000000u -#define CCM_POST5_SELECT_SHIFT 28 -#define CCM_POST5_BUSY2_MASK 0x80000000u -#define CCM_POST5_BUSY2_SHIFT 31 -/* POST_ROOT5_SET Bit Fields */ -#define CCM_POST_ROOT5_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT5_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT5_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_SET_POST_PODF_SHIFT))&CCM_POST_ROOT5_SET_POST_PODF_MASK) -#define CCM_POST_ROOT5_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT5_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT5_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT5_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT5_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT5_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT5_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT5_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT5_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT5_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT5_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT5_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT5_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT5_SET_BUSY2_SHIFT 31 -/* POST_ROOT5_CLR Bit Fields */ -#define CCM_POST_ROOT5_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT5_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT5_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT5_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT5_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT5_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT5_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT5_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT5_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT5_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT5_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT5_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT5_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT5_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT5_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT5_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT5_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT5_CLR_BUSY2_SHIFT 31 -/* POST_ROOT5_TOG Bit Fields */ -#define CCM_POST_ROOT5_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT5_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT5_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT5_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT5_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT5_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT5_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT5_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT5_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT5_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT5_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT5_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT5_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT5_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT5_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT5_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT5_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT5_TOG_BUSY2_SHIFT 31 -/* PRE5 Bit Fields */ -#define CCM_PRE5_PRE_PODF_B_MASK 0x7u -#define CCM_PRE5_PRE_PODF_B_SHIFT 0 -#define CCM_PRE5_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE5_PRE_PODF_B_SHIFT))&CCM_PRE5_PRE_PODF_B_MASK) -#define CCM_PRE5_BUSY0_MASK 0x8u -#define CCM_PRE5_BUSY0_SHIFT 3 -#define CCM_PRE5_MUX_B_MASK 0x700u -#define CCM_PRE5_MUX_B_SHIFT 8 -#define CCM_PRE5_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE5_MUX_B_SHIFT))&CCM_PRE5_MUX_B_MASK) -#define CCM_PRE5_EN_B_MASK 0x1000u -#define CCM_PRE5_EN_B_SHIFT 12 -#define CCM_PRE5_BUSY1_MASK 0x8000u -#define CCM_PRE5_BUSY1_SHIFT 15 -#define CCM_PRE5_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE5_PRE_PODF_A_SHIFT 16 -#define CCM_PRE5_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE5_PRE_PODF_A_SHIFT))&CCM_PRE5_PRE_PODF_A_MASK) -#define CCM_PRE5_BUSY3_MASK 0x80000u -#define CCM_PRE5_BUSY3_SHIFT 19 -#define CCM_PRE5_MUX_A_MASK 0x7000000u -#define CCM_PRE5_MUX_A_SHIFT 24 -#define CCM_PRE5_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE5_MUX_A_SHIFT))&CCM_PRE5_MUX_A_MASK) -#define CCM_PRE5_EN_A_MASK 0x10000000u -#define CCM_PRE5_EN_A_SHIFT 28 -#define CCM_PRE5_BUSY4_MASK 0x80000000u -#define CCM_PRE5_BUSY4_SHIFT 31 -/* PRE_ROOT5_SET Bit Fields */ -#define CCM_PRE_ROOT5_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT5_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT5_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT5_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT5_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT5_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT5_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT5_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT5_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_SET_MUX_B_SHIFT))&CCM_PRE_ROOT5_SET_MUX_B_MASK) -#define CCM_PRE_ROOT5_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT5_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT5_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT5_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT5_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT5_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT5_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT5_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT5_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT5_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT5_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT5_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT5_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_SET_MUX_A_SHIFT))&CCM_PRE_ROOT5_SET_MUX_A_MASK) -#define CCM_PRE_ROOT5_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT5_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT5_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT5_SET_BUSY4_SHIFT 31 -/* PRE_ROOT5_CLR Bit Fields */ -#define CCM_PRE_ROOT5_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT5_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT5_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT5_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT5_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT5_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT5_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT5_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT5_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT5_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT5_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT5_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT5_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT5_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT5_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT5_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT5_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT5_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT5_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT5_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT5_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT5_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT5_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT5_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT5_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT5_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT5_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT5_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT5_TOG Bit Fields */ -#define CCM_PRE_ROOT5_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT5_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT5_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT5_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT5_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT5_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT5_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT5_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT5_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT5_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT5_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT5_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT5_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT5_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT5_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT5_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT5_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT5_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT5_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT5_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT5_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT5_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT5_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT5_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT5_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT5_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT5_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT5_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL5 Bit Fields */ -#define CCM_ACCESS_CTRL5_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL5_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL5_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL5_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL5_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL5_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL5_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL5_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL5_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL5_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL5_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL5_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL5_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL5_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL5_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL5_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL5_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL5_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL5_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL5_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL5_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL5_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL5_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL5_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL5_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL5_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL5_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL5_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL5_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL5_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL5_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL5_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL5_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL5_LOCK_SHIFT 31 -/* ACCESS_CTRL5_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL5_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL5_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL5_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL5_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL5_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL5_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL5_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL5_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL5_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL5_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL5_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL5_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL5_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL5_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL5_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL5_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT6 Bit Fields */ -#define CCM_TARGET_ROOT6_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT6_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT6_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_POST_PODF_SHIFT))&CCM_TARGET_ROOT6_POST_PODF_MASK) -#define CCM_TARGET_ROOT6_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT6_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT6_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT6_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT6_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT6_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT6_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT6_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT6_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT6_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT6_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_PRE_PODF_SHIFT))&CCM_TARGET_ROOT6_PRE_PODF_MASK) -#define CCM_TARGET_ROOT6_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT6_MUX_SHIFT 24 -#define CCM_TARGET_ROOT6_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_MUX_SHIFT))&CCM_TARGET_ROOT6_MUX_MASK) -#define CCM_TARGET_ROOT6_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT6_ENABLE_SHIFT 28 -/* TARGET_ROOT6_SET Bit Fields */ -#define CCM_TARGET_ROOT6_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT6_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT6_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT6_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT6_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT6_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT6_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT6_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT6_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT6_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT6_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT6_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT6_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT6_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT6_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT6_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT6_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT6_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT6_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_SET_MUX_SHIFT))&CCM_TARGET_ROOT6_SET_MUX_MASK) -#define CCM_TARGET_ROOT6_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT6_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT6_CLR Bit Fields */ -#define CCM_TARGET_ROOT6_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT6_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT6_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT6_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT6_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT6_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT6_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT6_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT6_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT6_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT6_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT6_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT6_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT6_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT6_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT6_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT6_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT6_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT6_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_CLR_MUX_SHIFT))&CCM_TARGET_ROOT6_CLR_MUX_MASK) -#define CCM_TARGET_ROOT6_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT6_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT6_TOG Bit Fields */ -#define CCM_TARGET_ROOT6_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT6_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT6_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT6_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT6_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT6_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT6_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT6_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT6_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT6_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT6_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT6_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT6_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT6_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT6_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT6_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT6_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT6_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT6_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_TOG_MUX_SHIFT))&CCM_TARGET_ROOT6_TOG_MUX_MASK) -#define CCM_TARGET_ROOT6_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT6_TOG_ENABLE_SHIFT 28 -/* POST6 Bit Fields */ -#define CCM_POST6_POST_PODF_MASK 0x3Fu -#define CCM_POST6_POST_PODF_SHIFT 0 -#define CCM_POST6_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST6_POST_PODF_SHIFT))&CCM_POST6_POST_PODF_MASK) -#define CCM_POST6_BUSY1_MASK 0x80u -#define CCM_POST6_BUSY1_SHIFT 7 -#define CCM_POST6_AUTO_PODF_MASK 0x700u -#define CCM_POST6_AUTO_PODF_SHIFT 8 -#define CCM_POST6_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST6_AUTO_PODF_SHIFT))&CCM_POST6_AUTO_PODF_MASK) -#define CCM_POST6_AUTO_EN_MASK 0x1000u -#define CCM_POST6_AUTO_EN_SHIFT 12 -#define CCM_POST6_SLOW_MASK 0x8000u -#define CCM_POST6_SLOW_SHIFT 15 -#define CCM_POST6_SELECT_MASK 0x10000000u -#define CCM_POST6_SELECT_SHIFT 28 -#define CCM_POST6_BUSY2_MASK 0x80000000u -#define CCM_POST6_BUSY2_SHIFT 31 -/* POST_ROOT6_SET Bit Fields */ -#define CCM_POST_ROOT6_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT6_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT6_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_SET_POST_PODF_SHIFT))&CCM_POST_ROOT6_SET_POST_PODF_MASK) -#define CCM_POST_ROOT6_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT6_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT6_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT6_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT6_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT6_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT6_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT6_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT6_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT6_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT6_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT6_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT6_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT6_SET_BUSY2_SHIFT 31 -/* POST_ROOT6_CLR Bit Fields */ -#define CCM_POST_ROOT6_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT6_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT6_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT6_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT6_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT6_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT6_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT6_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT6_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT6_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT6_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT6_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT6_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT6_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT6_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT6_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT6_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT6_CLR_BUSY2_SHIFT 31 -/* POST_ROOT6_TOG Bit Fields */ -#define CCM_POST_ROOT6_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT6_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT6_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT6_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT6_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT6_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT6_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT6_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT6_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT6_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT6_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT6_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT6_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT6_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT6_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT6_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT6_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT6_TOG_BUSY2_SHIFT 31 -/* PRE6 Bit Fields */ -#define CCM_PRE6_PRE_PODF_B_MASK 0x7u -#define CCM_PRE6_PRE_PODF_B_SHIFT 0 -#define CCM_PRE6_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE6_PRE_PODF_B_SHIFT))&CCM_PRE6_PRE_PODF_B_MASK) -#define CCM_PRE6_BUSY0_MASK 0x8u -#define CCM_PRE6_BUSY0_SHIFT 3 -#define CCM_PRE6_MUX_B_MASK 0x700u -#define CCM_PRE6_MUX_B_SHIFT 8 -#define CCM_PRE6_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE6_MUX_B_SHIFT))&CCM_PRE6_MUX_B_MASK) -#define CCM_PRE6_EN_B_MASK 0x1000u -#define CCM_PRE6_EN_B_SHIFT 12 -#define CCM_PRE6_BUSY1_MASK 0x8000u -#define CCM_PRE6_BUSY1_SHIFT 15 -#define CCM_PRE6_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE6_PRE_PODF_A_SHIFT 16 -#define CCM_PRE6_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE6_PRE_PODF_A_SHIFT))&CCM_PRE6_PRE_PODF_A_MASK) -#define CCM_PRE6_BUSY3_MASK 0x80000u -#define CCM_PRE6_BUSY3_SHIFT 19 -#define CCM_PRE6_MUX_A_MASK 0x7000000u -#define CCM_PRE6_MUX_A_SHIFT 24 -#define CCM_PRE6_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE6_MUX_A_SHIFT))&CCM_PRE6_MUX_A_MASK) -#define CCM_PRE6_EN_A_MASK 0x10000000u -#define CCM_PRE6_EN_A_SHIFT 28 -#define CCM_PRE6_BUSY4_MASK 0x80000000u -#define CCM_PRE6_BUSY4_SHIFT 31 -/* PRE_ROOT6_SET Bit Fields */ -#define CCM_PRE_ROOT6_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT6_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT6_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT6_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT6_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT6_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT6_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT6_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT6_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_SET_MUX_B_SHIFT))&CCM_PRE_ROOT6_SET_MUX_B_MASK) -#define CCM_PRE_ROOT6_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT6_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT6_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT6_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT6_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT6_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT6_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT6_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT6_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT6_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT6_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT6_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT6_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_SET_MUX_A_SHIFT))&CCM_PRE_ROOT6_SET_MUX_A_MASK) -#define CCM_PRE_ROOT6_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT6_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT6_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT6_SET_BUSY4_SHIFT 31 -/* PRE_ROOT6_CLR Bit Fields */ -#define CCM_PRE_ROOT6_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT6_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT6_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT6_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT6_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT6_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT6_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT6_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT6_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT6_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT6_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT6_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT6_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT6_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT6_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT6_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT6_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT6_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT6_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT6_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT6_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT6_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT6_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT6_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT6_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT6_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT6_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT6_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT6_TOG Bit Fields */ -#define CCM_PRE_ROOT6_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT6_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT6_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT6_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT6_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT6_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT6_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT6_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT6_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT6_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT6_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT6_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT6_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT6_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT6_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT6_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT6_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT6_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT6_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT6_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT6_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT6_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT6_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT6_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT6_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT6_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT6_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT6_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL6 Bit Fields */ -#define CCM_ACCESS_CTRL6_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL6_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL6_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL6_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL6_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL6_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL6_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL6_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL6_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL6_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL6_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL6_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL6_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL6_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL6_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL6_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL6_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL6_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL6_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL6_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL6_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL6_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL6_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL6_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL6_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL6_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL6_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL6_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL6_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL6_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL6_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL6_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL6_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL6_LOCK_SHIFT 31 -/* ACCESS_CTRL6_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL6_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL6_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL6_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL6_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL6_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL6_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL6_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL6_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL6_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL6_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL6_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL6_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL6_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL6_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL6_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL6_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT7 Bit Fields */ -#define CCM_TARGET_ROOT7_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT7_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT7_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_POST_PODF_SHIFT))&CCM_TARGET_ROOT7_POST_PODF_MASK) -#define CCM_TARGET_ROOT7_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT7_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT7_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT7_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT7_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT7_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT7_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT7_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT7_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT7_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT7_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_PRE_PODF_SHIFT))&CCM_TARGET_ROOT7_PRE_PODF_MASK) -#define CCM_TARGET_ROOT7_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT7_MUX_SHIFT 24 -#define CCM_TARGET_ROOT7_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_MUX_SHIFT))&CCM_TARGET_ROOT7_MUX_MASK) -#define CCM_TARGET_ROOT7_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT7_ENABLE_SHIFT 28 -/* TARGET_ROOT7_SET Bit Fields */ -#define CCM_TARGET_ROOT7_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT7_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT7_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT7_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT7_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT7_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT7_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT7_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT7_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT7_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT7_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT7_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT7_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT7_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT7_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT7_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT7_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT7_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT7_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_SET_MUX_SHIFT))&CCM_TARGET_ROOT7_SET_MUX_MASK) -#define CCM_TARGET_ROOT7_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT7_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT7_CLR Bit Fields */ -#define CCM_TARGET_ROOT7_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT7_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT7_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT7_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT7_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT7_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT7_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT7_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT7_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT7_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT7_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT7_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT7_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT7_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT7_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT7_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT7_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT7_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT7_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_CLR_MUX_SHIFT))&CCM_TARGET_ROOT7_CLR_MUX_MASK) -#define CCM_TARGET_ROOT7_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT7_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT7_TOG Bit Fields */ -#define CCM_TARGET_ROOT7_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT7_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT7_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT7_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT7_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT7_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT7_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT7_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT7_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT7_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT7_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT7_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT7_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT7_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT7_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT7_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT7_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT7_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT7_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_TOG_MUX_SHIFT))&CCM_TARGET_ROOT7_TOG_MUX_MASK) -#define CCM_TARGET_ROOT7_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT7_TOG_ENABLE_SHIFT 28 -/* POST7 Bit Fields */ -#define CCM_POST7_POST_PODF_MASK 0x3Fu -#define CCM_POST7_POST_PODF_SHIFT 0 -#define CCM_POST7_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST7_POST_PODF_SHIFT))&CCM_POST7_POST_PODF_MASK) -#define CCM_POST7_BUSY1_MASK 0x80u -#define CCM_POST7_BUSY1_SHIFT 7 -#define CCM_POST7_AUTO_PODF_MASK 0x700u -#define CCM_POST7_AUTO_PODF_SHIFT 8 -#define CCM_POST7_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST7_AUTO_PODF_SHIFT))&CCM_POST7_AUTO_PODF_MASK) -#define CCM_POST7_AUTO_EN_MASK 0x1000u -#define CCM_POST7_AUTO_EN_SHIFT 12 -#define CCM_POST7_SLOW_MASK 0x8000u -#define CCM_POST7_SLOW_SHIFT 15 -#define CCM_POST7_SELECT_MASK 0x10000000u -#define CCM_POST7_SELECT_SHIFT 28 -#define CCM_POST7_BUSY2_MASK 0x80000000u -#define CCM_POST7_BUSY2_SHIFT 31 -/* POST_ROOT7_SET Bit Fields */ -#define CCM_POST_ROOT7_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT7_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT7_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_SET_POST_PODF_SHIFT))&CCM_POST_ROOT7_SET_POST_PODF_MASK) -#define CCM_POST_ROOT7_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT7_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT7_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT7_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT7_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT7_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT7_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT7_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT7_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT7_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT7_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT7_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT7_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT7_SET_BUSY2_SHIFT 31 -/* POST_ROOT7_CLR Bit Fields */ -#define CCM_POST_ROOT7_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT7_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT7_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT7_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT7_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT7_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT7_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT7_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT7_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT7_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT7_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT7_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT7_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT7_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT7_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT7_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT7_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT7_CLR_BUSY2_SHIFT 31 -/* POST_ROOT7_TOG Bit Fields */ -#define CCM_POST_ROOT7_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT7_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT7_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT7_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT7_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT7_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT7_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT7_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT7_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT7_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT7_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT7_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT7_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT7_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT7_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT7_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT7_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT7_TOG_BUSY2_SHIFT 31 -/* PRE7 Bit Fields */ -#define CCM_PRE7_PRE_PODF_B_MASK 0x7u -#define CCM_PRE7_PRE_PODF_B_SHIFT 0 -#define CCM_PRE7_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE7_PRE_PODF_B_SHIFT))&CCM_PRE7_PRE_PODF_B_MASK) -#define CCM_PRE7_BUSY0_MASK 0x8u -#define CCM_PRE7_BUSY0_SHIFT 3 -#define CCM_PRE7_MUX_B_MASK 0x700u -#define CCM_PRE7_MUX_B_SHIFT 8 -#define CCM_PRE7_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE7_MUX_B_SHIFT))&CCM_PRE7_MUX_B_MASK) -#define CCM_PRE7_EN_B_MASK 0x1000u -#define CCM_PRE7_EN_B_SHIFT 12 -#define CCM_PRE7_BUSY1_MASK 0x8000u -#define CCM_PRE7_BUSY1_SHIFT 15 -#define CCM_PRE7_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE7_PRE_PODF_A_SHIFT 16 -#define CCM_PRE7_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE7_PRE_PODF_A_SHIFT))&CCM_PRE7_PRE_PODF_A_MASK) -#define CCM_PRE7_BUSY3_MASK 0x80000u -#define CCM_PRE7_BUSY3_SHIFT 19 -#define CCM_PRE7_MUX_A_MASK 0x7000000u -#define CCM_PRE7_MUX_A_SHIFT 24 -#define CCM_PRE7_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE7_MUX_A_SHIFT))&CCM_PRE7_MUX_A_MASK) -#define CCM_PRE7_EN_A_MASK 0x10000000u -#define CCM_PRE7_EN_A_SHIFT 28 -#define CCM_PRE7_BUSY4_MASK 0x80000000u -#define CCM_PRE7_BUSY4_SHIFT 31 -/* PRE_ROOT7_SET Bit Fields */ -#define CCM_PRE_ROOT7_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT7_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT7_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT7_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT7_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT7_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT7_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT7_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT7_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_SET_MUX_B_SHIFT))&CCM_PRE_ROOT7_SET_MUX_B_MASK) -#define CCM_PRE_ROOT7_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT7_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT7_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT7_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT7_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT7_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT7_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT7_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT7_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT7_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT7_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT7_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT7_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_SET_MUX_A_SHIFT))&CCM_PRE_ROOT7_SET_MUX_A_MASK) -#define CCM_PRE_ROOT7_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT7_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT7_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT7_SET_BUSY4_SHIFT 31 -/* PRE_ROOT7_CLR Bit Fields */ -#define CCM_PRE_ROOT7_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT7_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT7_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT7_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT7_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT7_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT7_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT7_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT7_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT7_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT7_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT7_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT7_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT7_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT7_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT7_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT7_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT7_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT7_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT7_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT7_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT7_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT7_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT7_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT7_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT7_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT7_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT7_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT7_TOG Bit Fields */ -#define CCM_PRE_ROOT7_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT7_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT7_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT7_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT7_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT7_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT7_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT7_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT7_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT7_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT7_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT7_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT7_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT7_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT7_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT7_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT7_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT7_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT7_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT7_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT7_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT7_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT7_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT7_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT7_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT7_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT7_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT7_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL7 Bit Fields */ -#define CCM_ACCESS_CTRL7_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL7_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL7_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL7_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL7_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL7_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL7_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL7_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL7_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL7_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL7_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL7_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL7_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL7_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL7_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL7_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL7_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL7_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL7_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL7_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL7_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL7_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL7_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL7_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL7_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL7_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL7_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL7_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL7_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL7_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL7_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL7_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL7_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL7_LOCK_SHIFT 31 -/* ACCESS_CTRL7_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL7_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL7_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL7_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL7_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL7_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL7_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL7_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL7_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL7_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL7_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL7_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL7_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL7_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL7_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL7_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL7_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT8 Bit Fields */ -#define CCM_TARGET_ROOT8_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT8_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT8_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_POST_PODF_SHIFT))&CCM_TARGET_ROOT8_POST_PODF_MASK) -#define CCM_TARGET_ROOT8_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT8_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT8_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT8_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT8_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT8_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT8_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT8_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT8_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT8_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT8_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_PRE_PODF_SHIFT))&CCM_TARGET_ROOT8_PRE_PODF_MASK) -#define CCM_TARGET_ROOT8_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT8_MUX_SHIFT 24 -#define CCM_TARGET_ROOT8_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_MUX_SHIFT))&CCM_TARGET_ROOT8_MUX_MASK) -#define CCM_TARGET_ROOT8_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT8_ENABLE_SHIFT 28 -/* TARGET_ROOT8_SET Bit Fields */ -#define CCM_TARGET_ROOT8_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT8_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT8_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT8_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT8_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT8_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT8_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT8_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT8_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT8_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT8_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT8_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT8_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT8_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT8_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT8_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT8_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT8_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT8_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_SET_MUX_SHIFT))&CCM_TARGET_ROOT8_SET_MUX_MASK) -#define CCM_TARGET_ROOT8_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT8_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT8_CLR Bit Fields */ -#define CCM_TARGET_ROOT8_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT8_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT8_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT8_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT8_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT8_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT8_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT8_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT8_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT8_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT8_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT8_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT8_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT8_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT8_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT8_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT8_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT8_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT8_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_CLR_MUX_SHIFT))&CCM_TARGET_ROOT8_CLR_MUX_MASK) -#define CCM_TARGET_ROOT8_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT8_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT8_TOG Bit Fields */ -#define CCM_TARGET_ROOT8_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT8_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT8_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT8_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT8_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT8_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT8_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT8_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT8_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT8_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT8_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT8_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT8_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT8_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT8_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT8_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT8_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT8_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT8_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_TOG_MUX_SHIFT))&CCM_TARGET_ROOT8_TOG_MUX_MASK) -#define CCM_TARGET_ROOT8_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT8_TOG_ENABLE_SHIFT 28 -/* POST8 Bit Fields */ -#define CCM_POST8_POST_PODF_MASK 0x3Fu -#define CCM_POST8_POST_PODF_SHIFT 0 -#define CCM_POST8_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST8_POST_PODF_SHIFT))&CCM_POST8_POST_PODF_MASK) -#define CCM_POST8_BUSY1_MASK 0x80u -#define CCM_POST8_BUSY1_SHIFT 7 -#define CCM_POST8_AUTO_PODF_MASK 0x700u -#define CCM_POST8_AUTO_PODF_SHIFT 8 -#define CCM_POST8_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST8_AUTO_PODF_SHIFT))&CCM_POST8_AUTO_PODF_MASK) -#define CCM_POST8_AUTO_EN_MASK 0x1000u -#define CCM_POST8_AUTO_EN_SHIFT 12 -#define CCM_POST8_SLOW_MASK 0x8000u -#define CCM_POST8_SLOW_SHIFT 15 -#define CCM_POST8_SELECT_MASK 0x10000000u -#define CCM_POST8_SELECT_SHIFT 28 -#define CCM_POST8_BUSY2_MASK 0x80000000u -#define CCM_POST8_BUSY2_SHIFT 31 -/* POST_ROOT8_SET Bit Fields */ -#define CCM_POST_ROOT8_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT8_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT8_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_SET_POST_PODF_SHIFT))&CCM_POST_ROOT8_SET_POST_PODF_MASK) -#define CCM_POST_ROOT8_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT8_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT8_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT8_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT8_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT8_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT8_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT8_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT8_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT8_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT8_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT8_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT8_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT8_SET_BUSY2_SHIFT 31 -/* POST_ROOT8_CLR Bit Fields */ -#define CCM_POST_ROOT8_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT8_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT8_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT8_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT8_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT8_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT8_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT8_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT8_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT8_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT8_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT8_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT8_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT8_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT8_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT8_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT8_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT8_CLR_BUSY2_SHIFT 31 -/* POST_ROOT8_TOG Bit Fields */ -#define CCM_POST_ROOT8_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT8_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT8_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT8_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT8_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT8_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT8_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT8_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT8_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT8_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT8_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT8_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT8_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT8_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT8_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT8_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT8_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT8_TOG_BUSY2_SHIFT 31 -/* PRE8 Bit Fields */ -#define CCM_PRE8_PRE_PODF_B_MASK 0x7u -#define CCM_PRE8_PRE_PODF_B_SHIFT 0 -#define CCM_PRE8_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE8_PRE_PODF_B_SHIFT))&CCM_PRE8_PRE_PODF_B_MASK) -#define CCM_PRE8_BUSY0_MASK 0x8u -#define CCM_PRE8_BUSY0_SHIFT 3 -#define CCM_PRE8_MUX_B_MASK 0x700u -#define CCM_PRE8_MUX_B_SHIFT 8 -#define CCM_PRE8_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE8_MUX_B_SHIFT))&CCM_PRE8_MUX_B_MASK) -#define CCM_PRE8_EN_B_MASK 0x1000u -#define CCM_PRE8_EN_B_SHIFT 12 -#define CCM_PRE8_BUSY1_MASK 0x8000u -#define CCM_PRE8_BUSY1_SHIFT 15 -#define CCM_PRE8_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE8_PRE_PODF_A_SHIFT 16 -#define CCM_PRE8_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE8_PRE_PODF_A_SHIFT))&CCM_PRE8_PRE_PODF_A_MASK) -#define CCM_PRE8_BUSY3_MASK 0x80000u -#define CCM_PRE8_BUSY3_SHIFT 19 -#define CCM_PRE8_MUX_A_MASK 0x7000000u -#define CCM_PRE8_MUX_A_SHIFT 24 -#define CCM_PRE8_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE8_MUX_A_SHIFT))&CCM_PRE8_MUX_A_MASK) -#define CCM_PRE8_EN_A_MASK 0x10000000u -#define CCM_PRE8_EN_A_SHIFT 28 -#define CCM_PRE8_BUSY4_MASK 0x80000000u -#define CCM_PRE8_BUSY4_SHIFT 31 -/* PRE_ROOT8_SET Bit Fields */ -#define CCM_PRE_ROOT8_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT8_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT8_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT8_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT8_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT8_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT8_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT8_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT8_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_SET_MUX_B_SHIFT))&CCM_PRE_ROOT8_SET_MUX_B_MASK) -#define CCM_PRE_ROOT8_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT8_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT8_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT8_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT8_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT8_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT8_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT8_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT8_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT8_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT8_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT8_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT8_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_SET_MUX_A_SHIFT))&CCM_PRE_ROOT8_SET_MUX_A_MASK) -#define CCM_PRE_ROOT8_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT8_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT8_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT8_SET_BUSY4_SHIFT 31 -/* PRE_ROOT8_CLR Bit Fields */ -#define CCM_PRE_ROOT8_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT8_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT8_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT8_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT8_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT8_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT8_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT8_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT8_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT8_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT8_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT8_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT8_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT8_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT8_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT8_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT8_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT8_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT8_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT8_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT8_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT8_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT8_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT8_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT8_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT8_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT8_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT8_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT8_TOG Bit Fields */ -#define CCM_PRE_ROOT8_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT8_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT8_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT8_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT8_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT8_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT8_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT8_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT8_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT8_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT8_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT8_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT8_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT8_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT8_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT8_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT8_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT8_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT8_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT8_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT8_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT8_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT8_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT8_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT8_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT8_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT8_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT8_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL8 Bit Fields */ -#define CCM_ACCESS_CTRL8_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL8_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL8_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL8_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL8_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL8_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL8_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL8_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL8_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL8_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL8_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL8_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL8_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL8_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL8_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL8_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL8_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL8_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL8_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL8_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL8_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL8_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL8_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL8_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL8_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL8_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL8_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL8_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL8_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL8_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL8_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL8_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL8_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL8_LOCK_SHIFT 31 -/* ACCESS_CTRL8_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL8_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL8_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL8_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL8_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL8_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL8_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL8_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL8_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL8_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL8_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL8_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL8_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL8_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL8_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL8_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL8_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT9 Bit Fields */ -#define CCM_TARGET_ROOT9_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT9_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT9_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_POST_PODF_SHIFT))&CCM_TARGET_ROOT9_POST_PODF_MASK) -#define CCM_TARGET_ROOT9_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT9_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT9_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT9_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT9_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT9_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT9_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT9_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT9_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT9_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT9_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_PRE_PODF_SHIFT))&CCM_TARGET_ROOT9_PRE_PODF_MASK) -#define CCM_TARGET_ROOT9_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT9_MUX_SHIFT 24 -#define CCM_TARGET_ROOT9_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_MUX_SHIFT))&CCM_TARGET_ROOT9_MUX_MASK) -#define CCM_TARGET_ROOT9_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT9_ENABLE_SHIFT 28 -/* TARGET_ROOT9_SET Bit Fields */ -#define CCM_TARGET_ROOT9_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT9_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT9_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT9_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT9_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT9_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT9_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT9_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT9_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT9_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT9_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT9_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT9_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT9_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT9_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT9_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT9_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT9_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT9_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_SET_MUX_SHIFT))&CCM_TARGET_ROOT9_SET_MUX_MASK) -#define CCM_TARGET_ROOT9_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT9_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT9_CLR Bit Fields */ -#define CCM_TARGET_ROOT9_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT9_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT9_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT9_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT9_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT9_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT9_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT9_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT9_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT9_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT9_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT9_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT9_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT9_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT9_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT9_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT9_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT9_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT9_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_CLR_MUX_SHIFT))&CCM_TARGET_ROOT9_CLR_MUX_MASK) -#define CCM_TARGET_ROOT9_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT9_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT9_TOG Bit Fields */ -#define CCM_TARGET_ROOT9_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT9_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT9_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT9_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT9_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT9_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT9_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT9_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT9_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT9_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT9_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT9_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT9_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT9_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT9_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT9_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT9_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT9_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT9_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_TOG_MUX_SHIFT))&CCM_TARGET_ROOT9_TOG_MUX_MASK) -#define CCM_TARGET_ROOT9_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT9_TOG_ENABLE_SHIFT 28 -/* POST9 Bit Fields */ -#define CCM_POST9_POST_PODF_MASK 0x3Fu -#define CCM_POST9_POST_PODF_SHIFT 0 -#define CCM_POST9_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST9_POST_PODF_SHIFT))&CCM_POST9_POST_PODF_MASK) -#define CCM_POST9_BUSY1_MASK 0x80u -#define CCM_POST9_BUSY1_SHIFT 7 -#define CCM_POST9_AUTO_PODF_MASK 0x700u -#define CCM_POST9_AUTO_PODF_SHIFT 8 -#define CCM_POST9_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST9_AUTO_PODF_SHIFT))&CCM_POST9_AUTO_PODF_MASK) -#define CCM_POST9_AUTO_EN_MASK 0x1000u -#define CCM_POST9_AUTO_EN_SHIFT 12 -#define CCM_POST9_SLOW_MASK 0x8000u -#define CCM_POST9_SLOW_SHIFT 15 -#define CCM_POST9_SELECT_MASK 0x10000000u -#define CCM_POST9_SELECT_SHIFT 28 -#define CCM_POST9_BUSY2_MASK 0x80000000u -#define CCM_POST9_BUSY2_SHIFT 31 -/* POST_ROOT9_SET Bit Fields */ -#define CCM_POST_ROOT9_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT9_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT9_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_SET_POST_PODF_SHIFT))&CCM_POST_ROOT9_SET_POST_PODF_MASK) -#define CCM_POST_ROOT9_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT9_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT9_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT9_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT9_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT9_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT9_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT9_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT9_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT9_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT9_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT9_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT9_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT9_SET_BUSY2_SHIFT 31 -/* POST_ROOT9_CLR Bit Fields */ -#define CCM_POST_ROOT9_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT9_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT9_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT9_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT9_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT9_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT9_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT9_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT9_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT9_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT9_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT9_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT9_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT9_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT9_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT9_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT9_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT9_CLR_BUSY2_SHIFT 31 -/* POST_ROOT9_TOG Bit Fields */ -#define CCM_POST_ROOT9_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT9_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT9_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT9_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT9_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT9_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT9_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT9_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT9_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT9_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT9_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT9_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT9_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT9_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT9_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT9_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT9_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT9_TOG_BUSY2_SHIFT 31 -/* PRE9 Bit Fields */ -#define CCM_PRE9_PRE_PODF_B_MASK 0x7u -#define CCM_PRE9_PRE_PODF_B_SHIFT 0 -#define CCM_PRE9_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE9_PRE_PODF_B_SHIFT))&CCM_PRE9_PRE_PODF_B_MASK) -#define CCM_PRE9_BUSY0_MASK 0x8u -#define CCM_PRE9_BUSY0_SHIFT 3 -#define CCM_PRE9_MUX_B_MASK 0x700u -#define CCM_PRE9_MUX_B_SHIFT 8 -#define CCM_PRE9_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE9_MUX_B_SHIFT))&CCM_PRE9_MUX_B_MASK) -#define CCM_PRE9_EN_B_MASK 0x1000u -#define CCM_PRE9_EN_B_SHIFT 12 -#define CCM_PRE9_BUSY1_MASK 0x8000u -#define CCM_PRE9_BUSY1_SHIFT 15 -#define CCM_PRE9_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE9_PRE_PODF_A_SHIFT 16 -#define CCM_PRE9_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE9_PRE_PODF_A_SHIFT))&CCM_PRE9_PRE_PODF_A_MASK) -#define CCM_PRE9_BUSY3_MASK 0x80000u -#define CCM_PRE9_BUSY3_SHIFT 19 -#define CCM_PRE9_MUX_A_MASK 0x7000000u -#define CCM_PRE9_MUX_A_SHIFT 24 -#define CCM_PRE9_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE9_MUX_A_SHIFT))&CCM_PRE9_MUX_A_MASK) -#define CCM_PRE9_EN_A_MASK 0x10000000u -#define CCM_PRE9_EN_A_SHIFT 28 -#define CCM_PRE9_BUSY4_MASK 0x80000000u -#define CCM_PRE9_BUSY4_SHIFT 31 -/* PRE_ROOT9_SET Bit Fields */ -#define CCM_PRE_ROOT9_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT9_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT9_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT9_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT9_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT9_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT9_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT9_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT9_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_SET_MUX_B_SHIFT))&CCM_PRE_ROOT9_SET_MUX_B_MASK) -#define CCM_PRE_ROOT9_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT9_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT9_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT9_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT9_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT9_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT9_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT9_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT9_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT9_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT9_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT9_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT9_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_SET_MUX_A_SHIFT))&CCM_PRE_ROOT9_SET_MUX_A_MASK) -#define CCM_PRE_ROOT9_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT9_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT9_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT9_SET_BUSY4_SHIFT 31 -/* PRE_ROOT9_CLR Bit Fields */ -#define CCM_PRE_ROOT9_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT9_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT9_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT9_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT9_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT9_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT9_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT9_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT9_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT9_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT9_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT9_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT9_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT9_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT9_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT9_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT9_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT9_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT9_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT9_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT9_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT9_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT9_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT9_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT9_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT9_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT9_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT9_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT9_TOG Bit Fields */ -#define CCM_PRE_ROOT9_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT9_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT9_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT9_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT9_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT9_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT9_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT9_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT9_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT9_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT9_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT9_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT9_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT9_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT9_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT9_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT9_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT9_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT9_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT9_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT9_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT9_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT9_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT9_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT9_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT9_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT9_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT9_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL9 Bit Fields */ -#define CCM_ACCESS_CTRL9_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL9_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL9_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL9_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL9_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL9_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL9_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL9_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL9_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL9_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL9_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL9_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL9_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL9_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL9_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL9_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL9_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL9_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL9_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL9_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL9_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL9_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL9_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL9_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL9_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL9_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL9_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL9_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL9_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL9_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL9_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL9_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL9_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL9_LOCK_SHIFT 31 -/* ACCESS_CTRL9_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL9_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL9_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL9_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL9_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL9_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL9_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL9_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL9_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL9_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL9_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL9_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL9_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL9_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL9_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL9_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL9_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT10 Bit Fields */ -#define CCM_TARGET_ROOT10_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT10_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT10_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_POST_PODF_SHIFT))&CCM_TARGET_ROOT10_POST_PODF_MASK) -#define CCM_TARGET_ROOT10_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT10_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT10_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT10_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT10_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT10_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT10_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT10_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT10_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT10_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT10_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_PRE_PODF_SHIFT))&CCM_TARGET_ROOT10_PRE_PODF_MASK) -#define CCM_TARGET_ROOT10_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT10_MUX_SHIFT 24 -#define CCM_TARGET_ROOT10_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_MUX_SHIFT))&CCM_TARGET_ROOT10_MUX_MASK) -#define CCM_TARGET_ROOT10_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT10_ENABLE_SHIFT 28 -/* TARGET_ROOT10_SET Bit Fields */ -#define CCM_TARGET_ROOT10_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT10_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT10_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT10_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT10_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT10_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT10_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT10_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT10_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT10_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT10_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT10_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT10_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT10_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT10_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT10_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT10_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT10_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT10_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_SET_MUX_SHIFT))&CCM_TARGET_ROOT10_SET_MUX_MASK) -#define CCM_TARGET_ROOT10_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT10_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT10_CLR Bit Fields */ -#define CCM_TARGET_ROOT10_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT10_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT10_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT10_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT10_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT10_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT10_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT10_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT10_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT10_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT10_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT10_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT10_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT10_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT10_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT10_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT10_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT10_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT10_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_CLR_MUX_SHIFT))&CCM_TARGET_ROOT10_CLR_MUX_MASK) -#define CCM_TARGET_ROOT10_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT10_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT10_TOG Bit Fields */ -#define CCM_TARGET_ROOT10_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT10_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT10_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT10_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT10_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT10_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT10_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT10_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT10_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT10_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT10_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT10_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT10_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT10_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT10_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT10_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT10_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT10_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT10_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_TOG_MUX_SHIFT))&CCM_TARGET_ROOT10_TOG_MUX_MASK) -#define CCM_TARGET_ROOT10_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT10_TOG_ENABLE_SHIFT 28 -/* POST10 Bit Fields */ -#define CCM_POST10_POST_PODF_MASK 0x3Fu -#define CCM_POST10_POST_PODF_SHIFT 0 -#define CCM_POST10_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST10_POST_PODF_SHIFT))&CCM_POST10_POST_PODF_MASK) -#define CCM_POST10_BUSY1_MASK 0x80u -#define CCM_POST10_BUSY1_SHIFT 7 -#define CCM_POST10_AUTO_PODF_MASK 0x700u -#define CCM_POST10_AUTO_PODF_SHIFT 8 -#define CCM_POST10_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST10_AUTO_PODF_SHIFT))&CCM_POST10_AUTO_PODF_MASK) -#define CCM_POST10_AUTO_EN_MASK 0x1000u -#define CCM_POST10_AUTO_EN_SHIFT 12 -#define CCM_POST10_SLOW_MASK 0x8000u -#define CCM_POST10_SLOW_SHIFT 15 -#define CCM_POST10_SELECT_MASK 0x10000000u -#define CCM_POST10_SELECT_SHIFT 28 -#define CCM_POST10_BUSY2_MASK 0x80000000u -#define CCM_POST10_BUSY2_SHIFT 31 -/* POST_ROOT10_SET Bit Fields */ -#define CCM_POST_ROOT10_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT10_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT10_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_SET_POST_PODF_SHIFT))&CCM_POST_ROOT10_SET_POST_PODF_MASK) -#define CCM_POST_ROOT10_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT10_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT10_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT10_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT10_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT10_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT10_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT10_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT10_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT10_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT10_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT10_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT10_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT10_SET_BUSY2_SHIFT 31 -/* POST_ROOT10_CLR Bit Fields */ -#define CCM_POST_ROOT10_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT10_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT10_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT10_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT10_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT10_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT10_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT10_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT10_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT10_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT10_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT10_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT10_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT10_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT10_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT10_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT10_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT10_CLR_BUSY2_SHIFT 31 -/* POST_ROOT10_TOG Bit Fields */ -#define CCM_POST_ROOT10_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT10_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT10_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT10_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT10_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT10_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT10_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT10_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT10_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT10_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT10_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT10_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT10_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT10_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT10_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT10_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT10_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT10_TOG_BUSY2_SHIFT 31 -/* PRE10 Bit Fields */ -#define CCM_PRE10_PRE_PODF_B_MASK 0x7u -#define CCM_PRE10_PRE_PODF_B_SHIFT 0 -#define CCM_PRE10_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE10_PRE_PODF_B_SHIFT))&CCM_PRE10_PRE_PODF_B_MASK) -#define CCM_PRE10_BUSY0_MASK 0x8u -#define CCM_PRE10_BUSY0_SHIFT 3 -#define CCM_PRE10_MUX_B_MASK 0x700u -#define CCM_PRE10_MUX_B_SHIFT 8 -#define CCM_PRE10_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE10_MUX_B_SHIFT))&CCM_PRE10_MUX_B_MASK) -#define CCM_PRE10_EN_B_MASK 0x1000u -#define CCM_PRE10_EN_B_SHIFT 12 -#define CCM_PRE10_BUSY1_MASK 0x8000u -#define CCM_PRE10_BUSY1_SHIFT 15 -#define CCM_PRE10_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE10_PRE_PODF_A_SHIFT 16 -#define CCM_PRE10_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE10_PRE_PODF_A_SHIFT))&CCM_PRE10_PRE_PODF_A_MASK) -#define CCM_PRE10_BUSY3_MASK 0x80000u -#define CCM_PRE10_BUSY3_SHIFT 19 -#define CCM_PRE10_MUX_A_MASK 0x7000000u -#define CCM_PRE10_MUX_A_SHIFT 24 -#define CCM_PRE10_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE10_MUX_A_SHIFT))&CCM_PRE10_MUX_A_MASK) -#define CCM_PRE10_EN_A_MASK 0x10000000u -#define CCM_PRE10_EN_A_SHIFT 28 -#define CCM_PRE10_BUSY4_MASK 0x80000000u -#define CCM_PRE10_BUSY4_SHIFT 31 -/* PRE_ROOT10_SET Bit Fields */ -#define CCM_PRE_ROOT10_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT10_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT10_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT10_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT10_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT10_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT10_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT10_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT10_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_SET_MUX_B_SHIFT))&CCM_PRE_ROOT10_SET_MUX_B_MASK) -#define CCM_PRE_ROOT10_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT10_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT10_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT10_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT10_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT10_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT10_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT10_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT10_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT10_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT10_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT10_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT10_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_SET_MUX_A_SHIFT))&CCM_PRE_ROOT10_SET_MUX_A_MASK) -#define CCM_PRE_ROOT10_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT10_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT10_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT10_SET_BUSY4_SHIFT 31 -/* PRE_ROOT10_CLR Bit Fields */ -#define CCM_PRE_ROOT10_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT10_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT10_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT10_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT10_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT10_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT10_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT10_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT10_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT10_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT10_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT10_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT10_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT10_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT10_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT10_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT10_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT10_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT10_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT10_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT10_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT10_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT10_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT10_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT10_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT10_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT10_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT10_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT10_TOG Bit Fields */ -#define CCM_PRE_ROOT10_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT10_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT10_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT10_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT10_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT10_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT10_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT10_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT10_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT10_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT10_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT10_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT10_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT10_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT10_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT10_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT10_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT10_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT10_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT10_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT10_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT10_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT10_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT10_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT10_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT10_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT10_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT10_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL10 Bit Fields */ -#define CCM_ACCESS_CTRL10_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL10_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL10_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL10_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL10_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL10_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL10_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL10_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL10_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL10_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL10_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL10_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL10_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL10_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL10_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL10_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL10_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL10_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL10_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL10_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL10_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL10_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL10_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL10_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL10_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL10_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL10_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL10_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL10_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL10_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL10_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL10_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL10_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL10_LOCK_SHIFT 31 -/* ACCESS_CTRL10_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL10_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL10_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL10_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL10_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL10_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL10_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL10_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL10_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL10_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL10_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL10_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL10_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL10_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL10_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL10_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL10_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT11 Bit Fields */ -#define CCM_TARGET_ROOT11_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT11_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT11_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_POST_PODF_SHIFT))&CCM_TARGET_ROOT11_POST_PODF_MASK) -#define CCM_TARGET_ROOT11_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT11_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT11_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT11_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT11_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT11_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT11_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT11_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT11_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT11_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT11_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_PRE_PODF_SHIFT))&CCM_TARGET_ROOT11_PRE_PODF_MASK) -#define CCM_TARGET_ROOT11_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT11_MUX_SHIFT 24 -#define CCM_TARGET_ROOT11_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_MUX_SHIFT))&CCM_TARGET_ROOT11_MUX_MASK) -#define CCM_TARGET_ROOT11_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT11_ENABLE_SHIFT 28 -/* TARGET_ROOT11_SET Bit Fields */ -#define CCM_TARGET_ROOT11_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT11_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT11_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT11_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT11_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT11_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT11_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT11_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT11_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT11_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT11_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT11_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT11_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT11_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT11_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT11_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT11_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT11_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT11_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_SET_MUX_SHIFT))&CCM_TARGET_ROOT11_SET_MUX_MASK) -#define CCM_TARGET_ROOT11_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT11_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT11_CLR Bit Fields */ -#define CCM_TARGET_ROOT11_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT11_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT11_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT11_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT11_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT11_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT11_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT11_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT11_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT11_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT11_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT11_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT11_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT11_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT11_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT11_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT11_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT11_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT11_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_CLR_MUX_SHIFT))&CCM_TARGET_ROOT11_CLR_MUX_MASK) -#define CCM_TARGET_ROOT11_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT11_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT11_TOG Bit Fields */ -#define CCM_TARGET_ROOT11_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT11_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT11_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT11_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT11_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT11_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT11_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT11_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT11_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT11_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT11_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT11_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT11_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT11_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT11_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT11_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT11_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT11_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT11_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_TOG_MUX_SHIFT))&CCM_TARGET_ROOT11_TOG_MUX_MASK) -#define CCM_TARGET_ROOT11_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT11_TOG_ENABLE_SHIFT 28 -/* POST11 Bit Fields */ -#define CCM_POST11_POST_PODF_MASK 0x3Fu -#define CCM_POST11_POST_PODF_SHIFT 0 -#define CCM_POST11_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST11_POST_PODF_SHIFT))&CCM_POST11_POST_PODF_MASK) -#define CCM_POST11_BUSY1_MASK 0x80u -#define CCM_POST11_BUSY1_SHIFT 7 -#define CCM_POST11_AUTO_PODF_MASK 0x700u -#define CCM_POST11_AUTO_PODF_SHIFT 8 -#define CCM_POST11_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST11_AUTO_PODF_SHIFT))&CCM_POST11_AUTO_PODF_MASK) -#define CCM_POST11_AUTO_EN_MASK 0x1000u -#define CCM_POST11_AUTO_EN_SHIFT 12 -#define CCM_POST11_SLOW_MASK 0x8000u -#define CCM_POST11_SLOW_SHIFT 15 -#define CCM_POST11_SELECT_MASK 0x10000000u -#define CCM_POST11_SELECT_SHIFT 28 -#define CCM_POST11_BUSY2_MASK 0x80000000u -#define CCM_POST11_BUSY2_SHIFT 31 -/* POST_ROOT11_SET Bit Fields */ -#define CCM_POST_ROOT11_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT11_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT11_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_SET_POST_PODF_SHIFT))&CCM_POST_ROOT11_SET_POST_PODF_MASK) -#define CCM_POST_ROOT11_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT11_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT11_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT11_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT11_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT11_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT11_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT11_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT11_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT11_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT11_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT11_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT11_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT11_SET_BUSY2_SHIFT 31 -/* POST_ROOT11_CLR Bit Fields */ -#define CCM_POST_ROOT11_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT11_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT11_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT11_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT11_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT11_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT11_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT11_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT11_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT11_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT11_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT11_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT11_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT11_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT11_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT11_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT11_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT11_CLR_BUSY2_SHIFT 31 -/* POST_ROOT11_TOG Bit Fields */ -#define CCM_POST_ROOT11_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT11_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT11_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT11_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT11_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT11_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT11_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT11_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT11_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT11_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT11_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT11_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT11_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT11_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT11_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT11_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT11_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT11_TOG_BUSY2_SHIFT 31 -/* PRE11 Bit Fields */ -#define CCM_PRE11_PRE_PODF_B_MASK 0x7u -#define CCM_PRE11_PRE_PODF_B_SHIFT 0 -#define CCM_PRE11_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE11_PRE_PODF_B_SHIFT))&CCM_PRE11_PRE_PODF_B_MASK) -#define CCM_PRE11_BUSY0_MASK 0x8u -#define CCM_PRE11_BUSY0_SHIFT 3 -#define CCM_PRE11_MUX_B_MASK 0x700u -#define CCM_PRE11_MUX_B_SHIFT 8 -#define CCM_PRE11_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE11_MUX_B_SHIFT))&CCM_PRE11_MUX_B_MASK) -#define CCM_PRE11_EN_B_MASK 0x1000u -#define CCM_PRE11_EN_B_SHIFT 12 -#define CCM_PRE11_BUSY1_MASK 0x8000u -#define CCM_PRE11_BUSY1_SHIFT 15 -#define CCM_PRE11_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE11_PRE_PODF_A_SHIFT 16 -#define CCM_PRE11_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE11_PRE_PODF_A_SHIFT))&CCM_PRE11_PRE_PODF_A_MASK) -#define CCM_PRE11_BUSY3_MASK 0x80000u -#define CCM_PRE11_BUSY3_SHIFT 19 -#define CCM_PRE11_MUX_A_MASK 0x7000000u -#define CCM_PRE11_MUX_A_SHIFT 24 -#define CCM_PRE11_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE11_MUX_A_SHIFT))&CCM_PRE11_MUX_A_MASK) -#define CCM_PRE11_EN_A_MASK 0x10000000u -#define CCM_PRE11_EN_A_SHIFT 28 -#define CCM_PRE11_BUSY4_MASK 0x80000000u -#define CCM_PRE11_BUSY4_SHIFT 31 -/* PRE_ROOT11_SET Bit Fields */ -#define CCM_PRE_ROOT11_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT11_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT11_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT11_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT11_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT11_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT11_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT11_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT11_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_SET_MUX_B_SHIFT))&CCM_PRE_ROOT11_SET_MUX_B_MASK) -#define CCM_PRE_ROOT11_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT11_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT11_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT11_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT11_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT11_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT11_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT11_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT11_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT11_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT11_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT11_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT11_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_SET_MUX_A_SHIFT))&CCM_PRE_ROOT11_SET_MUX_A_MASK) -#define CCM_PRE_ROOT11_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT11_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT11_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT11_SET_BUSY4_SHIFT 31 -/* PRE_ROOT11_CLR Bit Fields */ -#define CCM_PRE_ROOT11_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT11_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT11_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT11_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT11_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT11_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT11_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT11_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT11_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT11_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT11_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT11_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT11_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT11_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT11_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT11_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT11_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT11_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT11_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT11_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT11_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT11_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT11_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT11_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT11_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT11_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT11_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT11_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT11_TOG Bit Fields */ -#define CCM_PRE_ROOT11_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT11_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT11_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT11_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT11_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT11_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT11_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT11_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT11_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT11_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT11_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT11_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT11_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT11_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT11_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT11_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT11_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT11_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT11_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT11_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT11_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT11_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT11_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT11_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT11_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT11_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT11_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT11_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL11 Bit Fields */ -#define CCM_ACCESS_CTRL11_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL11_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL11_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL11_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL11_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL11_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL11_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL11_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL11_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL11_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL11_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL11_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL11_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL11_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL11_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL11_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL11_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL11_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL11_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL11_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL11_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL11_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL11_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL11_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL11_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL11_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL11_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL11_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL11_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL11_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL11_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL11_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL11_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL11_LOCK_SHIFT 31 -/* ACCESS_CTRL11_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL11_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL11_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL11_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL11_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL11_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL11_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL11_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL11_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL11_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL11_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL11_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL11_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL11_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL11_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL11_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL11_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT12 Bit Fields */ -#define CCM_TARGET_ROOT12_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT12_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT12_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_POST_PODF_SHIFT))&CCM_TARGET_ROOT12_POST_PODF_MASK) -#define CCM_TARGET_ROOT12_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT12_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT12_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT12_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT12_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT12_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT12_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT12_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT12_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT12_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT12_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_PRE_PODF_SHIFT))&CCM_TARGET_ROOT12_PRE_PODF_MASK) -#define CCM_TARGET_ROOT12_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT12_MUX_SHIFT 24 -#define CCM_TARGET_ROOT12_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_MUX_SHIFT))&CCM_TARGET_ROOT12_MUX_MASK) -#define CCM_TARGET_ROOT12_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT12_ENABLE_SHIFT 28 -/* TARGET_ROOT12_SET Bit Fields */ -#define CCM_TARGET_ROOT12_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT12_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT12_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT12_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT12_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT12_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT12_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT12_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT12_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT12_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT12_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT12_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT12_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT12_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT12_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT12_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT12_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT12_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT12_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_SET_MUX_SHIFT))&CCM_TARGET_ROOT12_SET_MUX_MASK) -#define CCM_TARGET_ROOT12_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT12_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT12_CLR Bit Fields */ -#define CCM_TARGET_ROOT12_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT12_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT12_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT12_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT12_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT12_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT12_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT12_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT12_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT12_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT12_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT12_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT12_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT12_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT12_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT12_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT12_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT12_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT12_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_CLR_MUX_SHIFT))&CCM_TARGET_ROOT12_CLR_MUX_MASK) -#define CCM_TARGET_ROOT12_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT12_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT12_TOG Bit Fields */ -#define CCM_TARGET_ROOT12_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT12_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT12_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT12_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT12_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT12_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT12_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT12_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT12_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT12_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT12_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT12_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT12_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT12_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT12_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT12_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT12_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT12_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT12_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_TOG_MUX_SHIFT))&CCM_TARGET_ROOT12_TOG_MUX_MASK) -#define CCM_TARGET_ROOT12_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT12_TOG_ENABLE_SHIFT 28 -/* POST12 Bit Fields */ -#define CCM_POST12_POST_PODF_MASK 0x3Fu -#define CCM_POST12_POST_PODF_SHIFT 0 -#define CCM_POST12_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST12_POST_PODF_SHIFT))&CCM_POST12_POST_PODF_MASK) -#define CCM_POST12_BUSY1_MASK 0x80u -#define CCM_POST12_BUSY1_SHIFT 7 -#define CCM_POST12_AUTO_PODF_MASK 0x700u -#define CCM_POST12_AUTO_PODF_SHIFT 8 -#define CCM_POST12_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST12_AUTO_PODF_SHIFT))&CCM_POST12_AUTO_PODF_MASK) -#define CCM_POST12_AUTO_EN_MASK 0x1000u -#define CCM_POST12_AUTO_EN_SHIFT 12 -#define CCM_POST12_SLOW_MASK 0x8000u -#define CCM_POST12_SLOW_SHIFT 15 -#define CCM_POST12_SELECT_MASK 0x10000000u -#define CCM_POST12_SELECT_SHIFT 28 -#define CCM_POST12_BUSY2_MASK 0x80000000u -#define CCM_POST12_BUSY2_SHIFT 31 -/* POST_ROOT12_SET Bit Fields */ -#define CCM_POST_ROOT12_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT12_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT12_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_SET_POST_PODF_SHIFT))&CCM_POST_ROOT12_SET_POST_PODF_MASK) -#define CCM_POST_ROOT12_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT12_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT12_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT12_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT12_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT12_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT12_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT12_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT12_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT12_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT12_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT12_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT12_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT12_SET_BUSY2_SHIFT 31 -/* POST_ROOT12_CLR Bit Fields */ -#define CCM_POST_ROOT12_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT12_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT12_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT12_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT12_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT12_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT12_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT12_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT12_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT12_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT12_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT12_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT12_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT12_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT12_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT12_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT12_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT12_CLR_BUSY2_SHIFT 31 -/* POST_ROOT12_TOG Bit Fields */ -#define CCM_POST_ROOT12_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT12_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT12_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT12_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT12_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT12_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT12_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT12_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT12_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT12_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT12_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT12_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT12_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT12_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT12_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT12_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT12_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT12_TOG_BUSY2_SHIFT 31 -/* PRE12 Bit Fields */ -#define CCM_PRE12_PRE_PODF_B_MASK 0x7u -#define CCM_PRE12_PRE_PODF_B_SHIFT 0 -#define CCM_PRE12_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE12_PRE_PODF_B_SHIFT))&CCM_PRE12_PRE_PODF_B_MASK) -#define CCM_PRE12_BUSY0_MASK 0x8u -#define CCM_PRE12_BUSY0_SHIFT 3 -#define CCM_PRE12_MUX_B_MASK 0x700u -#define CCM_PRE12_MUX_B_SHIFT 8 -#define CCM_PRE12_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE12_MUX_B_SHIFT))&CCM_PRE12_MUX_B_MASK) -#define CCM_PRE12_EN_B_MASK 0x1000u -#define CCM_PRE12_EN_B_SHIFT 12 -#define CCM_PRE12_BUSY1_MASK 0x8000u -#define CCM_PRE12_BUSY1_SHIFT 15 -#define CCM_PRE12_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE12_PRE_PODF_A_SHIFT 16 -#define CCM_PRE12_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE12_PRE_PODF_A_SHIFT))&CCM_PRE12_PRE_PODF_A_MASK) -#define CCM_PRE12_BUSY3_MASK 0x80000u -#define CCM_PRE12_BUSY3_SHIFT 19 -#define CCM_PRE12_MUX_A_MASK 0x7000000u -#define CCM_PRE12_MUX_A_SHIFT 24 -#define CCM_PRE12_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE12_MUX_A_SHIFT))&CCM_PRE12_MUX_A_MASK) -#define CCM_PRE12_EN_A_MASK 0x10000000u -#define CCM_PRE12_EN_A_SHIFT 28 -#define CCM_PRE12_BUSY4_MASK 0x80000000u -#define CCM_PRE12_BUSY4_SHIFT 31 -/* PRE_ROOT12_SET Bit Fields */ -#define CCM_PRE_ROOT12_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT12_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT12_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT12_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT12_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT12_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT12_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT12_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT12_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_SET_MUX_B_SHIFT))&CCM_PRE_ROOT12_SET_MUX_B_MASK) -#define CCM_PRE_ROOT12_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT12_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT12_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT12_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT12_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT12_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT12_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT12_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT12_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT12_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT12_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT12_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT12_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_SET_MUX_A_SHIFT))&CCM_PRE_ROOT12_SET_MUX_A_MASK) -#define CCM_PRE_ROOT12_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT12_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT12_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT12_SET_BUSY4_SHIFT 31 -/* PRE_ROOT12_CLR Bit Fields */ -#define CCM_PRE_ROOT12_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT12_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT12_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT12_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT12_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT12_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT12_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT12_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT12_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT12_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT12_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT12_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT12_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT12_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT12_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT12_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT12_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT12_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT12_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT12_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT12_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT12_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT12_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT12_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT12_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT12_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT12_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT12_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT12_TOG Bit Fields */ -#define CCM_PRE_ROOT12_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT12_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT12_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT12_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT12_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT12_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT12_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT12_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT12_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT12_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT12_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT12_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT12_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT12_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT12_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT12_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT12_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT12_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT12_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT12_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT12_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT12_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT12_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT12_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT12_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT12_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT12_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT12_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL12 Bit Fields */ -#define CCM_ACCESS_CTRL12_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL12_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL12_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL12_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL12_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL12_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL12_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL12_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL12_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL12_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL12_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL12_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL12_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL12_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL12_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL12_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL12_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL12_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL12_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL12_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL12_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL12_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL12_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL12_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL12_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL12_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL12_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL12_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL12_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL12_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL12_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL12_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL12_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL12_LOCK_SHIFT 31 -/* ACCESS_CTRL12_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL12_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL12_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL12_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL12_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL12_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL12_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL12_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL12_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL12_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL12_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL12_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL12_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL12_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL12_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL12_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL12_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT13 Bit Fields */ -#define CCM_TARGET_ROOT13_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT13_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT13_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_POST_PODF_SHIFT))&CCM_TARGET_ROOT13_POST_PODF_MASK) -#define CCM_TARGET_ROOT13_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT13_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT13_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT13_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT13_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT13_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT13_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT13_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT13_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT13_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT13_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_PRE_PODF_SHIFT))&CCM_TARGET_ROOT13_PRE_PODF_MASK) -#define CCM_TARGET_ROOT13_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT13_MUX_SHIFT 24 -#define CCM_TARGET_ROOT13_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_MUX_SHIFT))&CCM_TARGET_ROOT13_MUX_MASK) -#define CCM_TARGET_ROOT13_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT13_ENABLE_SHIFT 28 -/* TARGET_ROOT13_SET Bit Fields */ -#define CCM_TARGET_ROOT13_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT13_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT13_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT13_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT13_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT13_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT13_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT13_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT13_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT13_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT13_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT13_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT13_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT13_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT13_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT13_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT13_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT13_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT13_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_SET_MUX_SHIFT))&CCM_TARGET_ROOT13_SET_MUX_MASK) -#define CCM_TARGET_ROOT13_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT13_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT13_CLR Bit Fields */ -#define CCM_TARGET_ROOT13_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT13_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT13_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT13_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT13_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT13_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT13_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT13_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT13_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT13_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT13_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT13_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT13_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT13_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT13_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT13_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT13_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT13_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT13_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_CLR_MUX_SHIFT))&CCM_TARGET_ROOT13_CLR_MUX_MASK) -#define CCM_TARGET_ROOT13_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT13_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT13_TOG Bit Fields */ -#define CCM_TARGET_ROOT13_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT13_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT13_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT13_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT13_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT13_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT13_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT13_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT13_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT13_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT13_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT13_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT13_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT13_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT13_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT13_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT13_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT13_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT13_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_TOG_MUX_SHIFT))&CCM_TARGET_ROOT13_TOG_MUX_MASK) -#define CCM_TARGET_ROOT13_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT13_TOG_ENABLE_SHIFT 28 -/* POST13 Bit Fields */ -#define CCM_POST13_POST_PODF_MASK 0x3Fu -#define CCM_POST13_POST_PODF_SHIFT 0 -#define CCM_POST13_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST13_POST_PODF_SHIFT))&CCM_POST13_POST_PODF_MASK) -#define CCM_POST13_BUSY1_MASK 0x80u -#define CCM_POST13_BUSY1_SHIFT 7 -#define CCM_POST13_AUTO_PODF_MASK 0x700u -#define CCM_POST13_AUTO_PODF_SHIFT 8 -#define CCM_POST13_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST13_AUTO_PODF_SHIFT))&CCM_POST13_AUTO_PODF_MASK) -#define CCM_POST13_AUTO_EN_MASK 0x1000u -#define CCM_POST13_AUTO_EN_SHIFT 12 -#define CCM_POST13_SLOW_MASK 0x8000u -#define CCM_POST13_SLOW_SHIFT 15 -#define CCM_POST13_SELECT_MASK 0x10000000u -#define CCM_POST13_SELECT_SHIFT 28 -#define CCM_POST13_BUSY2_MASK 0x80000000u -#define CCM_POST13_BUSY2_SHIFT 31 -/* POST_ROOT13_SET Bit Fields */ -#define CCM_POST_ROOT13_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT13_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT13_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_SET_POST_PODF_SHIFT))&CCM_POST_ROOT13_SET_POST_PODF_MASK) -#define CCM_POST_ROOT13_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT13_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT13_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT13_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT13_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT13_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT13_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT13_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT13_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT13_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT13_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT13_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT13_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT13_SET_BUSY2_SHIFT 31 -/* POST_ROOT13_CLR Bit Fields */ -#define CCM_POST_ROOT13_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT13_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT13_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT13_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT13_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT13_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT13_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT13_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT13_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT13_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT13_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT13_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT13_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT13_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT13_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT13_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT13_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT13_CLR_BUSY2_SHIFT 31 -/* POST_ROOT13_TOG Bit Fields */ -#define CCM_POST_ROOT13_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT13_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT13_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT13_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT13_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT13_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT13_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT13_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT13_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT13_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT13_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT13_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT13_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT13_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT13_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT13_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT13_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT13_TOG_BUSY2_SHIFT 31 -/* PRE13 Bit Fields */ -#define CCM_PRE13_PRE_PODF_B_MASK 0x7u -#define CCM_PRE13_PRE_PODF_B_SHIFT 0 -#define CCM_PRE13_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE13_PRE_PODF_B_SHIFT))&CCM_PRE13_PRE_PODF_B_MASK) -#define CCM_PRE13_BUSY0_MASK 0x8u -#define CCM_PRE13_BUSY0_SHIFT 3 -#define CCM_PRE13_MUX_B_MASK 0x700u -#define CCM_PRE13_MUX_B_SHIFT 8 -#define CCM_PRE13_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE13_MUX_B_SHIFT))&CCM_PRE13_MUX_B_MASK) -#define CCM_PRE13_EN_B_MASK 0x1000u -#define CCM_PRE13_EN_B_SHIFT 12 -#define CCM_PRE13_BUSY1_MASK 0x8000u -#define CCM_PRE13_BUSY1_SHIFT 15 -#define CCM_PRE13_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE13_PRE_PODF_A_SHIFT 16 -#define CCM_PRE13_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE13_PRE_PODF_A_SHIFT))&CCM_PRE13_PRE_PODF_A_MASK) -#define CCM_PRE13_BUSY3_MASK 0x80000u -#define CCM_PRE13_BUSY3_SHIFT 19 -#define CCM_PRE13_MUX_A_MASK 0x7000000u -#define CCM_PRE13_MUX_A_SHIFT 24 -#define CCM_PRE13_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE13_MUX_A_SHIFT))&CCM_PRE13_MUX_A_MASK) -#define CCM_PRE13_EN_A_MASK 0x10000000u -#define CCM_PRE13_EN_A_SHIFT 28 -#define CCM_PRE13_BUSY4_MASK 0x80000000u -#define CCM_PRE13_BUSY4_SHIFT 31 -/* PRE_ROOT13_SET Bit Fields */ -#define CCM_PRE_ROOT13_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT13_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT13_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT13_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT13_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT13_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT13_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT13_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT13_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_SET_MUX_B_SHIFT))&CCM_PRE_ROOT13_SET_MUX_B_MASK) -#define CCM_PRE_ROOT13_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT13_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT13_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT13_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT13_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT13_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT13_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT13_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT13_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT13_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT13_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT13_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT13_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_SET_MUX_A_SHIFT))&CCM_PRE_ROOT13_SET_MUX_A_MASK) -#define CCM_PRE_ROOT13_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT13_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT13_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT13_SET_BUSY4_SHIFT 31 -/* PRE_ROOT13_CLR Bit Fields */ -#define CCM_PRE_ROOT13_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT13_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT13_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT13_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT13_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT13_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT13_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT13_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT13_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT13_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT13_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT13_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT13_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT13_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT13_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT13_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT13_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT13_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT13_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT13_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT13_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT13_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT13_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT13_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT13_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT13_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT13_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT13_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT13_TOG Bit Fields */ -#define CCM_PRE_ROOT13_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT13_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT13_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT13_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT13_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT13_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT13_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT13_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT13_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT13_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT13_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT13_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT13_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT13_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT13_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT13_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT13_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT13_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT13_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT13_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT13_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT13_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT13_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT13_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT13_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT13_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT13_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT13_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL13 Bit Fields */ -#define CCM_ACCESS_CTRL13_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL13_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL13_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL13_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL13_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL13_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL13_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL13_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL13_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL13_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL13_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL13_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL13_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL13_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL13_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL13_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL13_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL13_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL13_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL13_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL13_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL13_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL13_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL13_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL13_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL13_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL13_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL13_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL13_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL13_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL13_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL13_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL13_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL13_LOCK_SHIFT 31 -/* ACCESS_CTRL13_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL13_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL13_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL13_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL13_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL13_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL13_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL13_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL13_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL13_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL13_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL13_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL13_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL13_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL13_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL13_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL13_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT14 Bit Fields */ -#define CCM_TARGET_ROOT14_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT14_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT14_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_POST_PODF_SHIFT))&CCM_TARGET_ROOT14_POST_PODF_MASK) -#define CCM_TARGET_ROOT14_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT14_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT14_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT14_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT14_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT14_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT14_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT14_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT14_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT14_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT14_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_PRE_PODF_SHIFT))&CCM_TARGET_ROOT14_PRE_PODF_MASK) -#define CCM_TARGET_ROOT14_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT14_MUX_SHIFT 24 -#define CCM_TARGET_ROOT14_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_MUX_SHIFT))&CCM_TARGET_ROOT14_MUX_MASK) -#define CCM_TARGET_ROOT14_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT14_ENABLE_SHIFT 28 -/* TARGET_ROOT14_SET Bit Fields */ -#define CCM_TARGET_ROOT14_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT14_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT14_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT14_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT14_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT14_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT14_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT14_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT14_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT14_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT14_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT14_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT14_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT14_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT14_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT14_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT14_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT14_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT14_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_SET_MUX_SHIFT))&CCM_TARGET_ROOT14_SET_MUX_MASK) -#define CCM_TARGET_ROOT14_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT14_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT14_CLR Bit Fields */ -#define CCM_TARGET_ROOT14_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT14_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT14_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT14_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT14_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT14_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT14_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT14_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT14_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT14_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT14_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT14_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT14_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT14_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT14_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT14_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT14_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT14_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT14_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_CLR_MUX_SHIFT))&CCM_TARGET_ROOT14_CLR_MUX_MASK) -#define CCM_TARGET_ROOT14_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT14_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT14_TOG Bit Fields */ -#define CCM_TARGET_ROOT14_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT14_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT14_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT14_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT14_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT14_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT14_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT14_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT14_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT14_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT14_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT14_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT14_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT14_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT14_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT14_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT14_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT14_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT14_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_TOG_MUX_SHIFT))&CCM_TARGET_ROOT14_TOG_MUX_MASK) -#define CCM_TARGET_ROOT14_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT14_TOG_ENABLE_SHIFT 28 -/* POST14 Bit Fields */ -#define CCM_POST14_POST_PODF_MASK 0x3Fu -#define CCM_POST14_POST_PODF_SHIFT 0 -#define CCM_POST14_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST14_POST_PODF_SHIFT))&CCM_POST14_POST_PODF_MASK) -#define CCM_POST14_BUSY1_MASK 0x80u -#define CCM_POST14_BUSY1_SHIFT 7 -#define CCM_POST14_AUTO_PODF_MASK 0x700u -#define CCM_POST14_AUTO_PODF_SHIFT 8 -#define CCM_POST14_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST14_AUTO_PODF_SHIFT))&CCM_POST14_AUTO_PODF_MASK) -#define CCM_POST14_AUTO_EN_MASK 0x1000u -#define CCM_POST14_AUTO_EN_SHIFT 12 -#define CCM_POST14_SLOW_MASK 0x8000u -#define CCM_POST14_SLOW_SHIFT 15 -#define CCM_POST14_SELECT_MASK 0x10000000u -#define CCM_POST14_SELECT_SHIFT 28 -#define CCM_POST14_BUSY2_MASK 0x80000000u -#define CCM_POST14_BUSY2_SHIFT 31 -/* POST_ROOT14_SET Bit Fields */ -#define CCM_POST_ROOT14_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT14_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT14_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_SET_POST_PODF_SHIFT))&CCM_POST_ROOT14_SET_POST_PODF_MASK) -#define CCM_POST_ROOT14_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT14_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT14_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT14_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT14_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT14_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT14_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT14_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT14_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT14_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT14_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT14_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT14_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT14_SET_BUSY2_SHIFT 31 -/* POST_ROOT14_CLR Bit Fields */ -#define CCM_POST_ROOT14_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT14_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT14_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT14_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT14_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT14_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT14_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT14_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT14_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT14_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT14_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT14_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT14_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT14_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT14_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT14_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT14_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT14_CLR_BUSY2_SHIFT 31 -/* POST_ROOT14_TOG Bit Fields */ -#define CCM_POST_ROOT14_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT14_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT14_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT14_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT14_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT14_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT14_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT14_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT14_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT14_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT14_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT14_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT14_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT14_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT14_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT14_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT14_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT14_TOG_BUSY2_SHIFT 31 -/* PRE14 Bit Fields */ -#define CCM_PRE14_PRE_PODF_B_MASK 0x7u -#define CCM_PRE14_PRE_PODF_B_SHIFT 0 -#define CCM_PRE14_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE14_PRE_PODF_B_SHIFT))&CCM_PRE14_PRE_PODF_B_MASK) -#define CCM_PRE14_BUSY0_MASK 0x8u -#define CCM_PRE14_BUSY0_SHIFT 3 -#define CCM_PRE14_MUX_B_MASK 0x700u -#define CCM_PRE14_MUX_B_SHIFT 8 -#define CCM_PRE14_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE14_MUX_B_SHIFT))&CCM_PRE14_MUX_B_MASK) -#define CCM_PRE14_EN_B_MASK 0x1000u -#define CCM_PRE14_EN_B_SHIFT 12 -#define CCM_PRE14_BUSY1_MASK 0x8000u -#define CCM_PRE14_BUSY1_SHIFT 15 -#define CCM_PRE14_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE14_PRE_PODF_A_SHIFT 16 -#define CCM_PRE14_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE14_PRE_PODF_A_SHIFT))&CCM_PRE14_PRE_PODF_A_MASK) -#define CCM_PRE14_BUSY3_MASK 0x80000u -#define CCM_PRE14_BUSY3_SHIFT 19 -#define CCM_PRE14_MUX_A_MASK 0x7000000u -#define CCM_PRE14_MUX_A_SHIFT 24 -#define CCM_PRE14_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE14_MUX_A_SHIFT))&CCM_PRE14_MUX_A_MASK) -#define CCM_PRE14_EN_A_MASK 0x10000000u -#define CCM_PRE14_EN_A_SHIFT 28 -#define CCM_PRE14_BUSY4_MASK 0x80000000u -#define CCM_PRE14_BUSY4_SHIFT 31 -/* PRE_ROOT14_SET Bit Fields */ -#define CCM_PRE_ROOT14_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT14_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT14_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT14_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT14_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT14_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT14_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT14_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT14_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_SET_MUX_B_SHIFT))&CCM_PRE_ROOT14_SET_MUX_B_MASK) -#define CCM_PRE_ROOT14_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT14_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT14_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT14_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT14_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT14_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT14_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT14_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT14_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT14_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT14_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT14_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT14_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_SET_MUX_A_SHIFT))&CCM_PRE_ROOT14_SET_MUX_A_MASK) -#define CCM_PRE_ROOT14_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT14_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT14_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT14_SET_BUSY4_SHIFT 31 -/* PRE_ROOT14_CLR Bit Fields */ -#define CCM_PRE_ROOT14_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT14_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT14_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT14_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT14_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT14_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT14_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT14_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT14_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT14_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT14_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT14_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT14_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT14_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT14_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT14_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT14_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT14_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT14_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT14_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT14_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT14_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT14_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT14_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT14_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT14_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT14_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT14_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT14_TOG Bit Fields */ -#define CCM_PRE_ROOT14_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT14_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT14_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT14_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT14_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT14_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT14_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT14_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT14_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT14_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT14_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT14_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT14_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT14_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT14_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT14_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT14_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT14_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT14_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT14_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT14_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT14_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT14_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT14_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT14_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT14_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT14_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT14_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL14 Bit Fields */ -#define CCM_ACCESS_CTRL14_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL14_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL14_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL14_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL14_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL14_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL14_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL14_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL14_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL14_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL14_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL14_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL14_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL14_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL14_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL14_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL14_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL14_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL14_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL14_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL14_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL14_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL14_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL14_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL14_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL14_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL14_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL14_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL14_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL14_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL14_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL14_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL14_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL14_LOCK_SHIFT 31 -/* ACCESS_CTRL14_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL14_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL14_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL14_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL14_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL14_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL14_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL14_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL14_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL14_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL14_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL14_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL14_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL14_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL14_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL14_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL14_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT15 Bit Fields */ -#define CCM_TARGET_ROOT15_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT15_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT15_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_POST_PODF_SHIFT))&CCM_TARGET_ROOT15_POST_PODF_MASK) -#define CCM_TARGET_ROOT15_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT15_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT15_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT15_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT15_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT15_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT15_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT15_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT15_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT15_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT15_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_PRE_PODF_SHIFT))&CCM_TARGET_ROOT15_PRE_PODF_MASK) -#define CCM_TARGET_ROOT15_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT15_MUX_SHIFT 24 -#define CCM_TARGET_ROOT15_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_MUX_SHIFT))&CCM_TARGET_ROOT15_MUX_MASK) -#define CCM_TARGET_ROOT15_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT15_ENABLE_SHIFT 28 -/* TARGET_ROOT15_SET Bit Fields */ -#define CCM_TARGET_ROOT15_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT15_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT15_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT15_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT15_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT15_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT15_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT15_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT15_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT15_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT15_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT15_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT15_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT15_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT15_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT15_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT15_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT15_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT15_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_SET_MUX_SHIFT))&CCM_TARGET_ROOT15_SET_MUX_MASK) -#define CCM_TARGET_ROOT15_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT15_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT15_CLR Bit Fields */ -#define CCM_TARGET_ROOT15_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT15_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT15_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT15_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT15_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT15_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT15_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT15_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT15_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT15_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT15_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT15_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT15_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT15_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT15_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT15_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT15_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT15_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT15_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_CLR_MUX_SHIFT))&CCM_TARGET_ROOT15_CLR_MUX_MASK) -#define CCM_TARGET_ROOT15_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT15_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT15_TOG Bit Fields */ -#define CCM_TARGET_ROOT15_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT15_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT15_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT15_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT15_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT15_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT15_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT15_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT15_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT15_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT15_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT15_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT15_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT15_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT15_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT15_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT15_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT15_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT15_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_TOG_MUX_SHIFT))&CCM_TARGET_ROOT15_TOG_MUX_MASK) -#define CCM_TARGET_ROOT15_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT15_TOG_ENABLE_SHIFT 28 -/* POST15 Bit Fields */ -#define CCM_POST15_POST_PODF_MASK 0x3Fu -#define CCM_POST15_POST_PODF_SHIFT 0 -#define CCM_POST15_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST15_POST_PODF_SHIFT))&CCM_POST15_POST_PODF_MASK) -#define CCM_POST15_BUSY1_MASK 0x80u -#define CCM_POST15_BUSY1_SHIFT 7 -#define CCM_POST15_AUTO_PODF_MASK 0x700u -#define CCM_POST15_AUTO_PODF_SHIFT 8 -#define CCM_POST15_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST15_AUTO_PODF_SHIFT))&CCM_POST15_AUTO_PODF_MASK) -#define CCM_POST15_AUTO_EN_MASK 0x1000u -#define CCM_POST15_AUTO_EN_SHIFT 12 -#define CCM_POST15_SLOW_MASK 0x8000u -#define CCM_POST15_SLOW_SHIFT 15 -#define CCM_POST15_SELECT_MASK 0x10000000u -#define CCM_POST15_SELECT_SHIFT 28 -#define CCM_POST15_BUSY2_MASK 0x80000000u -#define CCM_POST15_BUSY2_SHIFT 31 -/* POST_ROOT15_SET Bit Fields */ -#define CCM_POST_ROOT15_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT15_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT15_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_SET_POST_PODF_SHIFT))&CCM_POST_ROOT15_SET_POST_PODF_MASK) -#define CCM_POST_ROOT15_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT15_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT15_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT15_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT15_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT15_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT15_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT15_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT15_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT15_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT15_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT15_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT15_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT15_SET_BUSY2_SHIFT 31 -/* POST_ROOT15_CLR Bit Fields */ -#define CCM_POST_ROOT15_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT15_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT15_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT15_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT15_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT15_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT15_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT15_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT15_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT15_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT15_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT15_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT15_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT15_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT15_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT15_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT15_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT15_CLR_BUSY2_SHIFT 31 -/* POST_ROOT15_TOG Bit Fields */ -#define CCM_POST_ROOT15_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT15_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT15_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT15_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT15_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT15_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT15_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT15_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT15_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT15_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT15_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT15_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT15_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT15_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT15_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT15_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT15_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT15_TOG_BUSY2_SHIFT 31 -/* PRE15 Bit Fields */ -#define CCM_PRE15_PRE_PODF_B_MASK 0x7u -#define CCM_PRE15_PRE_PODF_B_SHIFT 0 -#define CCM_PRE15_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE15_PRE_PODF_B_SHIFT))&CCM_PRE15_PRE_PODF_B_MASK) -#define CCM_PRE15_BUSY0_MASK 0x8u -#define CCM_PRE15_BUSY0_SHIFT 3 -#define CCM_PRE15_MUX_B_MASK 0x700u -#define CCM_PRE15_MUX_B_SHIFT 8 -#define CCM_PRE15_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE15_MUX_B_SHIFT))&CCM_PRE15_MUX_B_MASK) -#define CCM_PRE15_EN_B_MASK 0x1000u -#define CCM_PRE15_EN_B_SHIFT 12 -#define CCM_PRE15_BUSY1_MASK 0x8000u -#define CCM_PRE15_BUSY1_SHIFT 15 -#define CCM_PRE15_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE15_PRE_PODF_A_SHIFT 16 -#define CCM_PRE15_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE15_PRE_PODF_A_SHIFT))&CCM_PRE15_PRE_PODF_A_MASK) -#define CCM_PRE15_BUSY3_MASK 0x80000u -#define CCM_PRE15_BUSY3_SHIFT 19 -#define CCM_PRE15_MUX_A_MASK 0x7000000u -#define CCM_PRE15_MUX_A_SHIFT 24 -#define CCM_PRE15_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE15_MUX_A_SHIFT))&CCM_PRE15_MUX_A_MASK) -#define CCM_PRE15_EN_A_MASK 0x10000000u -#define CCM_PRE15_EN_A_SHIFT 28 -#define CCM_PRE15_BUSY4_MASK 0x80000000u -#define CCM_PRE15_BUSY4_SHIFT 31 -/* PRE_ROOT15_SET Bit Fields */ -#define CCM_PRE_ROOT15_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT15_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT15_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT15_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT15_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT15_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT15_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT15_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT15_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_SET_MUX_B_SHIFT))&CCM_PRE_ROOT15_SET_MUX_B_MASK) -#define CCM_PRE_ROOT15_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT15_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT15_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT15_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT15_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT15_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT15_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT15_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT15_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT15_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT15_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT15_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT15_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_SET_MUX_A_SHIFT))&CCM_PRE_ROOT15_SET_MUX_A_MASK) -#define CCM_PRE_ROOT15_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT15_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT15_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT15_SET_BUSY4_SHIFT 31 -/* PRE_ROOT15_CLR Bit Fields */ -#define CCM_PRE_ROOT15_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT15_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT15_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT15_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT15_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT15_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT15_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT15_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT15_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT15_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT15_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT15_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT15_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT15_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT15_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT15_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT15_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT15_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT15_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT15_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT15_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT15_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT15_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT15_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT15_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT15_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT15_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT15_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT15_TOG Bit Fields */ -#define CCM_PRE_ROOT15_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT15_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT15_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT15_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT15_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT15_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT15_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT15_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT15_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT15_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT15_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT15_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT15_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT15_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT15_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT15_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT15_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT15_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT15_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT15_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT15_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT15_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT15_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT15_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT15_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT15_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT15_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT15_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL15 Bit Fields */ -#define CCM_ACCESS_CTRL15_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL15_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL15_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL15_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL15_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL15_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL15_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL15_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL15_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL15_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL15_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL15_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL15_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL15_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL15_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL15_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL15_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL15_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL15_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL15_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL15_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL15_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL15_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL15_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL15_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL15_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL15_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL15_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL15_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL15_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL15_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL15_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL15_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL15_LOCK_SHIFT 31 -/* ACCESS_CTRL15_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL15_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL15_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL15_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL15_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL15_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL15_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL15_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL15_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL15_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL15_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL15_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL15_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL15_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL15_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL15_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL15_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT16 Bit Fields */ -#define CCM_TARGET_ROOT16_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT16_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT16_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_POST_PODF_SHIFT))&CCM_TARGET_ROOT16_POST_PODF_MASK) -#define CCM_TARGET_ROOT16_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT16_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT16_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT16_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT16_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT16_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT16_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT16_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT16_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT16_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT16_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_PRE_PODF_SHIFT))&CCM_TARGET_ROOT16_PRE_PODF_MASK) -#define CCM_TARGET_ROOT16_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT16_MUX_SHIFT 24 -#define CCM_TARGET_ROOT16_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_MUX_SHIFT))&CCM_TARGET_ROOT16_MUX_MASK) -#define CCM_TARGET_ROOT16_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT16_ENABLE_SHIFT 28 -/* TARGET_ROOT16_SET Bit Fields */ -#define CCM_TARGET_ROOT16_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT16_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT16_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT16_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT16_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT16_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT16_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT16_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT16_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT16_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT16_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT16_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT16_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT16_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT16_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT16_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT16_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT16_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT16_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_SET_MUX_SHIFT))&CCM_TARGET_ROOT16_SET_MUX_MASK) -#define CCM_TARGET_ROOT16_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT16_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT16_CLR Bit Fields */ -#define CCM_TARGET_ROOT16_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT16_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT16_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT16_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT16_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT16_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT16_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT16_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT16_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT16_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT16_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT16_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT16_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT16_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT16_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT16_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT16_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT16_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT16_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_CLR_MUX_SHIFT))&CCM_TARGET_ROOT16_CLR_MUX_MASK) -#define CCM_TARGET_ROOT16_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT16_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT16_TOG Bit Fields */ -#define CCM_TARGET_ROOT16_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT16_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT16_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT16_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT16_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT16_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT16_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT16_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT16_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT16_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT16_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT16_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT16_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT16_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT16_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT16_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT16_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT16_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT16_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_TOG_MUX_SHIFT))&CCM_TARGET_ROOT16_TOG_MUX_MASK) -#define CCM_TARGET_ROOT16_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT16_TOG_ENABLE_SHIFT 28 -/* POST16 Bit Fields */ -#define CCM_POST16_POST_PODF_MASK 0x3Fu -#define CCM_POST16_POST_PODF_SHIFT 0 -#define CCM_POST16_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST16_POST_PODF_SHIFT))&CCM_POST16_POST_PODF_MASK) -#define CCM_POST16_BUSY1_MASK 0x80u -#define CCM_POST16_BUSY1_SHIFT 7 -#define CCM_POST16_AUTO_PODF_MASK 0x700u -#define CCM_POST16_AUTO_PODF_SHIFT 8 -#define CCM_POST16_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST16_AUTO_PODF_SHIFT))&CCM_POST16_AUTO_PODF_MASK) -#define CCM_POST16_AUTO_EN_MASK 0x1000u -#define CCM_POST16_AUTO_EN_SHIFT 12 -#define CCM_POST16_SLOW_MASK 0x8000u -#define CCM_POST16_SLOW_SHIFT 15 -#define CCM_POST16_SELECT_MASK 0x10000000u -#define CCM_POST16_SELECT_SHIFT 28 -#define CCM_POST16_BUSY2_MASK 0x80000000u -#define CCM_POST16_BUSY2_SHIFT 31 -/* POST_ROOT16_SET Bit Fields */ -#define CCM_POST_ROOT16_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT16_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT16_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_SET_POST_PODF_SHIFT))&CCM_POST_ROOT16_SET_POST_PODF_MASK) -#define CCM_POST_ROOT16_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT16_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT16_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT16_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT16_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT16_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT16_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT16_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT16_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT16_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT16_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT16_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT16_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT16_SET_BUSY2_SHIFT 31 -/* POST_ROOT16_CLR Bit Fields */ -#define CCM_POST_ROOT16_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT16_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT16_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT16_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT16_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT16_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT16_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT16_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT16_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT16_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT16_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT16_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT16_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT16_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT16_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT16_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT16_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT16_CLR_BUSY2_SHIFT 31 -/* POST_ROOT16_TOG Bit Fields */ -#define CCM_POST_ROOT16_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT16_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT16_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT16_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT16_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT16_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT16_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT16_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT16_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT16_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT16_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT16_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT16_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT16_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT16_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT16_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT16_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT16_TOG_BUSY2_SHIFT 31 -/* PRE16 Bit Fields */ -#define CCM_PRE16_PRE_PODF_B_MASK 0x7u -#define CCM_PRE16_PRE_PODF_B_SHIFT 0 -#define CCM_PRE16_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE16_PRE_PODF_B_SHIFT))&CCM_PRE16_PRE_PODF_B_MASK) -#define CCM_PRE16_BUSY0_MASK 0x8u -#define CCM_PRE16_BUSY0_SHIFT 3 -#define CCM_PRE16_MUX_B_MASK 0x700u -#define CCM_PRE16_MUX_B_SHIFT 8 -#define CCM_PRE16_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE16_MUX_B_SHIFT))&CCM_PRE16_MUX_B_MASK) -#define CCM_PRE16_EN_B_MASK 0x1000u -#define CCM_PRE16_EN_B_SHIFT 12 -#define CCM_PRE16_BUSY1_MASK 0x8000u -#define CCM_PRE16_BUSY1_SHIFT 15 -#define CCM_PRE16_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE16_PRE_PODF_A_SHIFT 16 -#define CCM_PRE16_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE16_PRE_PODF_A_SHIFT))&CCM_PRE16_PRE_PODF_A_MASK) -#define CCM_PRE16_BUSY3_MASK 0x80000u -#define CCM_PRE16_BUSY3_SHIFT 19 -#define CCM_PRE16_MUX_A_MASK 0x7000000u -#define CCM_PRE16_MUX_A_SHIFT 24 -#define CCM_PRE16_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE16_MUX_A_SHIFT))&CCM_PRE16_MUX_A_MASK) -#define CCM_PRE16_EN_A_MASK 0x10000000u -#define CCM_PRE16_EN_A_SHIFT 28 -#define CCM_PRE16_BUSY4_MASK 0x80000000u -#define CCM_PRE16_BUSY4_SHIFT 31 -/* PRE_ROOT16_SET Bit Fields */ -#define CCM_PRE_ROOT16_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT16_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT16_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT16_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT16_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT16_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT16_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT16_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT16_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_SET_MUX_B_SHIFT))&CCM_PRE_ROOT16_SET_MUX_B_MASK) -#define CCM_PRE_ROOT16_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT16_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT16_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT16_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT16_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT16_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT16_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT16_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT16_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT16_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT16_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT16_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT16_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_SET_MUX_A_SHIFT))&CCM_PRE_ROOT16_SET_MUX_A_MASK) -#define CCM_PRE_ROOT16_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT16_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT16_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT16_SET_BUSY4_SHIFT 31 -/* PRE_ROOT16_CLR Bit Fields */ -#define CCM_PRE_ROOT16_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT16_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT16_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT16_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT16_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT16_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT16_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT16_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT16_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT16_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT16_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT16_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT16_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT16_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT16_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT16_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT16_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT16_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT16_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT16_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT16_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT16_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT16_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT16_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT16_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT16_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT16_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT16_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT16_TOG Bit Fields */ -#define CCM_PRE_ROOT16_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT16_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT16_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT16_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT16_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT16_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT16_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT16_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT16_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT16_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT16_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT16_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT16_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT16_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT16_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT16_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT16_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT16_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT16_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT16_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT16_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT16_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT16_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT16_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT16_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT16_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT16_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT16_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL16 Bit Fields */ -#define CCM_ACCESS_CTRL16_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL16_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL16_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL16_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL16_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL16_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL16_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL16_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL16_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL16_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL16_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL16_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL16_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL16_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL16_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL16_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL16_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL16_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL16_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL16_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL16_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL16_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL16_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL16_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL16_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL16_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL16_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL16_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL16_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL16_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL16_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL16_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL16_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL16_LOCK_SHIFT 31 -/* ACCESS_CTRL16_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL16_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL16_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL16_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL16_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL16_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL16_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL16_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL16_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL16_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL16_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL16_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL16_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL16_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL16_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL16_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL16_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT17 Bit Fields */ -#define CCM_TARGET_ROOT17_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT17_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT17_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_POST_PODF_SHIFT))&CCM_TARGET_ROOT17_POST_PODF_MASK) -#define CCM_TARGET_ROOT17_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT17_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT17_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT17_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT17_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT17_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT17_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT17_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT17_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT17_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT17_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_PRE_PODF_SHIFT))&CCM_TARGET_ROOT17_PRE_PODF_MASK) -#define CCM_TARGET_ROOT17_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT17_MUX_SHIFT 24 -#define CCM_TARGET_ROOT17_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_MUX_SHIFT))&CCM_TARGET_ROOT17_MUX_MASK) -#define CCM_TARGET_ROOT17_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT17_ENABLE_SHIFT 28 -/* TARGET_ROOT17_SET Bit Fields */ -#define CCM_TARGET_ROOT17_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT17_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT17_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT17_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT17_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT17_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT17_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT17_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT17_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT17_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT17_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT17_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT17_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT17_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT17_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT17_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT17_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT17_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT17_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_SET_MUX_SHIFT))&CCM_TARGET_ROOT17_SET_MUX_MASK) -#define CCM_TARGET_ROOT17_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT17_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT17_CLR Bit Fields */ -#define CCM_TARGET_ROOT17_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT17_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT17_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT17_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT17_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT17_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT17_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT17_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT17_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT17_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT17_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT17_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT17_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT17_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT17_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT17_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT17_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT17_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT17_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_CLR_MUX_SHIFT))&CCM_TARGET_ROOT17_CLR_MUX_MASK) -#define CCM_TARGET_ROOT17_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT17_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT17_TOG Bit Fields */ -#define CCM_TARGET_ROOT17_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT17_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT17_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT17_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT17_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT17_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT17_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT17_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT17_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT17_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT17_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT17_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT17_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT17_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT17_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT17_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT17_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT17_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT17_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_TOG_MUX_SHIFT))&CCM_TARGET_ROOT17_TOG_MUX_MASK) -#define CCM_TARGET_ROOT17_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT17_TOG_ENABLE_SHIFT 28 -/* POST17 Bit Fields */ -#define CCM_POST17_POST_PODF_MASK 0x3Fu -#define CCM_POST17_POST_PODF_SHIFT 0 -#define CCM_POST17_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST17_POST_PODF_SHIFT))&CCM_POST17_POST_PODF_MASK) -#define CCM_POST17_BUSY1_MASK 0x80u -#define CCM_POST17_BUSY1_SHIFT 7 -#define CCM_POST17_AUTO_PODF_MASK 0x700u -#define CCM_POST17_AUTO_PODF_SHIFT 8 -#define CCM_POST17_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST17_AUTO_PODF_SHIFT))&CCM_POST17_AUTO_PODF_MASK) -#define CCM_POST17_AUTO_EN_MASK 0x1000u -#define CCM_POST17_AUTO_EN_SHIFT 12 -#define CCM_POST17_SLOW_MASK 0x8000u -#define CCM_POST17_SLOW_SHIFT 15 -#define CCM_POST17_SELECT_MASK 0x10000000u -#define CCM_POST17_SELECT_SHIFT 28 -#define CCM_POST17_BUSY2_MASK 0x80000000u -#define CCM_POST17_BUSY2_SHIFT 31 -/* POST_ROOT17_SET Bit Fields */ -#define CCM_POST_ROOT17_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT17_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT17_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_SET_POST_PODF_SHIFT))&CCM_POST_ROOT17_SET_POST_PODF_MASK) -#define CCM_POST_ROOT17_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT17_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT17_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT17_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT17_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT17_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT17_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT17_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT17_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT17_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT17_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT17_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT17_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT17_SET_BUSY2_SHIFT 31 -/* POST_ROOT17_CLR Bit Fields */ -#define CCM_POST_ROOT17_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT17_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT17_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT17_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT17_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT17_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT17_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT17_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT17_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT17_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT17_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT17_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT17_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT17_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT17_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT17_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT17_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT17_CLR_BUSY2_SHIFT 31 -/* POST_ROOT17_TOG Bit Fields */ -#define CCM_POST_ROOT17_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT17_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT17_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT17_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT17_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT17_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT17_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT17_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT17_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT17_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT17_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT17_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT17_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT17_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT17_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT17_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT17_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT17_TOG_BUSY2_SHIFT 31 -/* PRE17 Bit Fields */ -#define CCM_PRE17_PRE_PODF_B_MASK 0x7u -#define CCM_PRE17_PRE_PODF_B_SHIFT 0 -#define CCM_PRE17_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE17_PRE_PODF_B_SHIFT))&CCM_PRE17_PRE_PODF_B_MASK) -#define CCM_PRE17_BUSY0_MASK 0x8u -#define CCM_PRE17_BUSY0_SHIFT 3 -#define CCM_PRE17_MUX_B_MASK 0x700u -#define CCM_PRE17_MUX_B_SHIFT 8 -#define CCM_PRE17_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE17_MUX_B_SHIFT))&CCM_PRE17_MUX_B_MASK) -#define CCM_PRE17_EN_B_MASK 0x1000u -#define CCM_PRE17_EN_B_SHIFT 12 -#define CCM_PRE17_BUSY1_MASK 0x8000u -#define CCM_PRE17_BUSY1_SHIFT 15 -#define CCM_PRE17_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE17_PRE_PODF_A_SHIFT 16 -#define CCM_PRE17_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE17_PRE_PODF_A_SHIFT))&CCM_PRE17_PRE_PODF_A_MASK) -#define CCM_PRE17_BUSY3_MASK 0x80000u -#define CCM_PRE17_BUSY3_SHIFT 19 -#define CCM_PRE17_MUX_A_MASK 0x7000000u -#define CCM_PRE17_MUX_A_SHIFT 24 -#define CCM_PRE17_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE17_MUX_A_SHIFT))&CCM_PRE17_MUX_A_MASK) -#define CCM_PRE17_EN_A_MASK 0x10000000u -#define CCM_PRE17_EN_A_SHIFT 28 -#define CCM_PRE17_BUSY4_MASK 0x80000000u -#define CCM_PRE17_BUSY4_SHIFT 31 -/* PRE_ROOT17_SET Bit Fields */ -#define CCM_PRE_ROOT17_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT17_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT17_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT17_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT17_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT17_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT17_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT17_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT17_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_SET_MUX_B_SHIFT))&CCM_PRE_ROOT17_SET_MUX_B_MASK) -#define CCM_PRE_ROOT17_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT17_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT17_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT17_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT17_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT17_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT17_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT17_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT17_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT17_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT17_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT17_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT17_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_SET_MUX_A_SHIFT))&CCM_PRE_ROOT17_SET_MUX_A_MASK) -#define CCM_PRE_ROOT17_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT17_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT17_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT17_SET_BUSY4_SHIFT 31 -/* PRE_ROOT17_CLR Bit Fields */ -#define CCM_PRE_ROOT17_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT17_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT17_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT17_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT17_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT17_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT17_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT17_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT17_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT17_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT17_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT17_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT17_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT17_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT17_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT17_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT17_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT17_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT17_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT17_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT17_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT17_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT17_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT17_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT17_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT17_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT17_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT17_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT17_TOG Bit Fields */ -#define CCM_PRE_ROOT17_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT17_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT17_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT17_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT17_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT17_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT17_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT17_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT17_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT17_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT17_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT17_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT17_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT17_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT17_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT17_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT17_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT17_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT17_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT17_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT17_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT17_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT17_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT17_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT17_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT17_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT17_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT17_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL17 Bit Fields */ -#define CCM_ACCESS_CTRL17_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL17_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL17_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL17_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL17_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL17_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL17_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL17_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL17_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL17_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL17_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL17_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL17_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL17_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL17_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL17_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL17_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL17_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL17_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL17_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL17_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL17_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL17_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL17_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL17_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL17_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL17_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL17_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL17_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL17_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL17_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL17_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL17_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL17_LOCK_SHIFT 31 -/* ACCESS_CTRL17_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL17_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL17_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL17_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL17_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL17_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL17_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL17_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL17_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL17_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL17_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL17_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL17_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL17_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL17_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL17_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL17_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT18 Bit Fields */ -#define CCM_TARGET_ROOT18_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT18_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT18_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_POST_PODF_SHIFT))&CCM_TARGET_ROOT18_POST_PODF_MASK) -#define CCM_TARGET_ROOT18_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT18_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT18_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT18_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT18_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT18_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT18_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT18_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT18_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT18_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT18_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_PRE_PODF_SHIFT))&CCM_TARGET_ROOT18_PRE_PODF_MASK) -#define CCM_TARGET_ROOT18_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT18_MUX_SHIFT 24 -#define CCM_TARGET_ROOT18_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_MUX_SHIFT))&CCM_TARGET_ROOT18_MUX_MASK) -#define CCM_TARGET_ROOT18_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT18_ENABLE_SHIFT 28 -/* TARGET_ROOT18_SET Bit Fields */ -#define CCM_TARGET_ROOT18_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT18_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT18_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT18_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT18_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT18_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT18_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT18_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT18_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT18_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT18_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT18_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT18_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT18_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT18_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT18_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT18_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT18_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT18_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_SET_MUX_SHIFT))&CCM_TARGET_ROOT18_SET_MUX_MASK) -#define CCM_TARGET_ROOT18_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT18_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT18_CLR Bit Fields */ -#define CCM_TARGET_ROOT18_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT18_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT18_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT18_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT18_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT18_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT18_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT18_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT18_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT18_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT18_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT18_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT18_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT18_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT18_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT18_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT18_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT18_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT18_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_CLR_MUX_SHIFT))&CCM_TARGET_ROOT18_CLR_MUX_MASK) -#define CCM_TARGET_ROOT18_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT18_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT18_TOG Bit Fields */ -#define CCM_TARGET_ROOT18_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT18_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT18_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT18_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT18_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT18_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT18_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT18_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT18_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT18_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT18_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT18_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT18_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT18_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT18_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT18_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT18_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT18_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT18_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_TOG_MUX_SHIFT))&CCM_TARGET_ROOT18_TOG_MUX_MASK) -#define CCM_TARGET_ROOT18_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT18_TOG_ENABLE_SHIFT 28 -/* POST18 Bit Fields */ -#define CCM_POST18_POST_PODF_MASK 0x3Fu -#define CCM_POST18_POST_PODF_SHIFT 0 -#define CCM_POST18_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST18_POST_PODF_SHIFT))&CCM_POST18_POST_PODF_MASK) -#define CCM_POST18_BUSY1_MASK 0x80u -#define CCM_POST18_BUSY1_SHIFT 7 -#define CCM_POST18_AUTO_PODF_MASK 0x700u -#define CCM_POST18_AUTO_PODF_SHIFT 8 -#define CCM_POST18_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST18_AUTO_PODF_SHIFT))&CCM_POST18_AUTO_PODF_MASK) -#define CCM_POST18_AUTO_EN_MASK 0x1000u -#define CCM_POST18_AUTO_EN_SHIFT 12 -#define CCM_POST18_SLOW_MASK 0x8000u -#define CCM_POST18_SLOW_SHIFT 15 -#define CCM_POST18_SELECT_MASK 0x10000000u -#define CCM_POST18_SELECT_SHIFT 28 -#define CCM_POST18_BUSY2_MASK 0x80000000u -#define CCM_POST18_BUSY2_SHIFT 31 -/* POST_ROOT18_SET Bit Fields */ -#define CCM_POST_ROOT18_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT18_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT18_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_SET_POST_PODF_SHIFT))&CCM_POST_ROOT18_SET_POST_PODF_MASK) -#define CCM_POST_ROOT18_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT18_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT18_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT18_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT18_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT18_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT18_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT18_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT18_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT18_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT18_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT18_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT18_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT18_SET_BUSY2_SHIFT 31 -/* POST_ROOT18_CLR Bit Fields */ -#define CCM_POST_ROOT18_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT18_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT18_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT18_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT18_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT18_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT18_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT18_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT18_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT18_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT18_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT18_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT18_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT18_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT18_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT18_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT18_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT18_CLR_BUSY2_SHIFT 31 -/* POST_ROOT18_TOG Bit Fields */ -#define CCM_POST_ROOT18_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT18_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT18_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT18_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT18_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT18_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT18_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT18_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT18_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT18_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT18_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT18_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT18_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT18_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT18_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT18_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT18_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT18_TOG_BUSY2_SHIFT 31 -/* PRE18 Bit Fields */ -#define CCM_PRE18_PRE_PODF_B_MASK 0x7u -#define CCM_PRE18_PRE_PODF_B_SHIFT 0 -#define CCM_PRE18_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE18_PRE_PODF_B_SHIFT))&CCM_PRE18_PRE_PODF_B_MASK) -#define CCM_PRE18_BUSY0_MASK 0x8u -#define CCM_PRE18_BUSY0_SHIFT 3 -#define CCM_PRE18_MUX_B_MASK 0x700u -#define CCM_PRE18_MUX_B_SHIFT 8 -#define CCM_PRE18_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE18_MUX_B_SHIFT))&CCM_PRE18_MUX_B_MASK) -#define CCM_PRE18_EN_B_MASK 0x1000u -#define CCM_PRE18_EN_B_SHIFT 12 -#define CCM_PRE18_BUSY1_MASK 0x8000u -#define CCM_PRE18_BUSY1_SHIFT 15 -#define CCM_PRE18_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE18_PRE_PODF_A_SHIFT 16 -#define CCM_PRE18_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE18_PRE_PODF_A_SHIFT))&CCM_PRE18_PRE_PODF_A_MASK) -#define CCM_PRE18_BUSY3_MASK 0x80000u -#define CCM_PRE18_BUSY3_SHIFT 19 -#define CCM_PRE18_MUX_A_MASK 0x7000000u -#define CCM_PRE18_MUX_A_SHIFT 24 -#define CCM_PRE18_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE18_MUX_A_SHIFT))&CCM_PRE18_MUX_A_MASK) -#define CCM_PRE18_EN_A_MASK 0x10000000u -#define CCM_PRE18_EN_A_SHIFT 28 -#define CCM_PRE18_BUSY4_MASK 0x80000000u -#define CCM_PRE18_BUSY4_SHIFT 31 -/* PRE_ROOT18_SET Bit Fields */ -#define CCM_PRE_ROOT18_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT18_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT18_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT18_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT18_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT18_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT18_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT18_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT18_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_SET_MUX_B_SHIFT))&CCM_PRE_ROOT18_SET_MUX_B_MASK) -#define CCM_PRE_ROOT18_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT18_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT18_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT18_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT18_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT18_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT18_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT18_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT18_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT18_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT18_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT18_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT18_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_SET_MUX_A_SHIFT))&CCM_PRE_ROOT18_SET_MUX_A_MASK) -#define CCM_PRE_ROOT18_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT18_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT18_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT18_SET_BUSY4_SHIFT 31 -/* PRE_ROOT18_CLR Bit Fields */ -#define CCM_PRE_ROOT18_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT18_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT18_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT18_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT18_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT18_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT18_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT18_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT18_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT18_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT18_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT18_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT18_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT18_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT18_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT18_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT18_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT18_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT18_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT18_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT18_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT18_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT18_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT18_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT18_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT18_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT18_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT18_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT18_TOG Bit Fields */ -#define CCM_PRE_ROOT18_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT18_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT18_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT18_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT18_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT18_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT18_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT18_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT18_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT18_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT18_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT18_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT18_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT18_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT18_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT18_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT18_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT18_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT18_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT18_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT18_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT18_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT18_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT18_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT18_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT18_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT18_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT18_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL18 Bit Fields */ -#define CCM_ACCESS_CTRL18_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL18_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL18_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL18_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL18_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL18_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL18_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL18_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL18_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL18_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL18_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL18_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL18_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL18_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL18_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL18_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL18_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL18_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL18_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL18_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL18_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL18_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL18_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL18_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL18_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL18_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL18_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL18_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL18_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL18_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL18_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL18_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL18_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL18_LOCK_SHIFT 31 -/* ACCESS_CTRL18_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL18_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL18_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL18_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL18_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL18_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL18_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL18_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL18_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL18_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL18_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL18_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL18_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL18_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL18_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL18_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL18_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT19 Bit Fields */ -#define CCM_TARGET_ROOT19_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT19_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT19_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_POST_PODF_SHIFT))&CCM_TARGET_ROOT19_POST_PODF_MASK) -#define CCM_TARGET_ROOT19_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT19_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT19_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT19_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT19_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT19_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT19_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT19_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT19_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT19_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT19_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_PRE_PODF_SHIFT))&CCM_TARGET_ROOT19_PRE_PODF_MASK) -#define CCM_TARGET_ROOT19_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT19_MUX_SHIFT 24 -#define CCM_TARGET_ROOT19_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_MUX_SHIFT))&CCM_TARGET_ROOT19_MUX_MASK) -#define CCM_TARGET_ROOT19_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT19_ENABLE_SHIFT 28 -/* TARGET_ROOT19_SET Bit Fields */ -#define CCM_TARGET_ROOT19_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT19_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT19_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT19_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT19_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT19_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT19_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT19_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT19_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT19_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT19_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT19_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT19_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT19_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT19_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT19_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT19_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT19_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT19_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_SET_MUX_SHIFT))&CCM_TARGET_ROOT19_SET_MUX_MASK) -#define CCM_TARGET_ROOT19_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT19_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT19_CLR Bit Fields */ -#define CCM_TARGET_ROOT19_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT19_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT19_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT19_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT19_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT19_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT19_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT19_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT19_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT19_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT19_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT19_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT19_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT19_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT19_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT19_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT19_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT19_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT19_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_CLR_MUX_SHIFT))&CCM_TARGET_ROOT19_CLR_MUX_MASK) -#define CCM_TARGET_ROOT19_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT19_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT19_TOG Bit Fields */ -#define CCM_TARGET_ROOT19_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT19_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT19_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT19_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT19_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT19_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT19_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT19_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT19_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT19_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT19_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT19_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT19_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT19_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT19_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT19_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT19_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT19_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT19_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_TOG_MUX_SHIFT))&CCM_TARGET_ROOT19_TOG_MUX_MASK) -#define CCM_TARGET_ROOT19_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT19_TOG_ENABLE_SHIFT 28 -/* POST19 Bit Fields */ -#define CCM_POST19_POST_PODF_MASK 0x3Fu -#define CCM_POST19_POST_PODF_SHIFT 0 -#define CCM_POST19_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST19_POST_PODF_SHIFT))&CCM_POST19_POST_PODF_MASK) -#define CCM_POST19_BUSY1_MASK 0x80u -#define CCM_POST19_BUSY1_SHIFT 7 -#define CCM_POST19_AUTO_PODF_MASK 0x700u -#define CCM_POST19_AUTO_PODF_SHIFT 8 -#define CCM_POST19_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST19_AUTO_PODF_SHIFT))&CCM_POST19_AUTO_PODF_MASK) -#define CCM_POST19_AUTO_EN_MASK 0x1000u -#define CCM_POST19_AUTO_EN_SHIFT 12 -#define CCM_POST19_SLOW_MASK 0x8000u -#define CCM_POST19_SLOW_SHIFT 15 -#define CCM_POST19_SELECT_MASK 0x10000000u -#define CCM_POST19_SELECT_SHIFT 28 -#define CCM_POST19_BUSY2_MASK 0x80000000u -#define CCM_POST19_BUSY2_SHIFT 31 -/* POST_ROOT19_SET Bit Fields */ -#define CCM_POST_ROOT19_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT19_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT19_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_SET_POST_PODF_SHIFT))&CCM_POST_ROOT19_SET_POST_PODF_MASK) -#define CCM_POST_ROOT19_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT19_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT19_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT19_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT19_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT19_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT19_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT19_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT19_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT19_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT19_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT19_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT19_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT19_SET_BUSY2_SHIFT 31 -/* POST_ROOT19_CLR Bit Fields */ -#define CCM_POST_ROOT19_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT19_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT19_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT19_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT19_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT19_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT19_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT19_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT19_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT19_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT19_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT19_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT19_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT19_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT19_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT19_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT19_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT19_CLR_BUSY2_SHIFT 31 -/* POST_ROOT19_TOG Bit Fields */ -#define CCM_POST_ROOT19_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT19_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT19_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT19_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT19_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT19_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT19_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT19_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT19_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT19_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT19_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT19_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT19_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT19_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT19_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT19_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT19_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT19_TOG_BUSY2_SHIFT 31 -/* PRE19 Bit Fields */ -#define CCM_PRE19_PRE_PODF_B_MASK 0x7u -#define CCM_PRE19_PRE_PODF_B_SHIFT 0 -#define CCM_PRE19_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE19_PRE_PODF_B_SHIFT))&CCM_PRE19_PRE_PODF_B_MASK) -#define CCM_PRE19_BUSY0_MASK 0x8u -#define CCM_PRE19_BUSY0_SHIFT 3 -#define CCM_PRE19_MUX_B_MASK 0x700u -#define CCM_PRE19_MUX_B_SHIFT 8 -#define CCM_PRE19_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE19_MUX_B_SHIFT))&CCM_PRE19_MUX_B_MASK) -#define CCM_PRE19_EN_B_MASK 0x1000u -#define CCM_PRE19_EN_B_SHIFT 12 -#define CCM_PRE19_BUSY1_MASK 0x8000u -#define CCM_PRE19_BUSY1_SHIFT 15 -#define CCM_PRE19_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE19_PRE_PODF_A_SHIFT 16 -#define CCM_PRE19_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE19_PRE_PODF_A_SHIFT))&CCM_PRE19_PRE_PODF_A_MASK) -#define CCM_PRE19_BUSY3_MASK 0x80000u -#define CCM_PRE19_BUSY3_SHIFT 19 -#define CCM_PRE19_MUX_A_MASK 0x7000000u -#define CCM_PRE19_MUX_A_SHIFT 24 -#define CCM_PRE19_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE19_MUX_A_SHIFT))&CCM_PRE19_MUX_A_MASK) -#define CCM_PRE19_EN_A_MASK 0x10000000u -#define CCM_PRE19_EN_A_SHIFT 28 -#define CCM_PRE19_BUSY4_MASK 0x80000000u -#define CCM_PRE19_BUSY4_SHIFT 31 -/* PRE_ROOT19_SET Bit Fields */ -#define CCM_PRE_ROOT19_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT19_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT19_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT19_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT19_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT19_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT19_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT19_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT19_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_SET_MUX_B_SHIFT))&CCM_PRE_ROOT19_SET_MUX_B_MASK) -#define CCM_PRE_ROOT19_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT19_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT19_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT19_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT19_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT19_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT19_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT19_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT19_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT19_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT19_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT19_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT19_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_SET_MUX_A_SHIFT))&CCM_PRE_ROOT19_SET_MUX_A_MASK) -#define CCM_PRE_ROOT19_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT19_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT19_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT19_SET_BUSY4_SHIFT 31 -/* PRE_ROOT19_CLR Bit Fields */ -#define CCM_PRE_ROOT19_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT19_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT19_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT19_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT19_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT19_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT19_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT19_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT19_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT19_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT19_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT19_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT19_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT19_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT19_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT19_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT19_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT19_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT19_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT19_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT19_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT19_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT19_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT19_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT19_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT19_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT19_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT19_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT19_TOG Bit Fields */ -#define CCM_PRE_ROOT19_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT19_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT19_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT19_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT19_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT19_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT19_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT19_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT19_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT19_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT19_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT19_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT19_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT19_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT19_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT19_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT19_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT19_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT19_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT19_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT19_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT19_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT19_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT19_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT19_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT19_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT19_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT19_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL19 Bit Fields */ -#define CCM_ACCESS_CTRL19_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL19_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL19_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL19_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL19_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL19_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL19_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL19_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL19_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL19_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL19_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL19_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL19_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL19_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL19_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL19_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL19_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL19_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL19_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL19_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL19_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL19_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL19_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL19_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL19_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL19_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL19_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL19_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL19_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL19_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL19_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL19_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL19_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL19_LOCK_SHIFT 31 -/* ACCESS_CTRL19_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL19_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL19_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL19_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL19_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL19_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL19_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL19_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL19_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL19_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL19_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL19_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL19_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL19_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL19_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL19_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL19_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT20 Bit Fields */ -#define CCM_TARGET_ROOT20_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT20_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT20_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_POST_PODF_SHIFT))&CCM_TARGET_ROOT20_POST_PODF_MASK) -#define CCM_TARGET_ROOT20_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT20_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT20_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT20_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT20_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT20_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT20_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT20_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT20_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT20_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT20_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_PRE_PODF_SHIFT))&CCM_TARGET_ROOT20_PRE_PODF_MASK) -#define CCM_TARGET_ROOT20_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT20_MUX_SHIFT 24 -#define CCM_TARGET_ROOT20_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_MUX_SHIFT))&CCM_TARGET_ROOT20_MUX_MASK) -#define CCM_TARGET_ROOT20_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT20_ENABLE_SHIFT 28 -/* TARGET_ROOT20_SET Bit Fields */ -#define CCM_TARGET_ROOT20_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT20_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT20_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT20_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT20_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT20_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT20_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT20_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT20_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT20_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT20_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT20_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT20_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT20_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT20_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT20_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT20_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT20_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT20_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_SET_MUX_SHIFT))&CCM_TARGET_ROOT20_SET_MUX_MASK) -#define CCM_TARGET_ROOT20_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT20_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT20_CLR Bit Fields */ -#define CCM_TARGET_ROOT20_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT20_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT20_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT20_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT20_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT20_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT20_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT20_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT20_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT20_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT20_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT20_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT20_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT20_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT20_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT20_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT20_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT20_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT20_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_CLR_MUX_SHIFT))&CCM_TARGET_ROOT20_CLR_MUX_MASK) -#define CCM_TARGET_ROOT20_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT20_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT20_TOG Bit Fields */ -#define CCM_TARGET_ROOT20_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT20_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT20_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT20_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT20_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT20_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT20_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT20_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT20_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT20_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT20_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT20_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT20_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT20_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT20_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT20_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT20_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT20_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT20_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_TOG_MUX_SHIFT))&CCM_TARGET_ROOT20_TOG_MUX_MASK) -#define CCM_TARGET_ROOT20_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT20_TOG_ENABLE_SHIFT 28 -/* POST20 Bit Fields */ -#define CCM_POST20_POST_PODF_MASK 0x3Fu -#define CCM_POST20_POST_PODF_SHIFT 0 -#define CCM_POST20_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST20_POST_PODF_SHIFT))&CCM_POST20_POST_PODF_MASK) -#define CCM_POST20_BUSY1_MASK 0x80u -#define CCM_POST20_BUSY1_SHIFT 7 -#define CCM_POST20_AUTO_PODF_MASK 0x700u -#define CCM_POST20_AUTO_PODF_SHIFT 8 -#define CCM_POST20_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST20_AUTO_PODF_SHIFT))&CCM_POST20_AUTO_PODF_MASK) -#define CCM_POST20_AUTO_EN_MASK 0x1000u -#define CCM_POST20_AUTO_EN_SHIFT 12 -#define CCM_POST20_SLOW_MASK 0x8000u -#define CCM_POST20_SLOW_SHIFT 15 -#define CCM_POST20_SELECT_MASK 0x10000000u -#define CCM_POST20_SELECT_SHIFT 28 -#define CCM_POST20_BUSY2_MASK 0x80000000u -#define CCM_POST20_BUSY2_SHIFT 31 -/* POST_ROOT20_SET Bit Fields */ -#define CCM_POST_ROOT20_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT20_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT20_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_SET_POST_PODF_SHIFT))&CCM_POST_ROOT20_SET_POST_PODF_MASK) -#define CCM_POST_ROOT20_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT20_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT20_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT20_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT20_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT20_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT20_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT20_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT20_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT20_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT20_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT20_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT20_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT20_SET_BUSY2_SHIFT 31 -/* POST_ROOT20_CLR Bit Fields */ -#define CCM_POST_ROOT20_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT20_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT20_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT20_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT20_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT20_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT20_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT20_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT20_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT20_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT20_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT20_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT20_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT20_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT20_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT20_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT20_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT20_CLR_BUSY2_SHIFT 31 -/* POST_ROOT20_TOG Bit Fields */ -#define CCM_POST_ROOT20_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT20_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT20_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT20_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT20_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT20_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT20_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT20_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT20_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT20_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT20_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT20_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT20_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT20_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT20_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT20_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT20_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT20_TOG_BUSY2_SHIFT 31 -/* PRE20 Bit Fields */ -#define CCM_PRE20_PRE_PODF_B_MASK 0x7u -#define CCM_PRE20_PRE_PODF_B_SHIFT 0 -#define CCM_PRE20_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE20_PRE_PODF_B_SHIFT))&CCM_PRE20_PRE_PODF_B_MASK) -#define CCM_PRE20_BUSY0_MASK 0x8u -#define CCM_PRE20_BUSY0_SHIFT 3 -#define CCM_PRE20_MUX_B_MASK 0x700u -#define CCM_PRE20_MUX_B_SHIFT 8 -#define CCM_PRE20_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE20_MUX_B_SHIFT))&CCM_PRE20_MUX_B_MASK) -#define CCM_PRE20_EN_B_MASK 0x1000u -#define CCM_PRE20_EN_B_SHIFT 12 -#define CCM_PRE20_BUSY1_MASK 0x8000u -#define CCM_PRE20_BUSY1_SHIFT 15 -#define CCM_PRE20_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE20_PRE_PODF_A_SHIFT 16 -#define CCM_PRE20_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE20_PRE_PODF_A_SHIFT))&CCM_PRE20_PRE_PODF_A_MASK) -#define CCM_PRE20_BUSY3_MASK 0x80000u -#define CCM_PRE20_BUSY3_SHIFT 19 -#define CCM_PRE20_MUX_A_MASK 0x7000000u -#define CCM_PRE20_MUX_A_SHIFT 24 -#define CCM_PRE20_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE20_MUX_A_SHIFT))&CCM_PRE20_MUX_A_MASK) -#define CCM_PRE20_EN_A_MASK 0x10000000u -#define CCM_PRE20_EN_A_SHIFT 28 -#define CCM_PRE20_BUSY4_MASK 0x80000000u -#define CCM_PRE20_BUSY4_SHIFT 31 -/* PRE_ROOT20_SET Bit Fields */ -#define CCM_PRE_ROOT20_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT20_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT20_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT20_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT20_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT20_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT20_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT20_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT20_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_SET_MUX_B_SHIFT))&CCM_PRE_ROOT20_SET_MUX_B_MASK) -#define CCM_PRE_ROOT20_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT20_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT20_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT20_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT20_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT20_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT20_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT20_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT20_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT20_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT20_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT20_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT20_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_SET_MUX_A_SHIFT))&CCM_PRE_ROOT20_SET_MUX_A_MASK) -#define CCM_PRE_ROOT20_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT20_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT20_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT20_SET_BUSY4_SHIFT 31 -/* PRE_ROOT20_CLR Bit Fields */ -#define CCM_PRE_ROOT20_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT20_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT20_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT20_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT20_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT20_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT20_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT20_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT20_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT20_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT20_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT20_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT20_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT20_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT20_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT20_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT20_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT20_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT20_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT20_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT20_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT20_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT20_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT20_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT20_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT20_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT20_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT20_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT20_TOG Bit Fields */ -#define CCM_PRE_ROOT20_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT20_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT20_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT20_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT20_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT20_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT20_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT20_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT20_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT20_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT20_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT20_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT20_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT20_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT20_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT20_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT20_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT20_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT20_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT20_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT20_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT20_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT20_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT20_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT20_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT20_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT20_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT20_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL20 Bit Fields */ -#define CCM_ACCESS_CTRL20_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL20_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL20_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL20_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL20_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL20_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL20_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL20_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL20_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL20_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL20_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL20_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL20_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL20_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL20_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL20_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL20_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL20_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL20_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL20_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL20_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL20_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL20_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL20_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL20_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL20_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL20_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL20_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL20_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL20_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL20_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL20_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL20_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL20_LOCK_SHIFT 31 -/* ACCESS_CTRL20_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL20_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL20_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL20_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL20_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL20_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL20_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL20_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL20_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL20_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL20_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL20_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL20_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL20_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL20_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL20_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL20_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT21 Bit Fields */ -#define CCM_TARGET_ROOT21_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT21_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT21_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_POST_PODF_SHIFT))&CCM_TARGET_ROOT21_POST_PODF_MASK) -#define CCM_TARGET_ROOT21_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT21_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT21_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT21_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT21_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT21_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT21_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT21_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT21_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT21_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT21_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_PRE_PODF_SHIFT))&CCM_TARGET_ROOT21_PRE_PODF_MASK) -#define CCM_TARGET_ROOT21_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT21_MUX_SHIFT 24 -#define CCM_TARGET_ROOT21_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_MUX_SHIFT))&CCM_TARGET_ROOT21_MUX_MASK) -#define CCM_TARGET_ROOT21_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT21_ENABLE_SHIFT 28 -/* TARGET_ROOT21_SET Bit Fields */ -#define CCM_TARGET_ROOT21_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT21_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT21_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT21_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT21_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT21_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT21_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT21_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT21_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT21_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT21_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT21_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT21_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT21_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT21_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT21_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT21_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT21_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT21_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_SET_MUX_SHIFT))&CCM_TARGET_ROOT21_SET_MUX_MASK) -#define CCM_TARGET_ROOT21_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT21_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT21_CLR Bit Fields */ -#define CCM_TARGET_ROOT21_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT21_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT21_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT21_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT21_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT21_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT21_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT21_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT21_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT21_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT21_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT21_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT21_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT21_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT21_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT21_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT21_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT21_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT21_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_CLR_MUX_SHIFT))&CCM_TARGET_ROOT21_CLR_MUX_MASK) -#define CCM_TARGET_ROOT21_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT21_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT21_TOG Bit Fields */ -#define CCM_TARGET_ROOT21_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT21_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT21_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT21_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT21_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT21_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT21_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT21_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT21_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT21_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT21_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT21_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT21_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT21_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT21_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT21_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT21_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT21_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT21_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_TOG_MUX_SHIFT))&CCM_TARGET_ROOT21_TOG_MUX_MASK) -#define CCM_TARGET_ROOT21_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT21_TOG_ENABLE_SHIFT 28 -/* POST21 Bit Fields */ -#define CCM_POST21_POST_PODF_MASK 0x3Fu -#define CCM_POST21_POST_PODF_SHIFT 0 -#define CCM_POST21_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST21_POST_PODF_SHIFT))&CCM_POST21_POST_PODF_MASK) -#define CCM_POST21_BUSY1_MASK 0x80u -#define CCM_POST21_BUSY1_SHIFT 7 -#define CCM_POST21_AUTO_PODF_MASK 0x700u -#define CCM_POST21_AUTO_PODF_SHIFT 8 -#define CCM_POST21_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST21_AUTO_PODF_SHIFT))&CCM_POST21_AUTO_PODF_MASK) -#define CCM_POST21_AUTO_EN_MASK 0x1000u -#define CCM_POST21_AUTO_EN_SHIFT 12 -#define CCM_POST21_SLOW_MASK 0x8000u -#define CCM_POST21_SLOW_SHIFT 15 -#define CCM_POST21_SELECT_MASK 0x10000000u -#define CCM_POST21_SELECT_SHIFT 28 -#define CCM_POST21_BUSY2_MASK 0x80000000u -#define CCM_POST21_BUSY2_SHIFT 31 -/* POST_ROOT21_SET Bit Fields */ -#define CCM_POST_ROOT21_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT21_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT21_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_SET_POST_PODF_SHIFT))&CCM_POST_ROOT21_SET_POST_PODF_MASK) -#define CCM_POST_ROOT21_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT21_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT21_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT21_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT21_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT21_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT21_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT21_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT21_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT21_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT21_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT21_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT21_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT21_SET_BUSY2_SHIFT 31 -/* POST_ROOT21_CLR Bit Fields */ -#define CCM_POST_ROOT21_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT21_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT21_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT21_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT21_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT21_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT21_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT21_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT21_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT21_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT21_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT21_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT21_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT21_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT21_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT21_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT21_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT21_CLR_BUSY2_SHIFT 31 -/* POST_ROOT21_TOG Bit Fields */ -#define CCM_POST_ROOT21_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT21_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT21_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT21_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT21_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT21_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT21_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT21_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT21_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT21_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT21_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT21_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT21_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT21_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT21_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT21_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT21_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT21_TOG_BUSY2_SHIFT 31 -/* PRE21 Bit Fields */ -#define CCM_PRE21_PRE_PODF_B_MASK 0x7u -#define CCM_PRE21_PRE_PODF_B_SHIFT 0 -#define CCM_PRE21_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE21_PRE_PODF_B_SHIFT))&CCM_PRE21_PRE_PODF_B_MASK) -#define CCM_PRE21_BUSY0_MASK 0x8u -#define CCM_PRE21_BUSY0_SHIFT 3 -#define CCM_PRE21_MUX_B_MASK 0x700u -#define CCM_PRE21_MUX_B_SHIFT 8 -#define CCM_PRE21_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE21_MUX_B_SHIFT))&CCM_PRE21_MUX_B_MASK) -#define CCM_PRE21_EN_B_MASK 0x1000u -#define CCM_PRE21_EN_B_SHIFT 12 -#define CCM_PRE21_BUSY1_MASK 0x8000u -#define CCM_PRE21_BUSY1_SHIFT 15 -#define CCM_PRE21_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE21_PRE_PODF_A_SHIFT 16 -#define CCM_PRE21_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE21_PRE_PODF_A_SHIFT))&CCM_PRE21_PRE_PODF_A_MASK) -#define CCM_PRE21_BUSY3_MASK 0x80000u -#define CCM_PRE21_BUSY3_SHIFT 19 -#define CCM_PRE21_MUX_A_MASK 0x7000000u -#define CCM_PRE21_MUX_A_SHIFT 24 -#define CCM_PRE21_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE21_MUX_A_SHIFT))&CCM_PRE21_MUX_A_MASK) -#define CCM_PRE21_EN_A_MASK 0x10000000u -#define CCM_PRE21_EN_A_SHIFT 28 -#define CCM_PRE21_BUSY4_MASK 0x80000000u -#define CCM_PRE21_BUSY4_SHIFT 31 -/* PRE_ROOT21_SET Bit Fields */ -#define CCM_PRE_ROOT21_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT21_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT21_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT21_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT21_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT21_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT21_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT21_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT21_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_SET_MUX_B_SHIFT))&CCM_PRE_ROOT21_SET_MUX_B_MASK) -#define CCM_PRE_ROOT21_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT21_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT21_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT21_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT21_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT21_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT21_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT21_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT21_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT21_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT21_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT21_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT21_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_SET_MUX_A_SHIFT))&CCM_PRE_ROOT21_SET_MUX_A_MASK) -#define CCM_PRE_ROOT21_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT21_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT21_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT21_SET_BUSY4_SHIFT 31 -/* PRE_ROOT21_CLR Bit Fields */ -#define CCM_PRE_ROOT21_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT21_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT21_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT21_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT21_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT21_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT21_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT21_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT21_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT21_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT21_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT21_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT21_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT21_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT21_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT21_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT21_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT21_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT21_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT21_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT21_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT21_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT21_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT21_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT21_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT21_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT21_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT21_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT21_TOG Bit Fields */ -#define CCM_PRE_ROOT21_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT21_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT21_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT21_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT21_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT21_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT21_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT21_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT21_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT21_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT21_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT21_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT21_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT21_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT21_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT21_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT21_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT21_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT21_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT21_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT21_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT21_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT21_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT21_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT21_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT21_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT21_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT21_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL21 Bit Fields */ -#define CCM_ACCESS_CTRL21_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL21_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL21_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL21_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL21_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL21_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL21_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL21_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL21_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL21_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL21_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL21_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL21_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL21_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL21_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL21_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL21_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL21_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL21_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL21_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL21_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL21_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL21_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL21_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL21_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL21_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL21_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL21_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL21_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL21_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL21_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL21_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL21_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL21_LOCK_SHIFT 31 -/* ACCESS_CTRL21_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL21_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL21_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL21_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL21_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL21_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL21_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL21_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL21_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL21_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL21_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL21_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL21_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL21_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL21_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL21_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL21_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT22 Bit Fields */ -#define CCM_TARGET_ROOT22_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT22_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT22_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_POST_PODF_SHIFT))&CCM_TARGET_ROOT22_POST_PODF_MASK) -#define CCM_TARGET_ROOT22_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT22_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT22_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT22_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT22_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT22_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT22_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT22_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT22_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT22_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT22_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_PRE_PODF_SHIFT))&CCM_TARGET_ROOT22_PRE_PODF_MASK) -#define CCM_TARGET_ROOT22_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT22_MUX_SHIFT 24 -#define CCM_TARGET_ROOT22_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_MUX_SHIFT))&CCM_TARGET_ROOT22_MUX_MASK) -#define CCM_TARGET_ROOT22_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT22_ENABLE_SHIFT 28 -/* TARGET_ROOT22_SET Bit Fields */ -#define CCM_TARGET_ROOT22_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT22_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT22_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT22_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT22_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT22_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT22_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT22_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT22_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT22_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT22_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT22_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT22_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT22_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT22_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT22_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT22_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT22_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT22_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_SET_MUX_SHIFT))&CCM_TARGET_ROOT22_SET_MUX_MASK) -#define CCM_TARGET_ROOT22_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT22_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT22_CLR Bit Fields */ -#define CCM_TARGET_ROOT22_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT22_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT22_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT22_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT22_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT22_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT22_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT22_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT22_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT22_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT22_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT22_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT22_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT22_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT22_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT22_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT22_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT22_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT22_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_CLR_MUX_SHIFT))&CCM_TARGET_ROOT22_CLR_MUX_MASK) -#define CCM_TARGET_ROOT22_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT22_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT22_TOG Bit Fields */ -#define CCM_TARGET_ROOT22_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT22_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT22_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT22_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT22_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT22_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT22_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT22_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT22_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT22_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT22_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT22_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT22_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT22_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT22_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT22_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT22_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT22_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT22_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_TOG_MUX_SHIFT))&CCM_TARGET_ROOT22_TOG_MUX_MASK) -#define CCM_TARGET_ROOT22_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT22_TOG_ENABLE_SHIFT 28 -/* POST22 Bit Fields */ -#define CCM_POST22_POST_PODF_MASK 0x3Fu -#define CCM_POST22_POST_PODF_SHIFT 0 -#define CCM_POST22_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST22_POST_PODF_SHIFT))&CCM_POST22_POST_PODF_MASK) -#define CCM_POST22_BUSY1_MASK 0x80u -#define CCM_POST22_BUSY1_SHIFT 7 -#define CCM_POST22_AUTO_PODF_MASK 0x700u -#define CCM_POST22_AUTO_PODF_SHIFT 8 -#define CCM_POST22_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST22_AUTO_PODF_SHIFT))&CCM_POST22_AUTO_PODF_MASK) -#define CCM_POST22_AUTO_EN_MASK 0x1000u -#define CCM_POST22_AUTO_EN_SHIFT 12 -#define CCM_POST22_SLOW_MASK 0x8000u -#define CCM_POST22_SLOW_SHIFT 15 -#define CCM_POST22_SELECT_MASK 0x10000000u -#define CCM_POST22_SELECT_SHIFT 28 -#define CCM_POST22_BUSY2_MASK 0x80000000u -#define CCM_POST22_BUSY2_SHIFT 31 -/* POST_ROOT22_SET Bit Fields */ -#define CCM_POST_ROOT22_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT22_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT22_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_SET_POST_PODF_SHIFT))&CCM_POST_ROOT22_SET_POST_PODF_MASK) -#define CCM_POST_ROOT22_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT22_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT22_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT22_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT22_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT22_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT22_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT22_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT22_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT22_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT22_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT22_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT22_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT22_SET_BUSY2_SHIFT 31 -/* POST_ROOT22_CLR Bit Fields */ -#define CCM_POST_ROOT22_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT22_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT22_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT22_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT22_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT22_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT22_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT22_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT22_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT22_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT22_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT22_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT22_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT22_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT22_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT22_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT22_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT22_CLR_BUSY2_SHIFT 31 -/* POST_ROOT22_TOG Bit Fields */ -#define CCM_POST_ROOT22_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT22_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT22_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT22_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT22_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT22_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT22_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT22_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT22_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT22_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT22_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT22_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT22_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT22_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT22_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT22_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT22_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT22_TOG_BUSY2_SHIFT 31 -/* PRE22 Bit Fields */ -#define CCM_PRE22_PRE_PODF_B_MASK 0x7u -#define CCM_PRE22_PRE_PODF_B_SHIFT 0 -#define CCM_PRE22_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE22_PRE_PODF_B_SHIFT))&CCM_PRE22_PRE_PODF_B_MASK) -#define CCM_PRE22_BUSY0_MASK 0x8u -#define CCM_PRE22_BUSY0_SHIFT 3 -#define CCM_PRE22_MUX_B_MASK 0x700u -#define CCM_PRE22_MUX_B_SHIFT 8 -#define CCM_PRE22_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE22_MUX_B_SHIFT))&CCM_PRE22_MUX_B_MASK) -#define CCM_PRE22_EN_B_MASK 0x1000u -#define CCM_PRE22_EN_B_SHIFT 12 -#define CCM_PRE22_BUSY1_MASK 0x8000u -#define CCM_PRE22_BUSY1_SHIFT 15 -#define CCM_PRE22_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE22_PRE_PODF_A_SHIFT 16 -#define CCM_PRE22_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE22_PRE_PODF_A_SHIFT))&CCM_PRE22_PRE_PODF_A_MASK) -#define CCM_PRE22_BUSY3_MASK 0x80000u -#define CCM_PRE22_BUSY3_SHIFT 19 -#define CCM_PRE22_MUX_A_MASK 0x7000000u -#define CCM_PRE22_MUX_A_SHIFT 24 -#define CCM_PRE22_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE22_MUX_A_SHIFT))&CCM_PRE22_MUX_A_MASK) -#define CCM_PRE22_EN_A_MASK 0x10000000u -#define CCM_PRE22_EN_A_SHIFT 28 -#define CCM_PRE22_BUSY4_MASK 0x80000000u -#define CCM_PRE22_BUSY4_SHIFT 31 -/* PRE_ROOT22_SET Bit Fields */ -#define CCM_PRE_ROOT22_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT22_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT22_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT22_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT22_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT22_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT22_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT22_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT22_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_SET_MUX_B_SHIFT))&CCM_PRE_ROOT22_SET_MUX_B_MASK) -#define CCM_PRE_ROOT22_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT22_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT22_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT22_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT22_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT22_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT22_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT22_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT22_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT22_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT22_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT22_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT22_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_SET_MUX_A_SHIFT))&CCM_PRE_ROOT22_SET_MUX_A_MASK) -#define CCM_PRE_ROOT22_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT22_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT22_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT22_SET_BUSY4_SHIFT 31 -/* PRE_ROOT22_CLR Bit Fields */ -#define CCM_PRE_ROOT22_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT22_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT22_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT22_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT22_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT22_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT22_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT22_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT22_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT22_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT22_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT22_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT22_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT22_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT22_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT22_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT22_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT22_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT22_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT22_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT22_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT22_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT22_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT22_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT22_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT22_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT22_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT22_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT22_TOG Bit Fields */ -#define CCM_PRE_ROOT22_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT22_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT22_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT22_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT22_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT22_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT22_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT22_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT22_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT22_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT22_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT22_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT22_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT22_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT22_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT22_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT22_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT22_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT22_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT22_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT22_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT22_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT22_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT22_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT22_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT22_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT22_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT22_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL22 Bit Fields */ -#define CCM_ACCESS_CTRL22_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL22_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL22_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL22_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL22_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL22_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL22_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL22_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL22_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL22_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL22_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL22_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL22_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL22_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL22_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL22_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL22_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL22_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL22_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL22_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL22_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL22_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL22_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL22_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL22_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL22_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL22_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL22_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL22_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL22_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL22_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL22_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL22_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL22_LOCK_SHIFT 31 -/* ACCESS_CTRL22_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL22_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL22_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL22_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL22_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL22_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL22_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL22_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL22_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL22_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL22_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL22_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL22_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL22_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL22_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL22_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL22_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT23 Bit Fields */ -#define CCM_TARGET_ROOT23_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT23_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT23_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_POST_PODF_SHIFT))&CCM_TARGET_ROOT23_POST_PODF_MASK) -#define CCM_TARGET_ROOT23_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT23_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT23_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT23_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT23_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT23_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT23_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT23_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT23_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT23_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT23_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_PRE_PODF_SHIFT))&CCM_TARGET_ROOT23_PRE_PODF_MASK) -#define CCM_TARGET_ROOT23_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT23_MUX_SHIFT 24 -#define CCM_TARGET_ROOT23_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_MUX_SHIFT))&CCM_TARGET_ROOT23_MUX_MASK) -#define CCM_TARGET_ROOT23_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT23_ENABLE_SHIFT 28 -/* TARGET_ROOT23_SET Bit Fields */ -#define CCM_TARGET_ROOT23_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT23_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT23_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT23_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT23_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT23_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT23_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT23_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT23_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT23_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT23_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT23_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT23_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT23_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT23_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT23_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT23_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT23_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT23_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_SET_MUX_SHIFT))&CCM_TARGET_ROOT23_SET_MUX_MASK) -#define CCM_TARGET_ROOT23_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT23_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT23_CLR Bit Fields */ -#define CCM_TARGET_ROOT23_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT23_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT23_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT23_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT23_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT23_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT23_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT23_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT23_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT23_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT23_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT23_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT23_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT23_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT23_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT23_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT23_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT23_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT23_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_CLR_MUX_SHIFT))&CCM_TARGET_ROOT23_CLR_MUX_MASK) -#define CCM_TARGET_ROOT23_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT23_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT23_TOG Bit Fields */ -#define CCM_TARGET_ROOT23_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT23_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT23_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT23_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT23_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT23_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT23_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT23_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT23_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT23_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT23_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT23_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT23_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT23_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT23_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT23_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT23_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT23_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT23_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_TOG_MUX_SHIFT))&CCM_TARGET_ROOT23_TOG_MUX_MASK) -#define CCM_TARGET_ROOT23_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT23_TOG_ENABLE_SHIFT 28 -/* POST23 Bit Fields */ -#define CCM_POST23_POST_PODF_MASK 0x3Fu -#define CCM_POST23_POST_PODF_SHIFT 0 -#define CCM_POST23_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST23_POST_PODF_SHIFT))&CCM_POST23_POST_PODF_MASK) -#define CCM_POST23_BUSY1_MASK 0x80u -#define CCM_POST23_BUSY1_SHIFT 7 -#define CCM_POST23_AUTO_PODF_MASK 0x700u -#define CCM_POST23_AUTO_PODF_SHIFT 8 -#define CCM_POST23_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST23_AUTO_PODF_SHIFT))&CCM_POST23_AUTO_PODF_MASK) -#define CCM_POST23_AUTO_EN_MASK 0x1000u -#define CCM_POST23_AUTO_EN_SHIFT 12 -#define CCM_POST23_SLOW_MASK 0x8000u -#define CCM_POST23_SLOW_SHIFT 15 -#define CCM_POST23_SELECT_MASK 0x10000000u -#define CCM_POST23_SELECT_SHIFT 28 -#define CCM_POST23_BUSY2_MASK 0x80000000u -#define CCM_POST23_BUSY2_SHIFT 31 -/* POST_ROOT23_SET Bit Fields */ -#define CCM_POST_ROOT23_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT23_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT23_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_SET_POST_PODF_SHIFT))&CCM_POST_ROOT23_SET_POST_PODF_MASK) -#define CCM_POST_ROOT23_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT23_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT23_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT23_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT23_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT23_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT23_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT23_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT23_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT23_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT23_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT23_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT23_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT23_SET_BUSY2_SHIFT 31 -/* POST_ROOT23_CLR Bit Fields */ -#define CCM_POST_ROOT23_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT23_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT23_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT23_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT23_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT23_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT23_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT23_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT23_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT23_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT23_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT23_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT23_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT23_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT23_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT23_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT23_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT23_CLR_BUSY2_SHIFT 31 -/* POST_ROOT23_TOG Bit Fields */ -#define CCM_POST_ROOT23_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT23_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT23_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT23_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT23_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT23_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT23_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT23_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT23_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT23_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT23_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT23_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT23_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT23_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT23_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT23_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT23_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT23_TOG_BUSY2_SHIFT 31 -/* PRE23 Bit Fields */ -#define CCM_PRE23_PRE_PODF_B_MASK 0x7u -#define CCM_PRE23_PRE_PODF_B_SHIFT 0 -#define CCM_PRE23_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE23_PRE_PODF_B_SHIFT))&CCM_PRE23_PRE_PODF_B_MASK) -#define CCM_PRE23_BUSY0_MASK 0x8u -#define CCM_PRE23_BUSY0_SHIFT 3 -#define CCM_PRE23_MUX_B_MASK 0x700u -#define CCM_PRE23_MUX_B_SHIFT 8 -#define CCM_PRE23_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE23_MUX_B_SHIFT))&CCM_PRE23_MUX_B_MASK) -#define CCM_PRE23_EN_B_MASK 0x1000u -#define CCM_PRE23_EN_B_SHIFT 12 -#define CCM_PRE23_BUSY1_MASK 0x8000u -#define CCM_PRE23_BUSY1_SHIFT 15 -#define CCM_PRE23_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE23_PRE_PODF_A_SHIFT 16 -#define CCM_PRE23_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE23_PRE_PODF_A_SHIFT))&CCM_PRE23_PRE_PODF_A_MASK) -#define CCM_PRE23_BUSY3_MASK 0x80000u -#define CCM_PRE23_BUSY3_SHIFT 19 -#define CCM_PRE23_MUX_A_MASK 0x7000000u -#define CCM_PRE23_MUX_A_SHIFT 24 -#define CCM_PRE23_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE23_MUX_A_SHIFT))&CCM_PRE23_MUX_A_MASK) -#define CCM_PRE23_EN_A_MASK 0x10000000u -#define CCM_PRE23_EN_A_SHIFT 28 -#define CCM_PRE23_BUSY4_MASK 0x80000000u -#define CCM_PRE23_BUSY4_SHIFT 31 -/* PRE_ROOT23_SET Bit Fields */ -#define CCM_PRE_ROOT23_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT23_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT23_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT23_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT23_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT23_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT23_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT23_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT23_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_SET_MUX_B_SHIFT))&CCM_PRE_ROOT23_SET_MUX_B_MASK) -#define CCM_PRE_ROOT23_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT23_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT23_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT23_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT23_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT23_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT23_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT23_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT23_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT23_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT23_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT23_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT23_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_SET_MUX_A_SHIFT))&CCM_PRE_ROOT23_SET_MUX_A_MASK) -#define CCM_PRE_ROOT23_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT23_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT23_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT23_SET_BUSY4_SHIFT 31 -/* PRE_ROOT23_CLR Bit Fields */ -#define CCM_PRE_ROOT23_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT23_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT23_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT23_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT23_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT23_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT23_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT23_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT23_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT23_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT23_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT23_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT23_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT23_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT23_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT23_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT23_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT23_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT23_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT23_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT23_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT23_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT23_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT23_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT23_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT23_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT23_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT23_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT23_TOG Bit Fields */ -#define CCM_PRE_ROOT23_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT23_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT23_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT23_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT23_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT23_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT23_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT23_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT23_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT23_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT23_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT23_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT23_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT23_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT23_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT23_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT23_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT23_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT23_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT23_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT23_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT23_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT23_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT23_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT23_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT23_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT23_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT23_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL23 Bit Fields */ -#define CCM_ACCESS_CTRL23_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL23_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL23_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL23_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL23_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL23_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL23_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL23_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL23_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL23_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL23_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL23_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL23_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL23_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL23_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL23_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL23_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL23_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL23_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL23_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL23_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL23_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL23_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL23_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL23_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL23_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL23_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL23_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL23_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL23_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL23_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL23_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL23_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL23_LOCK_SHIFT 31 -/* ACCESS_CTRL23_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL23_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL23_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL23_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL23_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL23_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL23_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL23_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL23_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL23_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL23_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL23_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL23_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL23_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL23_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL23_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL23_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT24 Bit Fields */ -#define CCM_TARGET_ROOT24_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT24_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT24_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_POST_PODF_SHIFT))&CCM_TARGET_ROOT24_POST_PODF_MASK) -#define CCM_TARGET_ROOT24_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT24_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT24_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT24_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT24_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT24_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT24_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT24_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT24_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT24_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT24_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_PRE_PODF_SHIFT))&CCM_TARGET_ROOT24_PRE_PODF_MASK) -#define CCM_TARGET_ROOT24_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT24_MUX_SHIFT 24 -#define CCM_TARGET_ROOT24_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_MUX_SHIFT))&CCM_TARGET_ROOT24_MUX_MASK) -#define CCM_TARGET_ROOT24_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT24_ENABLE_SHIFT 28 -/* TARGET_ROOT24_SET Bit Fields */ -#define CCM_TARGET_ROOT24_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT24_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT24_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT24_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT24_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT24_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT24_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT24_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT24_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT24_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT24_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT24_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT24_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT24_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT24_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT24_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT24_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT24_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT24_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_SET_MUX_SHIFT))&CCM_TARGET_ROOT24_SET_MUX_MASK) -#define CCM_TARGET_ROOT24_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT24_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT24_CLR Bit Fields */ -#define CCM_TARGET_ROOT24_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT24_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT24_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT24_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT24_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT24_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT24_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT24_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT24_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT24_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT24_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT24_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT24_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT24_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT24_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT24_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT24_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT24_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT24_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_CLR_MUX_SHIFT))&CCM_TARGET_ROOT24_CLR_MUX_MASK) -#define CCM_TARGET_ROOT24_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT24_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT24_TOG Bit Fields */ -#define CCM_TARGET_ROOT24_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT24_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT24_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT24_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT24_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT24_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT24_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT24_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT24_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT24_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT24_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT24_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT24_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT24_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT24_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT24_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT24_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT24_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT24_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_TOG_MUX_SHIFT))&CCM_TARGET_ROOT24_TOG_MUX_MASK) -#define CCM_TARGET_ROOT24_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT24_TOG_ENABLE_SHIFT 28 -/* POST24 Bit Fields */ -#define CCM_POST24_POST_PODF_MASK 0x3Fu -#define CCM_POST24_POST_PODF_SHIFT 0 -#define CCM_POST24_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST24_POST_PODF_SHIFT))&CCM_POST24_POST_PODF_MASK) -#define CCM_POST24_BUSY1_MASK 0x80u -#define CCM_POST24_BUSY1_SHIFT 7 -#define CCM_POST24_AUTO_PODF_MASK 0x700u -#define CCM_POST24_AUTO_PODF_SHIFT 8 -#define CCM_POST24_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST24_AUTO_PODF_SHIFT))&CCM_POST24_AUTO_PODF_MASK) -#define CCM_POST24_AUTO_EN_MASK 0x1000u -#define CCM_POST24_AUTO_EN_SHIFT 12 -#define CCM_POST24_SLOW_MASK 0x8000u -#define CCM_POST24_SLOW_SHIFT 15 -#define CCM_POST24_SELECT_MASK 0x10000000u -#define CCM_POST24_SELECT_SHIFT 28 -#define CCM_POST24_BUSY2_MASK 0x80000000u -#define CCM_POST24_BUSY2_SHIFT 31 -/* POST_ROOT24_SET Bit Fields */ -#define CCM_POST_ROOT24_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT24_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT24_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_SET_POST_PODF_SHIFT))&CCM_POST_ROOT24_SET_POST_PODF_MASK) -#define CCM_POST_ROOT24_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT24_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT24_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT24_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT24_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT24_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT24_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT24_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT24_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT24_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT24_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT24_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT24_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT24_SET_BUSY2_SHIFT 31 -/* POST_ROOT24_CLR Bit Fields */ -#define CCM_POST_ROOT24_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT24_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT24_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT24_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT24_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT24_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT24_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT24_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT24_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT24_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT24_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT24_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT24_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT24_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT24_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT24_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT24_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT24_CLR_BUSY2_SHIFT 31 -/* POST_ROOT24_TOG Bit Fields */ -#define CCM_POST_ROOT24_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT24_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT24_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT24_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT24_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT24_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT24_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT24_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT24_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT24_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT24_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT24_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT24_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT24_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT24_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT24_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT24_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT24_TOG_BUSY2_SHIFT 31 -/* PRE24 Bit Fields */ -#define CCM_PRE24_PRE_PODF_B_MASK 0x7u -#define CCM_PRE24_PRE_PODF_B_SHIFT 0 -#define CCM_PRE24_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE24_PRE_PODF_B_SHIFT))&CCM_PRE24_PRE_PODF_B_MASK) -#define CCM_PRE24_BUSY0_MASK 0x8u -#define CCM_PRE24_BUSY0_SHIFT 3 -#define CCM_PRE24_MUX_B_MASK 0x700u -#define CCM_PRE24_MUX_B_SHIFT 8 -#define CCM_PRE24_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE24_MUX_B_SHIFT))&CCM_PRE24_MUX_B_MASK) -#define CCM_PRE24_EN_B_MASK 0x1000u -#define CCM_PRE24_EN_B_SHIFT 12 -#define CCM_PRE24_BUSY1_MASK 0x8000u -#define CCM_PRE24_BUSY1_SHIFT 15 -#define CCM_PRE24_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE24_PRE_PODF_A_SHIFT 16 -#define CCM_PRE24_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE24_PRE_PODF_A_SHIFT))&CCM_PRE24_PRE_PODF_A_MASK) -#define CCM_PRE24_BUSY3_MASK 0x80000u -#define CCM_PRE24_BUSY3_SHIFT 19 -#define CCM_PRE24_MUX_A_MASK 0x7000000u -#define CCM_PRE24_MUX_A_SHIFT 24 -#define CCM_PRE24_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE24_MUX_A_SHIFT))&CCM_PRE24_MUX_A_MASK) -#define CCM_PRE24_EN_A_MASK 0x10000000u -#define CCM_PRE24_EN_A_SHIFT 28 -#define CCM_PRE24_BUSY4_MASK 0x80000000u -#define CCM_PRE24_BUSY4_SHIFT 31 -/* PRE_ROOT24_SET Bit Fields */ -#define CCM_PRE_ROOT24_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT24_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT24_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT24_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT24_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT24_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT24_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT24_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT24_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_SET_MUX_B_SHIFT))&CCM_PRE_ROOT24_SET_MUX_B_MASK) -#define CCM_PRE_ROOT24_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT24_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT24_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT24_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT24_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT24_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT24_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT24_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT24_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT24_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT24_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT24_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT24_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_SET_MUX_A_SHIFT))&CCM_PRE_ROOT24_SET_MUX_A_MASK) -#define CCM_PRE_ROOT24_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT24_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT24_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT24_SET_BUSY4_SHIFT 31 -/* PRE_ROOT24_CLR Bit Fields */ -#define CCM_PRE_ROOT24_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT24_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT24_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT24_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT24_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT24_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT24_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT24_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT24_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT24_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT24_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT24_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT24_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT24_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT24_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT24_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT24_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT24_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT24_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT24_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT24_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT24_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT24_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT24_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT24_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT24_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT24_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT24_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT24_TOG Bit Fields */ -#define CCM_PRE_ROOT24_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT24_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT24_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT24_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT24_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT24_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT24_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT24_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT24_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT24_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT24_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT24_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT24_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT24_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT24_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT24_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT24_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT24_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT24_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT24_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT24_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT24_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT24_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT24_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT24_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT24_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT24_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT24_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL24 Bit Fields */ -#define CCM_ACCESS_CTRL24_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL24_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL24_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL24_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL24_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL24_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL24_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL24_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL24_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL24_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL24_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL24_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL24_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL24_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL24_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL24_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL24_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL24_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL24_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL24_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL24_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL24_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL24_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL24_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL24_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL24_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL24_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL24_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL24_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL24_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL24_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL24_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL24_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL24_LOCK_SHIFT 31 -/* ACCESS_CTRL24_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL24_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL24_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL24_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL24_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL24_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL24_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL24_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL24_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL24_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL24_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL24_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL24_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL24_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL24_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL24_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL24_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT25 Bit Fields */ -#define CCM_TARGET_ROOT25_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT25_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT25_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_POST_PODF_SHIFT))&CCM_TARGET_ROOT25_POST_PODF_MASK) -#define CCM_TARGET_ROOT25_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT25_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT25_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT25_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT25_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT25_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT25_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT25_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT25_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT25_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT25_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_PRE_PODF_SHIFT))&CCM_TARGET_ROOT25_PRE_PODF_MASK) -#define CCM_TARGET_ROOT25_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT25_MUX_SHIFT 24 -#define CCM_TARGET_ROOT25_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_MUX_SHIFT))&CCM_TARGET_ROOT25_MUX_MASK) -#define CCM_TARGET_ROOT25_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT25_ENABLE_SHIFT 28 -/* TARGET_ROOT25_SET Bit Fields */ -#define CCM_TARGET_ROOT25_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT25_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT25_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT25_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT25_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT25_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT25_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT25_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT25_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT25_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT25_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT25_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT25_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT25_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT25_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT25_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT25_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT25_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT25_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_SET_MUX_SHIFT))&CCM_TARGET_ROOT25_SET_MUX_MASK) -#define CCM_TARGET_ROOT25_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT25_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT25_CLR Bit Fields */ -#define CCM_TARGET_ROOT25_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT25_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT25_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT25_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT25_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT25_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT25_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT25_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT25_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT25_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT25_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT25_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT25_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT25_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT25_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT25_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT25_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT25_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT25_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_CLR_MUX_SHIFT))&CCM_TARGET_ROOT25_CLR_MUX_MASK) -#define CCM_TARGET_ROOT25_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT25_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT25_TOG Bit Fields */ -#define CCM_TARGET_ROOT25_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT25_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT25_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT25_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT25_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT25_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT25_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT25_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT25_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT25_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT25_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT25_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT25_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT25_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT25_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT25_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT25_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT25_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT25_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_TOG_MUX_SHIFT))&CCM_TARGET_ROOT25_TOG_MUX_MASK) -#define CCM_TARGET_ROOT25_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT25_TOG_ENABLE_SHIFT 28 -/* POST25 Bit Fields */ -#define CCM_POST25_POST_PODF_MASK 0x3Fu -#define CCM_POST25_POST_PODF_SHIFT 0 -#define CCM_POST25_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST25_POST_PODF_SHIFT))&CCM_POST25_POST_PODF_MASK) -#define CCM_POST25_BUSY1_MASK 0x80u -#define CCM_POST25_BUSY1_SHIFT 7 -#define CCM_POST25_AUTO_PODF_MASK 0x700u -#define CCM_POST25_AUTO_PODF_SHIFT 8 -#define CCM_POST25_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST25_AUTO_PODF_SHIFT))&CCM_POST25_AUTO_PODF_MASK) -#define CCM_POST25_AUTO_EN_MASK 0x1000u -#define CCM_POST25_AUTO_EN_SHIFT 12 -#define CCM_POST25_SLOW_MASK 0x8000u -#define CCM_POST25_SLOW_SHIFT 15 -#define CCM_POST25_SELECT_MASK 0x10000000u -#define CCM_POST25_SELECT_SHIFT 28 -#define CCM_POST25_BUSY2_MASK 0x80000000u -#define CCM_POST25_BUSY2_SHIFT 31 -/* POST_ROOT25_SET Bit Fields */ -#define CCM_POST_ROOT25_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT25_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT25_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_SET_POST_PODF_SHIFT))&CCM_POST_ROOT25_SET_POST_PODF_MASK) -#define CCM_POST_ROOT25_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT25_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT25_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT25_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT25_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT25_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT25_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT25_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT25_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT25_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT25_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT25_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT25_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT25_SET_BUSY2_SHIFT 31 -/* POST_ROOT25_CLR Bit Fields */ -#define CCM_POST_ROOT25_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT25_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT25_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT25_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT25_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT25_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT25_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT25_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT25_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT25_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT25_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT25_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT25_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT25_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT25_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT25_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT25_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT25_CLR_BUSY2_SHIFT 31 -/* POST_ROOT25_TOG Bit Fields */ -#define CCM_POST_ROOT25_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT25_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT25_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT25_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT25_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT25_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT25_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT25_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT25_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT25_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT25_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT25_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT25_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT25_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT25_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT25_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT25_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT25_TOG_BUSY2_SHIFT 31 -/* PRE25 Bit Fields */ -#define CCM_PRE25_PRE_PODF_B_MASK 0x7u -#define CCM_PRE25_PRE_PODF_B_SHIFT 0 -#define CCM_PRE25_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE25_PRE_PODF_B_SHIFT))&CCM_PRE25_PRE_PODF_B_MASK) -#define CCM_PRE25_BUSY0_MASK 0x8u -#define CCM_PRE25_BUSY0_SHIFT 3 -#define CCM_PRE25_MUX_B_MASK 0x700u -#define CCM_PRE25_MUX_B_SHIFT 8 -#define CCM_PRE25_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE25_MUX_B_SHIFT))&CCM_PRE25_MUX_B_MASK) -#define CCM_PRE25_EN_B_MASK 0x1000u -#define CCM_PRE25_EN_B_SHIFT 12 -#define CCM_PRE25_BUSY1_MASK 0x8000u -#define CCM_PRE25_BUSY1_SHIFT 15 -#define CCM_PRE25_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE25_PRE_PODF_A_SHIFT 16 -#define CCM_PRE25_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE25_PRE_PODF_A_SHIFT))&CCM_PRE25_PRE_PODF_A_MASK) -#define CCM_PRE25_BUSY3_MASK 0x80000u -#define CCM_PRE25_BUSY3_SHIFT 19 -#define CCM_PRE25_MUX_A_MASK 0x7000000u -#define CCM_PRE25_MUX_A_SHIFT 24 -#define CCM_PRE25_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE25_MUX_A_SHIFT))&CCM_PRE25_MUX_A_MASK) -#define CCM_PRE25_EN_A_MASK 0x10000000u -#define CCM_PRE25_EN_A_SHIFT 28 -#define CCM_PRE25_BUSY4_MASK 0x80000000u -#define CCM_PRE25_BUSY4_SHIFT 31 -/* PRE_ROOT25_SET Bit Fields */ -#define CCM_PRE_ROOT25_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT25_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT25_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT25_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT25_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT25_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT25_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT25_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT25_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_SET_MUX_B_SHIFT))&CCM_PRE_ROOT25_SET_MUX_B_MASK) -#define CCM_PRE_ROOT25_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT25_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT25_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT25_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT25_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT25_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT25_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT25_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT25_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT25_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT25_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT25_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT25_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_SET_MUX_A_SHIFT))&CCM_PRE_ROOT25_SET_MUX_A_MASK) -#define CCM_PRE_ROOT25_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT25_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT25_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT25_SET_BUSY4_SHIFT 31 -/* PRE_ROOT25_CLR Bit Fields */ -#define CCM_PRE_ROOT25_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT25_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT25_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT25_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT25_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT25_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT25_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT25_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT25_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT25_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT25_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT25_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT25_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT25_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT25_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT25_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT25_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT25_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT25_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT25_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT25_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT25_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT25_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT25_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT25_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT25_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT25_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT25_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT25_TOG Bit Fields */ -#define CCM_PRE_ROOT25_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT25_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT25_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT25_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT25_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT25_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT25_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT25_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT25_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT25_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT25_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT25_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT25_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT25_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT25_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT25_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT25_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT25_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT25_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT25_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT25_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT25_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT25_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT25_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT25_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT25_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT25_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT25_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL25 Bit Fields */ -#define CCM_ACCESS_CTRL25_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL25_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL25_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL25_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL25_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL25_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL25_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL25_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL25_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL25_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL25_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL25_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL25_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL25_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL25_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL25_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL25_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL25_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL25_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL25_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL25_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL25_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL25_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL25_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL25_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL25_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL25_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL25_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL25_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL25_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL25_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL25_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL25_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL25_LOCK_SHIFT 31 -/* ACCESS_CTRL25_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL25_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL25_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL25_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL25_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL25_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL25_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL25_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL25_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL25_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL25_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL25_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL25_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL25_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL25_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL25_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL25_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT26 Bit Fields */ -#define CCM_TARGET_ROOT26_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT26_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT26_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_POST_PODF_SHIFT))&CCM_TARGET_ROOT26_POST_PODF_MASK) -#define CCM_TARGET_ROOT26_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT26_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT26_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT26_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT26_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT26_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT26_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT26_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT26_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT26_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT26_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_PRE_PODF_SHIFT))&CCM_TARGET_ROOT26_PRE_PODF_MASK) -#define CCM_TARGET_ROOT26_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT26_MUX_SHIFT 24 -#define CCM_TARGET_ROOT26_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_MUX_SHIFT))&CCM_TARGET_ROOT26_MUX_MASK) -#define CCM_TARGET_ROOT26_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT26_ENABLE_SHIFT 28 -/* TARGET_ROOT26_SET Bit Fields */ -#define CCM_TARGET_ROOT26_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT26_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT26_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT26_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT26_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT26_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT26_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT26_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT26_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT26_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT26_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT26_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT26_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT26_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT26_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT26_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT26_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT26_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT26_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_SET_MUX_SHIFT))&CCM_TARGET_ROOT26_SET_MUX_MASK) -#define CCM_TARGET_ROOT26_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT26_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT26_CLR Bit Fields */ -#define CCM_TARGET_ROOT26_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT26_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT26_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT26_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT26_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT26_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT26_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT26_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT26_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT26_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT26_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT26_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT26_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT26_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT26_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT26_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT26_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT26_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT26_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_CLR_MUX_SHIFT))&CCM_TARGET_ROOT26_CLR_MUX_MASK) -#define CCM_TARGET_ROOT26_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT26_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT26_TOG Bit Fields */ -#define CCM_TARGET_ROOT26_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT26_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT26_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT26_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT26_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT26_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT26_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT26_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT26_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT26_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT26_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT26_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT26_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT26_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT26_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT26_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT26_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT26_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT26_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_TOG_MUX_SHIFT))&CCM_TARGET_ROOT26_TOG_MUX_MASK) -#define CCM_TARGET_ROOT26_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT26_TOG_ENABLE_SHIFT 28 -/* POST26 Bit Fields */ -#define CCM_POST26_POST_PODF_MASK 0x3Fu -#define CCM_POST26_POST_PODF_SHIFT 0 -#define CCM_POST26_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST26_POST_PODF_SHIFT))&CCM_POST26_POST_PODF_MASK) -#define CCM_POST26_BUSY1_MASK 0x80u -#define CCM_POST26_BUSY1_SHIFT 7 -#define CCM_POST26_AUTO_PODF_MASK 0x700u -#define CCM_POST26_AUTO_PODF_SHIFT 8 -#define CCM_POST26_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST26_AUTO_PODF_SHIFT))&CCM_POST26_AUTO_PODF_MASK) -#define CCM_POST26_AUTO_EN_MASK 0x1000u -#define CCM_POST26_AUTO_EN_SHIFT 12 -#define CCM_POST26_SLOW_MASK 0x8000u -#define CCM_POST26_SLOW_SHIFT 15 -#define CCM_POST26_SELECT_MASK 0x10000000u -#define CCM_POST26_SELECT_SHIFT 28 -#define CCM_POST26_BUSY2_MASK 0x80000000u -#define CCM_POST26_BUSY2_SHIFT 31 -/* POST_ROOT26_SET Bit Fields */ -#define CCM_POST_ROOT26_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT26_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT26_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_SET_POST_PODF_SHIFT))&CCM_POST_ROOT26_SET_POST_PODF_MASK) -#define CCM_POST_ROOT26_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT26_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT26_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT26_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT26_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT26_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT26_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT26_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT26_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT26_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT26_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT26_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT26_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT26_SET_BUSY2_SHIFT 31 -/* POST_ROOT26_CLR Bit Fields */ -#define CCM_POST_ROOT26_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT26_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT26_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT26_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT26_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT26_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT26_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT26_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT26_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT26_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT26_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT26_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT26_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT26_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT26_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT26_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT26_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT26_CLR_BUSY2_SHIFT 31 -/* POST_ROOT26_TOG Bit Fields */ -#define CCM_POST_ROOT26_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT26_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT26_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT26_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT26_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT26_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT26_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT26_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT26_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT26_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT26_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT26_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT26_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT26_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT26_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT26_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT26_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT26_TOG_BUSY2_SHIFT 31 -/* PRE26 Bit Fields */ -#define CCM_PRE26_PRE_PODF_B_MASK 0x7u -#define CCM_PRE26_PRE_PODF_B_SHIFT 0 -#define CCM_PRE26_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE26_PRE_PODF_B_SHIFT))&CCM_PRE26_PRE_PODF_B_MASK) -#define CCM_PRE26_BUSY0_MASK 0x8u -#define CCM_PRE26_BUSY0_SHIFT 3 -#define CCM_PRE26_MUX_B_MASK 0x700u -#define CCM_PRE26_MUX_B_SHIFT 8 -#define CCM_PRE26_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE26_MUX_B_SHIFT))&CCM_PRE26_MUX_B_MASK) -#define CCM_PRE26_EN_B_MASK 0x1000u -#define CCM_PRE26_EN_B_SHIFT 12 -#define CCM_PRE26_BUSY1_MASK 0x8000u -#define CCM_PRE26_BUSY1_SHIFT 15 -#define CCM_PRE26_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE26_PRE_PODF_A_SHIFT 16 -#define CCM_PRE26_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE26_PRE_PODF_A_SHIFT))&CCM_PRE26_PRE_PODF_A_MASK) -#define CCM_PRE26_BUSY3_MASK 0x80000u -#define CCM_PRE26_BUSY3_SHIFT 19 -#define CCM_PRE26_MUX_A_MASK 0x7000000u -#define CCM_PRE26_MUX_A_SHIFT 24 -#define CCM_PRE26_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE26_MUX_A_SHIFT))&CCM_PRE26_MUX_A_MASK) -#define CCM_PRE26_EN_A_MASK 0x10000000u -#define CCM_PRE26_EN_A_SHIFT 28 -#define CCM_PRE26_BUSY4_MASK 0x80000000u -#define CCM_PRE26_BUSY4_SHIFT 31 -/* PRE_ROOT26_SET Bit Fields */ -#define CCM_PRE_ROOT26_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT26_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT26_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT26_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT26_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT26_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT26_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT26_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT26_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_SET_MUX_B_SHIFT))&CCM_PRE_ROOT26_SET_MUX_B_MASK) -#define CCM_PRE_ROOT26_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT26_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT26_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT26_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT26_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT26_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT26_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT26_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT26_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT26_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT26_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT26_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT26_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_SET_MUX_A_SHIFT))&CCM_PRE_ROOT26_SET_MUX_A_MASK) -#define CCM_PRE_ROOT26_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT26_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT26_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT26_SET_BUSY4_SHIFT 31 -/* PRE_ROOT26_CLR Bit Fields */ -#define CCM_PRE_ROOT26_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT26_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT26_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT26_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT26_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT26_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT26_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT26_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT26_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT26_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT26_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT26_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT26_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT26_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT26_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT26_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT26_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT26_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT26_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT26_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT26_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT26_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT26_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT26_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT26_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT26_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT26_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT26_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT26_TOG Bit Fields */ -#define CCM_PRE_ROOT26_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT26_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT26_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT26_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT26_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT26_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT26_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT26_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT26_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT26_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT26_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT26_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT26_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT26_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT26_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT26_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT26_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT26_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT26_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT26_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT26_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT26_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT26_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT26_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT26_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT26_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT26_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT26_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL26 Bit Fields */ -#define CCM_ACCESS_CTRL26_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL26_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL26_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL26_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL26_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL26_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL26_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL26_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL26_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL26_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL26_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL26_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL26_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL26_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL26_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL26_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL26_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL26_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL26_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL26_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL26_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL26_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL26_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL26_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL26_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL26_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL26_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL26_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL26_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL26_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL26_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL26_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL26_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL26_LOCK_SHIFT 31 -/* ACCESS_CTRL26_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL26_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL26_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL26_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL26_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL26_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL26_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL26_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL26_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL26_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL26_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL26_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL26_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL26_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL26_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL26_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL26_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT27 Bit Fields */ -#define CCM_TARGET_ROOT27_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT27_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT27_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_POST_PODF_SHIFT))&CCM_TARGET_ROOT27_POST_PODF_MASK) -#define CCM_TARGET_ROOT27_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT27_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT27_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT27_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT27_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT27_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT27_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT27_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT27_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT27_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT27_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_PRE_PODF_SHIFT))&CCM_TARGET_ROOT27_PRE_PODF_MASK) -#define CCM_TARGET_ROOT27_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT27_MUX_SHIFT 24 -#define CCM_TARGET_ROOT27_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_MUX_SHIFT))&CCM_TARGET_ROOT27_MUX_MASK) -#define CCM_TARGET_ROOT27_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT27_ENABLE_SHIFT 28 -/* TARGET_ROOT27_SET Bit Fields */ -#define CCM_TARGET_ROOT27_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT27_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT27_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT27_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT27_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT27_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT27_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT27_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT27_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT27_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT27_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT27_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT27_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT27_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT27_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT27_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT27_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT27_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT27_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_SET_MUX_SHIFT))&CCM_TARGET_ROOT27_SET_MUX_MASK) -#define CCM_TARGET_ROOT27_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT27_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT27_CLR Bit Fields */ -#define CCM_TARGET_ROOT27_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT27_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT27_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT27_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT27_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT27_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT27_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT27_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT27_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT27_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT27_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT27_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT27_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT27_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT27_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT27_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT27_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT27_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT27_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_CLR_MUX_SHIFT))&CCM_TARGET_ROOT27_CLR_MUX_MASK) -#define CCM_TARGET_ROOT27_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT27_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT27_TOG Bit Fields */ -#define CCM_TARGET_ROOT27_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT27_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT27_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT27_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT27_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT27_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT27_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT27_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT27_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT27_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT27_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT27_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT27_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT27_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT27_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT27_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT27_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT27_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT27_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_TOG_MUX_SHIFT))&CCM_TARGET_ROOT27_TOG_MUX_MASK) -#define CCM_TARGET_ROOT27_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT27_TOG_ENABLE_SHIFT 28 -/* POST27 Bit Fields */ -#define CCM_POST27_POST_PODF_MASK 0x3Fu -#define CCM_POST27_POST_PODF_SHIFT 0 -#define CCM_POST27_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST27_POST_PODF_SHIFT))&CCM_POST27_POST_PODF_MASK) -#define CCM_POST27_BUSY1_MASK 0x80u -#define CCM_POST27_BUSY1_SHIFT 7 -#define CCM_POST27_AUTO_PODF_MASK 0x700u -#define CCM_POST27_AUTO_PODF_SHIFT 8 -#define CCM_POST27_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST27_AUTO_PODF_SHIFT))&CCM_POST27_AUTO_PODF_MASK) -#define CCM_POST27_AUTO_EN_MASK 0x1000u -#define CCM_POST27_AUTO_EN_SHIFT 12 -#define CCM_POST27_SLOW_MASK 0x8000u -#define CCM_POST27_SLOW_SHIFT 15 -#define CCM_POST27_SELECT_MASK 0x10000000u -#define CCM_POST27_SELECT_SHIFT 28 -#define CCM_POST27_BUSY2_MASK 0x80000000u -#define CCM_POST27_BUSY2_SHIFT 31 -/* POST_ROOT27_SET Bit Fields */ -#define CCM_POST_ROOT27_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT27_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT27_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_SET_POST_PODF_SHIFT))&CCM_POST_ROOT27_SET_POST_PODF_MASK) -#define CCM_POST_ROOT27_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT27_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT27_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT27_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT27_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT27_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT27_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT27_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT27_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT27_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT27_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT27_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT27_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT27_SET_BUSY2_SHIFT 31 -/* POST_ROOT27_CLR Bit Fields */ -#define CCM_POST_ROOT27_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT27_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT27_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT27_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT27_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT27_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT27_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT27_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT27_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT27_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT27_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT27_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT27_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT27_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT27_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT27_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT27_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT27_CLR_BUSY2_SHIFT 31 -/* POST_ROOT27_TOG Bit Fields */ -#define CCM_POST_ROOT27_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT27_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT27_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT27_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT27_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT27_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT27_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT27_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT27_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT27_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT27_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT27_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT27_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT27_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT27_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT27_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT27_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT27_TOG_BUSY2_SHIFT 31 -/* PRE27 Bit Fields */ -#define CCM_PRE27_PRE_PODF_B_MASK 0x7u -#define CCM_PRE27_PRE_PODF_B_SHIFT 0 -#define CCM_PRE27_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE27_PRE_PODF_B_SHIFT))&CCM_PRE27_PRE_PODF_B_MASK) -#define CCM_PRE27_BUSY0_MASK 0x8u -#define CCM_PRE27_BUSY0_SHIFT 3 -#define CCM_PRE27_MUX_B_MASK 0x700u -#define CCM_PRE27_MUX_B_SHIFT 8 -#define CCM_PRE27_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE27_MUX_B_SHIFT))&CCM_PRE27_MUX_B_MASK) -#define CCM_PRE27_EN_B_MASK 0x1000u -#define CCM_PRE27_EN_B_SHIFT 12 -#define CCM_PRE27_BUSY1_MASK 0x8000u -#define CCM_PRE27_BUSY1_SHIFT 15 -#define CCM_PRE27_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE27_PRE_PODF_A_SHIFT 16 -#define CCM_PRE27_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE27_PRE_PODF_A_SHIFT))&CCM_PRE27_PRE_PODF_A_MASK) -#define CCM_PRE27_BUSY3_MASK 0x80000u -#define CCM_PRE27_BUSY3_SHIFT 19 -#define CCM_PRE27_MUX_A_MASK 0x7000000u -#define CCM_PRE27_MUX_A_SHIFT 24 -#define CCM_PRE27_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE27_MUX_A_SHIFT))&CCM_PRE27_MUX_A_MASK) -#define CCM_PRE27_EN_A_MASK 0x10000000u -#define CCM_PRE27_EN_A_SHIFT 28 -#define CCM_PRE27_BUSY4_MASK 0x80000000u -#define CCM_PRE27_BUSY4_SHIFT 31 -/* PRE_ROOT27_SET Bit Fields */ -#define CCM_PRE_ROOT27_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT27_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT27_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT27_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT27_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT27_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT27_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT27_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT27_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_SET_MUX_B_SHIFT))&CCM_PRE_ROOT27_SET_MUX_B_MASK) -#define CCM_PRE_ROOT27_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT27_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT27_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT27_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT27_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT27_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT27_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT27_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT27_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT27_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT27_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT27_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT27_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_SET_MUX_A_SHIFT))&CCM_PRE_ROOT27_SET_MUX_A_MASK) -#define CCM_PRE_ROOT27_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT27_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT27_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT27_SET_BUSY4_SHIFT 31 -/* PRE_ROOT27_CLR Bit Fields */ -#define CCM_PRE_ROOT27_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT27_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT27_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT27_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT27_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT27_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT27_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT27_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT27_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT27_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT27_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT27_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT27_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT27_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT27_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT27_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT27_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT27_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT27_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT27_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT27_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT27_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT27_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT27_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT27_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT27_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT27_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT27_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT27_TOG Bit Fields */ -#define CCM_PRE_ROOT27_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT27_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT27_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT27_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT27_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT27_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT27_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT27_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT27_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT27_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT27_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT27_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT27_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT27_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT27_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT27_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT27_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT27_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT27_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT27_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT27_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT27_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT27_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT27_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT27_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT27_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT27_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT27_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL27 Bit Fields */ -#define CCM_ACCESS_CTRL27_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL27_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL27_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL27_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL27_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL27_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL27_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL27_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL27_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL27_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL27_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL27_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL27_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL27_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL27_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL27_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL27_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL27_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL27_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL27_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL27_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL27_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL27_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL27_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL27_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL27_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL27_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL27_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL27_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL27_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL27_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL27_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL27_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL27_LOCK_SHIFT 31 -/* ACCESS_CTRL27_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL27_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL27_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL27_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL27_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL27_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL27_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL27_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL27_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL27_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL27_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL27_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL27_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL27_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL27_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL27_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL27_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT28 Bit Fields */ -#define CCM_TARGET_ROOT28_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT28_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT28_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_POST_PODF_SHIFT))&CCM_TARGET_ROOT28_POST_PODF_MASK) -#define CCM_TARGET_ROOT28_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT28_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT28_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT28_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT28_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT28_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT28_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT28_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT28_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT28_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT28_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_PRE_PODF_SHIFT))&CCM_TARGET_ROOT28_PRE_PODF_MASK) -#define CCM_TARGET_ROOT28_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT28_MUX_SHIFT 24 -#define CCM_TARGET_ROOT28_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_MUX_SHIFT))&CCM_TARGET_ROOT28_MUX_MASK) -#define CCM_TARGET_ROOT28_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT28_ENABLE_SHIFT 28 -/* TARGET_ROOT28_SET Bit Fields */ -#define CCM_TARGET_ROOT28_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT28_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT28_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT28_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT28_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT28_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT28_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT28_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT28_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT28_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT28_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT28_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT28_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT28_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT28_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT28_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT28_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT28_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT28_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_SET_MUX_SHIFT))&CCM_TARGET_ROOT28_SET_MUX_MASK) -#define CCM_TARGET_ROOT28_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT28_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT28_CLR Bit Fields */ -#define CCM_TARGET_ROOT28_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT28_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT28_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT28_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT28_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT28_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT28_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT28_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT28_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT28_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT28_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT28_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT28_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT28_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT28_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT28_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT28_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT28_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT28_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_CLR_MUX_SHIFT))&CCM_TARGET_ROOT28_CLR_MUX_MASK) -#define CCM_TARGET_ROOT28_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT28_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT28_TOG Bit Fields */ -#define CCM_TARGET_ROOT28_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT28_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT28_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT28_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT28_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT28_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT28_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT28_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT28_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT28_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT28_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT28_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT28_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT28_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT28_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT28_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT28_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT28_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT28_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_TOG_MUX_SHIFT))&CCM_TARGET_ROOT28_TOG_MUX_MASK) -#define CCM_TARGET_ROOT28_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT28_TOG_ENABLE_SHIFT 28 -/* POST28 Bit Fields */ -#define CCM_POST28_POST_PODF_MASK 0x3Fu -#define CCM_POST28_POST_PODF_SHIFT 0 -#define CCM_POST28_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST28_POST_PODF_SHIFT))&CCM_POST28_POST_PODF_MASK) -#define CCM_POST28_BUSY1_MASK 0x80u -#define CCM_POST28_BUSY1_SHIFT 7 -#define CCM_POST28_AUTO_PODF_MASK 0x700u -#define CCM_POST28_AUTO_PODF_SHIFT 8 -#define CCM_POST28_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST28_AUTO_PODF_SHIFT))&CCM_POST28_AUTO_PODF_MASK) -#define CCM_POST28_AUTO_EN_MASK 0x1000u -#define CCM_POST28_AUTO_EN_SHIFT 12 -#define CCM_POST28_SLOW_MASK 0x8000u -#define CCM_POST28_SLOW_SHIFT 15 -#define CCM_POST28_SELECT_MASK 0x10000000u -#define CCM_POST28_SELECT_SHIFT 28 -#define CCM_POST28_BUSY2_MASK 0x80000000u -#define CCM_POST28_BUSY2_SHIFT 31 -/* POST_ROOT28_SET Bit Fields */ -#define CCM_POST_ROOT28_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT28_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT28_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_SET_POST_PODF_SHIFT))&CCM_POST_ROOT28_SET_POST_PODF_MASK) -#define CCM_POST_ROOT28_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT28_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT28_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT28_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT28_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT28_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT28_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT28_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT28_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT28_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT28_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT28_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT28_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT28_SET_BUSY2_SHIFT 31 -/* POST_ROOT28_CLR Bit Fields */ -#define CCM_POST_ROOT28_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT28_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT28_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT28_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT28_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT28_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT28_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT28_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT28_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT28_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT28_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT28_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT28_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT28_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT28_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT28_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT28_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT28_CLR_BUSY2_SHIFT 31 -/* POST_ROOT28_TOG Bit Fields */ -#define CCM_POST_ROOT28_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT28_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT28_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT28_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT28_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT28_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT28_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT28_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT28_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT28_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT28_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT28_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT28_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT28_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT28_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT28_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT28_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT28_TOG_BUSY2_SHIFT 31 -/* PRE28 Bit Fields */ -#define CCM_PRE28_PRE_PODF_B_MASK 0x7u -#define CCM_PRE28_PRE_PODF_B_SHIFT 0 -#define CCM_PRE28_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE28_PRE_PODF_B_SHIFT))&CCM_PRE28_PRE_PODF_B_MASK) -#define CCM_PRE28_BUSY0_MASK 0x8u -#define CCM_PRE28_BUSY0_SHIFT 3 -#define CCM_PRE28_MUX_B_MASK 0x700u -#define CCM_PRE28_MUX_B_SHIFT 8 -#define CCM_PRE28_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE28_MUX_B_SHIFT))&CCM_PRE28_MUX_B_MASK) -#define CCM_PRE28_EN_B_MASK 0x1000u -#define CCM_PRE28_EN_B_SHIFT 12 -#define CCM_PRE28_BUSY1_MASK 0x8000u -#define CCM_PRE28_BUSY1_SHIFT 15 -#define CCM_PRE28_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE28_PRE_PODF_A_SHIFT 16 -#define CCM_PRE28_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE28_PRE_PODF_A_SHIFT))&CCM_PRE28_PRE_PODF_A_MASK) -#define CCM_PRE28_BUSY3_MASK 0x80000u -#define CCM_PRE28_BUSY3_SHIFT 19 -#define CCM_PRE28_MUX_A_MASK 0x7000000u -#define CCM_PRE28_MUX_A_SHIFT 24 -#define CCM_PRE28_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE28_MUX_A_SHIFT))&CCM_PRE28_MUX_A_MASK) -#define CCM_PRE28_EN_A_MASK 0x10000000u -#define CCM_PRE28_EN_A_SHIFT 28 -#define CCM_PRE28_BUSY4_MASK 0x80000000u -#define CCM_PRE28_BUSY4_SHIFT 31 -/* PRE_ROOT28_SET Bit Fields */ -#define CCM_PRE_ROOT28_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT28_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT28_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT28_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT28_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT28_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT28_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT28_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT28_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_SET_MUX_B_SHIFT))&CCM_PRE_ROOT28_SET_MUX_B_MASK) -#define CCM_PRE_ROOT28_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT28_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT28_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT28_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT28_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT28_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT28_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT28_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT28_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT28_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT28_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT28_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT28_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_SET_MUX_A_SHIFT))&CCM_PRE_ROOT28_SET_MUX_A_MASK) -#define CCM_PRE_ROOT28_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT28_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT28_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT28_SET_BUSY4_SHIFT 31 -/* PRE_ROOT28_CLR Bit Fields */ -#define CCM_PRE_ROOT28_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT28_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT28_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT28_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT28_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT28_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT28_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT28_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT28_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT28_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT28_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT28_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT28_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT28_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT28_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT28_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT28_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT28_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT28_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT28_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT28_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT28_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT28_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT28_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT28_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT28_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT28_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT28_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT28_TOG Bit Fields */ -#define CCM_PRE_ROOT28_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT28_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT28_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT28_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT28_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT28_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT28_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT28_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT28_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT28_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT28_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT28_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT28_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT28_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT28_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT28_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT28_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT28_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT28_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT28_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT28_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT28_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT28_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT28_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT28_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT28_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT28_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT28_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL28 Bit Fields */ -#define CCM_ACCESS_CTRL28_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL28_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL28_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL28_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL28_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL28_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL28_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL28_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL28_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL28_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL28_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL28_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL28_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL28_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL28_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL28_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL28_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL28_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL28_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL28_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL28_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL28_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL28_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL28_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL28_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL28_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL28_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL28_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL28_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL28_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL28_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL28_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL28_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL28_LOCK_SHIFT 31 -/* ACCESS_CTRL28_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL28_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL28_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL28_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL28_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL28_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL28_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL28_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL28_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL28_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL28_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL28_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL28_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL28_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL28_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL28_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL28_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT29 Bit Fields */ -#define CCM_TARGET_ROOT29_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT29_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT29_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_POST_PODF_SHIFT))&CCM_TARGET_ROOT29_POST_PODF_MASK) -#define CCM_TARGET_ROOT29_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT29_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT29_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT29_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT29_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT29_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT29_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT29_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT29_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT29_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT29_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_PRE_PODF_SHIFT))&CCM_TARGET_ROOT29_PRE_PODF_MASK) -#define CCM_TARGET_ROOT29_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT29_MUX_SHIFT 24 -#define CCM_TARGET_ROOT29_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_MUX_SHIFT))&CCM_TARGET_ROOT29_MUX_MASK) -#define CCM_TARGET_ROOT29_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT29_ENABLE_SHIFT 28 -/* TARGET_ROOT29_SET Bit Fields */ -#define CCM_TARGET_ROOT29_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT29_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT29_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT29_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT29_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT29_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT29_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT29_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT29_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT29_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT29_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT29_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT29_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT29_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT29_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT29_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT29_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT29_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT29_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_SET_MUX_SHIFT))&CCM_TARGET_ROOT29_SET_MUX_MASK) -#define CCM_TARGET_ROOT29_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT29_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT29_CLR Bit Fields */ -#define CCM_TARGET_ROOT29_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT29_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT29_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT29_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT29_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT29_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT29_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT29_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT29_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT29_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT29_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT29_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT29_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT29_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT29_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT29_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT29_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT29_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT29_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_CLR_MUX_SHIFT))&CCM_TARGET_ROOT29_CLR_MUX_MASK) -#define CCM_TARGET_ROOT29_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT29_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT29_TOG Bit Fields */ -#define CCM_TARGET_ROOT29_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT29_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT29_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT29_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT29_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT29_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT29_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT29_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT29_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT29_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT29_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT29_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT29_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT29_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT29_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT29_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT29_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT29_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT29_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_TOG_MUX_SHIFT))&CCM_TARGET_ROOT29_TOG_MUX_MASK) -#define CCM_TARGET_ROOT29_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT29_TOG_ENABLE_SHIFT 28 -/* POST29 Bit Fields */ -#define CCM_POST29_POST_PODF_MASK 0x3Fu -#define CCM_POST29_POST_PODF_SHIFT 0 -#define CCM_POST29_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST29_POST_PODF_SHIFT))&CCM_POST29_POST_PODF_MASK) -#define CCM_POST29_BUSY1_MASK 0x80u -#define CCM_POST29_BUSY1_SHIFT 7 -#define CCM_POST29_AUTO_PODF_MASK 0x700u -#define CCM_POST29_AUTO_PODF_SHIFT 8 -#define CCM_POST29_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST29_AUTO_PODF_SHIFT))&CCM_POST29_AUTO_PODF_MASK) -#define CCM_POST29_AUTO_EN_MASK 0x1000u -#define CCM_POST29_AUTO_EN_SHIFT 12 -#define CCM_POST29_SLOW_MASK 0x8000u -#define CCM_POST29_SLOW_SHIFT 15 -#define CCM_POST29_SELECT_MASK 0x10000000u -#define CCM_POST29_SELECT_SHIFT 28 -#define CCM_POST29_BUSY2_MASK 0x80000000u -#define CCM_POST29_BUSY2_SHIFT 31 -/* POST_ROOT29_SET Bit Fields */ -#define CCM_POST_ROOT29_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT29_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT29_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_SET_POST_PODF_SHIFT))&CCM_POST_ROOT29_SET_POST_PODF_MASK) -#define CCM_POST_ROOT29_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT29_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT29_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT29_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT29_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT29_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT29_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT29_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT29_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT29_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT29_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT29_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT29_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT29_SET_BUSY2_SHIFT 31 -/* POST_ROOT29_CLR Bit Fields */ -#define CCM_POST_ROOT29_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT29_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT29_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT29_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT29_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT29_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT29_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT29_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT29_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT29_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT29_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT29_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT29_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT29_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT29_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT29_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT29_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT29_CLR_BUSY2_SHIFT 31 -/* POST_ROOT29_TOG Bit Fields */ -#define CCM_POST_ROOT29_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT29_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT29_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT29_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT29_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT29_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT29_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT29_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT29_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT29_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT29_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT29_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT29_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT29_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT29_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT29_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT29_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT29_TOG_BUSY2_SHIFT 31 -/* PRE29 Bit Fields */ -#define CCM_PRE29_PRE_PODF_B_MASK 0x7u -#define CCM_PRE29_PRE_PODF_B_SHIFT 0 -#define CCM_PRE29_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE29_PRE_PODF_B_SHIFT))&CCM_PRE29_PRE_PODF_B_MASK) -#define CCM_PRE29_BUSY0_MASK 0x8u -#define CCM_PRE29_BUSY0_SHIFT 3 -#define CCM_PRE29_MUX_B_MASK 0x700u -#define CCM_PRE29_MUX_B_SHIFT 8 -#define CCM_PRE29_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE29_MUX_B_SHIFT))&CCM_PRE29_MUX_B_MASK) -#define CCM_PRE29_EN_B_MASK 0x1000u -#define CCM_PRE29_EN_B_SHIFT 12 -#define CCM_PRE29_BUSY1_MASK 0x8000u -#define CCM_PRE29_BUSY1_SHIFT 15 -#define CCM_PRE29_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE29_PRE_PODF_A_SHIFT 16 -#define CCM_PRE29_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE29_PRE_PODF_A_SHIFT))&CCM_PRE29_PRE_PODF_A_MASK) -#define CCM_PRE29_BUSY3_MASK 0x80000u -#define CCM_PRE29_BUSY3_SHIFT 19 -#define CCM_PRE29_MUX_A_MASK 0x7000000u -#define CCM_PRE29_MUX_A_SHIFT 24 -#define CCM_PRE29_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE29_MUX_A_SHIFT))&CCM_PRE29_MUX_A_MASK) -#define CCM_PRE29_EN_A_MASK 0x10000000u -#define CCM_PRE29_EN_A_SHIFT 28 -#define CCM_PRE29_BUSY4_MASK 0x80000000u -#define CCM_PRE29_BUSY4_SHIFT 31 -/* PRE_ROOT29_SET Bit Fields */ -#define CCM_PRE_ROOT29_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT29_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT29_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT29_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT29_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT29_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT29_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT29_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT29_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_SET_MUX_B_SHIFT))&CCM_PRE_ROOT29_SET_MUX_B_MASK) -#define CCM_PRE_ROOT29_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT29_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT29_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT29_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT29_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT29_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT29_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT29_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT29_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT29_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT29_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT29_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT29_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_SET_MUX_A_SHIFT))&CCM_PRE_ROOT29_SET_MUX_A_MASK) -#define CCM_PRE_ROOT29_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT29_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT29_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT29_SET_BUSY4_SHIFT 31 -/* PRE_ROOT29_CLR Bit Fields */ -#define CCM_PRE_ROOT29_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT29_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT29_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT29_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT29_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT29_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT29_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT29_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT29_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT29_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT29_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT29_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT29_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT29_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT29_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT29_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT29_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT29_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT29_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT29_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT29_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT29_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT29_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT29_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT29_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT29_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT29_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT29_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT29_TOG Bit Fields */ -#define CCM_PRE_ROOT29_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT29_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT29_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT29_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT29_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT29_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT29_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT29_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT29_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT29_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT29_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT29_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT29_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT29_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT29_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT29_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT29_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT29_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT29_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT29_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT29_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT29_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT29_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT29_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT29_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT29_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT29_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT29_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL29 Bit Fields */ -#define CCM_ACCESS_CTRL29_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL29_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL29_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL29_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL29_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL29_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL29_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL29_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL29_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL29_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL29_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL29_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL29_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL29_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL29_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL29_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL29_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL29_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL29_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL29_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL29_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL29_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL29_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL29_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL29_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL29_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL29_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL29_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL29_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL29_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL29_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL29_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL29_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL29_LOCK_SHIFT 31 -/* ACCESS_CTRL29_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL29_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL29_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL29_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL29_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL29_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL29_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL29_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL29_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL29_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL29_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL29_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL29_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL29_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL29_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL29_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL29_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT30 Bit Fields */ -#define CCM_TARGET_ROOT30_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT30_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT30_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_POST_PODF_SHIFT))&CCM_TARGET_ROOT30_POST_PODF_MASK) -#define CCM_TARGET_ROOT30_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT30_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT30_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT30_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT30_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT30_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT30_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT30_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT30_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT30_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT30_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_PRE_PODF_SHIFT))&CCM_TARGET_ROOT30_PRE_PODF_MASK) -#define CCM_TARGET_ROOT30_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT30_MUX_SHIFT 24 -#define CCM_TARGET_ROOT30_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_MUX_SHIFT))&CCM_TARGET_ROOT30_MUX_MASK) -#define CCM_TARGET_ROOT30_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT30_ENABLE_SHIFT 28 -/* TARGET_ROOT30_SET Bit Fields */ -#define CCM_TARGET_ROOT30_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT30_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT30_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT30_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT30_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT30_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT30_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT30_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT30_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT30_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT30_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT30_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT30_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT30_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT30_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT30_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT30_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT30_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT30_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_SET_MUX_SHIFT))&CCM_TARGET_ROOT30_SET_MUX_MASK) -#define CCM_TARGET_ROOT30_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT30_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT30_CLR Bit Fields */ -#define CCM_TARGET_ROOT30_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT30_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT30_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT30_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT30_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT30_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT30_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT30_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT30_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT30_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT30_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT30_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT30_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT30_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT30_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT30_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT30_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT30_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT30_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_CLR_MUX_SHIFT))&CCM_TARGET_ROOT30_CLR_MUX_MASK) -#define CCM_TARGET_ROOT30_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT30_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT30_TOG Bit Fields */ -#define CCM_TARGET_ROOT30_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT30_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT30_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT30_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT30_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT30_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT30_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT30_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT30_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT30_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT30_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT30_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT30_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT30_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT30_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT30_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT30_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT30_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT30_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_TOG_MUX_SHIFT))&CCM_TARGET_ROOT30_TOG_MUX_MASK) -#define CCM_TARGET_ROOT30_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT30_TOG_ENABLE_SHIFT 28 -/* POST30 Bit Fields */ -#define CCM_POST30_POST_PODF_MASK 0x3Fu -#define CCM_POST30_POST_PODF_SHIFT 0 -#define CCM_POST30_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST30_POST_PODF_SHIFT))&CCM_POST30_POST_PODF_MASK) -#define CCM_POST30_BUSY1_MASK 0x80u -#define CCM_POST30_BUSY1_SHIFT 7 -#define CCM_POST30_AUTO_PODF_MASK 0x700u -#define CCM_POST30_AUTO_PODF_SHIFT 8 -#define CCM_POST30_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST30_AUTO_PODF_SHIFT))&CCM_POST30_AUTO_PODF_MASK) -#define CCM_POST30_AUTO_EN_MASK 0x1000u -#define CCM_POST30_AUTO_EN_SHIFT 12 -#define CCM_POST30_SLOW_MASK 0x8000u -#define CCM_POST30_SLOW_SHIFT 15 -#define CCM_POST30_SELECT_MASK 0x10000000u -#define CCM_POST30_SELECT_SHIFT 28 -#define CCM_POST30_BUSY2_MASK 0x80000000u -#define CCM_POST30_BUSY2_SHIFT 31 -/* POST_ROOT30_SET Bit Fields */ -#define CCM_POST_ROOT30_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT30_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT30_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_SET_POST_PODF_SHIFT))&CCM_POST_ROOT30_SET_POST_PODF_MASK) -#define CCM_POST_ROOT30_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT30_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT30_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT30_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT30_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT30_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT30_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT30_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT30_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT30_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT30_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT30_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT30_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT30_SET_BUSY2_SHIFT 31 -/* POST_ROOT30_CLR Bit Fields */ -#define CCM_POST_ROOT30_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT30_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT30_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT30_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT30_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT30_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT30_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT30_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT30_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT30_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT30_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT30_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT30_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT30_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT30_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT30_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT30_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT30_CLR_BUSY2_SHIFT 31 -/* POST_ROOT30_TOG Bit Fields */ -#define CCM_POST_ROOT30_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT30_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT30_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT30_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT30_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT30_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT30_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT30_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT30_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT30_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT30_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT30_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT30_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT30_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT30_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT30_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT30_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT30_TOG_BUSY2_SHIFT 31 -/* PRE30 Bit Fields */ -#define CCM_PRE30_PRE_PODF_B_MASK 0x7u -#define CCM_PRE30_PRE_PODF_B_SHIFT 0 -#define CCM_PRE30_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE30_PRE_PODF_B_SHIFT))&CCM_PRE30_PRE_PODF_B_MASK) -#define CCM_PRE30_BUSY0_MASK 0x8u -#define CCM_PRE30_BUSY0_SHIFT 3 -#define CCM_PRE30_MUX_B_MASK 0x700u -#define CCM_PRE30_MUX_B_SHIFT 8 -#define CCM_PRE30_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE30_MUX_B_SHIFT))&CCM_PRE30_MUX_B_MASK) -#define CCM_PRE30_EN_B_MASK 0x1000u -#define CCM_PRE30_EN_B_SHIFT 12 -#define CCM_PRE30_BUSY1_MASK 0x8000u -#define CCM_PRE30_BUSY1_SHIFT 15 -#define CCM_PRE30_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE30_PRE_PODF_A_SHIFT 16 -#define CCM_PRE30_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE30_PRE_PODF_A_SHIFT))&CCM_PRE30_PRE_PODF_A_MASK) -#define CCM_PRE30_BUSY3_MASK 0x80000u -#define CCM_PRE30_BUSY3_SHIFT 19 -#define CCM_PRE30_MUX_A_MASK 0x7000000u -#define CCM_PRE30_MUX_A_SHIFT 24 -#define CCM_PRE30_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE30_MUX_A_SHIFT))&CCM_PRE30_MUX_A_MASK) -#define CCM_PRE30_EN_A_MASK 0x10000000u -#define CCM_PRE30_EN_A_SHIFT 28 -#define CCM_PRE30_BUSY4_MASK 0x80000000u -#define CCM_PRE30_BUSY4_SHIFT 31 -/* PRE_ROOT30_SET Bit Fields */ -#define CCM_PRE_ROOT30_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT30_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT30_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT30_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT30_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT30_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT30_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT30_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT30_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_SET_MUX_B_SHIFT))&CCM_PRE_ROOT30_SET_MUX_B_MASK) -#define CCM_PRE_ROOT30_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT30_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT30_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT30_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT30_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT30_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT30_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT30_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT30_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT30_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT30_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT30_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT30_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_SET_MUX_A_SHIFT))&CCM_PRE_ROOT30_SET_MUX_A_MASK) -#define CCM_PRE_ROOT30_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT30_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT30_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT30_SET_BUSY4_SHIFT 31 -/* PRE_ROOT30_CLR Bit Fields */ -#define CCM_PRE_ROOT30_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT30_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT30_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT30_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT30_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT30_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT30_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT30_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT30_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT30_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT30_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT30_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT30_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT30_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT30_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT30_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT30_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT30_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT30_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT30_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT30_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT30_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT30_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT30_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT30_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT30_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT30_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT30_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT30_TOG Bit Fields */ -#define CCM_PRE_ROOT30_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT30_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT30_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT30_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT30_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT30_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT30_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT30_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT30_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT30_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT30_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT30_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT30_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT30_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT30_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT30_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT30_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT30_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT30_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT30_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT30_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT30_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT30_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT30_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT30_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT30_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT30_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT30_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL30 Bit Fields */ -#define CCM_ACCESS_CTRL30_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL30_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL30_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL30_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL30_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL30_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL30_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL30_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL30_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL30_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL30_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL30_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL30_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL30_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL30_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL30_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL30_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL30_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL30_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL30_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL30_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL30_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL30_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL30_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL30_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL30_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL30_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL30_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL30_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL30_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL30_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL30_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL30_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL30_LOCK_SHIFT 31 -/* ACCESS_CTRL30_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL30_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL30_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL30_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL30_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL30_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL30_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL30_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL30_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL30_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL30_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL30_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL30_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL30_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL30_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL30_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL30_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT31 Bit Fields */ -#define CCM_TARGET_ROOT31_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT31_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT31_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_POST_PODF_SHIFT))&CCM_TARGET_ROOT31_POST_PODF_MASK) -#define CCM_TARGET_ROOT31_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT31_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT31_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT31_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT31_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT31_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT31_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT31_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT31_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT31_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT31_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_PRE_PODF_SHIFT))&CCM_TARGET_ROOT31_PRE_PODF_MASK) -#define CCM_TARGET_ROOT31_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT31_MUX_SHIFT 24 -#define CCM_TARGET_ROOT31_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_MUX_SHIFT))&CCM_TARGET_ROOT31_MUX_MASK) -#define CCM_TARGET_ROOT31_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT31_ENABLE_SHIFT 28 -/* TARGET_ROOT31_SET Bit Fields */ -#define CCM_TARGET_ROOT31_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT31_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT31_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT31_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT31_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT31_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT31_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT31_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT31_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT31_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT31_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT31_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT31_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT31_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT31_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT31_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT31_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT31_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT31_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_SET_MUX_SHIFT))&CCM_TARGET_ROOT31_SET_MUX_MASK) -#define CCM_TARGET_ROOT31_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT31_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT31_CLR Bit Fields */ -#define CCM_TARGET_ROOT31_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT31_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT31_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT31_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT31_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT31_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT31_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT31_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT31_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT31_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT31_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT31_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT31_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT31_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT31_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT31_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT31_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT31_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT31_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_CLR_MUX_SHIFT))&CCM_TARGET_ROOT31_CLR_MUX_MASK) -#define CCM_TARGET_ROOT31_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT31_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT31_TOG Bit Fields */ -#define CCM_TARGET_ROOT31_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT31_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT31_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT31_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT31_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT31_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT31_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT31_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT31_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT31_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT31_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT31_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT31_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT31_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT31_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT31_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT31_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT31_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT31_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_TOG_MUX_SHIFT))&CCM_TARGET_ROOT31_TOG_MUX_MASK) -#define CCM_TARGET_ROOT31_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT31_TOG_ENABLE_SHIFT 28 -/* POST31 Bit Fields */ -#define CCM_POST31_POST_PODF_MASK 0x3Fu -#define CCM_POST31_POST_PODF_SHIFT 0 -#define CCM_POST31_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST31_POST_PODF_SHIFT))&CCM_POST31_POST_PODF_MASK) -#define CCM_POST31_BUSY1_MASK 0x80u -#define CCM_POST31_BUSY1_SHIFT 7 -#define CCM_POST31_AUTO_PODF_MASK 0x700u -#define CCM_POST31_AUTO_PODF_SHIFT 8 -#define CCM_POST31_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST31_AUTO_PODF_SHIFT))&CCM_POST31_AUTO_PODF_MASK) -#define CCM_POST31_AUTO_EN_MASK 0x1000u -#define CCM_POST31_AUTO_EN_SHIFT 12 -#define CCM_POST31_SLOW_MASK 0x8000u -#define CCM_POST31_SLOW_SHIFT 15 -#define CCM_POST31_SELECT_MASK 0x10000000u -#define CCM_POST31_SELECT_SHIFT 28 -#define CCM_POST31_BUSY2_MASK 0x80000000u -#define CCM_POST31_BUSY2_SHIFT 31 -/* POST_ROOT31_SET Bit Fields */ -#define CCM_POST_ROOT31_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT31_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT31_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_SET_POST_PODF_SHIFT))&CCM_POST_ROOT31_SET_POST_PODF_MASK) -#define CCM_POST_ROOT31_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT31_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT31_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT31_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT31_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT31_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT31_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT31_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT31_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT31_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT31_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT31_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT31_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT31_SET_BUSY2_SHIFT 31 -/* POST_ROOT31_CLR Bit Fields */ -#define CCM_POST_ROOT31_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT31_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT31_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT31_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT31_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT31_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT31_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT31_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT31_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT31_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT31_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT31_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT31_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT31_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT31_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT31_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT31_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT31_CLR_BUSY2_SHIFT 31 -/* POST_ROOT31_TOG Bit Fields */ -#define CCM_POST_ROOT31_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT31_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT31_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT31_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT31_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT31_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT31_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT31_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT31_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT31_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT31_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT31_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT31_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT31_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT31_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT31_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT31_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT31_TOG_BUSY2_SHIFT 31 -/* PRE31 Bit Fields */ -#define CCM_PRE31_PRE_PODF_B_MASK 0x7u -#define CCM_PRE31_PRE_PODF_B_SHIFT 0 -#define CCM_PRE31_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE31_PRE_PODF_B_SHIFT))&CCM_PRE31_PRE_PODF_B_MASK) -#define CCM_PRE31_BUSY0_MASK 0x8u -#define CCM_PRE31_BUSY0_SHIFT 3 -#define CCM_PRE31_MUX_B_MASK 0x700u -#define CCM_PRE31_MUX_B_SHIFT 8 -#define CCM_PRE31_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE31_MUX_B_SHIFT))&CCM_PRE31_MUX_B_MASK) -#define CCM_PRE31_EN_B_MASK 0x1000u -#define CCM_PRE31_EN_B_SHIFT 12 -#define CCM_PRE31_BUSY1_MASK 0x8000u -#define CCM_PRE31_BUSY1_SHIFT 15 -#define CCM_PRE31_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE31_PRE_PODF_A_SHIFT 16 -#define CCM_PRE31_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE31_PRE_PODF_A_SHIFT))&CCM_PRE31_PRE_PODF_A_MASK) -#define CCM_PRE31_BUSY3_MASK 0x80000u -#define CCM_PRE31_BUSY3_SHIFT 19 -#define CCM_PRE31_MUX_A_MASK 0x7000000u -#define CCM_PRE31_MUX_A_SHIFT 24 -#define CCM_PRE31_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE31_MUX_A_SHIFT))&CCM_PRE31_MUX_A_MASK) -#define CCM_PRE31_EN_A_MASK 0x10000000u -#define CCM_PRE31_EN_A_SHIFT 28 -#define CCM_PRE31_BUSY4_MASK 0x80000000u -#define CCM_PRE31_BUSY4_SHIFT 31 -/* PRE_ROOT31_SET Bit Fields */ -#define CCM_PRE_ROOT31_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT31_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT31_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT31_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT31_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT31_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT31_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT31_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT31_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_SET_MUX_B_SHIFT))&CCM_PRE_ROOT31_SET_MUX_B_MASK) -#define CCM_PRE_ROOT31_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT31_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT31_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT31_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT31_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT31_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT31_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT31_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT31_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT31_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT31_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT31_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT31_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_SET_MUX_A_SHIFT))&CCM_PRE_ROOT31_SET_MUX_A_MASK) -#define CCM_PRE_ROOT31_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT31_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT31_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT31_SET_BUSY4_SHIFT 31 -/* PRE_ROOT31_CLR Bit Fields */ -#define CCM_PRE_ROOT31_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT31_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT31_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT31_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT31_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT31_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT31_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT31_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT31_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT31_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT31_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT31_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT31_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT31_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT31_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT31_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT31_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT31_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT31_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT31_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT31_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT31_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT31_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT31_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT31_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT31_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT31_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT31_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT31_TOG Bit Fields */ -#define CCM_PRE_ROOT31_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT31_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT31_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT31_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT31_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT31_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT31_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT31_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT31_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT31_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT31_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT31_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT31_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT31_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT31_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT31_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT31_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT31_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT31_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT31_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT31_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT31_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT31_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT31_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT31_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT31_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT31_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT31_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL31 Bit Fields */ -#define CCM_ACCESS_CTRL31_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL31_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL31_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL31_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL31_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL31_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL31_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL31_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL31_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL31_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL31_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL31_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL31_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL31_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL31_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL31_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL31_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL31_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL31_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL31_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL31_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL31_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL31_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL31_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL31_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL31_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL31_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL31_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL31_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL31_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL31_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL31_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL31_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL31_LOCK_SHIFT 31 -/* ACCESS_CTRL31_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL31_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL31_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL31_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL31_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL31_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL31_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL31_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL31_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL31_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL31_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL31_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL31_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL31_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL31_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL31_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL31_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT32 Bit Fields */ -#define CCM_TARGET_ROOT32_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT32_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT32_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_POST_PODF_SHIFT))&CCM_TARGET_ROOT32_POST_PODF_MASK) -#define CCM_TARGET_ROOT32_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT32_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT32_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT32_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT32_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT32_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT32_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT32_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT32_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT32_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT32_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_PRE_PODF_SHIFT))&CCM_TARGET_ROOT32_PRE_PODF_MASK) -#define CCM_TARGET_ROOT32_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT32_MUX_SHIFT 24 -#define CCM_TARGET_ROOT32_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_MUX_SHIFT))&CCM_TARGET_ROOT32_MUX_MASK) -#define CCM_TARGET_ROOT32_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT32_ENABLE_SHIFT 28 -/* TARGET_ROOT32_SET Bit Fields */ -#define CCM_TARGET_ROOT32_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT32_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT32_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT32_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT32_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT32_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT32_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT32_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT32_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT32_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT32_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT32_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT32_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT32_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT32_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT32_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT32_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT32_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT32_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_SET_MUX_SHIFT))&CCM_TARGET_ROOT32_SET_MUX_MASK) -#define CCM_TARGET_ROOT32_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT32_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT32_CLR Bit Fields */ -#define CCM_TARGET_ROOT32_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT32_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT32_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT32_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT32_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT32_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT32_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT32_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT32_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT32_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT32_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT32_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT32_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT32_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT32_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT32_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT32_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT32_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT32_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_CLR_MUX_SHIFT))&CCM_TARGET_ROOT32_CLR_MUX_MASK) -#define CCM_TARGET_ROOT32_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT32_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT32_TOG Bit Fields */ -#define CCM_TARGET_ROOT32_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT32_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT32_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT32_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT32_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT32_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT32_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT32_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT32_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT32_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT32_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT32_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT32_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT32_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT32_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT32_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT32_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT32_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT32_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_TOG_MUX_SHIFT))&CCM_TARGET_ROOT32_TOG_MUX_MASK) -#define CCM_TARGET_ROOT32_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT32_TOG_ENABLE_SHIFT 28 -/* POST32 Bit Fields */ -#define CCM_POST32_POST_PODF_MASK 0x3Fu -#define CCM_POST32_POST_PODF_SHIFT 0 -#define CCM_POST32_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST32_POST_PODF_SHIFT))&CCM_POST32_POST_PODF_MASK) -#define CCM_POST32_BUSY1_MASK 0x80u -#define CCM_POST32_BUSY1_SHIFT 7 -#define CCM_POST32_AUTO_PODF_MASK 0x700u -#define CCM_POST32_AUTO_PODF_SHIFT 8 -#define CCM_POST32_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST32_AUTO_PODF_SHIFT))&CCM_POST32_AUTO_PODF_MASK) -#define CCM_POST32_AUTO_EN_MASK 0x1000u -#define CCM_POST32_AUTO_EN_SHIFT 12 -#define CCM_POST32_SLOW_MASK 0x8000u -#define CCM_POST32_SLOW_SHIFT 15 -#define CCM_POST32_SELECT_MASK 0x10000000u -#define CCM_POST32_SELECT_SHIFT 28 -#define CCM_POST32_BUSY2_MASK 0x80000000u -#define CCM_POST32_BUSY2_SHIFT 31 -/* POST_ROOT32_SET Bit Fields */ -#define CCM_POST_ROOT32_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT32_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT32_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_SET_POST_PODF_SHIFT))&CCM_POST_ROOT32_SET_POST_PODF_MASK) -#define CCM_POST_ROOT32_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT32_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT32_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT32_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT32_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT32_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT32_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT32_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT32_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT32_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT32_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT32_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT32_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT32_SET_BUSY2_SHIFT 31 -/* POST_ROOT32_CLR Bit Fields */ -#define CCM_POST_ROOT32_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT32_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT32_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT32_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT32_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT32_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT32_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT32_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT32_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT32_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT32_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT32_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT32_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT32_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT32_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT32_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT32_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT32_CLR_BUSY2_SHIFT 31 -/* POST_ROOT32_TOG Bit Fields */ -#define CCM_POST_ROOT32_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT32_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT32_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT32_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT32_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT32_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT32_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT32_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT32_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT32_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT32_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT32_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT32_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT32_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT32_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT32_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT32_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT32_TOG_BUSY2_SHIFT 31 -/* PRE32 Bit Fields */ -#define CCM_PRE32_PRE_PODF_B_MASK 0x7u -#define CCM_PRE32_PRE_PODF_B_SHIFT 0 -#define CCM_PRE32_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE32_PRE_PODF_B_SHIFT))&CCM_PRE32_PRE_PODF_B_MASK) -#define CCM_PRE32_BUSY0_MASK 0x8u -#define CCM_PRE32_BUSY0_SHIFT 3 -#define CCM_PRE32_MUX_B_MASK 0x700u -#define CCM_PRE32_MUX_B_SHIFT 8 -#define CCM_PRE32_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE32_MUX_B_SHIFT))&CCM_PRE32_MUX_B_MASK) -#define CCM_PRE32_EN_B_MASK 0x1000u -#define CCM_PRE32_EN_B_SHIFT 12 -#define CCM_PRE32_BUSY1_MASK 0x8000u -#define CCM_PRE32_BUSY1_SHIFT 15 -#define CCM_PRE32_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE32_PRE_PODF_A_SHIFT 16 -#define CCM_PRE32_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE32_PRE_PODF_A_SHIFT))&CCM_PRE32_PRE_PODF_A_MASK) -#define CCM_PRE32_BUSY3_MASK 0x80000u -#define CCM_PRE32_BUSY3_SHIFT 19 -#define CCM_PRE32_MUX_A_MASK 0x7000000u -#define CCM_PRE32_MUX_A_SHIFT 24 -#define CCM_PRE32_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE32_MUX_A_SHIFT))&CCM_PRE32_MUX_A_MASK) -#define CCM_PRE32_EN_A_MASK 0x10000000u -#define CCM_PRE32_EN_A_SHIFT 28 -#define CCM_PRE32_BUSY4_MASK 0x80000000u -#define CCM_PRE32_BUSY4_SHIFT 31 -/* PRE_ROOT32_SET Bit Fields */ -#define CCM_PRE_ROOT32_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT32_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT32_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT32_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT32_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT32_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT32_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT32_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT32_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_SET_MUX_B_SHIFT))&CCM_PRE_ROOT32_SET_MUX_B_MASK) -#define CCM_PRE_ROOT32_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT32_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT32_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT32_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT32_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT32_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT32_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT32_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT32_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT32_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT32_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT32_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT32_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_SET_MUX_A_SHIFT))&CCM_PRE_ROOT32_SET_MUX_A_MASK) -#define CCM_PRE_ROOT32_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT32_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT32_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT32_SET_BUSY4_SHIFT 31 -/* PRE_ROOT32_CLR Bit Fields */ -#define CCM_PRE_ROOT32_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT32_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT32_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT32_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT32_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT32_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT32_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT32_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT32_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT32_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT32_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT32_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT32_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT32_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT32_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT32_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT32_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT32_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT32_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT32_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT32_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT32_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT32_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT32_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT32_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT32_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT32_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT32_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT32_TOG Bit Fields */ -#define CCM_PRE_ROOT32_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT32_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT32_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT32_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT32_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT32_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT32_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT32_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT32_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT32_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT32_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT32_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT32_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT32_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT32_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT32_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT32_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT32_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT32_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT32_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT32_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT32_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT32_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT32_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT32_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT32_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT32_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT32_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL32 Bit Fields */ -#define CCM_ACCESS_CTRL32_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL32_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL32_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL32_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL32_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL32_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL32_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL32_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL32_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL32_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL32_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL32_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL32_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL32_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL32_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL32_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL32_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL32_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL32_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL32_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL32_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL32_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL32_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL32_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL32_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL32_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL32_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL32_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL32_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL32_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL32_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL32_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL32_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL32_LOCK_SHIFT 31 -/* ACCESS_CTRL32_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL32_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL32_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL32_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL32_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL32_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL32_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL32_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL32_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL32_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL32_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL32_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL32_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL32_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL32_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL32_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL32_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT33 Bit Fields */ -#define CCM_TARGET_ROOT33_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT33_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT33_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_POST_PODF_SHIFT))&CCM_TARGET_ROOT33_POST_PODF_MASK) -#define CCM_TARGET_ROOT33_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT33_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT33_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT33_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT33_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT33_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT33_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT33_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT33_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT33_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT33_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_PRE_PODF_SHIFT))&CCM_TARGET_ROOT33_PRE_PODF_MASK) -#define CCM_TARGET_ROOT33_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT33_MUX_SHIFT 24 -#define CCM_TARGET_ROOT33_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_MUX_SHIFT))&CCM_TARGET_ROOT33_MUX_MASK) -#define CCM_TARGET_ROOT33_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT33_ENABLE_SHIFT 28 -/* TARGET_ROOT33_SET Bit Fields */ -#define CCM_TARGET_ROOT33_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT33_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT33_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT33_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT33_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT33_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT33_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT33_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT33_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT33_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT33_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT33_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT33_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT33_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT33_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT33_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT33_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT33_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT33_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_SET_MUX_SHIFT))&CCM_TARGET_ROOT33_SET_MUX_MASK) -#define CCM_TARGET_ROOT33_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT33_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT33_CLR Bit Fields */ -#define CCM_TARGET_ROOT33_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT33_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT33_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT33_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT33_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT33_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT33_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT33_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT33_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT33_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT33_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT33_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT33_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT33_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT33_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT33_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT33_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT33_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT33_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_CLR_MUX_SHIFT))&CCM_TARGET_ROOT33_CLR_MUX_MASK) -#define CCM_TARGET_ROOT33_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT33_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT33_TOG Bit Fields */ -#define CCM_TARGET_ROOT33_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT33_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT33_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT33_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT33_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT33_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT33_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT33_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT33_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT33_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT33_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT33_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT33_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT33_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT33_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT33_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT33_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT33_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT33_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_TOG_MUX_SHIFT))&CCM_TARGET_ROOT33_TOG_MUX_MASK) -#define CCM_TARGET_ROOT33_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT33_TOG_ENABLE_SHIFT 28 -/* POST33 Bit Fields */ -#define CCM_POST33_POST_PODF_MASK 0x3Fu -#define CCM_POST33_POST_PODF_SHIFT 0 -#define CCM_POST33_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST33_POST_PODF_SHIFT))&CCM_POST33_POST_PODF_MASK) -#define CCM_POST33_BUSY1_MASK 0x80u -#define CCM_POST33_BUSY1_SHIFT 7 -#define CCM_POST33_AUTO_PODF_MASK 0x700u -#define CCM_POST33_AUTO_PODF_SHIFT 8 -#define CCM_POST33_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST33_AUTO_PODF_SHIFT))&CCM_POST33_AUTO_PODF_MASK) -#define CCM_POST33_AUTO_EN_MASK 0x1000u -#define CCM_POST33_AUTO_EN_SHIFT 12 -#define CCM_POST33_SLOW_MASK 0x8000u -#define CCM_POST33_SLOW_SHIFT 15 -#define CCM_POST33_SELECT_MASK 0x10000000u -#define CCM_POST33_SELECT_SHIFT 28 -#define CCM_POST33_BUSY2_MASK 0x80000000u -#define CCM_POST33_BUSY2_SHIFT 31 -/* POST_ROOT33_SET Bit Fields */ -#define CCM_POST_ROOT33_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT33_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT33_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_SET_POST_PODF_SHIFT))&CCM_POST_ROOT33_SET_POST_PODF_MASK) -#define CCM_POST_ROOT33_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT33_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT33_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT33_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT33_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT33_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT33_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT33_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT33_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT33_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT33_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT33_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT33_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT33_SET_BUSY2_SHIFT 31 -/* POST_ROOT33_CLR Bit Fields */ -#define CCM_POST_ROOT33_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT33_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT33_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT33_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT33_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT33_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT33_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT33_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT33_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT33_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT33_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT33_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT33_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT33_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT33_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT33_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT33_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT33_CLR_BUSY2_SHIFT 31 -/* POST_ROOT33_TOG Bit Fields */ -#define CCM_POST_ROOT33_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT33_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT33_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT33_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT33_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT33_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT33_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT33_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT33_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT33_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT33_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT33_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT33_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT33_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT33_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT33_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT33_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT33_TOG_BUSY2_SHIFT 31 -/* PRE33 Bit Fields */ -#define CCM_PRE33_PRE_PODF_B_MASK 0x7u -#define CCM_PRE33_PRE_PODF_B_SHIFT 0 -#define CCM_PRE33_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE33_PRE_PODF_B_SHIFT))&CCM_PRE33_PRE_PODF_B_MASK) -#define CCM_PRE33_BUSY0_MASK 0x8u -#define CCM_PRE33_BUSY0_SHIFT 3 -#define CCM_PRE33_MUX_B_MASK 0x700u -#define CCM_PRE33_MUX_B_SHIFT 8 -#define CCM_PRE33_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE33_MUX_B_SHIFT))&CCM_PRE33_MUX_B_MASK) -#define CCM_PRE33_EN_B_MASK 0x1000u -#define CCM_PRE33_EN_B_SHIFT 12 -#define CCM_PRE33_BUSY1_MASK 0x8000u -#define CCM_PRE33_BUSY1_SHIFT 15 -#define CCM_PRE33_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE33_PRE_PODF_A_SHIFT 16 -#define CCM_PRE33_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE33_PRE_PODF_A_SHIFT))&CCM_PRE33_PRE_PODF_A_MASK) -#define CCM_PRE33_BUSY3_MASK 0x80000u -#define CCM_PRE33_BUSY3_SHIFT 19 -#define CCM_PRE33_MUX_A_MASK 0x7000000u -#define CCM_PRE33_MUX_A_SHIFT 24 -#define CCM_PRE33_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE33_MUX_A_SHIFT))&CCM_PRE33_MUX_A_MASK) -#define CCM_PRE33_EN_A_MASK 0x10000000u -#define CCM_PRE33_EN_A_SHIFT 28 -#define CCM_PRE33_BUSY4_MASK 0x80000000u -#define CCM_PRE33_BUSY4_SHIFT 31 -/* PRE_ROOT33_SET Bit Fields */ -#define CCM_PRE_ROOT33_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT33_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT33_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT33_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT33_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT33_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT33_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT33_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT33_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_SET_MUX_B_SHIFT))&CCM_PRE_ROOT33_SET_MUX_B_MASK) -#define CCM_PRE_ROOT33_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT33_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT33_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT33_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT33_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT33_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT33_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT33_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT33_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT33_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT33_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT33_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT33_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_SET_MUX_A_SHIFT))&CCM_PRE_ROOT33_SET_MUX_A_MASK) -#define CCM_PRE_ROOT33_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT33_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT33_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT33_SET_BUSY4_SHIFT 31 -/* PRE_ROOT33_CLR Bit Fields */ -#define CCM_PRE_ROOT33_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT33_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT33_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT33_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT33_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT33_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT33_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT33_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT33_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT33_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT33_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT33_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT33_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT33_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT33_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT33_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT33_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT33_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT33_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT33_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT33_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT33_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT33_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT33_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT33_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT33_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT33_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT33_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT33_TOG Bit Fields */ -#define CCM_PRE_ROOT33_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT33_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT33_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT33_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT33_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT33_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT33_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT33_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT33_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT33_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT33_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT33_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT33_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT33_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT33_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT33_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT33_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT33_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT33_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT33_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT33_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT33_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT33_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT33_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT33_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT33_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT33_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT33_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL33 Bit Fields */ -#define CCM_ACCESS_CTRL33_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL33_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL33_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL33_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL33_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL33_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL33_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL33_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL33_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL33_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL33_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL33_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL33_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL33_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL33_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL33_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL33_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL33_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL33_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL33_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL33_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL33_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL33_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL33_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL33_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL33_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL33_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL33_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL33_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL33_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL33_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL33_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL33_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL33_LOCK_SHIFT 31 -/* ACCESS_CTRL33_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL33_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL33_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL33_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL33_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL33_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL33_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL33_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL33_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL33_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL33_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL33_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL33_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL33_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL33_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL33_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL33_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT34 Bit Fields */ -#define CCM_TARGET_ROOT34_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT34_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT34_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_POST_PODF_SHIFT))&CCM_TARGET_ROOT34_POST_PODF_MASK) -#define CCM_TARGET_ROOT34_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT34_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT34_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT34_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT34_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT34_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT34_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT34_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT34_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT34_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT34_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_PRE_PODF_SHIFT))&CCM_TARGET_ROOT34_PRE_PODF_MASK) -#define CCM_TARGET_ROOT34_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT34_MUX_SHIFT 24 -#define CCM_TARGET_ROOT34_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_MUX_SHIFT))&CCM_TARGET_ROOT34_MUX_MASK) -#define CCM_TARGET_ROOT34_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT34_ENABLE_SHIFT 28 -/* TARGET_ROOT34_SET Bit Fields */ -#define CCM_TARGET_ROOT34_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT34_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT34_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT34_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT34_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT34_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT34_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT34_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT34_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT34_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT34_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT34_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT34_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT34_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT34_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT34_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT34_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT34_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT34_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_SET_MUX_SHIFT))&CCM_TARGET_ROOT34_SET_MUX_MASK) -#define CCM_TARGET_ROOT34_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT34_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT34_CLR Bit Fields */ -#define CCM_TARGET_ROOT34_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT34_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT34_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT34_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT34_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT34_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT34_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT34_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT34_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT34_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT34_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT34_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT34_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT34_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT34_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT34_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT34_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT34_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT34_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_CLR_MUX_SHIFT))&CCM_TARGET_ROOT34_CLR_MUX_MASK) -#define CCM_TARGET_ROOT34_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT34_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT34_TOG Bit Fields */ -#define CCM_TARGET_ROOT34_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT34_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT34_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT34_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT34_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT34_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT34_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT34_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT34_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT34_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT34_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT34_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT34_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT34_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT34_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT34_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT34_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT34_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT34_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_TOG_MUX_SHIFT))&CCM_TARGET_ROOT34_TOG_MUX_MASK) -#define CCM_TARGET_ROOT34_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT34_TOG_ENABLE_SHIFT 28 -/* POST34 Bit Fields */ -#define CCM_POST34_POST_PODF_MASK 0x3Fu -#define CCM_POST34_POST_PODF_SHIFT 0 -#define CCM_POST34_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST34_POST_PODF_SHIFT))&CCM_POST34_POST_PODF_MASK) -#define CCM_POST34_BUSY1_MASK 0x80u -#define CCM_POST34_BUSY1_SHIFT 7 -#define CCM_POST34_AUTO_PODF_MASK 0x700u -#define CCM_POST34_AUTO_PODF_SHIFT 8 -#define CCM_POST34_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST34_AUTO_PODF_SHIFT))&CCM_POST34_AUTO_PODF_MASK) -#define CCM_POST34_AUTO_EN_MASK 0x1000u -#define CCM_POST34_AUTO_EN_SHIFT 12 -#define CCM_POST34_SLOW_MASK 0x8000u -#define CCM_POST34_SLOW_SHIFT 15 -#define CCM_POST34_SELECT_MASK 0x10000000u -#define CCM_POST34_SELECT_SHIFT 28 -#define CCM_POST34_BUSY2_MASK 0x80000000u -#define CCM_POST34_BUSY2_SHIFT 31 -/* POST_ROOT34_SET Bit Fields */ -#define CCM_POST_ROOT34_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT34_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT34_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_SET_POST_PODF_SHIFT))&CCM_POST_ROOT34_SET_POST_PODF_MASK) -#define CCM_POST_ROOT34_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT34_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT34_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT34_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT34_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT34_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT34_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT34_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT34_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT34_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT34_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT34_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT34_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT34_SET_BUSY2_SHIFT 31 -/* POST_ROOT34_CLR Bit Fields */ -#define CCM_POST_ROOT34_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT34_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT34_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT34_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT34_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT34_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT34_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT34_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT34_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT34_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT34_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT34_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT34_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT34_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT34_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT34_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT34_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT34_CLR_BUSY2_SHIFT 31 -/* POST_ROOT34_TOG Bit Fields */ -#define CCM_POST_ROOT34_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT34_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT34_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT34_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT34_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT34_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT34_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT34_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT34_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT34_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT34_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT34_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT34_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT34_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT34_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT34_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT34_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT34_TOG_BUSY2_SHIFT 31 -/* PRE34 Bit Fields */ -#define CCM_PRE34_PRE_PODF_B_MASK 0x7u -#define CCM_PRE34_PRE_PODF_B_SHIFT 0 -#define CCM_PRE34_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE34_PRE_PODF_B_SHIFT))&CCM_PRE34_PRE_PODF_B_MASK) -#define CCM_PRE34_BUSY0_MASK 0x8u -#define CCM_PRE34_BUSY0_SHIFT 3 -#define CCM_PRE34_MUX_B_MASK 0x700u -#define CCM_PRE34_MUX_B_SHIFT 8 -#define CCM_PRE34_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE34_MUX_B_SHIFT))&CCM_PRE34_MUX_B_MASK) -#define CCM_PRE34_EN_B_MASK 0x1000u -#define CCM_PRE34_EN_B_SHIFT 12 -#define CCM_PRE34_BUSY1_MASK 0x8000u -#define CCM_PRE34_BUSY1_SHIFT 15 -#define CCM_PRE34_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE34_PRE_PODF_A_SHIFT 16 -#define CCM_PRE34_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE34_PRE_PODF_A_SHIFT))&CCM_PRE34_PRE_PODF_A_MASK) -#define CCM_PRE34_BUSY3_MASK 0x80000u -#define CCM_PRE34_BUSY3_SHIFT 19 -#define CCM_PRE34_MUX_A_MASK 0x7000000u -#define CCM_PRE34_MUX_A_SHIFT 24 -#define CCM_PRE34_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE34_MUX_A_SHIFT))&CCM_PRE34_MUX_A_MASK) -#define CCM_PRE34_EN_A_MASK 0x10000000u -#define CCM_PRE34_EN_A_SHIFT 28 -#define CCM_PRE34_BUSY4_MASK 0x80000000u -#define CCM_PRE34_BUSY4_SHIFT 31 -/* PRE_ROOT34_SET Bit Fields */ -#define CCM_PRE_ROOT34_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT34_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT34_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT34_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT34_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT34_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT34_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT34_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT34_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_SET_MUX_B_SHIFT))&CCM_PRE_ROOT34_SET_MUX_B_MASK) -#define CCM_PRE_ROOT34_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT34_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT34_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT34_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT34_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT34_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT34_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT34_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT34_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT34_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT34_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT34_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT34_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_SET_MUX_A_SHIFT))&CCM_PRE_ROOT34_SET_MUX_A_MASK) -#define CCM_PRE_ROOT34_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT34_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT34_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT34_SET_BUSY4_SHIFT 31 -/* PRE_ROOT34_CLR Bit Fields */ -#define CCM_PRE_ROOT34_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT34_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT34_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT34_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT34_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT34_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT34_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT34_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT34_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT34_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT34_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT34_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT34_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT34_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT34_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT34_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT34_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT34_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT34_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT34_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT34_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT34_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT34_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT34_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT34_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT34_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT34_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT34_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT34_TOG Bit Fields */ -#define CCM_PRE_ROOT34_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT34_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT34_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT34_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT34_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT34_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT34_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT34_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT34_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT34_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT34_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT34_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT34_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT34_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT34_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT34_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT34_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT34_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT34_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT34_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT34_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT34_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT34_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT34_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT34_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT34_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT34_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT34_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL34 Bit Fields */ -#define CCM_ACCESS_CTRL34_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL34_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL34_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL34_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL34_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL34_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL34_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL34_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL34_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL34_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL34_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL34_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL34_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL34_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL34_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL34_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL34_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL34_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL34_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL34_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL34_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL34_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL34_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL34_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL34_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL34_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL34_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL34_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL34_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL34_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL34_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL34_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL34_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL34_LOCK_SHIFT 31 -/* ACCESS_CTRL34_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL34_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL34_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL34_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL34_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL34_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL34_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL34_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL34_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL34_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL34_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL34_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL34_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL34_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL34_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL34_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL34_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT35 Bit Fields */ -#define CCM_TARGET_ROOT35_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT35_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT35_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_POST_PODF_SHIFT))&CCM_TARGET_ROOT35_POST_PODF_MASK) -#define CCM_TARGET_ROOT35_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT35_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT35_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT35_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT35_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT35_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT35_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT35_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT35_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT35_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT35_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_PRE_PODF_SHIFT))&CCM_TARGET_ROOT35_PRE_PODF_MASK) -#define CCM_TARGET_ROOT35_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT35_MUX_SHIFT 24 -#define CCM_TARGET_ROOT35_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_MUX_SHIFT))&CCM_TARGET_ROOT35_MUX_MASK) -#define CCM_TARGET_ROOT35_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT35_ENABLE_SHIFT 28 -/* TARGET_ROOT35_SET Bit Fields */ -#define CCM_TARGET_ROOT35_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT35_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT35_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT35_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT35_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT35_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT35_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT35_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT35_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT35_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT35_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT35_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT35_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT35_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT35_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT35_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT35_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT35_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT35_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_SET_MUX_SHIFT))&CCM_TARGET_ROOT35_SET_MUX_MASK) -#define CCM_TARGET_ROOT35_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT35_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT35_CLR Bit Fields */ -#define CCM_TARGET_ROOT35_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT35_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT35_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT35_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT35_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT35_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT35_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT35_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT35_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT35_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT35_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT35_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT35_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT35_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT35_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT35_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT35_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT35_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT35_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_CLR_MUX_SHIFT))&CCM_TARGET_ROOT35_CLR_MUX_MASK) -#define CCM_TARGET_ROOT35_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT35_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT35_TOG Bit Fields */ -#define CCM_TARGET_ROOT35_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT35_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT35_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT35_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT35_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT35_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT35_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT35_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT35_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT35_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT35_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT35_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT35_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT35_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT35_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT35_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT35_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT35_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT35_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_TOG_MUX_SHIFT))&CCM_TARGET_ROOT35_TOG_MUX_MASK) -#define CCM_TARGET_ROOT35_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT35_TOG_ENABLE_SHIFT 28 -/* POST35 Bit Fields */ -#define CCM_POST35_POST_PODF_MASK 0x3Fu -#define CCM_POST35_POST_PODF_SHIFT 0 -#define CCM_POST35_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST35_POST_PODF_SHIFT))&CCM_POST35_POST_PODF_MASK) -#define CCM_POST35_BUSY1_MASK 0x80u -#define CCM_POST35_BUSY1_SHIFT 7 -#define CCM_POST35_AUTO_PODF_MASK 0x700u -#define CCM_POST35_AUTO_PODF_SHIFT 8 -#define CCM_POST35_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST35_AUTO_PODF_SHIFT))&CCM_POST35_AUTO_PODF_MASK) -#define CCM_POST35_AUTO_EN_MASK 0x1000u -#define CCM_POST35_AUTO_EN_SHIFT 12 -#define CCM_POST35_SLOW_MASK 0x8000u -#define CCM_POST35_SLOW_SHIFT 15 -#define CCM_POST35_SELECT_MASK 0x10000000u -#define CCM_POST35_SELECT_SHIFT 28 -#define CCM_POST35_BUSY2_MASK 0x80000000u -#define CCM_POST35_BUSY2_SHIFT 31 -/* POST_ROOT35_SET Bit Fields */ -#define CCM_POST_ROOT35_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT35_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT35_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_SET_POST_PODF_SHIFT))&CCM_POST_ROOT35_SET_POST_PODF_MASK) -#define CCM_POST_ROOT35_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT35_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT35_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT35_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT35_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT35_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT35_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT35_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT35_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT35_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT35_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT35_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT35_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT35_SET_BUSY2_SHIFT 31 -/* POST_ROOT35_CLR Bit Fields */ -#define CCM_POST_ROOT35_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT35_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT35_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT35_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT35_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT35_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT35_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT35_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT35_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT35_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT35_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT35_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT35_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT35_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT35_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT35_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT35_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT35_CLR_BUSY2_SHIFT 31 -/* POST_ROOT35_TOG Bit Fields */ -#define CCM_POST_ROOT35_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT35_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT35_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT35_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT35_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT35_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT35_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT35_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT35_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT35_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT35_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT35_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT35_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT35_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT35_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT35_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT35_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT35_TOG_BUSY2_SHIFT 31 -/* PRE35 Bit Fields */ -#define CCM_PRE35_PRE_PODF_B_MASK 0x7u -#define CCM_PRE35_PRE_PODF_B_SHIFT 0 -#define CCM_PRE35_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE35_PRE_PODF_B_SHIFT))&CCM_PRE35_PRE_PODF_B_MASK) -#define CCM_PRE35_BUSY0_MASK 0x8u -#define CCM_PRE35_BUSY0_SHIFT 3 -#define CCM_PRE35_MUX_B_MASK 0x700u -#define CCM_PRE35_MUX_B_SHIFT 8 -#define CCM_PRE35_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE35_MUX_B_SHIFT))&CCM_PRE35_MUX_B_MASK) -#define CCM_PRE35_EN_B_MASK 0x1000u -#define CCM_PRE35_EN_B_SHIFT 12 -#define CCM_PRE35_BUSY1_MASK 0x8000u -#define CCM_PRE35_BUSY1_SHIFT 15 -#define CCM_PRE35_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE35_PRE_PODF_A_SHIFT 16 -#define CCM_PRE35_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE35_PRE_PODF_A_SHIFT))&CCM_PRE35_PRE_PODF_A_MASK) -#define CCM_PRE35_BUSY3_MASK 0x80000u -#define CCM_PRE35_BUSY3_SHIFT 19 -#define CCM_PRE35_MUX_A_MASK 0x7000000u -#define CCM_PRE35_MUX_A_SHIFT 24 -#define CCM_PRE35_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE35_MUX_A_SHIFT))&CCM_PRE35_MUX_A_MASK) -#define CCM_PRE35_EN_A_MASK 0x10000000u -#define CCM_PRE35_EN_A_SHIFT 28 -#define CCM_PRE35_BUSY4_MASK 0x80000000u -#define CCM_PRE35_BUSY4_SHIFT 31 -/* PRE_ROOT35_SET Bit Fields */ -#define CCM_PRE_ROOT35_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT35_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT35_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT35_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT35_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT35_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT35_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT35_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT35_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_SET_MUX_B_SHIFT))&CCM_PRE_ROOT35_SET_MUX_B_MASK) -#define CCM_PRE_ROOT35_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT35_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT35_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT35_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT35_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT35_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT35_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT35_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT35_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT35_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT35_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT35_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT35_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_SET_MUX_A_SHIFT))&CCM_PRE_ROOT35_SET_MUX_A_MASK) -#define CCM_PRE_ROOT35_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT35_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT35_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT35_SET_BUSY4_SHIFT 31 -/* PRE_ROOT35_CLR Bit Fields */ -#define CCM_PRE_ROOT35_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT35_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT35_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT35_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT35_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT35_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT35_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT35_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT35_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT35_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT35_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT35_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT35_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT35_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT35_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT35_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT35_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT35_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT35_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT35_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT35_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT35_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT35_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT35_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT35_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT35_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT35_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT35_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT35_TOG Bit Fields */ -#define CCM_PRE_ROOT35_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT35_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT35_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT35_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT35_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT35_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT35_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT35_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT35_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT35_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT35_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT35_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT35_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT35_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT35_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT35_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT35_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT35_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT35_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT35_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT35_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT35_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT35_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT35_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT35_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT35_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT35_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT35_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL35 Bit Fields */ -#define CCM_ACCESS_CTRL35_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL35_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL35_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL35_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL35_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL35_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL35_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL35_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL35_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL35_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL35_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL35_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL35_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL35_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL35_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL35_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL35_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL35_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL35_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL35_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL35_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL35_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL35_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL35_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL35_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL35_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL35_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL35_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL35_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL35_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL35_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL35_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL35_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL35_LOCK_SHIFT 31 -/* ACCESS_CTRL35_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL35_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL35_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL35_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL35_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL35_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL35_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL35_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL35_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL35_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL35_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL35_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL35_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL35_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL35_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL35_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL35_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT36 Bit Fields */ -#define CCM_TARGET_ROOT36_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT36_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT36_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_POST_PODF_SHIFT))&CCM_TARGET_ROOT36_POST_PODF_MASK) -#define CCM_TARGET_ROOT36_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT36_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT36_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT36_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT36_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT36_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT36_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT36_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT36_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT36_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT36_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_PRE_PODF_SHIFT))&CCM_TARGET_ROOT36_PRE_PODF_MASK) -#define CCM_TARGET_ROOT36_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT36_MUX_SHIFT 24 -#define CCM_TARGET_ROOT36_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_MUX_SHIFT))&CCM_TARGET_ROOT36_MUX_MASK) -#define CCM_TARGET_ROOT36_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT36_ENABLE_SHIFT 28 -/* TARGET_ROOT36_SET Bit Fields */ -#define CCM_TARGET_ROOT36_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT36_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT36_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT36_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT36_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT36_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT36_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT36_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT36_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT36_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT36_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT36_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT36_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT36_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT36_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT36_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT36_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT36_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT36_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_SET_MUX_SHIFT))&CCM_TARGET_ROOT36_SET_MUX_MASK) -#define CCM_TARGET_ROOT36_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT36_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT36_CLR Bit Fields */ -#define CCM_TARGET_ROOT36_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT36_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT36_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT36_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT36_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT36_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT36_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT36_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT36_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT36_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT36_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT36_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT36_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT36_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT36_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT36_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT36_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT36_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT36_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_CLR_MUX_SHIFT))&CCM_TARGET_ROOT36_CLR_MUX_MASK) -#define CCM_TARGET_ROOT36_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT36_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT36_TOG Bit Fields */ -#define CCM_TARGET_ROOT36_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT36_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT36_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT36_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT36_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT36_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT36_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT36_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT36_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT36_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT36_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT36_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT36_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT36_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT36_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT36_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT36_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT36_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT36_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_TOG_MUX_SHIFT))&CCM_TARGET_ROOT36_TOG_MUX_MASK) -#define CCM_TARGET_ROOT36_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT36_TOG_ENABLE_SHIFT 28 -/* POST36 Bit Fields */ -#define CCM_POST36_POST_PODF_MASK 0x3Fu -#define CCM_POST36_POST_PODF_SHIFT 0 -#define CCM_POST36_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST36_POST_PODF_SHIFT))&CCM_POST36_POST_PODF_MASK) -#define CCM_POST36_BUSY1_MASK 0x80u -#define CCM_POST36_BUSY1_SHIFT 7 -#define CCM_POST36_AUTO_PODF_MASK 0x700u -#define CCM_POST36_AUTO_PODF_SHIFT 8 -#define CCM_POST36_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST36_AUTO_PODF_SHIFT))&CCM_POST36_AUTO_PODF_MASK) -#define CCM_POST36_AUTO_EN_MASK 0x1000u -#define CCM_POST36_AUTO_EN_SHIFT 12 -#define CCM_POST36_SLOW_MASK 0x8000u -#define CCM_POST36_SLOW_SHIFT 15 -#define CCM_POST36_SELECT_MASK 0x10000000u -#define CCM_POST36_SELECT_SHIFT 28 -#define CCM_POST36_BUSY2_MASK 0x80000000u -#define CCM_POST36_BUSY2_SHIFT 31 -/* POST_ROOT36_SET Bit Fields */ -#define CCM_POST_ROOT36_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT36_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT36_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_SET_POST_PODF_SHIFT))&CCM_POST_ROOT36_SET_POST_PODF_MASK) -#define CCM_POST_ROOT36_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT36_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT36_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT36_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT36_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT36_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT36_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT36_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT36_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT36_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT36_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT36_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT36_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT36_SET_BUSY2_SHIFT 31 -/* POST_ROOT36_CLR Bit Fields */ -#define CCM_POST_ROOT36_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT36_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT36_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT36_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT36_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT36_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT36_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT36_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT36_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT36_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT36_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT36_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT36_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT36_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT36_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT36_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT36_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT36_CLR_BUSY2_SHIFT 31 -/* POST_ROOT36_TOG Bit Fields */ -#define CCM_POST_ROOT36_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT36_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT36_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT36_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT36_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT36_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT36_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT36_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT36_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT36_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT36_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT36_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT36_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT36_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT36_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT36_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT36_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT36_TOG_BUSY2_SHIFT 31 -/* PRE36 Bit Fields */ -#define CCM_PRE36_PRE_PODF_B_MASK 0x7u -#define CCM_PRE36_PRE_PODF_B_SHIFT 0 -#define CCM_PRE36_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE36_PRE_PODF_B_SHIFT))&CCM_PRE36_PRE_PODF_B_MASK) -#define CCM_PRE36_BUSY0_MASK 0x8u -#define CCM_PRE36_BUSY0_SHIFT 3 -#define CCM_PRE36_MUX_B_MASK 0x700u -#define CCM_PRE36_MUX_B_SHIFT 8 -#define CCM_PRE36_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE36_MUX_B_SHIFT))&CCM_PRE36_MUX_B_MASK) -#define CCM_PRE36_EN_B_MASK 0x1000u -#define CCM_PRE36_EN_B_SHIFT 12 -#define CCM_PRE36_BUSY1_MASK 0x8000u -#define CCM_PRE36_BUSY1_SHIFT 15 -#define CCM_PRE36_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE36_PRE_PODF_A_SHIFT 16 -#define CCM_PRE36_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE36_PRE_PODF_A_SHIFT))&CCM_PRE36_PRE_PODF_A_MASK) -#define CCM_PRE36_BUSY3_MASK 0x80000u -#define CCM_PRE36_BUSY3_SHIFT 19 -#define CCM_PRE36_MUX_A_MASK 0x7000000u -#define CCM_PRE36_MUX_A_SHIFT 24 -#define CCM_PRE36_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE36_MUX_A_SHIFT))&CCM_PRE36_MUX_A_MASK) -#define CCM_PRE36_EN_A_MASK 0x10000000u -#define CCM_PRE36_EN_A_SHIFT 28 -#define CCM_PRE36_BUSY4_MASK 0x80000000u -#define CCM_PRE36_BUSY4_SHIFT 31 -/* PRE_ROOT36_SET Bit Fields */ -#define CCM_PRE_ROOT36_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT36_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT36_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT36_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT36_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT36_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT36_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT36_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT36_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_SET_MUX_B_SHIFT))&CCM_PRE_ROOT36_SET_MUX_B_MASK) -#define CCM_PRE_ROOT36_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT36_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT36_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT36_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT36_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT36_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT36_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT36_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT36_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT36_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT36_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT36_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT36_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_SET_MUX_A_SHIFT))&CCM_PRE_ROOT36_SET_MUX_A_MASK) -#define CCM_PRE_ROOT36_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT36_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT36_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT36_SET_BUSY4_SHIFT 31 -/* PRE_ROOT36_CLR Bit Fields */ -#define CCM_PRE_ROOT36_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT36_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT36_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT36_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT36_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT36_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT36_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT36_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT36_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT36_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT36_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT36_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT36_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT36_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT36_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT36_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT36_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT36_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT36_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT36_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT36_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT36_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT36_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT36_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT36_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT36_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT36_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT36_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT36_TOG Bit Fields */ -#define CCM_PRE_ROOT36_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT36_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT36_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT36_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT36_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT36_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT36_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT36_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT36_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT36_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT36_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT36_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT36_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT36_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT36_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT36_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT36_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT36_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT36_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT36_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT36_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT36_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT36_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT36_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT36_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT36_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT36_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT36_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL36 Bit Fields */ -#define CCM_ACCESS_CTRL36_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL36_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL36_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL36_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL36_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL36_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL36_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL36_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL36_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL36_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL36_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL36_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL36_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL36_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL36_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL36_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL36_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL36_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL36_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL36_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL36_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL36_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL36_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL36_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL36_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL36_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL36_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL36_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL36_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL36_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL36_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL36_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL36_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL36_LOCK_SHIFT 31 -/* ACCESS_CTRL36_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL36_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL36_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL36_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL36_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL36_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL36_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL36_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL36_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL36_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL36_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL36_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL36_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL36_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL36_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL36_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL36_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT37 Bit Fields */ -#define CCM_TARGET_ROOT37_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT37_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT37_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_POST_PODF_SHIFT))&CCM_TARGET_ROOT37_POST_PODF_MASK) -#define CCM_TARGET_ROOT37_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT37_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT37_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT37_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT37_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT37_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT37_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT37_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT37_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT37_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT37_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_PRE_PODF_SHIFT))&CCM_TARGET_ROOT37_PRE_PODF_MASK) -#define CCM_TARGET_ROOT37_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT37_MUX_SHIFT 24 -#define CCM_TARGET_ROOT37_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_MUX_SHIFT))&CCM_TARGET_ROOT37_MUX_MASK) -#define CCM_TARGET_ROOT37_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT37_ENABLE_SHIFT 28 -/* TARGET_ROOT37_SET Bit Fields */ -#define CCM_TARGET_ROOT37_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT37_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT37_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT37_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT37_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT37_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT37_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT37_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT37_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT37_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT37_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT37_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT37_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT37_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT37_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT37_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT37_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT37_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT37_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_SET_MUX_SHIFT))&CCM_TARGET_ROOT37_SET_MUX_MASK) -#define CCM_TARGET_ROOT37_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT37_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT37_CLR Bit Fields */ -#define CCM_TARGET_ROOT37_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT37_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT37_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT37_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT37_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT37_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT37_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT37_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT37_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT37_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT37_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT37_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT37_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT37_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT37_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT37_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT37_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT37_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT37_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_CLR_MUX_SHIFT))&CCM_TARGET_ROOT37_CLR_MUX_MASK) -#define CCM_TARGET_ROOT37_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT37_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT37_TOG Bit Fields */ -#define CCM_TARGET_ROOT37_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT37_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT37_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT37_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT37_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT37_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT37_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT37_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT37_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT37_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT37_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT37_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT37_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT37_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT37_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT37_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT37_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT37_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT37_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_TOG_MUX_SHIFT))&CCM_TARGET_ROOT37_TOG_MUX_MASK) -#define CCM_TARGET_ROOT37_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT37_TOG_ENABLE_SHIFT 28 -/* POST37 Bit Fields */ -#define CCM_POST37_POST_PODF_MASK 0x3Fu -#define CCM_POST37_POST_PODF_SHIFT 0 -#define CCM_POST37_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST37_POST_PODF_SHIFT))&CCM_POST37_POST_PODF_MASK) -#define CCM_POST37_BUSY1_MASK 0x80u -#define CCM_POST37_BUSY1_SHIFT 7 -#define CCM_POST37_AUTO_PODF_MASK 0x700u -#define CCM_POST37_AUTO_PODF_SHIFT 8 -#define CCM_POST37_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST37_AUTO_PODF_SHIFT))&CCM_POST37_AUTO_PODF_MASK) -#define CCM_POST37_AUTO_EN_MASK 0x1000u -#define CCM_POST37_AUTO_EN_SHIFT 12 -#define CCM_POST37_SLOW_MASK 0x8000u -#define CCM_POST37_SLOW_SHIFT 15 -#define CCM_POST37_SELECT_MASK 0x10000000u -#define CCM_POST37_SELECT_SHIFT 28 -#define CCM_POST37_BUSY2_MASK 0x80000000u -#define CCM_POST37_BUSY2_SHIFT 31 -/* POST_ROOT37_SET Bit Fields */ -#define CCM_POST_ROOT37_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT37_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT37_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_SET_POST_PODF_SHIFT))&CCM_POST_ROOT37_SET_POST_PODF_MASK) -#define CCM_POST_ROOT37_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT37_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT37_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT37_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT37_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT37_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT37_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT37_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT37_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT37_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT37_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT37_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT37_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT37_SET_BUSY2_SHIFT 31 -/* POST_ROOT37_CLR Bit Fields */ -#define CCM_POST_ROOT37_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT37_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT37_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT37_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT37_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT37_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT37_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT37_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT37_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT37_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT37_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT37_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT37_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT37_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT37_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT37_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT37_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT37_CLR_BUSY2_SHIFT 31 -/* POST_ROOT37_TOG Bit Fields */ -#define CCM_POST_ROOT37_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT37_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT37_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT37_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT37_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT37_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT37_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT37_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT37_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT37_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT37_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT37_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT37_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT37_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT37_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT37_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT37_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT37_TOG_BUSY2_SHIFT 31 -/* PRE37 Bit Fields */ -#define CCM_PRE37_PRE_PODF_B_MASK 0x7u -#define CCM_PRE37_PRE_PODF_B_SHIFT 0 -#define CCM_PRE37_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE37_PRE_PODF_B_SHIFT))&CCM_PRE37_PRE_PODF_B_MASK) -#define CCM_PRE37_BUSY0_MASK 0x8u -#define CCM_PRE37_BUSY0_SHIFT 3 -#define CCM_PRE37_MUX_B_MASK 0x700u -#define CCM_PRE37_MUX_B_SHIFT 8 -#define CCM_PRE37_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE37_MUX_B_SHIFT))&CCM_PRE37_MUX_B_MASK) -#define CCM_PRE37_EN_B_MASK 0x1000u -#define CCM_PRE37_EN_B_SHIFT 12 -#define CCM_PRE37_BUSY1_MASK 0x8000u -#define CCM_PRE37_BUSY1_SHIFT 15 -#define CCM_PRE37_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE37_PRE_PODF_A_SHIFT 16 -#define CCM_PRE37_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE37_PRE_PODF_A_SHIFT))&CCM_PRE37_PRE_PODF_A_MASK) -#define CCM_PRE37_BUSY3_MASK 0x80000u -#define CCM_PRE37_BUSY3_SHIFT 19 -#define CCM_PRE37_MUX_A_MASK 0x7000000u -#define CCM_PRE37_MUX_A_SHIFT 24 -#define CCM_PRE37_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE37_MUX_A_SHIFT))&CCM_PRE37_MUX_A_MASK) -#define CCM_PRE37_EN_A_MASK 0x10000000u -#define CCM_PRE37_EN_A_SHIFT 28 -#define CCM_PRE37_BUSY4_MASK 0x80000000u -#define CCM_PRE37_BUSY4_SHIFT 31 -/* PRE_ROOT37_SET Bit Fields */ -#define CCM_PRE_ROOT37_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT37_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT37_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT37_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT37_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT37_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT37_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT37_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT37_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_SET_MUX_B_SHIFT))&CCM_PRE_ROOT37_SET_MUX_B_MASK) -#define CCM_PRE_ROOT37_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT37_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT37_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT37_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT37_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT37_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT37_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT37_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT37_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT37_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT37_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT37_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT37_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_SET_MUX_A_SHIFT))&CCM_PRE_ROOT37_SET_MUX_A_MASK) -#define CCM_PRE_ROOT37_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT37_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT37_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT37_SET_BUSY4_SHIFT 31 -/* PRE_ROOT37_CLR Bit Fields */ -#define CCM_PRE_ROOT37_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT37_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT37_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT37_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT37_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT37_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT37_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT37_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT37_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT37_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT37_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT37_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT37_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT37_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT37_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT37_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT37_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT37_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT37_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT37_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT37_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT37_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT37_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT37_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT37_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT37_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT37_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT37_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT37_TOG Bit Fields */ -#define CCM_PRE_ROOT37_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT37_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT37_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT37_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT37_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT37_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT37_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT37_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT37_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT37_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT37_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT37_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT37_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT37_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT37_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT37_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT37_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT37_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT37_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT37_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT37_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT37_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT37_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT37_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT37_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT37_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT37_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT37_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL37 Bit Fields */ -#define CCM_ACCESS_CTRL37_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL37_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL37_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL37_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL37_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL37_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL37_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL37_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL37_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL37_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL37_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL37_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL37_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL37_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL37_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL37_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL37_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL37_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL37_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL37_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL37_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL37_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL37_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL37_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL37_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL37_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL37_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL37_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL37_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL37_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL37_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL37_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL37_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL37_LOCK_SHIFT 31 -/* ACCESS_CTRL37_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL37_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL37_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL37_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL37_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL37_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL37_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL37_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL37_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL37_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL37_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL37_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL37_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL37_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL37_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL37_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL37_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT38 Bit Fields */ -#define CCM_TARGET_ROOT38_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT38_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT38_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_POST_PODF_SHIFT))&CCM_TARGET_ROOT38_POST_PODF_MASK) -#define CCM_TARGET_ROOT38_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT38_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT38_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT38_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT38_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT38_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT38_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT38_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT38_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT38_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT38_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_PRE_PODF_SHIFT))&CCM_TARGET_ROOT38_PRE_PODF_MASK) -#define CCM_TARGET_ROOT38_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT38_MUX_SHIFT 24 -#define CCM_TARGET_ROOT38_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_MUX_SHIFT))&CCM_TARGET_ROOT38_MUX_MASK) -#define CCM_TARGET_ROOT38_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT38_ENABLE_SHIFT 28 -/* TARGET_ROOT38_SET Bit Fields */ -#define CCM_TARGET_ROOT38_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT38_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT38_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT38_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT38_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT38_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT38_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT38_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT38_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT38_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT38_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT38_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT38_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT38_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT38_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT38_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT38_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT38_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT38_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_SET_MUX_SHIFT))&CCM_TARGET_ROOT38_SET_MUX_MASK) -#define CCM_TARGET_ROOT38_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT38_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT38_CLR Bit Fields */ -#define CCM_TARGET_ROOT38_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT38_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT38_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT38_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT38_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT38_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT38_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT38_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT38_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT38_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT38_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT38_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT38_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT38_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT38_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT38_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT38_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT38_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT38_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_CLR_MUX_SHIFT))&CCM_TARGET_ROOT38_CLR_MUX_MASK) -#define CCM_TARGET_ROOT38_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT38_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT38_TOG Bit Fields */ -#define CCM_TARGET_ROOT38_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT38_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT38_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT38_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT38_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT38_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT38_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT38_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT38_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT38_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT38_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT38_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT38_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT38_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT38_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT38_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT38_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT38_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT38_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_TOG_MUX_SHIFT))&CCM_TARGET_ROOT38_TOG_MUX_MASK) -#define CCM_TARGET_ROOT38_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT38_TOG_ENABLE_SHIFT 28 -/* POST38 Bit Fields */ -#define CCM_POST38_POST_PODF_MASK 0x3Fu -#define CCM_POST38_POST_PODF_SHIFT 0 -#define CCM_POST38_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST38_POST_PODF_SHIFT))&CCM_POST38_POST_PODF_MASK) -#define CCM_POST38_BUSY1_MASK 0x80u -#define CCM_POST38_BUSY1_SHIFT 7 -#define CCM_POST38_AUTO_PODF_MASK 0x700u -#define CCM_POST38_AUTO_PODF_SHIFT 8 -#define CCM_POST38_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST38_AUTO_PODF_SHIFT))&CCM_POST38_AUTO_PODF_MASK) -#define CCM_POST38_AUTO_EN_MASK 0x1000u -#define CCM_POST38_AUTO_EN_SHIFT 12 -#define CCM_POST38_SLOW_MASK 0x8000u -#define CCM_POST38_SLOW_SHIFT 15 -#define CCM_POST38_SELECT_MASK 0x10000000u -#define CCM_POST38_SELECT_SHIFT 28 -#define CCM_POST38_BUSY2_MASK 0x80000000u -#define CCM_POST38_BUSY2_SHIFT 31 -/* POST_ROOT38_SET Bit Fields */ -#define CCM_POST_ROOT38_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT38_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT38_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_SET_POST_PODF_SHIFT))&CCM_POST_ROOT38_SET_POST_PODF_MASK) -#define CCM_POST_ROOT38_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT38_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT38_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT38_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT38_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT38_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT38_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT38_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT38_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT38_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT38_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT38_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT38_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT38_SET_BUSY2_SHIFT 31 -/* POST_ROOT38_CLR Bit Fields */ -#define CCM_POST_ROOT38_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT38_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT38_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT38_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT38_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT38_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT38_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT38_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT38_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT38_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT38_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT38_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT38_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT38_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT38_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT38_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT38_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT38_CLR_BUSY2_SHIFT 31 -/* POST_ROOT38_TOG Bit Fields */ -#define CCM_POST_ROOT38_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT38_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT38_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT38_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT38_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT38_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT38_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT38_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT38_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT38_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT38_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT38_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT38_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT38_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT38_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT38_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT38_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT38_TOG_BUSY2_SHIFT 31 -/* PRE38 Bit Fields */ -#define CCM_PRE38_PRE_PODF_B_MASK 0x7u -#define CCM_PRE38_PRE_PODF_B_SHIFT 0 -#define CCM_PRE38_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE38_PRE_PODF_B_SHIFT))&CCM_PRE38_PRE_PODF_B_MASK) -#define CCM_PRE38_BUSY0_MASK 0x8u -#define CCM_PRE38_BUSY0_SHIFT 3 -#define CCM_PRE38_MUX_B_MASK 0x700u -#define CCM_PRE38_MUX_B_SHIFT 8 -#define CCM_PRE38_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE38_MUX_B_SHIFT))&CCM_PRE38_MUX_B_MASK) -#define CCM_PRE38_EN_B_MASK 0x1000u -#define CCM_PRE38_EN_B_SHIFT 12 -#define CCM_PRE38_BUSY1_MASK 0x8000u -#define CCM_PRE38_BUSY1_SHIFT 15 -#define CCM_PRE38_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE38_PRE_PODF_A_SHIFT 16 -#define CCM_PRE38_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE38_PRE_PODF_A_SHIFT))&CCM_PRE38_PRE_PODF_A_MASK) -#define CCM_PRE38_BUSY3_MASK 0x80000u -#define CCM_PRE38_BUSY3_SHIFT 19 -#define CCM_PRE38_MUX_A_MASK 0x7000000u -#define CCM_PRE38_MUX_A_SHIFT 24 -#define CCM_PRE38_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE38_MUX_A_SHIFT))&CCM_PRE38_MUX_A_MASK) -#define CCM_PRE38_EN_A_MASK 0x10000000u -#define CCM_PRE38_EN_A_SHIFT 28 -#define CCM_PRE38_BUSY4_MASK 0x80000000u -#define CCM_PRE38_BUSY4_SHIFT 31 -/* PRE_ROOT38_SET Bit Fields */ -#define CCM_PRE_ROOT38_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT38_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT38_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT38_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT38_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT38_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT38_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT38_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT38_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_SET_MUX_B_SHIFT))&CCM_PRE_ROOT38_SET_MUX_B_MASK) -#define CCM_PRE_ROOT38_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT38_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT38_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT38_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT38_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT38_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT38_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT38_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT38_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT38_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT38_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT38_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT38_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_SET_MUX_A_SHIFT))&CCM_PRE_ROOT38_SET_MUX_A_MASK) -#define CCM_PRE_ROOT38_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT38_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT38_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT38_SET_BUSY4_SHIFT 31 -/* PRE_ROOT38_CLR Bit Fields */ -#define CCM_PRE_ROOT38_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT38_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT38_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT38_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT38_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT38_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT38_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT38_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT38_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT38_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT38_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT38_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT38_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT38_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT38_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT38_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT38_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT38_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT38_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT38_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT38_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT38_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT38_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT38_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT38_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT38_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT38_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT38_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT38_TOG Bit Fields */ -#define CCM_PRE_ROOT38_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT38_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT38_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT38_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT38_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT38_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT38_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT38_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT38_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT38_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT38_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT38_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT38_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT38_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT38_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT38_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT38_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT38_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT38_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT38_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT38_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT38_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT38_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT38_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT38_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT38_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT38_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT38_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL38 Bit Fields */ -#define CCM_ACCESS_CTRL38_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL38_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL38_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL38_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL38_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL38_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL38_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL38_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL38_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL38_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL38_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL38_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL38_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL38_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL38_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL38_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL38_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL38_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL38_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL38_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL38_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL38_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL38_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL38_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL38_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL38_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL38_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL38_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL38_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL38_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL38_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL38_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL38_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL38_LOCK_SHIFT 31 -/* ACCESS_CTRL38_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL38_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL38_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL38_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL38_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL38_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL38_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL38_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL38_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL38_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL38_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL38_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL38_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL38_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL38_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL38_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL38_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT39 Bit Fields */ -#define CCM_TARGET_ROOT39_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT39_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT39_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_POST_PODF_SHIFT))&CCM_TARGET_ROOT39_POST_PODF_MASK) -#define CCM_TARGET_ROOT39_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT39_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT39_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT39_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT39_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT39_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT39_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT39_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT39_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT39_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT39_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_PRE_PODF_SHIFT))&CCM_TARGET_ROOT39_PRE_PODF_MASK) -#define CCM_TARGET_ROOT39_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT39_MUX_SHIFT 24 -#define CCM_TARGET_ROOT39_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_MUX_SHIFT))&CCM_TARGET_ROOT39_MUX_MASK) -#define CCM_TARGET_ROOT39_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT39_ENABLE_SHIFT 28 -/* TARGET_ROOT39_SET Bit Fields */ -#define CCM_TARGET_ROOT39_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT39_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT39_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT39_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT39_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT39_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT39_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT39_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT39_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT39_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT39_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT39_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT39_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT39_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT39_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT39_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT39_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT39_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT39_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_SET_MUX_SHIFT))&CCM_TARGET_ROOT39_SET_MUX_MASK) -#define CCM_TARGET_ROOT39_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT39_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT39_CLR Bit Fields */ -#define CCM_TARGET_ROOT39_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT39_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT39_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT39_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT39_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT39_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT39_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT39_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT39_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT39_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT39_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT39_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT39_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT39_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT39_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT39_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT39_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT39_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT39_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_CLR_MUX_SHIFT))&CCM_TARGET_ROOT39_CLR_MUX_MASK) -#define CCM_TARGET_ROOT39_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT39_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT39_TOG Bit Fields */ -#define CCM_TARGET_ROOT39_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT39_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT39_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT39_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT39_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT39_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT39_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT39_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT39_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT39_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT39_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT39_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT39_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT39_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT39_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT39_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT39_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT39_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT39_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_TOG_MUX_SHIFT))&CCM_TARGET_ROOT39_TOG_MUX_MASK) -#define CCM_TARGET_ROOT39_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT39_TOG_ENABLE_SHIFT 28 -/* POST39 Bit Fields */ -#define CCM_POST39_POST_PODF_MASK 0x3Fu -#define CCM_POST39_POST_PODF_SHIFT 0 -#define CCM_POST39_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST39_POST_PODF_SHIFT))&CCM_POST39_POST_PODF_MASK) -#define CCM_POST39_BUSY1_MASK 0x80u -#define CCM_POST39_BUSY1_SHIFT 7 -#define CCM_POST39_AUTO_PODF_MASK 0x700u -#define CCM_POST39_AUTO_PODF_SHIFT 8 -#define CCM_POST39_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST39_AUTO_PODF_SHIFT))&CCM_POST39_AUTO_PODF_MASK) -#define CCM_POST39_AUTO_EN_MASK 0x1000u -#define CCM_POST39_AUTO_EN_SHIFT 12 -#define CCM_POST39_SLOW_MASK 0x8000u -#define CCM_POST39_SLOW_SHIFT 15 -#define CCM_POST39_SELECT_MASK 0x10000000u -#define CCM_POST39_SELECT_SHIFT 28 -#define CCM_POST39_BUSY2_MASK 0x80000000u -#define CCM_POST39_BUSY2_SHIFT 31 -/* POST_ROOT39_SET Bit Fields */ -#define CCM_POST_ROOT39_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT39_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT39_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_SET_POST_PODF_SHIFT))&CCM_POST_ROOT39_SET_POST_PODF_MASK) -#define CCM_POST_ROOT39_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT39_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT39_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT39_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT39_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT39_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT39_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT39_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT39_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT39_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT39_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT39_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT39_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT39_SET_BUSY2_SHIFT 31 -/* POST_ROOT39_CLR Bit Fields */ -#define CCM_POST_ROOT39_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT39_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT39_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT39_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT39_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT39_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT39_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT39_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT39_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT39_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT39_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT39_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT39_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT39_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT39_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT39_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT39_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT39_CLR_BUSY2_SHIFT 31 -/* POST_ROOT39_TOG Bit Fields */ -#define CCM_POST_ROOT39_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT39_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT39_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT39_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT39_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT39_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT39_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT39_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT39_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT39_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT39_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT39_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT39_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT39_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT39_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT39_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT39_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT39_TOG_BUSY2_SHIFT 31 -/* PRE39 Bit Fields */ -#define CCM_PRE39_PRE_PODF_B_MASK 0x7u -#define CCM_PRE39_PRE_PODF_B_SHIFT 0 -#define CCM_PRE39_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE39_PRE_PODF_B_SHIFT))&CCM_PRE39_PRE_PODF_B_MASK) -#define CCM_PRE39_BUSY0_MASK 0x8u -#define CCM_PRE39_BUSY0_SHIFT 3 -#define CCM_PRE39_MUX_B_MASK 0x700u -#define CCM_PRE39_MUX_B_SHIFT 8 -#define CCM_PRE39_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE39_MUX_B_SHIFT))&CCM_PRE39_MUX_B_MASK) -#define CCM_PRE39_EN_B_MASK 0x1000u -#define CCM_PRE39_EN_B_SHIFT 12 -#define CCM_PRE39_BUSY1_MASK 0x8000u -#define CCM_PRE39_BUSY1_SHIFT 15 -#define CCM_PRE39_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE39_PRE_PODF_A_SHIFT 16 -#define CCM_PRE39_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE39_PRE_PODF_A_SHIFT))&CCM_PRE39_PRE_PODF_A_MASK) -#define CCM_PRE39_BUSY3_MASK 0x80000u -#define CCM_PRE39_BUSY3_SHIFT 19 -#define CCM_PRE39_MUX_A_MASK 0x7000000u -#define CCM_PRE39_MUX_A_SHIFT 24 -#define CCM_PRE39_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE39_MUX_A_SHIFT))&CCM_PRE39_MUX_A_MASK) -#define CCM_PRE39_EN_A_MASK 0x10000000u -#define CCM_PRE39_EN_A_SHIFT 28 -#define CCM_PRE39_BUSY4_MASK 0x80000000u -#define CCM_PRE39_BUSY4_SHIFT 31 -/* PRE_ROOT39_SET Bit Fields */ -#define CCM_PRE_ROOT39_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT39_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT39_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT39_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT39_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT39_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT39_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT39_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT39_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_SET_MUX_B_SHIFT))&CCM_PRE_ROOT39_SET_MUX_B_MASK) -#define CCM_PRE_ROOT39_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT39_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT39_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT39_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT39_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT39_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT39_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT39_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT39_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT39_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT39_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT39_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT39_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_SET_MUX_A_SHIFT))&CCM_PRE_ROOT39_SET_MUX_A_MASK) -#define CCM_PRE_ROOT39_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT39_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT39_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT39_SET_BUSY4_SHIFT 31 -/* PRE_ROOT39_CLR Bit Fields */ -#define CCM_PRE_ROOT39_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT39_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT39_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT39_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT39_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT39_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT39_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT39_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT39_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT39_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT39_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT39_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT39_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT39_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT39_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT39_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT39_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT39_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT39_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT39_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT39_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT39_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT39_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT39_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT39_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT39_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT39_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT39_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT39_TOG Bit Fields */ -#define CCM_PRE_ROOT39_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT39_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT39_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT39_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT39_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT39_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT39_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT39_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT39_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT39_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT39_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT39_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT39_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT39_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT39_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT39_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT39_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT39_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT39_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT39_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT39_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT39_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT39_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT39_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT39_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT39_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT39_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT39_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL39 Bit Fields */ -#define CCM_ACCESS_CTRL39_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL39_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL39_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL39_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL39_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL39_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL39_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL39_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL39_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL39_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL39_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL39_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL39_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL39_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL39_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL39_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL39_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL39_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL39_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL39_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL39_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL39_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL39_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL39_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL39_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL39_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL39_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL39_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL39_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL39_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL39_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL39_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL39_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL39_LOCK_SHIFT 31 -/* ACCESS_CTRL39_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL39_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL39_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL39_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL39_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL39_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL39_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL39_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL39_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL39_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL39_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL39_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL39_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL39_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL39_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL39_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL39_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT40 Bit Fields */ -#define CCM_TARGET_ROOT40_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT40_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT40_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_POST_PODF_SHIFT))&CCM_TARGET_ROOT40_POST_PODF_MASK) -#define CCM_TARGET_ROOT40_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT40_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT40_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT40_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT40_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT40_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT40_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT40_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT40_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT40_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT40_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_PRE_PODF_SHIFT))&CCM_TARGET_ROOT40_PRE_PODF_MASK) -#define CCM_TARGET_ROOT40_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT40_MUX_SHIFT 24 -#define CCM_TARGET_ROOT40_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_MUX_SHIFT))&CCM_TARGET_ROOT40_MUX_MASK) -#define CCM_TARGET_ROOT40_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT40_ENABLE_SHIFT 28 -/* TARGET_ROOT40_SET Bit Fields */ -#define CCM_TARGET_ROOT40_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT40_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT40_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT40_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT40_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT40_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT40_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT40_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT40_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT40_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT40_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT40_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT40_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT40_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT40_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT40_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT40_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT40_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT40_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_SET_MUX_SHIFT))&CCM_TARGET_ROOT40_SET_MUX_MASK) -#define CCM_TARGET_ROOT40_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT40_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT40_CLR Bit Fields */ -#define CCM_TARGET_ROOT40_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT40_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT40_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT40_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT40_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT40_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT40_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT40_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT40_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT40_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT40_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT40_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT40_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT40_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT40_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT40_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT40_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT40_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT40_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_CLR_MUX_SHIFT))&CCM_TARGET_ROOT40_CLR_MUX_MASK) -#define CCM_TARGET_ROOT40_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT40_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT40_TOG Bit Fields */ -#define CCM_TARGET_ROOT40_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT40_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT40_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT40_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT40_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT40_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT40_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT40_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT40_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT40_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT40_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT40_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT40_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT40_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT40_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT40_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT40_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT40_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT40_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_TOG_MUX_SHIFT))&CCM_TARGET_ROOT40_TOG_MUX_MASK) -#define CCM_TARGET_ROOT40_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT40_TOG_ENABLE_SHIFT 28 -/* POST40 Bit Fields */ -#define CCM_POST40_POST_PODF_MASK 0x3Fu -#define CCM_POST40_POST_PODF_SHIFT 0 -#define CCM_POST40_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST40_POST_PODF_SHIFT))&CCM_POST40_POST_PODF_MASK) -#define CCM_POST40_BUSY1_MASK 0x80u -#define CCM_POST40_BUSY1_SHIFT 7 -#define CCM_POST40_AUTO_PODF_MASK 0x700u -#define CCM_POST40_AUTO_PODF_SHIFT 8 -#define CCM_POST40_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST40_AUTO_PODF_SHIFT))&CCM_POST40_AUTO_PODF_MASK) -#define CCM_POST40_AUTO_EN_MASK 0x1000u -#define CCM_POST40_AUTO_EN_SHIFT 12 -#define CCM_POST40_SLOW_MASK 0x8000u -#define CCM_POST40_SLOW_SHIFT 15 -#define CCM_POST40_SELECT_MASK 0x10000000u -#define CCM_POST40_SELECT_SHIFT 28 -#define CCM_POST40_BUSY2_MASK 0x80000000u -#define CCM_POST40_BUSY2_SHIFT 31 -/* POST_ROOT40_SET Bit Fields */ -#define CCM_POST_ROOT40_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT40_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT40_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_SET_POST_PODF_SHIFT))&CCM_POST_ROOT40_SET_POST_PODF_MASK) -#define CCM_POST_ROOT40_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT40_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT40_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT40_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT40_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT40_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT40_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT40_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT40_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT40_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT40_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT40_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT40_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT40_SET_BUSY2_SHIFT 31 -/* POST_ROOT40_CLR Bit Fields */ -#define CCM_POST_ROOT40_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT40_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT40_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT40_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT40_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT40_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT40_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT40_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT40_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT40_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT40_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT40_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT40_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT40_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT40_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT40_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT40_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT40_CLR_BUSY2_SHIFT 31 -/* POST_ROOT40_TOG Bit Fields */ -#define CCM_POST_ROOT40_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT40_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT40_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT40_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT40_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT40_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT40_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT40_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT40_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT40_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT40_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT40_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT40_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT40_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT40_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT40_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT40_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT40_TOG_BUSY2_SHIFT 31 -/* PRE40 Bit Fields */ -#define CCM_PRE40_PRE_PODF_B_MASK 0x7u -#define CCM_PRE40_PRE_PODF_B_SHIFT 0 -#define CCM_PRE40_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE40_PRE_PODF_B_SHIFT))&CCM_PRE40_PRE_PODF_B_MASK) -#define CCM_PRE40_BUSY0_MASK 0x8u -#define CCM_PRE40_BUSY0_SHIFT 3 -#define CCM_PRE40_MUX_B_MASK 0x700u -#define CCM_PRE40_MUX_B_SHIFT 8 -#define CCM_PRE40_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE40_MUX_B_SHIFT))&CCM_PRE40_MUX_B_MASK) -#define CCM_PRE40_EN_B_MASK 0x1000u -#define CCM_PRE40_EN_B_SHIFT 12 -#define CCM_PRE40_BUSY1_MASK 0x8000u -#define CCM_PRE40_BUSY1_SHIFT 15 -#define CCM_PRE40_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE40_PRE_PODF_A_SHIFT 16 -#define CCM_PRE40_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE40_PRE_PODF_A_SHIFT))&CCM_PRE40_PRE_PODF_A_MASK) -#define CCM_PRE40_BUSY3_MASK 0x80000u -#define CCM_PRE40_BUSY3_SHIFT 19 -#define CCM_PRE40_MUX_A_MASK 0x7000000u -#define CCM_PRE40_MUX_A_SHIFT 24 -#define CCM_PRE40_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE40_MUX_A_SHIFT))&CCM_PRE40_MUX_A_MASK) -#define CCM_PRE40_EN_A_MASK 0x10000000u -#define CCM_PRE40_EN_A_SHIFT 28 -#define CCM_PRE40_BUSY4_MASK 0x80000000u -#define CCM_PRE40_BUSY4_SHIFT 31 -/* PRE_ROOT40_SET Bit Fields */ -#define CCM_PRE_ROOT40_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT40_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT40_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT40_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT40_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT40_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT40_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT40_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT40_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_SET_MUX_B_SHIFT))&CCM_PRE_ROOT40_SET_MUX_B_MASK) -#define CCM_PRE_ROOT40_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT40_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT40_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT40_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT40_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT40_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT40_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT40_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT40_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT40_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT40_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT40_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT40_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_SET_MUX_A_SHIFT))&CCM_PRE_ROOT40_SET_MUX_A_MASK) -#define CCM_PRE_ROOT40_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT40_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT40_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT40_SET_BUSY4_SHIFT 31 -/* PRE_ROOT40_CLR Bit Fields */ -#define CCM_PRE_ROOT40_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT40_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT40_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT40_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT40_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT40_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT40_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT40_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT40_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT40_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT40_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT40_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT40_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT40_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT40_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT40_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT40_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT40_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT40_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT40_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT40_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT40_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT40_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT40_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT40_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT40_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT40_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT40_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT40_TOG Bit Fields */ -#define CCM_PRE_ROOT40_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT40_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT40_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT40_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT40_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT40_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT40_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT40_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT40_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT40_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT40_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT40_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT40_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT40_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT40_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT40_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT40_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT40_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT40_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT40_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT40_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT40_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT40_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT40_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT40_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT40_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT40_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT40_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL40 Bit Fields */ -#define CCM_ACCESS_CTRL40_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL40_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL40_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL40_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL40_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL40_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL40_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL40_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL40_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL40_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL40_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL40_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL40_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL40_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL40_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL40_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL40_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL40_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL40_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL40_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL40_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL40_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL40_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL40_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL40_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL40_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL40_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL40_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL40_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL40_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL40_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL40_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL40_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL40_LOCK_SHIFT 31 -/* ACCESS_CTRL40_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL40_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL40_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL40_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL40_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL40_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL40_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL40_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL40_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL40_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL40_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL40_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL40_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL40_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL40_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL40_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL40_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT41 Bit Fields */ -#define CCM_TARGET_ROOT41_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT41_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT41_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_POST_PODF_SHIFT))&CCM_TARGET_ROOT41_POST_PODF_MASK) -#define CCM_TARGET_ROOT41_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT41_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT41_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT41_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT41_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT41_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT41_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT41_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT41_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT41_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT41_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_PRE_PODF_SHIFT))&CCM_TARGET_ROOT41_PRE_PODF_MASK) -#define CCM_TARGET_ROOT41_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT41_MUX_SHIFT 24 -#define CCM_TARGET_ROOT41_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_MUX_SHIFT))&CCM_TARGET_ROOT41_MUX_MASK) -#define CCM_TARGET_ROOT41_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT41_ENABLE_SHIFT 28 -/* TARGET_ROOT41_SET Bit Fields */ -#define CCM_TARGET_ROOT41_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT41_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT41_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT41_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT41_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT41_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT41_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT41_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT41_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT41_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT41_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT41_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT41_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT41_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT41_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT41_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT41_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT41_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT41_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_SET_MUX_SHIFT))&CCM_TARGET_ROOT41_SET_MUX_MASK) -#define CCM_TARGET_ROOT41_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT41_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT41_CLR Bit Fields */ -#define CCM_TARGET_ROOT41_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT41_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT41_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT41_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT41_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT41_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT41_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT41_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT41_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT41_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT41_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT41_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT41_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT41_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT41_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT41_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT41_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT41_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT41_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_CLR_MUX_SHIFT))&CCM_TARGET_ROOT41_CLR_MUX_MASK) -#define CCM_TARGET_ROOT41_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT41_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT41_TOG Bit Fields */ -#define CCM_TARGET_ROOT41_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT41_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT41_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT41_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT41_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT41_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT41_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT41_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT41_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT41_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT41_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT41_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT41_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT41_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT41_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT41_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT41_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT41_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT41_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_TOG_MUX_SHIFT))&CCM_TARGET_ROOT41_TOG_MUX_MASK) -#define CCM_TARGET_ROOT41_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT41_TOG_ENABLE_SHIFT 28 -/* POST41 Bit Fields */ -#define CCM_POST41_POST_PODF_MASK 0x3Fu -#define CCM_POST41_POST_PODF_SHIFT 0 -#define CCM_POST41_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST41_POST_PODF_SHIFT))&CCM_POST41_POST_PODF_MASK) -#define CCM_POST41_BUSY1_MASK 0x80u -#define CCM_POST41_BUSY1_SHIFT 7 -#define CCM_POST41_AUTO_PODF_MASK 0x700u -#define CCM_POST41_AUTO_PODF_SHIFT 8 -#define CCM_POST41_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST41_AUTO_PODF_SHIFT))&CCM_POST41_AUTO_PODF_MASK) -#define CCM_POST41_AUTO_EN_MASK 0x1000u -#define CCM_POST41_AUTO_EN_SHIFT 12 -#define CCM_POST41_SLOW_MASK 0x8000u -#define CCM_POST41_SLOW_SHIFT 15 -#define CCM_POST41_SELECT_MASK 0x10000000u -#define CCM_POST41_SELECT_SHIFT 28 -#define CCM_POST41_BUSY2_MASK 0x80000000u -#define CCM_POST41_BUSY2_SHIFT 31 -/* POST_ROOT41_SET Bit Fields */ -#define CCM_POST_ROOT41_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT41_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT41_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_SET_POST_PODF_SHIFT))&CCM_POST_ROOT41_SET_POST_PODF_MASK) -#define CCM_POST_ROOT41_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT41_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT41_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT41_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT41_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT41_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT41_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT41_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT41_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT41_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT41_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT41_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT41_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT41_SET_BUSY2_SHIFT 31 -/* POST_ROOT41_CLR Bit Fields */ -#define CCM_POST_ROOT41_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT41_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT41_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT41_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT41_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT41_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT41_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT41_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT41_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT41_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT41_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT41_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT41_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT41_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT41_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT41_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT41_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT41_CLR_BUSY2_SHIFT 31 -/* POST_ROOT41_TOG Bit Fields */ -#define CCM_POST_ROOT41_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT41_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT41_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT41_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT41_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT41_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT41_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT41_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT41_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT41_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT41_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT41_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT41_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT41_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT41_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT41_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT41_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT41_TOG_BUSY2_SHIFT 31 -/* PRE41 Bit Fields */ -#define CCM_PRE41_PRE_PODF_B_MASK 0x7u -#define CCM_PRE41_PRE_PODF_B_SHIFT 0 -#define CCM_PRE41_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE41_PRE_PODF_B_SHIFT))&CCM_PRE41_PRE_PODF_B_MASK) -#define CCM_PRE41_BUSY0_MASK 0x8u -#define CCM_PRE41_BUSY0_SHIFT 3 -#define CCM_PRE41_MUX_B_MASK 0x700u -#define CCM_PRE41_MUX_B_SHIFT 8 -#define CCM_PRE41_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE41_MUX_B_SHIFT))&CCM_PRE41_MUX_B_MASK) -#define CCM_PRE41_EN_B_MASK 0x1000u -#define CCM_PRE41_EN_B_SHIFT 12 -#define CCM_PRE41_BUSY1_MASK 0x8000u -#define CCM_PRE41_BUSY1_SHIFT 15 -#define CCM_PRE41_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE41_PRE_PODF_A_SHIFT 16 -#define CCM_PRE41_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE41_PRE_PODF_A_SHIFT))&CCM_PRE41_PRE_PODF_A_MASK) -#define CCM_PRE41_BUSY3_MASK 0x80000u -#define CCM_PRE41_BUSY3_SHIFT 19 -#define CCM_PRE41_MUX_A_MASK 0x7000000u -#define CCM_PRE41_MUX_A_SHIFT 24 -#define CCM_PRE41_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE41_MUX_A_SHIFT))&CCM_PRE41_MUX_A_MASK) -#define CCM_PRE41_EN_A_MASK 0x10000000u -#define CCM_PRE41_EN_A_SHIFT 28 -#define CCM_PRE41_BUSY4_MASK 0x80000000u -#define CCM_PRE41_BUSY4_SHIFT 31 -/* PRE_ROOT41_SET Bit Fields */ -#define CCM_PRE_ROOT41_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT41_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT41_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT41_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT41_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT41_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT41_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT41_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT41_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_SET_MUX_B_SHIFT))&CCM_PRE_ROOT41_SET_MUX_B_MASK) -#define CCM_PRE_ROOT41_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT41_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT41_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT41_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT41_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT41_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT41_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT41_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT41_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT41_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT41_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT41_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT41_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_SET_MUX_A_SHIFT))&CCM_PRE_ROOT41_SET_MUX_A_MASK) -#define CCM_PRE_ROOT41_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT41_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT41_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT41_SET_BUSY4_SHIFT 31 -/* PRE_ROOT41_CLR Bit Fields */ -#define CCM_PRE_ROOT41_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT41_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT41_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT41_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT41_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT41_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT41_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT41_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT41_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT41_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT41_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT41_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT41_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT41_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT41_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT41_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT41_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT41_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT41_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT41_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT41_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT41_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT41_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT41_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT41_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT41_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT41_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT41_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT41_TOG Bit Fields */ -#define CCM_PRE_ROOT41_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT41_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT41_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT41_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT41_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT41_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT41_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT41_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT41_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT41_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT41_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT41_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT41_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT41_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT41_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT41_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT41_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT41_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT41_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT41_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT41_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT41_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT41_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT41_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT41_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT41_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT41_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT41_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL41 Bit Fields */ -#define CCM_ACCESS_CTRL41_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL41_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL41_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL41_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL41_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL41_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL41_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL41_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL41_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL41_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL41_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL41_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL41_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL41_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL41_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL41_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL41_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL41_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL41_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL41_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL41_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL41_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL41_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL41_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL41_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL41_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL41_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL41_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL41_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL41_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL41_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL41_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL41_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL41_LOCK_SHIFT 31 -/* ACCESS_CTRL41_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL41_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL41_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL41_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL41_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL41_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL41_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL41_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL41_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL41_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL41_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL41_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL41_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL41_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL41_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL41_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL41_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT42 Bit Fields */ -#define CCM_TARGET_ROOT42_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT42_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT42_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_POST_PODF_SHIFT))&CCM_TARGET_ROOT42_POST_PODF_MASK) -#define CCM_TARGET_ROOT42_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT42_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT42_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT42_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT42_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT42_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT42_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT42_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT42_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT42_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT42_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_PRE_PODF_SHIFT))&CCM_TARGET_ROOT42_PRE_PODF_MASK) -#define CCM_TARGET_ROOT42_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT42_MUX_SHIFT 24 -#define CCM_TARGET_ROOT42_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_MUX_SHIFT))&CCM_TARGET_ROOT42_MUX_MASK) -#define CCM_TARGET_ROOT42_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT42_ENABLE_SHIFT 28 -/* TARGET_ROOT42_SET Bit Fields */ -#define CCM_TARGET_ROOT42_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT42_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT42_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT42_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT42_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT42_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT42_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT42_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT42_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT42_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT42_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT42_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT42_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT42_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT42_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT42_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT42_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT42_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT42_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_SET_MUX_SHIFT))&CCM_TARGET_ROOT42_SET_MUX_MASK) -#define CCM_TARGET_ROOT42_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT42_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT42_CLR Bit Fields */ -#define CCM_TARGET_ROOT42_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT42_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT42_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT42_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT42_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT42_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT42_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT42_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT42_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT42_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT42_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT42_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT42_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT42_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT42_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT42_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT42_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT42_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT42_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_CLR_MUX_SHIFT))&CCM_TARGET_ROOT42_CLR_MUX_MASK) -#define CCM_TARGET_ROOT42_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT42_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT42_TOG Bit Fields */ -#define CCM_TARGET_ROOT42_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT42_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT42_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT42_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT42_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT42_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT42_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT42_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT42_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT42_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT42_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT42_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT42_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT42_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT42_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT42_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT42_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT42_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT42_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_TOG_MUX_SHIFT))&CCM_TARGET_ROOT42_TOG_MUX_MASK) -#define CCM_TARGET_ROOT42_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT42_TOG_ENABLE_SHIFT 28 -/* POST42 Bit Fields */ -#define CCM_POST42_POST_PODF_MASK 0x3Fu -#define CCM_POST42_POST_PODF_SHIFT 0 -#define CCM_POST42_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST42_POST_PODF_SHIFT))&CCM_POST42_POST_PODF_MASK) -#define CCM_POST42_BUSY1_MASK 0x80u -#define CCM_POST42_BUSY1_SHIFT 7 -#define CCM_POST42_AUTO_PODF_MASK 0x700u -#define CCM_POST42_AUTO_PODF_SHIFT 8 -#define CCM_POST42_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST42_AUTO_PODF_SHIFT))&CCM_POST42_AUTO_PODF_MASK) -#define CCM_POST42_AUTO_EN_MASK 0x1000u -#define CCM_POST42_AUTO_EN_SHIFT 12 -#define CCM_POST42_SLOW_MASK 0x8000u -#define CCM_POST42_SLOW_SHIFT 15 -#define CCM_POST42_SELECT_MASK 0x10000000u -#define CCM_POST42_SELECT_SHIFT 28 -#define CCM_POST42_BUSY2_MASK 0x80000000u -#define CCM_POST42_BUSY2_SHIFT 31 -/* POST_ROOT42_SET Bit Fields */ -#define CCM_POST_ROOT42_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT42_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT42_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_SET_POST_PODF_SHIFT))&CCM_POST_ROOT42_SET_POST_PODF_MASK) -#define CCM_POST_ROOT42_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT42_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT42_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT42_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT42_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT42_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT42_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT42_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT42_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT42_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT42_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT42_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT42_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT42_SET_BUSY2_SHIFT 31 -/* POST_ROOT42_CLR Bit Fields */ -#define CCM_POST_ROOT42_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT42_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT42_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT42_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT42_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT42_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT42_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT42_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT42_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT42_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT42_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT42_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT42_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT42_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT42_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT42_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT42_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT42_CLR_BUSY2_SHIFT 31 -/* POST_ROOT42_TOG Bit Fields */ -#define CCM_POST_ROOT42_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT42_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT42_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT42_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT42_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT42_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT42_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT42_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT42_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT42_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT42_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT42_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT42_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT42_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT42_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT42_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT42_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT42_TOG_BUSY2_SHIFT 31 -/* PRE42 Bit Fields */ -#define CCM_PRE42_PRE_PODF_B_MASK 0x7u -#define CCM_PRE42_PRE_PODF_B_SHIFT 0 -#define CCM_PRE42_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE42_PRE_PODF_B_SHIFT))&CCM_PRE42_PRE_PODF_B_MASK) -#define CCM_PRE42_BUSY0_MASK 0x8u -#define CCM_PRE42_BUSY0_SHIFT 3 -#define CCM_PRE42_MUX_B_MASK 0x700u -#define CCM_PRE42_MUX_B_SHIFT 8 -#define CCM_PRE42_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE42_MUX_B_SHIFT))&CCM_PRE42_MUX_B_MASK) -#define CCM_PRE42_EN_B_MASK 0x1000u -#define CCM_PRE42_EN_B_SHIFT 12 -#define CCM_PRE42_BUSY1_MASK 0x8000u -#define CCM_PRE42_BUSY1_SHIFT 15 -#define CCM_PRE42_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE42_PRE_PODF_A_SHIFT 16 -#define CCM_PRE42_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE42_PRE_PODF_A_SHIFT))&CCM_PRE42_PRE_PODF_A_MASK) -#define CCM_PRE42_BUSY3_MASK 0x80000u -#define CCM_PRE42_BUSY3_SHIFT 19 -#define CCM_PRE42_MUX_A_MASK 0x7000000u -#define CCM_PRE42_MUX_A_SHIFT 24 -#define CCM_PRE42_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE42_MUX_A_SHIFT))&CCM_PRE42_MUX_A_MASK) -#define CCM_PRE42_EN_A_MASK 0x10000000u -#define CCM_PRE42_EN_A_SHIFT 28 -#define CCM_PRE42_BUSY4_MASK 0x80000000u -#define CCM_PRE42_BUSY4_SHIFT 31 -/* PRE_ROOT42_SET Bit Fields */ -#define CCM_PRE_ROOT42_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT42_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT42_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT42_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT42_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT42_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT42_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT42_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT42_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_SET_MUX_B_SHIFT))&CCM_PRE_ROOT42_SET_MUX_B_MASK) -#define CCM_PRE_ROOT42_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT42_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT42_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT42_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT42_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT42_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT42_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT42_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT42_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT42_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT42_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT42_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT42_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_SET_MUX_A_SHIFT))&CCM_PRE_ROOT42_SET_MUX_A_MASK) -#define CCM_PRE_ROOT42_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT42_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT42_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT42_SET_BUSY4_SHIFT 31 -/* PRE_ROOT42_CLR Bit Fields */ -#define CCM_PRE_ROOT42_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT42_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT42_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT42_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT42_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT42_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT42_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT42_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT42_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT42_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT42_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT42_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT42_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT42_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT42_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT42_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT42_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT42_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT42_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT42_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT42_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT42_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT42_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT42_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT42_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT42_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT42_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT42_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT42_TOG Bit Fields */ -#define CCM_PRE_ROOT42_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT42_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT42_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT42_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT42_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT42_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT42_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT42_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT42_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT42_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT42_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT42_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT42_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT42_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT42_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT42_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT42_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT42_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT42_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT42_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT42_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT42_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT42_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT42_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT42_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT42_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT42_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT42_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL42 Bit Fields */ -#define CCM_ACCESS_CTRL42_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL42_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL42_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL42_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL42_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL42_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL42_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL42_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL42_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL42_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL42_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL42_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL42_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL42_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL42_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL42_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL42_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL42_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL42_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL42_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL42_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL42_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL42_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL42_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL42_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL42_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL42_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL42_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL42_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL42_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL42_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL42_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL42_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL42_LOCK_SHIFT 31 -/* ACCESS_CTRL42_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL42_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL42_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL42_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL42_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL42_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL42_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL42_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL42_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL42_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL42_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL42_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL42_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL42_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL42_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL42_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL42_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT43 Bit Fields */ -#define CCM_TARGET_ROOT43_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT43_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT43_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_POST_PODF_SHIFT))&CCM_TARGET_ROOT43_POST_PODF_MASK) -#define CCM_TARGET_ROOT43_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT43_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT43_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT43_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT43_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT43_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT43_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT43_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT43_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT43_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT43_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_PRE_PODF_SHIFT))&CCM_TARGET_ROOT43_PRE_PODF_MASK) -#define CCM_TARGET_ROOT43_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT43_MUX_SHIFT 24 -#define CCM_TARGET_ROOT43_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_MUX_SHIFT))&CCM_TARGET_ROOT43_MUX_MASK) -#define CCM_TARGET_ROOT43_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT43_ENABLE_SHIFT 28 -/* TARGET_ROOT43_SET Bit Fields */ -#define CCM_TARGET_ROOT43_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT43_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT43_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT43_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT43_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT43_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT43_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT43_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT43_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT43_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT43_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT43_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT43_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT43_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT43_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT43_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT43_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT43_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT43_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_SET_MUX_SHIFT))&CCM_TARGET_ROOT43_SET_MUX_MASK) -#define CCM_TARGET_ROOT43_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT43_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT43_CLR Bit Fields */ -#define CCM_TARGET_ROOT43_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT43_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT43_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT43_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT43_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT43_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT43_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT43_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT43_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT43_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT43_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT43_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT43_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT43_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT43_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT43_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT43_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT43_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT43_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_CLR_MUX_SHIFT))&CCM_TARGET_ROOT43_CLR_MUX_MASK) -#define CCM_TARGET_ROOT43_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT43_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT43_TOG Bit Fields */ -#define CCM_TARGET_ROOT43_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT43_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT43_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT43_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT43_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT43_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT43_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT43_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT43_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT43_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT43_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT43_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT43_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT43_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT43_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT43_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT43_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT43_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT43_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_TOG_MUX_SHIFT))&CCM_TARGET_ROOT43_TOG_MUX_MASK) -#define CCM_TARGET_ROOT43_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT43_TOG_ENABLE_SHIFT 28 -/* POST43 Bit Fields */ -#define CCM_POST43_POST_PODF_MASK 0x3Fu -#define CCM_POST43_POST_PODF_SHIFT 0 -#define CCM_POST43_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST43_POST_PODF_SHIFT))&CCM_POST43_POST_PODF_MASK) -#define CCM_POST43_BUSY1_MASK 0x80u -#define CCM_POST43_BUSY1_SHIFT 7 -#define CCM_POST43_AUTO_PODF_MASK 0x700u -#define CCM_POST43_AUTO_PODF_SHIFT 8 -#define CCM_POST43_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST43_AUTO_PODF_SHIFT))&CCM_POST43_AUTO_PODF_MASK) -#define CCM_POST43_AUTO_EN_MASK 0x1000u -#define CCM_POST43_AUTO_EN_SHIFT 12 -#define CCM_POST43_SLOW_MASK 0x8000u -#define CCM_POST43_SLOW_SHIFT 15 -#define CCM_POST43_SELECT_MASK 0x10000000u -#define CCM_POST43_SELECT_SHIFT 28 -#define CCM_POST43_BUSY2_MASK 0x80000000u -#define CCM_POST43_BUSY2_SHIFT 31 -/* POST_ROOT43_SET Bit Fields */ -#define CCM_POST_ROOT43_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT43_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT43_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_SET_POST_PODF_SHIFT))&CCM_POST_ROOT43_SET_POST_PODF_MASK) -#define CCM_POST_ROOT43_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT43_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT43_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT43_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT43_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT43_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT43_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT43_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT43_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT43_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT43_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT43_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT43_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT43_SET_BUSY2_SHIFT 31 -/* POST_ROOT43_CLR Bit Fields */ -#define CCM_POST_ROOT43_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT43_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT43_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT43_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT43_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT43_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT43_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT43_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT43_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT43_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT43_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT43_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT43_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT43_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT43_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT43_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT43_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT43_CLR_BUSY2_SHIFT 31 -/* POST_ROOT43_TOG Bit Fields */ -#define CCM_POST_ROOT43_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT43_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT43_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT43_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT43_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT43_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT43_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT43_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT43_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT43_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT43_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT43_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT43_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT43_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT43_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT43_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT43_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT43_TOG_BUSY2_SHIFT 31 -/* PRE43 Bit Fields */ -#define CCM_PRE43_PRE_PODF_B_MASK 0x7u -#define CCM_PRE43_PRE_PODF_B_SHIFT 0 -#define CCM_PRE43_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE43_PRE_PODF_B_SHIFT))&CCM_PRE43_PRE_PODF_B_MASK) -#define CCM_PRE43_BUSY0_MASK 0x8u -#define CCM_PRE43_BUSY0_SHIFT 3 -#define CCM_PRE43_MUX_B_MASK 0x700u -#define CCM_PRE43_MUX_B_SHIFT 8 -#define CCM_PRE43_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE43_MUX_B_SHIFT))&CCM_PRE43_MUX_B_MASK) -#define CCM_PRE43_EN_B_MASK 0x1000u -#define CCM_PRE43_EN_B_SHIFT 12 -#define CCM_PRE43_BUSY1_MASK 0x8000u -#define CCM_PRE43_BUSY1_SHIFT 15 -#define CCM_PRE43_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE43_PRE_PODF_A_SHIFT 16 -#define CCM_PRE43_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE43_PRE_PODF_A_SHIFT))&CCM_PRE43_PRE_PODF_A_MASK) -#define CCM_PRE43_BUSY3_MASK 0x80000u -#define CCM_PRE43_BUSY3_SHIFT 19 -#define CCM_PRE43_MUX_A_MASK 0x7000000u -#define CCM_PRE43_MUX_A_SHIFT 24 -#define CCM_PRE43_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE43_MUX_A_SHIFT))&CCM_PRE43_MUX_A_MASK) -#define CCM_PRE43_EN_A_MASK 0x10000000u -#define CCM_PRE43_EN_A_SHIFT 28 -#define CCM_PRE43_BUSY4_MASK 0x80000000u -#define CCM_PRE43_BUSY4_SHIFT 31 -/* PRE_ROOT43_SET Bit Fields */ -#define CCM_PRE_ROOT43_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT43_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT43_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT43_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT43_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT43_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT43_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT43_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT43_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_SET_MUX_B_SHIFT))&CCM_PRE_ROOT43_SET_MUX_B_MASK) -#define CCM_PRE_ROOT43_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT43_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT43_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT43_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT43_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT43_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT43_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT43_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT43_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT43_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT43_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT43_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT43_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_SET_MUX_A_SHIFT))&CCM_PRE_ROOT43_SET_MUX_A_MASK) -#define CCM_PRE_ROOT43_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT43_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT43_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT43_SET_BUSY4_SHIFT 31 -/* PRE_ROOT43_CLR Bit Fields */ -#define CCM_PRE_ROOT43_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT43_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT43_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT43_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT43_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT43_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT43_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT43_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT43_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT43_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT43_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT43_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT43_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT43_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT43_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT43_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT43_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT43_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT43_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT43_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT43_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT43_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT43_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT43_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT43_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT43_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT43_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT43_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT43_TOG Bit Fields */ -#define CCM_PRE_ROOT43_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT43_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT43_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT43_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT43_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT43_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT43_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT43_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT43_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT43_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT43_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT43_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT43_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT43_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT43_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT43_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT43_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT43_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT43_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT43_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT43_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT43_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT43_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT43_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT43_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT43_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT43_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT43_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL43 Bit Fields */ -#define CCM_ACCESS_CTRL43_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL43_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL43_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL43_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL43_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL43_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL43_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL43_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL43_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL43_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL43_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL43_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL43_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL43_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL43_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL43_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL43_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL43_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL43_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL43_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL43_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL43_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL43_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL43_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL43_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL43_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL43_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL43_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL43_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL43_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL43_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL43_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL43_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL43_LOCK_SHIFT 31 -/* ACCESS_CTRL43_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL43_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL43_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL43_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL43_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL43_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL43_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL43_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL43_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL43_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL43_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL43_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL43_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL43_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL43_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL43_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL43_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT44 Bit Fields */ -#define CCM_TARGET_ROOT44_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT44_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT44_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_POST_PODF_SHIFT))&CCM_TARGET_ROOT44_POST_PODF_MASK) -#define CCM_TARGET_ROOT44_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT44_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT44_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT44_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT44_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT44_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT44_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT44_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT44_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT44_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT44_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_PRE_PODF_SHIFT))&CCM_TARGET_ROOT44_PRE_PODF_MASK) -#define CCM_TARGET_ROOT44_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT44_MUX_SHIFT 24 -#define CCM_TARGET_ROOT44_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_MUX_SHIFT))&CCM_TARGET_ROOT44_MUX_MASK) -#define CCM_TARGET_ROOT44_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT44_ENABLE_SHIFT 28 -/* TARGET_ROOT44_SET Bit Fields */ -#define CCM_TARGET_ROOT44_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT44_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT44_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT44_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT44_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT44_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT44_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT44_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT44_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT44_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT44_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT44_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT44_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT44_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT44_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT44_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT44_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT44_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT44_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_SET_MUX_SHIFT))&CCM_TARGET_ROOT44_SET_MUX_MASK) -#define CCM_TARGET_ROOT44_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT44_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT44_CLR Bit Fields */ -#define CCM_TARGET_ROOT44_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT44_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT44_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT44_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT44_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT44_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT44_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT44_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT44_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT44_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT44_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT44_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT44_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT44_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT44_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT44_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT44_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT44_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT44_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_CLR_MUX_SHIFT))&CCM_TARGET_ROOT44_CLR_MUX_MASK) -#define CCM_TARGET_ROOT44_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT44_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT44_TOG Bit Fields */ -#define CCM_TARGET_ROOT44_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT44_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT44_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT44_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT44_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT44_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT44_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT44_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT44_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT44_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT44_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT44_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT44_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT44_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT44_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT44_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT44_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT44_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT44_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_TOG_MUX_SHIFT))&CCM_TARGET_ROOT44_TOG_MUX_MASK) -#define CCM_TARGET_ROOT44_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT44_TOG_ENABLE_SHIFT 28 -/* POST44 Bit Fields */ -#define CCM_POST44_POST_PODF_MASK 0x3Fu -#define CCM_POST44_POST_PODF_SHIFT 0 -#define CCM_POST44_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST44_POST_PODF_SHIFT))&CCM_POST44_POST_PODF_MASK) -#define CCM_POST44_BUSY1_MASK 0x80u -#define CCM_POST44_BUSY1_SHIFT 7 -#define CCM_POST44_AUTO_PODF_MASK 0x700u -#define CCM_POST44_AUTO_PODF_SHIFT 8 -#define CCM_POST44_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST44_AUTO_PODF_SHIFT))&CCM_POST44_AUTO_PODF_MASK) -#define CCM_POST44_AUTO_EN_MASK 0x1000u -#define CCM_POST44_AUTO_EN_SHIFT 12 -#define CCM_POST44_SLOW_MASK 0x8000u -#define CCM_POST44_SLOW_SHIFT 15 -#define CCM_POST44_SELECT_MASK 0x10000000u -#define CCM_POST44_SELECT_SHIFT 28 -#define CCM_POST44_BUSY2_MASK 0x80000000u -#define CCM_POST44_BUSY2_SHIFT 31 -/* POST_ROOT44_SET Bit Fields */ -#define CCM_POST_ROOT44_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT44_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT44_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_SET_POST_PODF_SHIFT))&CCM_POST_ROOT44_SET_POST_PODF_MASK) -#define CCM_POST_ROOT44_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT44_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT44_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT44_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT44_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT44_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT44_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT44_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT44_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT44_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT44_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT44_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT44_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT44_SET_BUSY2_SHIFT 31 -/* POST_ROOT44_CLR Bit Fields */ -#define CCM_POST_ROOT44_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT44_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT44_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT44_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT44_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT44_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT44_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT44_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT44_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT44_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT44_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT44_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT44_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT44_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT44_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT44_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT44_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT44_CLR_BUSY2_SHIFT 31 -/* POST_ROOT44_TOG Bit Fields */ -#define CCM_POST_ROOT44_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT44_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT44_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT44_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT44_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT44_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT44_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT44_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT44_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT44_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT44_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT44_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT44_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT44_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT44_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT44_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT44_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT44_TOG_BUSY2_SHIFT 31 -/* PRE44 Bit Fields */ -#define CCM_PRE44_PRE_PODF_B_MASK 0x7u -#define CCM_PRE44_PRE_PODF_B_SHIFT 0 -#define CCM_PRE44_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE44_PRE_PODF_B_SHIFT))&CCM_PRE44_PRE_PODF_B_MASK) -#define CCM_PRE44_BUSY0_MASK 0x8u -#define CCM_PRE44_BUSY0_SHIFT 3 -#define CCM_PRE44_MUX_B_MASK 0x700u -#define CCM_PRE44_MUX_B_SHIFT 8 -#define CCM_PRE44_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE44_MUX_B_SHIFT))&CCM_PRE44_MUX_B_MASK) -#define CCM_PRE44_EN_B_MASK 0x1000u -#define CCM_PRE44_EN_B_SHIFT 12 -#define CCM_PRE44_BUSY1_MASK 0x8000u -#define CCM_PRE44_BUSY1_SHIFT 15 -#define CCM_PRE44_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE44_PRE_PODF_A_SHIFT 16 -#define CCM_PRE44_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE44_PRE_PODF_A_SHIFT))&CCM_PRE44_PRE_PODF_A_MASK) -#define CCM_PRE44_BUSY3_MASK 0x80000u -#define CCM_PRE44_BUSY3_SHIFT 19 -#define CCM_PRE44_MUX_A_MASK 0x7000000u -#define CCM_PRE44_MUX_A_SHIFT 24 -#define CCM_PRE44_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE44_MUX_A_SHIFT))&CCM_PRE44_MUX_A_MASK) -#define CCM_PRE44_EN_A_MASK 0x10000000u -#define CCM_PRE44_EN_A_SHIFT 28 -#define CCM_PRE44_BUSY4_MASK 0x80000000u -#define CCM_PRE44_BUSY4_SHIFT 31 -/* PRE_ROOT44_SET Bit Fields */ -#define CCM_PRE_ROOT44_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT44_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT44_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT44_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT44_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT44_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT44_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT44_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT44_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_SET_MUX_B_SHIFT))&CCM_PRE_ROOT44_SET_MUX_B_MASK) -#define CCM_PRE_ROOT44_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT44_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT44_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT44_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT44_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT44_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT44_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT44_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT44_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT44_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT44_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT44_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT44_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_SET_MUX_A_SHIFT))&CCM_PRE_ROOT44_SET_MUX_A_MASK) -#define CCM_PRE_ROOT44_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT44_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT44_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT44_SET_BUSY4_SHIFT 31 -/* PRE_ROOT44_CLR Bit Fields */ -#define CCM_PRE_ROOT44_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT44_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT44_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT44_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT44_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT44_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT44_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT44_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT44_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT44_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT44_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT44_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT44_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT44_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT44_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT44_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT44_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT44_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT44_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT44_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT44_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT44_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT44_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT44_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT44_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT44_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT44_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT44_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT44_TOG Bit Fields */ -#define CCM_PRE_ROOT44_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT44_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT44_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT44_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT44_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT44_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT44_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT44_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT44_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT44_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT44_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT44_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT44_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT44_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT44_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT44_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT44_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT44_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT44_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT44_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT44_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT44_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT44_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT44_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT44_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT44_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT44_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT44_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL44 Bit Fields */ -#define CCM_ACCESS_CTRL44_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL44_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL44_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL44_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL44_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL44_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL44_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL44_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL44_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL44_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL44_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL44_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL44_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL44_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL44_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL44_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL44_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL44_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL44_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL44_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL44_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL44_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL44_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL44_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL44_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL44_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL44_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL44_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL44_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL44_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL44_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL44_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL44_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL44_LOCK_SHIFT 31 -/* ACCESS_CTRL44_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL44_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL44_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL44_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL44_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL44_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL44_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL44_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL44_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL44_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL44_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL44_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL44_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL44_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL44_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL44_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL44_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT45 Bit Fields */ -#define CCM_TARGET_ROOT45_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT45_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT45_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_POST_PODF_SHIFT))&CCM_TARGET_ROOT45_POST_PODF_MASK) -#define CCM_TARGET_ROOT45_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT45_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT45_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT45_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT45_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT45_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT45_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT45_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT45_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT45_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT45_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_PRE_PODF_SHIFT))&CCM_TARGET_ROOT45_PRE_PODF_MASK) -#define CCM_TARGET_ROOT45_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT45_MUX_SHIFT 24 -#define CCM_TARGET_ROOT45_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_MUX_SHIFT))&CCM_TARGET_ROOT45_MUX_MASK) -#define CCM_TARGET_ROOT45_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT45_ENABLE_SHIFT 28 -/* TARGET_ROOT45_SET Bit Fields */ -#define CCM_TARGET_ROOT45_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT45_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT45_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT45_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT45_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT45_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT45_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT45_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT45_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT45_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT45_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT45_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT45_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT45_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT45_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT45_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT45_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT45_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT45_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_SET_MUX_SHIFT))&CCM_TARGET_ROOT45_SET_MUX_MASK) -#define CCM_TARGET_ROOT45_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT45_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT45_CLR Bit Fields */ -#define CCM_TARGET_ROOT45_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT45_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT45_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT45_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT45_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT45_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT45_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT45_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT45_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT45_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT45_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT45_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT45_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT45_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT45_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT45_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT45_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT45_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT45_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_CLR_MUX_SHIFT))&CCM_TARGET_ROOT45_CLR_MUX_MASK) -#define CCM_TARGET_ROOT45_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT45_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT45_TOG Bit Fields */ -#define CCM_TARGET_ROOT45_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT45_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT45_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT45_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT45_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT45_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT45_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT45_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT45_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT45_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT45_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT45_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT45_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT45_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT45_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT45_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT45_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT45_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT45_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_TOG_MUX_SHIFT))&CCM_TARGET_ROOT45_TOG_MUX_MASK) -#define CCM_TARGET_ROOT45_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT45_TOG_ENABLE_SHIFT 28 -/* POST45 Bit Fields */ -#define CCM_POST45_POST_PODF_MASK 0x3Fu -#define CCM_POST45_POST_PODF_SHIFT 0 -#define CCM_POST45_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST45_POST_PODF_SHIFT))&CCM_POST45_POST_PODF_MASK) -#define CCM_POST45_BUSY1_MASK 0x80u -#define CCM_POST45_BUSY1_SHIFT 7 -#define CCM_POST45_AUTO_PODF_MASK 0x700u -#define CCM_POST45_AUTO_PODF_SHIFT 8 -#define CCM_POST45_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST45_AUTO_PODF_SHIFT))&CCM_POST45_AUTO_PODF_MASK) -#define CCM_POST45_AUTO_EN_MASK 0x1000u -#define CCM_POST45_AUTO_EN_SHIFT 12 -#define CCM_POST45_SLOW_MASK 0x8000u -#define CCM_POST45_SLOW_SHIFT 15 -#define CCM_POST45_SELECT_MASK 0x10000000u -#define CCM_POST45_SELECT_SHIFT 28 -#define CCM_POST45_BUSY2_MASK 0x80000000u -#define CCM_POST45_BUSY2_SHIFT 31 -/* POST_ROOT45_SET Bit Fields */ -#define CCM_POST_ROOT45_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT45_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT45_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_SET_POST_PODF_SHIFT))&CCM_POST_ROOT45_SET_POST_PODF_MASK) -#define CCM_POST_ROOT45_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT45_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT45_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT45_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT45_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT45_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT45_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT45_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT45_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT45_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT45_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT45_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT45_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT45_SET_BUSY2_SHIFT 31 -/* POST_ROOT45_CLR Bit Fields */ -#define CCM_POST_ROOT45_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT45_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT45_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT45_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT45_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT45_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT45_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT45_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT45_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT45_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT45_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT45_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT45_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT45_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT45_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT45_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT45_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT45_CLR_BUSY2_SHIFT 31 -/* POST_ROOT45_TOG Bit Fields */ -#define CCM_POST_ROOT45_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT45_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT45_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT45_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT45_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT45_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT45_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT45_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT45_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT45_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT45_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT45_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT45_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT45_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT45_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT45_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT45_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT45_TOG_BUSY2_SHIFT 31 -/* PRE45 Bit Fields */ -#define CCM_PRE45_PRE_PODF_B_MASK 0x7u -#define CCM_PRE45_PRE_PODF_B_SHIFT 0 -#define CCM_PRE45_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE45_PRE_PODF_B_SHIFT))&CCM_PRE45_PRE_PODF_B_MASK) -#define CCM_PRE45_BUSY0_MASK 0x8u -#define CCM_PRE45_BUSY0_SHIFT 3 -#define CCM_PRE45_MUX_B_MASK 0x700u -#define CCM_PRE45_MUX_B_SHIFT 8 -#define CCM_PRE45_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE45_MUX_B_SHIFT))&CCM_PRE45_MUX_B_MASK) -#define CCM_PRE45_EN_B_MASK 0x1000u -#define CCM_PRE45_EN_B_SHIFT 12 -#define CCM_PRE45_BUSY1_MASK 0x8000u -#define CCM_PRE45_BUSY1_SHIFT 15 -#define CCM_PRE45_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE45_PRE_PODF_A_SHIFT 16 -#define CCM_PRE45_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE45_PRE_PODF_A_SHIFT))&CCM_PRE45_PRE_PODF_A_MASK) -#define CCM_PRE45_BUSY3_MASK 0x80000u -#define CCM_PRE45_BUSY3_SHIFT 19 -#define CCM_PRE45_MUX_A_MASK 0x7000000u -#define CCM_PRE45_MUX_A_SHIFT 24 -#define CCM_PRE45_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE45_MUX_A_SHIFT))&CCM_PRE45_MUX_A_MASK) -#define CCM_PRE45_EN_A_MASK 0x10000000u -#define CCM_PRE45_EN_A_SHIFT 28 -#define CCM_PRE45_BUSY4_MASK 0x80000000u -#define CCM_PRE45_BUSY4_SHIFT 31 -/* PRE_ROOT45_SET Bit Fields */ -#define CCM_PRE_ROOT45_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT45_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT45_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT45_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT45_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT45_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT45_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT45_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT45_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_SET_MUX_B_SHIFT))&CCM_PRE_ROOT45_SET_MUX_B_MASK) -#define CCM_PRE_ROOT45_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT45_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT45_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT45_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT45_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT45_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT45_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT45_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT45_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT45_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT45_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT45_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT45_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_SET_MUX_A_SHIFT))&CCM_PRE_ROOT45_SET_MUX_A_MASK) -#define CCM_PRE_ROOT45_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT45_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT45_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT45_SET_BUSY4_SHIFT 31 -/* PRE_ROOT45_CLR Bit Fields */ -#define CCM_PRE_ROOT45_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT45_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT45_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT45_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT45_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT45_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT45_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT45_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT45_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT45_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT45_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT45_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT45_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT45_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT45_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT45_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT45_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT45_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT45_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT45_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT45_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT45_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT45_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT45_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT45_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT45_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT45_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT45_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT45_TOG Bit Fields */ -#define CCM_PRE_ROOT45_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT45_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT45_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT45_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT45_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT45_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT45_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT45_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT45_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT45_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT45_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT45_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT45_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT45_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT45_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT45_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT45_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT45_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT45_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT45_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT45_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT45_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT45_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT45_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT45_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT45_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT45_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT45_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL45 Bit Fields */ -#define CCM_ACCESS_CTRL45_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL45_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL45_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL45_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL45_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL45_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL45_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL45_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL45_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL45_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL45_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL45_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL45_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL45_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL45_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL45_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL45_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL45_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL45_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL45_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL45_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL45_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL45_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL45_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL45_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL45_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL45_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL45_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL45_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL45_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL45_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL45_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL45_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL45_LOCK_SHIFT 31 -/* ACCESS_CTRL45_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL45_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL45_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL45_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL45_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL45_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL45_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL45_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL45_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL45_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL45_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL45_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL45_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL45_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL45_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL45_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL45_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT46 Bit Fields */ -#define CCM_TARGET_ROOT46_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT46_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT46_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_POST_PODF_SHIFT))&CCM_TARGET_ROOT46_POST_PODF_MASK) -#define CCM_TARGET_ROOT46_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT46_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT46_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT46_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT46_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT46_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT46_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT46_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT46_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT46_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT46_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_PRE_PODF_SHIFT))&CCM_TARGET_ROOT46_PRE_PODF_MASK) -#define CCM_TARGET_ROOT46_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT46_MUX_SHIFT 24 -#define CCM_TARGET_ROOT46_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_MUX_SHIFT))&CCM_TARGET_ROOT46_MUX_MASK) -#define CCM_TARGET_ROOT46_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT46_ENABLE_SHIFT 28 -/* TARGET_ROOT46_SET Bit Fields */ -#define CCM_TARGET_ROOT46_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT46_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT46_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT46_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT46_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT46_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT46_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT46_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT46_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT46_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT46_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT46_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT46_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT46_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT46_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT46_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT46_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT46_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT46_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_SET_MUX_SHIFT))&CCM_TARGET_ROOT46_SET_MUX_MASK) -#define CCM_TARGET_ROOT46_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT46_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT46_CLR Bit Fields */ -#define CCM_TARGET_ROOT46_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT46_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT46_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT46_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT46_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT46_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT46_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT46_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT46_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT46_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT46_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT46_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT46_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT46_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT46_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT46_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT46_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT46_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT46_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_CLR_MUX_SHIFT))&CCM_TARGET_ROOT46_CLR_MUX_MASK) -#define CCM_TARGET_ROOT46_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT46_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT46_TOG Bit Fields */ -#define CCM_TARGET_ROOT46_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT46_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT46_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT46_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT46_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT46_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT46_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT46_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT46_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT46_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT46_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT46_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT46_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT46_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT46_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT46_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT46_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT46_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT46_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_TOG_MUX_SHIFT))&CCM_TARGET_ROOT46_TOG_MUX_MASK) -#define CCM_TARGET_ROOT46_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT46_TOG_ENABLE_SHIFT 28 -/* POST46 Bit Fields */ -#define CCM_POST46_POST_PODF_MASK 0x3Fu -#define CCM_POST46_POST_PODF_SHIFT 0 -#define CCM_POST46_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST46_POST_PODF_SHIFT))&CCM_POST46_POST_PODF_MASK) -#define CCM_POST46_BUSY1_MASK 0x80u -#define CCM_POST46_BUSY1_SHIFT 7 -#define CCM_POST46_AUTO_PODF_MASK 0x700u -#define CCM_POST46_AUTO_PODF_SHIFT 8 -#define CCM_POST46_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST46_AUTO_PODF_SHIFT))&CCM_POST46_AUTO_PODF_MASK) -#define CCM_POST46_AUTO_EN_MASK 0x1000u -#define CCM_POST46_AUTO_EN_SHIFT 12 -#define CCM_POST46_SLOW_MASK 0x8000u -#define CCM_POST46_SLOW_SHIFT 15 -#define CCM_POST46_SELECT_MASK 0x10000000u -#define CCM_POST46_SELECT_SHIFT 28 -#define CCM_POST46_BUSY2_MASK 0x80000000u -#define CCM_POST46_BUSY2_SHIFT 31 -/* POST_ROOT46_SET Bit Fields */ -#define CCM_POST_ROOT46_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT46_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT46_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_SET_POST_PODF_SHIFT))&CCM_POST_ROOT46_SET_POST_PODF_MASK) -#define CCM_POST_ROOT46_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT46_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT46_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT46_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT46_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT46_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT46_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT46_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT46_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT46_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT46_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT46_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT46_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT46_SET_BUSY2_SHIFT 31 -/* POST_ROOT46_CLR Bit Fields */ -#define CCM_POST_ROOT46_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT46_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT46_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT46_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT46_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT46_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT46_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT46_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT46_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT46_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT46_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT46_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT46_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT46_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT46_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT46_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT46_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT46_CLR_BUSY2_SHIFT 31 -/* POST_ROOT46_TOG Bit Fields */ -#define CCM_POST_ROOT46_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT46_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT46_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT46_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT46_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT46_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT46_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT46_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT46_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT46_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT46_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT46_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT46_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT46_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT46_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT46_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT46_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT46_TOG_BUSY2_SHIFT 31 -/* PRE46 Bit Fields */ -#define CCM_PRE46_PRE_PODF_B_MASK 0x7u -#define CCM_PRE46_PRE_PODF_B_SHIFT 0 -#define CCM_PRE46_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE46_PRE_PODF_B_SHIFT))&CCM_PRE46_PRE_PODF_B_MASK) -#define CCM_PRE46_BUSY0_MASK 0x8u -#define CCM_PRE46_BUSY0_SHIFT 3 -#define CCM_PRE46_MUX_B_MASK 0x700u -#define CCM_PRE46_MUX_B_SHIFT 8 -#define CCM_PRE46_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE46_MUX_B_SHIFT))&CCM_PRE46_MUX_B_MASK) -#define CCM_PRE46_EN_B_MASK 0x1000u -#define CCM_PRE46_EN_B_SHIFT 12 -#define CCM_PRE46_BUSY1_MASK 0x8000u -#define CCM_PRE46_BUSY1_SHIFT 15 -#define CCM_PRE46_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE46_PRE_PODF_A_SHIFT 16 -#define CCM_PRE46_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE46_PRE_PODF_A_SHIFT))&CCM_PRE46_PRE_PODF_A_MASK) -#define CCM_PRE46_BUSY3_MASK 0x80000u -#define CCM_PRE46_BUSY3_SHIFT 19 -#define CCM_PRE46_MUX_A_MASK 0x7000000u -#define CCM_PRE46_MUX_A_SHIFT 24 -#define CCM_PRE46_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE46_MUX_A_SHIFT))&CCM_PRE46_MUX_A_MASK) -#define CCM_PRE46_EN_A_MASK 0x10000000u -#define CCM_PRE46_EN_A_SHIFT 28 -#define CCM_PRE46_BUSY4_MASK 0x80000000u -#define CCM_PRE46_BUSY4_SHIFT 31 -/* PRE_ROOT46_SET Bit Fields */ -#define CCM_PRE_ROOT46_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT46_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT46_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT46_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT46_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT46_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT46_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT46_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT46_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_SET_MUX_B_SHIFT))&CCM_PRE_ROOT46_SET_MUX_B_MASK) -#define CCM_PRE_ROOT46_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT46_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT46_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT46_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT46_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT46_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT46_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT46_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT46_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT46_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT46_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT46_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT46_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_SET_MUX_A_SHIFT))&CCM_PRE_ROOT46_SET_MUX_A_MASK) -#define CCM_PRE_ROOT46_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT46_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT46_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT46_SET_BUSY4_SHIFT 31 -/* PRE_ROOT46_CLR Bit Fields */ -#define CCM_PRE_ROOT46_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT46_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT46_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT46_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT46_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT46_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT46_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT46_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT46_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT46_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT46_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT46_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT46_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT46_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT46_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT46_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT46_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT46_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT46_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT46_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT46_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT46_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT46_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT46_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT46_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT46_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT46_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT46_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT46_TOG Bit Fields */ -#define CCM_PRE_ROOT46_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT46_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT46_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT46_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT46_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT46_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT46_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT46_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT46_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT46_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT46_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT46_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT46_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT46_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT46_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT46_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT46_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT46_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT46_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT46_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT46_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT46_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT46_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT46_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT46_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT46_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT46_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT46_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL46 Bit Fields */ -#define CCM_ACCESS_CTRL46_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL46_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL46_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL46_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL46_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL46_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL46_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL46_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL46_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL46_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL46_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL46_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL46_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL46_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL46_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL46_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL46_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL46_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL46_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL46_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL46_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL46_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL46_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL46_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL46_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL46_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL46_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL46_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL46_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL46_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL46_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL46_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL46_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL46_LOCK_SHIFT 31 -/* ACCESS_CTRL46_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL46_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL46_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL46_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL46_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL46_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL46_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL46_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL46_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL46_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL46_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL46_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL46_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL46_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL46_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL46_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL46_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT47 Bit Fields */ -#define CCM_TARGET_ROOT47_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT47_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT47_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_POST_PODF_SHIFT))&CCM_TARGET_ROOT47_POST_PODF_MASK) -#define CCM_TARGET_ROOT47_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT47_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT47_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT47_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT47_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT47_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT47_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT47_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT47_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT47_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT47_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_PRE_PODF_SHIFT))&CCM_TARGET_ROOT47_PRE_PODF_MASK) -#define CCM_TARGET_ROOT47_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT47_MUX_SHIFT 24 -#define CCM_TARGET_ROOT47_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_MUX_SHIFT))&CCM_TARGET_ROOT47_MUX_MASK) -#define CCM_TARGET_ROOT47_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT47_ENABLE_SHIFT 28 -/* TARGET_ROOT47_SET Bit Fields */ -#define CCM_TARGET_ROOT47_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT47_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT47_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT47_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT47_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT47_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT47_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT47_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT47_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT47_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT47_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT47_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT47_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT47_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT47_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT47_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT47_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT47_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT47_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_SET_MUX_SHIFT))&CCM_TARGET_ROOT47_SET_MUX_MASK) -#define CCM_TARGET_ROOT47_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT47_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT47_CLR Bit Fields */ -#define CCM_TARGET_ROOT47_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT47_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT47_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT47_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT47_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT47_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT47_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT47_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT47_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT47_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT47_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT47_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT47_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT47_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT47_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT47_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT47_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT47_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT47_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_CLR_MUX_SHIFT))&CCM_TARGET_ROOT47_CLR_MUX_MASK) -#define CCM_TARGET_ROOT47_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT47_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT47_TOG Bit Fields */ -#define CCM_TARGET_ROOT47_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT47_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT47_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT47_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT47_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT47_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT47_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT47_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT47_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT47_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT47_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT47_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT47_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT47_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT47_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT47_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT47_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT47_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT47_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_TOG_MUX_SHIFT))&CCM_TARGET_ROOT47_TOG_MUX_MASK) -#define CCM_TARGET_ROOT47_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT47_TOG_ENABLE_SHIFT 28 -/* POST47 Bit Fields */ -#define CCM_POST47_POST_PODF_MASK 0x3Fu -#define CCM_POST47_POST_PODF_SHIFT 0 -#define CCM_POST47_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST47_POST_PODF_SHIFT))&CCM_POST47_POST_PODF_MASK) -#define CCM_POST47_BUSY1_MASK 0x80u -#define CCM_POST47_BUSY1_SHIFT 7 -#define CCM_POST47_AUTO_PODF_MASK 0x700u -#define CCM_POST47_AUTO_PODF_SHIFT 8 -#define CCM_POST47_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST47_AUTO_PODF_SHIFT))&CCM_POST47_AUTO_PODF_MASK) -#define CCM_POST47_AUTO_EN_MASK 0x1000u -#define CCM_POST47_AUTO_EN_SHIFT 12 -#define CCM_POST47_SLOW_MASK 0x8000u -#define CCM_POST47_SLOW_SHIFT 15 -#define CCM_POST47_SELECT_MASK 0x10000000u -#define CCM_POST47_SELECT_SHIFT 28 -#define CCM_POST47_BUSY2_MASK 0x80000000u -#define CCM_POST47_BUSY2_SHIFT 31 -/* POST_ROOT47_SET Bit Fields */ -#define CCM_POST_ROOT47_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT47_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT47_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_SET_POST_PODF_SHIFT))&CCM_POST_ROOT47_SET_POST_PODF_MASK) -#define CCM_POST_ROOT47_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT47_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT47_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT47_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT47_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT47_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT47_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT47_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT47_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT47_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT47_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT47_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT47_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT47_SET_BUSY2_SHIFT 31 -/* POST_ROOT47_CLR Bit Fields */ -#define CCM_POST_ROOT47_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT47_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT47_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT47_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT47_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT47_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT47_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT47_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT47_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT47_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT47_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT47_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT47_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT47_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT47_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT47_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT47_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT47_CLR_BUSY2_SHIFT 31 -/* POST_ROOT47_TOG Bit Fields */ -#define CCM_POST_ROOT47_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT47_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT47_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT47_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT47_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT47_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT47_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT47_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT47_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT47_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT47_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT47_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT47_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT47_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT47_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT47_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT47_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT47_TOG_BUSY2_SHIFT 31 -/* PRE47 Bit Fields */ -#define CCM_PRE47_PRE_PODF_B_MASK 0x7u -#define CCM_PRE47_PRE_PODF_B_SHIFT 0 -#define CCM_PRE47_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE47_PRE_PODF_B_SHIFT))&CCM_PRE47_PRE_PODF_B_MASK) -#define CCM_PRE47_BUSY0_MASK 0x8u -#define CCM_PRE47_BUSY0_SHIFT 3 -#define CCM_PRE47_MUX_B_MASK 0x700u -#define CCM_PRE47_MUX_B_SHIFT 8 -#define CCM_PRE47_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE47_MUX_B_SHIFT))&CCM_PRE47_MUX_B_MASK) -#define CCM_PRE47_EN_B_MASK 0x1000u -#define CCM_PRE47_EN_B_SHIFT 12 -#define CCM_PRE47_BUSY1_MASK 0x8000u -#define CCM_PRE47_BUSY1_SHIFT 15 -#define CCM_PRE47_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE47_PRE_PODF_A_SHIFT 16 -#define CCM_PRE47_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE47_PRE_PODF_A_SHIFT))&CCM_PRE47_PRE_PODF_A_MASK) -#define CCM_PRE47_BUSY3_MASK 0x80000u -#define CCM_PRE47_BUSY3_SHIFT 19 -#define CCM_PRE47_MUX_A_MASK 0x7000000u -#define CCM_PRE47_MUX_A_SHIFT 24 -#define CCM_PRE47_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE47_MUX_A_SHIFT))&CCM_PRE47_MUX_A_MASK) -#define CCM_PRE47_EN_A_MASK 0x10000000u -#define CCM_PRE47_EN_A_SHIFT 28 -#define CCM_PRE47_BUSY4_MASK 0x80000000u -#define CCM_PRE47_BUSY4_SHIFT 31 -/* PRE_ROOT47_SET Bit Fields */ -#define CCM_PRE_ROOT47_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT47_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT47_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT47_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT47_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT47_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT47_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT47_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT47_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_SET_MUX_B_SHIFT))&CCM_PRE_ROOT47_SET_MUX_B_MASK) -#define CCM_PRE_ROOT47_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT47_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT47_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT47_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT47_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT47_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT47_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT47_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT47_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT47_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT47_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT47_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT47_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_SET_MUX_A_SHIFT))&CCM_PRE_ROOT47_SET_MUX_A_MASK) -#define CCM_PRE_ROOT47_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT47_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT47_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT47_SET_BUSY4_SHIFT 31 -/* PRE_ROOT47_CLR Bit Fields */ -#define CCM_PRE_ROOT47_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT47_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT47_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT47_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT47_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT47_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT47_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT47_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT47_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT47_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT47_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT47_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT47_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT47_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT47_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT47_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT47_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT47_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT47_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT47_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT47_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT47_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT47_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT47_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT47_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT47_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT47_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT47_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT47_TOG Bit Fields */ -#define CCM_PRE_ROOT47_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT47_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT47_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT47_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT47_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT47_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT47_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT47_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT47_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT47_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT47_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT47_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT47_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT47_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT47_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT47_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT47_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT47_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT47_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT47_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT47_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT47_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT47_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT47_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT47_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT47_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT47_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT47_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL47 Bit Fields */ -#define CCM_ACCESS_CTRL47_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL47_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL47_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL47_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL47_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL47_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL47_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL47_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL47_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL47_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL47_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL47_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL47_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL47_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL47_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL47_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL47_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL47_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL47_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL47_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL47_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL47_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL47_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL47_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL47_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL47_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL47_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL47_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL47_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL47_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL47_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL47_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL47_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL47_LOCK_SHIFT 31 -/* ACCESS_CTRL47_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL47_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL47_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL47_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL47_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL47_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL47_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL47_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL47_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL47_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL47_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL47_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL47_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL47_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL47_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL47_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL47_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT48 Bit Fields */ -#define CCM_TARGET_ROOT48_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT48_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT48_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_POST_PODF_SHIFT))&CCM_TARGET_ROOT48_POST_PODF_MASK) -#define CCM_TARGET_ROOT48_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT48_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT48_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT48_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT48_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT48_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT48_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT48_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT48_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT48_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT48_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_PRE_PODF_SHIFT))&CCM_TARGET_ROOT48_PRE_PODF_MASK) -#define CCM_TARGET_ROOT48_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT48_MUX_SHIFT 24 -#define CCM_TARGET_ROOT48_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_MUX_SHIFT))&CCM_TARGET_ROOT48_MUX_MASK) -#define CCM_TARGET_ROOT48_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT48_ENABLE_SHIFT 28 -/* TARGET_ROOT48_SET Bit Fields */ -#define CCM_TARGET_ROOT48_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT48_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT48_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT48_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT48_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT48_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT48_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT48_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT48_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT48_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT48_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT48_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT48_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT48_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT48_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT48_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT48_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT48_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT48_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_SET_MUX_SHIFT))&CCM_TARGET_ROOT48_SET_MUX_MASK) -#define CCM_TARGET_ROOT48_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT48_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT48_CLR Bit Fields */ -#define CCM_TARGET_ROOT48_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT48_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT48_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT48_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT48_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT48_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT48_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT48_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT48_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT48_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT48_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT48_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT48_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT48_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT48_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT48_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT48_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT48_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT48_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_CLR_MUX_SHIFT))&CCM_TARGET_ROOT48_CLR_MUX_MASK) -#define CCM_TARGET_ROOT48_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT48_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT48_TOG Bit Fields */ -#define CCM_TARGET_ROOT48_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT48_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT48_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT48_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT48_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT48_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT48_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT48_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT48_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT48_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT48_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT48_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT48_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT48_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT48_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT48_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT48_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT48_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT48_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_TOG_MUX_SHIFT))&CCM_TARGET_ROOT48_TOG_MUX_MASK) -#define CCM_TARGET_ROOT48_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT48_TOG_ENABLE_SHIFT 28 -/* POST48 Bit Fields */ -#define CCM_POST48_POST_PODF_MASK 0x3Fu -#define CCM_POST48_POST_PODF_SHIFT 0 -#define CCM_POST48_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST48_POST_PODF_SHIFT))&CCM_POST48_POST_PODF_MASK) -#define CCM_POST48_BUSY1_MASK 0x80u -#define CCM_POST48_BUSY1_SHIFT 7 -#define CCM_POST48_AUTO_PODF_MASK 0x700u -#define CCM_POST48_AUTO_PODF_SHIFT 8 -#define CCM_POST48_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST48_AUTO_PODF_SHIFT))&CCM_POST48_AUTO_PODF_MASK) -#define CCM_POST48_AUTO_EN_MASK 0x1000u -#define CCM_POST48_AUTO_EN_SHIFT 12 -#define CCM_POST48_SLOW_MASK 0x8000u -#define CCM_POST48_SLOW_SHIFT 15 -#define CCM_POST48_SELECT_MASK 0x10000000u -#define CCM_POST48_SELECT_SHIFT 28 -#define CCM_POST48_BUSY2_MASK 0x80000000u -#define CCM_POST48_BUSY2_SHIFT 31 -/* POST_ROOT48_SET Bit Fields */ -#define CCM_POST_ROOT48_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT48_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT48_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_SET_POST_PODF_SHIFT))&CCM_POST_ROOT48_SET_POST_PODF_MASK) -#define CCM_POST_ROOT48_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT48_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT48_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT48_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT48_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT48_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT48_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT48_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT48_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT48_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT48_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT48_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT48_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT48_SET_BUSY2_SHIFT 31 -/* POST_ROOT48_CLR Bit Fields */ -#define CCM_POST_ROOT48_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT48_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT48_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT48_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT48_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT48_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT48_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT48_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT48_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT48_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT48_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT48_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT48_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT48_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT48_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT48_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT48_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT48_CLR_BUSY2_SHIFT 31 -/* POST_ROOT48_TOG Bit Fields */ -#define CCM_POST_ROOT48_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT48_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT48_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT48_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT48_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT48_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT48_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT48_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT48_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT48_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT48_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT48_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT48_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT48_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT48_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT48_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT48_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT48_TOG_BUSY2_SHIFT 31 -/* PRE48 Bit Fields */ -#define CCM_PRE48_PRE_PODF_B_MASK 0x7u -#define CCM_PRE48_PRE_PODF_B_SHIFT 0 -#define CCM_PRE48_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE48_PRE_PODF_B_SHIFT))&CCM_PRE48_PRE_PODF_B_MASK) -#define CCM_PRE48_BUSY0_MASK 0x8u -#define CCM_PRE48_BUSY0_SHIFT 3 -#define CCM_PRE48_MUX_B_MASK 0x700u -#define CCM_PRE48_MUX_B_SHIFT 8 -#define CCM_PRE48_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE48_MUX_B_SHIFT))&CCM_PRE48_MUX_B_MASK) -#define CCM_PRE48_EN_B_MASK 0x1000u -#define CCM_PRE48_EN_B_SHIFT 12 -#define CCM_PRE48_BUSY1_MASK 0x8000u -#define CCM_PRE48_BUSY1_SHIFT 15 -#define CCM_PRE48_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE48_PRE_PODF_A_SHIFT 16 -#define CCM_PRE48_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE48_PRE_PODF_A_SHIFT))&CCM_PRE48_PRE_PODF_A_MASK) -#define CCM_PRE48_BUSY3_MASK 0x80000u -#define CCM_PRE48_BUSY3_SHIFT 19 -#define CCM_PRE48_MUX_A_MASK 0x7000000u -#define CCM_PRE48_MUX_A_SHIFT 24 -#define CCM_PRE48_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE48_MUX_A_SHIFT))&CCM_PRE48_MUX_A_MASK) -#define CCM_PRE48_EN_A_MASK 0x10000000u -#define CCM_PRE48_EN_A_SHIFT 28 -#define CCM_PRE48_BUSY4_MASK 0x80000000u -#define CCM_PRE48_BUSY4_SHIFT 31 -/* PRE_ROOT48_SET Bit Fields */ -#define CCM_PRE_ROOT48_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT48_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT48_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT48_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT48_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT48_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT48_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT48_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT48_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_SET_MUX_B_SHIFT))&CCM_PRE_ROOT48_SET_MUX_B_MASK) -#define CCM_PRE_ROOT48_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT48_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT48_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT48_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT48_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT48_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT48_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT48_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT48_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT48_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT48_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT48_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT48_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_SET_MUX_A_SHIFT))&CCM_PRE_ROOT48_SET_MUX_A_MASK) -#define CCM_PRE_ROOT48_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT48_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT48_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT48_SET_BUSY4_SHIFT 31 -/* PRE_ROOT48_CLR Bit Fields */ -#define CCM_PRE_ROOT48_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT48_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT48_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT48_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT48_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT48_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT48_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT48_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT48_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT48_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT48_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT48_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT48_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT48_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT48_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT48_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT48_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT48_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT48_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT48_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT48_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT48_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT48_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT48_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT48_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT48_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT48_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT48_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT48_TOG Bit Fields */ -#define CCM_PRE_ROOT48_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT48_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT48_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT48_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT48_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT48_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT48_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT48_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT48_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT48_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT48_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT48_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT48_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT48_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT48_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT48_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT48_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT48_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT48_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT48_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT48_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT48_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT48_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT48_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT48_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT48_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT48_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT48_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL48 Bit Fields */ -#define CCM_ACCESS_CTRL48_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL48_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL48_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL48_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL48_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL48_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL48_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL48_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL48_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL48_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL48_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL48_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL48_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL48_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL48_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL48_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL48_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL48_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL48_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL48_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL48_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL48_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL48_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL48_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL48_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL48_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL48_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL48_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL48_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL48_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL48_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL48_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL48_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL48_LOCK_SHIFT 31 -/* ACCESS_CTRL48_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL48_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL48_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL48_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL48_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL48_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL48_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL48_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL48_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL48_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL48_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL48_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL48_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL48_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL48_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL48_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL48_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT49 Bit Fields */ -#define CCM_TARGET_ROOT49_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT49_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT49_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_POST_PODF_SHIFT))&CCM_TARGET_ROOT49_POST_PODF_MASK) -#define CCM_TARGET_ROOT49_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT49_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT49_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT49_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT49_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT49_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT49_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT49_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT49_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT49_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT49_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_PRE_PODF_SHIFT))&CCM_TARGET_ROOT49_PRE_PODF_MASK) -#define CCM_TARGET_ROOT49_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT49_MUX_SHIFT 24 -#define CCM_TARGET_ROOT49_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_MUX_SHIFT))&CCM_TARGET_ROOT49_MUX_MASK) -#define CCM_TARGET_ROOT49_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT49_ENABLE_SHIFT 28 -/* TARGET_ROOT49_SET Bit Fields */ -#define CCM_TARGET_ROOT49_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT49_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT49_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT49_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT49_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT49_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT49_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT49_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT49_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT49_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT49_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT49_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT49_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT49_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT49_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT49_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT49_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT49_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT49_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_SET_MUX_SHIFT))&CCM_TARGET_ROOT49_SET_MUX_MASK) -#define CCM_TARGET_ROOT49_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT49_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT49_CLR Bit Fields */ -#define CCM_TARGET_ROOT49_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT49_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT49_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT49_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT49_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT49_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT49_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT49_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT49_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT49_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT49_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT49_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT49_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT49_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT49_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT49_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT49_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT49_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT49_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_CLR_MUX_SHIFT))&CCM_TARGET_ROOT49_CLR_MUX_MASK) -#define CCM_TARGET_ROOT49_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT49_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT49_TOG Bit Fields */ -#define CCM_TARGET_ROOT49_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT49_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT49_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT49_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT49_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT49_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT49_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT49_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT49_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT49_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT49_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT49_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT49_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT49_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT49_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT49_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT49_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT49_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT49_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_TOG_MUX_SHIFT))&CCM_TARGET_ROOT49_TOG_MUX_MASK) -#define CCM_TARGET_ROOT49_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT49_TOG_ENABLE_SHIFT 28 -/* POST49 Bit Fields */ -#define CCM_POST49_POST_PODF_MASK 0x3Fu -#define CCM_POST49_POST_PODF_SHIFT 0 -#define CCM_POST49_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST49_POST_PODF_SHIFT))&CCM_POST49_POST_PODF_MASK) -#define CCM_POST49_BUSY1_MASK 0x80u -#define CCM_POST49_BUSY1_SHIFT 7 -#define CCM_POST49_AUTO_PODF_MASK 0x700u -#define CCM_POST49_AUTO_PODF_SHIFT 8 -#define CCM_POST49_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST49_AUTO_PODF_SHIFT))&CCM_POST49_AUTO_PODF_MASK) -#define CCM_POST49_AUTO_EN_MASK 0x1000u -#define CCM_POST49_AUTO_EN_SHIFT 12 -#define CCM_POST49_SLOW_MASK 0x8000u -#define CCM_POST49_SLOW_SHIFT 15 -#define CCM_POST49_SELECT_MASK 0x10000000u -#define CCM_POST49_SELECT_SHIFT 28 -#define CCM_POST49_BUSY2_MASK 0x80000000u -#define CCM_POST49_BUSY2_SHIFT 31 -/* POST_ROOT49_SET Bit Fields */ -#define CCM_POST_ROOT49_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT49_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT49_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_SET_POST_PODF_SHIFT))&CCM_POST_ROOT49_SET_POST_PODF_MASK) -#define CCM_POST_ROOT49_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT49_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT49_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT49_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT49_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT49_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT49_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT49_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT49_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT49_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT49_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT49_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT49_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT49_SET_BUSY2_SHIFT 31 -/* POST_ROOT49_CLR Bit Fields */ -#define CCM_POST_ROOT49_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT49_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT49_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT49_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT49_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT49_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT49_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT49_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT49_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT49_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT49_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT49_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT49_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT49_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT49_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT49_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT49_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT49_CLR_BUSY2_SHIFT 31 -/* POST_ROOT49_TOG Bit Fields */ -#define CCM_POST_ROOT49_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT49_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT49_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT49_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT49_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT49_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT49_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT49_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT49_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT49_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT49_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT49_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT49_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT49_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT49_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT49_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT49_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT49_TOG_BUSY2_SHIFT 31 -/* PRE49 Bit Fields */ -#define CCM_PRE49_PRE_PODF_B_MASK 0x7u -#define CCM_PRE49_PRE_PODF_B_SHIFT 0 -#define CCM_PRE49_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE49_PRE_PODF_B_SHIFT))&CCM_PRE49_PRE_PODF_B_MASK) -#define CCM_PRE49_BUSY0_MASK 0x8u -#define CCM_PRE49_BUSY0_SHIFT 3 -#define CCM_PRE49_MUX_B_MASK 0x700u -#define CCM_PRE49_MUX_B_SHIFT 8 -#define CCM_PRE49_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE49_MUX_B_SHIFT))&CCM_PRE49_MUX_B_MASK) -#define CCM_PRE49_EN_B_MASK 0x1000u -#define CCM_PRE49_EN_B_SHIFT 12 -#define CCM_PRE49_BUSY1_MASK 0x8000u -#define CCM_PRE49_BUSY1_SHIFT 15 -#define CCM_PRE49_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE49_PRE_PODF_A_SHIFT 16 -#define CCM_PRE49_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE49_PRE_PODF_A_SHIFT))&CCM_PRE49_PRE_PODF_A_MASK) -#define CCM_PRE49_BUSY3_MASK 0x80000u -#define CCM_PRE49_BUSY3_SHIFT 19 -#define CCM_PRE49_MUX_A_MASK 0x7000000u -#define CCM_PRE49_MUX_A_SHIFT 24 -#define CCM_PRE49_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE49_MUX_A_SHIFT))&CCM_PRE49_MUX_A_MASK) -#define CCM_PRE49_EN_A_MASK 0x10000000u -#define CCM_PRE49_EN_A_SHIFT 28 -#define CCM_PRE49_BUSY4_MASK 0x80000000u -#define CCM_PRE49_BUSY4_SHIFT 31 -/* PRE_ROOT49_SET Bit Fields */ -#define CCM_PRE_ROOT49_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT49_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT49_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT49_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT49_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT49_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT49_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT49_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT49_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_SET_MUX_B_SHIFT))&CCM_PRE_ROOT49_SET_MUX_B_MASK) -#define CCM_PRE_ROOT49_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT49_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT49_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT49_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT49_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT49_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT49_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT49_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT49_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT49_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT49_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT49_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT49_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_SET_MUX_A_SHIFT))&CCM_PRE_ROOT49_SET_MUX_A_MASK) -#define CCM_PRE_ROOT49_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT49_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT49_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT49_SET_BUSY4_SHIFT 31 -/* PRE_ROOT49_CLR Bit Fields */ -#define CCM_PRE_ROOT49_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT49_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT49_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT49_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT49_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT49_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT49_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT49_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT49_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT49_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT49_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT49_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT49_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT49_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT49_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT49_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT49_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT49_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT49_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT49_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT49_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT49_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT49_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT49_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT49_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT49_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT49_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT49_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT49_TOG Bit Fields */ -#define CCM_PRE_ROOT49_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT49_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT49_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT49_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT49_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT49_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT49_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT49_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT49_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT49_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT49_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT49_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT49_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT49_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT49_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT49_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT49_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT49_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT49_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT49_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT49_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT49_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT49_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT49_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT49_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT49_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT49_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT49_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL49 Bit Fields */ -#define CCM_ACCESS_CTRL49_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL49_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL49_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL49_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL49_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL49_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL49_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL49_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL49_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL49_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL49_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL49_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL49_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL49_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL49_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL49_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL49_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL49_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL49_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL49_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL49_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL49_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL49_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL49_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL49_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL49_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL49_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL49_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL49_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL49_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL49_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL49_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL49_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL49_LOCK_SHIFT 31 -/* ACCESS_CTRL49_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL49_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL49_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL49_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL49_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL49_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL49_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL49_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL49_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL49_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL49_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL49_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL49_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL49_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL49_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL49_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL49_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT50 Bit Fields */ -#define CCM_TARGET_ROOT50_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT50_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT50_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_POST_PODF_SHIFT))&CCM_TARGET_ROOT50_POST_PODF_MASK) -#define CCM_TARGET_ROOT50_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT50_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT50_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT50_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT50_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT50_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT50_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT50_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT50_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT50_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT50_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_PRE_PODF_SHIFT))&CCM_TARGET_ROOT50_PRE_PODF_MASK) -#define CCM_TARGET_ROOT50_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT50_MUX_SHIFT 24 -#define CCM_TARGET_ROOT50_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_MUX_SHIFT))&CCM_TARGET_ROOT50_MUX_MASK) -#define CCM_TARGET_ROOT50_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT50_ENABLE_SHIFT 28 -/* TARGET_ROOT50_SET Bit Fields */ -#define CCM_TARGET_ROOT50_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT50_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT50_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT50_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT50_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT50_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT50_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT50_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT50_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT50_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT50_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT50_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT50_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT50_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT50_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT50_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT50_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT50_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT50_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_SET_MUX_SHIFT))&CCM_TARGET_ROOT50_SET_MUX_MASK) -#define CCM_TARGET_ROOT50_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT50_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT50_CLR Bit Fields */ -#define CCM_TARGET_ROOT50_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT50_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT50_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT50_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT50_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT50_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT50_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT50_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT50_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT50_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT50_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT50_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT50_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT50_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT50_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT50_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT50_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT50_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT50_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_CLR_MUX_SHIFT))&CCM_TARGET_ROOT50_CLR_MUX_MASK) -#define CCM_TARGET_ROOT50_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT50_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT50_TOG Bit Fields */ -#define CCM_TARGET_ROOT50_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT50_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT50_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT50_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT50_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT50_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT50_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT50_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT50_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT50_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT50_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT50_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT50_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT50_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT50_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT50_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT50_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT50_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT50_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_TOG_MUX_SHIFT))&CCM_TARGET_ROOT50_TOG_MUX_MASK) -#define CCM_TARGET_ROOT50_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT50_TOG_ENABLE_SHIFT 28 -/* POST50 Bit Fields */ -#define CCM_POST50_POST_PODF_MASK 0x3Fu -#define CCM_POST50_POST_PODF_SHIFT 0 -#define CCM_POST50_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST50_POST_PODF_SHIFT))&CCM_POST50_POST_PODF_MASK) -#define CCM_POST50_BUSY1_MASK 0x80u -#define CCM_POST50_BUSY1_SHIFT 7 -#define CCM_POST50_AUTO_PODF_MASK 0x700u -#define CCM_POST50_AUTO_PODF_SHIFT 8 -#define CCM_POST50_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST50_AUTO_PODF_SHIFT))&CCM_POST50_AUTO_PODF_MASK) -#define CCM_POST50_AUTO_EN_MASK 0x1000u -#define CCM_POST50_AUTO_EN_SHIFT 12 -#define CCM_POST50_SLOW_MASK 0x8000u -#define CCM_POST50_SLOW_SHIFT 15 -#define CCM_POST50_SELECT_MASK 0x10000000u -#define CCM_POST50_SELECT_SHIFT 28 -#define CCM_POST50_BUSY2_MASK 0x80000000u -#define CCM_POST50_BUSY2_SHIFT 31 -/* POST_ROOT50_SET Bit Fields */ -#define CCM_POST_ROOT50_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT50_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT50_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_SET_POST_PODF_SHIFT))&CCM_POST_ROOT50_SET_POST_PODF_MASK) -#define CCM_POST_ROOT50_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT50_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT50_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT50_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT50_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT50_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT50_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT50_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT50_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT50_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT50_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT50_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT50_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT50_SET_BUSY2_SHIFT 31 -/* POST_ROOT50_CLR Bit Fields */ -#define CCM_POST_ROOT50_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT50_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT50_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT50_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT50_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT50_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT50_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT50_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT50_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT50_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT50_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT50_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT50_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT50_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT50_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT50_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT50_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT50_CLR_BUSY2_SHIFT 31 -/* POST_ROOT50_TOG Bit Fields */ -#define CCM_POST_ROOT50_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT50_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT50_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT50_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT50_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT50_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT50_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT50_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT50_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT50_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT50_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT50_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT50_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT50_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT50_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT50_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT50_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT50_TOG_BUSY2_SHIFT 31 -/* PRE50 Bit Fields */ -#define CCM_PRE50_PRE_PODF_B_MASK 0x7u -#define CCM_PRE50_PRE_PODF_B_SHIFT 0 -#define CCM_PRE50_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE50_PRE_PODF_B_SHIFT))&CCM_PRE50_PRE_PODF_B_MASK) -#define CCM_PRE50_BUSY0_MASK 0x8u -#define CCM_PRE50_BUSY0_SHIFT 3 -#define CCM_PRE50_MUX_B_MASK 0x700u -#define CCM_PRE50_MUX_B_SHIFT 8 -#define CCM_PRE50_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE50_MUX_B_SHIFT))&CCM_PRE50_MUX_B_MASK) -#define CCM_PRE50_EN_B_MASK 0x1000u -#define CCM_PRE50_EN_B_SHIFT 12 -#define CCM_PRE50_BUSY1_MASK 0x8000u -#define CCM_PRE50_BUSY1_SHIFT 15 -#define CCM_PRE50_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE50_PRE_PODF_A_SHIFT 16 -#define CCM_PRE50_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE50_PRE_PODF_A_SHIFT))&CCM_PRE50_PRE_PODF_A_MASK) -#define CCM_PRE50_BUSY3_MASK 0x80000u -#define CCM_PRE50_BUSY3_SHIFT 19 -#define CCM_PRE50_MUX_A_MASK 0x7000000u -#define CCM_PRE50_MUX_A_SHIFT 24 -#define CCM_PRE50_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE50_MUX_A_SHIFT))&CCM_PRE50_MUX_A_MASK) -#define CCM_PRE50_EN_A_MASK 0x10000000u -#define CCM_PRE50_EN_A_SHIFT 28 -#define CCM_PRE50_BUSY4_MASK 0x80000000u -#define CCM_PRE50_BUSY4_SHIFT 31 -/* PRE_ROOT50_SET Bit Fields */ -#define CCM_PRE_ROOT50_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT50_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT50_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT50_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT50_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT50_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT50_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT50_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT50_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_SET_MUX_B_SHIFT))&CCM_PRE_ROOT50_SET_MUX_B_MASK) -#define CCM_PRE_ROOT50_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT50_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT50_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT50_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT50_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT50_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT50_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT50_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT50_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT50_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT50_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT50_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT50_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_SET_MUX_A_SHIFT))&CCM_PRE_ROOT50_SET_MUX_A_MASK) -#define CCM_PRE_ROOT50_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT50_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT50_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT50_SET_BUSY4_SHIFT 31 -/* PRE_ROOT50_CLR Bit Fields */ -#define CCM_PRE_ROOT50_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT50_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT50_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT50_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT50_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT50_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT50_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT50_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT50_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT50_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT50_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT50_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT50_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT50_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT50_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT50_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT50_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT50_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT50_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT50_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT50_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT50_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT50_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT50_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT50_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT50_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT50_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT50_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT50_TOG Bit Fields */ -#define CCM_PRE_ROOT50_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT50_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT50_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT50_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT50_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT50_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT50_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT50_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT50_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT50_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT50_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT50_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT50_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT50_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT50_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT50_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT50_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT50_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT50_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT50_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT50_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT50_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT50_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT50_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT50_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT50_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT50_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT50_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL50 Bit Fields */ -#define CCM_ACCESS_CTRL50_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL50_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL50_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL50_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL50_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL50_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL50_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL50_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL50_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL50_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL50_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL50_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL50_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL50_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL50_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL50_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL50_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL50_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL50_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL50_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL50_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL50_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL50_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL50_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL50_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL50_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL50_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL50_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL50_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL50_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL50_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL50_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL50_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL50_LOCK_SHIFT 31 -/* ACCESS_CTRL50_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL50_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL50_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL50_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL50_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL50_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL50_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL50_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL50_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL50_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL50_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL50_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL50_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL50_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL50_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL50_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL50_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT51 Bit Fields */ -#define CCM_TARGET_ROOT51_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT51_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT51_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_POST_PODF_SHIFT))&CCM_TARGET_ROOT51_POST_PODF_MASK) -#define CCM_TARGET_ROOT51_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT51_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT51_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT51_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT51_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT51_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT51_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT51_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT51_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT51_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT51_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_PRE_PODF_SHIFT))&CCM_TARGET_ROOT51_PRE_PODF_MASK) -#define CCM_TARGET_ROOT51_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT51_MUX_SHIFT 24 -#define CCM_TARGET_ROOT51_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_MUX_SHIFT))&CCM_TARGET_ROOT51_MUX_MASK) -#define CCM_TARGET_ROOT51_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT51_ENABLE_SHIFT 28 -/* TARGET_ROOT51_SET Bit Fields */ -#define CCM_TARGET_ROOT51_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT51_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT51_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT51_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT51_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT51_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT51_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT51_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT51_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT51_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT51_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT51_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT51_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT51_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT51_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT51_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT51_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT51_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT51_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_SET_MUX_SHIFT))&CCM_TARGET_ROOT51_SET_MUX_MASK) -#define CCM_TARGET_ROOT51_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT51_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT51_CLR Bit Fields */ -#define CCM_TARGET_ROOT51_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT51_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT51_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT51_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT51_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT51_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT51_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT51_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT51_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT51_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT51_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT51_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT51_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT51_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT51_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT51_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT51_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT51_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT51_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_CLR_MUX_SHIFT))&CCM_TARGET_ROOT51_CLR_MUX_MASK) -#define CCM_TARGET_ROOT51_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT51_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT51_TOG Bit Fields */ -#define CCM_TARGET_ROOT51_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT51_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT51_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT51_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT51_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT51_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT51_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT51_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT51_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT51_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT51_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT51_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT51_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT51_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT51_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT51_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT51_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT51_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT51_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_TOG_MUX_SHIFT))&CCM_TARGET_ROOT51_TOG_MUX_MASK) -#define CCM_TARGET_ROOT51_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT51_TOG_ENABLE_SHIFT 28 -/* POST51 Bit Fields */ -#define CCM_POST51_POST_PODF_MASK 0x3Fu -#define CCM_POST51_POST_PODF_SHIFT 0 -#define CCM_POST51_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST51_POST_PODF_SHIFT))&CCM_POST51_POST_PODF_MASK) -#define CCM_POST51_BUSY1_MASK 0x80u -#define CCM_POST51_BUSY1_SHIFT 7 -#define CCM_POST51_AUTO_PODF_MASK 0x700u -#define CCM_POST51_AUTO_PODF_SHIFT 8 -#define CCM_POST51_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST51_AUTO_PODF_SHIFT))&CCM_POST51_AUTO_PODF_MASK) -#define CCM_POST51_AUTO_EN_MASK 0x1000u -#define CCM_POST51_AUTO_EN_SHIFT 12 -#define CCM_POST51_SLOW_MASK 0x8000u -#define CCM_POST51_SLOW_SHIFT 15 -#define CCM_POST51_SELECT_MASK 0x10000000u -#define CCM_POST51_SELECT_SHIFT 28 -#define CCM_POST51_BUSY2_MASK 0x80000000u -#define CCM_POST51_BUSY2_SHIFT 31 -/* POST_ROOT51_SET Bit Fields */ -#define CCM_POST_ROOT51_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT51_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT51_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_SET_POST_PODF_SHIFT))&CCM_POST_ROOT51_SET_POST_PODF_MASK) -#define CCM_POST_ROOT51_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT51_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT51_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT51_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT51_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT51_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT51_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT51_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT51_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT51_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT51_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT51_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT51_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT51_SET_BUSY2_SHIFT 31 -/* POST_ROOT51_CLR Bit Fields */ -#define CCM_POST_ROOT51_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT51_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT51_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT51_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT51_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT51_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT51_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT51_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT51_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT51_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT51_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT51_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT51_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT51_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT51_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT51_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT51_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT51_CLR_BUSY2_SHIFT 31 -/* POST_ROOT51_TOG Bit Fields */ -#define CCM_POST_ROOT51_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT51_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT51_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT51_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT51_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT51_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT51_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT51_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT51_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT51_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT51_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT51_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT51_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT51_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT51_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT51_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT51_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT51_TOG_BUSY2_SHIFT 31 -/* PRE51 Bit Fields */ -#define CCM_PRE51_PRE_PODF_B_MASK 0x7u -#define CCM_PRE51_PRE_PODF_B_SHIFT 0 -#define CCM_PRE51_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE51_PRE_PODF_B_SHIFT))&CCM_PRE51_PRE_PODF_B_MASK) -#define CCM_PRE51_BUSY0_MASK 0x8u -#define CCM_PRE51_BUSY0_SHIFT 3 -#define CCM_PRE51_MUX_B_MASK 0x700u -#define CCM_PRE51_MUX_B_SHIFT 8 -#define CCM_PRE51_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE51_MUX_B_SHIFT))&CCM_PRE51_MUX_B_MASK) -#define CCM_PRE51_EN_B_MASK 0x1000u -#define CCM_PRE51_EN_B_SHIFT 12 -#define CCM_PRE51_BUSY1_MASK 0x8000u -#define CCM_PRE51_BUSY1_SHIFT 15 -#define CCM_PRE51_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE51_PRE_PODF_A_SHIFT 16 -#define CCM_PRE51_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE51_PRE_PODF_A_SHIFT))&CCM_PRE51_PRE_PODF_A_MASK) -#define CCM_PRE51_BUSY3_MASK 0x80000u -#define CCM_PRE51_BUSY3_SHIFT 19 -#define CCM_PRE51_MUX_A_MASK 0x7000000u -#define CCM_PRE51_MUX_A_SHIFT 24 -#define CCM_PRE51_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE51_MUX_A_SHIFT))&CCM_PRE51_MUX_A_MASK) -#define CCM_PRE51_EN_A_MASK 0x10000000u -#define CCM_PRE51_EN_A_SHIFT 28 -#define CCM_PRE51_BUSY4_MASK 0x80000000u -#define CCM_PRE51_BUSY4_SHIFT 31 -/* PRE_ROOT51_SET Bit Fields */ -#define CCM_PRE_ROOT51_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT51_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT51_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT51_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT51_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT51_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT51_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT51_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT51_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_SET_MUX_B_SHIFT))&CCM_PRE_ROOT51_SET_MUX_B_MASK) -#define CCM_PRE_ROOT51_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT51_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT51_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT51_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT51_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT51_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT51_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT51_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT51_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT51_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT51_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT51_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT51_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_SET_MUX_A_SHIFT))&CCM_PRE_ROOT51_SET_MUX_A_MASK) -#define CCM_PRE_ROOT51_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT51_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT51_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT51_SET_BUSY4_SHIFT 31 -/* PRE_ROOT51_CLR Bit Fields */ -#define CCM_PRE_ROOT51_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT51_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT51_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT51_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT51_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT51_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT51_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT51_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT51_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT51_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT51_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT51_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT51_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT51_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT51_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT51_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT51_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT51_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT51_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT51_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT51_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT51_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT51_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT51_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT51_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT51_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT51_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT51_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT51_TOG Bit Fields */ -#define CCM_PRE_ROOT51_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT51_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT51_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT51_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT51_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT51_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT51_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT51_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT51_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT51_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT51_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT51_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT51_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT51_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT51_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT51_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT51_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT51_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT51_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT51_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT51_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT51_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT51_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT51_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT51_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT51_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT51_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT51_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL51 Bit Fields */ -#define CCM_ACCESS_CTRL51_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL51_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL51_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL51_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL51_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL51_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL51_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL51_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL51_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL51_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL51_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL51_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL51_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL51_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL51_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL51_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL51_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL51_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL51_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL51_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL51_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL51_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL51_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL51_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL51_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL51_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL51_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL51_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL51_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL51_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL51_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL51_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL51_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL51_LOCK_SHIFT 31 -/* ACCESS_CTRL51_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL51_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL51_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL51_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL51_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL51_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL51_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL51_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL51_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL51_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL51_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL51_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL51_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL51_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL51_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL51_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL51_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT52 Bit Fields */ -#define CCM_TARGET_ROOT52_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT52_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT52_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_POST_PODF_SHIFT))&CCM_TARGET_ROOT52_POST_PODF_MASK) -#define CCM_TARGET_ROOT52_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT52_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT52_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT52_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT52_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT52_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT52_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT52_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT52_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT52_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT52_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_PRE_PODF_SHIFT))&CCM_TARGET_ROOT52_PRE_PODF_MASK) -#define CCM_TARGET_ROOT52_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT52_MUX_SHIFT 24 -#define CCM_TARGET_ROOT52_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_MUX_SHIFT))&CCM_TARGET_ROOT52_MUX_MASK) -#define CCM_TARGET_ROOT52_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT52_ENABLE_SHIFT 28 -/* TARGET_ROOT52_SET Bit Fields */ -#define CCM_TARGET_ROOT52_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT52_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT52_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT52_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT52_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT52_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT52_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT52_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT52_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT52_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT52_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT52_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT52_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT52_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT52_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT52_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT52_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT52_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT52_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_SET_MUX_SHIFT))&CCM_TARGET_ROOT52_SET_MUX_MASK) -#define CCM_TARGET_ROOT52_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT52_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT52_CLR Bit Fields */ -#define CCM_TARGET_ROOT52_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT52_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT52_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT52_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT52_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT52_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT52_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT52_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT52_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT52_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT52_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT52_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT52_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT52_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT52_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT52_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT52_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT52_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT52_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_CLR_MUX_SHIFT))&CCM_TARGET_ROOT52_CLR_MUX_MASK) -#define CCM_TARGET_ROOT52_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT52_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT52_TOG Bit Fields */ -#define CCM_TARGET_ROOT52_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT52_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT52_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT52_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT52_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT52_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT52_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT52_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT52_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT52_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT52_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT52_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT52_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT52_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT52_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT52_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT52_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT52_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT52_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_TOG_MUX_SHIFT))&CCM_TARGET_ROOT52_TOG_MUX_MASK) -#define CCM_TARGET_ROOT52_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT52_TOG_ENABLE_SHIFT 28 -/* POST52 Bit Fields */ -#define CCM_POST52_POST_PODF_MASK 0x3Fu -#define CCM_POST52_POST_PODF_SHIFT 0 -#define CCM_POST52_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST52_POST_PODF_SHIFT))&CCM_POST52_POST_PODF_MASK) -#define CCM_POST52_BUSY1_MASK 0x80u -#define CCM_POST52_BUSY1_SHIFT 7 -#define CCM_POST52_AUTO_PODF_MASK 0x700u -#define CCM_POST52_AUTO_PODF_SHIFT 8 -#define CCM_POST52_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST52_AUTO_PODF_SHIFT))&CCM_POST52_AUTO_PODF_MASK) -#define CCM_POST52_AUTO_EN_MASK 0x1000u -#define CCM_POST52_AUTO_EN_SHIFT 12 -#define CCM_POST52_SLOW_MASK 0x8000u -#define CCM_POST52_SLOW_SHIFT 15 -#define CCM_POST52_SELECT_MASK 0x10000000u -#define CCM_POST52_SELECT_SHIFT 28 -#define CCM_POST52_BUSY2_MASK 0x80000000u -#define CCM_POST52_BUSY2_SHIFT 31 -/* POST_ROOT52_SET Bit Fields */ -#define CCM_POST_ROOT52_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT52_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT52_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_SET_POST_PODF_SHIFT))&CCM_POST_ROOT52_SET_POST_PODF_MASK) -#define CCM_POST_ROOT52_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT52_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT52_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT52_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT52_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT52_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT52_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT52_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT52_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT52_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT52_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT52_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT52_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT52_SET_BUSY2_SHIFT 31 -/* POST_ROOT52_CLR Bit Fields */ -#define CCM_POST_ROOT52_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT52_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT52_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT52_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT52_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT52_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT52_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT52_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT52_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT52_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT52_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT52_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT52_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT52_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT52_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT52_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT52_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT52_CLR_BUSY2_SHIFT 31 -/* POST_ROOT52_TOG Bit Fields */ -#define CCM_POST_ROOT52_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT52_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT52_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT52_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT52_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT52_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT52_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT52_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT52_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT52_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT52_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT52_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT52_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT52_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT52_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT52_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT52_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT52_TOG_BUSY2_SHIFT 31 -/* PRE52 Bit Fields */ -#define CCM_PRE52_PRE_PODF_B_MASK 0x7u -#define CCM_PRE52_PRE_PODF_B_SHIFT 0 -#define CCM_PRE52_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE52_PRE_PODF_B_SHIFT))&CCM_PRE52_PRE_PODF_B_MASK) -#define CCM_PRE52_BUSY0_MASK 0x8u -#define CCM_PRE52_BUSY0_SHIFT 3 -#define CCM_PRE52_MUX_B_MASK 0x700u -#define CCM_PRE52_MUX_B_SHIFT 8 -#define CCM_PRE52_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE52_MUX_B_SHIFT))&CCM_PRE52_MUX_B_MASK) -#define CCM_PRE52_EN_B_MASK 0x1000u -#define CCM_PRE52_EN_B_SHIFT 12 -#define CCM_PRE52_BUSY1_MASK 0x8000u -#define CCM_PRE52_BUSY1_SHIFT 15 -#define CCM_PRE52_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE52_PRE_PODF_A_SHIFT 16 -#define CCM_PRE52_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE52_PRE_PODF_A_SHIFT))&CCM_PRE52_PRE_PODF_A_MASK) -#define CCM_PRE52_BUSY3_MASK 0x80000u -#define CCM_PRE52_BUSY3_SHIFT 19 -#define CCM_PRE52_MUX_A_MASK 0x7000000u -#define CCM_PRE52_MUX_A_SHIFT 24 -#define CCM_PRE52_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE52_MUX_A_SHIFT))&CCM_PRE52_MUX_A_MASK) -#define CCM_PRE52_EN_A_MASK 0x10000000u -#define CCM_PRE52_EN_A_SHIFT 28 -#define CCM_PRE52_BUSY4_MASK 0x80000000u -#define CCM_PRE52_BUSY4_SHIFT 31 -/* PRE_ROOT52_SET Bit Fields */ -#define CCM_PRE_ROOT52_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT52_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT52_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT52_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT52_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT52_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT52_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT52_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT52_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_SET_MUX_B_SHIFT))&CCM_PRE_ROOT52_SET_MUX_B_MASK) -#define CCM_PRE_ROOT52_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT52_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT52_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT52_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT52_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT52_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT52_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT52_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT52_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT52_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT52_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT52_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT52_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_SET_MUX_A_SHIFT))&CCM_PRE_ROOT52_SET_MUX_A_MASK) -#define CCM_PRE_ROOT52_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT52_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT52_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT52_SET_BUSY4_SHIFT 31 -/* PRE_ROOT52_CLR Bit Fields */ -#define CCM_PRE_ROOT52_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT52_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT52_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT52_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT52_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT52_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT52_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT52_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT52_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT52_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT52_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT52_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT52_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT52_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT52_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT52_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT52_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT52_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT52_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT52_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT52_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT52_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT52_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT52_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT52_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT52_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT52_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT52_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT52_TOG Bit Fields */ -#define CCM_PRE_ROOT52_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT52_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT52_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT52_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT52_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT52_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT52_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT52_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT52_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT52_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT52_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT52_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT52_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT52_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT52_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT52_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT52_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT52_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT52_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT52_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT52_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT52_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT52_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT52_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT52_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT52_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT52_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT52_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL52 Bit Fields */ -#define CCM_ACCESS_CTRL52_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL52_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL52_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL52_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL52_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL52_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL52_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL52_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL52_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL52_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL52_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL52_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL52_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL52_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL52_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL52_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL52_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL52_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL52_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL52_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL52_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL52_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL52_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL52_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL52_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL52_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL52_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL52_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL52_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL52_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL52_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL52_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL52_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL52_LOCK_SHIFT 31 -/* ACCESS_CTRL52_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL52_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL52_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL52_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL52_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL52_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL52_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL52_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL52_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL52_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL52_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL52_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL52_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL52_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL52_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL52_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL52_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT53 Bit Fields */ -#define CCM_TARGET_ROOT53_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT53_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT53_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_POST_PODF_SHIFT))&CCM_TARGET_ROOT53_POST_PODF_MASK) -#define CCM_TARGET_ROOT53_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT53_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT53_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT53_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT53_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT53_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT53_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT53_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT53_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT53_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT53_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_PRE_PODF_SHIFT))&CCM_TARGET_ROOT53_PRE_PODF_MASK) -#define CCM_TARGET_ROOT53_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT53_MUX_SHIFT 24 -#define CCM_TARGET_ROOT53_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_MUX_SHIFT))&CCM_TARGET_ROOT53_MUX_MASK) -#define CCM_TARGET_ROOT53_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT53_ENABLE_SHIFT 28 -/* TARGET_ROOT53_SET Bit Fields */ -#define CCM_TARGET_ROOT53_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT53_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT53_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT53_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT53_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT53_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT53_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT53_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT53_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT53_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT53_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT53_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT53_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT53_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT53_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT53_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT53_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT53_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT53_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_SET_MUX_SHIFT))&CCM_TARGET_ROOT53_SET_MUX_MASK) -#define CCM_TARGET_ROOT53_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT53_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT53_CLR Bit Fields */ -#define CCM_TARGET_ROOT53_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT53_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT53_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT53_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT53_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT53_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT53_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT53_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT53_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT53_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT53_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT53_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT53_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT53_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT53_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT53_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT53_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT53_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT53_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_CLR_MUX_SHIFT))&CCM_TARGET_ROOT53_CLR_MUX_MASK) -#define CCM_TARGET_ROOT53_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT53_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT53_TOG Bit Fields */ -#define CCM_TARGET_ROOT53_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT53_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT53_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT53_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT53_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT53_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT53_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT53_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT53_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT53_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT53_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT53_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT53_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT53_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT53_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT53_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT53_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT53_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT53_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_TOG_MUX_SHIFT))&CCM_TARGET_ROOT53_TOG_MUX_MASK) -#define CCM_TARGET_ROOT53_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT53_TOG_ENABLE_SHIFT 28 -/* POST53 Bit Fields */ -#define CCM_POST53_POST_PODF_MASK 0x3Fu -#define CCM_POST53_POST_PODF_SHIFT 0 -#define CCM_POST53_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST53_POST_PODF_SHIFT))&CCM_POST53_POST_PODF_MASK) -#define CCM_POST53_BUSY1_MASK 0x80u -#define CCM_POST53_BUSY1_SHIFT 7 -#define CCM_POST53_AUTO_PODF_MASK 0x700u -#define CCM_POST53_AUTO_PODF_SHIFT 8 -#define CCM_POST53_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST53_AUTO_PODF_SHIFT))&CCM_POST53_AUTO_PODF_MASK) -#define CCM_POST53_AUTO_EN_MASK 0x1000u -#define CCM_POST53_AUTO_EN_SHIFT 12 -#define CCM_POST53_SLOW_MASK 0x8000u -#define CCM_POST53_SLOW_SHIFT 15 -#define CCM_POST53_SELECT_MASK 0x10000000u -#define CCM_POST53_SELECT_SHIFT 28 -#define CCM_POST53_BUSY2_MASK 0x80000000u -#define CCM_POST53_BUSY2_SHIFT 31 -/* POST_ROOT53_SET Bit Fields */ -#define CCM_POST_ROOT53_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT53_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT53_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_SET_POST_PODF_SHIFT))&CCM_POST_ROOT53_SET_POST_PODF_MASK) -#define CCM_POST_ROOT53_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT53_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT53_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT53_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT53_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT53_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT53_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT53_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT53_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT53_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT53_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT53_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT53_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT53_SET_BUSY2_SHIFT 31 -/* POST_ROOT53_CLR Bit Fields */ -#define CCM_POST_ROOT53_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT53_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT53_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT53_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT53_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT53_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT53_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT53_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT53_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT53_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT53_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT53_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT53_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT53_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT53_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT53_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT53_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT53_CLR_BUSY2_SHIFT 31 -/* POST_ROOT53_TOG Bit Fields */ -#define CCM_POST_ROOT53_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT53_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT53_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT53_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT53_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT53_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT53_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT53_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT53_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT53_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT53_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT53_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT53_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT53_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT53_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT53_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT53_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT53_TOG_BUSY2_SHIFT 31 -/* PRE53 Bit Fields */ -#define CCM_PRE53_PRE_PODF_B_MASK 0x7u -#define CCM_PRE53_PRE_PODF_B_SHIFT 0 -#define CCM_PRE53_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE53_PRE_PODF_B_SHIFT))&CCM_PRE53_PRE_PODF_B_MASK) -#define CCM_PRE53_BUSY0_MASK 0x8u -#define CCM_PRE53_BUSY0_SHIFT 3 -#define CCM_PRE53_MUX_B_MASK 0x700u -#define CCM_PRE53_MUX_B_SHIFT 8 -#define CCM_PRE53_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE53_MUX_B_SHIFT))&CCM_PRE53_MUX_B_MASK) -#define CCM_PRE53_EN_B_MASK 0x1000u -#define CCM_PRE53_EN_B_SHIFT 12 -#define CCM_PRE53_BUSY1_MASK 0x8000u -#define CCM_PRE53_BUSY1_SHIFT 15 -#define CCM_PRE53_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE53_PRE_PODF_A_SHIFT 16 -#define CCM_PRE53_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE53_PRE_PODF_A_SHIFT))&CCM_PRE53_PRE_PODF_A_MASK) -#define CCM_PRE53_BUSY3_MASK 0x80000u -#define CCM_PRE53_BUSY3_SHIFT 19 -#define CCM_PRE53_MUX_A_MASK 0x7000000u -#define CCM_PRE53_MUX_A_SHIFT 24 -#define CCM_PRE53_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE53_MUX_A_SHIFT))&CCM_PRE53_MUX_A_MASK) -#define CCM_PRE53_EN_A_MASK 0x10000000u -#define CCM_PRE53_EN_A_SHIFT 28 -#define CCM_PRE53_BUSY4_MASK 0x80000000u -#define CCM_PRE53_BUSY4_SHIFT 31 -/* PRE_ROOT53_SET Bit Fields */ -#define CCM_PRE_ROOT53_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT53_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT53_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT53_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT53_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT53_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT53_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT53_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT53_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_SET_MUX_B_SHIFT))&CCM_PRE_ROOT53_SET_MUX_B_MASK) -#define CCM_PRE_ROOT53_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT53_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT53_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT53_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT53_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT53_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT53_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT53_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT53_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT53_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT53_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT53_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT53_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_SET_MUX_A_SHIFT))&CCM_PRE_ROOT53_SET_MUX_A_MASK) -#define CCM_PRE_ROOT53_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT53_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT53_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT53_SET_BUSY4_SHIFT 31 -/* PRE_ROOT53_CLR Bit Fields */ -#define CCM_PRE_ROOT53_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT53_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT53_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT53_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT53_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT53_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT53_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT53_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT53_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT53_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT53_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT53_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT53_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT53_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT53_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT53_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT53_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT53_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT53_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT53_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT53_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT53_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT53_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT53_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT53_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT53_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT53_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT53_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT53_TOG Bit Fields */ -#define CCM_PRE_ROOT53_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT53_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT53_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT53_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT53_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT53_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT53_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT53_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT53_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT53_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT53_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT53_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT53_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT53_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT53_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT53_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT53_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT53_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT53_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT53_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT53_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT53_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT53_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT53_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT53_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT53_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT53_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT53_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL53 Bit Fields */ -#define CCM_ACCESS_CTRL53_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL53_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL53_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL53_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL53_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL53_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL53_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL53_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL53_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL53_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL53_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL53_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL53_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL53_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL53_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL53_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL53_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL53_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL53_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL53_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL53_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL53_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL53_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL53_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL53_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL53_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL53_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL53_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL53_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL53_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL53_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL53_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL53_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL53_LOCK_SHIFT 31 -/* ACCESS_CTRL53_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL53_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL53_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL53_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL53_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL53_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL53_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL53_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL53_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL53_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL53_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL53_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL53_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL53_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL53_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL53_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL53_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT54 Bit Fields */ -#define CCM_TARGET_ROOT54_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT54_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT54_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_POST_PODF_SHIFT))&CCM_TARGET_ROOT54_POST_PODF_MASK) -#define CCM_TARGET_ROOT54_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT54_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT54_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT54_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT54_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT54_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT54_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT54_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT54_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT54_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT54_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_PRE_PODF_SHIFT))&CCM_TARGET_ROOT54_PRE_PODF_MASK) -#define CCM_TARGET_ROOT54_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT54_MUX_SHIFT 24 -#define CCM_TARGET_ROOT54_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_MUX_SHIFT))&CCM_TARGET_ROOT54_MUX_MASK) -#define CCM_TARGET_ROOT54_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT54_ENABLE_SHIFT 28 -/* TARGET_ROOT54_SET Bit Fields */ -#define CCM_TARGET_ROOT54_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT54_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT54_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT54_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT54_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT54_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT54_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT54_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT54_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT54_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT54_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT54_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT54_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT54_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT54_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT54_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT54_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT54_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT54_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_SET_MUX_SHIFT))&CCM_TARGET_ROOT54_SET_MUX_MASK) -#define CCM_TARGET_ROOT54_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT54_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT54_CLR Bit Fields */ -#define CCM_TARGET_ROOT54_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT54_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT54_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT54_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT54_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT54_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT54_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT54_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT54_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT54_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT54_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT54_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT54_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT54_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT54_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT54_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT54_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT54_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT54_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_CLR_MUX_SHIFT))&CCM_TARGET_ROOT54_CLR_MUX_MASK) -#define CCM_TARGET_ROOT54_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT54_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT54_TOG Bit Fields */ -#define CCM_TARGET_ROOT54_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT54_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT54_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT54_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT54_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT54_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT54_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT54_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT54_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT54_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT54_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT54_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT54_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT54_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT54_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT54_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT54_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT54_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT54_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_TOG_MUX_SHIFT))&CCM_TARGET_ROOT54_TOG_MUX_MASK) -#define CCM_TARGET_ROOT54_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT54_TOG_ENABLE_SHIFT 28 -/* POST54 Bit Fields */ -#define CCM_POST54_POST_PODF_MASK 0x3Fu -#define CCM_POST54_POST_PODF_SHIFT 0 -#define CCM_POST54_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST54_POST_PODF_SHIFT))&CCM_POST54_POST_PODF_MASK) -#define CCM_POST54_BUSY1_MASK 0x80u -#define CCM_POST54_BUSY1_SHIFT 7 -#define CCM_POST54_AUTO_PODF_MASK 0x700u -#define CCM_POST54_AUTO_PODF_SHIFT 8 -#define CCM_POST54_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST54_AUTO_PODF_SHIFT))&CCM_POST54_AUTO_PODF_MASK) -#define CCM_POST54_AUTO_EN_MASK 0x1000u -#define CCM_POST54_AUTO_EN_SHIFT 12 -#define CCM_POST54_SLOW_MASK 0x8000u -#define CCM_POST54_SLOW_SHIFT 15 -#define CCM_POST54_SELECT_MASK 0x10000000u -#define CCM_POST54_SELECT_SHIFT 28 -#define CCM_POST54_BUSY2_MASK 0x80000000u -#define CCM_POST54_BUSY2_SHIFT 31 -/* POST_ROOT54_SET Bit Fields */ -#define CCM_POST_ROOT54_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT54_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT54_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_SET_POST_PODF_SHIFT))&CCM_POST_ROOT54_SET_POST_PODF_MASK) -#define CCM_POST_ROOT54_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT54_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT54_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT54_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT54_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT54_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT54_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT54_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT54_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT54_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT54_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT54_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT54_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT54_SET_BUSY2_SHIFT 31 -/* POST_ROOT54_CLR Bit Fields */ -#define CCM_POST_ROOT54_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT54_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT54_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT54_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT54_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT54_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT54_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT54_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT54_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT54_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT54_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT54_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT54_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT54_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT54_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT54_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT54_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT54_CLR_BUSY2_SHIFT 31 -/* POST_ROOT54_TOG Bit Fields */ -#define CCM_POST_ROOT54_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT54_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT54_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT54_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT54_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT54_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT54_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT54_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT54_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT54_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT54_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT54_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT54_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT54_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT54_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT54_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT54_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT54_TOG_BUSY2_SHIFT 31 -/* PRE54 Bit Fields */ -#define CCM_PRE54_PRE_PODF_B_MASK 0x7u -#define CCM_PRE54_PRE_PODF_B_SHIFT 0 -#define CCM_PRE54_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE54_PRE_PODF_B_SHIFT))&CCM_PRE54_PRE_PODF_B_MASK) -#define CCM_PRE54_BUSY0_MASK 0x8u -#define CCM_PRE54_BUSY0_SHIFT 3 -#define CCM_PRE54_MUX_B_MASK 0x700u -#define CCM_PRE54_MUX_B_SHIFT 8 -#define CCM_PRE54_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE54_MUX_B_SHIFT))&CCM_PRE54_MUX_B_MASK) -#define CCM_PRE54_EN_B_MASK 0x1000u -#define CCM_PRE54_EN_B_SHIFT 12 -#define CCM_PRE54_BUSY1_MASK 0x8000u -#define CCM_PRE54_BUSY1_SHIFT 15 -#define CCM_PRE54_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE54_PRE_PODF_A_SHIFT 16 -#define CCM_PRE54_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE54_PRE_PODF_A_SHIFT))&CCM_PRE54_PRE_PODF_A_MASK) -#define CCM_PRE54_BUSY3_MASK 0x80000u -#define CCM_PRE54_BUSY3_SHIFT 19 -#define CCM_PRE54_MUX_A_MASK 0x7000000u -#define CCM_PRE54_MUX_A_SHIFT 24 -#define CCM_PRE54_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE54_MUX_A_SHIFT))&CCM_PRE54_MUX_A_MASK) -#define CCM_PRE54_EN_A_MASK 0x10000000u -#define CCM_PRE54_EN_A_SHIFT 28 -#define CCM_PRE54_BUSY4_MASK 0x80000000u -#define CCM_PRE54_BUSY4_SHIFT 31 -/* PRE_ROOT54_SET Bit Fields */ -#define CCM_PRE_ROOT54_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT54_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT54_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT54_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT54_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT54_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT54_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT54_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT54_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_SET_MUX_B_SHIFT))&CCM_PRE_ROOT54_SET_MUX_B_MASK) -#define CCM_PRE_ROOT54_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT54_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT54_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT54_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT54_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT54_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT54_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT54_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT54_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT54_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT54_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT54_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT54_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_SET_MUX_A_SHIFT))&CCM_PRE_ROOT54_SET_MUX_A_MASK) -#define CCM_PRE_ROOT54_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT54_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT54_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT54_SET_BUSY4_SHIFT 31 -/* PRE_ROOT54_CLR Bit Fields */ -#define CCM_PRE_ROOT54_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT54_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT54_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT54_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT54_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT54_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT54_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT54_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT54_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT54_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT54_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT54_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT54_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT54_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT54_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT54_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT54_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT54_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT54_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT54_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT54_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT54_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT54_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT54_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT54_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT54_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT54_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT54_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT54_TOG Bit Fields */ -#define CCM_PRE_ROOT54_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT54_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT54_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT54_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT54_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT54_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT54_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT54_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT54_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT54_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT54_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT54_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT54_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT54_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT54_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT54_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT54_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT54_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT54_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT54_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT54_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT54_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT54_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT54_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT54_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT54_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT54_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT54_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL54 Bit Fields */ -#define CCM_ACCESS_CTRL54_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL54_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL54_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL54_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL54_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL54_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL54_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL54_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL54_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL54_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL54_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL54_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL54_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL54_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL54_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL54_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL54_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL54_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL54_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL54_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL54_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL54_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL54_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL54_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL54_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL54_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL54_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL54_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL54_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL54_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL54_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL54_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL54_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL54_LOCK_SHIFT 31 -/* ACCESS_CTRL54_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL54_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL54_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL54_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL54_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL54_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL54_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL54_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL54_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL54_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL54_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL54_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL54_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL54_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL54_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL54_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL54_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT55 Bit Fields */ -#define CCM_TARGET_ROOT55_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT55_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT55_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_POST_PODF_SHIFT))&CCM_TARGET_ROOT55_POST_PODF_MASK) -#define CCM_TARGET_ROOT55_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT55_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT55_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT55_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT55_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT55_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT55_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT55_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT55_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT55_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT55_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_PRE_PODF_SHIFT))&CCM_TARGET_ROOT55_PRE_PODF_MASK) -#define CCM_TARGET_ROOT55_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT55_MUX_SHIFT 24 -#define CCM_TARGET_ROOT55_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_MUX_SHIFT))&CCM_TARGET_ROOT55_MUX_MASK) -#define CCM_TARGET_ROOT55_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT55_ENABLE_SHIFT 28 -/* TARGET_ROOT55_SET Bit Fields */ -#define CCM_TARGET_ROOT55_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT55_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT55_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT55_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT55_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT55_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT55_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT55_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT55_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT55_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT55_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT55_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT55_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT55_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT55_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT55_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT55_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT55_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT55_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_SET_MUX_SHIFT))&CCM_TARGET_ROOT55_SET_MUX_MASK) -#define CCM_TARGET_ROOT55_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT55_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT55_CLR Bit Fields */ -#define CCM_TARGET_ROOT55_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT55_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT55_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT55_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT55_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT55_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT55_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT55_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT55_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT55_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT55_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT55_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT55_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT55_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT55_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT55_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT55_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT55_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT55_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_CLR_MUX_SHIFT))&CCM_TARGET_ROOT55_CLR_MUX_MASK) -#define CCM_TARGET_ROOT55_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT55_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT55_TOG Bit Fields */ -#define CCM_TARGET_ROOT55_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT55_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT55_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT55_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT55_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT55_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT55_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT55_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT55_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT55_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT55_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT55_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT55_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT55_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT55_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT55_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT55_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT55_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT55_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_TOG_MUX_SHIFT))&CCM_TARGET_ROOT55_TOG_MUX_MASK) -#define CCM_TARGET_ROOT55_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT55_TOG_ENABLE_SHIFT 28 -/* POST55 Bit Fields */ -#define CCM_POST55_POST_PODF_MASK 0x3Fu -#define CCM_POST55_POST_PODF_SHIFT 0 -#define CCM_POST55_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST55_POST_PODF_SHIFT))&CCM_POST55_POST_PODF_MASK) -#define CCM_POST55_BUSY1_MASK 0x80u -#define CCM_POST55_BUSY1_SHIFT 7 -#define CCM_POST55_AUTO_PODF_MASK 0x700u -#define CCM_POST55_AUTO_PODF_SHIFT 8 -#define CCM_POST55_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST55_AUTO_PODF_SHIFT))&CCM_POST55_AUTO_PODF_MASK) -#define CCM_POST55_AUTO_EN_MASK 0x1000u -#define CCM_POST55_AUTO_EN_SHIFT 12 -#define CCM_POST55_SLOW_MASK 0x8000u -#define CCM_POST55_SLOW_SHIFT 15 -#define CCM_POST55_SELECT_MASK 0x10000000u -#define CCM_POST55_SELECT_SHIFT 28 -#define CCM_POST55_BUSY2_MASK 0x80000000u -#define CCM_POST55_BUSY2_SHIFT 31 -/* POST_ROOT55_SET Bit Fields */ -#define CCM_POST_ROOT55_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT55_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT55_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_SET_POST_PODF_SHIFT))&CCM_POST_ROOT55_SET_POST_PODF_MASK) -#define CCM_POST_ROOT55_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT55_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT55_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT55_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT55_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT55_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT55_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT55_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT55_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT55_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT55_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT55_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT55_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT55_SET_BUSY2_SHIFT 31 -/* POST_ROOT55_CLR Bit Fields */ -#define CCM_POST_ROOT55_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT55_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT55_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT55_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT55_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT55_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT55_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT55_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT55_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT55_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT55_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT55_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT55_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT55_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT55_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT55_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT55_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT55_CLR_BUSY2_SHIFT 31 -/* POST_ROOT55_TOG Bit Fields */ -#define CCM_POST_ROOT55_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT55_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT55_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT55_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT55_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT55_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT55_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT55_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT55_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT55_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT55_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT55_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT55_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT55_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT55_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT55_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT55_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT55_TOG_BUSY2_SHIFT 31 -/* PRE55 Bit Fields */ -#define CCM_PRE55_PRE_PODF_B_MASK 0x7u -#define CCM_PRE55_PRE_PODF_B_SHIFT 0 -#define CCM_PRE55_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE55_PRE_PODF_B_SHIFT))&CCM_PRE55_PRE_PODF_B_MASK) -#define CCM_PRE55_BUSY0_MASK 0x8u -#define CCM_PRE55_BUSY0_SHIFT 3 -#define CCM_PRE55_MUX_B_MASK 0x700u -#define CCM_PRE55_MUX_B_SHIFT 8 -#define CCM_PRE55_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE55_MUX_B_SHIFT))&CCM_PRE55_MUX_B_MASK) -#define CCM_PRE55_EN_B_MASK 0x1000u -#define CCM_PRE55_EN_B_SHIFT 12 -#define CCM_PRE55_BUSY1_MASK 0x8000u -#define CCM_PRE55_BUSY1_SHIFT 15 -#define CCM_PRE55_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE55_PRE_PODF_A_SHIFT 16 -#define CCM_PRE55_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE55_PRE_PODF_A_SHIFT))&CCM_PRE55_PRE_PODF_A_MASK) -#define CCM_PRE55_BUSY3_MASK 0x80000u -#define CCM_PRE55_BUSY3_SHIFT 19 -#define CCM_PRE55_MUX_A_MASK 0x7000000u -#define CCM_PRE55_MUX_A_SHIFT 24 -#define CCM_PRE55_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE55_MUX_A_SHIFT))&CCM_PRE55_MUX_A_MASK) -#define CCM_PRE55_EN_A_MASK 0x10000000u -#define CCM_PRE55_EN_A_SHIFT 28 -#define CCM_PRE55_BUSY4_MASK 0x80000000u -#define CCM_PRE55_BUSY4_SHIFT 31 -/* PRE_ROOT55_SET Bit Fields */ -#define CCM_PRE_ROOT55_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT55_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT55_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT55_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT55_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT55_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT55_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT55_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT55_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_SET_MUX_B_SHIFT))&CCM_PRE_ROOT55_SET_MUX_B_MASK) -#define CCM_PRE_ROOT55_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT55_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT55_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT55_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT55_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT55_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT55_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT55_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT55_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT55_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT55_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT55_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT55_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_SET_MUX_A_SHIFT))&CCM_PRE_ROOT55_SET_MUX_A_MASK) -#define CCM_PRE_ROOT55_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT55_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT55_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT55_SET_BUSY4_SHIFT 31 -/* PRE_ROOT55_CLR Bit Fields */ -#define CCM_PRE_ROOT55_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT55_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT55_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT55_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT55_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT55_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT55_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT55_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT55_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT55_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT55_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT55_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT55_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT55_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT55_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT55_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT55_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT55_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT55_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT55_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT55_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT55_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT55_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT55_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT55_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT55_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT55_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT55_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT55_TOG Bit Fields */ -#define CCM_PRE_ROOT55_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT55_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT55_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT55_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT55_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT55_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT55_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT55_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT55_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT55_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT55_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT55_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT55_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT55_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT55_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT55_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT55_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT55_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT55_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT55_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT55_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT55_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT55_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT55_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT55_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT55_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT55_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT55_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL55 Bit Fields */ -#define CCM_ACCESS_CTRL55_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL55_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL55_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL55_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL55_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL55_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL55_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL55_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL55_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL55_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL55_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL55_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL55_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL55_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL55_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL55_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL55_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL55_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL55_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL55_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL55_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL55_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL55_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL55_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL55_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL55_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL55_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL55_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL55_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL55_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL55_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL55_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL55_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL55_LOCK_SHIFT 31 -/* ACCESS_CTRL55_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL55_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL55_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL55_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL55_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL55_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL55_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL55_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL55_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL55_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL55_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL55_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL55_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL55_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL55_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL55_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL55_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT56 Bit Fields */ -#define CCM_TARGET_ROOT56_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT56_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT56_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_POST_PODF_SHIFT))&CCM_TARGET_ROOT56_POST_PODF_MASK) -#define CCM_TARGET_ROOT56_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT56_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT56_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT56_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT56_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT56_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT56_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT56_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT56_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT56_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT56_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_PRE_PODF_SHIFT))&CCM_TARGET_ROOT56_PRE_PODF_MASK) -#define CCM_TARGET_ROOT56_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT56_MUX_SHIFT 24 -#define CCM_TARGET_ROOT56_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_MUX_SHIFT))&CCM_TARGET_ROOT56_MUX_MASK) -#define CCM_TARGET_ROOT56_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT56_ENABLE_SHIFT 28 -/* TARGET_ROOT56_SET Bit Fields */ -#define CCM_TARGET_ROOT56_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT56_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT56_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT56_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT56_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT56_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT56_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT56_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT56_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT56_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT56_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT56_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT56_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT56_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT56_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT56_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT56_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT56_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT56_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_SET_MUX_SHIFT))&CCM_TARGET_ROOT56_SET_MUX_MASK) -#define CCM_TARGET_ROOT56_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT56_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT56_CLR Bit Fields */ -#define CCM_TARGET_ROOT56_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT56_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT56_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT56_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT56_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT56_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT56_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT56_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT56_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT56_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT56_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT56_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT56_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT56_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT56_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT56_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT56_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT56_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT56_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_CLR_MUX_SHIFT))&CCM_TARGET_ROOT56_CLR_MUX_MASK) -#define CCM_TARGET_ROOT56_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT56_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT56_TOG Bit Fields */ -#define CCM_TARGET_ROOT56_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT56_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT56_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT56_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT56_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT56_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT56_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT56_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT56_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT56_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT56_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT56_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT56_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT56_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT56_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT56_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT56_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT56_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT56_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_TOG_MUX_SHIFT))&CCM_TARGET_ROOT56_TOG_MUX_MASK) -#define CCM_TARGET_ROOT56_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT56_TOG_ENABLE_SHIFT 28 -/* POST56 Bit Fields */ -#define CCM_POST56_POST_PODF_MASK 0x3Fu -#define CCM_POST56_POST_PODF_SHIFT 0 -#define CCM_POST56_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST56_POST_PODF_SHIFT))&CCM_POST56_POST_PODF_MASK) -#define CCM_POST56_BUSY1_MASK 0x80u -#define CCM_POST56_BUSY1_SHIFT 7 -#define CCM_POST56_AUTO_PODF_MASK 0x700u -#define CCM_POST56_AUTO_PODF_SHIFT 8 -#define CCM_POST56_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST56_AUTO_PODF_SHIFT))&CCM_POST56_AUTO_PODF_MASK) -#define CCM_POST56_AUTO_EN_MASK 0x1000u -#define CCM_POST56_AUTO_EN_SHIFT 12 -#define CCM_POST56_SLOW_MASK 0x8000u -#define CCM_POST56_SLOW_SHIFT 15 -#define CCM_POST56_SELECT_MASK 0x10000000u -#define CCM_POST56_SELECT_SHIFT 28 -#define CCM_POST56_BUSY2_MASK 0x80000000u -#define CCM_POST56_BUSY2_SHIFT 31 -/* POST_ROOT56_SET Bit Fields */ -#define CCM_POST_ROOT56_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT56_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT56_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_SET_POST_PODF_SHIFT))&CCM_POST_ROOT56_SET_POST_PODF_MASK) -#define CCM_POST_ROOT56_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT56_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT56_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT56_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT56_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT56_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT56_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT56_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT56_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT56_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT56_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT56_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT56_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT56_SET_BUSY2_SHIFT 31 -/* POST_ROOT56_CLR Bit Fields */ -#define CCM_POST_ROOT56_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT56_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT56_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT56_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT56_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT56_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT56_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT56_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT56_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT56_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT56_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT56_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT56_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT56_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT56_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT56_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT56_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT56_CLR_BUSY2_SHIFT 31 -/* POST_ROOT56_TOG Bit Fields */ -#define CCM_POST_ROOT56_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT56_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT56_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT56_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT56_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT56_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT56_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT56_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT56_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT56_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT56_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT56_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT56_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT56_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT56_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT56_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT56_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT56_TOG_BUSY2_SHIFT 31 -/* PRE56 Bit Fields */ -#define CCM_PRE56_PRE_PODF_B_MASK 0x7u -#define CCM_PRE56_PRE_PODF_B_SHIFT 0 -#define CCM_PRE56_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE56_PRE_PODF_B_SHIFT))&CCM_PRE56_PRE_PODF_B_MASK) -#define CCM_PRE56_BUSY0_MASK 0x8u -#define CCM_PRE56_BUSY0_SHIFT 3 -#define CCM_PRE56_MUX_B_MASK 0x700u -#define CCM_PRE56_MUX_B_SHIFT 8 -#define CCM_PRE56_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE56_MUX_B_SHIFT))&CCM_PRE56_MUX_B_MASK) -#define CCM_PRE56_EN_B_MASK 0x1000u -#define CCM_PRE56_EN_B_SHIFT 12 -#define CCM_PRE56_BUSY1_MASK 0x8000u -#define CCM_PRE56_BUSY1_SHIFT 15 -#define CCM_PRE56_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE56_PRE_PODF_A_SHIFT 16 -#define CCM_PRE56_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE56_PRE_PODF_A_SHIFT))&CCM_PRE56_PRE_PODF_A_MASK) -#define CCM_PRE56_BUSY3_MASK 0x80000u -#define CCM_PRE56_BUSY3_SHIFT 19 -#define CCM_PRE56_MUX_A_MASK 0x7000000u -#define CCM_PRE56_MUX_A_SHIFT 24 -#define CCM_PRE56_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE56_MUX_A_SHIFT))&CCM_PRE56_MUX_A_MASK) -#define CCM_PRE56_EN_A_MASK 0x10000000u -#define CCM_PRE56_EN_A_SHIFT 28 -#define CCM_PRE56_BUSY4_MASK 0x80000000u -#define CCM_PRE56_BUSY4_SHIFT 31 -/* PRE_ROOT56_SET Bit Fields */ -#define CCM_PRE_ROOT56_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT56_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT56_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT56_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT56_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT56_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT56_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT56_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT56_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_SET_MUX_B_SHIFT))&CCM_PRE_ROOT56_SET_MUX_B_MASK) -#define CCM_PRE_ROOT56_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT56_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT56_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT56_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT56_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT56_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT56_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT56_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT56_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT56_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT56_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT56_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT56_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_SET_MUX_A_SHIFT))&CCM_PRE_ROOT56_SET_MUX_A_MASK) -#define CCM_PRE_ROOT56_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT56_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT56_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT56_SET_BUSY4_SHIFT 31 -/* PRE_ROOT56_CLR Bit Fields */ -#define CCM_PRE_ROOT56_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT56_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT56_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT56_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT56_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT56_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT56_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT56_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT56_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT56_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT56_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT56_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT56_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT56_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT56_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT56_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT56_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT56_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT56_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT56_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT56_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT56_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT56_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT56_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT56_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT56_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT56_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT56_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT56_TOG Bit Fields */ -#define CCM_PRE_ROOT56_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT56_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT56_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT56_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT56_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT56_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT56_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT56_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT56_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT56_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT56_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT56_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT56_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT56_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT56_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT56_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT56_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT56_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT56_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT56_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT56_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT56_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT56_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT56_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT56_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT56_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT56_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT56_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL56 Bit Fields */ -#define CCM_ACCESS_CTRL56_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL56_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL56_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL56_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL56_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL56_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL56_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL56_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL56_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL56_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL56_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL56_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL56_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL56_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL56_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL56_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL56_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL56_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL56_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL56_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL56_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL56_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL56_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL56_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL56_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL56_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL56_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL56_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL56_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL56_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL56_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL56_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL56_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL56_LOCK_SHIFT 31 -/* ACCESS_CTRL56_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL56_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL56_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL56_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL56_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL56_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL56_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL56_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL56_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL56_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL56_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL56_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL56_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL56_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL56_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL56_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL56_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT57 Bit Fields */ -#define CCM_TARGET_ROOT57_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT57_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT57_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_POST_PODF_SHIFT))&CCM_TARGET_ROOT57_POST_PODF_MASK) -#define CCM_TARGET_ROOT57_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT57_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT57_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT57_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT57_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT57_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT57_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT57_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT57_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT57_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT57_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_PRE_PODF_SHIFT))&CCM_TARGET_ROOT57_PRE_PODF_MASK) -#define CCM_TARGET_ROOT57_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT57_MUX_SHIFT 24 -#define CCM_TARGET_ROOT57_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_MUX_SHIFT))&CCM_TARGET_ROOT57_MUX_MASK) -#define CCM_TARGET_ROOT57_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT57_ENABLE_SHIFT 28 -/* TARGET_ROOT57_SET Bit Fields */ -#define CCM_TARGET_ROOT57_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT57_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT57_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT57_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT57_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT57_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT57_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT57_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT57_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT57_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT57_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT57_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT57_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT57_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT57_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT57_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT57_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT57_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT57_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_SET_MUX_SHIFT))&CCM_TARGET_ROOT57_SET_MUX_MASK) -#define CCM_TARGET_ROOT57_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT57_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT57_CLR Bit Fields */ -#define CCM_TARGET_ROOT57_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT57_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT57_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT57_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT57_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT57_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT57_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT57_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT57_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT57_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT57_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT57_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT57_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT57_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT57_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT57_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT57_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT57_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT57_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_CLR_MUX_SHIFT))&CCM_TARGET_ROOT57_CLR_MUX_MASK) -#define CCM_TARGET_ROOT57_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT57_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT57_TOG Bit Fields */ -#define CCM_TARGET_ROOT57_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT57_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT57_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT57_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT57_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT57_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT57_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT57_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT57_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT57_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT57_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT57_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT57_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT57_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT57_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT57_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT57_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT57_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT57_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_TOG_MUX_SHIFT))&CCM_TARGET_ROOT57_TOG_MUX_MASK) -#define CCM_TARGET_ROOT57_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT57_TOG_ENABLE_SHIFT 28 -/* POST57 Bit Fields */ -#define CCM_POST57_POST_PODF_MASK 0x3Fu -#define CCM_POST57_POST_PODF_SHIFT 0 -#define CCM_POST57_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST57_POST_PODF_SHIFT))&CCM_POST57_POST_PODF_MASK) -#define CCM_POST57_BUSY1_MASK 0x80u -#define CCM_POST57_BUSY1_SHIFT 7 -#define CCM_POST57_AUTO_PODF_MASK 0x700u -#define CCM_POST57_AUTO_PODF_SHIFT 8 -#define CCM_POST57_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST57_AUTO_PODF_SHIFT))&CCM_POST57_AUTO_PODF_MASK) -#define CCM_POST57_AUTO_EN_MASK 0x1000u -#define CCM_POST57_AUTO_EN_SHIFT 12 -#define CCM_POST57_SLOW_MASK 0x8000u -#define CCM_POST57_SLOW_SHIFT 15 -#define CCM_POST57_SELECT_MASK 0x10000000u -#define CCM_POST57_SELECT_SHIFT 28 -#define CCM_POST57_BUSY2_MASK 0x80000000u -#define CCM_POST57_BUSY2_SHIFT 31 -/* POST_ROOT57_SET Bit Fields */ -#define CCM_POST_ROOT57_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT57_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT57_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_SET_POST_PODF_SHIFT))&CCM_POST_ROOT57_SET_POST_PODF_MASK) -#define CCM_POST_ROOT57_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT57_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT57_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT57_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT57_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT57_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT57_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT57_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT57_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT57_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT57_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT57_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT57_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT57_SET_BUSY2_SHIFT 31 -/* POST_ROOT57_CLR Bit Fields */ -#define CCM_POST_ROOT57_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT57_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT57_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT57_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT57_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT57_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT57_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT57_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT57_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT57_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT57_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT57_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT57_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT57_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT57_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT57_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT57_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT57_CLR_BUSY2_SHIFT 31 -/* POST_ROOT57_TOG Bit Fields */ -#define CCM_POST_ROOT57_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT57_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT57_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT57_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT57_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT57_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT57_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT57_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT57_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT57_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT57_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT57_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT57_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT57_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT57_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT57_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT57_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT57_TOG_BUSY2_SHIFT 31 -/* PRE57 Bit Fields */ -#define CCM_PRE57_PRE_PODF_B_MASK 0x7u -#define CCM_PRE57_PRE_PODF_B_SHIFT 0 -#define CCM_PRE57_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE57_PRE_PODF_B_SHIFT))&CCM_PRE57_PRE_PODF_B_MASK) -#define CCM_PRE57_BUSY0_MASK 0x8u -#define CCM_PRE57_BUSY0_SHIFT 3 -#define CCM_PRE57_MUX_B_MASK 0x700u -#define CCM_PRE57_MUX_B_SHIFT 8 -#define CCM_PRE57_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE57_MUX_B_SHIFT))&CCM_PRE57_MUX_B_MASK) -#define CCM_PRE57_EN_B_MASK 0x1000u -#define CCM_PRE57_EN_B_SHIFT 12 -#define CCM_PRE57_BUSY1_MASK 0x8000u -#define CCM_PRE57_BUSY1_SHIFT 15 -#define CCM_PRE57_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE57_PRE_PODF_A_SHIFT 16 -#define CCM_PRE57_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE57_PRE_PODF_A_SHIFT))&CCM_PRE57_PRE_PODF_A_MASK) -#define CCM_PRE57_BUSY3_MASK 0x80000u -#define CCM_PRE57_BUSY3_SHIFT 19 -#define CCM_PRE57_MUX_A_MASK 0x7000000u -#define CCM_PRE57_MUX_A_SHIFT 24 -#define CCM_PRE57_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE57_MUX_A_SHIFT))&CCM_PRE57_MUX_A_MASK) -#define CCM_PRE57_EN_A_MASK 0x10000000u -#define CCM_PRE57_EN_A_SHIFT 28 -#define CCM_PRE57_BUSY4_MASK 0x80000000u -#define CCM_PRE57_BUSY4_SHIFT 31 -/* PRE_ROOT57_SET Bit Fields */ -#define CCM_PRE_ROOT57_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT57_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT57_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT57_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT57_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT57_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT57_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT57_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT57_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_SET_MUX_B_SHIFT))&CCM_PRE_ROOT57_SET_MUX_B_MASK) -#define CCM_PRE_ROOT57_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT57_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT57_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT57_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT57_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT57_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT57_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT57_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT57_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT57_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT57_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT57_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT57_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_SET_MUX_A_SHIFT))&CCM_PRE_ROOT57_SET_MUX_A_MASK) -#define CCM_PRE_ROOT57_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT57_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT57_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT57_SET_BUSY4_SHIFT 31 -/* PRE_ROOT57_CLR Bit Fields */ -#define CCM_PRE_ROOT57_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT57_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT57_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT57_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT57_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT57_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT57_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT57_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT57_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT57_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT57_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT57_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT57_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT57_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT57_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT57_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT57_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT57_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT57_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT57_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT57_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT57_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT57_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT57_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT57_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT57_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT57_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT57_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT57_TOG Bit Fields */ -#define CCM_PRE_ROOT57_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT57_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT57_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT57_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT57_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT57_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT57_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT57_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT57_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT57_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT57_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT57_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT57_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT57_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT57_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT57_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT57_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT57_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT57_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT57_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT57_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT57_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT57_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT57_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT57_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT57_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT57_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT57_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL57 Bit Fields */ -#define CCM_ACCESS_CTRL57_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL57_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL57_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL57_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL57_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL57_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL57_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL57_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL57_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL57_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL57_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL57_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL57_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL57_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL57_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL57_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL57_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL57_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL57_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL57_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL57_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL57_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL57_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL57_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL57_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL57_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL57_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL57_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL57_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL57_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL57_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL57_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL57_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL57_LOCK_SHIFT 31 -/* ACCESS_CTRL57_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL57_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL57_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL57_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL57_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL57_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL57_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL57_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL57_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL57_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL57_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL57_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL57_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL57_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL57_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL57_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL57_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT58 Bit Fields */ -#define CCM_TARGET_ROOT58_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT58_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT58_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_POST_PODF_SHIFT))&CCM_TARGET_ROOT58_POST_PODF_MASK) -#define CCM_TARGET_ROOT58_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT58_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT58_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT58_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT58_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT58_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT58_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT58_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT58_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT58_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT58_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_PRE_PODF_SHIFT))&CCM_TARGET_ROOT58_PRE_PODF_MASK) -#define CCM_TARGET_ROOT58_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT58_MUX_SHIFT 24 -#define CCM_TARGET_ROOT58_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_MUX_SHIFT))&CCM_TARGET_ROOT58_MUX_MASK) -#define CCM_TARGET_ROOT58_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT58_ENABLE_SHIFT 28 -/* TARGET_ROOT58_SET Bit Fields */ -#define CCM_TARGET_ROOT58_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT58_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT58_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT58_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT58_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT58_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT58_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT58_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT58_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT58_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT58_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT58_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT58_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT58_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT58_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT58_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT58_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT58_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT58_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_SET_MUX_SHIFT))&CCM_TARGET_ROOT58_SET_MUX_MASK) -#define CCM_TARGET_ROOT58_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT58_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT58_CLR Bit Fields */ -#define CCM_TARGET_ROOT58_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT58_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT58_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT58_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT58_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT58_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT58_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT58_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT58_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT58_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT58_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT58_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT58_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT58_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT58_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT58_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT58_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT58_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT58_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_CLR_MUX_SHIFT))&CCM_TARGET_ROOT58_CLR_MUX_MASK) -#define CCM_TARGET_ROOT58_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT58_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT58_TOG Bit Fields */ -#define CCM_TARGET_ROOT58_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT58_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT58_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT58_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT58_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT58_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT58_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT58_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT58_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT58_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT58_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT58_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT58_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT58_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT58_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT58_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT58_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT58_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT58_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_TOG_MUX_SHIFT))&CCM_TARGET_ROOT58_TOG_MUX_MASK) -#define CCM_TARGET_ROOT58_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT58_TOG_ENABLE_SHIFT 28 -/* POST58 Bit Fields */ -#define CCM_POST58_POST_PODF_MASK 0x3Fu -#define CCM_POST58_POST_PODF_SHIFT 0 -#define CCM_POST58_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST58_POST_PODF_SHIFT))&CCM_POST58_POST_PODF_MASK) -#define CCM_POST58_BUSY1_MASK 0x80u -#define CCM_POST58_BUSY1_SHIFT 7 -#define CCM_POST58_AUTO_PODF_MASK 0x700u -#define CCM_POST58_AUTO_PODF_SHIFT 8 -#define CCM_POST58_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST58_AUTO_PODF_SHIFT))&CCM_POST58_AUTO_PODF_MASK) -#define CCM_POST58_AUTO_EN_MASK 0x1000u -#define CCM_POST58_AUTO_EN_SHIFT 12 -#define CCM_POST58_SLOW_MASK 0x8000u -#define CCM_POST58_SLOW_SHIFT 15 -#define CCM_POST58_SELECT_MASK 0x10000000u -#define CCM_POST58_SELECT_SHIFT 28 -#define CCM_POST58_BUSY2_MASK 0x80000000u -#define CCM_POST58_BUSY2_SHIFT 31 -/* POST_ROOT58_SET Bit Fields */ -#define CCM_POST_ROOT58_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT58_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT58_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_SET_POST_PODF_SHIFT))&CCM_POST_ROOT58_SET_POST_PODF_MASK) -#define CCM_POST_ROOT58_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT58_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT58_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT58_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT58_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT58_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT58_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT58_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT58_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT58_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT58_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT58_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT58_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT58_SET_BUSY2_SHIFT 31 -/* POST_ROOT58_CLR Bit Fields */ -#define CCM_POST_ROOT58_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT58_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT58_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT58_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT58_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT58_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT58_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT58_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT58_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT58_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT58_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT58_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT58_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT58_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT58_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT58_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT58_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT58_CLR_BUSY2_SHIFT 31 -/* POST_ROOT58_TOG Bit Fields */ -#define CCM_POST_ROOT58_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT58_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT58_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT58_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT58_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT58_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT58_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT58_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT58_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT58_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT58_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT58_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT58_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT58_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT58_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT58_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT58_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT58_TOG_BUSY2_SHIFT 31 -/* PRE58 Bit Fields */ -#define CCM_PRE58_PRE_PODF_B_MASK 0x7u -#define CCM_PRE58_PRE_PODF_B_SHIFT 0 -#define CCM_PRE58_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE58_PRE_PODF_B_SHIFT))&CCM_PRE58_PRE_PODF_B_MASK) -#define CCM_PRE58_BUSY0_MASK 0x8u -#define CCM_PRE58_BUSY0_SHIFT 3 -#define CCM_PRE58_MUX_B_MASK 0x700u -#define CCM_PRE58_MUX_B_SHIFT 8 -#define CCM_PRE58_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE58_MUX_B_SHIFT))&CCM_PRE58_MUX_B_MASK) -#define CCM_PRE58_EN_B_MASK 0x1000u -#define CCM_PRE58_EN_B_SHIFT 12 -#define CCM_PRE58_BUSY1_MASK 0x8000u -#define CCM_PRE58_BUSY1_SHIFT 15 -#define CCM_PRE58_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE58_PRE_PODF_A_SHIFT 16 -#define CCM_PRE58_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE58_PRE_PODF_A_SHIFT))&CCM_PRE58_PRE_PODF_A_MASK) -#define CCM_PRE58_BUSY3_MASK 0x80000u -#define CCM_PRE58_BUSY3_SHIFT 19 -#define CCM_PRE58_MUX_A_MASK 0x7000000u -#define CCM_PRE58_MUX_A_SHIFT 24 -#define CCM_PRE58_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE58_MUX_A_SHIFT))&CCM_PRE58_MUX_A_MASK) -#define CCM_PRE58_EN_A_MASK 0x10000000u -#define CCM_PRE58_EN_A_SHIFT 28 -#define CCM_PRE58_BUSY4_MASK 0x80000000u -#define CCM_PRE58_BUSY4_SHIFT 31 -/* PRE_ROOT58_SET Bit Fields */ -#define CCM_PRE_ROOT58_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT58_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT58_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT58_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT58_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT58_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT58_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT58_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT58_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_SET_MUX_B_SHIFT))&CCM_PRE_ROOT58_SET_MUX_B_MASK) -#define CCM_PRE_ROOT58_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT58_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT58_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT58_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT58_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT58_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT58_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT58_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT58_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT58_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT58_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT58_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT58_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_SET_MUX_A_SHIFT))&CCM_PRE_ROOT58_SET_MUX_A_MASK) -#define CCM_PRE_ROOT58_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT58_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT58_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT58_SET_BUSY4_SHIFT 31 -/* PRE_ROOT58_CLR Bit Fields */ -#define CCM_PRE_ROOT58_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT58_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT58_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT58_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT58_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT58_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT58_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT58_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT58_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT58_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT58_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT58_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT58_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT58_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT58_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT58_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT58_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT58_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT58_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT58_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT58_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT58_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT58_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT58_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT58_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT58_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT58_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT58_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT58_TOG Bit Fields */ -#define CCM_PRE_ROOT58_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT58_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT58_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT58_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT58_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT58_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT58_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT58_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT58_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT58_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT58_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT58_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT58_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT58_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT58_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT58_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT58_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT58_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT58_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT58_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT58_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT58_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT58_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT58_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT58_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT58_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT58_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT58_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL58 Bit Fields */ -#define CCM_ACCESS_CTRL58_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL58_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL58_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL58_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL58_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL58_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL58_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL58_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL58_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL58_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL58_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL58_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL58_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL58_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL58_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL58_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL58_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL58_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL58_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL58_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL58_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL58_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL58_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL58_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL58_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL58_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL58_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL58_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL58_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL58_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL58_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL58_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL58_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL58_LOCK_SHIFT 31 -/* ACCESS_CTRL58_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL58_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL58_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL58_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL58_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL58_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL58_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL58_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL58_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL58_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL58_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL58_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL58_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL58_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL58_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL58_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL58_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT59 Bit Fields */ -#define CCM_TARGET_ROOT59_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT59_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT59_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_POST_PODF_SHIFT))&CCM_TARGET_ROOT59_POST_PODF_MASK) -#define CCM_TARGET_ROOT59_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT59_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT59_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT59_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT59_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT59_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT59_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT59_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT59_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT59_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT59_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_PRE_PODF_SHIFT))&CCM_TARGET_ROOT59_PRE_PODF_MASK) -#define CCM_TARGET_ROOT59_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT59_MUX_SHIFT 24 -#define CCM_TARGET_ROOT59_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_MUX_SHIFT))&CCM_TARGET_ROOT59_MUX_MASK) -#define CCM_TARGET_ROOT59_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT59_ENABLE_SHIFT 28 -/* TARGET_ROOT59_SET Bit Fields */ -#define CCM_TARGET_ROOT59_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT59_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT59_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT59_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT59_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT59_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT59_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT59_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT59_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT59_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT59_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT59_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT59_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT59_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT59_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT59_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT59_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT59_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT59_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_SET_MUX_SHIFT))&CCM_TARGET_ROOT59_SET_MUX_MASK) -#define CCM_TARGET_ROOT59_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT59_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT59_CLR Bit Fields */ -#define CCM_TARGET_ROOT59_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT59_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT59_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT59_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT59_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT59_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT59_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT59_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT59_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT59_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT59_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT59_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT59_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT59_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT59_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT59_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT59_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT59_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT59_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_CLR_MUX_SHIFT))&CCM_TARGET_ROOT59_CLR_MUX_MASK) -#define CCM_TARGET_ROOT59_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT59_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT59_TOG Bit Fields */ -#define CCM_TARGET_ROOT59_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT59_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT59_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT59_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT59_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT59_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT59_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT59_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT59_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT59_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT59_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT59_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT59_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT59_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT59_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT59_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT59_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT59_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT59_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_TOG_MUX_SHIFT))&CCM_TARGET_ROOT59_TOG_MUX_MASK) -#define CCM_TARGET_ROOT59_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT59_TOG_ENABLE_SHIFT 28 -/* POST59 Bit Fields */ -#define CCM_POST59_POST_PODF_MASK 0x3Fu -#define CCM_POST59_POST_PODF_SHIFT 0 -#define CCM_POST59_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST59_POST_PODF_SHIFT))&CCM_POST59_POST_PODF_MASK) -#define CCM_POST59_BUSY1_MASK 0x80u -#define CCM_POST59_BUSY1_SHIFT 7 -#define CCM_POST59_AUTO_PODF_MASK 0x700u -#define CCM_POST59_AUTO_PODF_SHIFT 8 -#define CCM_POST59_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST59_AUTO_PODF_SHIFT))&CCM_POST59_AUTO_PODF_MASK) -#define CCM_POST59_AUTO_EN_MASK 0x1000u -#define CCM_POST59_AUTO_EN_SHIFT 12 -#define CCM_POST59_SLOW_MASK 0x8000u -#define CCM_POST59_SLOW_SHIFT 15 -#define CCM_POST59_SELECT_MASK 0x10000000u -#define CCM_POST59_SELECT_SHIFT 28 -#define CCM_POST59_BUSY2_MASK 0x80000000u -#define CCM_POST59_BUSY2_SHIFT 31 -/* POST_ROOT59_SET Bit Fields */ -#define CCM_POST_ROOT59_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT59_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT59_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_SET_POST_PODF_SHIFT))&CCM_POST_ROOT59_SET_POST_PODF_MASK) -#define CCM_POST_ROOT59_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT59_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT59_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT59_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT59_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT59_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT59_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT59_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT59_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT59_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT59_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT59_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT59_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT59_SET_BUSY2_SHIFT 31 -/* POST_ROOT59_CLR Bit Fields */ -#define CCM_POST_ROOT59_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT59_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT59_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT59_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT59_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT59_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT59_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT59_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT59_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT59_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT59_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT59_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT59_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT59_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT59_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT59_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT59_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT59_CLR_BUSY2_SHIFT 31 -/* POST_ROOT59_TOG Bit Fields */ -#define CCM_POST_ROOT59_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT59_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT59_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT59_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT59_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT59_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT59_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT59_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT59_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT59_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT59_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT59_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT59_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT59_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT59_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT59_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT59_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT59_TOG_BUSY2_SHIFT 31 -/* PRE59 Bit Fields */ -#define CCM_PRE59_PRE_PODF_B_MASK 0x7u -#define CCM_PRE59_PRE_PODF_B_SHIFT 0 -#define CCM_PRE59_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE59_PRE_PODF_B_SHIFT))&CCM_PRE59_PRE_PODF_B_MASK) -#define CCM_PRE59_BUSY0_MASK 0x8u -#define CCM_PRE59_BUSY0_SHIFT 3 -#define CCM_PRE59_MUX_B_MASK 0x700u -#define CCM_PRE59_MUX_B_SHIFT 8 -#define CCM_PRE59_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE59_MUX_B_SHIFT))&CCM_PRE59_MUX_B_MASK) -#define CCM_PRE59_EN_B_MASK 0x1000u -#define CCM_PRE59_EN_B_SHIFT 12 -#define CCM_PRE59_BUSY1_MASK 0x8000u -#define CCM_PRE59_BUSY1_SHIFT 15 -#define CCM_PRE59_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE59_PRE_PODF_A_SHIFT 16 -#define CCM_PRE59_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE59_PRE_PODF_A_SHIFT))&CCM_PRE59_PRE_PODF_A_MASK) -#define CCM_PRE59_BUSY3_MASK 0x80000u -#define CCM_PRE59_BUSY3_SHIFT 19 -#define CCM_PRE59_MUX_A_MASK 0x7000000u -#define CCM_PRE59_MUX_A_SHIFT 24 -#define CCM_PRE59_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE59_MUX_A_SHIFT))&CCM_PRE59_MUX_A_MASK) -#define CCM_PRE59_EN_A_MASK 0x10000000u -#define CCM_PRE59_EN_A_SHIFT 28 -#define CCM_PRE59_BUSY4_MASK 0x80000000u -#define CCM_PRE59_BUSY4_SHIFT 31 -/* PRE_ROOT59_SET Bit Fields */ -#define CCM_PRE_ROOT59_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT59_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT59_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT59_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT59_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT59_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT59_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT59_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT59_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_SET_MUX_B_SHIFT))&CCM_PRE_ROOT59_SET_MUX_B_MASK) -#define CCM_PRE_ROOT59_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT59_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT59_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT59_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT59_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT59_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT59_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT59_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT59_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT59_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT59_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT59_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT59_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_SET_MUX_A_SHIFT))&CCM_PRE_ROOT59_SET_MUX_A_MASK) -#define CCM_PRE_ROOT59_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT59_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT59_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT59_SET_BUSY4_SHIFT 31 -/* PRE_ROOT59_CLR Bit Fields */ -#define CCM_PRE_ROOT59_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT59_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT59_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT59_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT59_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT59_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT59_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT59_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT59_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT59_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT59_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT59_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT59_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT59_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT59_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT59_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT59_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT59_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT59_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT59_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT59_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT59_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT59_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT59_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT59_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT59_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT59_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT59_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT59_TOG Bit Fields */ -#define CCM_PRE_ROOT59_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT59_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT59_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT59_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT59_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT59_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT59_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT59_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT59_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT59_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT59_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT59_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT59_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT59_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT59_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT59_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT59_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT59_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT59_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT59_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT59_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT59_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT59_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT59_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT59_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT59_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT59_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT59_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL59 Bit Fields */ -#define CCM_ACCESS_CTRL59_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL59_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL59_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL59_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL59_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL59_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL59_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL59_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL59_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL59_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL59_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL59_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL59_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL59_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL59_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL59_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL59_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL59_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL59_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL59_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL59_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL59_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL59_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL59_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL59_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL59_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL59_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL59_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL59_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL59_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL59_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL59_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL59_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL59_LOCK_SHIFT 31 -/* ACCESS_CTRL59_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL59_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL59_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL59_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL59_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL59_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL59_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL59_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL59_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL59_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL59_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL59_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL59_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL59_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL59_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL59_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL59_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT60 Bit Fields */ -#define CCM_TARGET_ROOT60_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT60_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT60_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_POST_PODF_SHIFT))&CCM_TARGET_ROOT60_POST_PODF_MASK) -#define CCM_TARGET_ROOT60_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT60_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT60_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT60_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT60_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT60_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT60_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT60_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT60_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT60_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT60_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_PRE_PODF_SHIFT))&CCM_TARGET_ROOT60_PRE_PODF_MASK) -#define CCM_TARGET_ROOT60_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT60_MUX_SHIFT 24 -#define CCM_TARGET_ROOT60_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_MUX_SHIFT))&CCM_TARGET_ROOT60_MUX_MASK) -#define CCM_TARGET_ROOT60_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT60_ENABLE_SHIFT 28 -/* TARGET_ROOT60_SET Bit Fields */ -#define CCM_TARGET_ROOT60_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT60_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT60_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT60_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT60_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT60_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT60_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT60_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT60_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT60_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT60_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT60_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT60_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT60_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT60_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT60_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT60_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT60_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT60_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_SET_MUX_SHIFT))&CCM_TARGET_ROOT60_SET_MUX_MASK) -#define CCM_TARGET_ROOT60_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT60_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT60_CLR Bit Fields */ -#define CCM_TARGET_ROOT60_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT60_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT60_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT60_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT60_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT60_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT60_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT60_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT60_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT60_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT60_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT60_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT60_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT60_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT60_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT60_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT60_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT60_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT60_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_CLR_MUX_SHIFT))&CCM_TARGET_ROOT60_CLR_MUX_MASK) -#define CCM_TARGET_ROOT60_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT60_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT60_TOG Bit Fields */ -#define CCM_TARGET_ROOT60_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT60_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT60_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT60_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT60_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT60_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT60_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT60_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT60_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT60_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT60_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT60_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT60_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT60_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT60_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT60_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT60_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT60_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT60_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_TOG_MUX_SHIFT))&CCM_TARGET_ROOT60_TOG_MUX_MASK) -#define CCM_TARGET_ROOT60_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT60_TOG_ENABLE_SHIFT 28 -/* POST60 Bit Fields */ -#define CCM_POST60_POST_PODF_MASK 0x3Fu -#define CCM_POST60_POST_PODF_SHIFT 0 -#define CCM_POST60_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST60_POST_PODF_SHIFT))&CCM_POST60_POST_PODF_MASK) -#define CCM_POST60_BUSY1_MASK 0x80u -#define CCM_POST60_BUSY1_SHIFT 7 -#define CCM_POST60_AUTO_PODF_MASK 0x700u -#define CCM_POST60_AUTO_PODF_SHIFT 8 -#define CCM_POST60_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST60_AUTO_PODF_SHIFT))&CCM_POST60_AUTO_PODF_MASK) -#define CCM_POST60_AUTO_EN_MASK 0x1000u -#define CCM_POST60_AUTO_EN_SHIFT 12 -#define CCM_POST60_SLOW_MASK 0x8000u -#define CCM_POST60_SLOW_SHIFT 15 -#define CCM_POST60_SELECT_MASK 0x10000000u -#define CCM_POST60_SELECT_SHIFT 28 -#define CCM_POST60_BUSY2_MASK 0x80000000u -#define CCM_POST60_BUSY2_SHIFT 31 -/* POST_ROOT60_SET Bit Fields */ -#define CCM_POST_ROOT60_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT60_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT60_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_SET_POST_PODF_SHIFT))&CCM_POST_ROOT60_SET_POST_PODF_MASK) -#define CCM_POST_ROOT60_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT60_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT60_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT60_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT60_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT60_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT60_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT60_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT60_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT60_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT60_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT60_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT60_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT60_SET_BUSY2_SHIFT 31 -/* POST_ROOT60_CLR Bit Fields */ -#define CCM_POST_ROOT60_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT60_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT60_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT60_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT60_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT60_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT60_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT60_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT60_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT60_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT60_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT60_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT60_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT60_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT60_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT60_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT60_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT60_CLR_BUSY2_SHIFT 31 -/* POST_ROOT60_TOG Bit Fields */ -#define CCM_POST_ROOT60_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT60_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT60_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT60_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT60_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT60_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT60_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT60_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT60_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT60_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT60_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT60_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT60_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT60_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT60_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT60_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT60_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT60_TOG_BUSY2_SHIFT 31 -/* PRE60 Bit Fields */ -#define CCM_PRE60_PRE_PODF_B_MASK 0x7u -#define CCM_PRE60_PRE_PODF_B_SHIFT 0 -#define CCM_PRE60_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE60_PRE_PODF_B_SHIFT))&CCM_PRE60_PRE_PODF_B_MASK) -#define CCM_PRE60_BUSY0_MASK 0x8u -#define CCM_PRE60_BUSY0_SHIFT 3 -#define CCM_PRE60_MUX_B_MASK 0x700u -#define CCM_PRE60_MUX_B_SHIFT 8 -#define CCM_PRE60_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE60_MUX_B_SHIFT))&CCM_PRE60_MUX_B_MASK) -#define CCM_PRE60_EN_B_MASK 0x1000u -#define CCM_PRE60_EN_B_SHIFT 12 -#define CCM_PRE60_BUSY1_MASK 0x8000u -#define CCM_PRE60_BUSY1_SHIFT 15 -#define CCM_PRE60_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE60_PRE_PODF_A_SHIFT 16 -#define CCM_PRE60_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE60_PRE_PODF_A_SHIFT))&CCM_PRE60_PRE_PODF_A_MASK) -#define CCM_PRE60_BUSY3_MASK 0x80000u -#define CCM_PRE60_BUSY3_SHIFT 19 -#define CCM_PRE60_MUX_A_MASK 0x7000000u -#define CCM_PRE60_MUX_A_SHIFT 24 -#define CCM_PRE60_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE60_MUX_A_SHIFT))&CCM_PRE60_MUX_A_MASK) -#define CCM_PRE60_EN_A_MASK 0x10000000u -#define CCM_PRE60_EN_A_SHIFT 28 -#define CCM_PRE60_BUSY4_MASK 0x80000000u -#define CCM_PRE60_BUSY4_SHIFT 31 -/* PRE_ROOT60_SET Bit Fields */ -#define CCM_PRE_ROOT60_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT60_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT60_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT60_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT60_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT60_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT60_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT60_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT60_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_SET_MUX_B_SHIFT))&CCM_PRE_ROOT60_SET_MUX_B_MASK) -#define CCM_PRE_ROOT60_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT60_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT60_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT60_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT60_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT60_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT60_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT60_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT60_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT60_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT60_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT60_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT60_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_SET_MUX_A_SHIFT))&CCM_PRE_ROOT60_SET_MUX_A_MASK) -#define CCM_PRE_ROOT60_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT60_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT60_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT60_SET_BUSY4_SHIFT 31 -/* PRE_ROOT60_CLR Bit Fields */ -#define CCM_PRE_ROOT60_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT60_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT60_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT60_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT60_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT60_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT60_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT60_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT60_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT60_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT60_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT60_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT60_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT60_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT60_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT60_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT60_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT60_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT60_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT60_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT60_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT60_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT60_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT60_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT60_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT60_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT60_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT60_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT60_TOG Bit Fields */ -#define CCM_PRE_ROOT60_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT60_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT60_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT60_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT60_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT60_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT60_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT60_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT60_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT60_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT60_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT60_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT60_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT60_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT60_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT60_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT60_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT60_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT60_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT60_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT60_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT60_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT60_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT60_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT60_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT60_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT60_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT60_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL60 Bit Fields */ -#define CCM_ACCESS_CTRL60_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL60_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL60_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL60_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL60_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL60_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL60_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL60_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL60_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL60_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL60_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL60_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL60_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL60_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL60_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL60_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL60_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL60_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL60_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL60_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL60_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL60_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL60_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL60_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL60_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL60_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL60_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL60_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL60_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL60_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL60_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL60_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL60_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL60_LOCK_SHIFT 31 -/* ACCESS_CTRL60_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL60_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL60_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL60_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL60_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL60_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL60_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL60_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL60_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL60_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL60_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL60_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL60_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL60_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL60_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL60_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL60_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT61 Bit Fields */ -#define CCM_TARGET_ROOT61_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT61_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT61_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_POST_PODF_SHIFT))&CCM_TARGET_ROOT61_POST_PODF_MASK) -#define CCM_TARGET_ROOT61_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT61_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT61_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT61_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT61_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT61_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT61_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT61_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT61_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT61_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT61_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_PRE_PODF_SHIFT))&CCM_TARGET_ROOT61_PRE_PODF_MASK) -#define CCM_TARGET_ROOT61_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT61_MUX_SHIFT 24 -#define CCM_TARGET_ROOT61_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_MUX_SHIFT))&CCM_TARGET_ROOT61_MUX_MASK) -#define CCM_TARGET_ROOT61_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT61_ENABLE_SHIFT 28 -/* TARGET_ROOT61_SET Bit Fields */ -#define CCM_TARGET_ROOT61_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT61_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT61_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT61_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT61_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT61_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT61_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT61_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT61_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT61_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT61_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT61_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT61_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT61_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT61_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT61_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT61_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT61_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT61_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_SET_MUX_SHIFT))&CCM_TARGET_ROOT61_SET_MUX_MASK) -#define CCM_TARGET_ROOT61_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT61_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT61_CLR Bit Fields */ -#define CCM_TARGET_ROOT61_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT61_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT61_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT61_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT61_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT61_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT61_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT61_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT61_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT61_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT61_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT61_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT61_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT61_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT61_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT61_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT61_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT61_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT61_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_CLR_MUX_SHIFT))&CCM_TARGET_ROOT61_CLR_MUX_MASK) -#define CCM_TARGET_ROOT61_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT61_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT61_TOG Bit Fields */ -#define CCM_TARGET_ROOT61_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT61_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT61_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT61_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT61_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT61_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT61_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT61_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT61_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT61_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT61_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT61_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT61_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT61_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT61_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT61_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT61_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT61_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT61_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_TOG_MUX_SHIFT))&CCM_TARGET_ROOT61_TOG_MUX_MASK) -#define CCM_TARGET_ROOT61_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT61_TOG_ENABLE_SHIFT 28 -/* POST61 Bit Fields */ -#define CCM_POST61_POST_PODF_MASK 0x3Fu -#define CCM_POST61_POST_PODF_SHIFT 0 -#define CCM_POST61_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST61_POST_PODF_SHIFT))&CCM_POST61_POST_PODF_MASK) -#define CCM_POST61_BUSY1_MASK 0x80u -#define CCM_POST61_BUSY1_SHIFT 7 -#define CCM_POST61_AUTO_PODF_MASK 0x700u -#define CCM_POST61_AUTO_PODF_SHIFT 8 -#define CCM_POST61_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST61_AUTO_PODF_SHIFT))&CCM_POST61_AUTO_PODF_MASK) -#define CCM_POST61_AUTO_EN_MASK 0x1000u -#define CCM_POST61_AUTO_EN_SHIFT 12 -#define CCM_POST61_SLOW_MASK 0x8000u -#define CCM_POST61_SLOW_SHIFT 15 -#define CCM_POST61_SELECT_MASK 0x10000000u -#define CCM_POST61_SELECT_SHIFT 28 -#define CCM_POST61_BUSY2_MASK 0x80000000u -#define CCM_POST61_BUSY2_SHIFT 31 -/* POST_ROOT61_SET Bit Fields */ -#define CCM_POST_ROOT61_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT61_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT61_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_SET_POST_PODF_SHIFT))&CCM_POST_ROOT61_SET_POST_PODF_MASK) -#define CCM_POST_ROOT61_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT61_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT61_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT61_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT61_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT61_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT61_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT61_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT61_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT61_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT61_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT61_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT61_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT61_SET_BUSY2_SHIFT 31 -/* POST_ROOT61_CLR Bit Fields */ -#define CCM_POST_ROOT61_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT61_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT61_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT61_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT61_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT61_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT61_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT61_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT61_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT61_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT61_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT61_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT61_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT61_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT61_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT61_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT61_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT61_CLR_BUSY2_SHIFT 31 -/* POST_ROOT61_TOG Bit Fields */ -#define CCM_POST_ROOT61_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT61_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT61_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT61_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT61_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT61_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT61_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT61_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT61_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT61_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT61_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT61_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT61_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT61_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT61_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT61_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT61_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT61_TOG_BUSY2_SHIFT 31 -/* PRE61 Bit Fields */ -#define CCM_PRE61_PRE_PODF_B_MASK 0x7u -#define CCM_PRE61_PRE_PODF_B_SHIFT 0 -#define CCM_PRE61_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE61_PRE_PODF_B_SHIFT))&CCM_PRE61_PRE_PODF_B_MASK) -#define CCM_PRE61_BUSY0_MASK 0x8u -#define CCM_PRE61_BUSY0_SHIFT 3 -#define CCM_PRE61_MUX_B_MASK 0x700u -#define CCM_PRE61_MUX_B_SHIFT 8 -#define CCM_PRE61_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE61_MUX_B_SHIFT))&CCM_PRE61_MUX_B_MASK) -#define CCM_PRE61_EN_B_MASK 0x1000u -#define CCM_PRE61_EN_B_SHIFT 12 -#define CCM_PRE61_BUSY1_MASK 0x8000u -#define CCM_PRE61_BUSY1_SHIFT 15 -#define CCM_PRE61_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE61_PRE_PODF_A_SHIFT 16 -#define CCM_PRE61_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE61_PRE_PODF_A_SHIFT))&CCM_PRE61_PRE_PODF_A_MASK) -#define CCM_PRE61_BUSY3_MASK 0x80000u -#define CCM_PRE61_BUSY3_SHIFT 19 -#define CCM_PRE61_MUX_A_MASK 0x7000000u -#define CCM_PRE61_MUX_A_SHIFT 24 -#define CCM_PRE61_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE61_MUX_A_SHIFT))&CCM_PRE61_MUX_A_MASK) -#define CCM_PRE61_EN_A_MASK 0x10000000u -#define CCM_PRE61_EN_A_SHIFT 28 -#define CCM_PRE61_BUSY4_MASK 0x80000000u -#define CCM_PRE61_BUSY4_SHIFT 31 -/* PRE_ROOT61_SET Bit Fields */ -#define CCM_PRE_ROOT61_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT61_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT61_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT61_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT61_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT61_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT61_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT61_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT61_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_SET_MUX_B_SHIFT))&CCM_PRE_ROOT61_SET_MUX_B_MASK) -#define CCM_PRE_ROOT61_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT61_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT61_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT61_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT61_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT61_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT61_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT61_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT61_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT61_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT61_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT61_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT61_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_SET_MUX_A_SHIFT))&CCM_PRE_ROOT61_SET_MUX_A_MASK) -#define CCM_PRE_ROOT61_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT61_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT61_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT61_SET_BUSY4_SHIFT 31 -/* PRE_ROOT61_CLR Bit Fields */ -#define CCM_PRE_ROOT61_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT61_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT61_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT61_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT61_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT61_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT61_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT61_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT61_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT61_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT61_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT61_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT61_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT61_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT61_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT61_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT61_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT61_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT61_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT61_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT61_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT61_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT61_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT61_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT61_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT61_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT61_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT61_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT61_TOG Bit Fields */ -#define CCM_PRE_ROOT61_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT61_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT61_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT61_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT61_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT61_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT61_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT61_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT61_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT61_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT61_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT61_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT61_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT61_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT61_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT61_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT61_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT61_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT61_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT61_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT61_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT61_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT61_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT61_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT61_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT61_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT61_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT61_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL61 Bit Fields */ -#define CCM_ACCESS_CTRL61_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL61_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL61_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL61_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL61_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL61_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL61_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL61_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL61_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL61_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL61_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL61_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL61_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL61_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL61_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL61_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL61_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL61_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL61_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL61_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL61_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL61_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL61_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL61_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL61_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL61_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL61_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL61_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL61_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL61_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL61_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL61_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL61_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL61_LOCK_SHIFT 31 -/* ACCESS_CTRL61_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL61_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL61_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL61_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL61_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL61_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL61_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL61_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL61_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL61_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL61_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL61_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL61_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL61_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL61_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL61_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL61_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT62 Bit Fields */ -#define CCM_TARGET_ROOT62_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT62_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT62_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_POST_PODF_SHIFT))&CCM_TARGET_ROOT62_POST_PODF_MASK) -#define CCM_TARGET_ROOT62_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT62_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT62_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT62_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT62_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT62_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT62_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT62_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT62_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT62_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT62_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_PRE_PODF_SHIFT))&CCM_TARGET_ROOT62_PRE_PODF_MASK) -#define CCM_TARGET_ROOT62_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT62_MUX_SHIFT 24 -#define CCM_TARGET_ROOT62_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_MUX_SHIFT))&CCM_TARGET_ROOT62_MUX_MASK) -#define CCM_TARGET_ROOT62_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT62_ENABLE_SHIFT 28 -/* TARGET_ROOT62_SET Bit Fields */ -#define CCM_TARGET_ROOT62_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT62_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT62_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT62_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT62_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT62_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT62_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT62_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT62_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT62_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT62_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT62_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT62_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT62_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT62_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT62_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT62_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT62_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT62_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_SET_MUX_SHIFT))&CCM_TARGET_ROOT62_SET_MUX_MASK) -#define CCM_TARGET_ROOT62_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT62_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT62_CLR Bit Fields */ -#define CCM_TARGET_ROOT62_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT62_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT62_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT62_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT62_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT62_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT62_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT62_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT62_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT62_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT62_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT62_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT62_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT62_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT62_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT62_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT62_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT62_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT62_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_CLR_MUX_SHIFT))&CCM_TARGET_ROOT62_CLR_MUX_MASK) -#define CCM_TARGET_ROOT62_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT62_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT62_TOG Bit Fields */ -#define CCM_TARGET_ROOT62_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT62_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT62_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT62_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT62_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT62_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT62_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT62_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT62_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT62_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT62_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT62_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT62_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT62_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT62_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT62_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT62_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT62_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT62_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_TOG_MUX_SHIFT))&CCM_TARGET_ROOT62_TOG_MUX_MASK) -#define CCM_TARGET_ROOT62_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT62_TOG_ENABLE_SHIFT 28 -/* POST62 Bit Fields */ -#define CCM_POST62_POST_PODF_MASK 0x3Fu -#define CCM_POST62_POST_PODF_SHIFT 0 -#define CCM_POST62_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST62_POST_PODF_SHIFT))&CCM_POST62_POST_PODF_MASK) -#define CCM_POST62_BUSY1_MASK 0x80u -#define CCM_POST62_BUSY1_SHIFT 7 -#define CCM_POST62_AUTO_PODF_MASK 0x700u -#define CCM_POST62_AUTO_PODF_SHIFT 8 -#define CCM_POST62_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST62_AUTO_PODF_SHIFT))&CCM_POST62_AUTO_PODF_MASK) -#define CCM_POST62_AUTO_EN_MASK 0x1000u -#define CCM_POST62_AUTO_EN_SHIFT 12 -#define CCM_POST62_SLOW_MASK 0x8000u -#define CCM_POST62_SLOW_SHIFT 15 -#define CCM_POST62_SELECT_MASK 0x10000000u -#define CCM_POST62_SELECT_SHIFT 28 -#define CCM_POST62_BUSY2_MASK 0x80000000u -#define CCM_POST62_BUSY2_SHIFT 31 -/* POST_ROOT62_SET Bit Fields */ -#define CCM_POST_ROOT62_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT62_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT62_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_SET_POST_PODF_SHIFT))&CCM_POST_ROOT62_SET_POST_PODF_MASK) -#define CCM_POST_ROOT62_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT62_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT62_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT62_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT62_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT62_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT62_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT62_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT62_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT62_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT62_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT62_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT62_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT62_SET_BUSY2_SHIFT 31 -/* POST_ROOT62_CLR Bit Fields */ -#define CCM_POST_ROOT62_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT62_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT62_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT62_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT62_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT62_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT62_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT62_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT62_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT62_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT62_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT62_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT62_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT62_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT62_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT62_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT62_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT62_CLR_BUSY2_SHIFT 31 -/* POST_ROOT62_TOG Bit Fields */ -#define CCM_POST_ROOT62_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT62_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT62_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT62_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT62_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT62_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT62_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT62_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT62_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT62_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT62_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT62_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT62_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT62_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT62_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT62_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT62_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT62_TOG_BUSY2_SHIFT 31 -/* PRE62 Bit Fields */ -#define CCM_PRE62_PRE_PODF_B_MASK 0x7u -#define CCM_PRE62_PRE_PODF_B_SHIFT 0 -#define CCM_PRE62_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE62_PRE_PODF_B_SHIFT))&CCM_PRE62_PRE_PODF_B_MASK) -#define CCM_PRE62_BUSY0_MASK 0x8u -#define CCM_PRE62_BUSY0_SHIFT 3 -#define CCM_PRE62_MUX_B_MASK 0x700u -#define CCM_PRE62_MUX_B_SHIFT 8 -#define CCM_PRE62_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE62_MUX_B_SHIFT))&CCM_PRE62_MUX_B_MASK) -#define CCM_PRE62_EN_B_MASK 0x1000u -#define CCM_PRE62_EN_B_SHIFT 12 -#define CCM_PRE62_BUSY1_MASK 0x8000u -#define CCM_PRE62_BUSY1_SHIFT 15 -#define CCM_PRE62_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE62_PRE_PODF_A_SHIFT 16 -#define CCM_PRE62_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE62_PRE_PODF_A_SHIFT))&CCM_PRE62_PRE_PODF_A_MASK) -#define CCM_PRE62_BUSY3_MASK 0x80000u -#define CCM_PRE62_BUSY3_SHIFT 19 -#define CCM_PRE62_MUX_A_MASK 0x7000000u -#define CCM_PRE62_MUX_A_SHIFT 24 -#define CCM_PRE62_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE62_MUX_A_SHIFT))&CCM_PRE62_MUX_A_MASK) -#define CCM_PRE62_EN_A_MASK 0x10000000u -#define CCM_PRE62_EN_A_SHIFT 28 -#define CCM_PRE62_BUSY4_MASK 0x80000000u -#define CCM_PRE62_BUSY4_SHIFT 31 -/* PRE_ROOT62_SET Bit Fields */ -#define CCM_PRE_ROOT62_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT62_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT62_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT62_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT62_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT62_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT62_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT62_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT62_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_SET_MUX_B_SHIFT))&CCM_PRE_ROOT62_SET_MUX_B_MASK) -#define CCM_PRE_ROOT62_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT62_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT62_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT62_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT62_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT62_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT62_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT62_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT62_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT62_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT62_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT62_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT62_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_SET_MUX_A_SHIFT))&CCM_PRE_ROOT62_SET_MUX_A_MASK) -#define CCM_PRE_ROOT62_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT62_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT62_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT62_SET_BUSY4_SHIFT 31 -/* PRE_ROOT62_CLR Bit Fields */ -#define CCM_PRE_ROOT62_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT62_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT62_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT62_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT62_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT62_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT62_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT62_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT62_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT62_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT62_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT62_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT62_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT62_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT62_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT62_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT62_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT62_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT62_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT62_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT62_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT62_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT62_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT62_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT62_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT62_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT62_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT62_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT62_TOG Bit Fields */ -#define CCM_PRE_ROOT62_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT62_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT62_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT62_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT62_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT62_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT62_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT62_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT62_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT62_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT62_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT62_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT62_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT62_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT62_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT62_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT62_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT62_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT62_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT62_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT62_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT62_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT62_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT62_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT62_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT62_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT62_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT62_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL62 Bit Fields */ -#define CCM_ACCESS_CTRL62_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL62_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL62_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL62_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL62_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL62_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL62_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL62_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL62_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL62_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL62_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL62_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL62_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL62_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL62_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL62_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL62_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL62_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL62_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL62_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL62_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL62_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL62_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL62_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL62_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL62_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL62_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL62_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL62_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL62_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL62_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL62_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL62_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL62_LOCK_SHIFT 31 -/* ACCESS_CTRL62_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL62_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL62_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL62_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL62_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL62_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL62_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL62_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL62_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL62_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL62_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL62_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL62_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL62_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL62_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL62_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL62_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT63 Bit Fields */ -#define CCM_TARGET_ROOT63_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT63_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT63_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_POST_PODF_SHIFT))&CCM_TARGET_ROOT63_POST_PODF_MASK) -#define CCM_TARGET_ROOT63_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT63_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT63_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT63_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT63_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT63_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT63_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT63_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT63_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT63_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT63_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_PRE_PODF_SHIFT))&CCM_TARGET_ROOT63_PRE_PODF_MASK) -#define CCM_TARGET_ROOT63_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT63_MUX_SHIFT 24 -#define CCM_TARGET_ROOT63_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_MUX_SHIFT))&CCM_TARGET_ROOT63_MUX_MASK) -#define CCM_TARGET_ROOT63_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT63_ENABLE_SHIFT 28 -/* TARGET_ROOT63_SET Bit Fields */ -#define CCM_TARGET_ROOT63_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT63_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT63_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT63_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT63_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT63_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT63_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT63_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT63_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT63_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT63_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT63_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT63_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT63_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT63_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT63_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT63_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT63_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT63_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_SET_MUX_SHIFT))&CCM_TARGET_ROOT63_SET_MUX_MASK) -#define CCM_TARGET_ROOT63_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT63_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT63_CLR Bit Fields */ -#define CCM_TARGET_ROOT63_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT63_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT63_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT63_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT63_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT63_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT63_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT63_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT63_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT63_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT63_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT63_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT63_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT63_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT63_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT63_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT63_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT63_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT63_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_CLR_MUX_SHIFT))&CCM_TARGET_ROOT63_CLR_MUX_MASK) -#define CCM_TARGET_ROOT63_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT63_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT63_TOG Bit Fields */ -#define CCM_TARGET_ROOT63_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT63_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT63_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT63_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT63_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT63_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT63_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT63_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT63_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT63_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT63_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT63_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT63_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT63_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT63_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT63_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT63_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT63_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT63_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_TOG_MUX_SHIFT))&CCM_TARGET_ROOT63_TOG_MUX_MASK) -#define CCM_TARGET_ROOT63_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT63_TOG_ENABLE_SHIFT 28 -/* POST63 Bit Fields */ -#define CCM_POST63_POST_PODF_MASK 0x3Fu -#define CCM_POST63_POST_PODF_SHIFT 0 -#define CCM_POST63_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST63_POST_PODF_SHIFT))&CCM_POST63_POST_PODF_MASK) -#define CCM_POST63_BUSY1_MASK 0x80u -#define CCM_POST63_BUSY1_SHIFT 7 -#define CCM_POST63_AUTO_PODF_MASK 0x700u -#define CCM_POST63_AUTO_PODF_SHIFT 8 -#define CCM_POST63_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST63_AUTO_PODF_SHIFT))&CCM_POST63_AUTO_PODF_MASK) -#define CCM_POST63_AUTO_EN_MASK 0x1000u -#define CCM_POST63_AUTO_EN_SHIFT 12 -#define CCM_POST63_SLOW_MASK 0x8000u -#define CCM_POST63_SLOW_SHIFT 15 -#define CCM_POST63_SELECT_MASK 0x10000000u -#define CCM_POST63_SELECT_SHIFT 28 -#define CCM_POST63_BUSY2_MASK 0x80000000u -#define CCM_POST63_BUSY2_SHIFT 31 -/* POST_ROOT63_SET Bit Fields */ -#define CCM_POST_ROOT63_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT63_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT63_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_SET_POST_PODF_SHIFT))&CCM_POST_ROOT63_SET_POST_PODF_MASK) -#define CCM_POST_ROOT63_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT63_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT63_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT63_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT63_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT63_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT63_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT63_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT63_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT63_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT63_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT63_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT63_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT63_SET_BUSY2_SHIFT 31 -/* POST_ROOT63_CLR Bit Fields */ -#define CCM_POST_ROOT63_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT63_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT63_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT63_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT63_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT63_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT63_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT63_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT63_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT63_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT63_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT63_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT63_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT63_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT63_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT63_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT63_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT63_CLR_BUSY2_SHIFT 31 -/* POST_ROOT63_TOG Bit Fields */ -#define CCM_POST_ROOT63_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT63_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT63_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT63_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT63_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT63_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT63_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT63_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT63_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT63_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT63_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT63_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT63_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT63_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT63_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT63_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT63_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT63_TOG_BUSY2_SHIFT 31 -/* PRE63 Bit Fields */ -#define CCM_PRE63_PRE_PODF_B_MASK 0x7u -#define CCM_PRE63_PRE_PODF_B_SHIFT 0 -#define CCM_PRE63_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE63_PRE_PODF_B_SHIFT))&CCM_PRE63_PRE_PODF_B_MASK) -#define CCM_PRE63_BUSY0_MASK 0x8u -#define CCM_PRE63_BUSY0_SHIFT 3 -#define CCM_PRE63_MUX_B_MASK 0x700u -#define CCM_PRE63_MUX_B_SHIFT 8 -#define CCM_PRE63_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE63_MUX_B_SHIFT))&CCM_PRE63_MUX_B_MASK) -#define CCM_PRE63_EN_B_MASK 0x1000u -#define CCM_PRE63_EN_B_SHIFT 12 -#define CCM_PRE63_BUSY1_MASK 0x8000u -#define CCM_PRE63_BUSY1_SHIFT 15 -#define CCM_PRE63_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE63_PRE_PODF_A_SHIFT 16 -#define CCM_PRE63_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE63_PRE_PODF_A_SHIFT))&CCM_PRE63_PRE_PODF_A_MASK) -#define CCM_PRE63_BUSY3_MASK 0x80000u -#define CCM_PRE63_BUSY3_SHIFT 19 -#define CCM_PRE63_MUX_A_MASK 0x7000000u -#define CCM_PRE63_MUX_A_SHIFT 24 -#define CCM_PRE63_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE63_MUX_A_SHIFT))&CCM_PRE63_MUX_A_MASK) -#define CCM_PRE63_EN_A_MASK 0x10000000u -#define CCM_PRE63_EN_A_SHIFT 28 -#define CCM_PRE63_BUSY4_MASK 0x80000000u -#define CCM_PRE63_BUSY4_SHIFT 31 -/* PRE_ROOT63_SET Bit Fields */ -#define CCM_PRE_ROOT63_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT63_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT63_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT63_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT63_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT63_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT63_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT63_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT63_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_SET_MUX_B_SHIFT))&CCM_PRE_ROOT63_SET_MUX_B_MASK) -#define CCM_PRE_ROOT63_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT63_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT63_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT63_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT63_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT63_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT63_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT63_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT63_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT63_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT63_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT63_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT63_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_SET_MUX_A_SHIFT))&CCM_PRE_ROOT63_SET_MUX_A_MASK) -#define CCM_PRE_ROOT63_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT63_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT63_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT63_SET_BUSY4_SHIFT 31 -/* PRE_ROOT63_CLR Bit Fields */ -#define CCM_PRE_ROOT63_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT63_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT63_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT63_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT63_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT63_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT63_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT63_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT63_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT63_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT63_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT63_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT63_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT63_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT63_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT63_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT63_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT63_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT63_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT63_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT63_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT63_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT63_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT63_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT63_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT63_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT63_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT63_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT63_TOG Bit Fields */ -#define CCM_PRE_ROOT63_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT63_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT63_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT63_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT63_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT63_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT63_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT63_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT63_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT63_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT63_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT63_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT63_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT63_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT63_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT63_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT63_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT63_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT63_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT63_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT63_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT63_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT63_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT63_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT63_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT63_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT63_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT63_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL63 Bit Fields */ -#define CCM_ACCESS_CTRL63_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL63_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL63_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL63_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL63_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL63_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL63_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL63_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL63_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL63_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL63_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL63_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL63_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL63_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL63_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL63_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL63_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL63_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL63_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL63_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL63_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL63_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL63_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL63_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL63_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL63_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL63_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL63_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL63_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL63_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL63_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL63_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL63_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL63_LOCK_SHIFT 31 -/* ACCESS_CTRL63_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL63_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL63_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL63_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL63_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL63_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL63_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL63_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL63_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL63_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL63_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL63_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL63_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL63_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL63_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL63_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL63_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT64 Bit Fields */ -#define CCM_TARGET_ROOT64_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT64_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT64_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_POST_PODF_SHIFT))&CCM_TARGET_ROOT64_POST_PODF_MASK) -#define CCM_TARGET_ROOT64_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT64_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT64_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT64_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT64_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT64_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT64_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT64_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT64_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT64_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT64_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_PRE_PODF_SHIFT))&CCM_TARGET_ROOT64_PRE_PODF_MASK) -#define CCM_TARGET_ROOT64_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT64_MUX_SHIFT 24 -#define CCM_TARGET_ROOT64_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_MUX_SHIFT))&CCM_TARGET_ROOT64_MUX_MASK) -#define CCM_TARGET_ROOT64_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT64_ENABLE_SHIFT 28 -/* TARGET_ROOT64_SET Bit Fields */ -#define CCM_TARGET_ROOT64_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT64_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT64_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT64_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT64_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT64_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT64_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT64_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT64_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT64_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT64_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT64_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT64_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT64_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT64_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT64_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT64_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT64_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT64_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_SET_MUX_SHIFT))&CCM_TARGET_ROOT64_SET_MUX_MASK) -#define CCM_TARGET_ROOT64_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT64_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT64_CLR Bit Fields */ -#define CCM_TARGET_ROOT64_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT64_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT64_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT64_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT64_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT64_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT64_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT64_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT64_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT64_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT64_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT64_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT64_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT64_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT64_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT64_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT64_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT64_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT64_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_CLR_MUX_SHIFT))&CCM_TARGET_ROOT64_CLR_MUX_MASK) -#define CCM_TARGET_ROOT64_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT64_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT64_TOG Bit Fields */ -#define CCM_TARGET_ROOT64_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT64_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT64_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT64_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT64_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT64_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT64_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT64_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT64_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT64_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT64_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT64_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT64_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT64_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT64_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT64_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT64_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT64_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT64_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_TOG_MUX_SHIFT))&CCM_TARGET_ROOT64_TOG_MUX_MASK) -#define CCM_TARGET_ROOT64_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT64_TOG_ENABLE_SHIFT 28 -/* POST64 Bit Fields */ -#define CCM_POST64_POST_PODF_MASK 0x3Fu -#define CCM_POST64_POST_PODF_SHIFT 0 -#define CCM_POST64_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST64_POST_PODF_SHIFT))&CCM_POST64_POST_PODF_MASK) -#define CCM_POST64_BUSY1_MASK 0x80u -#define CCM_POST64_BUSY1_SHIFT 7 -#define CCM_POST64_AUTO_PODF_MASK 0x700u -#define CCM_POST64_AUTO_PODF_SHIFT 8 -#define CCM_POST64_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST64_AUTO_PODF_SHIFT))&CCM_POST64_AUTO_PODF_MASK) -#define CCM_POST64_AUTO_EN_MASK 0x1000u -#define CCM_POST64_AUTO_EN_SHIFT 12 -#define CCM_POST64_SLOW_MASK 0x8000u -#define CCM_POST64_SLOW_SHIFT 15 -#define CCM_POST64_SELECT_MASK 0x10000000u -#define CCM_POST64_SELECT_SHIFT 28 -#define CCM_POST64_BUSY2_MASK 0x80000000u -#define CCM_POST64_BUSY2_SHIFT 31 -/* POST_ROOT64_SET Bit Fields */ -#define CCM_POST_ROOT64_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT64_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT64_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_SET_POST_PODF_SHIFT))&CCM_POST_ROOT64_SET_POST_PODF_MASK) -#define CCM_POST_ROOT64_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT64_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT64_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT64_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT64_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT64_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT64_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT64_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT64_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT64_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT64_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT64_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT64_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT64_SET_BUSY2_SHIFT 31 -/* POST_ROOT64_CLR Bit Fields */ -#define CCM_POST_ROOT64_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT64_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT64_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT64_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT64_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT64_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT64_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT64_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT64_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT64_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT64_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT64_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT64_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT64_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT64_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT64_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT64_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT64_CLR_BUSY2_SHIFT 31 -/* POST_ROOT64_TOG Bit Fields */ -#define CCM_POST_ROOT64_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT64_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT64_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT64_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT64_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT64_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT64_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT64_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT64_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT64_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT64_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT64_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT64_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT64_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT64_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT64_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT64_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT64_TOG_BUSY2_SHIFT 31 -/* PRE64 Bit Fields */ -#define CCM_PRE64_PRE_PODF_B_MASK 0x7u -#define CCM_PRE64_PRE_PODF_B_SHIFT 0 -#define CCM_PRE64_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE64_PRE_PODF_B_SHIFT))&CCM_PRE64_PRE_PODF_B_MASK) -#define CCM_PRE64_BUSY0_MASK 0x8u -#define CCM_PRE64_BUSY0_SHIFT 3 -#define CCM_PRE64_MUX_B_MASK 0x700u -#define CCM_PRE64_MUX_B_SHIFT 8 -#define CCM_PRE64_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE64_MUX_B_SHIFT))&CCM_PRE64_MUX_B_MASK) -#define CCM_PRE64_EN_B_MASK 0x1000u -#define CCM_PRE64_EN_B_SHIFT 12 -#define CCM_PRE64_BUSY1_MASK 0x8000u -#define CCM_PRE64_BUSY1_SHIFT 15 -#define CCM_PRE64_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE64_PRE_PODF_A_SHIFT 16 -#define CCM_PRE64_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE64_PRE_PODF_A_SHIFT))&CCM_PRE64_PRE_PODF_A_MASK) -#define CCM_PRE64_BUSY3_MASK 0x80000u -#define CCM_PRE64_BUSY3_SHIFT 19 -#define CCM_PRE64_MUX_A_MASK 0x7000000u -#define CCM_PRE64_MUX_A_SHIFT 24 -#define CCM_PRE64_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE64_MUX_A_SHIFT))&CCM_PRE64_MUX_A_MASK) -#define CCM_PRE64_EN_A_MASK 0x10000000u -#define CCM_PRE64_EN_A_SHIFT 28 -#define CCM_PRE64_BUSY4_MASK 0x80000000u -#define CCM_PRE64_BUSY4_SHIFT 31 -/* PRE_ROOT64_SET Bit Fields */ -#define CCM_PRE_ROOT64_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT64_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT64_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT64_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT64_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT64_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT64_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT64_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT64_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_SET_MUX_B_SHIFT))&CCM_PRE_ROOT64_SET_MUX_B_MASK) -#define CCM_PRE_ROOT64_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT64_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT64_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT64_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT64_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT64_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT64_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT64_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT64_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT64_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT64_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT64_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT64_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_SET_MUX_A_SHIFT))&CCM_PRE_ROOT64_SET_MUX_A_MASK) -#define CCM_PRE_ROOT64_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT64_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT64_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT64_SET_BUSY4_SHIFT 31 -/* PRE_ROOT64_CLR Bit Fields */ -#define CCM_PRE_ROOT64_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT64_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT64_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT64_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT64_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT64_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT64_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT64_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT64_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT64_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT64_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT64_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT64_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT64_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT64_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT64_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT64_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT64_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT64_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT64_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT64_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT64_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT64_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT64_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT64_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT64_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT64_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT64_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT64_TOG Bit Fields */ -#define CCM_PRE_ROOT64_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT64_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT64_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT64_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT64_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT64_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT64_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT64_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT64_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT64_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT64_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT64_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT64_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT64_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT64_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT64_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT64_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT64_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT64_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT64_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT64_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT64_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT64_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT64_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT64_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT64_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT64_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT64_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL64 Bit Fields */ -#define CCM_ACCESS_CTRL64_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL64_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL64_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL64_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL64_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL64_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL64_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL64_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL64_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL64_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL64_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL64_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL64_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL64_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL64_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL64_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL64_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL64_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL64_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL64_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL64_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL64_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL64_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL64_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL64_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL64_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL64_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL64_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL64_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL64_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL64_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL64_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL64_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL64_LOCK_SHIFT 31 -/* ACCESS_CTRL64_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL64_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL64_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL64_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL64_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL64_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL64_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL64_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL64_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL64_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL64_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL64_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL64_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL64_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL64_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL64_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL64_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT65 Bit Fields */ -#define CCM_TARGET_ROOT65_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT65_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT65_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_POST_PODF_SHIFT))&CCM_TARGET_ROOT65_POST_PODF_MASK) -#define CCM_TARGET_ROOT65_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT65_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT65_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT65_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT65_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT65_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT65_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT65_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT65_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT65_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT65_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_PRE_PODF_SHIFT))&CCM_TARGET_ROOT65_PRE_PODF_MASK) -#define CCM_TARGET_ROOT65_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT65_MUX_SHIFT 24 -#define CCM_TARGET_ROOT65_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_MUX_SHIFT))&CCM_TARGET_ROOT65_MUX_MASK) -#define CCM_TARGET_ROOT65_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT65_ENABLE_SHIFT 28 -/* TARGET_ROOT65_SET Bit Fields */ -#define CCM_TARGET_ROOT65_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT65_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT65_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT65_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT65_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT65_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT65_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT65_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT65_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT65_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT65_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT65_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT65_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT65_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT65_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT65_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT65_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT65_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT65_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_SET_MUX_SHIFT))&CCM_TARGET_ROOT65_SET_MUX_MASK) -#define CCM_TARGET_ROOT65_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT65_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT65_CLR Bit Fields */ -#define CCM_TARGET_ROOT65_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT65_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT65_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT65_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT65_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT65_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT65_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT65_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT65_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT65_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT65_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT65_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT65_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT65_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT65_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT65_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT65_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT65_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT65_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_CLR_MUX_SHIFT))&CCM_TARGET_ROOT65_CLR_MUX_MASK) -#define CCM_TARGET_ROOT65_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT65_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT65_TOG Bit Fields */ -#define CCM_TARGET_ROOT65_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT65_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT65_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT65_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT65_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT65_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT65_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT65_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT65_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT65_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT65_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT65_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT65_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT65_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT65_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT65_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT65_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT65_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT65_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_TOG_MUX_SHIFT))&CCM_TARGET_ROOT65_TOG_MUX_MASK) -#define CCM_TARGET_ROOT65_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT65_TOG_ENABLE_SHIFT 28 -/* POST65 Bit Fields */ -#define CCM_POST65_POST_PODF_MASK 0x3Fu -#define CCM_POST65_POST_PODF_SHIFT 0 -#define CCM_POST65_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST65_POST_PODF_SHIFT))&CCM_POST65_POST_PODF_MASK) -#define CCM_POST65_BUSY1_MASK 0x80u -#define CCM_POST65_BUSY1_SHIFT 7 -#define CCM_POST65_AUTO_PODF_MASK 0x700u -#define CCM_POST65_AUTO_PODF_SHIFT 8 -#define CCM_POST65_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST65_AUTO_PODF_SHIFT))&CCM_POST65_AUTO_PODF_MASK) -#define CCM_POST65_AUTO_EN_MASK 0x1000u -#define CCM_POST65_AUTO_EN_SHIFT 12 -#define CCM_POST65_SLOW_MASK 0x8000u -#define CCM_POST65_SLOW_SHIFT 15 -#define CCM_POST65_SELECT_MASK 0x10000000u -#define CCM_POST65_SELECT_SHIFT 28 -#define CCM_POST65_BUSY2_MASK 0x80000000u -#define CCM_POST65_BUSY2_SHIFT 31 -/* POST_ROOT65_SET Bit Fields */ -#define CCM_POST_ROOT65_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT65_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT65_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_SET_POST_PODF_SHIFT))&CCM_POST_ROOT65_SET_POST_PODF_MASK) -#define CCM_POST_ROOT65_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT65_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT65_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT65_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT65_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT65_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT65_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT65_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT65_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT65_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT65_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT65_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT65_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT65_SET_BUSY2_SHIFT 31 -/* POST_ROOT65_CLR Bit Fields */ -#define CCM_POST_ROOT65_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT65_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT65_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT65_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT65_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT65_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT65_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT65_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT65_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT65_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT65_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT65_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT65_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT65_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT65_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT65_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT65_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT65_CLR_BUSY2_SHIFT 31 -/* POST_ROOT65_TOG Bit Fields */ -#define CCM_POST_ROOT65_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT65_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT65_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT65_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT65_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT65_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT65_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT65_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT65_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT65_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT65_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT65_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT65_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT65_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT65_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT65_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT65_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT65_TOG_BUSY2_SHIFT 31 -/* PRE65 Bit Fields */ -#define CCM_PRE65_PRE_PODF_B_MASK 0x7u -#define CCM_PRE65_PRE_PODF_B_SHIFT 0 -#define CCM_PRE65_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE65_PRE_PODF_B_SHIFT))&CCM_PRE65_PRE_PODF_B_MASK) -#define CCM_PRE65_BUSY0_MASK 0x8u -#define CCM_PRE65_BUSY0_SHIFT 3 -#define CCM_PRE65_MUX_B_MASK 0x700u -#define CCM_PRE65_MUX_B_SHIFT 8 -#define CCM_PRE65_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE65_MUX_B_SHIFT))&CCM_PRE65_MUX_B_MASK) -#define CCM_PRE65_EN_B_MASK 0x1000u -#define CCM_PRE65_EN_B_SHIFT 12 -#define CCM_PRE65_BUSY1_MASK 0x8000u -#define CCM_PRE65_BUSY1_SHIFT 15 -#define CCM_PRE65_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE65_PRE_PODF_A_SHIFT 16 -#define CCM_PRE65_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE65_PRE_PODF_A_SHIFT))&CCM_PRE65_PRE_PODF_A_MASK) -#define CCM_PRE65_BUSY3_MASK 0x80000u -#define CCM_PRE65_BUSY3_SHIFT 19 -#define CCM_PRE65_MUX_A_MASK 0x7000000u -#define CCM_PRE65_MUX_A_SHIFT 24 -#define CCM_PRE65_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE65_MUX_A_SHIFT))&CCM_PRE65_MUX_A_MASK) -#define CCM_PRE65_EN_A_MASK 0x10000000u -#define CCM_PRE65_EN_A_SHIFT 28 -#define CCM_PRE65_BUSY4_MASK 0x80000000u -#define CCM_PRE65_BUSY4_SHIFT 31 -/* PRE_ROOT65_SET Bit Fields */ -#define CCM_PRE_ROOT65_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT65_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT65_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT65_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT65_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT65_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT65_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT65_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT65_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_SET_MUX_B_SHIFT))&CCM_PRE_ROOT65_SET_MUX_B_MASK) -#define CCM_PRE_ROOT65_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT65_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT65_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT65_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT65_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT65_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT65_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT65_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT65_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT65_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT65_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT65_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT65_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_SET_MUX_A_SHIFT))&CCM_PRE_ROOT65_SET_MUX_A_MASK) -#define CCM_PRE_ROOT65_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT65_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT65_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT65_SET_BUSY4_SHIFT 31 -/* PRE_ROOT65_CLR Bit Fields */ -#define CCM_PRE_ROOT65_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT65_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT65_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT65_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT65_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT65_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT65_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT65_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT65_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT65_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT65_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT65_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT65_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT65_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT65_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT65_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT65_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT65_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT65_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT65_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT65_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT65_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT65_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT65_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT65_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT65_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT65_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT65_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT65_TOG Bit Fields */ -#define CCM_PRE_ROOT65_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT65_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT65_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT65_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT65_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT65_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT65_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT65_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT65_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT65_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT65_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT65_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT65_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT65_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT65_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT65_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT65_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT65_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT65_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT65_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT65_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT65_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT65_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT65_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT65_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT65_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT65_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT65_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL65 Bit Fields */ -#define CCM_ACCESS_CTRL65_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL65_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL65_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL65_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL65_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL65_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL65_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL65_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL65_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL65_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL65_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL65_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL65_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL65_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL65_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL65_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL65_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL65_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL65_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL65_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL65_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL65_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL65_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL65_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL65_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL65_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL65_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL65_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL65_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL65_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL65_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL65_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL65_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL65_LOCK_SHIFT 31 -/* ACCESS_CTRL65_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL65_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL65_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL65_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL65_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL65_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL65_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL65_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL65_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL65_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL65_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL65_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL65_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL65_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL65_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL65_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL65_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT66 Bit Fields */ -#define CCM_TARGET_ROOT66_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT66_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT66_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_POST_PODF_SHIFT))&CCM_TARGET_ROOT66_POST_PODF_MASK) -#define CCM_TARGET_ROOT66_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT66_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT66_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT66_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT66_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT66_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT66_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT66_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT66_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT66_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT66_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_PRE_PODF_SHIFT))&CCM_TARGET_ROOT66_PRE_PODF_MASK) -#define CCM_TARGET_ROOT66_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT66_MUX_SHIFT 24 -#define CCM_TARGET_ROOT66_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_MUX_SHIFT))&CCM_TARGET_ROOT66_MUX_MASK) -#define CCM_TARGET_ROOT66_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT66_ENABLE_SHIFT 28 -/* TARGET_ROOT66_SET Bit Fields */ -#define CCM_TARGET_ROOT66_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT66_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT66_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT66_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT66_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT66_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT66_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT66_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT66_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT66_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT66_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT66_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT66_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT66_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT66_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT66_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT66_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT66_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT66_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_SET_MUX_SHIFT))&CCM_TARGET_ROOT66_SET_MUX_MASK) -#define CCM_TARGET_ROOT66_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT66_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT66_CLR Bit Fields */ -#define CCM_TARGET_ROOT66_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT66_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT66_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT66_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT66_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT66_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT66_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT66_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT66_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT66_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT66_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT66_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT66_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT66_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT66_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT66_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT66_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT66_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT66_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_CLR_MUX_SHIFT))&CCM_TARGET_ROOT66_CLR_MUX_MASK) -#define CCM_TARGET_ROOT66_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT66_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT66_TOG Bit Fields */ -#define CCM_TARGET_ROOT66_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT66_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT66_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT66_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT66_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT66_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT66_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT66_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT66_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT66_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT66_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT66_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT66_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT66_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT66_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT66_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT66_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT66_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT66_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_TOG_MUX_SHIFT))&CCM_TARGET_ROOT66_TOG_MUX_MASK) -#define CCM_TARGET_ROOT66_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT66_TOG_ENABLE_SHIFT 28 -/* POST66 Bit Fields */ -#define CCM_POST66_POST_PODF_MASK 0x3Fu -#define CCM_POST66_POST_PODF_SHIFT 0 -#define CCM_POST66_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST66_POST_PODF_SHIFT))&CCM_POST66_POST_PODF_MASK) -#define CCM_POST66_BUSY1_MASK 0x80u -#define CCM_POST66_BUSY1_SHIFT 7 -#define CCM_POST66_AUTO_PODF_MASK 0x700u -#define CCM_POST66_AUTO_PODF_SHIFT 8 -#define CCM_POST66_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST66_AUTO_PODF_SHIFT))&CCM_POST66_AUTO_PODF_MASK) -#define CCM_POST66_AUTO_EN_MASK 0x1000u -#define CCM_POST66_AUTO_EN_SHIFT 12 -#define CCM_POST66_SLOW_MASK 0x8000u -#define CCM_POST66_SLOW_SHIFT 15 -#define CCM_POST66_SELECT_MASK 0x10000000u -#define CCM_POST66_SELECT_SHIFT 28 -#define CCM_POST66_BUSY2_MASK 0x80000000u -#define CCM_POST66_BUSY2_SHIFT 31 -/* POST_ROOT66_SET Bit Fields */ -#define CCM_POST_ROOT66_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT66_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT66_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_SET_POST_PODF_SHIFT))&CCM_POST_ROOT66_SET_POST_PODF_MASK) -#define CCM_POST_ROOT66_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT66_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT66_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT66_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT66_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT66_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT66_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT66_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT66_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT66_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT66_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT66_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT66_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT66_SET_BUSY2_SHIFT 31 -/* POST_ROOT66_CLR Bit Fields */ -#define CCM_POST_ROOT66_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT66_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT66_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT66_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT66_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT66_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT66_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT66_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT66_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT66_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT66_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT66_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT66_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT66_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT66_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT66_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT66_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT66_CLR_BUSY2_SHIFT 31 -/* POST_ROOT66_TOG Bit Fields */ -#define CCM_POST_ROOT66_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT66_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT66_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT66_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT66_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT66_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT66_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT66_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT66_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT66_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT66_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT66_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT66_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT66_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT66_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT66_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT66_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT66_TOG_BUSY2_SHIFT 31 -/* PRE66 Bit Fields */ -#define CCM_PRE66_PRE_PODF_B_MASK 0x7u -#define CCM_PRE66_PRE_PODF_B_SHIFT 0 -#define CCM_PRE66_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE66_PRE_PODF_B_SHIFT))&CCM_PRE66_PRE_PODF_B_MASK) -#define CCM_PRE66_BUSY0_MASK 0x8u -#define CCM_PRE66_BUSY0_SHIFT 3 -#define CCM_PRE66_MUX_B_MASK 0x700u -#define CCM_PRE66_MUX_B_SHIFT 8 -#define CCM_PRE66_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE66_MUX_B_SHIFT))&CCM_PRE66_MUX_B_MASK) -#define CCM_PRE66_EN_B_MASK 0x1000u -#define CCM_PRE66_EN_B_SHIFT 12 -#define CCM_PRE66_BUSY1_MASK 0x8000u -#define CCM_PRE66_BUSY1_SHIFT 15 -#define CCM_PRE66_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE66_PRE_PODF_A_SHIFT 16 -#define CCM_PRE66_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE66_PRE_PODF_A_SHIFT))&CCM_PRE66_PRE_PODF_A_MASK) -#define CCM_PRE66_BUSY3_MASK 0x80000u -#define CCM_PRE66_BUSY3_SHIFT 19 -#define CCM_PRE66_MUX_A_MASK 0x7000000u -#define CCM_PRE66_MUX_A_SHIFT 24 -#define CCM_PRE66_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE66_MUX_A_SHIFT))&CCM_PRE66_MUX_A_MASK) -#define CCM_PRE66_EN_A_MASK 0x10000000u -#define CCM_PRE66_EN_A_SHIFT 28 -#define CCM_PRE66_BUSY4_MASK 0x80000000u -#define CCM_PRE66_BUSY4_SHIFT 31 -/* PRE_ROOT66_SET Bit Fields */ -#define CCM_PRE_ROOT66_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT66_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT66_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT66_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT66_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT66_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT66_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT66_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT66_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_SET_MUX_B_SHIFT))&CCM_PRE_ROOT66_SET_MUX_B_MASK) -#define CCM_PRE_ROOT66_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT66_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT66_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT66_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT66_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT66_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT66_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT66_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT66_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT66_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT66_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT66_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT66_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_SET_MUX_A_SHIFT))&CCM_PRE_ROOT66_SET_MUX_A_MASK) -#define CCM_PRE_ROOT66_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT66_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT66_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT66_SET_BUSY4_SHIFT 31 -/* PRE_ROOT66_CLR Bit Fields */ -#define CCM_PRE_ROOT66_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT66_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT66_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT66_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT66_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT66_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT66_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT66_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT66_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT66_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT66_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT66_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT66_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT66_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT66_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT66_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT66_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT66_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT66_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT66_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT66_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT66_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT66_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT66_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT66_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT66_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT66_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT66_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT66_TOG Bit Fields */ -#define CCM_PRE_ROOT66_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT66_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT66_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT66_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT66_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT66_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT66_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT66_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT66_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT66_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT66_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT66_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT66_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT66_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT66_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT66_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT66_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT66_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT66_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT66_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT66_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT66_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT66_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT66_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT66_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT66_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT66_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT66_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL66 Bit Fields */ -#define CCM_ACCESS_CTRL66_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL66_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL66_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL66_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL66_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL66_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL66_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL66_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL66_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL66_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL66_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL66_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL66_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL66_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL66_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL66_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL66_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL66_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL66_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL66_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL66_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL66_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL66_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL66_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL66_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL66_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL66_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL66_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL66_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL66_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL66_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL66_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL66_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL66_LOCK_SHIFT 31 -/* ACCESS_CTRL66_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL66_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL66_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL66_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL66_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL66_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL66_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL66_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL66_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL66_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL66_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL66_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL66_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL66_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL66_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL66_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL66_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT67 Bit Fields */ -#define CCM_TARGET_ROOT67_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT67_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT67_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_POST_PODF_SHIFT))&CCM_TARGET_ROOT67_POST_PODF_MASK) -#define CCM_TARGET_ROOT67_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT67_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT67_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT67_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT67_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT67_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT67_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT67_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT67_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT67_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT67_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_PRE_PODF_SHIFT))&CCM_TARGET_ROOT67_PRE_PODF_MASK) -#define CCM_TARGET_ROOT67_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT67_MUX_SHIFT 24 -#define CCM_TARGET_ROOT67_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_MUX_SHIFT))&CCM_TARGET_ROOT67_MUX_MASK) -#define CCM_TARGET_ROOT67_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT67_ENABLE_SHIFT 28 -/* TARGET_ROOT67_SET Bit Fields */ -#define CCM_TARGET_ROOT67_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT67_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT67_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT67_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT67_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT67_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT67_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT67_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT67_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT67_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT67_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT67_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT67_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT67_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT67_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT67_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT67_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT67_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT67_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_SET_MUX_SHIFT))&CCM_TARGET_ROOT67_SET_MUX_MASK) -#define CCM_TARGET_ROOT67_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT67_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT67_CLR Bit Fields */ -#define CCM_TARGET_ROOT67_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT67_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT67_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT67_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT67_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT67_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT67_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT67_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT67_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT67_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT67_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT67_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT67_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT67_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT67_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT67_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT67_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT67_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT67_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_CLR_MUX_SHIFT))&CCM_TARGET_ROOT67_CLR_MUX_MASK) -#define CCM_TARGET_ROOT67_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT67_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT67_TOG Bit Fields */ -#define CCM_TARGET_ROOT67_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT67_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT67_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT67_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT67_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT67_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT67_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT67_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT67_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT67_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT67_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT67_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT67_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT67_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT67_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT67_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT67_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT67_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT67_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_TOG_MUX_SHIFT))&CCM_TARGET_ROOT67_TOG_MUX_MASK) -#define CCM_TARGET_ROOT67_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT67_TOG_ENABLE_SHIFT 28 -/* POST67 Bit Fields */ -#define CCM_POST67_POST_PODF_MASK 0x3Fu -#define CCM_POST67_POST_PODF_SHIFT 0 -#define CCM_POST67_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST67_POST_PODF_SHIFT))&CCM_POST67_POST_PODF_MASK) -#define CCM_POST67_BUSY1_MASK 0x80u -#define CCM_POST67_BUSY1_SHIFT 7 -#define CCM_POST67_AUTO_PODF_MASK 0x700u -#define CCM_POST67_AUTO_PODF_SHIFT 8 -#define CCM_POST67_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST67_AUTO_PODF_SHIFT))&CCM_POST67_AUTO_PODF_MASK) -#define CCM_POST67_AUTO_EN_MASK 0x1000u -#define CCM_POST67_AUTO_EN_SHIFT 12 -#define CCM_POST67_SLOW_MASK 0x8000u -#define CCM_POST67_SLOW_SHIFT 15 -#define CCM_POST67_SELECT_MASK 0x10000000u -#define CCM_POST67_SELECT_SHIFT 28 -#define CCM_POST67_BUSY2_MASK 0x80000000u -#define CCM_POST67_BUSY2_SHIFT 31 -/* POST_ROOT67_SET Bit Fields */ -#define CCM_POST_ROOT67_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT67_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT67_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_SET_POST_PODF_SHIFT))&CCM_POST_ROOT67_SET_POST_PODF_MASK) -#define CCM_POST_ROOT67_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT67_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT67_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT67_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT67_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT67_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT67_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT67_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT67_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT67_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT67_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT67_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT67_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT67_SET_BUSY2_SHIFT 31 -/* POST_ROOT67_CLR Bit Fields */ -#define CCM_POST_ROOT67_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT67_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT67_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT67_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT67_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT67_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT67_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT67_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT67_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT67_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT67_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT67_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT67_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT67_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT67_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT67_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT67_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT67_CLR_BUSY2_SHIFT 31 -/* POST_ROOT67_TOG Bit Fields */ -#define CCM_POST_ROOT67_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT67_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT67_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT67_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT67_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT67_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT67_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT67_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT67_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT67_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT67_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT67_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT67_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT67_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT67_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT67_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT67_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT67_TOG_BUSY2_SHIFT 31 -/* PRE67 Bit Fields */ -#define CCM_PRE67_PRE_PODF_B_MASK 0x7u -#define CCM_PRE67_PRE_PODF_B_SHIFT 0 -#define CCM_PRE67_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE67_PRE_PODF_B_SHIFT))&CCM_PRE67_PRE_PODF_B_MASK) -#define CCM_PRE67_BUSY0_MASK 0x8u -#define CCM_PRE67_BUSY0_SHIFT 3 -#define CCM_PRE67_MUX_B_MASK 0x700u -#define CCM_PRE67_MUX_B_SHIFT 8 -#define CCM_PRE67_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE67_MUX_B_SHIFT))&CCM_PRE67_MUX_B_MASK) -#define CCM_PRE67_EN_B_MASK 0x1000u -#define CCM_PRE67_EN_B_SHIFT 12 -#define CCM_PRE67_BUSY1_MASK 0x8000u -#define CCM_PRE67_BUSY1_SHIFT 15 -#define CCM_PRE67_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE67_PRE_PODF_A_SHIFT 16 -#define CCM_PRE67_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE67_PRE_PODF_A_SHIFT))&CCM_PRE67_PRE_PODF_A_MASK) -#define CCM_PRE67_BUSY3_MASK 0x80000u -#define CCM_PRE67_BUSY3_SHIFT 19 -#define CCM_PRE67_MUX_A_MASK 0x7000000u -#define CCM_PRE67_MUX_A_SHIFT 24 -#define CCM_PRE67_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE67_MUX_A_SHIFT))&CCM_PRE67_MUX_A_MASK) -#define CCM_PRE67_EN_A_MASK 0x10000000u -#define CCM_PRE67_EN_A_SHIFT 28 -#define CCM_PRE67_BUSY4_MASK 0x80000000u -#define CCM_PRE67_BUSY4_SHIFT 31 -/* PRE_ROOT67_SET Bit Fields */ -#define CCM_PRE_ROOT67_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT67_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT67_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT67_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT67_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT67_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT67_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT67_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT67_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_SET_MUX_B_SHIFT))&CCM_PRE_ROOT67_SET_MUX_B_MASK) -#define CCM_PRE_ROOT67_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT67_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT67_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT67_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT67_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT67_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT67_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT67_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT67_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT67_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT67_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT67_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT67_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_SET_MUX_A_SHIFT))&CCM_PRE_ROOT67_SET_MUX_A_MASK) -#define CCM_PRE_ROOT67_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT67_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT67_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT67_SET_BUSY4_SHIFT 31 -/* PRE_ROOT67_CLR Bit Fields */ -#define CCM_PRE_ROOT67_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT67_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT67_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT67_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT67_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT67_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT67_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT67_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT67_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT67_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT67_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT67_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT67_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT67_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT67_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT67_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT67_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT67_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT67_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT67_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT67_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT67_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT67_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT67_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT67_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT67_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT67_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT67_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT67_TOG Bit Fields */ -#define CCM_PRE_ROOT67_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT67_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT67_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT67_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT67_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT67_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT67_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT67_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT67_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT67_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT67_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT67_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT67_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT67_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT67_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT67_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT67_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT67_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT67_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT67_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT67_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT67_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT67_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT67_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT67_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT67_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT67_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT67_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL67 Bit Fields */ -#define CCM_ACCESS_CTRL67_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL67_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL67_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL67_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL67_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL67_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL67_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL67_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL67_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL67_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL67_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL67_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL67_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL67_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL67_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL67_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL67_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL67_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL67_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL67_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL67_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL67_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL67_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL67_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL67_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL67_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL67_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL67_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL67_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL67_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL67_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL67_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL67_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL67_LOCK_SHIFT 31 -/* ACCESS_CTRL67_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL67_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL67_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL67_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL67_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL67_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL67_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL67_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL67_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL67_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL67_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL67_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL67_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL67_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL67_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL67_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL67_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT68 Bit Fields */ -#define CCM_TARGET_ROOT68_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT68_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT68_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_POST_PODF_SHIFT))&CCM_TARGET_ROOT68_POST_PODF_MASK) -#define CCM_TARGET_ROOT68_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT68_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT68_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT68_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT68_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT68_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT68_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT68_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT68_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT68_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT68_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_PRE_PODF_SHIFT))&CCM_TARGET_ROOT68_PRE_PODF_MASK) -#define CCM_TARGET_ROOT68_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT68_MUX_SHIFT 24 -#define CCM_TARGET_ROOT68_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_MUX_SHIFT))&CCM_TARGET_ROOT68_MUX_MASK) -#define CCM_TARGET_ROOT68_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT68_ENABLE_SHIFT 28 -/* TARGET_ROOT68_SET Bit Fields */ -#define CCM_TARGET_ROOT68_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT68_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT68_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT68_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT68_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT68_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT68_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT68_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT68_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT68_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT68_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT68_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT68_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT68_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT68_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT68_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT68_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT68_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT68_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_SET_MUX_SHIFT))&CCM_TARGET_ROOT68_SET_MUX_MASK) -#define CCM_TARGET_ROOT68_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT68_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT68_CLR Bit Fields */ -#define CCM_TARGET_ROOT68_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT68_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT68_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT68_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT68_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT68_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT68_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT68_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT68_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT68_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT68_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT68_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT68_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT68_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT68_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT68_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT68_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT68_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT68_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_CLR_MUX_SHIFT))&CCM_TARGET_ROOT68_CLR_MUX_MASK) -#define CCM_TARGET_ROOT68_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT68_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT68_TOG Bit Fields */ -#define CCM_TARGET_ROOT68_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT68_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT68_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT68_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT68_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT68_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT68_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT68_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT68_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT68_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT68_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT68_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT68_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT68_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT68_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT68_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT68_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT68_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT68_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_TOG_MUX_SHIFT))&CCM_TARGET_ROOT68_TOG_MUX_MASK) -#define CCM_TARGET_ROOT68_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT68_TOG_ENABLE_SHIFT 28 -/* POST68 Bit Fields */ -#define CCM_POST68_POST_PODF_MASK 0x3Fu -#define CCM_POST68_POST_PODF_SHIFT 0 -#define CCM_POST68_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST68_POST_PODF_SHIFT))&CCM_POST68_POST_PODF_MASK) -#define CCM_POST68_BUSY1_MASK 0x80u -#define CCM_POST68_BUSY1_SHIFT 7 -#define CCM_POST68_AUTO_PODF_MASK 0x700u -#define CCM_POST68_AUTO_PODF_SHIFT 8 -#define CCM_POST68_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST68_AUTO_PODF_SHIFT))&CCM_POST68_AUTO_PODF_MASK) -#define CCM_POST68_AUTO_EN_MASK 0x1000u -#define CCM_POST68_AUTO_EN_SHIFT 12 -#define CCM_POST68_SLOW_MASK 0x8000u -#define CCM_POST68_SLOW_SHIFT 15 -#define CCM_POST68_SELECT_MASK 0x10000000u -#define CCM_POST68_SELECT_SHIFT 28 -#define CCM_POST68_BUSY2_MASK 0x80000000u -#define CCM_POST68_BUSY2_SHIFT 31 -/* POST_ROOT68_SET Bit Fields */ -#define CCM_POST_ROOT68_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT68_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT68_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_SET_POST_PODF_SHIFT))&CCM_POST_ROOT68_SET_POST_PODF_MASK) -#define CCM_POST_ROOT68_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT68_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT68_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT68_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT68_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT68_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT68_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT68_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT68_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT68_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT68_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT68_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT68_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT68_SET_BUSY2_SHIFT 31 -/* POST_ROOT68_CLR Bit Fields */ -#define CCM_POST_ROOT68_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT68_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT68_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT68_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT68_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT68_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT68_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT68_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT68_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT68_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT68_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT68_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT68_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT68_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT68_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT68_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT68_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT68_CLR_BUSY2_SHIFT 31 -/* POST_ROOT68_TOG Bit Fields */ -#define CCM_POST_ROOT68_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT68_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT68_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT68_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT68_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT68_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT68_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT68_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT68_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT68_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT68_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT68_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT68_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT68_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT68_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT68_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT68_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT68_TOG_BUSY2_SHIFT 31 -/* PRE68 Bit Fields */ -#define CCM_PRE68_PRE_PODF_B_MASK 0x7u -#define CCM_PRE68_PRE_PODF_B_SHIFT 0 -#define CCM_PRE68_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE68_PRE_PODF_B_SHIFT))&CCM_PRE68_PRE_PODF_B_MASK) -#define CCM_PRE68_BUSY0_MASK 0x8u -#define CCM_PRE68_BUSY0_SHIFT 3 -#define CCM_PRE68_MUX_B_MASK 0x700u -#define CCM_PRE68_MUX_B_SHIFT 8 -#define CCM_PRE68_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE68_MUX_B_SHIFT))&CCM_PRE68_MUX_B_MASK) -#define CCM_PRE68_EN_B_MASK 0x1000u -#define CCM_PRE68_EN_B_SHIFT 12 -#define CCM_PRE68_BUSY1_MASK 0x8000u -#define CCM_PRE68_BUSY1_SHIFT 15 -#define CCM_PRE68_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE68_PRE_PODF_A_SHIFT 16 -#define CCM_PRE68_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE68_PRE_PODF_A_SHIFT))&CCM_PRE68_PRE_PODF_A_MASK) -#define CCM_PRE68_BUSY3_MASK 0x80000u -#define CCM_PRE68_BUSY3_SHIFT 19 -#define CCM_PRE68_MUX_A_MASK 0x7000000u -#define CCM_PRE68_MUX_A_SHIFT 24 -#define CCM_PRE68_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE68_MUX_A_SHIFT))&CCM_PRE68_MUX_A_MASK) -#define CCM_PRE68_EN_A_MASK 0x10000000u -#define CCM_PRE68_EN_A_SHIFT 28 -#define CCM_PRE68_BUSY4_MASK 0x80000000u -#define CCM_PRE68_BUSY4_SHIFT 31 -/* PRE_ROOT68_SET Bit Fields */ -#define CCM_PRE_ROOT68_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT68_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT68_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT68_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT68_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT68_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT68_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT68_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT68_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_SET_MUX_B_SHIFT))&CCM_PRE_ROOT68_SET_MUX_B_MASK) -#define CCM_PRE_ROOT68_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT68_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT68_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT68_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT68_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT68_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT68_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT68_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT68_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT68_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT68_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT68_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT68_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_SET_MUX_A_SHIFT))&CCM_PRE_ROOT68_SET_MUX_A_MASK) -#define CCM_PRE_ROOT68_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT68_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT68_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT68_SET_BUSY4_SHIFT 31 -/* PRE_ROOT68_CLR Bit Fields */ -#define CCM_PRE_ROOT68_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT68_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT68_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT68_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT68_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT68_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT68_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT68_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT68_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT68_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT68_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT68_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT68_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT68_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT68_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT68_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT68_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT68_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT68_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT68_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT68_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT68_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT68_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT68_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT68_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT68_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT68_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT68_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT68_TOG Bit Fields */ -#define CCM_PRE_ROOT68_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT68_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT68_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT68_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT68_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT68_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT68_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT68_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT68_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT68_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT68_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT68_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT68_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT68_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT68_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT68_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT68_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT68_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT68_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT68_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT68_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT68_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT68_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT68_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT68_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT68_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT68_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT68_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL68 Bit Fields */ -#define CCM_ACCESS_CTRL68_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL68_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL68_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL68_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL68_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL68_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL68_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL68_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL68_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL68_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL68_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL68_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL68_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL68_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL68_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL68_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL68_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL68_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL68_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL68_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL68_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL68_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL68_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL68_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL68_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL68_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL68_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL68_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL68_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL68_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL68_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL68_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL68_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL68_LOCK_SHIFT 31 -/* ACCESS_CTRL68_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL68_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL68_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL68_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL68_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL68_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL68_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL68_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL68_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL68_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL68_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL68_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL68_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL68_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL68_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL68_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL68_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT69 Bit Fields */ -#define CCM_TARGET_ROOT69_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT69_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT69_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_POST_PODF_SHIFT))&CCM_TARGET_ROOT69_POST_PODF_MASK) -#define CCM_TARGET_ROOT69_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT69_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT69_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT69_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT69_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT69_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT69_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT69_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT69_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT69_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT69_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_PRE_PODF_SHIFT))&CCM_TARGET_ROOT69_PRE_PODF_MASK) -#define CCM_TARGET_ROOT69_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT69_MUX_SHIFT 24 -#define CCM_TARGET_ROOT69_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_MUX_SHIFT))&CCM_TARGET_ROOT69_MUX_MASK) -#define CCM_TARGET_ROOT69_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT69_ENABLE_SHIFT 28 -/* TARGET_ROOT69_SET Bit Fields */ -#define CCM_TARGET_ROOT69_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT69_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT69_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT69_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT69_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT69_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT69_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT69_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT69_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT69_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT69_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT69_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT69_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT69_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT69_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT69_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT69_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT69_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT69_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_SET_MUX_SHIFT))&CCM_TARGET_ROOT69_SET_MUX_MASK) -#define CCM_TARGET_ROOT69_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT69_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT69_CLR Bit Fields */ -#define CCM_TARGET_ROOT69_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT69_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT69_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT69_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT69_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT69_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT69_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT69_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT69_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT69_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT69_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT69_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT69_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT69_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT69_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT69_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT69_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT69_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT69_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_CLR_MUX_SHIFT))&CCM_TARGET_ROOT69_CLR_MUX_MASK) -#define CCM_TARGET_ROOT69_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT69_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT69_TOG Bit Fields */ -#define CCM_TARGET_ROOT69_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT69_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT69_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT69_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT69_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT69_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT69_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT69_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT69_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT69_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT69_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT69_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT69_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT69_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT69_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT69_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT69_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT69_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT69_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_TOG_MUX_SHIFT))&CCM_TARGET_ROOT69_TOG_MUX_MASK) -#define CCM_TARGET_ROOT69_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT69_TOG_ENABLE_SHIFT 28 -/* POST69 Bit Fields */ -#define CCM_POST69_POST_PODF_MASK 0x3Fu -#define CCM_POST69_POST_PODF_SHIFT 0 -#define CCM_POST69_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST69_POST_PODF_SHIFT))&CCM_POST69_POST_PODF_MASK) -#define CCM_POST69_BUSY1_MASK 0x80u -#define CCM_POST69_BUSY1_SHIFT 7 -#define CCM_POST69_AUTO_PODF_MASK 0x700u -#define CCM_POST69_AUTO_PODF_SHIFT 8 -#define CCM_POST69_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST69_AUTO_PODF_SHIFT))&CCM_POST69_AUTO_PODF_MASK) -#define CCM_POST69_AUTO_EN_MASK 0x1000u -#define CCM_POST69_AUTO_EN_SHIFT 12 -#define CCM_POST69_SLOW_MASK 0x8000u -#define CCM_POST69_SLOW_SHIFT 15 -#define CCM_POST69_SELECT_MASK 0x10000000u -#define CCM_POST69_SELECT_SHIFT 28 -#define CCM_POST69_BUSY2_MASK 0x80000000u -#define CCM_POST69_BUSY2_SHIFT 31 -/* POST_ROOT69_SET Bit Fields */ -#define CCM_POST_ROOT69_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT69_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT69_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_SET_POST_PODF_SHIFT))&CCM_POST_ROOT69_SET_POST_PODF_MASK) -#define CCM_POST_ROOT69_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT69_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT69_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT69_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT69_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT69_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT69_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT69_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT69_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT69_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT69_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT69_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT69_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT69_SET_BUSY2_SHIFT 31 -/* POST_ROOT69_CLR Bit Fields */ -#define CCM_POST_ROOT69_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT69_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT69_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT69_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT69_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT69_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT69_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT69_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT69_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT69_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT69_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT69_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT69_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT69_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT69_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT69_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT69_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT69_CLR_BUSY2_SHIFT 31 -/* POST_ROOT69_TOG Bit Fields */ -#define CCM_POST_ROOT69_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT69_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT69_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT69_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT69_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT69_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT69_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT69_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT69_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT69_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT69_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT69_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT69_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT69_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT69_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT69_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT69_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT69_TOG_BUSY2_SHIFT 31 -/* PRE69 Bit Fields */ -#define CCM_PRE69_PRE_PODF_B_MASK 0x7u -#define CCM_PRE69_PRE_PODF_B_SHIFT 0 -#define CCM_PRE69_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE69_PRE_PODF_B_SHIFT))&CCM_PRE69_PRE_PODF_B_MASK) -#define CCM_PRE69_BUSY0_MASK 0x8u -#define CCM_PRE69_BUSY0_SHIFT 3 -#define CCM_PRE69_MUX_B_MASK 0x700u -#define CCM_PRE69_MUX_B_SHIFT 8 -#define CCM_PRE69_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE69_MUX_B_SHIFT))&CCM_PRE69_MUX_B_MASK) -#define CCM_PRE69_EN_B_MASK 0x1000u -#define CCM_PRE69_EN_B_SHIFT 12 -#define CCM_PRE69_BUSY1_MASK 0x8000u -#define CCM_PRE69_BUSY1_SHIFT 15 -#define CCM_PRE69_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE69_PRE_PODF_A_SHIFT 16 -#define CCM_PRE69_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE69_PRE_PODF_A_SHIFT))&CCM_PRE69_PRE_PODF_A_MASK) -#define CCM_PRE69_BUSY3_MASK 0x80000u -#define CCM_PRE69_BUSY3_SHIFT 19 -#define CCM_PRE69_MUX_A_MASK 0x7000000u -#define CCM_PRE69_MUX_A_SHIFT 24 -#define CCM_PRE69_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE69_MUX_A_SHIFT))&CCM_PRE69_MUX_A_MASK) -#define CCM_PRE69_EN_A_MASK 0x10000000u -#define CCM_PRE69_EN_A_SHIFT 28 -#define CCM_PRE69_BUSY4_MASK 0x80000000u -#define CCM_PRE69_BUSY4_SHIFT 31 -/* PRE_ROOT69_SET Bit Fields */ -#define CCM_PRE_ROOT69_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT69_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT69_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT69_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT69_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT69_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT69_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT69_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT69_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_SET_MUX_B_SHIFT))&CCM_PRE_ROOT69_SET_MUX_B_MASK) -#define CCM_PRE_ROOT69_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT69_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT69_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT69_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT69_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT69_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT69_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT69_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT69_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT69_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT69_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT69_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT69_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_SET_MUX_A_SHIFT))&CCM_PRE_ROOT69_SET_MUX_A_MASK) -#define CCM_PRE_ROOT69_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT69_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT69_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT69_SET_BUSY4_SHIFT 31 -/* PRE_ROOT69_CLR Bit Fields */ -#define CCM_PRE_ROOT69_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT69_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT69_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT69_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT69_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT69_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT69_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT69_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT69_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT69_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT69_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT69_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT69_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT69_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT69_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT69_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT69_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT69_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT69_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT69_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT69_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT69_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT69_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT69_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT69_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT69_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT69_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT69_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT69_TOG Bit Fields */ -#define CCM_PRE_ROOT69_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT69_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT69_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT69_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT69_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT69_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT69_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT69_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT69_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT69_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT69_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT69_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT69_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT69_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT69_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT69_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT69_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT69_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT69_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT69_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT69_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT69_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT69_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT69_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT69_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT69_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT69_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT69_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL69 Bit Fields */ -#define CCM_ACCESS_CTRL69_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL69_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL69_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL69_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL69_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL69_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL69_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL69_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL69_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL69_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL69_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL69_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL69_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL69_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL69_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL69_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL69_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL69_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL69_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL69_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL69_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL69_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL69_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL69_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL69_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL69_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL69_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL69_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL69_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL69_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL69_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL69_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL69_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL69_LOCK_SHIFT 31 -/* ACCESS_CTRL69_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL69_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL69_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL69_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL69_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL69_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL69_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL69_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL69_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL69_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL69_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL69_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL69_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL69_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL69_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL69_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL69_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT70 Bit Fields */ -#define CCM_TARGET_ROOT70_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT70_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT70_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_POST_PODF_SHIFT))&CCM_TARGET_ROOT70_POST_PODF_MASK) -#define CCM_TARGET_ROOT70_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT70_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT70_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT70_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT70_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT70_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT70_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT70_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT70_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT70_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT70_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_PRE_PODF_SHIFT))&CCM_TARGET_ROOT70_PRE_PODF_MASK) -#define CCM_TARGET_ROOT70_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT70_MUX_SHIFT 24 -#define CCM_TARGET_ROOT70_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_MUX_SHIFT))&CCM_TARGET_ROOT70_MUX_MASK) -#define CCM_TARGET_ROOT70_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT70_ENABLE_SHIFT 28 -/* TARGET_ROOT70_SET Bit Fields */ -#define CCM_TARGET_ROOT70_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT70_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT70_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT70_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT70_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT70_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT70_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT70_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT70_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT70_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT70_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT70_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT70_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT70_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT70_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT70_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT70_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT70_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT70_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_SET_MUX_SHIFT))&CCM_TARGET_ROOT70_SET_MUX_MASK) -#define CCM_TARGET_ROOT70_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT70_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT70_CLR Bit Fields */ -#define CCM_TARGET_ROOT70_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT70_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT70_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT70_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT70_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT70_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT70_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT70_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT70_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT70_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT70_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT70_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT70_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT70_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT70_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT70_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT70_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT70_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT70_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_CLR_MUX_SHIFT))&CCM_TARGET_ROOT70_CLR_MUX_MASK) -#define CCM_TARGET_ROOT70_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT70_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT70_TOG Bit Fields */ -#define CCM_TARGET_ROOT70_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT70_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT70_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT70_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT70_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT70_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT70_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT70_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT70_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT70_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT70_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT70_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT70_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT70_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT70_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT70_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT70_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT70_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT70_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_TOG_MUX_SHIFT))&CCM_TARGET_ROOT70_TOG_MUX_MASK) -#define CCM_TARGET_ROOT70_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT70_TOG_ENABLE_SHIFT 28 -/* POST70 Bit Fields */ -#define CCM_POST70_POST_PODF_MASK 0x3Fu -#define CCM_POST70_POST_PODF_SHIFT 0 -#define CCM_POST70_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST70_POST_PODF_SHIFT))&CCM_POST70_POST_PODF_MASK) -#define CCM_POST70_BUSY1_MASK 0x80u -#define CCM_POST70_BUSY1_SHIFT 7 -#define CCM_POST70_AUTO_PODF_MASK 0x700u -#define CCM_POST70_AUTO_PODF_SHIFT 8 -#define CCM_POST70_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST70_AUTO_PODF_SHIFT))&CCM_POST70_AUTO_PODF_MASK) -#define CCM_POST70_AUTO_EN_MASK 0x1000u -#define CCM_POST70_AUTO_EN_SHIFT 12 -#define CCM_POST70_SLOW_MASK 0x8000u -#define CCM_POST70_SLOW_SHIFT 15 -#define CCM_POST70_SELECT_MASK 0x10000000u -#define CCM_POST70_SELECT_SHIFT 28 -#define CCM_POST70_BUSY2_MASK 0x80000000u -#define CCM_POST70_BUSY2_SHIFT 31 -/* POST_ROOT70_SET Bit Fields */ -#define CCM_POST_ROOT70_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT70_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT70_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_SET_POST_PODF_SHIFT))&CCM_POST_ROOT70_SET_POST_PODF_MASK) -#define CCM_POST_ROOT70_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT70_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT70_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT70_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT70_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT70_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT70_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT70_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT70_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT70_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT70_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT70_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT70_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT70_SET_BUSY2_SHIFT 31 -/* POST_ROOT70_CLR Bit Fields */ -#define CCM_POST_ROOT70_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT70_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT70_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT70_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT70_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT70_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT70_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT70_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT70_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT70_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT70_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT70_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT70_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT70_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT70_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT70_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT70_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT70_CLR_BUSY2_SHIFT 31 -/* POST_ROOT70_TOG Bit Fields */ -#define CCM_POST_ROOT70_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT70_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT70_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT70_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT70_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT70_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT70_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT70_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT70_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT70_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT70_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT70_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT70_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT70_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT70_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT70_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT70_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT70_TOG_BUSY2_SHIFT 31 -/* PRE70 Bit Fields */ -#define CCM_PRE70_PRE_PODF_B_MASK 0x7u -#define CCM_PRE70_PRE_PODF_B_SHIFT 0 -#define CCM_PRE70_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE70_PRE_PODF_B_SHIFT))&CCM_PRE70_PRE_PODF_B_MASK) -#define CCM_PRE70_BUSY0_MASK 0x8u -#define CCM_PRE70_BUSY0_SHIFT 3 -#define CCM_PRE70_MUX_B_MASK 0x700u -#define CCM_PRE70_MUX_B_SHIFT 8 -#define CCM_PRE70_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE70_MUX_B_SHIFT))&CCM_PRE70_MUX_B_MASK) -#define CCM_PRE70_EN_B_MASK 0x1000u -#define CCM_PRE70_EN_B_SHIFT 12 -#define CCM_PRE70_BUSY1_MASK 0x8000u -#define CCM_PRE70_BUSY1_SHIFT 15 -#define CCM_PRE70_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE70_PRE_PODF_A_SHIFT 16 -#define CCM_PRE70_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE70_PRE_PODF_A_SHIFT))&CCM_PRE70_PRE_PODF_A_MASK) -#define CCM_PRE70_BUSY3_MASK 0x80000u -#define CCM_PRE70_BUSY3_SHIFT 19 -#define CCM_PRE70_MUX_A_MASK 0x7000000u -#define CCM_PRE70_MUX_A_SHIFT 24 -#define CCM_PRE70_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE70_MUX_A_SHIFT))&CCM_PRE70_MUX_A_MASK) -#define CCM_PRE70_EN_A_MASK 0x10000000u -#define CCM_PRE70_EN_A_SHIFT 28 -#define CCM_PRE70_BUSY4_MASK 0x80000000u -#define CCM_PRE70_BUSY4_SHIFT 31 -/* PRE_ROOT70_SET Bit Fields */ -#define CCM_PRE_ROOT70_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT70_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT70_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT70_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT70_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT70_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT70_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT70_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT70_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_SET_MUX_B_SHIFT))&CCM_PRE_ROOT70_SET_MUX_B_MASK) -#define CCM_PRE_ROOT70_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT70_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT70_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT70_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT70_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT70_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT70_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT70_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT70_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT70_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT70_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT70_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT70_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_SET_MUX_A_SHIFT))&CCM_PRE_ROOT70_SET_MUX_A_MASK) -#define CCM_PRE_ROOT70_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT70_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT70_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT70_SET_BUSY4_SHIFT 31 -/* PRE_ROOT70_CLR Bit Fields */ -#define CCM_PRE_ROOT70_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT70_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT70_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT70_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT70_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT70_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT70_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT70_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT70_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT70_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT70_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT70_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT70_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT70_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT70_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT70_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT70_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT70_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT70_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT70_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT70_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT70_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT70_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT70_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT70_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT70_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT70_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT70_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT70_TOG Bit Fields */ -#define CCM_PRE_ROOT70_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT70_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT70_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT70_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT70_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT70_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT70_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT70_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT70_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT70_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT70_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT70_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT70_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT70_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT70_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT70_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT70_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT70_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT70_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT70_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT70_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT70_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT70_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT70_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT70_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT70_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT70_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT70_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL70 Bit Fields */ -#define CCM_ACCESS_CTRL70_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL70_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL70_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL70_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL70_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL70_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL70_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL70_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL70_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL70_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL70_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL70_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL70_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL70_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL70_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL70_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL70_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL70_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL70_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL70_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL70_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL70_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL70_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL70_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL70_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL70_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL70_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL70_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL70_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL70_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL70_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL70_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL70_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL70_LOCK_SHIFT 31 -/* ACCESS_CTRL70_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL70_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL70_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL70_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL70_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL70_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL70_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL70_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL70_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL70_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL70_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL70_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL70_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL70_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL70_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL70_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL70_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT71 Bit Fields */ -#define CCM_TARGET_ROOT71_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT71_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT71_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_POST_PODF_SHIFT))&CCM_TARGET_ROOT71_POST_PODF_MASK) -#define CCM_TARGET_ROOT71_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT71_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT71_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT71_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT71_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT71_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT71_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT71_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT71_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT71_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT71_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_PRE_PODF_SHIFT))&CCM_TARGET_ROOT71_PRE_PODF_MASK) -#define CCM_TARGET_ROOT71_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT71_MUX_SHIFT 24 -#define CCM_TARGET_ROOT71_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_MUX_SHIFT))&CCM_TARGET_ROOT71_MUX_MASK) -#define CCM_TARGET_ROOT71_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT71_ENABLE_SHIFT 28 -/* TARGET_ROOT71_SET Bit Fields */ -#define CCM_TARGET_ROOT71_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT71_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT71_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT71_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT71_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT71_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT71_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT71_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT71_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT71_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT71_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT71_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT71_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT71_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT71_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT71_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT71_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT71_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT71_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_SET_MUX_SHIFT))&CCM_TARGET_ROOT71_SET_MUX_MASK) -#define CCM_TARGET_ROOT71_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT71_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT71_CLR Bit Fields */ -#define CCM_TARGET_ROOT71_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT71_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT71_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT71_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT71_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT71_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT71_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT71_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT71_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT71_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT71_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT71_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT71_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT71_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT71_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT71_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT71_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT71_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT71_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_CLR_MUX_SHIFT))&CCM_TARGET_ROOT71_CLR_MUX_MASK) -#define CCM_TARGET_ROOT71_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT71_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT71_TOG Bit Fields */ -#define CCM_TARGET_ROOT71_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT71_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT71_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT71_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT71_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT71_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT71_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT71_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT71_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT71_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT71_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT71_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT71_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT71_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT71_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT71_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT71_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT71_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT71_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_TOG_MUX_SHIFT))&CCM_TARGET_ROOT71_TOG_MUX_MASK) -#define CCM_TARGET_ROOT71_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT71_TOG_ENABLE_SHIFT 28 -/* POST71 Bit Fields */ -#define CCM_POST71_POST_PODF_MASK 0x3Fu -#define CCM_POST71_POST_PODF_SHIFT 0 -#define CCM_POST71_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST71_POST_PODF_SHIFT))&CCM_POST71_POST_PODF_MASK) -#define CCM_POST71_BUSY1_MASK 0x80u -#define CCM_POST71_BUSY1_SHIFT 7 -#define CCM_POST71_AUTO_PODF_MASK 0x700u -#define CCM_POST71_AUTO_PODF_SHIFT 8 -#define CCM_POST71_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST71_AUTO_PODF_SHIFT))&CCM_POST71_AUTO_PODF_MASK) -#define CCM_POST71_AUTO_EN_MASK 0x1000u -#define CCM_POST71_AUTO_EN_SHIFT 12 -#define CCM_POST71_SLOW_MASK 0x8000u -#define CCM_POST71_SLOW_SHIFT 15 -#define CCM_POST71_SELECT_MASK 0x10000000u -#define CCM_POST71_SELECT_SHIFT 28 -#define CCM_POST71_BUSY2_MASK 0x80000000u -#define CCM_POST71_BUSY2_SHIFT 31 -/* POST_ROOT71_SET Bit Fields */ -#define CCM_POST_ROOT71_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT71_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT71_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_SET_POST_PODF_SHIFT))&CCM_POST_ROOT71_SET_POST_PODF_MASK) -#define CCM_POST_ROOT71_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT71_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT71_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT71_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT71_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT71_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT71_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT71_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT71_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT71_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT71_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT71_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT71_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT71_SET_BUSY2_SHIFT 31 -/* POST_ROOT71_CLR Bit Fields */ -#define CCM_POST_ROOT71_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT71_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT71_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT71_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT71_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT71_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT71_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT71_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT71_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT71_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT71_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT71_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT71_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT71_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT71_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT71_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT71_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT71_CLR_BUSY2_SHIFT 31 -/* POST_ROOT71_TOG Bit Fields */ -#define CCM_POST_ROOT71_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT71_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT71_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT71_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT71_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT71_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT71_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT71_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT71_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT71_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT71_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT71_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT71_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT71_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT71_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT71_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT71_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT71_TOG_BUSY2_SHIFT 31 -/* PRE71 Bit Fields */ -#define CCM_PRE71_PRE_PODF_B_MASK 0x7u -#define CCM_PRE71_PRE_PODF_B_SHIFT 0 -#define CCM_PRE71_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE71_PRE_PODF_B_SHIFT))&CCM_PRE71_PRE_PODF_B_MASK) -#define CCM_PRE71_BUSY0_MASK 0x8u -#define CCM_PRE71_BUSY0_SHIFT 3 -#define CCM_PRE71_MUX_B_MASK 0x700u -#define CCM_PRE71_MUX_B_SHIFT 8 -#define CCM_PRE71_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE71_MUX_B_SHIFT))&CCM_PRE71_MUX_B_MASK) -#define CCM_PRE71_EN_B_MASK 0x1000u -#define CCM_PRE71_EN_B_SHIFT 12 -#define CCM_PRE71_BUSY1_MASK 0x8000u -#define CCM_PRE71_BUSY1_SHIFT 15 -#define CCM_PRE71_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE71_PRE_PODF_A_SHIFT 16 -#define CCM_PRE71_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE71_PRE_PODF_A_SHIFT))&CCM_PRE71_PRE_PODF_A_MASK) -#define CCM_PRE71_BUSY3_MASK 0x80000u -#define CCM_PRE71_BUSY3_SHIFT 19 -#define CCM_PRE71_MUX_A_MASK 0x7000000u -#define CCM_PRE71_MUX_A_SHIFT 24 -#define CCM_PRE71_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE71_MUX_A_SHIFT))&CCM_PRE71_MUX_A_MASK) -#define CCM_PRE71_EN_A_MASK 0x10000000u -#define CCM_PRE71_EN_A_SHIFT 28 -#define CCM_PRE71_BUSY4_MASK 0x80000000u -#define CCM_PRE71_BUSY4_SHIFT 31 -/* PRE_ROOT71_SET Bit Fields */ -#define CCM_PRE_ROOT71_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT71_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT71_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT71_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT71_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT71_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT71_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT71_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT71_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_SET_MUX_B_SHIFT))&CCM_PRE_ROOT71_SET_MUX_B_MASK) -#define CCM_PRE_ROOT71_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT71_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT71_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT71_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT71_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT71_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT71_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT71_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT71_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT71_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT71_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT71_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT71_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_SET_MUX_A_SHIFT))&CCM_PRE_ROOT71_SET_MUX_A_MASK) -#define CCM_PRE_ROOT71_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT71_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT71_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT71_SET_BUSY4_SHIFT 31 -/* PRE_ROOT71_CLR Bit Fields */ -#define CCM_PRE_ROOT71_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT71_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT71_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT71_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT71_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT71_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT71_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT71_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT71_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT71_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT71_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT71_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT71_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT71_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT71_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT71_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT71_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT71_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT71_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT71_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT71_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT71_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT71_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT71_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT71_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT71_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT71_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT71_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT71_TOG Bit Fields */ -#define CCM_PRE_ROOT71_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT71_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT71_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT71_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT71_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT71_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT71_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT71_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT71_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT71_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT71_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT71_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT71_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT71_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT71_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT71_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT71_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT71_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT71_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT71_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT71_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT71_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT71_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT71_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT71_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT71_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT71_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT71_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL71 Bit Fields */ -#define CCM_ACCESS_CTRL71_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL71_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL71_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL71_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL71_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL71_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL71_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL71_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL71_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL71_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL71_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL71_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL71_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL71_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL71_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL71_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL71_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL71_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL71_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL71_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL71_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL71_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL71_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL71_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL71_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL71_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL71_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL71_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL71_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL71_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL71_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL71_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL71_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL71_LOCK_SHIFT 31 -/* ACCESS_CTRL71_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL71_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL71_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL71_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL71_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL71_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL71_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL71_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL71_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL71_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL71_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL71_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL71_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL71_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL71_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL71_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL71_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT72 Bit Fields */ -#define CCM_TARGET_ROOT72_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT72_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT72_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_POST_PODF_SHIFT))&CCM_TARGET_ROOT72_POST_PODF_MASK) -#define CCM_TARGET_ROOT72_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT72_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT72_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT72_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT72_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT72_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT72_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT72_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT72_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT72_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT72_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_PRE_PODF_SHIFT))&CCM_TARGET_ROOT72_PRE_PODF_MASK) -#define CCM_TARGET_ROOT72_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT72_MUX_SHIFT 24 -#define CCM_TARGET_ROOT72_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_MUX_SHIFT))&CCM_TARGET_ROOT72_MUX_MASK) -#define CCM_TARGET_ROOT72_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT72_ENABLE_SHIFT 28 -/* TARGET_ROOT72_SET Bit Fields */ -#define CCM_TARGET_ROOT72_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT72_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT72_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT72_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT72_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT72_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT72_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT72_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT72_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT72_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT72_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT72_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT72_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT72_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT72_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT72_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT72_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT72_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT72_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_SET_MUX_SHIFT))&CCM_TARGET_ROOT72_SET_MUX_MASK) -#define CCM_TARGET_ROOT72_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT72_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT72_CLR Bit Fields */ -#define CCM_TARGET_ROOT72_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT72_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT72_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT72_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT72_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT72_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT72_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT72_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT72_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT72_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT72_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT72_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT72_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT72_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT72_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT72_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT72_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT72_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT72_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_CLR_MUX_SHIFT))&CCM_TARGET_ROOT72_CLR_MUX_MASK) -#define CCM_TARGET_ROOT72_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT72_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT72_TOG Bit Fields */ -#define CCM_TARGET_ROOT72_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT72_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT72_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT72_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT72_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT72_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT72_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT72_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT72_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT72_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT72_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT72_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT72_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT72_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT72_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT72_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT72_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT72_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT72_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_TOG_MUX_SHIFT))&CCM_TARGET_ROOT72_TOG_MUX_MASK) -#define CCM_TARGET_ROOT72_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT72_TOG_ENABLE_SHIFT 28 -/* POST72 Bit Fields */ -#define CCM_POST72_POST_PODF_MASK 0x3Fu -#define CCM_POST72_POST_PODF_SHIFT 0 -#define CCM_POST72_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST72_POST_PODF_SHIFT))&CCM_POST72_POST_PODF_MASK) -#define CCM_POST72_BUSY1_MASK 0x80u -#define CCM_POST72_BUSY1_SHIFT 7 -#define CCM_POST72_AUTO_PODF_MASK 0x700u -#define CCM_POST72_AUTO_PODF_SHIFT 8 -#define CCM_POST72_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST72_AUTO_PODF_SHIFT))&CCM_POST72_AUTO_PODF_MASK) -#define CCM_POST72_AUTO_EN_MASK 0x1000u -#define CCM_POST72_AUTO_EN_SHIFT 12 -#define CCM_POST72_SLOW_MASK 0x8000u -#define CCM_POST72_SLOW_SHIFT 15 -#define CCM_POST72_SELECT_MASK 0x10000000u -#define CCM_POST72_SELECT_SHIFT 28 -#define CCM_POST72_BUSY2_MASK 0x80000000u -#define CCM_POST72_BUSY2_SHIFT 31 -/* POST_ROOT72_SET Bit Fields */ -#define CCM_POST_ROOT72_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT72_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT72_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_SET_POST_PODF_SHIFT))&CCM_POST_ROOT72_SET_POST_PODF_MASK) -#define CCM_POST_ROOT72_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT72_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT72_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT72_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT72_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT72_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT72_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT72_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT72_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT72_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT72_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT72_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT72_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT72_SET_BUSY2_SHIFT 31 -/* POST_ROOT72_CLR Bit Fields */ -#define CCM_POST_ROOT72_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT72_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT72_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT72_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT72_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT72_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT72_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT72_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT72_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT72_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT72_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT72_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT72_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT72_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT72_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT72_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT72_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT72_CLR_BUSY2_SHIFT 31 -/* POST_ROOT72_TOG Bit Fields */ -#define CCM_POST_ROOT72_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT72_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT72_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT72_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT72_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT72_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT72_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT72_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT72_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT72_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT72_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT72_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT72_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT72_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT72_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT72_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT72_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT72_TOG_BUSY2_SHIFT 31 -/* PRE72 Bit Fields */ -#define CCM_PRE72_PRE_PODF_B_MASK 0x7u -#define CCM_PRE72_PRE_PODF_B_SHIFT 0 -#define CCM_PRE72_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE72_PRE_PODF_B_SHIFT))&CCM_PRE72_PRE_PODF_B_MASK) -#define CCM_PRE72_BUSY0_MASK 0x8u -#define CCM_PRE72_BUSY0_SHIFT 3 -#define CCM_PRE72_MUX_B_MASK 0x700u -#define CCM_PRE72_MUX_B_SHIFT 8 -#define CCM_PRE72_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE72_MUX_B_SHIFT))&CCM_PRE72_MUX_B_MASK) -#define CCM_PRE72_EN_B_MASK 0x1000u -#define CCM_PRE72_EN_B_SHIFT 12 -#define CCM_PRE72_BUSY1_MASK 0x8000u -#define CCM_PRE72_BUSY1_SHIFT 15 -#define CCM_PRE72_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE72_PRE_PODF_A_SHIFT 16 -#define CCM_PRE72_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE72_PRE_PODF_A_SHIFT))&CCM_PRE72_PRE_PODF_A_MASK) -#define CCM_PRE72_BUSY3_MASK 0x80000u -#define CCM_PRE72_BUSY3_SHIFT 19 -#define CCM_PRE72_MUX_A_MASK 0x7000000u -#define CCM_PRE72_MUX_A_SHIFT 24 -#define CCM_PRE72_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE72_MUX_A_SHIFT))&CCM_PRE72_MUX_A_MASK) -#define CCM_PRE72_EN_A_MASK 0x10000000u -#define CCM_PRE72_EN_A_SHIFT 28 -#define CCM_PRE72_BUSY4_MASK 0x80000000u -#define CCM_PRE72_BUSY4_SHIFT 31 -/* PRE_ROOT72_SET Bit Fields */ -#define CCM_PRE_ROOT72_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT72_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT72_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT72_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT72_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT72_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT72_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT72_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT72_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_SET_MUX_B_SHIFT))&CCM_PRE_ROOT72_SET_MUX_B_MASK) -#define CCM_PRE_ROOT72_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT72_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT72_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT72_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT72_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT72_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT72_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT72_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT72_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT72_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT72_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT72_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT72_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_SET_MUX_A_SHIFT))&CCM_PRE_ROOT72_SET_MUX_A_MASK) -#define CCM_PRE_ROOT72_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT72_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT72_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT72_SET_BUSY4_SHIFT 31 -/* PRE_ROOT72_CLR Bit Fields */ -#define CCM_PRE_ROOT72_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT72_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT72_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT72_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT72_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT72_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT72_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT72_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT72_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT72_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT72_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT72_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT72_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT72_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT72_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT72_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT72_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT72_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT72_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT72_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT72_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT72_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT72_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT72_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT72_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT72_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT72_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT72_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT72_TOG Bit Fields */ -#define CCM_PRE_ROOT72_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT72_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT72_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT72_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT72_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT72_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT72_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT72_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT72_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT72_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT72_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT72_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT72_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT72_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT72_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT72_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT72_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT72_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT72_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT72_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT72_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT72_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT72_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT72_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT72_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT72_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT72_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT72_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL72 Bit Fields */ -#define CCM_ACCESS_CTRL72_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL72_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL72_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL72_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL72_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL72_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL72_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL72_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL72_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL72_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL72_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL72_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL72_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL72_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL72_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL72_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL72_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL72_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL72_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL72_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL72_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL72_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL72_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL72_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL72_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL72_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL72_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL72_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL72_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL72_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL72_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL72_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL72_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL72_LOCK_SHIFT 31 -/* ACCESS_CTRL72_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL72_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL72_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL72_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL72_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL72_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL72_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL72_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL72_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL72_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL72_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL72_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL72_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL72_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL72_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL72_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL72_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT73 Bit Fields */ -#define CCM_TARGET_ROOT73_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT73_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT73_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_POST_PODF_SHIFT))&CCM_TARGET_ROOT73_POST_PODF_MASK) -#define CCM_TARGET_ROOT73_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT73_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT73_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT73_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT73_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT73_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT73_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT73_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT73_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT73_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT73_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_PRE_PODF_SHIFT))&CCM_TARGET_ROOT73_PRE_PODF_MASK) -#define CCM_TARGET_ROOT73_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT73_MUX_SHIFT 24 -#define CCM_TARGET_ROOT73_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_MUX_SHIFT))&CCM_TARGET_ROOT73_MUX_MASK) -#define CCM_TARGET_ROOT73_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT73_ENABLE_SHIFT 28 -/* TARGET_ROOT73_SET Bit Fields */ -#define CCM_TARGET_ROOT73_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT73_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT73_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT73_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT73_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT73_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT73_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT73_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT73_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT73_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT73_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT73_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT73_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT73_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT73_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT73_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT73_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT73_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT73_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_SET_MUX_SHIFT))&CCM_TARGET_ROOT73_SET_MUX_MASK) -#define CCM_TARGET_ROOT73_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT73_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT73_CLR Bit Fields */ -#define CCM_TARGET_ROOT73_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT73_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT73_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT73_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT73_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT73_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT73_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT73_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT73_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT73_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT73_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT73_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT73_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT73_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT73_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT73_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT73_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT73_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT73_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_CLR_MUX_SHIFT))&CCM_TARGET_ROOT73_CLR_MUX_MASK) -#define CCM_TARGET_ROOT73_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT73_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT73_TOG Bit Fields */ -#define CCM_TARGET_ROOT73_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT73_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT73_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT73_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT73_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT73_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT73_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT73_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT73_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT73_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT73_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT73_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT73_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT73_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT73_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT73_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT73_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT73_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT73_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_TOG_MUX_SHIFT))&CCM_TARGET_ROOT73_TOG_MUX_MASK) -#define CCM_TARGET_ROOT73_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT73_TOG_ENABLE_SHIFT 28 -/* POST73 Bit Fields */ -#define CCM_POST73_POST_PODF_MASK 0x3Fu -#define CCM_POST73_POST_PODF_SHIFT 0 -#define CCM_POST73_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST73_POST_PODF_SHIFT))&CCM_POST73_POST_PODF_MASK) -#define CCM_POST73_BUSY1_MASK 0x80u -#define CCM_POST73_BUSY1_SHIFT 7 -#define CCM_POST73_AUTO_PODF_MASK 0x700u -#define CCM_POST73_AUTO_PODF_SHIFT 8 -#define CCM_POST73_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST73_AUTO_PODF_SHIFT))&CCM_POST73_AUTO_PODF_MASK) -#define CCM_POST73_AUTO_EN_MASK 0x1000u -#define CCM_POST73_AUTO_EN_SHIFT 12 -#define CCM_POST73_SLOW_MASK 0x8000u -#define CCM_POST73_SLOW_SHIFT 15 -#define CCM_POST73_SELECT_MASK 0x10000000u -#define CCM_POST73_SELECT_SHIFT 28 -#define CCM_POST73_BUSY2_MASK 0x80000000u -#define CCM_POST73_BUSY2_SHIFT 31 -/* POST_ROOT73_SET Bit Fields */ -#define CCM_POST_ROOT73_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT73_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT73_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_SET_POST_PODF_SHIFT))&CCM_POST_ROOT73_SET_POST_PODF_MASK) -#define CCM_POST_ROOT73_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT73_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT73_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT73_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT73_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT73_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT73_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT73_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT73_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT73_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT73_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT73_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT73_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT73_SET_BUSY2_SHIFT 31 -/* POST_ROOT73_CLR Bit Fields */ -#define CCM_POST_ROOT73_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT73_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT73_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT73_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT73_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT73_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT73_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT73_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT73_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT73_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT73_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT73_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT73_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT73_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT73_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT73_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT73_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT73_CLR_BUSY2_SHIFT 31 -/* POST_ROOT73_TOG Bit Fields */ -#define CCM_POST_ROOT73_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT73_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT73_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT73_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT73_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT73_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT73_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT73_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT73_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT73_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT73_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT73_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT73_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT73_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT73_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT73_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT73_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT73_TOG_BUSY2_SHIFT 31 -/* PRE73 Bit Fields */ -#define CCM_PRE73_PRE_PODF_B_MASK 0x7u -#define CCM_PRE73_PRE_PODF_B_SHIFT 0 -#define CCM_PRE73_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE73_PRE_PODF_B_SHIFT))&CCM_PRE73_PRE_PODF_B_MASK) -#define CCM_PRE73_BUSY0_MASK 0x8u -#define CCM_PRE73_BUSY0_SHIFT 3 -#define CCM_PRE73_MUX_B_MASK 0x700u -#define CCM_PRE73_MUX_B_SHIFT 8 -#define CCM_PRE73_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE73_MUX_B_SHIFT))&CCM_PRE73_MUX_B_MASK) -#define CCM_PRE73_EN_B_MASK 0x1000u -#define CCM_PRE73_EN_B_SHIFT 12 -#define CCM_PRE73_BUSY1_MASK 0x8000u -#define CCM_PRE73_BUSY1_SHIFT 15 -#define CCM_PRE73_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE73_PRE_PODF_A_SHIFT 16 -#define CCM_PRE73_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE73_PRE_PODF_A_SHIFT))&CCM_PRE73_PRE_PODF_A_MASK) -#define CCM_PRE73_BUSY3_MASK 0x80000u -#define CCM_PRE73_BUSY3_SHIFT 19 -#define CCM_PRE73_MUX_A_MASK 0x7000000u -#define CCM_PRE73_MUX_A_SHIFT 24 -#define CCM_PRE73_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE73_MUX_A_SHIFT))&CCM_PRE73_MUX_A_MASK) -#define CCM_PRE73_EN_A_MASK 0x10000000u -#define CCM_PRE73_EN_A_SHIFT 28 -#define CCM_PRE73_BUSY4_MASK 0x80000000u -#define CCM_PRE73_BUSY4_SHIFT 31 -/* PRE_ROOT73_SET Bit Fields */ -#define CCM_PRE_ROOT73_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT73_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT73_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT73_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT73_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT73_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT73_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT73_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT73_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_SET_MUX_B_SHIFT))&CCM_PRE_ROOT73_SET_MUX_B_MASK) -#define CCM_PRE_ROOT73_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT73_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT73_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT73_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT73_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT73_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT73_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT73_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT73_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT73_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT73_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT73_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT73_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_SET_MUX_A_SHIFT))&CCM_PRE_ROOT73_SET_MUX_A_MASK) -#define CCM_PRE_ROOT73_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT73_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT73_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT73_SET_BUSY4_SHIFT 31 -/* PRE_ROOT73_CLR Bit Fields */ -#define CCM_PRE_ROOT73_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT73_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT73_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT73_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT73_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT73_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT73_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT73_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT73_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT73_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT73_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT73_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT73_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT73_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT73_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT73_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT73_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT73_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT73_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT73_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT73_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT73_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT73_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT73_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT73_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT73_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT73_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT73_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT73_TOG Bit Fields */ -#define CCM_PRE_ROOT73_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT73_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT73_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT73_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT73_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT73_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT73_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT73_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT73_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT73_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT73_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT73_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT73_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT73_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT73_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT73_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT73_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT73_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT73_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT73_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT73_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT73_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT73_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT73_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT73_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT73_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT73_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT73_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL73 Bit Fields */ -#define CCM_ACCESS_CTRL73_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL73_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL73_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL73_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL73_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL73_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL73_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL73_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL73_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL73_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL73_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL73_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL73_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL73_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL73_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL73_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL73_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL73_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL73_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL73_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL73_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL73_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL73_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL73_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL73_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL73_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL73_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL73_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL73_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL73_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL73_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL73_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL73_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL73_LOCK_SHIFT 31 -/* ACCESS_CTRL73_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL73_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL73_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL73_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL73_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL73_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL73_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL73_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL73_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL73_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL73_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL73_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL73_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL73_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL73_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL73_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL73_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT74 Bit Fields */ -#define CCM_TARGET_ROOT74_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT74_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT74_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_POST_PODF_SHIFT))&CCM_TARGET_ROOT74_POST_PODF_MASK) -#define CCM_TARGET_ROOT74_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT74_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT74_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT74_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT74_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT74_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT74_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT74_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT74_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT74_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT74_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_PRE_PODF_SHIFT))&CCM_TARGET_ROOT74_PRE_PODF_MASK) -#define CCM_TARGET_ROOT74_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT74_MUX_SHIFT 24 -#define CCM_TARGET_ROOT74_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_MUX_SHIFT))&CCM_TARGET_ROOT74_MUX_MASK) -#define CCM_TARGET_ROOT74_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT74_ENABLE_SHIFT 28 -/* TARGET_ROOT74_SET Bit Fields */ -#define CCM_TARGET_ROOT74_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT74_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT74_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT74_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT74_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT74_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT74_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT74_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT74_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT74_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT74_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT74_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT74_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT74_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT74_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT74_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT74_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT74_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT74_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_SET_MUX_SHIFT))&CCM_TARGET_ROOT74_SET_MUX_MASK) -#define CCM_TARGET_ROOT74_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT74_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT74_CLR Bit Fields */ -#define CCM_TARGET_ROOT74_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT74_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT74_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT74_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT74_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT74_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT74_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT74_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT74_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT74_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT74_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT74_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT74_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT74_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT74_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT74_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT74_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT74_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT74_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_CLR_MUX_SHIFT))&CCM_TARGET_ROOT74_CLR_MUX_MASK) -#define CCM_TARGET_ROOT74_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT74_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT74_TOG Bit Fields */ -#define CCM_TARGET_ROOT74_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT74_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT74_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT74_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT74_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT74_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT74_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT74_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT74_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT74_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT74_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT74_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT74_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT74_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT74_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT74_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT74_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT74_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT74_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_TOG_MUX_SHIFT))&CCM_TARGET_ROOT74_TOG_MUX_MASK) -#define CCM_TARGET_ROOT74_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT74_TOG_ENABLE_SHIFT 28 -/* POST74 Bit Fields */ -#define CCM_POST74_POST_PODF_MASK 0x3Fu -#define CCM_POST74_POST_PODF_SHIFT 0 -#define CCM_POST74_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST74_POST_PODF_SHIFT))&CCM_POST74_POST_PODF_MASK) -#define CCM_POST74_BUSY1_MASK 0x80u -#define CCM_POST74_BUSY1_SHIFT 7 -#define CCM_POST74_AUTO_PODF_MASK 0x700u -#define CCM_POST74_AUTO_PODF_SHIFT 8 -#define CCM_POST74_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST74_AUTO_PODF_SHIFT))&CCM_POST74_AUTO_PODF_MASK) -#define CCM_POST74_AUTO_EN_MASK 0x1000u -#define CCM_POST74_AUTO_EN_SHIFT 12 -#define CCM_POST74_SLOW_MASK 0x8000u -#define CCM_POST74_SLOW_SHIFT 15 -#define CCM_POST74_SELECT_MASK 0x10000000u -#define CCM_POST74_SELECT_SHIFT 28 -#define CCM_POST74_BUSY2_MASK 0x80000000u -#define CCM_POST74_BUSY2_SHIFT 31 -/* POST_ROOT74_SET Bit Fields */ -#define CCM_POST_ROOT74_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT74_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT74_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_SET_POST_PODF_SHIFT))&CCM_POST_ROOT74_SET_POST_PODF_MASK) -#define CCM_POST_ROOT74_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT74_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT74_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT74_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT74_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT74_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT74_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT74_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT74_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT74_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT74_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT74_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT74_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT74_SET_BUSY2_SHIFT 31 -/* POST_ROOT74_CLR Bit Fields */ -#define CCM_POST_ROOT74_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT74_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT74_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT74_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT74_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT74_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT74_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT74_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT74_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT74_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT74_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT74_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT74_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT74_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT74_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT74_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT74_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT74_CLR_BUSY2_SHIFT 31 -/* POST_ROOT74_TOG Bit Fields */ -#define CCM_POST_ROOT74_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT74_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT74_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT74_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT74_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT74_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT74_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT74_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT74_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT74_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT74_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT74_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT74_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT74_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT74_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT74_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT74_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT74_TOG_BUSY2_SHIFT 31 -/* PRE74 Bit Fields */ -#define CCM_PRE74_PRE_PODF_B_MASK 0x7u -#define CCM_PRE74_PRE_PODF_B_SHIFT 0 -#define CCM_PRE74_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE74_PRE_PODF_B_SHIFT))&CCM_PRE74_PRE_PODF_B_MASK) -#define CCM_PRE74_BUSY0_MASK 0x8u -#define CCM_PRE74_BUSY0_SHIFT 3 -#define CCM_PRE74_MUX_B_MASK 0x700u -#define CCM_PRE74_MUX_B_SHIFT 8 -#define CCM_PRE74_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE74_MUX_B_SHIFT))&CCM_PRE74_MUX_B_MASK) -#define CCM_PRE74_EN_B_MASK 0x1000u -#define CCM_PRE74_EN_B_SHIFT 12 -#define CCM_PRE74_BUSY1_MASK 0x8000u -#define CCM_PRE74_BUSY1_SHIFT 15 -#define CCM_PRE74_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE74_PRE_PODF_A_SHIFT 16 -#define CCM_PRE74_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE74_PRE_PODF_A_SHIFT))&CCM_PRE74_PRE_PODF_A_MASK) -#define CCM_PRE74_BUSY3_MASK 0x80000u -#define CCM_PRE74_BUSY3_SHIFT 19 -#define CCM_PRE74_MUX_A_MASK 0x7000000u -#define CCM_PRE74_MUX_A_SHIFT 24 -#define CCM_PRE74_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE74_MUX_A_SHIFT))&CCM_PRE74_MUX_A_MASK) -#define CCM_PRE74_EN_A_MASK 0x10000000u -#define CCM_PRE74_EN_A_SHIFT 28 -#define CCM_PRE74_BUSY4_MASK 0x80000000u -#define CCM_PRE74_BUSY4_SHIFT 31 -/* PRE_ROOT74_SET Bit Fields */ -#define CCM_PRE_ROOT74_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT74_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT74_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT74_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT74_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT74_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT74_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT74_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT74_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_SET_MUX_B_SHIFT))&CCM_PRE_ROOT74_SET_MUX_B_MASK) -#define CCM_PRE_ROOT74_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT74_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT74_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT74_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT74_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT74_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT74_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT74_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT74_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT74_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT74_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT74_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT74_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_SET_MUX_A_SHIFT))&CCM_PRE_ROOT74_SET_MUX_A_MASK) -#define CCM_PRE_ROOT74_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT74_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT74_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT74_SET_BUSY4_SHIFT 31 -/* PRE_ROOT74_CLR Bit Fields */ -#define CCM_PRE_ROOT74_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT74_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT74_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT74_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT74_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT74_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT74_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT74_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT74_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT74_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT74_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT74_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT74_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT74_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT74_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT74_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT74_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT74_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT74_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT74_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT74_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT74_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT74_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT74_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT74_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT74_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT74_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT74_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT74_TOG Bit Fields */ -#define CCM_PRE_ROOT74_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT74_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT74_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT74_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT74_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT74_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT74_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT74_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT74_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT74_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT74_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT74_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT74_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT74_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT74_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT74_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT74_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT74_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT74_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT74_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT74_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT74_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT74_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT74_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT74_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT74_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT74_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT74_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL74 Bit Fields */ -#define CCM_ACCESS_CTRL74_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL74_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL74_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL74_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL74_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL74_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL74_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL74_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL74_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL74_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL74_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL74_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL74_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL74_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL74_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL74_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL74_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL74_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL74_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL74_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL74_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL74_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL74_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL74_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL74_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL74_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL74_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL74_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL74_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL74_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL74_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL74_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL74_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL74_LOCK_SHIFT 31 -/* ACCESS_CTRL74_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL74_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL74_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL74_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL74_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL74_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL74_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL74_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL74_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL74_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL74_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL74_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL74_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL74_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL74_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL74_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL74_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT75 Bit Fields */ -#define CCM_TARGET_ROOT75_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT75_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT75_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_POST_PODF_SHIFT))&CCM_TARGET_ROOT75_POST_PODF_MASK) -#define CCM_TARGET_ROOT75_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT75_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT75_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT75_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT75_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT75_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT75_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT75_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT75_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT75_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT75_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_PRE_PODF_SHIFT))&CCM_TARGET_ROOT75_PRE_PODF_MASK) -#define CCM_TARGET_ROOT75_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT75_MUX_SHIFT 24 -#define CCM_TARGET_ROOT75_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_MUX_SHIFT))&CCM_TARGET_ROOT75_MUX_MASK) -#define CCM_TARGET_ROOT75_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT75_ENABLE_SHIFT 28 -/* TARGET_ROOT75_SET Bit Fields */ -#define CCM_TARGET_ROOT75_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT75_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT75_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT75_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT75_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT75_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT75_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT75_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT75_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT75_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT75_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT75_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT75_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT75_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT75_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT75_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT75_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT75_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT75_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_SET_MUX_SHIFT))&CCM_TARGET_ROOT75_SET_MUX_MASK) -#define CCM_TARGET_ROOT75_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT75_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT75_CLR Bit Fields */ -#define CCM_TARGET_ROOT75_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT75_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT75_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT75_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT75_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT75_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT75_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT75_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT75_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT75_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT75_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT75_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT75_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT75_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT75_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT75_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT75_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT75_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT75_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_CLR_MUX_SHIFT))&CCM_TARGET_ROOT75_CLR_MUX_MASK) -#define CCM_TARGET_ROOT75_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT75_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT75_TOG Bit Fields */ -#define CCM_TARGET_ROOT75_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT75_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT75_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT75_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT75_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT75_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT75_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT75_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT75_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT75_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT75_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT75_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT75_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT75_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT75_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT75_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT75_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT75_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT75_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_TOG_MUX_SHIFT))&CCM_TARGET_ROOT75_TOG_MUX_MASK) -#define CCM_TARGET_ROOT75_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT75_TOG_ENABLE_SHIFT 28 -/* POST75 Bit Fields */ -#define CCM_POST75_POST_PODF_MASK 0x3Fu -#define CCM_POST75_POST_PODF_SHIFT 0 -#define CCM_POST75_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST75_POST_PODF_SHIFT))&CCM_POST75_POST_PODF_MASK) -#define CCM_POST75_BUSY1_MASK 0x80u -#define CCM_POST75_BUSY1_SHIFT 7 -#define CCM_POST75_AUTO_PODF_MASK 0x700u -#define CCM_POST75_AUTO_PODF_SHIFT 8 -#define CCM_POST75_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST75_AUTO_PODF_SHIFT))&CCM_POST75_AUTO_PODF_MASK) -#define CCM_POST75_AUTO_EN_MASK 0x1000u -#define CCM_POST75_AUTO_EN_SHIFT 12 -#define CCM_POST75_SLOW_MASK 0x8000u -#define CCM_POST75_SLOW_SHIFT 15 -#define CCM_POST75_SELECT_MASK 0x10000000u -#define CCM_POST75_SELECT_SHIFT 28 -#define CCM_POST75_BUSY2_MASK 0x80000000u -#define CCM_POST75_BUSY2_SHIFT 31 -/* POST_ROOT75_SET Bit Fields */ -#define CCM_POST_ROOT75_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT75_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT75_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_SET_POST_PODF_SHIFT))&CCM_POST_ROOT75_SET_POST_PODF_MASK) -#define CCM_POST_ROOT75_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT75_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT75_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT75_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT75_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT75_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT75_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT75_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT75_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT75_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT75_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT75_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT75_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT75_SET_BUSY2_SHIFT 31 -/* POST_ROOT75_CLR Bit Fields */ -#define CCM_POST_ROOT75_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT75_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT75_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT75_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT75_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT75_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT75_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT75_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT75_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT75_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT75_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT75_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT75_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT75_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT75_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT75_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT75_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT75_CLR_BUSY2_SHIFT 31 -/* POST_ROOT75_TOG Bit Fields */ -#define CCM_POST_ROOT75_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT75_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT75_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT75_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT75_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT75_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT75_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT75_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT75_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT75_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT75_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT75_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT75_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT75_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT75_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT75_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT75_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT75_TOG_BUSY2_SHIFT 31 -/* PRE75 Bit Fields */ -#define CCM_PRE75_PRE_PODF_B_MASK 0x7u -#define CCM_PRE75_PRE_PODF_B_SHIFT 0 -#define CCM_PRE75_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE75_PRE_PODF_B_SHIFT))&CCM_PRE75_PRE_PODF_B_MASK) -#define CCM_PRE75_BUSY0_MASK 0x8u -#define CCM_PRE75_BUSY0_SHIFT 3 -#define CCM_PRE75_MUX_B_MASK 0x700u -#define CCM_PRE75_MUX_B_SHIFT 8 -#define CCM_PRE75_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE75_MUX_B_SHIFT))&CCM_PRE75_MUX_B_MASK) -#define CCM_PRE75_EN_B_MASK 0x1000u -#define CCM_PRE75_EN_B_SHIFT 12 -#define CCM_PRE75_BUSY1_MASK 0x8000u -#define CCM_PRE75_BUSY1_SHIFT 15 -#define CCM_PRE75_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE75_PRE_PODF_A_SHIFT 16 -#define CCM_PRE75_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE75_PRE_PODF_A_SHIFT))&CCM_PRE75_PRE_PODF_A_MASK) -#define CCM_PRE75_BUSY3_MASK 0x80000u -#define CCM_PRE75_BUSY3_SHIFT 19 -#define CCM_PRE75_MUX_A_MASK 0x7000000u -#define CCM_PRE75_MUX_A_SHIFT 24 -#define CCM_PRE75_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE75_MUX_A_SHIFT))&CCM_PRE75_MUX_A_MASK) -#define CCM_PRE75_EN_A_MASK 0x10000000u -#define CCM_PRE75_EN_A_SHIFT 28 -#define CCM_PRE75_BUSY4_MASK 0x80000000u -#define CCM_PRE75_BUSY4_SHIFT 31 -/* PRE_ROOT75_SET Bit Fields */ -#define CCM_PRE_ROOT75_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT75_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT75_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT75_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT75_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT75_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT75_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT75_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT75_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_SET_MUX_B_SHIFT))&CCM_PRE_ROOT75_SET_MUX_B_MASK) -#define CCM_PRE_ROOT75_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT75_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT75_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT75_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT75_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT75_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT75_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT75_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT75_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT75_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT75_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT75_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT75_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_SET_MUX_A_SHIFT))&CCM_PRE_ROOT75_SET_MUX_A_MASK) -#define CCM_PRE_ROOT75_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT75_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT75_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT75_SET_BUSY4_SHIFT 31 -/* PRE_ROOT75_CLR Bit Fields */ -#define CCM_PRE_ROOT75_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT75_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT75_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT75_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT75_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT75_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT75_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT75_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT75_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT75_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT75_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT75_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT75_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT75_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT75_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT75_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT75_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT75_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT75_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT75_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT75_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT75_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT75_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT75_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT75_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT75_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT75_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT75_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT75_TOG Bit Fields */ -#define CCM_PRE_ROOT75_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT75_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT75_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT75_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT75_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT75_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT75_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT75_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT75_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT75_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT75_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT75_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT75_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT75_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT75_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT75_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT75_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT75_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT75_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT75_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT75_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT75_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT75_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT75_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT75_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT75_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT75_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT75_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL75 Bit Fields */ -#define CCM_ACCESS_CTRL75_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL75_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL75_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL75_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL75_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL75_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL75_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL75_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL75_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL75_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL75_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL75_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL75_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL75_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL75_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL75_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL75_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL75_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL75_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL75_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL75_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL75_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL75_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL75_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL75_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL75_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL75_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL75_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL75_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL75_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL75_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL75_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL75_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL75_LOCK_SHIFT 31 -/* ACCESS_CTRL75_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL75_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL75_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL75_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL75_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL75_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL75_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL75_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL75_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL75_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL75_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL75_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL75_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL75_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL75_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL75_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL75_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT76 Bit Fields */ -#define CCM_TARGET_ROOT76_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT76_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT76_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_POST_PODF_SHIFT))&CCM_TARGET_ROOT76_POST_PODF_MASK) -#define CCM_TARGET_ROOT76_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT76_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT76_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT76_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT76_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT76_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT76_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT76_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT76_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT76_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT76_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_PRE_PODF_SHIFT))&CCM_TARGET_ROOT76_PRE_PODF_MASK) -#define CCM_TARGET_ROOT76_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT76_MUX_SHIFT 24 -#define CCM_TARGET_ROOT76_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_MUX_SHIFT))&CCM_TARGET_ROOT76_MUX_MASK) -#define CCM_TARGET_ROOT76_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT76_ENABLE_SHIFT 28 -/* TARGET_ROOT76_SET Bit Fields */ -#define CCM_TARGET_ROOT76_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT76_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT76_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT76_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT76_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT76_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT76_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT76_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT76_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT76_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT76_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT76_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT76_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT76_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT76_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT76_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT76_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT76_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT76_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_SET_MUX_SHIFT))&CCM_TARGET_ROOT76_SET_MUX_MASK) -#define CCM_TARGET_ROOT76_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT76_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT76_CLR Bit Fields */ -#define CCM_TARGET_ROOT76_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT76_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT76_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT76_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT76_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT76_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT76_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT76_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT76_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT76_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT76_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT76_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT76_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT76_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT76_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT76_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT76_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT76_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT76_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_CLR_MUX_SHIFT))&CCM_TARGET_ROOT76_CLR_MUX_MASK) -#define CCM_TARGET_ROOT76_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT76_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT76_TOG Bit Fields */ -#define CCM_TARGET_ROOT76_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT76_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT76_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT76_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT76_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT76_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT76_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT76_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT76_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT76_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT76_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT76_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT76_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT76_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT76_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT76_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT76_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT76_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT76_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_TOG_MUX_SHIFT))&CCM_TARGET_ROOT76_TOG_MUX_MASK) -#define CCM_TARGET_ROOT76_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT76_TOG_ENABLE_SHIFT 28 -/* POST76 Bit Fields */ -#define CCM_POST76_POST_PODF_MASK 0x3Fu -#define CCM_POST76_POST_PODF_SHIFT 0 -#define CCM_POST76_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST76_POST_PODF_SHIFT))&CCM_POST76_POST_PODF_MASK) -#define CCM_POST76_BUSY1_MASK 0x80u -#define CCM_POST76_BUSY1_SHIFT 7 -#define CCM_POST76_AUTO_PODF_MASK 0x700u -#define CCM_POST76_AUTO_PODF_SHIFT 8 -#define CCM_POST76_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST76_AUTO_PODF_SHIFT))&CCM_POST76_AUTO_PODF_MASK) -#define CCM_POST76_AUTO_EN_MASK 0x1000u -#define CCM_POST76_AUTO_EN_SHIFT 12 -#define CCM_POST76_SLOW_MASK 0x8000u -#define CCM_POST76_SLOW_SHIFT 15 -#define CCM_POST76_SELECT_MASK 0x10000000u -#define CCM_POST76_SELECT_SHIFT 28 -#define CCM_POST76_BUSY2_MASK 0x80000000u -#define CCM_POST76_BUSY2_SHIFT 31 -/* POST_ROOT76_SET Bit Fields */ -#define CCM_POST_ROOT76_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT76_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT76_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_SET_POST_PODF_SHIFT))&CCM_POST_ROOT76_SET_POST_PODF_MASK) -#define CCM_POST_ROOT76_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT76_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT76_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT76_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT76_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT76_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT76_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT76_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT76_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT76_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT76_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT76_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT76_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT76_SET_BUSY2_SHIFT 31 -/* POST_ROOT76_CLR Bit Fields */ -#define CCM_POST_ROOT76_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT76_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT76_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT76_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT76_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT76_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT76_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT76_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT76_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT76_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT76_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT76_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT76_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT76_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT76_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT76_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT76_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT76_CLR_BUSY2_SHIFT 31 -/* POST_ROOT76_TOG Bit Fields */ -#define CCM_POST_ROOT76_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT76_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT76_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT76_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT76_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT76_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT76_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT76_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT76_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT76_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT76_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT76_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT76_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT76_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT76_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT76_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT76_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT76_TOG_BUSY2_SHIFT 31 -/* PRE76 Bit Fields */ -#define CCM_PRE76_PRE_PODF_B_MASK 0x7u -#define CCM_PRE76_PRE_PODF_B_SHIFT 0 -#define CCM_PRE76_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE76_PRE_PODF_B_SHIFT))&CCM_PRE76_PRE_PODF_B_MASK) -#define CCM_PRE76_BUSY0_MASK 0x8u -#define CCM_PRE76_BUSY0_SHIFT 3 -#define CCM_PRE76_MUX_B_MASK 0x700u -#define CCM_PRE76_MUX_B_SHIFT 8 -#define CCM_PRE76_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE76_MUX_B_SHIFT))&CCM_PRE76_MUX_B_MASK) -#define CCM_PRE76_EN_B_MASK 0x1000u -#define CCM_PRE76_EN_B_SHIFT 12 -#define CCM_PRE76_BUSY1_MASK 0x8000u -#define CCM_PRE76_BUSY1_SHIFT 15 -#define CCM_PRE76_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE76_PRE_PODF_A_SHIFT 16 -#define CCM_PRE76_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE76_PRE_PODF_A_SHIFT))&CCM_PRE76_PRE_PODF_A_MASK) -#define CCM_PRE76_BUSY3_MASK 0x80000u -#define CCM_PRE76_BUSY3_SHIFT 19 -#define CCM_PRE76_MUX_A_MASK 0x7000000u -#define CCM_PRE76_MUX_A_SHIFT 24 -#define CCM_PRE76_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE76_MUX_A_SHIFT))&CCM_PRE76_MUX_A_MASK) -#define CCM_PRE76_EN_A_MASK 0x10000000u -#define CCM_PRE76_EN_A_SHIFT 28 -#define CCM_PRE76_BUSY4_MASK 0x80000000u -#define CCM_PRE76_BUSY4_SHIFT 31 -/* PRE_ROOT76_SET Bit Fields */ -#define CCM_PRE_ROOT76_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT76_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT76_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT76_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT76_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT76_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT76_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT76_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT76_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_SET_MUX_B_SHIFT))&CCM_PRE_ROOT76_SET_MUX_B_MASK) -#define CCM_PRE_ROOT76_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT76_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT76_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT76_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT76_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT76_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT76_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT76_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT76_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT76_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT76_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT76_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT76_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_SET_MUX_A_SHIFT))&CCM_PRE_ROOT76_SET_MUX_A_MASK) -#define CCM_PRE_ROOT76_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT76_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT76_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT76_SET_BUSY4_SHIFT 31 -/* PRE_ROOT76_CLR Bit Fields */ -#define CCM_PRE_ROOT76_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT76_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT76_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT76_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT76_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT76_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT76_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT76_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT76_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT76_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT76_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT76_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT76_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT76_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT76_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT76_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT76_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT76_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT76_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT76_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT76_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT76_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT76_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT76_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT76_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT76_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT76_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT76_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT76_TOG Bit Fields */ -#define CCM_PRE_ROOT76_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT76_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT76_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT76_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT76_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT76_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT76_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT76_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT76_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT76_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT76_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT76_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT76_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT76_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT76_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT76_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT76_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT76_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT76_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT76_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT76_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT76_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT76_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT76_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT76_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT76_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT76_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT76_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL76 Bit Fields */ -#define CCM_ACCESS_CTRL76_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL76_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL76_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL76_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL76_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL76_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL76_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL76_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL76_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL76_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL76_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL76_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL76_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL76_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL76_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL76_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL76_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL76_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL76_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL76_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL76_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL76_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL76_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL76_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL76_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL76_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL76_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL76_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL76_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL76_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL76_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL76_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL76_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL76_LOCK_SHIFT 31 -/* ACCESS_CTRL76_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL76_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL76_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL76_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL76_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL76_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL76_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL76_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL76_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL76_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL76_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL76_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL76_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL76_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL76_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL76_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL76_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT77 Bit Fields */ -#define CCM_TARGET_ROOT77_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT77_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT77_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_POST_PODF_SHIFT))&CCM_TARGET_ROOT77_POST_PODF_MASK) -#define CCM_TARGET_ROOT77_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT77_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT77_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT77_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT77_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT77_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT77_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT77_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT77_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT77_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT77_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_PRE_PODF_SHIFT))&CCM_TARGET_ROOT77_PRE_PODF_MASK) -#define CCM_TARGET_ROOT77_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT77_MUX_SHIFT 24 -#define CCM_TARGET_ROOT77_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_MUX_SHIFT))&CCM_TARGET_ROOT77_MUX_MASK) -#define CCM_TARGET_ROOT77_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT77_ENABLE_SHIFT 28 -/* TARGET_ROOT77_SET Bit Fields */ -#define CCM_TARGET_ROOT77_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT77_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT77_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT77_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT77_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT77_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT77_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT77_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT77_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT77_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT77_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT77_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT77_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT77_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT77_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT77_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT77_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT77_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT77_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_SET_MUX_SHIFT))&CCM_TARGET_ROOT77_SET_MUX_MASK) -#define CCM_TARGET_ROOT77_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT77_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT77_CLR Bit Fields */ -#define CCM_TARGET_ROOT77_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT77_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT77_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT77_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT77_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT77_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT77_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT77_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT77_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT77_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT77_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT77_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT77_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT77_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT77_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT77_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT77_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT77_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT77_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_CLR_MUX_SHIFT))&CCM_TARGET_ROOT77_CLR_MUX_MASK) -#define CCM_TARGET_ROOT77_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT77_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT77_TOG Bit Fields */ -#define CCM_TARGET_ROOT77_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT77_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT77_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT77_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT77_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT77_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT77_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT77_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT77_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT77_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT77_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT77_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT77_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT77_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT77_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT77_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT77_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT77_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT77_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_TOG_MUX_SHIFT))&CCM_TARGET_ROOT77_TOG_MUX_MASK) -#define CCM_TARGET_ROOT77_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT77_TOG_ENABLE_SHIFT 28 -/* POST77 Bit Fields */ -#define CCM_POST77_POST_PODF_MASK 0x3Fu -#define CCM_POST77_POST_PODF_SHIFT 0 -#define CCM_POST77_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST77_POST_PODF_SHIFT))&CCM_POST77_POST_PODF_MASK) -#define CCM_POST77_BUSY1_MASK 0x80u -#define CCM_POST77_BUSY1_SHIFT 7 -#define CCM_POST77_AUTO_PODF_MASK 0x700u -#define CCM_POST77_AUTO_PODF_SHIFT 8 -#define CCM_POST77_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST77_AUTO_PODF_SHIFT))&CCM_POST77_AUTO_PODF_MASK) -#define CCM_POST77_AUTO_EN_MASK 0x1000u -#define CCM_POST77_AUTO_EN_SHIFT 12 -#define CCM_POST77_SLOW_MASK 0x8000u -#define CCM_POST77_SLOW_SHIFT 15 -#define CCM_POST77_SELECT_MASK 0x10000000u -#define CCM_POST77_SELECT_SHIFT 28 -#define CCM_POST77_BUSY2_MASK 0x80000000u -#define CCM_POST77_BUSY2_SHIFT 31 -/* POST_ROOT77_SET Bit Fields */ -#define CCM_POST_ROOT77_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT77_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT77_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_SET_POST_PODF_SHIFT))&CCM_POST_ROOT77_SET_POST_PODF_MASK) -#define CCM_POST_ROOT77_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT77_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT77_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT77_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT77_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT77_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT77_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT77_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT77_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT77_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT77_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT77_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT77_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT77_SET_BUSY2_SHIFT 31 -/* POST_ROOT77_CLR Bit Fields */ -#define CCM_POST_ROOT77_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT77_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT77_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT77_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT77_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT77_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT77_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT77_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT77_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT77_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT77_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT77_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT77_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT77_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT77_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT77_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT77_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT77_CLR_BUSY2_SHIFT 31 -/* POST_ROOT77_TOG Bit Fields */ -#define CCM_POST_ROOT77_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT77_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT77_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT77_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT77_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT77_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT77_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT77_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT77_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT77_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT77_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT77_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT77_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT77_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT77_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT77_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT77_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT77_TOG_BUSY2_SHIFT 31 -/* PRE77 Bit Fields */ -#define CCM_PRE77_PRE_PODF_B_MASK 0x7u -#define CCM_PRE77_PRE_PODF_B_SHIFT 0 -#define CCM_PRE77_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE77_PRE_PODF_B_SHIFT))&CCM_PRE77_PRE_PODF_B_MASK) -#define CCM_PRE77_BUSY0_MASK 0x8u -#define CCM_PRE77_BUSY0_SHIFT 3 -#define CCM_PRE77_MUX_B_MASK 0x700u -#define CCM_PRE77_MUX_B_SHIFT 8 -#define CCM_PRE77_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE77_MUX_B_SHIFT))&CCM_PRE77_MUX_B_MASK) -#define CCM_PRE77_EN_B_MASK 0x1000u -#define CCM_PRE77_EN_B_SHIFT 12 -#define CCM_PRE77_BUSY1_MASK 0x8000u -#define CCM_PRE77_BUSY1_SHIFT 15 -#define CCM_PRE77_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE77_PRE_PODF_A_SHIFT 16 -#define CCM_PRE77_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE77_PRE_PODF_A_SHIFT))&CCM_PRE77_PRE_PODF_A_MASK) -#define CCM_PRE77_BUSY3_MASK 0x80000u -#define CCM_PRE77_BUSY3_SHIFT 19 -#define CCM_PRE77_MUX_A_MASK 0x7000000u -#define CCM_PRE77_MUX_A_SHIFT 24 -#define CCM_PRE77_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE77_MUX_A_SHIFT))&CCM_PRE77_MUX_A_MASK) -#define CCM_PRE77_EN_A_MASK 0x10000000u -#define CCM_PRE77_EN_A_SHIFT 28 -#define CCM_PRE77_BUSY4_MASK 0x80000000u -#define CCM_PRE77_BUSY4_SHIFT 31 -/* PRE_ROOT77_SET Bit Fields */ -#define CCM_PRE_ROOT77_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT77_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT77_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT77_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT77_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT77_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT77_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT77_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT77_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_SET_MUX_B_SHIFT))&CCM_PRE_ROOT77_SET_MUX_B_MASK) -#define CCM_PRE_ROOT77_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT77_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT77_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT77_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT77_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT77_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT77_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT77_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT77_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT77_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT77_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT77_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT77_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_SET_MUX_A_SHIFT))&CCM_PRE_ROOT77_SET_MUX_A_MASK) -#define CCM_PRE_ROOT77_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT77_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT77_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT77_SET_BUSY4_SHIFT 31 -/* PRE_ROOT77_CLR Bit Fields */ -#define CCM_PRE_ROOT77_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT77_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT77_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT77_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT77_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT77_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT77_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT77_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT77_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT77_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT77_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT77_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT77_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT77_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT77_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT77_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT77_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT77_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT77_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT77_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT77_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT77_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT77_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT77_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT77_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT77_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT77_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT77_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT77_TOG Bit Fields */ -#define CCM_PRE_ROOT77_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT77_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT77_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT77_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT77_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT77_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT77_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT77_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT77_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT77_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT77_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT77_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT77_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT77_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT77_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT77_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT77_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT77_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT77_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT77_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT77_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT77_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT77_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT77_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT77_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT77_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT77_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT77_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL77 Bit Fields */ -#define CCM_ACCESS_CTRL77_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL77_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL77_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL77_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL77_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL77_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL77_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL77_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL77_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL77_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL77_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL77_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL77_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL77_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL77_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL77_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL77_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL77_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL77_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL77_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL77_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL77_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL77_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL77_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL77_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL77_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL77_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL77_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL77_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL77_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL77_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL77_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL77_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL77_LOCK_SHIFT 31 -/* ACCESS_CTRL77_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL77_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL77_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL77_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL77_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL77_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL77_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL77_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL77_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL77_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL77_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL77_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL77_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL77_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL77_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL77_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL77_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT78 Bit Fields */ -#define CCM_TARGET_ROOT78_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT78_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT78_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_POST_PODF_SHIFT))&CCM_TARGET_ROOT78_POST_PODF_MASK) -#define CCM_TARGET_ROOT78_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT78_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT78_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT78_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT78_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT78_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT78_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT78_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT78_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT78_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT78_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_PRE_PODF_SHIFT))&CCM_TARGET_ROOT78_PRE_PODF_MASK) -#define CCM_TARGET_ROOT78_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT78_MUX_SHIFT 24 -#define CCM_TARGET_ROOT78_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_MUX_SHIFT))&CCM_TARGET_ROOT78_MUX_MASK) -#define CCM_TARGET_ROOT78_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT78_ENABLE_SHIFT 28 -/* TARGET_ROOT78_SET Bit Fields */ -#define CCM_TARGET_ROOT78_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT78_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT78_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT78_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT78_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT78_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT78_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT78_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT78_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT78_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT78_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT78_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT78_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT78_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT78_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT78_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT78_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT78_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT78_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_SET_MUX_SHIFT))&CCM_TARGET_ROOT78_SET_MUX_MASK) -#define CCM_TARGET_ROOT78_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT78_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT78_CLR Bit Fields */ -#define CCM_TARGET_ROOT78_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT78_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT78_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT78_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT78_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT78_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT78_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT78_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT78_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT78_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT78_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT78_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT78_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT78_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT78_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT78_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT78_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT78_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT78_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_CLR_MUX_SHIFT))&CCM_TARGET_ROOT78_CLR_MUX_MASK) -#define CCM_TARGET_ROOT78_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT78_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT78_TOG Bit Fields */ -#define CCM_TARGET_ROOT78_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT78_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT78_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT78_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT78_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT78_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT78_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT78_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT78_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT78_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT78_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT78_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT78_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT78_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT78_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT78_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT78_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT78_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT78_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_TOG_MUX_SHIFT))&CCM_TARGET_ROOT78_TOG_MUX_MASK) -#define CCM_TARGET_ROOT78_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT78_TOG_ENABLE_SHIFT 28 -/* POST78 Bit Fields */ -#define CCM_POST78_POST_PODF_MASK 0x3Fu -#define CCM_POST78_POST_PODF_SHIFT 0 -#define CCM_POST78_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST78_POST_PODF_SHIFT))&CCM_POST78_POST_PODF_MASK) -#define CCM_POST78_BUSY1_MASK 0x80u -#define CCM_POST78_BUSY1_SHIFT 7 -#define CCM_POST78_AUTO_PODF_MASK 0x700u -#define CCM_POST78_AUTO_PODF_SHIFT 8 -#define CCM_POST78_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST78_AUTO_PODF_SHIFT))&CCM_POST78_AUTO_PODF_MASK) -#define CCM_POST78_AUTO_EN_MASK 0x1000u -#define CCM_POST78_AUTO_EN_SHIFT 12 -#define CCM_POST78_SLOW_MASK 0x8000u -#define CCM_POST78_SLOW_SHIFT 15 -#define CCM_POST78_SELECT_MASK 0x10000000u -#define CCM_POST78_SELECT_SHIFT 28 -#define CCM_POST78_BUSY2_MASK 0x80000000u -#define CCM_POST78_BUSY2_SHIFT 31 -/* POST_ROOT78_SET Bit Fields */ -#define CCM_POST_ROOT78_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT78_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT78_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_SET_POST_PODF_SHIFT))&CCM_POST_ROOT78_SET_POST_PODF_MASK) -#define CCM_POST_ROOT78_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT78_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT78_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT78_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT78_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT78_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT78_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT78_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT78_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT78_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT78_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT78_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT78_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT78_SET_BUSY2_SHIFT 31 -/* POST_ROOT78_CLR Bit Fields */ -#define CCM_POST_ROOT78_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT78_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT78_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT78_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT78_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT78_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT78_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT78_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT78_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT78_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT78_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT78_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT78_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT78_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT78_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT78_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT78_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT78_CLR_BUSY2_SHIFT 31 -/* POST_ROOT78_TOG Bit Fields */ -#define CCM_POST_ROOT78_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT78_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT78_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT78_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT78_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT78_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT78_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT78_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT78_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT78_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT78_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT78_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT78_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT78_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT78_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT78_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT78_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT78_TOG_BUSY2_SHIFT 31 -/* PRE78 Bit Fields */ -#define CCM_PRE78_PRE_PODF_B_MASK 0x7u -#define CCM_PRE78_PRE_PODF_B_SHIFT 0 -#define CCM_PRE78_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE78_PRE_PODF_B_SHIFT))&CCM_PRE78_PRE_PODF_B_MASK) -#define CCM_PRE78_BUSY0_MASK 0x8u -#define CCM_PRE78_BUSY0_SHIFT 3 -#define CCM_PRE78_MUX_B_MASK 0x700u -#define CCM_PRE78_MUX_B_SHIFT 8 -#define CCM_PRE78_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE78_MUX_B_SHIFT))&CCM_PRE78_MUX_B_MASK) -#define CCM_PRE78_EN_B_MASK 0x1000u -#define CCM_PRE78_EN_B_SHIFT 12 -#define CCM_PRE78_BUSY1_MASK 0x8000u -#define CCM_PRE78_BUSY1_SHIFT 15 -#define CCM_PRE78_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE78_PRE_PODF_A_SHIFT 16 -#define CCM_PRE78_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE78_PRE_PODF_A_SHIFT))&CCM_PRE78_PRE_PODF_A_MASK) -#define CCM_PRE78_BUSY3_MASK 0x80000u -#define CCM_PRE78_BUSY3_SHIFT 19 -#define CCM_PRE78_MUX_A_MASK 0x7000000u -#define CCM_PRE78_MUX_A_SHIFT 24 -#define CCM_PRE78_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE78_MUX_A_SHIFT))&CCM_PRE78_MUX_A_MASK) -#define CCM_PRE78_EN_A_MASK 0x10000000u -#define CCM_PRE78_EN_A_SHIFT 28 -#define CCM_PRE78_BUSY4_MASK 0x80000000u -#define CCM_PRE78_BUSY4_SHIFT 31 -/* PRE_ROOT78_SET Bit Fields */ -#define CCM_PRE_ROOT78_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT78_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT78_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT78_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT78_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT78_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT78_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT78_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT78_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_SET_MUX_B_SHIFT))&CCM_PRE_ROOT78_SET_MUX_B_MASK) -#define CCM_PRE_ROOT78_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT78_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT78_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT78_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT78_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT78_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT78_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT78_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT78_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT78_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT78_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT78_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT78_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_SET_MUX_A_SHIFT))&CCM_PRE_ROOT78_SET_MUX_A_MASK) -#define CCM_PRE_ROOT78_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT78_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT78_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT78_SET_BUSY4_SHIFT 31 -/* PRE_ROOT78_CLR Bit Fields */ -#define CCM_PRE_ROOT78_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT78_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT78_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT78_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT78_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT78_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT78_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT78_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT78_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT78_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT78_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT78_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT78_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT78_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT78_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT78_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT78_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT78_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT78_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT78_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT78_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT78_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT78_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT78_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT78_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT78_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT78_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT78_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT78_TOG Bit Fields */ -#define CCM_PRE_ROOT78_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT78_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT78_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT78_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT78_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT78_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT78_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT78_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT78_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT78_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT78_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT78_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT78_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT78_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT78_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT78_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT78_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT78_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT78_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT78_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT78_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT78_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT78_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT78_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT78_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT78_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT78_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT78_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL78 Bit Fields */ -#define CCM_ACCESS_CTRL78_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL78_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL78_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL78_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL78_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL78_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL78_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL78_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL78_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL78_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL78_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL78_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL78_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL78_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL78_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL78_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL78_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL78_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL78_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL78_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL78_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL78_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL78_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL78_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL78_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL78_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL78_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL78_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL78_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL78_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL78_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL78_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL78_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL78_LOCK_SHIFT 31 -/* ACCESS_CTRL78_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL78_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL78_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL78_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL78_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL78_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL78_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL78_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL78_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL78_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL78_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL78_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL78_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL78_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL78_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL78_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL78_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT79 Bit Fields */ -#define CCM_TARGET_ROOT79_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT79_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT79_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_POST_PODF_SHIFT))&CCM_TARGET_ROOT79_POST_PODF_MASK) -#define CCM_TARGET_ROOT79_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT79_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT79_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT79_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT79_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT79_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT79_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT79_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT79_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT79_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT79_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_PRE_PODF_SHIFT))&CCM_TARGET_ROOT79_PRE_PODF_MASK) -#define CCM_TARGET_ROOT79_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT79_MUX_SHIFT 24 -#define CCM_TARGET_ROOT79_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_MUX_SHIFT))&CCM_TARGET_ROOT79_MUX_MASK) -#define CCM_TARGET_ROOT79_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT79_ENABLE_SHIFT 28 -/* TARGET_ROOT79_SET Bit Fields */ -#define CCM_TARGET_ROOT79_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT79_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT79_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT79_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT79_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT79_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT79_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT79_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT79_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT79_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT79_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT79_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT79_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT79_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT79_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT79_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT79_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT79_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT79_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_SET_MUX_SHIFT))&CCM_TARGET_ROOT79_SET_MUX_MASK) -#define CCM_TARGET_ROOT79_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT79_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT79_CLR Bit Fields */ -#define CCM_TARGET_ROOT79_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT79_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT79_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT79_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT79_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT79_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT79_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT79_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT79_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT79_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT79_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT79_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT79_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT79_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT79_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT79_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT79_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT79_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT79_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_CLR_MUX_SHIFT))&CCM_TARGET_ROOT79_CLR_MUX_MASK) -#define CCM_TARGET_ROOT79_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT79_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT79_TOG Bit Fields */ -#define CCM_TARGET_ROOT79_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT79_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT79_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT79_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT79_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT79_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT79_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT79_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT79_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT79_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT79_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT79_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT79_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT79_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT79_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT79_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT79_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT79_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT79_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_TOG_MUX_SHIFT))&CCM_TARGET_ROOT79_TOG_MUX_MASK) -#define CCM_TARGET_ROOT79_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT79_TOG_ENABLE_SHIFT 28 -/* POST79 Bit Fields */ -#define CCM_POST79_POST_PODF_MASK 0x3Fu -#define CCM_POST79_POST_PODF_SHIFT 0 -#define CCM_POST79_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST79_POST_PODF_SHIFT))&CCM_POST79_POST_PODF_MASK) -#define CCM_POST79_BUSY1_MASK 0x80u -#define CCM_POST79_BUSY1_SHIFT 7 -#define CCM_POST79_AUTO_PODF_MASK 0x700u -#define CCM_POST79_AUTO_PODF_SHIFT 8 -#define CCM_POST79_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST79_AUTO_PODF_SHIFT))&CCM_POST79_AUTO_PODF_MASK) -#define CCM_POST79_AUTO_EN_MASK 0x1000u -#define CCM_POST79_AUTO_EN_SHIFT 12 -#define CCM_POST79_SLOW_MASK 0x8000u -#define CCM_POST79_SLOW_SHIFT 15 -#define CCM_POST79_SELECT_MASK 0x10000000u -#define CCM_POST79_SELECT_SHIFT 28 -#define CCM_POST79_BUSY2_MASK 0x80000000u -#define CCM_POST79_BUSY2_SHIFT 31 -/* POST_ROOT79_SET Bit Fields */ -#define CCM_POST_ROOT79_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT79_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT79_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_SET_POST_PODF_SHIFT))&CCM_POST_ROOT79_SET_POST_PODF_MASK) -#define CCM_POST_ROOT79_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT79_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT79_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT79_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT79_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT79_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT79_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT79_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT79_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT79_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT79_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT79_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT79_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT79_SET_BUSY2_SHIFT 31 -/* POST_ROOT79_CLR Bit Fields */ -#define CCM_POST_ROOT79_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT79_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT79_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT79_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT79_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT79_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT79_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT79_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT79_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT79_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT79_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT79_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT79_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT79_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT79_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT79_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT79_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT79_CLR_BUSY2_SHIFT 31 -/* POST_ROOT79_TOG Bit Fields */ -#define CCM_POST_ROOT79_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT79_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT79_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT79_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT79_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT79_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT79_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT79_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT79_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT79_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT79_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT79_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT79_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT79_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT79_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT79_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT79_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT79_TOG_BUSY2_SHIFT 31 -/* PRE79 Bit Fields */ -#define CCM_PRE79_PRE_PODF_B_MASK 0x7u -#define CCM_PRE79_PRE_PODF_B_SHIFT 0 -#define CCM_PRE79_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE79_PRE_PODF_B_SHIFT))&CCM_PRE79_PRE_PODF_B_MASK) -#define CCM_PRE79_BUSY0_MASK 0x8u -#define CCM_PRE79_BUSY0_SHIFT 3 -#define CCM_PRE79_MUX_B_MASK 0x700u -#define CCM_PRE79_MUX_B_SHIFT 8 -#define CCM_PRE79_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE79_MUX_B_SHIFT))&CCM_PRE79_MUX_B_MASK) -#define CCM_PRE79_EN_B_MASK 0x1000u -#define CCM_PRE79_EN_B_SHIFT 12 -#define CCM_PRE79_BUSY1_MASK 0x8000u -#define CCM_PRE79_BUSY1_SHIFT 15 -#define CCM_PRE79_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE79_PRE_PODF_A_SHIFT 16 -#define CCM_PRE79_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE79_PRE_PODF_A_SHIFT))&CCM_PRE79_PRE_PODF_A_MASK) -#define CCM_PRE79_BUSY3_MASK 0x80000u -#define CCM_PRE79_BUSY3_SHIFT 19 -#define CCM_PRE79_MUX_A_MASK 0x7000000u -#define CCM_PRE79_MUX_A_SHIFT 24 -#define CCM_PRE79_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE79_MUX_A_SHIFT))&CCM_PRE79_MUX_A_MASK) -#define CCM_PRE79_EN_A_MASK 0x10000000u -#define CCM_PRE79_EN_A_SHIFT 28 -#define CCM_PRE79_BUSY4_MASK 0x80000000u -#define CCM_PRE79_BUSY4_SHIFT 31 -/* PRE_ROOT79_SET Bit Fields */ -#define CCM_PRE_ROOT79_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT79_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT79_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT79_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT79_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT79_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT79_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT79_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT79_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_SET_MUX_B_SHIFT))&CCM_PRE_ROOT79_SET_MUX_B_MASK) -#define CCM_PRE_ROOT79_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT79_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT79_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT79_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT79_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT79_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT79_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT79_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT79_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT79_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT79_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT79_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT79_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_SET_MUX_A_SHIFT))&CCM_PRE_ROOT79_SET_MUX_A_MASK) -#define CCM_PRE_ROOT79_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT79_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT79_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT79_SET_BUSY4_SHIFT 31 -/* PRE_ROOT79_CLR Bit Fields */ -#define CCM_PRE_ROOT79_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT79_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT79_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT79_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT79_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT79_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT79_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT79_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT79_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT79_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT79_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT79_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT79_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT79_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT79_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT79_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT79_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT79_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT79_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT79_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT79_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT79_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT79_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT79_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT79_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT79_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT79_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT79_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT79_TOG Bit Fields */ -#define CCM_PRE_ROOT79_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT79_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT79_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT79_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT79_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT79_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT79_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT79_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT79_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT79_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT79_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT79_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT79_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT79_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT79_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT79_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT79_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT79_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT79_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT79_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT79_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT79_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT79_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT79_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT79_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT79_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT79_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT79_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL79 Bit Fields */ -#define CCM_ACCESS_CTRL79_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL79_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL79_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL79_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL79_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL79_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL79_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL79_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL79_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL79_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL79_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL79_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL79_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL79_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL79_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL79_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL79_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL79_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL79_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL79_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL79_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL79_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL79_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL79_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL79_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL79_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL79_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL79_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL79_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL79_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL79_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL79_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL79_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL79_LOCK_SHIFT 31 -/* ACCESS_CTRL79_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL79_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL79_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL79_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL79_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL79_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL79_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL79_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL79_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL79_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL79_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL79_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL79_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL79_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL79_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL79_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL79_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT80 Bit Fields */ -#define CCM_TARGET_ROOT80_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT80_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT80_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_POST_PODF_SHIFT))&CCM_TARGET_ROOT80_POST_PODF_MASK) -#define CCM_TARGET_ROOT80_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT80_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT80_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT80_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT80_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT80_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT80_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT80_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT80_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT80_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT80_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_PRE_PODF_SHIFT))&CCM_TARGET_ROOT80_PRE_PODF_MASK) -#define CCM_TARGET_ROOT80_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT80_MUX_SHIFT 24 -#define CCM_TARGET_ROOT80_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_MUX_SHIFT))&CCM_TARGET_ROOT80_MUX_MASK) -#define CCM_TARGET_ROOT80_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT80_ENABLE_SHIFT 28 -/* TARGET_ROOT80_SET Bit Fields */ -#define CCM_TARGET_ROOT80_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT80_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT80_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT80_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT80_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT80_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT80_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT80_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT80_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT80_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT80_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT80_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT80_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT80_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT80_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT80_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT80_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT80_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT80_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_SET_MUX_SHIFT))&CCM_TARGET_ROOT80_SET_MUX_MASK) -#define CCM_TARGET_ROOT80_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT80_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT80_CLR Bit Fields */ -#define CCM_TARGET_ROOT80_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT80_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT80_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT80_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT80_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT80_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT80_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT80_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT80_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT80_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT80_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT80_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT80_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT80_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT80_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT80_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT80_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT80_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT80_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_CLR_MUX_SHIFT))&CCM_TARGET_ROOT80_CLR_MUX_MASK) -#define CCM_TARGET_ROOT80_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT80_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT80_TOG Bit Fields */ -#define CCM_TARGET_ROOT80_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT80_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT80_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT80_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT80_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT80_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT80_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT80_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT80_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT80_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT80_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT80_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT80_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT80_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT80_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT80_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT80_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT80_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT80_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_TOG_MUX_SHIFT))&CCM_TARGET_ROOT80_TOG_MUX_MASK) -#define CCM_TARGET_ROOT80_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT80_TOG_ENABLE_SHIFT 28 -/* POST80 Bit Fields */ -#define CCM_POST80_POST_PODF_MASK 0x3Fu -#define CCM_POST80_POST_PODF_SHIFT 0 -#define CCM_POST80_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST80_POST_PODF_SHIFT))&CCM_POST80_POST_PODF_MASK) -#define CCM_POST80_BUSY1_MASK 0x80u -#define CCM_POST80_BUSY1_SHIFT 7 -#define CCM_POST80_AUTO_PODF_MASK 0x700u -#define CCM_POST80_AUTO_PODF_SHIFT 8 -#define CCM_POST80_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST80_AUTO_PODF_SHIFT))&CCM_POST80_AUTO_PODF_MASK) -#define CCM_POST80_AUTO_EN_MASK 0x1000u -#define CCM_POST80_AUTO_EN_SHIFT 12 -#define CCM_POST80_SLOW_MASK 0x8000u -#define CCM_POST80_SLOW_SHIFT 15 -#define CCM_POST80_SELECT_MASK 0x10000000u -#define CCM_POST80_SELECT_SHIFT 28 -#define CCM_POST80_BUSY2_MASK 0x80000000u -#define CCM_POST80_BUSY2_SHIFT 31 -/* POST_ROOT80_SET Bit Fields */ -#define CCM_POST_ROOT80_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT80_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT80_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_SET_POST_PODF_SHIFT))&CCM_POST_ROOT80_SET_POST_PODF_MASK) -#define CCM_POST_ROOT80_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT80_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT80_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT80_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT80_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT80_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT80_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT80_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT80_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT80_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT80_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT80_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT80_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT80_SET_BUSY2_SHIFT 31 -/* POST_ROOT80_CLR Bit Fields */ -#define CCM_POST_ROOT80_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT80_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT80_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT80_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT80_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT80_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT80_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT80_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT80_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT80_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT80_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT80_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT80_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT80_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT80_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT80_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT80_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT80_CLR_BUSY2_SHIFT 31 -/* POST_ROOT80_TOG Bit Fields */ -#define CCM_POST_ROOT80_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT80_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT80_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT80_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT80_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT80_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT80_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT80_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT80_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT80_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT80_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT80_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT80_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT80_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT80_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT80_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT80_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT80_TOG_BUSY2_SHIFT 31 -/* PRE80 Bit Fields */ -#define CCM_PRE80_PRE_PODF_B_MASK 0x7u -#define CCM_PRE80_PRE_PODF_B_SHIFT 0 -#define CCM_PRE80_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE80_PRE_PODF_B_SHIFT))&CCM_PRE80_PRE_PODF_B_MASK) -#define CCM_PRE80_BUSY0_MASK 0x8u -#define CCM_PRE80_BUSY0_SHIFT 3 -#define CCM_PRE80_MUX_B_MASK 0x700u -#define CCM_PRE80_MUX_B_SHIFT 8 -#define CCM_PRE80_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE80_MUX_B_SHIFT))&CCM_PRE80_MUX_B_MASK) -#define CCM_PRE80_EN_B_MASK 0x1000u -#define CCM_PRE80_EN_B_SHIFT 12 -#define CCM_PRE80_BUSY1_MASK 0x8000u -#define CCM_PRE80_BUSY1_SHIFT 15 -#define CCM_PRE80_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE80_PRE_PODF_A_SHIFT 16 -#define CCM_PRE80_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE80_PRE_PODF_A_SHIFT))&CCM_PRE80_PRE_PODF_A_MASK) -#define CCM_PRE80_BUSY3_MASK 0x80000u -#define CCM_PRE80_BUSY3_SHIFT 19 -#define CCM_PRE80_MUX_A_MASK 0x7000000u -#define CCM_PRE80_MUX_A_SHIFT 24 -#define CCM_PRE80_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE80_MUX_A_SHIFT))&CCM_PRE80_MUX_A_MASK) -#define CCM_PRE80_EN_A_MASK 0x10000000u -#define CCM_PRE80_EN_A_SHIFT 28 -#define CCM_PRE80_BUSY4_MASK 0x80000000u -#define CCM_PRE80_BUSY4_SHIFT 31 -/* PRE_ROOT80_SET Bit Fields */ -#define CCM_PRE_ROOT80_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT80_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT80_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT80_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT80_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT80_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT80_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT80_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT80_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_SET_MUX_B_SHIFT))&CCM_PRE_ROOT80_SET_MUX_B_MASK) -#define CCM_PRE_ROOT80_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT80_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT80_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT80_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT80_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT80_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT80_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT80_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT80_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT80_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT80_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT80_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT80_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_SET_MUX_A_SHIFT))&CCM_PRE_ROOT80_SET_MUX_A_MASK) -#define CCM_PRE_ROOT80_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT80_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT80_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT80_SET_BUSY4_SHIFT 31 -/* PRE_ROOT80_CLR Bit Fields */ -#define CCM_PRE_ROOT80_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT80_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT80_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT80_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT80_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT80_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT80_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT80_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT80_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT80_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT80_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT80_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT80_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT80_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT80_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT80_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT80_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT80_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT80_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT80_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT80_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT80_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT80_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT80_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT80_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT80_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT80_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT80_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT80_TOG Bit Fields */ -#define CCM_PRE_ROOT80_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT80_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT80_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT80_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT80_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT80_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT80_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT80_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT80_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT80_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT80_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT80_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT80_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT80_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT80_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT80_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT80_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT80_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT80_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT80_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT80_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT80_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT80_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT80_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT80_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT80_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT80_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT80_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL80 Bit Fields */ -#define CCM_ACCESS_CTRL80_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL80_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL80_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL80_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL80_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL80_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL80_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL80_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL80_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL80_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL80_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL80_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL80_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL80_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL80_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL80_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL80_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL80_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL80_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL80_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL80_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL80_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL80_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL80_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL80_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL80_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL80_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL80_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL80_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL80_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL80_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL80_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL80_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL80_LOCK_SHIFT 31 -/* ACCESS_CTRL80_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL80_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL80_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL80_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL80_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL80_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL80_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL80_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL80_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL80_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL80_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL80_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL80_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL80_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL80_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL80_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL80_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT81 Bit Fields */ -#define CCM_TARGET_ROOT81_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT81_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT81_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_POST_PODF_SHIFT))&CCM_TARGET_ROOT81_POST_PODF_MASK) -#define CCM_TARGET_ROOT81_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT81_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT81_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT81_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT81_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT81_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT81_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT81_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT81_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT81_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT81_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_PRE_PODF_SHIFT))&CCM_TARGET_ROOT81_PRE_PODF_MASK) -#define CCM_TARGET_ROOT81_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT81_MUX_SHIFT 24 -#define CCM_TARGET_ROOT81_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_MUX_SHIFT))&CCM_TARGET_ROOT81_MUX_MASK) -#define CCM_TARGET_ROOT81_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT81_ENABLE_SHIFT 28 -/* TARGET_ROOT81_SET Bit Fields */ -#define CCM_TARGET_ROOT81_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT81_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT81_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT81_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT81_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT81_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT81_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT81_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT81_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT81_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT81_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT81_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT81_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT81_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT81_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT81_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT81_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT81_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT81_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_SET_MUX_SHIFT))&CCM_TARGET_ROOT81_SET_MUX_MASK) -#define CCM_TARGET_ROOT81_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT81_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT81_CLR Bit Fields */ -#define CCM_TARGET_ROOT81_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT81_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT81_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT81_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT81_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT81_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT81_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT81_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT81_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT81_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT81_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT81_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT81_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT81_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT81_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT81_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT81_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT81_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT81_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_CLR_MUX_SHIFT))&CCM_TARGET_ROOT81_CLR_MUX_MASK) -#define CCM_TARGET_ROOT81_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT81_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT81_TOG Bit Fields */ -#define CCM_TARGET_ROOT81_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT81_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT81_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT81_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT81_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT81_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT81_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT81_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT81_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT81_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT81_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT81_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT81_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT81_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT81_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT81_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT81_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT81_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT81_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_TOG_MUX_SHIFT))&CCM_TARGET_ROOT81_TOG_MUX_MASK) -#define CCM_TARGET_ROOT81_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT81_TOG_ENABLE_SHIFT 28 -/* POST81 Bit Fields */ -#define CCM_POST81_POST_PODF_MASK 0x3Fu -#define CCM_POST81_POST_PODF_SHIFT 0 -#define CCM_POST81_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST81_POST_PODF_SHIFT))&CCM_POST81_POST_PODF_MASK) -#define CCM_POST81_BUSY1_MASK 0x80u -#define CCM_POST81_BUSY1_SHIFT 7 -#define CCM_POST81_AUTO_PODF_MASK 0x700u -#define CCM_POST81_AUTO_PODF_SHIFT 8 -#define CCM_POST81_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST81_AUTO_PODF_SHIFT))&CCM_POST81_AUTO_PODF_MASK) -#define CCM_POST81_AUTO_EN_MASK 0x1000u -#define CCM_POST81_AUTO_EN_SHIFT 12 -#define CCM_POST81_SLOW_MASK 0x8000u -#define CCM_POST81_SLOW_SHIFT 15 -#define CCM_POST81_SELECT_MASK 0x10000000u -#define CCM_POST81_SELECT_SHIFT 28 -#define CCM_POST81_BUSY2_MASK 0x80000000u -#define CCM_POST81_BUSY2_SHIFT 31 -/* POST_ROOT81_SET Bit Fields */ -#define CCM_POST_ROOT81_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT81_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT81_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_SET_POST_PODF_SHIFT))&CCM_POST_ROOT81_SET_POST_PODF_MASK) -#define CCM_POST_ROOT81_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT81_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT81_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT81_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT81_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT81_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT81_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT81_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT81_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT81_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT81_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT81_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT81_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT81_SET_BUSY2_SHIFT 31 -/* POST_ROOT81_CLR Bit Fields */ -#define CCM_POST_ROOT81_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT81_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT81_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT81_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT81_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT81_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT81_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT81_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT81_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT81_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT81_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT81_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT81_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT81_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT81_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT81_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT81_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT81_CLR_BUSY2_SHIFT 31 -/* POST_ROOT81_TOG Bit Fields */ -#define CCM_POST_ROOT81_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT81_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT81_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT81_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT81_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT81_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT81_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT81_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT81_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT81_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT81_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT81_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT81_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT81_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT81_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT81_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT81_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT81_TOG_BUSY2_SHIFT 31 -/* PRE81 Bit Fields */ -#define CCM_PRE81_PRE_PODF_B_MASK 0x7u -#define CCM_PRE81_PRE_PODF_B_SHIFT 0 -#define CCM_PRE81_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE81_PRE_PODF_B_SHIFT))&CCM_PRE81_PRE_PODF_B_MASK) -#define CCM_PRE81_BUSY0_MASK 0x8u -#define CCM_PRE81_BUSY0_SHIFT 3 -#define CCM_PRE81_MUX_B_MASK 0x700u -#define CCM_PRE81_MUX_B_SHIFT 8 -#define CCM_PRE81_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE81_MUX_B_SHIFT))&CCM_PRE81_MUX_B_MASK) -#define CCM_PRE81_EN_B_MASK 0x1000u -#define CCM_PRE81_EN_B_SHIFT 12 -#define CCM_PRE81_BUSY1_MASK 0x8000u -#define CCM_PRE81_BUSY1_SHIFT 15 -#define CCM_PRE81_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE81_PRE_PODF_A_SHIFT 16 -#define CCM_PRE81_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE81_PRE_PODF_A_SHIFT))&CCM_PRE81_PRE_PODF_A_MASK) -#define CCM_PRE81_BUSY3_MASK 0x80000u -#define CCM_PRE81_BUSY3_SHIFT 19 -#define CCM_PRE81_MUX_A_MASK 0x7000000u -#define CCM_PRE81_MUX_A_SHIFT 24 -#define CCM_PRE81_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE81_MUX_A_SHIFT))&CCM_PRE81_MUX_A_MASK) -#define CCM_PRE81_EN_A_MASK 0x10000000u -#define CCM_PRE81_EN_A_SHIFT 28 -#define CCM_PRE81_BUSY4_MASK 0x80000000u -#define CCM_PRE81_BUSY4_SHIFT 31 -/* PRE_ROOT81_SET Bit Fields */ -#define CCM_PRE_ROOT81_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT81_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT81_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT81_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT81_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT81_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT81_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT81_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT81_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_SET_MUX_B_SHIFT))&CCM_PRE_ROOT81_SET_MUX_B_MASK) -#define CCM_PRE_ROOT81_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT81_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT81_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT81_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT81_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT81_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT81_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT81_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT81_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT81_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT81_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT81_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT81_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_SET_MUX_A_SHIFT))&CCM_PRE_ROOT81_SET_MUX_A_MASK) -#define CCM_PRE_ROOT81_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT81_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT81_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT81_SET_BUSY4_SHIFT 31 -/* PRE_ROOT81_CLR Bit Fields */ -#define CCM_PRE_ROOT81_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT81_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT81_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT81_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT81_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT81_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT81_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT81_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT81_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT81_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT81_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT81_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT81_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT81_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT81_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT81_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT81_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT81_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT81_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT81_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT81_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT81_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT81_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT81_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT81_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT81_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT81_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT81_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT81_TOG Bit Fields */ -#define CCM_PRE_ROOT81_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT81_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT81_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT81_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT81_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT81_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT81_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT81_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT81_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT81_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT81_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT81_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT81_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT81_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT81_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT81_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT81_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT81_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT81_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT81_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT81_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT81_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT81_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT81_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT81_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT81_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT81_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT81_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL81 Bit Fields */ -#define CCM_ACCESS_CTRL81_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL81_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL81_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL81_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL81_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL81_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL81_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL81_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL81_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL81_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL81_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL81_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL81_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL81_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL81_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL81_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL81_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL81_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL81_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL81_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL81_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL81_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL81_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL81_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL81_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL81_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL81_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL81_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL81_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL81_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL81_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL81_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL81_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL81_LOCK_SHIFT 31 -/* ACCESS_CTRL81_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL81_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL81_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL81_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL81_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL81_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL81_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL81_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL81_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL81_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL81_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL81_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL81_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL81_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL81_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL81_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL81_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT82 Bit Fields */ -#define CCM_TARGET_ROOT82_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT82_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT82_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_POST_PODF_SHIFT))&CCM_TARGET_ROOT82_POST_PODF_MASK) -#define CCM_TARGET_ROOT82_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT82_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT82_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT82_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT82_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT82_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT82_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT82_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT82_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT82_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT82_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_PRE_PODF_SHIFT))&CCM_TARGET_ROOT82_PRE_PODF_MASK) -#define CCM_TARGET_ROOT82_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT82_MUX_SHIFT 24 -#define CCM_TARGET_ROOT82_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_MUX_SHIFT))&CCM_TARGET_ROOT82_MUX_MASK) -#define CCM_TARGET_ROOT82_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT82_ENABLE_SHIFT 28 -/* TARGET_ROOT82_SET Bit Fields */ -#define CCM_TARGET_ROOT82_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT82_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT82_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT82_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT82_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT82_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT82_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT82_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT82_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT82_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT82_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT82_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT82_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT82_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT82_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT82_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT82_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT82_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT82_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_SET_MUX_SHIFT))&CCM_TARGET_ROOT82_SET_MUX_MASK) -#define CCM_TARGET_ROOT82_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT82_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT82_CLR Bit Fields */ -#define CCM_TARGET_ROOT82_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT82_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT82_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT82_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT82_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT82_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT82_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT82_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT82_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT82_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT82_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT82_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT82_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT82_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT82_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT82_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT82_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT82_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT82_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_CLR_MUX_SHIFT))&CCM_TARGET_ROOT82_CLR_MUX_MASK) -#define CCM_TARGET_ROOT82_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT82_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT82_TOG Bit Fields */ -#define CCM_TARGET_ROOT82_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT82_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT82_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT82_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT82_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT82_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT82_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT82_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT82_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT82_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT82_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT82_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT82_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT82_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT82_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT82_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT82_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT82_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT82_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_TOG_MUX_SHIFT))&CCM_TARGET_ROOT82_TOG_MUX_MASK) -#define CCM_TARGET_ROOT82_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT82_TOG_ENABLE_SHIFT 28 -/* POST82 Bit Fields */ -#define CCM_POST82_POST_PODF_MASK 0x3Fu -#define CCM_POST82_POST_PODF_SHIFT 0 -#define CCM_POST82_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST82_POST_PODF_SHIFT))&CCM_POST82_POST_PODF_MASK) -#define CCM_POST82_BUSY1_MASK 0x80u -#define CCM_POST82_BUSY1_SHIFT 7 -#define CCM_POST82_AUTO_PODF_MASK 0x700u -#define CCM_POST82_AUTO_PODF_SHIFT 8 -#define CCM_POST82_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST82_AUTO_PODF_SHIFT))&CCM_POST82_AUTO_PODF_MASK) -#define CCM_POST82_AUTO_EN_MASK 0x1000u -#define CCM_POST82_AUTO_EN_SHIFT 12 -#define CCM_POST82_SLOW_MASK 0x8000u -#define CCM_POST82_SLOW_SHIFT 15 -#define CCM_POST82_SELECT_MASK 0x10000000u -#define CCM_POST82_SELECT_SHIFT 28 -#define CCM_POST82_BUSY2_MASK 0x80000000u -#define CCM_POST82_BUSY2_SHIFT 31 -/* POST_ROOT82_SET Bit Fields */ -#define CCM_POST_ROOT82_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT82_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT82_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_SET_POST_PODF_SHIFT))&CCM_POST_ROOT82_SET_POST_PODF_MASK) -#define CCM_POST_ROOT82_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT82_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT82_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT82_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT82_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT82_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT82_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT82_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT82_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT82_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT82_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT82_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT82_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT82_SET_BUSY2_SHIFT 31 -/* POST_ROOT82_CLR Bit Fields */ -#define CCM_POST_ROOT82_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT82_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT82_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT82_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT82_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT82_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT82_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT82_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT82_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT82_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT82_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT82_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT82_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT82_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT82_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT82_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT82_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT82_CLR_BUSY2_SHIFT 31 -/* POST_ROOT82_TOG Bit Fields */ -#define CCM_POST_ROOT82_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT82_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT82_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT82_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT82_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT82_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT82_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT82_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT82_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT82_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT82_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT82_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT82_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT82_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT82_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT82_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT82_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT82_TOG_BUSY2_SHIFT 31 -/* PRE82 Bit Fields */ -#define CCM_PRE82_PRE_PODF_B_MASK 0x7u -#define CCM_PRE82_PRE_PODF_B_SHIFT 0 -#define CCM_PRE82_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE82_PRE_PODF_B_SHIFT))&CCM_PRE82_PRE_PODF_B_MASK) -#define CCM_PRE82_BUSY0_MASK 0x8u -#define CCM_PRE82_BUSY0_SHIFT 3 -#define CCM_PRE82_MUX_B_MASK 0x700u -#define CCM_PRE82_MUX_B_SHIFT 8 -#define CCM_PRE82_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE82_MUX_B_SHIFT))&CCM_PRE82_MUX_B_MASK) -#define CCM_PRE82_EN_B_MASK 0x1000u -#define CCM_PRE82_EN_B_SHIFT 12 -#define CCM_PRE82_BUSY1_MASK 0x8000u -#define CCM_PRE82_BUSY1_SHIFT 15 -#define CCM_PRE82_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE82_PRE_PODF_A_SHIFT 16 -#define CCM_PRE82_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE82_PRE_PODF_A_SHIFT))&CCM_PRE82_PRE_PODF_A_MASK) -#define CCM_PRE82_BUSY3_MASK 0x80000u -#define CCM_PRE82_BUSY3_SHIFT 19 -#define CCM_PRE82_MUX_A_MASK 0x7000000u -#define CCM_PRE82_MUX_A_SHIFT 24 -#define CCM_PRE82_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE82_MUX_A_SHIFT))&CCM_PRE82_MUX_A_MASK) -#define CCM_PRE82_EN_A_MASK 0x10000000u -#define CCM_PRE82_EN_A_SHIFT 28 -#define CCM_PRE82_BUSY4_MASK 0x80000000u -#define CCM_PRE82_BUSY4_SHIFT 31 -/* PRE_ROOT82_SET Bit Fields */ -#define CCM_PRE_ROOT82_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT82_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT82_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT82_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT82_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT82_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT82_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT82_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT82_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_SET_MUX_B_SHIFT))&CCM_PRE_ROOT82_SET_MUX_B_MASK) -#define CCM_PRE_ROOT82_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT82_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT82_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT82_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT82_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT82_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT82_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT82_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT82_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT82_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT82_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT82_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT82_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_SET_MUX_A_SHIFT))&CCM_PRE_ROOT82_SET_MUX_A_MASK) -#define CCM_PRE_ROOT82_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT82_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT82_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT82_SET_BUSY4_SHIFT 31 -/* PRE_ROOT82_CLR Bit Fields */ -#define CCM_PRE_ROOT82_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT82_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT82_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT82_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT82_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT82_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT82_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT82_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT82_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT82_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT82_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT82_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT82_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT82_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT82_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT82_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT82_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT82_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT82_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT82_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT82_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT82_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT82_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT82_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT82_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT82_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT82_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT82_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT82_TOG Bit Fields */ -#define CCM_PRE_ROOT82_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT82_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT82_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT82_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT82_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT82_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT82_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT82_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT82_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT82_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT82_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT82_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT82_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT82_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT82_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT82_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT82_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT82_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT82_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT82_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT82_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT82_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT82_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT82_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT82_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT82_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT82_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT82_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL82 Bit Fields */ -#define CCM_ACCESS_CTRL82_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL82_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL82_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL82_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL82_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL82_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL82_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL82_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL82_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL82_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL82_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL82_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL82_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL82_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL82_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL82_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL82_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL82_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL82_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL82_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL82_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL82_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL82_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL82_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL82_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL82_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL82_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL82_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL82_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL82_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL82_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL82_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL82_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL82_LOCK_SHIFT 31 -/* ACCESS_CTRL82_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL82_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL82_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL82_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL82_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL82_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL82_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL82_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL82_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL82_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL82_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL82_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL82_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL82_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL82_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL82_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL82_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT83 Bit Fields */ -#define CCM_TARGET_ROOT83_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT83_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT83_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_POST_PODF_SHIFT))&CCM_TARGET_ROOT83_POST_PODF_MASK) -#define CCM_TARGET_ROOT83_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT83_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT83_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT83_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT83_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT83_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT83_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT83_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT83_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT83_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT83_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_PRE_PODF_SHIFT))&CCM_TARGET_ROOT83_PRE_PODF_MASK) -#define CCM_TARGET_ROOT83_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT83_MUX_SHIFT 24 -#define CCM_TARGET_ROOT83_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_MUX_SHIFT))&CCM_TARGET_ROOT83_MUX_MASK) -#define CCM_TARGET_ROOT83_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT83_ENABLE_SHIFT 28 -/* TARGET_ROOT83_SET Bit Fields */ -#define CCM_TARGET_ROOT83_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT83_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT83_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT83_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT83_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT83_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT83_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT83_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT83_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT83_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT83_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT83_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT83_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT83_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT83_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT83_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT83_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT83_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT83_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_SET_MUX_SHIFT))&CCM_TARGET_ROOT83_SET_MUX_MASK) -#define CCM_TARGET_ROOT83_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT83_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT83_CLR Bit Fields */ -#define CCM_TARGET_ROOT83_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT83_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT83_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT83_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT83_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT83_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT83_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT83_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT83_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT83_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT83_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT83_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT83_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT83_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT83_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT83_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT83_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT83_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT83_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_CLR_MUX_SHIFT))&CCM_TARGET_ROOT83_CLR_MUX_MASK) -#define CCM_TARGET_ROOT83_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT83_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT83_TOG Bit Fields */ -#define CCM_TARGET_ROOT83_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT83_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT83_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT83_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT83_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT83_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT83_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT83_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT83_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT83_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT83_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT83_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT83_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT83_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT83_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT83_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT83_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT83_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT83_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_TOG_MUX_SHIFT))&CCM_TARGET_ROOT83_TOG_MUX_MASK) -#define CCM_TARGET_ROOT83_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT83_TOG_ENABLE_SHIFT 28 -/* POST83 Bit Fields */ -#define CCM_POST83_POST_PODF_MASK 0x3Fu -#define CCM_POST83_POST_PODF_SHIFT 0 -#define CCM_POST83_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST83_POST_PODF_SHIFT))&CCM_POST83_POST_PODF_MASK) -#define CCM_POST83_BUSY1_MASK 0x80u -#define CCM_POST83_BUSY1_SHIFT 7 -#define CCM_POST83_AUTO_PODF_MASK 0x700u -#define CCM_POST83_AUTO_PODF_SHIFT 8 -#define CCM_POST83_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST83_AUTO_PODF_SHIFT))&CCM_POST83_AUTO_PODF_MASK) -#define CCM_POST83_AUTO_EN_MASK 0x1000u -#define CCM_POST83_AUTO_EN_SHIFT 12 -#define CCM_POST83_SLOW_MASK 0x8000u -#define CCM_POST83_SLOW_SHIFT 15 -#define CCM_POST83_SELECT_MASK 0x10000000u -#define CCM_POST83_SELECT_SHIFT 28 -#define CCM_POST83_BUSY2_MASK 0x80000000u -#define CCM_POST83_BUSY2_SHIFT 31 -/* POST_ROOT83_SET Bit Fields */ -#define CCM_POST_ROOT83_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT83_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT83_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_SET_POST_PODF_SHIFT))&CCM_POST_ROOT83_SET_POST_PODF_MASK) -#define CCM_POST_ROOT83_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT83_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT83_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT83_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT83_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT83_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT83_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT83_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT83_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT83_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT83_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT83_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT83_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT83_SET_BUSY2_SHIFT 31 -/* POST_ROOT83_CLR Bit Fields */ -#define CCM_POST_ROOT83_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT83_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT83_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT83_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT83_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT83_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT83_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT83_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT83_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT83_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT83_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT83_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT83_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT83_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT83_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT83_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT83_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT83_CLR_BUSY2_SHIFT 31 -/* POST_ROOT83_TOG Bit Fields */ -#define CCM_POST_ROOT83_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT83_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT83_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT83_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT83_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT83_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT83_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT83_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT83_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT83_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT83_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT83_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT83_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT83_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT83_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT83_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT83_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT83_TOG_BUSY2_SHIFT 31 -/* PRE83 Bit Fields */ -#define CCM_PRE83_PRE_PODF_B_MASK 0x7u -#define CCM_PRE83_PRE_PODF_B_SHIFT 0 -#define CCM_PRE83_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE83_PRE_PODF_B_SHIFT))&CCM_PRE83_PRE_PODF_B_MASK) -#define CCM_PRE83_BUSY0_MASK 0x8u -#define CCM_PRE83_BUSY0_SHIFT 3 -#define CCM_PRE83_MUX_B_MASK 0x700u -#define CCM_PRE83_MUX_B_SHIFT 8 -#define CCM_PRE83_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE83_MUX_B_SHIFT))&CCM_PRE83_MUX_B_MASK) -#define CCM_PRE83_EN_B_MASK 0x1000u -#define CCM_PRE83_EN_B_SHIFT 12 -#define CCM_PRE83_BUSY1_MASK 0x8000u -#define CCM_PRE83_BUSY1_SHIFT 15 -#define CCM_PRE83_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE83_PRE_PODF_A_SHIFT 16 -#define CCM_PRE83_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE83_PRE_PODF_A_SHIFT))&CCM_PRE83_PRE_PODF_A_MASK) -#define CCM_PRE83_BUSY3_MASK 0x80000u -#define CCM_PRE83_BUSY3_SHIFT 19 -#define CCM_PRE83_MUX_A_MASK 0x7000000u -#define CCM_PRE83_MUX_A_SHIFT 24 -#define CCM_PRE83_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE83_MUX_A_SHIFT))&CCM_PRE83_MUX_A_MASK) -#define CCM_PRE83_EN_A_MASK 0x10000000u -#define CCM_PRE83_EN_A_SHIFT 28 -#define CCM_PRE83_BUSY4_MASK 0x80000000u -#define CCM_PRE83_BUSY4_SHIFT 31 -/* PRE_ROOT83_SET Bit Fields */ -#define CCM_PRE_ROOT83_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT83_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT83_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT83_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT83_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT83_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT83_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT83_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT83_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_SET_MUX_B_SHIFT))&CCM_PRE_ROOT83_SET_MUX_B_MASK) -#define CCM_PRE_ROOT83_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT83_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT83_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT83_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT83_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT83_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT83_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT83_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT83_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT83_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT83_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT83_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT83_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_SET_MUX_A_SHIFT))&CCM_PRE_ROOT83_SET_MUX_A_MASK) -#define CCM_PRE_ROOT83_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT83_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT83_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT83_SET_BUSY4_SHIFT 31 -/* PRE_ROOT83_CLR Bit Fields */ -#define CCM_PRE_ROOT83_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT83_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT83_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT83_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT83_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT83_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT83_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT83_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT83_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT83_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT83_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT83_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT83_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT83_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT83_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT83_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT83_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT83_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT83_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT83_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT83_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT83_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT83_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT83_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT83_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT83_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT83_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT83_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT83_TOG Bit Fields */ -#define CCM_PRE_ROOT83_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT83_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT83_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT83_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT83_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT83_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT83_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT83_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT83_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT83_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT83_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT83_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT83_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT83_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT83_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT83_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT83_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT83_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT83_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT83_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT83_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT83_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT83_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT83_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT83_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT83_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT83_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT83_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL83 Bit Fields */ -#define CCM_ACCESS_CTRL83_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL83_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL83_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL83_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL83_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL83_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL83_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL83_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL83_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL83_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL83_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL83_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL83_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL83_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL83_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL83_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL83_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL83_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL83_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL83_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL83_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL83_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL83_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL83_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL83_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL83_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL83_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL83_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL83_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL83_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL83_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL83_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL83_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL83_LOCK_SHIFT 31 -/* ACCESS_CTRL83_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL83_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL83_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL83_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL83_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL83_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL83_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL83_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL83_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL83_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL83_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL83_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL83_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL83_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL83_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL83_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL83_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT84 Bit Fields */ -#define CCM_TARGET_ROOT84_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT84_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT84_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_POST_PODF_SHIFT))&CCM_TARGET_ROOT84_POST_PODF_MASK) -#define CCM_TARGET_ROOT84_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT84_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT84_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT84_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT84_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT84_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT84_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT84_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT84_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT84_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT84_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_PRE_PODF_SHIFT))&CCM_TARGET_ROOT84_PRE_PODF_MASK) -#define CCM_TARGET_ROOT84_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT84_MUX_SHIFT 24 -#define CCM_TARGET_ROOT84_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_MUX_SHIFT))&CCM_TARGET_ROOT84_MUX_MASK) -#define CCM_TARGET_ROOT84_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT84_ENABLE_SHIFT 28 -/* TARGET_ROOT84_SET Bit Fields */ -#define CCM_TARGET_ROOT84_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT84_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT84_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT84_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT84_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT84_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT84_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT84_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT84_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT84_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT84_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT84_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT84_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT84_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT84_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT84_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT84_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT84_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT84_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_SET_MUX_SHIFT))&CCM_TARGET_ROOT84_SET_MUX_MASK) -#define CCM_TARGET_ROOT84_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT84_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT84_CLR Bit Fields */ -#define CCM_TARGET_ROOT84_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT84_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT84_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT84_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT84_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT84_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT84_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT84_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT84_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT84_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT84_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT84_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT84_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT84_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT84_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT84_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT84_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT84_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT84_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_CLR_MUX_SHIFT))&CCM_TARGET_ROOT84_CLR_MUX_MASK) -#define CCM_TARGET_ROOT84_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT84_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT84_TOG Bit Fields */ -#define CCM_TARGET_ROOT84_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT84_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT84_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT84_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT84_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT84_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT84_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT84_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT84_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT84_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT84_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT84_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT84_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT84_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT84_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT84_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT84_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT84_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT84_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_TOG_MUX_SHIFT))&CCM_TARGET_ROOT84_TOG_MUX_MASK) -#define CCM_TARGET_ROOT84_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT84_TOG_ENABLE_SHIFT 28 -/* POST84 Bit Fields */ -#define CCM_POST84_POST_PODF_MASK 0x3Fu -#define CCM_POST84_POST_PODF_SHIFT 0 -#define CCM_POST84_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST84_POST_PODF_SHIFT))&CCM_POST84_POST_PODF_MASK) -#define CCM_POST84_BUSY1_MASK 0x80u -#define CCM_POST84_BUSY1_SHIFT 7 -#define CCM_POST84_AUTO_PODF_MASK 0x700u -#define CCM_POST84_AUTO_PODF_SHIFT 8 -#define CCM_POST84_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST84_AUTO_PODF_SHIFT))&CCM_POST84_AUTO_PODF_MASK) -#define CCM_POST84_AUTO_EN_MASK 0x1000u -#define CCM_POST84_AUTO_EN_SHIFT 12 -#define CCM_POST84_SLOW_MASK 0x8000u -#define CCM_POST84_SLOW_SHIFT 15 -#define CCM_POST84_SELECT_MASK 0x10000000u -#define CCM_POST84_SELECT_SHIFT 28 -#define CCM_POST84_BUSY2_MASK 0x80000000u -#define CCM_POST84_BUSY2_SHIFT 31 -/* POST_ROOT84_SET Bit Fields */ -#define CCM_POST_ROOT84_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT84_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT84_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_SET_POST_PODF_SHIFT))&CCM_POST_ROOT84_SET_POST_PODF_MASK) -#define CCM_POST_ROOT84_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT84_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT84_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT84_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT84_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT84_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT84_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT84_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT84_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT84_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT84_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT84_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT84_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT84_SET_BUSY2_SHIFT 31 -/* POST_ROOT84_CLR Bit Fields */ -#define CCM_POST_ROOT84_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT84_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT84_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT84_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT84_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT84_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT84_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT84_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT84_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT84_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT84_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT84_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT84_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT84_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT84_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT84_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT84_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT84_CLR_BUSY2_SHIFT 31 -/* POST_ROOT84_TOG Bit Fields */ -#define CCM_POST_ROOT84_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT84_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT84_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT84_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT84_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT84_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT84_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT84_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT84_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT84_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT84_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT84_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT84_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT84_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT84_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT84_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT84_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT84_TOG_BUSY2_SHIFT 31 -/* PRE84 Bit Fields */ -#define CCM_PRE84_PRE_PODF_B_MASK 0x7u -#define CCM_PRE84_PRE_PODF_B_SHIFT 0 -#define CCM_PRE84_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE84_PRE_PODF_B_SHIFT))&CCM_PRE84_PRE_PODF_B_MASK) -#define CCM_PRE84_BUSY0_MASK 0x8u -#define CCM_PRE84_BUSY0_SHIFT 3 -#define CCM_PRE84_MUX_B_MASK 0x700u -#define CCM_PRE84_MUX_B_SHIFT 8 -#define CCM_PRE84_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE84_MUX_B_SHIFT))&CCM_PRE84_MUX_B_MASK) -#define CCM_PRE84_EN_B_MASK 0x1000u -#define CCM_PRE84_EN_B_SHIFT 12 -#define CCM_PRE84_BUSY1_MASK 0x8000u -#define CCM_PRE84_BUSY1_SHIFT 15 -#define CCM_PRE84_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE84_PRE_PODF_A_SHIFT 16 -#define CCM_PRE84_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE84_PRE_PODF_A_SHIFT))&CCM_PRE84_PRE_PODF_A_MASK) -#define CCM_PRE84_BUSY3_MASK 0x80000u -#define CCM_PRE84_BUSY3_SHIFT 19 -#define CCM_PRE84_MUX_A_MASK 0x7000000u -#define CCM_PRE84_MUX_A_SHIFT 24 -#define CCM_PRE84_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE84_MUX_A_SHIFT))&CCM_PRE84_MUX_A_MASK) -#define CCM_PRE84_EN_A_MASK 0x10000000u -#define CCM_PRE84_EN_A_SHIFT 28 -#define CCM_PRE84_BUSY4_MASK 0x80000000u -#define CCM_PRE84_BUSY4_SHIFT 31 -/* PRE_ROOT84_SET Bit Fields */ -#define CCM_PRE_ROOT84_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT84_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT84_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT84_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT84_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT84_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT84_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT84_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT84_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_SET_MUX_B_SHIFT))&CCM_PRE_ROOT84_SET_MUX_B_MASK) -#define CCM_PRE_ROOT84_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT84_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT84_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT84_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT84_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT84_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT84_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT84_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT84_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT84_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT84_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT84_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT84_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_SET_MUX_A_SHIFT))&CCM_PRE_ROOT84_SET_MUX_A_MASK) -#define CCM_PRE_ROOT84_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT84_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT84_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT84_SET_BUSY4_SHIFT 31 -/* PRE_ROOT84_CLR Bit Fields */ -#define CCM_PRE_ROOT84_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT84_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT84_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT84_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT84_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT84_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT84_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT84_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT84_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT84_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT84_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT84_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT84_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT84_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT84_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT84_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT84_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT84_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT84_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT84_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT84_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT84_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT84_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT84_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT84_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT84_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT84_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT84_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT84_TOG Bit Fields */ -#define CCM_PRE_ROOT84_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT84_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT84_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT84_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT84_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT84_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT84_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT84_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT84_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT84_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT84_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT84_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT84_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT84_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT84_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT84_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT84_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT84_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT84_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT84_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT84_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT84_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT84_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT84_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT84_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT84_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT84_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT84_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL84 Bit Fields */ -#define CCM_ACCESS_CTRL84_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL84_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL84_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL84_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL84_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL84_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL84_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL84_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL84_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL84_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL84_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL84_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL84_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL84_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL84_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL84_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL84_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL84_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL84_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL84_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL84_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL84_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL84_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL84_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL84_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL84_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL84_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL84_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL84_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL84_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL84_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL84_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL84_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL84_LOCK_SHIFT 31 -/* ACCESS_CTRL84_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL84_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL84_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL84_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL84_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL84_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL84_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL84_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL84_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL84_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL84_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL84_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL84_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL84_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL84_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL84_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL84_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT85 Bit Fields */ -#define CCM_TARGET_ROOT85_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT85_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT85_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_POST_PODF_SHIFT))&CCM_TARGET_ROOT85_POST_PODF_MASK) -#define CCM_TARGET_ROOT85_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT85_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT85_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT85_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT85_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT85_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT85_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT85_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT85_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT85_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT85_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_PRE_PODF_SHIFT))&CCM_TARGET_ROOT85_PRE_PODF_MASK) -#define CCM_TARGET_ROOT85_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT85_MUX_SHIFT 24 -#define CCM_TARGET_ROOT85_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_MUX_SHIFT))&CCM_TARGET_ROOT85_MUX_MASK) -#define CCM_TARGET_ROOT85_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT85_ENABLE_SHIFT 28 -/* TARGET_ROOT85_SET Bit Fields */ -#define CCM_TARGET_ROOT85_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT85_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT85_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT85_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT85_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT85_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT85_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT85_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT85_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT85_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT85_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT85_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT85_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT85_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT85_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT85_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT85_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT85_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT85_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_SET_MUX_SHIFT))&CCM_TARGET_ROOT85_SET_MUX_MASK) -#define CCM_TARGET_ROOT85_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT85_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT85_CLR Bit Fields */ -#define CCM_TARGET_ROOT85_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT85_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT85_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT85_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT85_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT85_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT85_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT85_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT85_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT85_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT85_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT85_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT85_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT85_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT85_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT85_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT85_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT85_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT85_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_CLR_MUX_SHIFT))&CCM_TARGET_ROOT85_CLR_MUX_MASK) -#define CCM_TARGET_ROOT85_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT85_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT85_TOG Bit Fields */ -#define CCM_TARGET_ROOT85_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT85_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT85_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT85_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT85_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT85_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT85_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT85_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT85_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT85_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT85_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT85_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT85_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT85_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT85_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT85_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT85_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT85_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT85_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_TOG_MUX_SHIFT))&CCM_TARGET_ROOT85_TOG_MUX_MASK) -#define CCM_TARGET_ROOT85_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT85_TOG_ENABLE_SHIFT 28 -/* POST85 Bit Fields */ -#define CCM_POST85_POST_PODF_MASK 0x3Fu -#define CCM_POST85_POST_PODF_SHIFT 0 -#define CCM_POST85_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST85_POST_PODF_SHIFT))&CCM_POST85_POST_PODF_MASK) -#define CCM_POST85_BUSY1_MASK 0x80u -#define CCM_POST85_BUSY1_SHIFT 7 -#define CCM_POST85_AUTO_PODF_MASK 0x700u -#define CCM_POST85_AUTO_PODF_SHIFT 8 -#define CCM_POST85_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST85_AUTO_PODF_SHIFT))&CCM_POST85_AUTO_PODF_MASK) -#define CCM_POST85_AUTO_EN_MASK 0x1000u -#define CCM_POST85_AUTO_EN_SHIFT 12 -#define CCM_POST85_SLOW_MASK 0x8000u -#define CCM_POST85_SLOW_SHIFT 15 -#define CCM_POST85_SELECT_MASK 0x10000000u -#define CCM_POST85_SELECT_SHIFT 28 -#define CCM_POST85_BUSY2_MASK 0x80000000u -#define CCM_POST85_BUSY2_SHIFT 31 -/* POST_ROOT85_SET Bit Fields */ -#define CCM_POST_ROOT85_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT85_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT85_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_SET_POST_PODF_SHIFT))&CCM_POST_ROOT85_SET_POST_PODF_MASK) -#define CCM_POST_ROOT85_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT85_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT85_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT85_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT85_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT85_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT85_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT85_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT85_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT85_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT85_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT85_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT85_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT85_SET_BUSY2_SHIFT 31 -/* POST_ROOT85_CLR Bit Fields */ -#define CCM_POST_ROOT85_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT85_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT85_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT85_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT85_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT85_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT85_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT85_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT85_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT85_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT85_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT85_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT85_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT85_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT85_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT85_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT85_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT85_CLR_BUSY2_SHIFT 31 -/* POST_ROOT85_TOG Bit Fields */ -#define CCM_POST_ROOT85_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT85_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT85_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT85_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT85_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT85_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT85_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT85_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT85_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT85_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT85_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT85_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT85_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT85_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT85_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT85_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT85_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT85_TOG_BUSY2_SHIFT 31 -/* PRE85 Bit Fields */ -#define CCM_PRE85_PRE_PODF_B_MASK 0x7u -#define CCM_PRE85_PRE_PODF_B_SHIFT 0 -#define CCM_PRE85_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE85_PRE_PODF_B_SHIFT))&CCM_PRE85_PRE_PODF_B_MASK) -#define CCM_PRE85_BUSY0_MASK 0x8u -#define CCM_PRE85_BUSY0_SHIFT 3 -#define CCM_PRE85_MUX_B_MASK 0x700u -#define CCM_PRE85_MUX_B_SHIFT 8 -#define CCM_PRE85_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE85_MUX_B_SHIFT))&CCM_PRE85_MUX_B_MASK) -#define CCM_PRE85_EN_B_MASK 0x1000u -#define CCM_PRE85_EN_B_SHIFT 12 -#define CCM_PRE85_BUSY1_MASK 0x8000u -#define CCM_PRE85_BUSY1_SHIFT 15 -#define CCM_PRE85_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE85_PRE_PODF_A_SHIFT 16 -#define CCM_PRE85_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE85_PRE_PODF_A_SHIFT))&CCM_PRE85_PRE_PODF_A_MASK) -#define CCM_PRE85_BUSY3_MASK 0x80000u -#define CCM_PRE85_BUSY3_SHIFT 19 -#define CCM_PRE85_MUX_A_MASK 0x7000000u -#define CCM_PRE85_MUX_A_SHIFT 24 -#define CCM_PRE85_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE85_MUX_A_SHIFT))&CCM_PRE85_MUX_A_MASK) -#define CCM_PRE85_EN_A_MASK 0x10000000u -#define CCM_PRE85_EN_A_SHIFT 28 -#define CCM_PRE85_BUSY4_MASK 0x80000000u -#define CCM_PRE85_BUSY4_SHIFT 31 -/* PRE_ROOT85_SET Bit Fields */ -#define CCM_PRE_ROOT85_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT85_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT85_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT85_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT85_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT85_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT85_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT85_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT85_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_SET_MUX_B_SHIFT))&CCM_PRE_ROOT85_SET_MUX_B_MASK) -#define CCM_PRE_ROOT85_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT85_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT85_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT85_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT85_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT85_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT85_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT85_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT85_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT85_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT85_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT85_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT85_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_SET_MUX_A_SHIFT))&CCM_PRE_ROOT85_SET_MUX_A_MASK) -#define CCM_PRE_ROOT85_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT85_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT85_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT85_SET_BUSY4_SHIFT 31 -/* PRE_ROOT85_CLR Bit Fields */ -#define CCM_PRE_ROOT85_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT85_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT85_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT85_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT85_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT85_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT85_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT85_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT85_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT85_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT85_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT85_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT85_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT85_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT85_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT85_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT85_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT85_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT85_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT85_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT85_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT85_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT85_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT85_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT85_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT85_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT85_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT85_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT85_TOG Bit Fields */ -#define CCM_PRE_ROOT85_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT85_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT85_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT85_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT85_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT85_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT85_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT85_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT85_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT85_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT85_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT85_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT85_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT85_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT85_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT85_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT85_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT85_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT85_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT85_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT85_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT85_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT85_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT85_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT85_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT85_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT85_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT85_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL85 Bit Fields */ -#define CCM_ACCESS_CTRL85_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL85_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL85_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL85_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL85_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL85_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL85_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL85_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL85_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL85_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL85_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL85_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL85_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL85_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL85_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL85_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL85_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL85_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL85_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL85_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL85_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL85_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL85_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL85_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL85_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL85_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL85_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL85_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL85_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL85_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL85_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL85_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL85_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL85_LOCK_SHIFT 31 -/* ACCESS_CTRL85_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL85_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL85_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL85_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL85_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL85_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL85_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL85_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL85_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL85_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL85_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL85_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL85_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL85_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL85_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL85_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL85_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT86 Bit Fields */ -#define CCM_TARGET_ROOT86_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT86_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT86_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_POST_PODF_SHIFT))&CCM_TARGET_ROOT86_POST_PODF_MASK) -#define CCM_TARGET_ROOT86_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT86_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT86_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT86_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT86_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT86_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT86_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT86_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT86_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT86_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT86_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_PRE_PODF_SHIFT))&CCM_TARGET_ROOT86_PRE_PODF_MASK) -#define CCM_TARGET_ROOT86_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT86_MUX_SHIFT 24 -#define CCM_TARGET_ROOT86_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_MUX_SHIFT))&CCM_TARGET_ROOT86_MUX_MASK) -#define CCM_TARGET_ROOT86_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT86_ENABLE_SHIFT 28 -/* TARGET_ROOT86_SET Bit Fields */ -#define CCM_TARGET_ROOT86_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT86_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT86_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT86_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT86_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT86_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT86_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT86_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT86_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT86_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT86_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT86_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT86_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT86_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT86_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT86_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT86_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT86_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT86_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_SET_MUX_SHIFT))&CCM_TARGET_ROOT86_SET_MUX_MASK) -#define CCM_TARGET_ROOT86_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT86_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT86_CLR Bit Fields */ -#define CCM_TARGET_ROOT86_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT86_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT86_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT86_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT86_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT86_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT86_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT86_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT86_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT86_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT86_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT86_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT86_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT86_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT86_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT86_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT86_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT86_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT86_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_CLR_MUX_SHIFT))&CCM_TARGET_ROOT86_CLR_MUX_MASK) -#define CCM_TARGET_ROOT86_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT86_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT86_TOG Bit Fields */ -#define CCM_TARGET_ROOT86_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT86_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT86_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT86_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT86_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT86_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT86_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT86_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT86_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT86_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT86_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT86_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT86_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT86_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT86_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT86_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT86_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT86_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT86_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_TOG_MUX_SHIFT))&CCM_TARGET_ROOT86_TOG_MUX_MASK) -#define CCM_TARGET_ROOT86_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT86_TOG_ENABLE_SHIFT 28 -/* POST86 Bit Fields */ -#define CCM_POST86_POST_PODF_MASK 0x3Fu -#define CCM_POST86_POST_PODF_SHIFT 0 -#define CCM_POST86_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST86_POST_PODF_SHIFT))&CCM_POST86_POST_PODF_MASK) -#define CCM_POST86_BUSY1_MASK 0x80u -#define CCM_POST86_BUSY1_SHIFT 7 -#define CCM_POST86_AUTO_PODF_MASK 0x700u -#define CCM_POST86_AUTO_PODF_SHIFT 8 -#define CCM_POST86_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST86_AUTO_PODF_SHIFT))&CCM_POST86_AUTO_PODF_MASK) -#define CCM_POST86_AUTO_EN_MASK 0x1000u -#define CCM_POST86_AUTO_EN_SHIFT 12 -#define CCM_POST86_SLOW_MASK 0x8000u -#define CCM_POST86_SLOW_SHIFT 15 -#define CCM_POST86_SELECT_MASK 0x10000000u -#define CCM_POST86_SELECT_SHIFT 28 -#define CCM_POST86_BUSY2_MASK 0x80000000u -#define CCM_POST86_BUSY2_SHIFT 31 -/* POST_ROOT86_SET Bit Fields */ -#define CCM_POST_ROOT86_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT86_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT86_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_SET_POST_PODF_SHIFT))&CCM_POST_ROOT86_SET_POST_PODF_MASK) -#define CCM_POST_ROOT86_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT86_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT86_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT86_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT86_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT86_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT86_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT86_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT86_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT86_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT86_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT86_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT86_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT86_SET_BUSY2_SHIFT 31 -/* POST_ROOT86_CLR Bit Fields */ -#define CCM_POST_ROOT86_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT86_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT86_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT86_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT86_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT86_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT86_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT86_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT86_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT86_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT86_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT86_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT86_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT86_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT86_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT86_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT86_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT86_CLR_BUSY2_SHIFT 31 -/* POST_ROOT86_TOG Bit Fields */ -#define CCM_POST_ROOT86_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT86_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT86_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT86_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT86_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT86_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT86_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT86_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT86_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT86_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT86_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT86_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT86_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT86_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT86_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT86_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT86_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT86_TOG_BUSY2_SHIFT 31 -/* PRE86 Bit Fields */ -#define CCM_PRE86_PRE_PODF_B_MASK 0x7u -#define CCM_PRE86_PRE_PODF_B_SHIFT 0 -#define CCM_PRE86_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE86_PRE_PODF_B_SHIFT))&CCM_PRE86_PRE_PODF_B_MASK) -#define CCM_PRE86_BUSY0_MASK 0x8u -#define CCM_PRE86_BUSY0_SHIFT 3 -#define CCM_PRE86_MUX_B_MASK 0x700u -#define CCM_PRE86_MUX_B_SHIFT 8 -#define CCM_PRE86_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE86_MUX_B_SHIFT))&CCM_PRE86_MUX_B_MASK) -#define CCM_PRE86_EN_B_MASK 0x1000u -#define CCM_PRE86_EN_B_SHIFT 12 -#define CCM_PRE86_BUSY1_MASK 0x8000u -#define CCM_PRE86_BUSY1_SHIFT 15 -#define CCM_PRE86_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE86_PRE_PODF_A_SHIFT 16 -#define CCM_PRE86_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE86_PRE_PODF_A_SHIFT))&CCM_PRE86_PRE_PODF_A_MASK) -#define CCM_PRE86_BUSY3_MASK 0x80000u -#define CCM_PRE86_BUSY3_SHIFT 19 -#define CCM_PRE86_MUX_A_MASK 0x7000000u -#define CCM_PRE86_MUX_A_SHIFT 24 -#define CCM_PRE86_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE86_MUX_A_SHIFT))&CCM_PRE86_MUX_A_MASK) -#define CCM_PRE86_EN_A_MASK 0x10000000u -#define CCM_PRE86_EN_A_SHIFT 28 -#define CCM_PRE86_BUSY4_MASK 0x80000000u -#define CCM_PRE86_BUSY4_SHIFT 31 -/* PRE_ROOT86_SET Bit Fields */ -#define CCM_PRE_ROOT86_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT86_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT86_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT86_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT86_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT86_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT86_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT86_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT86_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_SET_MUX_B_SHIFT))&CCM_PRE_ROOT86_SET_MUX_B_MASK) -#define CCM_PRE_ROOT86_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT86_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT86_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT86_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT86_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT86_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT86_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT86_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT86_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT86_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT86_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT86_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT86_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_SET_MUX_A_SHIFT))&CCM_PRE_ROOT86_SET_MUX_A_MASK) -#define CCM_PRE_ROOT86_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT86_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT86_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT86_SET_BUSY4_SHIFT 31 -/* PRE_ROOT86_CLR Bit Fields */ -#define CCM_PRE_ROOT86_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT86_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT86_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT86_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT86_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT86_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT86_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT86_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT86_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT86_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT86_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT86_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT86_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT86_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT86_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT86_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT86_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT86_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT86_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT86_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT86_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT86_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT86_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT86_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT86_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT86_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT86_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT86_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT86_TOG Bit Fields */ -#define CCM_PRE_ROOT86_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT86_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT86_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT86_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT86_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT86_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT86_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT86_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT86_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT86_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT86_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT86_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT86_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT86_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT86_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT86_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT86_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT86_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT86_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT86_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT86_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT86_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT86_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT86_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT86_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT86_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT86_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT86_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL86 Bit Fields */ -#define CCM_ACCESS_CTRL86_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL86_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL86_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL86_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL86_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL86_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL86_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL86_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL86_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL86_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL86_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL86_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL86_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL86_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL86_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL86_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL86_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL86_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL86_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL86_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL86_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL86_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL86_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL86_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL86_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL86_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL86_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL86_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL86_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL86_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL86_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL86_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL86_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL86_LOCK_SHIFT 31 -/* ACCESS_CTRL86_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL86_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL86_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL86_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL86_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL86_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL86_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL86_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL86_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL86_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL86_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL86_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL86_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL86_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL86_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL86_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL86_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT87 Bit Fields */ -#define CCM_TARGET_ROOT87_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT87_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT87_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_POST_PODF_SHIFT))&CCM_TARGET_ROOT87_POST_PODF_MASK) -#define CCM_TARGET_ROOT87_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT87_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT87_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT87_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT87_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT87_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT87_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT87_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT87_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT87_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT87_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_PRE_PODF_SHIFT))&CCM_TARGET_ROOT87_PRE_PODF_MASK) -#define CCM_TARGET_ROOT87_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT87_MUX_SHIFT 24 -#define CCM_TARGET_ROOT87_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_MUX_SHIFT))&CCM_TARGET_ROOT87_MUX_MASK) -#define CCM_TARGET_ROOT87_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT87_ENABLE_SHIFT 28 -/* TARGET_ROOT87_SET Bit Fields */ -#define CCM_TARGET_ROOT87_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT87_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT87_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT87_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT87_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT87_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT87_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT87_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT87_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT87_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT87_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT87_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT87_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT87_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT87_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT87_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT87_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT87_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT87_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_SET_MUX_SHIFT))&CCM_TARGET_ROOT87_SET_MUX_MASK) -#define CCM_TARGET_ROOT87_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT87_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT87_CLR Bit Fields */ -#define CCM_TARGET_ROOT87_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT87_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT87_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT87_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT87_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT87_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT87_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT87_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT87_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT87_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT87_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT87_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT87_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT87_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT87_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT87_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT87_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT87_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT87_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_CLR_MUX_SHIFT))&CCM_TARGET_ROOT87_CLR_MUX_MASK) -#define CCM_TARGET_ROOT87_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT87_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT87_TOG Bit Fields */ -#define CCM_TARGET_ROOT87_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT87_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT87_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT87_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT87_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT87_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT87_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT87_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT87_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT87_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT87_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT87_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT87_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT87_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT87_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT87_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT87_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT87_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT87_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_TOG_MUX_SHIFT))&CCM_TARGET_ROOT87_TOG_MUX_MASK) -#define CCM_TARGET_ROOT87_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT87_TOG_ENABLE_SHIFT 28 -/* POST87 Bit Fields */ -#define CCM_POST87_POST_PODF_MASK 0x3Fu -#define CCM_POST87_POST_PODF_SHIFT 0 -#define CCM_POST87_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST87_POST_PODF_SHIFT))&CCM_POST87_POST_PODF_MASK) -#define CCM_POST87_BUSY1_MASK 0x80u -#define CCM_POST87_BUSY1_SHIFT 7 -#define CCM_POST87_AUTO_PODF_MASK 0x700u -#define CCM_POST87_AUTO_PODF_SHIFT 8 -#define CCM_POST87_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST87_AUTO_PODF_SHIFT))&CCM_POST87_AUTO_PODF_MASK) -#define CCM_POST87_AUTO_EN_MASK 0x1000u -#define CCM_POST87_AUTO_EN_SHIFT 12 -#define CCM_POST87_SLOW_MASK 0x8000u -#define CCM_POST87_SLOW_SHIFT 15 -#define CCM_POST87_SELECT_MASK 0x10000000u -#define CCM_POST87_SELECT_SHIFT 28 -#define CCM_POST87_BUSY2_MASK 0x80000000u -#define CCM_POST87_BUSY2_SHIFT 31 -/* POST_ROOT87_SET Bit Fields */ -#define CCM_POST_ROOT87_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT87_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT87_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_SET_POST_PODF_SHIFT))&CCM_POST_ROOT87_SET_POST_PODF_MASK) -#define CCM_POST_ROOT87_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT87_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT87_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT87_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT87_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT87_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT87_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT87_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT87_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT87_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT87_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT87_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT87_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT87_SET_BUSY2_SHIFT 31 -/* POST_ROOT87_CLR Bit Fields */ -#define CCM_POST_ROOT87_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT87_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT87_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT87_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT87_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT87_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT87_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT87_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT87_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT87_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT87_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT87_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT87_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT87_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT87_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT87_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT87_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT87_CLR_BUSY2_SHIFT 31 -/* POST_ROOT87_TOG Bit Fields */ -#define CCM_POST_ROOT87_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT87_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT87_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT87_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT87_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT87_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT87_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT87_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT87_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT87_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT87_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT87_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT87_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT87_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT87_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT87_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT87_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT87_TOG_BUSY2_SHIFT 31 -/* PRE87 Bit Fields */ -#define CCM_PRE87_PRE_PODF_B_MASK 0x7u -#define CCM_PRE87_PRE_PODF_B_SHIFT 0 -#define CCM_PRE87_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE87_PRE_PODF_B_SHIFT))&CCM_PRE87_PRE_PODF_B_MASK) -#define CCM_PRE87_BUSY0_MASK 0x8u -#define CCM_PRE87_BUSY0_SHIFT 3 -#define CCM_PRE87_MUX_B_MASK 0x700u -#define CCM_PRE87_MUX_B_SHIFT 8 -#define CCM_PRE87_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE87_MUX_B_SHIFT))&CCM_PRE87_MUX_B_MASK) -#define CCM_PRE87_EN_B_MASK 0x1000u -#define CCM_PRE87_EN_B_SHIFT 12 -#define CCM_PRE87_BUSY1_MASK 0x8000u -#define CCM_PRE87_BUSY1_SHIFT 15 -#define CCM_PRE87_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE87_PRE_PODF_A_SHIFT 16 -#define CCM_PRE87_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE87_PRE_PODF_A_SHIFT))&CCM_PRE87_PRE_PODF_A_MASK) -#define CCM_PRE87_BUSY3_MASK 0x80000u -#define CCM_PRE87_BUSY3_SHIFT 19 -#define CCM_PRE87_MUX_A_MASK 0x7000000u -#define CCM_PRE87_MUX_A_SHIFT 24 -#define CCM_PRE87_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE87_MUX_A_SHIFT))&CCM_PRE87_MUX_A_MASK) -#define CCM_PRE87_EN_A_MASK 0x10000000u -#define CCM_PRE87_EN_A_SHIFT 28 -#define CCM_PRE87_BUSY4_MASK 0x80000000u -#define CCM_PRE87_BUSY4_SHIFT 31 -/* PRE_ROOT87_SET Bit Fields */ -#define CCM_PRE_ROOT87_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT87_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT87_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT87_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT87_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT87_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT87_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT87_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT87_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_SET_MUX_B_SHIFT))&CCM_PRE_ROOT87_SET_MUX_B_MASK) -#define CCM_PRE_ROOT87_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT87_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT87_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT87_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT87_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT87_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT87_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT87_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT87_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT87_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT87_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT87_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT87_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_SET_MUX_A_SHIFT))&CCM_PRE_ROOT87_SET_MUX_A_MASK) -#define CCM_PRE_ROOT87_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT87_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT87_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT87_SET_BUSY4_SHIFT 31 -/* PRE_ROOT87_CLR Bit Fields */ -#define CCM_PRE_ROOT87_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT87_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT87_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT87_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT87_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT87_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT87_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT87_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT87_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT87_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT87_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT87_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT87_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT87_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT87_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT87_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT87_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT87_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT87_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT87_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT87_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT87_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT87_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT87_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT87_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT87_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT87_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT87_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT87_TOG Bit Fields */ -#define CCM_PRE_ROOT87_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT87_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT87_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT87_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT87_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT87_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT87_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT87_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT87_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT87_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT87_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT87_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT87_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT87_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT87_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT87_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT87_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT87_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT87_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT87_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT87_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT87_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT87_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT87_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT87_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT87_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT87_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT87_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL87 Bit Fields */ -#define CCM_ACCESS_CTRL87_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL87_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL87_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL87_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL87_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL87_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL87_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL87_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL87_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL87_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL87_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL87_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL87_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL87_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL87_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL87_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL87_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL87_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL87_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL87_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL87_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL87_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL87_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL87_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL87_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL87_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL87_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL87_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL87_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL87_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL87_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL87_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL87_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL87_LOCK_SHIFT 31 -/* ACCESS_CTRL87_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL87_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL87_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL87_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL87_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL87_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL87_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL87_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL87_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL87_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL87_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL87_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL87_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL87_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL87_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL87_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL87_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT88 Bit Fields */ -#define CCM_TARGET_ROOT88_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT88_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT88_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_POST_PODF_SHIFT))&CCM_TARGET_ROOT88_POST_PODF_MASK) -#define CCM_TARGET_ROOT88_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT88_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT88_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT88_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT88_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT88_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT88_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT88_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT88_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT88_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT88_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_PRE_PODF_SHIFT))&CCM_TARGET_ROOT88_PRE_PODF_MASK) -#define CCM_TARGET_ROOT88_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT88_MUX_SHIFT 24 -#define CCM_TARGET_ROOT88_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_MUX_SHIFT))&CCM_TARGET_ROOT88_MUX_MASK) -#define CCM_TARGET_ROOT88_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT88_ENABLE_SHIFT 28 -/* TARGET_ROOT88_SET Bit Fields */ -#define CCM_TARGET_ROOT88_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT88_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT88_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT88_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT88_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT88_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT88_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT88_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT88_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT88_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT88_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT88_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT88_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT88_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT88_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT88_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT88_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT88_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT88_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_SET_MUX_SHIFT))&CCM_TARGET_ROOT88_SET_MUX_MASK) -#define CCM_TARGET_ROOT88_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT88_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT88_CLR Bit Fields */ -#define CCM_TARGET_ROOT88_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT88_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT88_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT88_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT88_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT88_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT88_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT88_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT88_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT88_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT88_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT88_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT88_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT88_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT88_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT88_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT88_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT88_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT88_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_CLR_MUX_SHIFT))&CCM_TARGET_ROOT88_CLR_MUX_MASK) -#define CCM_TARGET_ROOT88_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT88_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT88_TOG Bit Fields */ -#define CCM_TARGET_ROOT88_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT88_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT88_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT88_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT88_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT88_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT88_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT88_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT88_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT88_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT88_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT88_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT88_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT88_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT88_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT88_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT88_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT88_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT88_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_TOG_MUX_SHIFT))&CCM_TARGET_ROOT88_TOG_MUX_MASK) -#define CCM_TARGET_ROOT88_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT88_TOG_ENABLE_SHIFT 28 -/* POST88 Bit Fields */ -#define CCM_POST88_POST_PODF_MASK 0x3Fu -#define CCM_POST88_POST_PODF_SHIFT 0 -#define CCM_POST88_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST88_POST_PODF_SHIFT))&CCM_POST88_POST_PODF_MASK) -#define CCM_POST88_BUSY1_MASK 0x80u -#define CCM_POST88_BUSY1_SHIFT 7 -#define CCM_POST88_AUTO_PODF_MASK 0x700u -#define CCM_POST88_AUTO_PODF_SHIFT 8 -#define CCM_POST88_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST88_AUTO_PODF_SHIFT))&CCM_POST88_AUTO_PODF_MASK) -#define CCM_POST88_AUTO_EN_MASK 0x1000u -#define CCM_POST88_AUTO_EN_SHIFT 12 -#define CCM_POST88_SLOW_MASK 0x8000u -#define CCM_POST88_SLOW_SHIFT 15 -#define CCM_POST88_SELECT_MASK 0x10000000u -#define CCM_POST88_SELECT_SHIFT 28 -#define CCM_POST88_BUSY2_MASK 0x80000000u -#define CCM_POST88_BUSY2_SHIFT 31 -/* POST_ROOT88_SET Bit Fields */ -#define CCM_POST_ROOT88_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT88_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT88_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_SET_POST_PODF_SHIFT))&CCM_POST_ROOT88_SET_POST_PODF_MASK) -#define CCM_POST_ROOT88_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT88_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT88_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT88_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT88_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT88_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT88_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT88_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT88_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT88_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT88_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT88_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT88_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT88_SET_BUSY2_SHIFT 31 -/* POST_ROOT88_CLR Bit Fields */ -#define CCM_POST_ROOT88_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT88_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT88_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT88_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT88_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT88_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT88_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT88_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT88_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT88_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT88_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT88_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT88_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT88_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT88_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT88_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT88_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT88_CLR_BUSY2_SHIFT 31 -/* POST_ROOT88_TOG Bit Fields */ -#define CCM_POST_ROOT88_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT88_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT88_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT88_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT88_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT88_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT88_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT88_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT88_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT88_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT88_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT88_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT88_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT88_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT88_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT88_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT88_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT88_TOG_BUSY2_SHIFT 31 -/* PRE88 Bit Fields */ -#define CCM_PRE88_PRE_PODF_B_MASK 0x7u -#define CCM_PRE88_PRE_PODF_B_SHIFT 0 -#define CCM_PRE88_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE88_PRE_PODF_B_SHIFT))&CCM_PRE88_PRE_PODF_B_MASK) -#define CCM_PRE88_BUSY0_MASK 0x8u -#define CCM_PRE88_BUSY0_SHIFT 3 -#define CCM_PRE88_MUX_B_MASK 0x700u -#define CCM_PRE88_MUX_B_SHIFT 8 -#define CCM_PRE88_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE88_MUX_B_SHIFT))&CCM_PRE88_MUX_B_MASK) -#define CCM_PRE88_EN_B_MASK 0x1000u -#define CCM_PRE88_EN_B_SHIFT 12 -#define CCM_PRE88_BUSY1_MASK 0x8000u -#define CCM_PRE88_BUSY1_SHIFT 15 -#define CCM_PRE88_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE88_PRE_PODF_A_SHIFT 16 -#define CCM_PRE88_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE88_PRE_PODF_A_SHIFT))&CCM_PRE88_PRE_PODF_A_MASK) -#define CCM_PRE88_BUSY3_MASK 0x80000u -#define CCM_PRE88_BUSY3_SHIFT 19 -#define CCM_PRE88_MUX_A_MASK 0x7000000u -#define CCM_PRE88_MUX_A_SHIFT 24 -#define CCM_PRE88_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE88_MUX_A_SHIFT))&CCM_PRE88_MUX_A_MASK) -#define CCM_PRE88_EN_A_MASK 0x10000000u -#define CCM_PRE88_EN_A_SHIFT 28 -#define CCM_PRE88_BUSY4_MASK 0x80000000u -#define CCM_PRE88_BUSY4_SHIFT 31 -/* PRE_ROOT88_SET Bit Fields */ -#define CCM_PRE_ROOT88_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT88_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT88_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT88_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT88_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT88_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT88_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT88_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT88_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_SET_MUX_B_SHIFT))&CCM_PRE_ROOT88_SET_MUX_B_MASK) -#define CCM_PRE_ROOT88_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT88_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT88_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT88_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT88_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT88_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT88_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT88_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT88_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT88_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT88_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT88_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT88_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_SET_MUX_A_SHIFT))&CCM_PRE_ROOT88_SET_MUX_A_MASK) -#define CCM_PRE_ROOT88_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT88_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT88_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT88_SET_BUSY4_SHIFT 31 -/* PRE_ROOT88_CLR Bit Fields */ -#define CCM_PRE_ROOT88_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT88_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT88_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT88_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT88_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT88_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT88_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT88_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT88_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT88_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT88_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT88_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT88_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT88_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT88_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT88_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT88_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT88_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT88_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT88_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT88_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT88_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT88_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT88_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT88_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT88_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT88_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT88_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT88_TOG Bit Fields */ -#define CCM_PRE_ROOT88_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT88_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT88_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT88_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT88_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT88_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT88_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT88_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT88_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT88_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT88_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT88_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT88_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT88_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT88_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT88_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT88_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT88_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT88_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT88_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT88_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT88_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT88_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT88_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT88_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT88_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT88_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT88_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL88 Bit Fields */ -#define CCM_ACCESS_CTRL88_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL88_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL88_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL88_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL88_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL88_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL88_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL88_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL88_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL88_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL88_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL88_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL88_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL88_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL88_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL88_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL88_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL88_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL88_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL88_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL88_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL88_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL88_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL88_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL88_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL88_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL88_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL88_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL88_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL88_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL88_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL88_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL88_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL88_LOCK_SHIFT 31 -/* ACCESS_CTRL88_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL88_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL88_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL88_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL88_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL88_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL88_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL88_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL88_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL88_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL88_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL88_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL88_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL88_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL88_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL88_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL88_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT89 Bit Fields */ -#define CCM_TARGET_ROOT89_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT89_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT89_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_POST_PODF_SHIFT))&CCM_TARGET_ROOT89_POST_PODF_MASK) -#define CCM_TARGET_ROOT89_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT89_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT89_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT89_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT89_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT89_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT89_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT89_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT89_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT89_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT89_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_PRE_PODF_SHIFT))&CCM_TARGET_ROOT89_PRE_PODF_MASK) -#define CCM_TARGET_ROOT89_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT89_MUX_SHIFT 24 -#define CCM_TARGET_ROOT89_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_MUX_SHIFT))&CCM_TARGET_ROOT89_MUX_MASK) -#define CCM_TARGET_ROOT89_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT89_ENABLE_SHIFT 28 -/* TARGET_ROOT89_SET Bit Fields */ -#define CCM_TARGET_ROOT89_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT89_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT89_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT89_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT89_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT89_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT89_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT89_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT89_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT89_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT89_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT89_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT89_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT89_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT89_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT89_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT89_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT89_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT89_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_SET_MUX_SHIFT))&CCM_TARGET_ROOT89_SET_MUX_MASK) -#define CCM_TARGET_ROOT89_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT89_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT89_CLR Bit Fields */ -#define CCM_TARGET_ROOT89_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT89_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT89_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT89_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT89_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT89_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT89_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT89_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT89_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT89_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT89_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT89_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT89_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT89_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT89_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT89_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT89_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT89_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT89_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_CLR_MUX_SHIFT))&CCM_TARGET_ROOT89_CLR_MUX_MASK) -#define CCM_TARGET_ROOT89_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT89_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT89_TOG Bit Fields */ -#define CCM_TARGET_ROOT89_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT89_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT89_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT89_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT89_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT89_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT89_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT89_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT89_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT89_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT89_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT89_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT89_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT89_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT89_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT89_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT89_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT89_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT89_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_TOG_MUX_SHIFT))&CCM_TARGET_ROOT89_TOG_MUX_MASK) -#define CCM_TARGET_ROOT89_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT89_TOG_ENABLE_SHIFT 28 -/* POST89 Bit Fields */ -#define CCM_POST89_POST_PODF_MASK 0x3Fu -#define CCM_POST89_POST_PODF_SHIFT 0 -#define CCM_POST89_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST89_POST_PODF_SHIFT))&CCM_POST89_POST_PODF_MASK) -#define CCM_POST89_BUSY1_MASK 0x80u -#define CCM_POST89_BUSY1_SHIFT 7 -#define CCM_POST89_AUTO_PODF_MASK 0x700u -#define CCM_POST89_AUTO_PODF_SHIFT 8 -#define CCM_POST89_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST89_AUTO_PODF_SHIFT))&CCM_POST89_AUTO_PODF_MASK) -#define CCM_POST89_AUTO_EN_MASK 0x1000u -#define CCM_POST89_AUTO_EN_SHIFT 12 -#define CCM_POST89_SLOW_MASK 0x8000u -#define CCM_POST89_SLOW_SHIFT 15 -#define CCM_POST89_SELECT_MASK 0x10000000u -#define CCM_POST89_SELECT_SHIFT 28 -#define CCM_POST89_BUSY2_MASK 0x80000000u -#define CCM_POST89_BUSY2_SHIFT 31 -/* POST_ROOT89_SET Bit Fields */ -#define CCM_POST_ROOT89_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT89_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT89_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_SET_POST_PODF_SHIFT))&CCM_POST_ROOT89_SET_POST_PODF_MASK) -#define CCM_POST_ROOT89_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT89_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT89_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT89_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT89_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT89_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT89_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT89_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT89_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT89_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT89_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT89_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT89_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT89_SET_BUSY2_SHIFT 31 -/* POST_ROOT89_CLR Bit Fields */ -#define CCM_POST_ROOT89_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT89_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT89_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT89_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT89_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT89_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT89_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT89_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT89_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT89_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT89_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT89_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT89_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT89_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT89_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT89_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT89_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT89_CLR_BUSY2_SHIFT 31 -/* POST_ROOT89_TOG Bit Fields */ -#define CCM_POST_ROOT89_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT89_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT89_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT89_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT89_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT89_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT89_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT89_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT89_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT89_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT89_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT89_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT89_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT89_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT89_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT89_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT89_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT89_TOG_BUSY2_SHIFT 31 -/* PRE89 Bit Fields */ -#define CCM_PRE89_PRE_PODF_B_MASK 0x7u -#define CCM_PRE89_PRE_PODF_B_SHIFT 0 -#define CCM_PRE89_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE89_PRE_PODF_B_SHIFT))&CCM_PRE89_PRE_PODF_B_MASK) -#define CCM_PRE89_BUSY0_MASK 0x8u -#define CCM_PRE89_BUSY0_SHIFT 3 -#define CCM_PRE89_MUX_B_MASK 0x700u -#define CCM_PRE89_MUX_B_SHIFT 8 -#define CCM_PRE89_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE89_MUX_B_SHIFT))&CCM_PRE89_MUX_B_MASK) -#define CCM_PRE89_EN_B_MASK 0x1000u -#define CCM_PRE89_EN_B_SHIFT 12 -#define CCM_PRE89_BUSY1_MASK 0x8000u -#define CCM_PRE89_BUSY1_SHIFT 15 -#define CCM_PRE89_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE89_PRE_PODF_A_SHIFT 16 -#define CCM_PRE89_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE89_PRE_PODF_A_SHIFT))&CCM_PRE89_PRE_PODF_A_MASK) -#define CCM_PRE89_BUSY3_MASK 0x80000u -#define CCM_PRE89_BUSY3_SHIFT 19 -#define CCM_PRE89_MUX_A_MASK 0x7000000u -#define CCM_PRE89_MUX_A_SHIFT 24 -#define CCM_PRE89_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE89_MUX_A_SHIFT))&CCM_PRE89_MUX_A_MASK) -#define CCM_PRE89_EN_A_MASK 0x10000000u -#define CCM_PRE89_EN_A_SHIFT 28 -#define CCM_PRE89_BUSY4_MASK 0x80000000u -#define CCM_PRE89_BUSY4_SHIFT 31 -/* PRE_ROOT89_SET Bit Fields */ -#define CCM_PRE_ROOT89_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT89_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT89_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT89_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT89_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT89_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT89_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT89_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT89_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_SET_MUX_B_SHIFT))&CCM_PRE_ROOT89_SET_MUX_B_MASK) -#define CCM_PRE_ROOT89_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT89_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT89_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT89_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT89_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT89_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT89_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT89_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT89_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT89_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT89_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT89_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT89_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_SET_MUX_A_SHIFT))&CCM_PRE_ROOT89_SET_MUX_A_MASK) -#define CCM_PRE_ROOT89_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT89_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT89_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT89_SET_BUSY4_SHIFT 31 -/* PRE_ROOT89_CLR Bit Fields */ -#define CCM_PRE_ROOT89_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT89_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT89_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT89_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT89_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT89_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT89_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT89_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT89_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT89_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT89_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT89_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT89_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT89_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT89_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT89_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT89_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT89_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT89_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT89_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT89_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT89_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT89_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT89_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT89_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT89_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT89_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT89_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT89_TOG Bit Fields */ -#define CCM_PRE_ROOT89_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT89_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT89_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT89_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT89_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT89_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT89_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT89_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT89_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT89_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT89_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT89_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT89_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT89_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT89_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT89_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT89_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT89_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT89_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT89_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT89_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT89_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT89_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT89_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT89_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT89_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT89_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT89_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL89 Bit Fields */ -#define CCM_ACCESS_CTRL89_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL89_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL89_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL89_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL89_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL89_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL89_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL89_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL89_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL89_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL89_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL89_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL89_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL89_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL89_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL89_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL89_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL89_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL89_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL89_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL89_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL89_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL89_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL89_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL89_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL89_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL89_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL89_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL89_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL89_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL89_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL89_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL89_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL89_LOCK_SHIFT 31 -/* ACCESS_CTRL89_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL89_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL89_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL89_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL89_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL89_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL89_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL89_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL89_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL89_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL89_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL89_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL89_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL89_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL89_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL89_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL89_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT90 Bit Fields */ -#define CCM_TARGET_ROOT90_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT90_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT90_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_POST_PODF_SHIFT))&CCM_TARGET_ROOT90_POST_PODF_MASK) -#define CCM_TARGET_ROOT90_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT90_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT90_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT90_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT90_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT90_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT90_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT90_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT90_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT90_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT90_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_PRE_PODF_SHIFT))&CCM_TARGET_ROOT90_PRE_PODF_MASK) -#define CCM_TARGET_ROOT90_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT90_MUX_SHIFT 24 -#define CCM_TARGET_ROOT90_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_MUX_SHIFT))&CCM_TARGET_ROOT90_MUX_MASK) -#define CCM_TARGET_ROOT90_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT90_ENABLE_SHIFT 28 -/* TARGET_ROOT90_SET Bit Fields */ -#define CCM_TARGET_ROOT90_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT90_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT90_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT90_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT90_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT90_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT90_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT90_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT90_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT90_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT90_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT90_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT90_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT90_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT90_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT90_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT90_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT90_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT90_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_SET_MUX_SHIFT))&CCM_TARGET_ROOT90_SET_MUX_MASK) -#define CCM_TARGET_ROOT90_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT90_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT90_CLR Bit Fields */ -#define CCM_TARGET_ROOT90_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT90_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT90_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT90_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT90_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT90_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT90_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT90_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT90_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT90_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT90_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT90_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT90_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT90_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT90_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT90_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT90_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT90_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT90_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_CLR_MUX_SHIFT))&CCM_TARGET_ROOT90_CLR_MUX_MASK) -#define CCM_TARGET_ROOT90_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT90_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT90_TOG Bit Fields */ -#define CCM_TARGET_ROOT90_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT90_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT90_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT90_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT90_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT90_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT90_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT90_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT90_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT90_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT90_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT90_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT90_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT90_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT90_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT90_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT90_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT90_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT90_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_TOG_MUX_SHIFT))&CCM_TARGET_ROOT90_TOG_MUX_MASK) -#define CCM_TARGET_ROOT90_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT90_TOG_ENABLE_SHIFT 28 -/* POST90 Bit Fields */ -#define CCM_POST90_POST_PODF_MASK 0x3Fu -#define CCM_POST90_POST_PODF_SHIFT 0 -#define CCM_POST90_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST90_POST_PODF_SHIFT))&CCM_POST90_POST_PODF_MASK) -#define CCM_POST90_BUSY1_MASK 0x80u -#define CCM_POST90_BUSY1_SHIFT 7 -#define CCM_POST90_AUTO_PODF_MASK 0x700u -#define CCM_POST90_AUTO_PODF_SHIFT 8 -#define CCM_POST90_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST90_AUTO_PODF_SHIFT))&CCM_POST90_AUTO_PODF_MASK) -#define CCM_POST90_AUTO_EN_MASK 0x1000u -#define CCM_POST90_AUTO_EN_SHIFT 12 -#define CCM_POST90_SLOW_MASK 0x8000u -#define CCM_POST90_SLOW_SHIFT 15 -#define CCM_POST90_SELECT_MASK 0x10000000u -#define CCM_POST90_SELECT_SHIFT 28 -#define CCM_POST90_BUSY2_MASK 0x80000000u -#define CCM_POST90_BUSY2_SHIFT 31 -/* POST_ROOT90_SET Bit Fields */ -#define CCM_POST_ROOT90_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT90_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT90_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_SET_POST_PODF_SHIFT))&CCM_POST_ROOT90_SET_POST_PODF_MASK) -#define CCM_POST_ROOT90_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT90_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT90_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT90_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT90_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT90_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT90_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT90_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT90_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT90_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT90_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT90_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT90_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT90_SET_BUSY2_SHIFT 31 -/* POST_ROOT90_CLR Bit Fields */ -#define CCM_POST_ROOT90_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT90_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT90_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT90_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT90_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT90_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT90_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT90_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT90_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT90_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT90_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT90_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT90_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT90_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT90_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT90_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT90_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT90_CLR_BUSY2_SHIFT 31 -/* POST_ROOT90_TOG Bit Fields */ -#define CCM_POST_ROOT90_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT90_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT90_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT90_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT90_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT90_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT90_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT90_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT90_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT90_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT90_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT90_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT90_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT90_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT90_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT90_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT90_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT90_TOG_BUSY2_SHIFT 31 -/* PRE90 Bit Fields */ -#define CCM_PRE90_PRE_PODF_B_MASK 0x7u -#define CCM_PRE90_PRE_PODF_B_SHIFT 0 -#define CCM_PRE90_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE90_PRE_PODF_B_SHIFT))&CCM_PRE90_PRE_PODF_B_MASK) -#define CCM_PRE90_BUSY0_MASK 0x8u -#define CCM_PRE90_BUSY0_SHIFT 3 -#define CCM_PRE90_MUX_B_MASK 0x700u -#define CCM_PRE90_MUX_B_SHIFT 8 -#define CCM_PRE90_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE90_MUX_B_SHIFT))&CCM_PRE90_MUX_B_MASK) -#define CCM_PRE90_EN_B_MASK 0x1000u -#define CCM_PRE90_EN_B_SHIFT 12 -#define CCM_PRE90_BUSY1_MASK 0x8000u -#define CCM_PRE90_BUSY1_SHIFT 15 -#define CCM_PRE90_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE90_PRE_PODF_A_SHIFT 16 -#define CCM_PRE90_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE90_PRE_PODF_A_SHIFT))&CCM_PRE90_PRE_PODF_A_MASK) -#define CCM_PRE90_BUSY3_MASK 0x80000u -#define CCM_PRE90_BUSY3_SHIFT 19 -#define CCM_PRE90_MUX_A_MASK 0x7000000u -#define CCM_PRE90_MUX_A_SHIFT 24 -#define CCM_PRE90_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE90_MUX_A_SHIFT))&CCM_PRE90_MUX_A_MASK) -#define CCM_PRE90_EN_A_MASK 0x10000000u -#define CCM_PRE90_EN_A_SHIFT 28 -#define CCM_PRE90_BUSY4_MASK 0x80000000u -#define CCM_PRE90_BUSY4_SHIFT 31 -/* PRE_ROOT90_SET Bit Fields */ -#define CCM_PRE_ROOT90_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT90_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT90_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT90_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT90_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT90_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT90_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT90_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT90_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_SET_MUX_B_SHIFT))&CCM_PRE_ROOT90_SET_MUX_B_MASK) -#define CCM_PRE_ROOT90_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT90_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT90_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT90_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT90_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT90_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT90_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT90_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT90_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT90_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT90_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT90_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT90_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_SET_MUX_A_SHIFT))&CCM_PRE_ROOT90_SET_MUX_A_MASK) -#define CCM_PRE_ROOT90_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT90_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT90_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT90_SET_BUSY4_SHIFT 31 -/* PRE_ROOT90_CLR Bit Fields */ -#define CCM_PRE_ROOT90_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT90_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT90_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT90_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT90_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT90_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT90_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT90_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT90_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT90_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT90_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT90_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT90_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT90_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT90_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT90_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT90_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT90_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT90_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT90_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT90_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT90_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT90_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT90_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT90_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT90_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT90_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT90_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT90_TOG Bit Fields */ -#define CCM_PRE_ROOT90_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT90_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT90_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT90_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT90_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT90_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT90_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT90_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT90_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT90_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT90_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT90_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT90_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT90_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT90_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT90_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT90_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT90_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT90_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT90_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT90_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT90_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT90_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT90_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT90_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT90_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT90_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT90_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL90 Bit Fields */ -#define CCM_ACCESS_CTRL90_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL90_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL90_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL90_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL90_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL90_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL90_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL90_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL90_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL90_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL90_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL90_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL90_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL90_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL90_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL90_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL90_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL90_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL90_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL90_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL90_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL90_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL90_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL90_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL90_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL90_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL90_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL90_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL90_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL90_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL90_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL90_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL90_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL90_LOCK_SHIFT 31 -/* ACCESS_CTRL90_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL90_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL90_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL90_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL90_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL90_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL90_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL90_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL90_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL90_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL90_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL90_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL90_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL90_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL90_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL90_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL90_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT91 Bit Fields */ -#define CCM_TARGET_ROOT91_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT91_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT91_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_POST_PODF_SHIFT))&CCM_TARGET_ROOT91_POST_PODF_MASK) -#define CCM_TARGET_ROOT91_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT91_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT91_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT91_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT91_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT91_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT91_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT91_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT91_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT91_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT91_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_PRE_PODF_SHIFT))&CCM_TARGET_ROOT91_PRE_PODF_MASK) -#define CCM_TARGET_ROOT91_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT91_MUX_SHIFT 24 -#define CCM_TARGET_ROOT91_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_MUX_SHIFT))&CCM_TARGET_ROOT91_MUX_MASK) -#define CCM_TARGET_ROOT91_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT91_ENABLE_SHIFT 28 -/* TARGET_ROOT91_SET Bit Fields */ -#define CCM_TARGET_ROOT91_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT91_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT91_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT91_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT91_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT91_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT91_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT91_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT91_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT91_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT91_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT91_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT91_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT91_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT91_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT91_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT91_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT91_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT91_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_SET_MUX_SHIFT))&CCM_TARGET_ROOT91_SET_MUX_MASK) -#define CCM_TARGET_ROOT91_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT91_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT91_CLR Bit Fields */ -#define CCM_TARGET_ROOT91_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT91_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT91_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT91_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT91_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT91_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT91_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT91_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT91_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT91_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT91_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT91_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT91_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT91_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT91_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT91_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT91_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT91_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT91_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_CLR_MUX_SHIFT))&CCM_TARGET_ROOT91_CLR_MUX_MASK) -#define CCM_TARGET_ROOT91_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT91_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT91_TOG Bit Fields */ -#define CCM_TARGET_ROOT91_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT91_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT91_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT91_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT91_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT91_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT91_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT91_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT91_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT91_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT91_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT91_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT91_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT91_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT91_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT91_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT91_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT91_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT91_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_TOG_MUX_SHIFT))&CCM_TARGET_ROOT91_TOG_MUX_MASK) -#define CCM_TARGET_ROOT91_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT91_TOG_ENABLE_SHIFT 28 -/* POST91 Bit Fields */ -#define CCM_POST91_POST_PODF_MASK 0x3Fu -#define CCM_POST91_POST_PODF_SHIFT 0 -#define CCM_POST91_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST91_POST_PODF_SHIFT))&CCM_POST91_POST_PODF_MASK) -#define CCM_POST91_BUSY1_MASK 0x80u -#define CCM_POST91_BUSY1_SHIFT 7 -#define CCM_POST91_AUTO_PODF_MASK 0x700u -#define CCM_POST91_AUTO_PODF_SHIFT 8 -#define CCM_POST91_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST91_AUTO_PODF_SHIFT))&CCM_POST91_AUTO_PODF_MASK) -#define CCM_POST91_AUTO_EN_MASK 0x1000u -#define CCM_POST91_AUTO_EN_SHIFT 12 -#define CCM_POST91_SLOW_MASK 0x8000u -#define CCM_POST91_SLOW_SHIFT 15 -#define CCM_POST91_SELECT_MASK 0x10000000u -#define CCM_POST91_SELECT_SHIFT 28 -#define CCM_POST91_BUSY2_MASK 0x80000000u -#define CCM_POST91_BUSY2_SHIFT 31 -/* POST_ROOT91_SET Bit Fields */ -#define CCM_POST_ROOT91_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT91_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT91_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_SET_POST_PODF_SHIFT))&CCM_POST_ROOT91_SET_POST_PODF_MASK) -#define CCM_POST_ROOT91_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT91_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT91_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT91_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT91_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT91_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT91_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT91_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT91_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT91_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT91_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT91_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT91_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT91_SET_BUSY2_SHIFT 31 -/* POST_ROOT91_CLR Bit Fields */ -#define CCM_POST_ROOT91_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT91_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT91_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT91_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT91_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT91_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT91_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT91_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT91_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT91_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT91_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT91_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT91_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT91_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT91_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT91_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT91_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT91_CLR_BUSY2_SHIFT 31 -/* POST_ROOT91_TOG Bit Fields */ -#define CCM_POST_ROOT91_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT91_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT91_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT91_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT91_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT91_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT91_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT91_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT91_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT91_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT91_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT91_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT91_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT91_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT91_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT91_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT91_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT91_TOG_BUSY2_SHIFT 31 -/* PRE91 Bit Fields */ -#define CCM_PRE91_PRE_PODF_B_MASK 0x7u -#define CCM_PRE91_PRE_PODF_B_SHIFT 0 -#define CCM_PRE91_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE91_PRE_PODF_B_SHIFT))&CCM_PRE91_PRE_PODF_B_MASK) -#define CCM_PRE91_BUSY0_MASK 0x8u -#define CCM_PRE91_BUSY0_SHIFT 3 -#define CCM_PRE91_MUX_B_MASK 0x700u -#define CCM_PRE91_MUX_B_SHIFT 8 -#define CCM_PRE91_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE91_MUX_B_SHIFT))&CCM_PRE91_MUX_B_MASK) -#define CCM_PRE91_EN_B_MASK 0x1000u -#define CCM_PRE91_EN_B_SHIFT 12 -#define CCM_PRE91_BUSY1_MASK 0x8000u -#define CCM_PRE91_BUSY1_SHIFT 15 -#define CCM_PRE91_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE91_PRE_PODF_A_SHIFT 16 -#define CCM_PRE91_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE91_PRE_PODF_A_SHIFT))&CCM_PRE91_PRE_PODF_A_MASK) -#define CCM_PRE91_BUSY3_MASK 0x80000u -#define CCM_PRE91_BUSY3_SHIFT 19 -#define CCM_PRE91_MUX_A_MASK 0x7000000u -#define CCM_PRE91_MUX_A_SHIFT 24 -#define CCM_PRE91_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE91_MUX_A_SHIFT))&CCM_PRE91_MUX_A_MASK) -#define CCM_PRE91_EN_A_MASK 0x10000000u -#define CCM_PRE91_EN_A_SHIFT 28 -#define CCM_PRE91_BUSY4_MASK 0x80000000u -#define CCM_PRE91_BUSY4_SHIFT 31 -/* PRE_ROOT91_SET Bit Fields */ -#define CCM_PRE_ROOT91_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT91_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT91_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT91_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT91_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT91_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT91_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT91_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT91_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_SET_MUX_B_SHIFT))&CCM_PRE_ROOT91_SET_MUX_B_MASK) -#define CCM_PRE_ROOT91_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT91_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT91_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT91_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT91_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT91_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT91_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT91_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT91_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT91_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT91_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT91_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT91_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_SET_MUX_A_SHIFT))&CCM_PRE_ROOT91_SET_MUX_A_MASK) -#define CCM_PRE_ROOT91_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT91_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT91_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT91_SET_BUSY4_SHIFT 31 -/* PRE_ROOT91_CLR Bit Fields */ -#define CCM_PRE_ROOT91_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT91_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT91_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT91_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT91_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT91_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT91_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT91_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT91_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT91_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT91_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT91_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT91_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT91_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT91_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT91_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT91_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT91_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT91_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT91_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT91_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT91_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT91_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT91_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT91_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT91_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT91_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT91_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT91_TOG Bit Fields */ -#define CCM_PRE_ROOT91_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT91_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT91_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT91_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT91_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT91_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT91_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT91_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT91_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT91_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT91_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT91_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT91_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT91_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT91_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT91_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT91_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT91_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT91_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT91_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT91_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT91_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT91_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT91_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT91_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT91_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT91_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT91_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL91 Bit Fields */ -#define CCM_ACCESS_CTRL91_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL91_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL91_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL91_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL91_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL91_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL91_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL91_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL91_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL91_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL91_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL91_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL91_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL91_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL91_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL91_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL91_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL91_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL91_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL91_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL91_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL91_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL91_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL91_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL91_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL91_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL91_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL91_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL91_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL91_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL91_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL91_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL91_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL91_LOCK_SHIFT 31 -/* ACCESS_CTRL91_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL91_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL91_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL91_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL91_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL91_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL91_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL91_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL91_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL91_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL91_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL91_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL91_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL91_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL91_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL91_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL91_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT92 Bit Fields */ -#define CCM_TARGET_ROOT92_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT92_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT92_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_POST_PODF_SHIFT))&CCM_TARGET_ROOT92_POST_PODF_MASK) -#define CCM_TARGET_ROOT92_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT92_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT92_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT92_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT92_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT92_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT92_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT92_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT92_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT92_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT92_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_PRE_PODF_SHIFT))&CCM_TARGET_ROOT92_PRE_PODF_MASK) -#define CCM_TARGET_ROOT92_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT92_MUX_SHIFT 24 -#define CCM_TARGET_ROOT92_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_MUX_SHIFT))&CCM_TARGET_ROOT92_MUX_MASK) -#define CCM_TARGET_ROOT92_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT92_ENABLE_SHIFT 28 -/* TARGET_ROOT92_SET Bit Fields */ -#define CCM_TARGET_ROOT92_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT92_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT92_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT92_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT92_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT92_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT92_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT92_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT92_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT92_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT92_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT92_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT92_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT92_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT92_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT92_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT92_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT92_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT92_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_SET_MUX_SHIFT))&CCM_TARGET_ROOT92_SET_MUX_MASK) -#define CCM_TARGET_ROOT92_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT92_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT92_CLR Bit Fields */ -#define CCM_TARGET_ROOT92_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT92_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT92_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT92_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT92_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT92_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT92_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT92_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT92_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT92_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT92_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT92_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT92_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT92_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT92_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT92_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT92_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT92_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT92_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_CLR_MUX_SHIFT))&CCM_TARGET_ROOT92_CLR_MUX_MASK) -#define CCM_TARGET_ROOT92_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT92_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT92_TOG Bit Fields */ -#define CCM_TARGET_ROOT92_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT92_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT92_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT92_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT92_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT92_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT92_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT92_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT92_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT92_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT92_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT92_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT92_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT92_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT92_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT92_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT92_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT92_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT92_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_TOG_MUX_SHIFT))&CCM_TARGET_ROOT92_TOG_MUX_MASK) -#define CCM_TARGET_ROOT92_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT92_TOG_ENABLE_SHIFT 28 -/* POST92 Bit Fields */ -#define CCM_POST92_POST_PODF_MASK 0x3Fu -#define CCM_POST92_POST_PODF_SHIFT 0 -#define CCM_POST92_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST92_POST_PODF_SHIFT))&CCM_POST92_POST_PODF_MASK) -#define CCM_POST92_BUSY1_MASK 0x80u -#define CCM_POST92_BUSY1_SHIFT 7 -#define CCM_POST92_AUTO_PODF_MASK 0x700u -#define CCM_POST92_AUTO_PODF_SHIFT 8 -#define CCM_POST92_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST92_AUTO_PODF_SHIFT))&CCM_POST92_AUTO_PODF_MASK) -#define CCM_POST92_AUTO_EN_MASK 0x1000u -#define CCM_POST92_AUTO_EN_SHIFT 12 -#define CCM_POST92_SLOW_MASK 0x8000u -#define CCM_POST92_SLOW_SHIFT 15 -#define CCM_POST92_SELECT_MASK 0x10000000u -#define CCM_POST92_SELECT_SHIFT 28 -#define CCM_POST92_BUSY2_MASK 0x80000000u -#define CCM_POST92_BUSY2_SHIFT 31 -/* POST_ROOT92_SET Bit Fields */ -#define CCM_POST_ROOT92_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT92_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT92_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_SET_POST_PODF_SHIFT))&CCM_POST_ROOT92_SET_POST_PODF_MASK) -#define CCM_POST_ROOT92_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT92_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT92_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT92_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT92_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT92_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT92_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT92_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT92_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT92_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT92_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT92_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT92_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT92_SET_BUSY2_SHIFT 31 -/* POST_ROOT92_CLR Bit Fields */ -#define CCM_POST_ROOT92_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT92_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT92_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT92_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT92_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT92_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT92_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT92_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT92_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT92_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT92_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT92_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT92_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT92_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT92_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT92_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT92_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT92_CLR_BUSY2_SHIFT 31 -/* POST_ROOT92_TOG Bit Fields */ -#define CCM_POST_ROOT92_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT92_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT92_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT92_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT92_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT92_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT92_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT92_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT92_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT92_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT92_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT92_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT92_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT92_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT92_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT92_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT92_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT92_TOG_BUSY2_SHIFT 31 -/* PRE92 Bit Fields */ -#define CCM_PRE92_PRE_PODF_B_MASK 0x7u -#define CCM_PRE92_PRE_PODF_B_SHIFT 0 -#define CCM_PRE92_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE92_PRE_PODF_B_SHIFT))&CCM_PRE92_PRE_PODF_B_MASK) -#define CCM_PRE92_BUSY0_MASK 0x8u -#define CCM_PRE92_BUSY0_SHIFT 3 -#define CCM_PRE92_MUX_B_MASK 0x700u -#define CCM_PRE92_MUX_B_SHIFT 8 -#define CCM_PRE92_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE92_MUX_B_SHIFT))&CCM_PRE92_MUX_B_MASK) -#define CCM_PRE92_EN_B_MASK 0x1000u -#define CCM_PRE92_EN_B_SHIFT 12 -#define CCM_PRE92_BUSY1_MASK 0x8000u -#define CCM_PRE92_BUSY1_SHIFT 15 -#define CCM_PRE92_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE92_PRE_PODF_A_SHIFT 16 -#define CCM_PRE92_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE92_PRE_PODF_A_SHIFT))&CCM_PRE92_PRE_PODF_A_MASK) -#define CCM_PRE92_BUSY3_MASK 0x80000u -#define CCM_PRE92_BUSY3_SHIFT 19 -#define CCM_PRE92_MUX_A_MASK 0x7000000u -#define CCM_PRE92_MUX_A_SHIFT 24 -#define CCM_PRE92_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE92_MUX_A_SHIFT))&CCM_PRE92_MUX_A_MASK) -#define CCM_PRE92_EN_A_MASK 0x10000000u -#define CCM_PRE92_EN_A_SHIFT 28 -#define CCM_PRE92_BUSY4_MASK 0x80000000u -#define CCM_PRE92_BUSY4_SHIFT 31 -/* PRE_ROOT92_SET Bit Fields */ -#define CCM_PRE_ROOT92_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT92_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT92_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT92_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT92_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT92_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT92_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT92_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT92_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_SET_MUX_B_SHIFT))&CCM_PRE_ROOT92_SET_MUX_B_MASK) -#define CCM_PRE_ROOT92_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT92_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT92_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT92_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT92_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT92_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT92_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT92_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT92_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT92_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT92_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT92_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT92_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_SET_MUX_A_SHIFT))&CCM_PRE_ROOT92_SET_MUX_A_MASK) -#define CCM_PRE_ROOT92_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT92_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT92_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT92_SET_BUSY4_SHIFT 31 -/* PRE_ROOT92_CLR Bit Fields */ -#define CCM_PRE_ROOT92_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT92_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT92_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT92_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT92_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT92_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT92_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT92_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT92_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT92_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT92_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT92_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT92_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT92_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT92_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT92_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT92_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT92_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT92_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT92_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT92_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT92_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT92_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT92_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT92_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT92_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT92_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT92_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT92_TOG Bit Fields */ -#define CCM_PRE_ROOT92_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT92_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT92_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT92_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT92_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT92_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT92_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT92_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT92_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT92_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT92_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT92_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT92_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT92_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT92_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT92_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT92_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT92_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT92_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT92_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT92_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT92_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT92_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT92_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT92_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT92_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT92_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT92_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL92 Bit Fields */ -#define CCM_ACCESS_CTRL92_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL92_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL92_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL92_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL92_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL92_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL92_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL92_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL92_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL92_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL92_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL92_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL92_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL92_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL92_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL92_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL92_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL92_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL92_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL92_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL92_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL92_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL92_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL92_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL92_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL92_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL92_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL92_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL92_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL92_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL92_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL92_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL92_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL92_LOCK_SHIFT 31 -/* ACCESS_CTRL92_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL92_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL92_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL92_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL92_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL92_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL92_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL92_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL92_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL92_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL92_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL92_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL92_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL92_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL92_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL92_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL92_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT93 Bit Fields */ -#define CCM_TARGET_ROOT93_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT93_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT93_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_POST_PODF_SHIFT))&CCM_TARGET_ROOT93_POST_PODF_MASK) -#define CCM_TARGET_ROOT93_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT93_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT93_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT93_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT93_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT93_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT93_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT93_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT93_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT93_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT93_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_PRE_PODF_SHIFT))&CCM_TARGET_ROOT93_PRE_PODF_MASK) -#define CCM_TARGET_ROOT93_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT93_MUX_SHIFT 24 -#define CCM_TARGET_ROOT93_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_MUX_SHIFT))&CCM_TARGET_ROOT93_MUX_MASK) -#define CCM_TARGET_ROOT93_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT93_ENABLE_SHIFT 28 -/* TARGET_ROOT93_SET Bit Fields */ -#define CCM_TARGET_ROOT93_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT93_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT93_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT93_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT93_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT93_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT93_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT93_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT93_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT93_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT93_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT93_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT93_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT93_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT93_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT93_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT93_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT93_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT93_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_SET_MUX_SHIFT))&CCM_TARGET_ROOT93_SET_MUX_MASK) -#define CCM_TARGET_ROOT93_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT93_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT93_CLR Bit Fields */ -#define CCM_TARGET_ROOT93_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT93_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT93_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT93_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT93_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT93_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT93_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT93_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT93_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT93_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT93_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT93_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT93_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT93_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT93_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT93_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT93_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT93_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT93_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_CLR_MUX_SHIFT))&CCM_TARGET_ROOT93_CLR_MUX_MASK) -#define CCM_TARGET_ROOT93_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT93_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT93_TOG Bit Fields */ -#define CCM_TARGET_ROOT93_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT93_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT93_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT93_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT93_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT93_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT93_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT93_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT93_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT93_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT93_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT93_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT93_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT93_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT93_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT93_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT93_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT93_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT93_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_TOG_MUX_SHIFT))&CCM_TARGET_ROOT93_TOG_MUX_MASK) -#define CCM_TARGET_ROOT93_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT93_TOG_ENABLE_SHIFT 28 -/* POST93 Bit Fields */ -#define CCM_POST93_POST_PODF_MASK 0x3Fu -#define CCM_POST93_POST_PODF_SHIFT 0 -#define CCM_POST93_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST93_POST_PODF_SHIFT))&CCM_POST93_POST_PODF_MASK) -#define CCM_POST93_BUSY1_MASK 0x80u -#define CCM_POST93_BUSY1_SHIFT 7 -#define CCM_POST93_AUTO_PODF_MASK 0x700u -#define CCM_POST93_AUTO_PODF_SHIFT 8 -#define CCM_POST93_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST93_AUTO_PODF_SHIFT))&CCM_POST93_AUTO_PODF_MASK) -#define CCM_POST93_AUTO_EN_MASK 0x1000u -#define CCM_POST93_AUTO_EN_SHIFT 12 -#define CCM_POST93_SLOW_MASK 0x8000u -#define CCM_POST93_SLOW_SHIFT 15 -#define CCM_POST93_SELECT_MASK 0x10000000u -#define CCM_POST93_SELECT_SHIFT 28 -#define CCM_POST93_BUSY2_MASK 0x80000000u -#define CCM_POST93_BUSY2_SHIFT 31 -/* POST_ROOT93_SET Bit Fields */ -#define CCM_POST_ROOT93_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT93_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT93_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_SET_POST_PODF_SHIFT))&CCM_POST_ROOT93_SET_POST_PODF_MASK) -#define CCM_POST_ROOT93_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT93_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT93_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT93_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT93_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT93_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT93_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT93_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT93_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT93_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT93_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT93_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT93_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT93_SET_BUSY2_SHIFT 31 -/* POST_ROOT93_CLR Bit Fields */ -#define CCM_POST_ROOT93_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT93_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT93_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT93_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT93_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT93_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT93_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT93_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT93_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT93_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT93_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT93_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT93_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT93_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT93_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT93_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT93_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT93_CLR_BUSY2_SHIFT 31 -/* POST_ROOT93_TOG Bit Fields */ -#define CCM_POST_ROOT93_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT93_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT93_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT93_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT93_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT93_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT93_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT93_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT93_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT93_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT93_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT93_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT93_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT93_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT93_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT93_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT93_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT93_TOG_BUSY2_SHIFT 31 -/* PRE93 Bit Fields */ -#define CCM_PRE93_PRE_PODF_B_MASK 0x7u -#define CCM_PRE93_PRE_PODF_B_SHIFT 0 -#define CCM_PRE93_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE93_PRE_PODF_B_SHIFT))&CCM_PRE93_PRE_PODF_B_MASK) -#define CCM_PRE93_BUSY0_MASK 0x8u -#define CCM_PRE93_BUSY0_SHIFT 3 -#define CCM_PRE93_MUX_B_MASK 0x700u -#define CCM_PRE93_MUX_B_SHIFT 8 -#define CCM_PRE93_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE93_MUX_B_SHIFT))&CCM_PRE93_MUX_B_MASK) -#define CCM_PRE93_EN_B_MASK 0x1000u -#define CCM_PRE93_EN_B_SHIFT 12 -#define CCM_PRE93_BUSY1_MASK 0x8000u -#define CCM_PRE93_BUSY1_SHIFT 15 -#define CCM_PRE93_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE93_PRE_PODF_A_SHIFT 16 -#define CCM_PRE93_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE93_PRE_PODF_A_SHIFT))&CCM_PRE93_PRE_PODF_A_MASK) -#define CCM_PRE93_BUSY3_MASK 0x80000u -#define CCM_PRE93_BUSY3_SHIFT 19 -#define CCM_PRE93_MUX_A_MASK 0x7000000u -#define CCM_PRE93_MUX_A_SHIFT 24 -#define CCM_PRE93_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE93_MUX_A_SHIFT))&CCM_PRE93_MUX_A_MASK) -#define CCM_PRE93_EN_A_MASK 0x10000000u -#define CCM_PRE93_EN_A_SHIFT 28 -#define CCM_PRE93_BUSY4_MASK 0x80000000u -#define CCM_PRE93_BUSY4_SHIFT 31 -/* PRE_ROOT93_SET Bit Fields */ -#define CCM_PRE_ROOT93_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT93_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT93_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT93_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT93_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT93_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT93_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT93_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT93_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_SET_MUX_B_SHIFT))&CCM_PRE_ROOT93_SET_MUX_B_MASK) -#define CCM_PRE_ROOT93_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT93_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT93_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT93_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT93_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT93_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT93_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT93_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT93_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT93_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT93_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT93_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT93_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_SET_MUX_A_SHIFT))&CCM_PRE_ROOT93_SET_MUX_A_MASK) -#define CCM_PRE_ROOT93_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT93_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT93_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT93_SET_BUSY4_SHIFT 31 -/* PRE_ROOT93_CLR Bit Fields */ -#define CCM_PRE_ROOT93_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT93_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT93_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT93_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT93_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT93_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT93_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT93_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT93_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT93_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT93_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT93_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT93_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT93_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT93_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT93_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT93_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT93_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT93_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT93_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT93_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT93_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT93_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT93_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT93_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT93_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT93_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT93_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT93_TOG Bit Fields */ -#define CCM_PRE_ROOT93_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT93_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT93_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT93_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT93_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT93_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT93_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT93_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT93_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT93_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT93_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT93_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT93_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT93_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT93_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT93_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT93_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT93_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT93_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT93_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT93_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT93_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT93_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT93_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT93_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT93_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT93_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT93_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL93 Bit Fields */ -#define CCM_ACCESS_CTRL93_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL93_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL93_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL93_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL93_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL93_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL93_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL93_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL93_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL93_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL93_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL93_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL93_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL93_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL93_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL93_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL93_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL93_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL93_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL93_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL93_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL93_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL93_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL93_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL93_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL93_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL93_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL93_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL93_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL93_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL93_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL93_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL93_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL93_LOCK_SHIFT 31 -/* ACCESS_CTRL93_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL93_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL93_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL93_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL93_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL93_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL93_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL93_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL93_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL93_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL93_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL93_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL93_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL93_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL93_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL93_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL93_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT94 Bit Fields */ -#define CCM_TARGET_ROOT94_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT94_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT94_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_POST_PODF_SHIFT))&CCM_TARGET_ROOT94_POST_PODF_MASK) -#define CCM_TARGET_ROOT94_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT94_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT94_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT94_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT94_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT94_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT94_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT94_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT94_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT94_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT94_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_PRE_PODF_SHIFT))&CCM_TARGET_ROOT94_PRE_PODF_MASK) -#define CCM_TARGET_ROOT94_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT94_MUX_SHIFT 24 -#define CCM_TARGET_ROOT94_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_MUX_SHIFT))&CCM_TARGET_ROOT94_MUX_MASK) -#define CCM_TARGET_ROOT94_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT94_ENABLE_SHIFT 28 -/* TARGET_ROOT94_SET Bit Fields */ -#define CCM_TARGET_ROOT94_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT94_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT94_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT94_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT94_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT94_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT94_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT94_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT94_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT94_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT94_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT94_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT94_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT94_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT94_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT94_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT94_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT94_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT94_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_SET_MUX_SHIFT))&CCM_TARGET_ROOT94_SET_MUX_MASK) -#define CCM_TARGET_ROOT94_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT94_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT94_CLR Bit Fields */ -#define CCM_TARGET_ROOT94_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT94_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT94_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT94_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT94_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT94_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT94_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT94_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT94_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT94_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT94_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT94_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT94_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT94_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT94_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT94_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT94_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT94_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT94_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_CLR_MUX_SHIFT))&CCM_TARGET_ROOT94_CLR_MUX_MASK) -#define CCM_TARGET_ROOT94_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT94_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT94_TOG Bit Fields */ -#define CCM_TARGET_ROOT94_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT94_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT94_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT94_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT94_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT94_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT94_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT94_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT94_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT94_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT94_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT94_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT94_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT94_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT94_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT94_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT94_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT94_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT94_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_TOG_MUX_SHIFT))&CCM_TARGET_ROOT94_TOG_MUX_MASK) -#define CCM_TARGET_ROOT94_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT94_TOG_ENABLE_SHIFT 28 -/* POST94 Bit Fields */ -#define CCM_POST94_POST_PODF_MASK 0x3Fu -#define CCM_POST94_POST_PODF_SHIFT 0 -#define CCM_POST94_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST94_POST_PODF_SHIFT))&CCM_POST94_POST_PODF_MASK) -#define CCM_POST94_BUSY1_MASK 0x80u -#define CCM_POST94_BUSY1_SHIFT 7 -#define CCM_POST94_AUTO_PODF_MASK 0x700u -#define CCM_POST94_AUTO_PODF_SHIFT 8 -#define CCM_POST94_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST94_AUTO_PODF_SHIFT))&CCM_POST94_AUTO_PODF_MASK) -#define CCM_POST94_AUTO_EN_MASK 0x1000u -#define CCM_POST94_AUTO_EN_SHIFT 12 -#define CCM_POST94_SLOW_MASK 0x8000u -#define CCM_POST94_SLOW_SHIFT 15 -#define CCM_POST94_SELECT_MASK 0x10000000u -#define CCM_POST94_SELECT_SHIFT 28 -#define CCM_POST94_BUSY2_MASK 0x80000000u -#define CCM_POST94_BUSY2_SHIFT 31 -/* POST_ROOT94_SET Bit Fields */ -#define CCM_POST_ROOT94_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT94_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT94_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_SET_POST_PODF_SHIFT))&CCM_POST_ROOT94_SET_POST_PODF_MASK) -#define CCM_POST_ROOT94_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT94_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT94_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT94_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT94_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT94_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT94_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT94_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT94_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT94_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT94_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT94_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT94_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT94_SET_BUSY2_SHIFT 31 -/* POST_ROOT94_CLR Bit Fields */ -#define CCM_POST_ROOT94_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT94_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT94_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT94_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT94_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT94_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT94_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT94_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT94_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT94_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT94_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT94_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT94_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT94_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT94_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT94_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT94_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT94_CLR_BUSY2_SHIFT 31 -/* POST_ROOT94_TOG Bit Fields */ -#define CCM_POST_ROOT94_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT94_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT94_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT94_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT94_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT94_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT94_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT94_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT94_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT94_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT94_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT94_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT94_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT94_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT94_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT94_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT94_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT94_TOG_BUSY2_SHIFT 31 -/* PRE94 Bit Fields */ -#define CCM_PRE94_PRE_PODF_B_MASK 0x7u -#define CCM_PRE94_PRE_PODF_B_SHIFT 0 -#define CCM_PRE94_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE94_PRE_PODF_B_SHIFT))&CCM_PRE94_PRE_PODF_B_MASK) -#define CCM_PRE94_BUSY0_MASK 0x8u -#define CCM_PRE94_BUSY0_SHIFT 3 -#define CCM_PRE94_MUX_B_MASK 0x700u -#define CCM_PRE94_MUX_B_SHIFT 8 -#define CCM_PRE94_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE94_MUX_B_SHIFT))&CCM_PRE94_MUX_B_MASK) -#define CCM_PRE94_EN_B_MASK 0x1000u -#define CCM_PRE94_EN_B_SHIFT 12 -#define CCM_PRE94_BUSY1_MASK 0x8000u -#define CCM_PRE94_BUSY1_SHIFT 15 -#define CCM_PRE94_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE94_PRE_PODF_A_SHIFT 16 -#define CCM_PRE94_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE94_PRE_PODF_A_SHIFT))&CCM_PRE94_PRE_PODF_A_MASK) -#define CCM_PRE94_BUSY3_MASK 0x80000u -#define CCM_PRE94_BUSY3_SHIFT 19 -#define CCM_PRE94_MUX_A_MASK 0x7000000u -#define CCM_PRE94_MUX_A_SHIFT 24 -#define CCM_PRE94_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE94_MUX_A_SHIFT))&CCM_PRE94_MUX_A_MASK) -#define CCM_PRE94_EN_A_MASK 0x10000000u -#define CCM_PRE94_EN_A_SHIFT 28 -#define CCM_PRE94_BUSY4_MASK 0x80000000u -#define CCM_PRE94_BUSY4_SHIFT 31 -/* PRE_ROOT94_SET Bit Fields */ -#define CCM_PRE_ROOT94_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT94_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT94_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT94_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT94_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT94_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT94_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT94_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT94_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_SET_MUX_B_SHIFT))&CCM_PRE_ROOT94_SET_MUX_B_MASK) -#define CCM_PRE_ROOT94_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT94_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT94_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT94_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT94_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT94_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT94_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT94_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT94_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT94_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT94_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT94_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT94_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_SET_MUX_A_SHIFT))&CCM_PRE_ROOT94_SET_MUX_A_MASK) -#define CCM_PRE_ROOT94_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT94_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT94_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT94_SET_BUSY4_SHIFT 31 -/* PRE_ROOT94_CLR Bit Fields */ -#define CCM_PRE_ROOT94_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT94_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT94_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT94_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT94_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT94_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT94_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT94_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT94_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT94_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT94_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT94_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT94_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT94_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT94_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT94_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT94_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT94_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT94_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT94_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT94_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT94_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT94_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT94_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT94_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT94_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT94_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT94_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT94_TOG Bit Fields */ -#define CCM_PRE_ROOT94_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT94_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT94_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT94_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT94_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT94_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT94_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT94_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT94_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT94_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT94_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT94_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT94_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT94_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT94_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT94_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT94_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT94_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT94_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT94_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT94_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT94_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT94_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT94_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT94_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT94_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT94_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT94_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL94 Bit Fields */ -#define CCM_ACCESS_CTRL94_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL94_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL94_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL94_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL94_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL94_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL94_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL94_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL94_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL94_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL94_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL94_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL94_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL94_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL94_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL94_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL94_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL94_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL94_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL94_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL94_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL94_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL94_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL94_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL94_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL94_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL94_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL94_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL94_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL94_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL94_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL94_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL94_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL94_LOCK_SHIFT 31 -/* ACCESS_CTRL94_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL94_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL94_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL94_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL94_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL94_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL94_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL94_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL94_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL94_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL94_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL94_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL94_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL94_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL94_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL94_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL94_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT95 Bit Fields */ -#define CCM_TARGET_ROOT95_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT95_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT95_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_POST_PODF_SHIFT))&CCM_TARGET_ROOT95_POST_PODF_MASK) -#define CCM_TARGET_ROOT95_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT95_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT95_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT95_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT95_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT95_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT95_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT95_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT95_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT95_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT95_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_PRE_PODF_SHIFT))&CCM_TARGET_ROOT95_PRE_PODF_MASK) -#define CCM_TARGET_ROOT95_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT95_MUX_SHIFT 24 -#define CCM_TARGET_ROOT95_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_MUX_SHIFT))&CCM_TARGET_ROOT95_MUX_MASK) -#define CCM_TARGET_ROOT95_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT95_ENABLE_SHIFT 28 -/* TARGET_ROOT95_SET Bit Fields */ -#define CCM_TARGET_ROOT95_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT95_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT95_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT95_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT95_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT95_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT95_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT95_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT95_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT95_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT95_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT95_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT95_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT95_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT95_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT95_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT95_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT95_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT95_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_SET_MUX_SHIFT))&CCM_TARGET_ROOT95_SET_MUX_MASK) -#define CCM_TARGET_ROOT95_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT95_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT95_CLR Bit Fields */ -#define CCM_TARGET_ROOT95_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT95_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT95_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT95_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT95_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT95_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT95_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT95_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT95_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT95_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT95_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT95_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT95_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT95_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT95_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT95_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT95_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT95_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT95_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_CLR_MUX_SHIFT))&CCM_TARGET_ROOT95_CLR_MUX_MASK) -#define CCM_TARGET_ROOT95_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT95_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT95_TOG Bit Fields */ -#define CCM_TARGET_ROOT95_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT95_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT95_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT95_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT95_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT95_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT95_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT95_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT95_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT95_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT95_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT95_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT95_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT95_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT95_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT95_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT95_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT95_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT95_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_TOG_MUX_SHIFT))&CCM_TARGET_ROOT95_TOG_MUX_MASK) -#define CCM_TARGET_ROOT95_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT95_TOG_ENABLE_SHIFT 28 -/* POST95 Bit Fields */ -#define CCM_POST95_POST_PODF_MASK 0x3Fu -#define CCM_POST95_POST_PODF_SHIFT 0 -#define CCM_POST95_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST95_POST_PODF_SHIFT))&CCM_POST95_POST_PODF_MASK) -#define CCM_POST95_BUSY1_MASK 0x80u -#define CCM_POST95_BUSY1_SHIFT 7 -#define CCM_POST95_AUTO_PODF_MASK 0x700u -#define CCM_POST95_AUTO_PODF_SHIFT 8 -#define CCM_POST95_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST95_AUTO_PODF_SHIFT))&CCM_POST95_AUTO_PODF_MASK) -#define CCM_POST95_AUTO_EN_MASK 0x1000u -#define CCM_POST95_AUTO_EN_SHIFT 12 -#define CCM_POST95_SLOW_MASK 0x8000u -#define CCM_POST95_SLOW_SHIFT 15 -#define CCM_POST95_SELECT_MASK 0x10000000u -#define CCM_POST95_SELECT_SHIFT 28 -#define CCM_POST95_BUSY2_MASK 0x80000000u -#define CCM_POST95_BUSY2_SHIFT 31 -/* POST_ROOT95_SET Bit Fields */ -#define CCM_POST_ROOT95_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT95_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT95_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_SET_POST_PODF_SHIFT))&CCM_POST_ROOT95_SET_POST_PODF_MASK) -#define CCM_POST_ROOT95_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT95_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT95_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT95_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT95_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT95_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT95_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT95_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT95_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT95_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT95_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT95_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT95_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT95_SET_BUSY2_SHIFT 31 -/* POST_ROOT95_CLR Bit Fields */ -#define CCM_POST_ROOT95_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT95_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT95_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT95_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT95_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT95_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT95_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT95_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT95_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT95_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT95_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT95_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT95_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT95_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT95_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT95_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT95_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT95_CLR_BUSY2_SHIFT 31 -/* POST_ROOT95_TOG Bit Fields */ -#define CCM_POST_ROOT95_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT95_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT95_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT95_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT95_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT95_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT95_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT95_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT95_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT95_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT95_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT95_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT95_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT95_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT95_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT95_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT95_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT95_TOG_BUSY2_SHIFT 31 -/* PRE95 Bit Fields */ -#define CCM_PRE95_PRE_PODF_B_MASK 0x7u -#define CCM_PRE95_PRE_PODF_B_SHIFT 0 -#define CCM_PRE95_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE95_PRE_PODF_B_SHIFT))&CCM_PRE95_PRE_PODF_B_MASK) -#define CCM_PRE95_BUSY0_MASK 0x8u -#define CCM_PRE95_BUSY0_SHIFT 3 -#define CCM_PRE95_MUX_B_MASK 0x700u -#define CCM_PRE95_MUX_B_SHIFT 8 -#define CCM_PRE95_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE95_MUX_B_SHIFT))&CCM_PRE95_MUX_B_MASK) -#define CCM_PRE95_EN_B_MASK 0x1000u -#define CCM_PRE95_EN_B_SHIFT 12 -#define CCM_PRE95_BUSY1_MASK 0x8000u -#define CCM_PRE95_BUSY1_SHIFT 15 -#define CCM_PRE95_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE95_PRE_PODF_A_SHIFT 16 -#define CCM_PRE95_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE95_PRE_PODF_A_SHIFT))&CCM_PRE95_PRE_PODF_A_MASK) -#define CCM_PRE95_BUSY3_MASK 0x80000u -#define CCM_PRE95_BUSY3_SHIFT 19 -#define CCM_PRE95_MUX_A_MASK 0x7000000u -#define CCM_PRE95_MUX_A_SHIFT 24 -#define CCM_PRE95_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE95_MUX_A_SHIFT))&CCM_PRE95_MUX_A_MASK) -#define CCM_PRE95_EN_A_MASK 0x10000000u -#define CCM_PRE95_EN_A_SHIFT 28 -#define CCM_PRE95_BUSY4_MASK 0x80000000u -#define CCM_PRE95_BUSY4_SHIFT 31 -/* PRE_ROOT95_SET Bit Fields */ -#define CCM_PRE_ROOT95_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT95_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT95_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT95_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT95_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT95_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT95_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT95_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT95_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_SET_MUX_B_SHIFT))&CCM_PRE_ROOT95_SET_MUX_B_MASK) -#define CCM_PRE_ROOT95_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT95_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT95_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT95_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT95_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT95_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT95_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT95_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT95_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT95_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT95_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT95_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT95_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_SET_MUX_A_SHIFT))&CCM_PRE_ROOT95_SET_MUX_A_MASK) -#define CCM_PRE_ROOT95_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT95_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT95_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT95_SET_BUSY4_SHIFT 31 -/* PRE_ROOT95_CLR Bit Fields */ -#define CCM_PRE_ROOT95_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT95_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT95_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT95_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT95_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT95_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT95_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT95_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT95_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT95_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT95_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT95_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT95_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT95_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT95_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT95_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT95_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT95_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT95_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT95_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT95_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT95_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT95_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT95_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT95_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT95_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT95_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT95_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT95_TOG Bit Fields */ -#define CCM_PRE_ROOT95_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT95_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT95_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT95_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT95_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT95_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT95_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT95_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT95_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT95_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT95_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT95_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT95_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT95_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT95_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT95_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT95_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT95_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT95_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT95_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT95_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT95_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT95_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT95_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT95_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT95_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT95_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT95_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL95 Bit Fields */ -#define CCM_ACCESS_CTRL95_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL95_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL95_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL95_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL95_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL95_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL95_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL95_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL95_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL95_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL95_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL95_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL95_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL95_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL95_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL95_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL95_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL95_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL95_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL95_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL95_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL95_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL95_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL95_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL95_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL95_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL95_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL95_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL95_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL95_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL95_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL95_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL95_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL95_LOCK_SHIFT 31 -/* ACCESS_CTRL95_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL95_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL95_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL95_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL95_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL95_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL95_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL95_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL95_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL95_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL95_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL95_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL95_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL95_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL95_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL95_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL95_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT96 Bit Fields */ -#define CCM_TARGET_ROOT96_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT96_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT96_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_POST_PODF_SHIFT))&CCM_TARGET_ROOT96_POST_PODF_MASK) -#define CCM_TARGET_ROOT96_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT96_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT96_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT96_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT96_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT96_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT96_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT96_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT96_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT96_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT96_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_PRE_PODF_SHIFT))&CCM_TARGET_ROOT96_PRE_PODF_MASK) -#define CCM_TARGET_ROOT96_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT96_MUX_SHIFT 24 -#define CCM_TARGET_ROOT96_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_MUX_SHIFT))&CCM_TARGET_ROOT96_MUX_MASK) -#define CCM_TARGET_ROOT96_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT96_ENABLE_SHIFT 28 -/* TARGET_ROOT96_SET Bit Fields */ -#define CCM_TARGET_ROOT96_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT96_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT96_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT96_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT96_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT96_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT96_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT96_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT96_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT96_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT96_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT96_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT96_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT96_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT96_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT96_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT96_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT96_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT96_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_SET_MUX_SHIFT))&CCM_TARGET_ROOT96_SET_MUX_MASK) -#define CCM_TARGET_ROOT96_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT96_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT96_CLR Bit Fields */ -#define CCM_TARGET_ROOT96_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT96_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT96_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT96_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT96_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT96_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT96_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT96_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT96_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT96_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT96_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT96_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT96_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT96_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT96_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT96_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT96_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT96_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT96_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_CLR_MUX_SHIFT))&CCM_TARGET_ROOT96_CLR_MUX_MASK) -#define CCM_TARGET_ROOT96_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT96_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT96_TOG Bit Fields */ -#define CCM_TARGET_ROOT96_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT96_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT96_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT96_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT96_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT96_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT96_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT96_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT96_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT96_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT96_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT96_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT96_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT96_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT96_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT96_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT96_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT96_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT96_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_TOG_MUX_SHIFT))&CCM_TARGET_ROOT96_TOG_MUX_MASK) -#define CCM_TARGET_ROOT96_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT96_TOG_ENABLE_SHIFT 28 -/* POST96 Bit Fields */ -#define CCM_POST96_POST_PODF_MASK 0x3Fu -#define CCM_POST96_POST_PODF_SHIFT 0 -#define CCM_POST96_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST96_POST_PODF_SHIFT))&CCM_POST96_POST_PODF_MASK) -#define CCM_POST96_BUSY1_MASK 0x80u -#define CCM_POST96_BUSY1_SHIFT 7 -#define CCM_POST96_AUTO_PODF_MASK 0x700u -#define CCM_POST96_AUTO_PODF_SHIFT 8 -#define CCM_POST96_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST96_AUTO_PODF_SHIFT))&CCM_POST96_AUTO_PODF_MASK) -#define CCM_POST96_AUTO_EN_MASK 0x1000u -#define CCM_POST96_AUTO_EN_SHIFT 12 -#define CCM_POST96_SLOW_MASK 0x8000u -#define CCM_POST96_SLOW_SHIFT 15 -#define CCM_POST96_SELECT_MASK 0x10000000u -#define CCM_POST96_SELECT_SHIFT 28 -#define CCM_POST96_BUSY2_MASK 0x80000000u -#define CCM_POST96_BUSY2_SHIFT 31 -/* POST_ROOT96_SET Bit Fields */ -#define CCM_POST_ROOT96_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT96_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT96_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_SET_POST_PODF_SHIFT))&CCM_POST_ROOT96_SET_POST_PODF_MASK) -#define CCM_POST_ROOT96_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT96_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT96_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT96_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT96_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT96_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT96_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT96_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT96_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT96_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT96_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT96_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT96_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT96_SET_BUSY2_SHIFT 31 -/* POST_ROOT96_CLR Bit Fields */ -#define CCM_POST_ROOT96_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT96_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT96_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT96_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT96_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT96_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT96_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT96_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT96_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT96_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT96_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT96_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT96_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT96_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT96_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT96_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT96_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT96_CLR_BUSY2_SHIFT 31 -/* POST_ROOT96_TOG Bit Fields */ -#define CCM_POST_ROOT96_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT96_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT96_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT96_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT96_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT96_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT96_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT96_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT96_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT96_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT96_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT96_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT96_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT96_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT96_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT96_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT96_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT96_TOG_BUSY2_SHIFT 31 -/* PRE96 Bit Fields */ -#define CCM_PRE96_PRE_PODF_B_MASK 0x7u -#define CCM_PRE96_PRE_PODF_B_SHIFT 0 -#define CCM_PRE96_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE96_PRE_PODF_B_SHIFT))&CCM_PRE96_PRE_PODF_B_MASK) -#define CCM_PRE96_BUSY0_MASK 0x8u -#define CCM_PRE96_BUSY0_SHIFT 3 -#define CCM_PRE96_MUX_B_MASK 0x700u -#define CCM_PRE96_MUX_B_SHIFT 8 -#define CCM_PRE96_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE96_MUX_B_SHIFT))&CCM_PRE96_MUX_B_MASK) -#define CCM_PRE96_EN_B_MASK 0x1000u -#define CCM_PRE96_EN_B_SHIFT 12 -#define CCM_PRE96_BUSY1_MASK 0x8000u -#define CCM_PRE96_BUSY1_SHIFT 15 -#define CCM_PRE96_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE96_PRE_PODF_A_SHIFT 16 -#define CCM_PRE96_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE96_PRE_PODF_A_SHIFT))&CCM_PRE96_PRE_PODF_A_MASK) -#define CCM_PRE96_BUSY3_MASK 0x80000u -#define CCM_PRE96_BUSY3_SHIFT 19 -#define CCM_PRE96_MUX_A_MASK 0x7000000u -#define CCM_PRE96_MUX_A_SHIFT 24 -#define CCM_PRE96_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE96_MUX_A_SHIFT))&CCM_PRE96_MUX_A_MASK) -#define CCM_PRE96_EN_A_MASK 0x10000000u -#define CCM_PRE96_EN_A_SHIFT 28 -#define CCM_PRE96_BUSY4_MASK 0x80000000u -#define CCM_PRE96_BUSY4_SHIFT 31 -/* PRE_ROOT96_SET Bit Fields */ -#define CCM_PRE_ROOT96_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT96_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT96_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT96_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT96_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT96_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT96_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT96_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT96_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_SET_MUX_B_SHIFT))&CCM_PRE_ROOT96_SET_MUX_B_MASK) -#define CCM_PRE_ROOT96_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT96_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT96_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT96_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT96_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT96_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT96_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT96_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT96_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT96_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT96_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT96_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT96_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_SET_MUX_A_SHIFT))&CCM_PRE_ROOT96_SET_MUX_A_MASK) -#define CCM_PRE_ROOT96_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT96_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT96_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT96_SET_BUSY4_SHIFT 31 -/* PRE_ROOT96_CLR Bit Fields */ -#define CCM_PRE_ROOT96_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT96_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT96_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT96_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT96_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT96_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT96_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT96_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT96_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT96_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT96_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT96_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT96_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT96_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT96_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT96_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT96_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT96_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT96_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT96_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT96_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT96_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT96_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT96_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT96_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT96_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT96_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT96_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT96_TOG Bit Fields */ -#define CCM_PRE_ROOT96_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT96_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT96_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT96_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT96_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT96_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT96_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT96_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT96_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT96_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT96_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT96_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT96_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT96_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT96_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT96_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT96_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT96_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT96_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT96_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT96_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT96_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT96_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT96_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT96_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT96_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT96_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT96_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL96 Bit Fields */ -#define CCM_ACCESS_CTRL96_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL96_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL96_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL96_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL96_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL96_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL96_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL96_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL96_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL96_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL96_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL96_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL96_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL96_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL96_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL96_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL96_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL96_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL96_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL96_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL96_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL96_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL96_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL96_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL96_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL96_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL96_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL96_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL96_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL96_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL96_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL96_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL96_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL96_LOCK_SHIFT 31 -/* ACCESS_CTRL96_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL96_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL96_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL96_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL96_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL96_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL96_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL96_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL96_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL96_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL96_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL96_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL96_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL96_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL96_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL96_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL96_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT97 Bit Fields */ -#define CCM_TARGET_ROOT97_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT97_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT97_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_POST_PODF_SHIFT))&CCM_TARGET_ROOT97_POST_PODF_MASK) -#define CCM_TARGET_ROOT97_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT97_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT97_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT97_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT97_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT97_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT97_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT97_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT97_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT97_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT97_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_PRE_PODF_SHIFT))&CCM_TARGET_ROOT97_PRE_PODF_MASK) -#define CCM_TARGET_ROOT97_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT97_MUX_SHIFT 24 -#define CCM_TARGET_ROOT97_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_MUX_SHIFT))&CCM_TARGET_ROOT97_MUX_MASK) -#define CCM_TARGET_ROOT97_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT97_ENABLE_SHIFT 28 -/* TARGET_ROOT97_SET Bit Fields */ -#define CCM_TARGET_ROOT97_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT97_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT97_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT97_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT97_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT97_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT97_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT97_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT97_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT97_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT97_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT97_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT97_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT97_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT97_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT97_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT97_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT97_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT97_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_SET_MUX_SHIFT))&CCM_TARGET_ROOT97_SET_MUX_MASK) -#define CCM_TARGET_ROOT97_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT97_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT97_CLR Bit Fields */ -#define CCM_TARGET_ROOT97_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT97_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT97_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT97_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT97_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT97_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT97_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT97_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT97_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT97_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT97_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT97_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT97_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT97_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT97_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT97_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT97_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT97_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT97_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_CLR_MUX_SHIFT))&CCM_TARGET_ROOT97_CLR_MUX_MASK) -#define CCM_TARGET_ROOT97_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT97_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT97_TOG Bit Fields */ -#define CCM_TARGET_ROOT97_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT97_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT97_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT97_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT97_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT97_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT97_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT97_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT97_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT97_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT97_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT97_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT97_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT97_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT97_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT97_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT97_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT97_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT97_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_TOG_MUX_SHIFT))&CCM_TARGET_ROOT97_TOG_MUX_MASK) -#define CCM_TARGET_ROOT97_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT97_TOG_ENABLE_SHIFT 28 -/* POST97 Bit Fields */ -#define CCM_POST97_POST_PODF_MASK 0x3Fu -#define CCM_POST97_POST_PODF_SHIFT 0 -#define CCM_POST97_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST97_POST_PODF_SHIFT))&CCM_POST97_POST_PODF_MASK) -#define CCM_POST97_BUSY1_MASK 0x80u -#define CCM_POST97_BUSY1_SHIFT 7 -#define CCM_POST97_AUTO_PODF_MASK 0x700u -#define CCM_POST97_AUTO_PODF_SHIFT 8 -#define CCM_POST97_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST97_AUTO_PODF_SHIFT))&CCM_POST97_AUTO_PODF_MASK) -#define CCM_POST97_AUTO_EN_MASK 0x1000u -#define CCM_POST97_AUTO_EN_SHIFT 12 -#define CCM_POST97_SLOW_MASK 0x8000u -#define CCM_POST97_SLOW_SHIFT 15 -#define CCM_POST97_SELECT_MASK 0x10000000u -#define CCM_POST97_SELECT_SHIFT 28 -#define CCM_POST97_BUSY2_MASK 0x80000000u -#define CCM_POST97_BUSY2_SHIFT 31 -/* POST_ROOT97_SET Bit Fields */ -#define CCM_POST_ROOT97_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT97_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT97_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_SET_POST_PODF_SHIFT))&CCM_POST_ROOT97_SET_POST_PODF_MASK) -#define CCM_POST_ROOT97_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT97_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT97_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT97_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT97_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT97_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT97_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT97_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT97_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT97_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT97_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT97_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT97_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT97_SET_BUSY2_SHIFT 31 -/* POST_ROOT97_CLR Bit Fields */ -#define CCM_POST_ROOT97_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT97_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT97_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT97_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT97_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT97_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT97_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT97_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT97_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT97_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT97_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT97_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT97_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT97_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT97_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT97_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT97_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT97_CLR_BUSY2_SHIFT 31 -/* POST_ROOT97_TOG Bit Fields */ -#define CCM_POST_ROOT97_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT97_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT97_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT97_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT97_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT97_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT97_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT97_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT97_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT97_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT97_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT97_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT97_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT97_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT97_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT97_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT97_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT97_TOG_BUSY2_SHIFT 31 -/* PRE97 Bit Fields */ -#define CCM_PRE97_PRE_PODF_B_MASK 0x7u -#define CCM_PRE97_PRE_PODF_B_SHIFT 0 -#define CCM_PRE97_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE97_PRE_PODF_B_SHIFT))&CCM_PRE97_PRE_PODF_B_MASK) -#define CCM_PRE97_BUSY0_MASK 0x8u -#define CCM_PRE97_BUSY0_SHIFT 3 -#define CCM_PRE97_MUX_B_MASK 0x700u -#define CCM_PRE97_MUX_B_SHIFT 8 -#define CCM_PRE97_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE97_MUX_B_SHIFT))&CCM_PRE97_MUX_B_MASK) -#define CCM_PRE97_EN_B_MASK 0x1000u -#define CCM_PRE97_EN_B_SHIFT 12 -#define CCM_PRE97_BUSY1_MASK 0x8000u -#define CCM_PRE97_BUSY1_SHIFT 15 -#define CCM_PRE97_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE97_PRE_PODF_A_SHIFT 16 -#define CCM_PRE97_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE97_PRE_PODF_A_SHIFT))&CCM_PRE97_PRE_PODF_A_MASK) -#define CCM_PRE97_BUSY3_MASK 0x80000u -#define CCM_PRE97_BUSY3_SHIFT 19 -#define CCM_PRE97_MUX_A_MASK 0x7000000u -#define CCM_PRE97_MUX_A_SHIFT 24 -#define CCM_PRE97_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE97_MUX_A_SHIFT))&CCM_PRE97_MUX_A_MASK) -#define CCM_PRE97_EN_A_MASK 0x10000000u -#define CCM_PRE97_EN_A_SHIFT 28 -#define CCM_PRE97_BUSY4_MASK 0x80000000u -#define CCM_PRE97_BUSY4_SHIFT 31 -/* PRE_ROOT97_SET Bit Fields */ -#define CCM_PRE_ROOT97_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT97_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT97_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT97_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT97_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT97_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT97_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT97_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT97_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_SET_MUX_B_SHIFT))&CCM_PRE_ROOT97_SET_MUX_B_MASK) -#define CCM_PRE_ROOT97_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT97_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT97_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT97_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT97_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT97_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT97_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT97_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT97_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT97_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT97_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT97_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT97_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_SET_MUX_A_SHIFT))&CCM_PRE_ROOT97_SET_MUX_A_MASK) -#define CCM_PRE_ROOT97_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT97_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT97_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT97_SET_BUSY4_SHIFT 31 -/* PRE_ROOT97_CLR Bit Fields */ -#define CCM_PRE_ROOT97_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT97_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT97_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT97_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT97_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT97_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT97_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT97_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT97_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT97_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT97_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT97_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT97_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT97_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT97_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT97_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT97_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT97_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT97_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT97_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT97_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT97_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT97_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT97_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT97_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT97_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT97_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT97_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT97_TOG Bit Fields */ -#define CCM_PRE_ROOT97_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT97_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT97_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT97_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT97_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT97_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT97_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT97_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT97_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT97_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT97_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT97_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT97_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT97_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT97_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT97_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT97_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT97_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT97_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT97_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT97_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT97_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT97_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT97_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT97_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT97_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT97_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT97_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL97 Bit Fields */ -#define CCM_ACCESS_CTRL97_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL97_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL97_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL97_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL97_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL97_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL97_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL97_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL97_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL97_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL97_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL97_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL97_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL97_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL97_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL97_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL97_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL97_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL97_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL97_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL97_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL97_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL97_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL97_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL97_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL97_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL97_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL97_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL97_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL97_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL97_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL97_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL97_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL97_LOCK_SHIFT 31 -/* ACCESS_CTRL97_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL97_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL97_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL97_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL97_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL97_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL97_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL97_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL97_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL97_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL97_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL97_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL97_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL97_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL97_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL97_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL97_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT98 Bit Fields */ -#define CCM_TARGET_ROOT98_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT98_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT98_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_POST_PODF_SHIFT))&CCM_TARGET_ROOT98_POST_PODF_MASK) -#define CCM_TARGET_ROOT98_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT98_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT98_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT98_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT98_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT98_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT98_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT98_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT98_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT98_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT98_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_PRE_PODF_SHIFT))&CCM_TARGET_ROOT98_PRE_PODF_MASK) -#define CCM_TARGET_ROOT98_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT98_MUX_SHIFT 24 -#define CCM_TARGET_ROOT98_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_MUX_SHIFT))&CCM_TARGET_ROOT98_MUX_MASK) -#define CCM_TARGET_ROOT98_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT98_ENABLE_SHIFT 28 -/* TARGET_ROOT98_SET Bit Fields */ -#define CCM_TARGET_ROOT98_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT98_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT98_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT98_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT98_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT98_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT98_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT98_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT98_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT98_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT98_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT98_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT98_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT98_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT98_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT98_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT98_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT98_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT98_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_SET_MUX_SHIFT))&CCM_TARGET_ROOT98_SET_MUX_MASK) -#define CCM_TARGET_ROOT98_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT98_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT98_CLR Bit Fields */ -#define CCM_TARGET_ROOT98_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT98_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT98_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT98_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT98_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT98_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT98_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT98_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT98_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT98_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT98_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT98_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT98_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT98_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT98_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT98_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT98_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT98_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT98_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_CLR_MUX_SHIFT))&CCM_TARGET_ROOT98_CLR_MUX_MASK) -#define CCM_TARGET_ROOT98_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT98_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT98_TOG Bit Fields */ -#define CCM_TARGET_ROOT98_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT98_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT98_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT98_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT98_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT98_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT98_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT98_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT98_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT98_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT98_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT98_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT98_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT98_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT98_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT98_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT98_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT98_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT98_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_TOG_MUX_SHIFT))&CCM_TARGET_ROOT98_TOG_MUX_MASK) -#define CCM_TARGET_ROOT98_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT98_TOG_ENABLE_SHIFT 28 -/* POST98 Bit Fields */ -#define CCM_POST98_POST_PODF_MASK 0x3Fu -#define CCM_POST98_POST_PODF_SHIFT 0 -#define CCM_POST98_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST98_POST_PODF_SHIFT))&CCM_POST98_POST_PODF_MASK) -#define CCM_POST98_BUSY1_MASK 0x80u -#define CCM_POST98_BUSY1_SHIFT 7 -#define CCM_POST98_AUTO_PODF_MASK 0x700u -#define CCM_POST98_AUTO_PODF_SHIFT 8 -#define CCM_POST98_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST98_AUTO_PODF_SHIFT))&CCM_POST98_AUTO_PODF_MASK) -#define CCM_POST98_AUTO_EN_MASK 0x1000u -#define CCM_POST98_AUTO_EN_SHIFT 12 -#define CCM_POST98_SLOW_MASK 0x8000u -#define CCM_POST98_SLOW_SHIFT 15 -#define CCM_POST98_SELECT_MASK 0x10000000u -#define CCM_POST98_SELECT_SHIFT 28 -#define CCM_POST98_BUSY2_MASK 0x80000000u -#define CCM_POST98_BUSY2_SHIFT 31 -/* POST_ROOT98_SET Bit Fields */ -#define CCM_POST_ROOT98_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT98_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT98_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_SET_POST_PODF_SHIFT))&CCM_POST_ROOT98_SET_POST_PODF_MASK) -#define CCM_POST_ROOT98_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT98_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT98_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT98_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT98_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT98_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT98_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT98_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT98_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT98_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT98_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT98_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT98_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT98_SET_BUSY2_SHIFT 31 -/* POST_ROOT98_CLR Bit Fields */ -#define CCM_POST_ROOT98_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT98_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT98_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT98_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT98_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT98_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT98_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT98_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT98_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT98_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT98_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT98_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT98_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT98_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT98_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT98_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT98_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT98_CLR_BUSY2_SHIFT 31 -/* POST_ROOT98_TOG Bit Fields */ -#define CCM_POST_ROOT98_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT98_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT98_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT98_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT98_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT98_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT98_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT98_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT98_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT98_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT98_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT98_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT98_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT98_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT98_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT98_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT98_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT98_TOG_BUSY2_SHIFT 31 -/* PRE98 Bit Fields */ -#define CCM_PRE98_PRE_PODF_B_MASK 0x7u -#define CCM_PRE98_PRE_PODF_B_SHIFT 0 -#define CCM_PRE98_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE98_PRE_PODF_B_SHIFT))&CCM_PRE98_PRE_PODF_B_MASK) -#define CCM_PRE98_BUSY0_MASK 0x8u -#define CCM_PRE98_BUSY0_SHIFT 3 -#define CCM_PRE98_MUX_B_MASK 0x700u -#define CCM_PRE98_MUX_B_SHIFT 8 -#define CCM_PRE98_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE98_MUX_B_SHIFT))&CCM_PRE98_MUX_B_MASK) -#define CCM_PRE98_EN_B_MASK 0x1000u -#define CCM_PRE98_EN_B_SHIFT 12 -#define CCM_PRE98_BUSY1_MASK 0x8000u -#define CCM_PRE98_BUSY1_SHIFT 15 -#define CCM_PRE98_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE98_PRE_PODF_A_SHIFT 16 -#define CCM_PRE98_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE98_PRE_PODF_A_SHIFT))&CCM_PRE98_PRE_PODF_A_MASK) -#define CCM_PRE98_BUSY3_MASK 0x80000u -#define CCM_PRE98_BUSY3_SHIFT 19 -#define CCM_PRE98_MUX_A_MASK 0x7000000u -#define CCM_PRE98_MUX_A_SHIFT 24 -#define CCM_PRE98_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE98_MUX_A_SHIFT))&CCM_PRE98_MUX_A_MASK) -#define CCM_PRE98_EN_A_MASK 0x10000000u -#define CCM_PRE98_EN_A_SHIFT 28 -#define CCM_PRE98_BUSY4_MASK 0x80000000u -#define CCM_PRE98_BUSY4_SHIFT 31 -/* PRE_ROOT98_SET Bit Fields */ -#define CCM_PRE_ROOT98_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT98_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT98_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT98_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT98_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT98_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT98_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT98_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT98_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_SET_MUX_B_SHIFT))&CCM_PRE_ROOT98_SET_MUX_B_MASK) -#define CCM_PRE_ROOT98_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT98_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT98_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT98_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT98_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT98_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT98_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT98_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT98_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT98_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT98_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT98_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT98_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_SET_MUX_A_SHIFT))&CCM_PRE_ROOT98_SET_MUX_A_MASK) -#define CCM_PRE_ROOT98_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT98_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT98_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT98_SET_BUSY4_SHIFT 31 -/* PRE_ROOT98_CLR Bit Fields */ -#define CCM_PRE_ROOT98_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT98_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT98_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT98_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT98_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT98_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT98_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT98_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT98_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT98_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT98_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT98_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT98_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT98_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT98_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT98_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT98_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT98_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT98_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT98_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT98_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT98_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT98_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT98_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT98_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT98_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT98_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT98_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT98_TOG Bit Fields */ -#define CCM_PRE_ROOT98_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT98_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT98_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT98_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT98_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT98_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT98_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT98_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT98_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT98_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT98_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT98_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT98_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT98_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT98_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT98_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT98_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT98_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT98_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT98_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT98_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT98_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT98_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT98_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT98_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT98_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT98_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT98_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL98 Bit Fields */ -#define CCM_ACCESS_CTRL98_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL98_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL98_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL98_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL98_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL98_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL98_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL98_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL98_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL98_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL98_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL98_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL98_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL98_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL98_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL98_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL98_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL98_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL98_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL98_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL98_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL98_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL98_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL98_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL98_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL98_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL98_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL98_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL98_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL98_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL98_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL98_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL98_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL98_LOCK_SHIFT 31 -/* ACCESS_CTRL98_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL98_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL98_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL98_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL98_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL98_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL98_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL98_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL98_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL98_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL98_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL98_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL98_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL98_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL98_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL98_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL98_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT99 Bit Fields */ -#define CCM_TARGET_ROOT99_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT99_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT99_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_POST_PODF_SHIFT))&CCM_TARGET_ROOT99_POST_PODF_MASK) -#define CCM_TARGET_ROOT99_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT99_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT99_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT99_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT99_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT99_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT99_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT99_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT99_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT99_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT99_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_PRE_PODF_SHIFT))&CCM_TARGET_ROOT99_PRE_PODF_MASK) -#define CCM_TARGET_ROOT99_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT99_MUX_SHIFT 24 -#define CCM_TARGET_ROOT99_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_MUX_SHIFT))&CCM_TARGET_ROOT99_MUX_MASK) -#define CCM_TARGET_ROOT99_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT99_ENABLE_SHIFT 28 -/* TARGET_ROOT99_SET Bit Fields */ -#define CCM_TARGET_ROOT99_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT99_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT99_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT99_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT99_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT99_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT99_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT99_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT99_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT99_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT99_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT99_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT99_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT99_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT99_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT99_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT99_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT99_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT99_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_SET_MUX_SHIFT))&CCM_TARGET_ROOT99_SET_MUX_MASK) -#define CCM_TARGET_ROOT99_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT99_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT99_CLR Bit Fields */ -#define CCM_TARGET_ROOT99_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT99_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT99_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT99_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT99_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT99_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT99_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT99_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT99_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT99_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT99_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT99_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT99_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT99_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT99_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT99_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT99_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT99_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT99_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_CLR_MUX_SHIFT))&CCM_TARGET_ROOT99_CLR_MUX_MASK) -#define CCM_TARGET_ROOT99_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT99_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT99_TOG Bit Fields */ -#define CCM_TARGET_ROOT99_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT99_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT99_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT99_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT99_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT99_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT99_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT99_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT99_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT99_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT99_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT99_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT99_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT99_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT99_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT99_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT99_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT99_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT99_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_TOG_MUX_SHIFT))&CCM_TARGET_ROOT99_TOG_MUX_MASK) -#define CCM_TARGET_ROOT99_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT99_TOG_ENABLE_SHIFT 28 -/* POST99 Bit Fields */ -#define CCM_POST99_POST_PODF_MASK 0x3Fu -#define CCM_POST99_POST_PODF_SHIFT 0 -#define CCM_POST99_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST99_POST_PODF_SHIFT))&CCM_POST99_POST_PODF_MASK) -#define CCM_POST99_BUSY1_MASK 0x80u -#define CCM_POST99_BUSY1_SHIFT 7 -#define CCM_POST99_AUTO_PODF_MASK 0x700u -#define CCM_POST99_AUTO_PODF_SHIFT 8 -#define CCM_POST99_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST99_AUTO_PODF_SHIFT))&CCM_POST99_AUTO_PODF_MASK) -#define CCM_POST99_AUTO_EN_MASK 0x1000u -#define CCM_POST99_AUTO_EN_SHIFT 12 -#define CCM_POST99_SLOW_MASK 0x8000u -#define CCM_POST99_SLOW_SHIFT 15 -#define CCM_POST99_SELECT_MASK 0x10000000u -#define CCM_POST99_SELECT_SHIFT 28 -#define CCM_POST99_BUSY2_MASK 0x80000000u -#define CCM_POST99_BUSY2_SHIFT 31 -/* POST_ROOT99_SET Bit Fields */ -#define CCM_POST_ROOT99_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT99_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT99_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_SET_POST_PODF_SHIFT))&CCM_POST_ROOT99_SET_POST_PODF_MASK) -#define CCM_POST_ROOT99_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT99_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT99_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT99_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT99_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT99_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT99_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT99_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT99_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT99_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT99_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT99_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT99_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT99_SET_BUSY2_SHIFT 31 -/* POST_ROOT99_CLR Bit Fields */ -#define CCM_POST_ROOT99_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT99_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT99_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT99_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT99_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT99_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT99_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT99_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT99_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT99_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT99_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT99_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT99_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT99_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT99_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT99_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT99_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT99_CLR_BUSY2_SHIFT 31 -/* POST_ROOT99_TOG Bit Fields */ -#define CCM_POST_ROOT99_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT99_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT99_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT99_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT99_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT99_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT99_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT99_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT99_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT99_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT99_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT99_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT99_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT99_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT99_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT99_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT99_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT99_TOG_BUSY2_SHIFT 31 -/* PRE99 Bit Fields */ -#define CCM_PRE99_PRE_PODF_B_MASK 0x7u -#define CCM_PRE99_PRE_PODF_B_SHIFT 0 -#define CCM_PRE99_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE99_PRE_PODF_B_SHIFT))&CCM_PRE99_PRE_PODF_B_MASK) -#define CCM_PRE99_BUSY0_MASK 0x8u -#define CCM_PRE99_BUSY0_SHIFT 3 -#define CCM_PRE99_MUX_B_MASK 0x700u -#define CCM_PRE99_MUX_B_SHIFT 8 -#define CCM_PRE99_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE99_MUX_B_SHIFT))&CCM_PRE99_MUX_B_MASK) -#define CCM_PRE99_EN_B_MASK 0x1000u -#define CCM_PRE99_EN_B_SHIFT 12 -#define CCM_PRE99_BUSY1_MASK 0x8000u -#define CCM_PRE99_BUSY1_SHIFT 15 -#define CCM_PRE99_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE99_PRE_PODF_A_SHIFT 16 -#define CCM_PRE99_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE99_PRE_PODF_A_SHIFT))&CCM_PRE99_PRE_PODF_A_MASK) -#define CCM_PRE99_BUSY3_MASK 0x80000u -#define CCM_PRE99_BUSY3_SHIFT 19 -#define CCM_PRE99_MUX_A_MASK 0x7000000u -#define CCM_PRE99_MUX_A_SHIFT 24 -#define CCM_PRE99_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE99_MUX_A_SHIFT))&CCM_PRE99_MUX_A_MASK) -#define CCM_PRE99_EN_A_MASK 0x10000000u -#define CCM_PRE99_EN_A_SHIFT 28 -#define CCM_PRE99_BUSY4_MASK 0x80000000u -#define CCM_PRE99_BUSY4_SHIFT 31 -/* PRE_ROOT99_SET Bit Fields */ -#define CCM_PRE_ROOT99_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT99_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT99_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT99_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT99_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT99_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT99_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT99_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT99_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_SET_MUX_B_SHIFT))&CCM_PRE_ROOT99_SET_MUX_B_MASK) -#define CCM_PRE_ROOT99_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT99_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT99_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT99_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT99_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT99_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT99_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT99_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT99_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT99_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT99_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT99_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT99_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_SET_MUX_A_SHIFT))&CCM_PRE_ROOT99_SET_MUX_A_MASK) -#define CCM_PRE_ROOT99_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT99_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT99_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT99_SET_BUSY4_SHIFT 31 -/* PRE_ROOT99_CLR Bit Fields */ -#define CCM_PRE_ROOT99_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT99_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT99_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT99_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT99_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT99_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT99_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT99_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT99_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT99_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT99_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT99_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT99_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT99_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT99_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT99_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT99_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT99_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT99_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT99_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT99_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT99_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT99_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT99_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT99_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT99_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT99_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT99_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT99_TOG Bit Fields */ -#define CCM_PRE_ROOT99_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT99_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT99_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT99_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT99_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT99_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT99_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT99_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT99_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT99_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT99_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT99_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT99_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT99_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT99_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT99_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT99_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT99_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT99_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT99_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT99_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT99_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT99_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT99_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT99_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT99_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT99_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT99_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL99 Bit Fields */ -#define CCM_ACCESS_CTRL99_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL99_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL99_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL99_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL99_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL99_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL99_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL99_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL99_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL99_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL99_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL99_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL99_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL99_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL99_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL99_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL99_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL99_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL99_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL99_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL99_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL99_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL99_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL99_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL99_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL99_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL99_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL99_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL99_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL99_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL99_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL99_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL99_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL99_LOCK_SHIFT 31 -/* ACCESS_CTRL99_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL99_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL99_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL99_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL99_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL99_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL99_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL99_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL99_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL99_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL99_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL99_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL99_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL99_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL99_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL99_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL99_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT100 Bit Fields */ -#define CCM_TARGET_ROOT100_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT100_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT100_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_POST_PODF_SHIFT))&CCM_TARGET_ROOT100_POST_PODF_MASK) -#define CCM_TARGET_ROOT100_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT100_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT100_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT100_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT100_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT100_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT100_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT100_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT100_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT100_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT100_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_PRE_PODF_SHIFT))&CCM_TARGET_ROOT100_PRE_PODF_MASK) -#define CCM_TARGET_ROOT100_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT100_MUX_SHIFT 24 -#define CCM_TARGET_ROOT100_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_MUX_SHIFT))&CCM_TARGET_ROOT100_MUX_MASK) -#define CCM_TARGET_ROOT100_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT100_ENABLE_SHIFT 28 -/* TARGET_ROOT100_SET Bit Fields */ -#define CCM_TARGET_ROOT100_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT100_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT100_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT100_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT100_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT100_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT100_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT100_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT100_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT100_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT100_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT100_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT100_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT100_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT100_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT100_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT100_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT100_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT100_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_SET_MUX_SHIFT))&CCM_TARGET_ROOT100_SET_MUX_MASK) -#define CCM_TARGET_ROOT100_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT100_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT100_CLR Bit Fields */ -#define CCM_TARGET_ROOT100_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT100_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT100_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT100_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT100_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT100_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT100_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT100_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT100_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT100_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT100_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT100_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT100_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT100_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT100_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT100_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT100_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT100_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT100_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_CLR_MUX_SHIFT))&CCM_TARGET_ROOT100_CLR_MUX_MASK) -#define CCM_TARGET_ROOT100_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT100_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT100_TOG Bit Fields */ -#define CCM_TARGET_ROOT100_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT100_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT100_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT100_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT100_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT100_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT100_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT100_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT100_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT100_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT100_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT100_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT100_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT100_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT100_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT100_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT100_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT100_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT100_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_TOG_MUX_SHIFT))&CCM_TARGET_ROOT100_TOG_MUX_MASK) -#define CCM_TARGET_ROOT100_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT100_TOG_ENABLE_SHIFT 28 -/* POST100 Bit Fields */ -#define CCM_POST100_POST_PODF_MASK 0x3Fu -#define CCM_POST100_POST_PODF_SHIFT 0 -#define CCM_POST100_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST100_POST_PODF_SHIFT))&CCM_POST100_POST_PODF_MASK) -#define CCM_POST100_BUSY1_MASK 0x80u -#define CCM_POST100_BUSY1_SHIFT 7 -#define CCM_POST100_AUTO_PODF_MASK 0x700u -#define CCM_POST100_AUTO_PODF_SHIFT 8 -#define CCM_POST100_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST100_AUTO_PODF_SHIFT))&CCM_POST100_AUTO_PODF_MASK) -#define CCM_POST100_AUTO_EN_MASK 0x1000u -#define CCM_POST100_AUTO_EN_SHIFT 12 -#define CCM_POST100_SLOW_MASK 0x8000u -#define CCM_POST100_SLOW_SHIFT 15 -#define CCM_POST100_SELECT_MASK 0x10000000u -#define CCM_POST100_SELECT_SHIFT 28 -#define CCM_POST100_BUSY2_MASK 0x80000000u -#define CCM_POST100_BUSY2_SHIFT 31 -/* POST_ROOT100_SET Bit Fields */ -#define CCM_POST_ROOT100_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT100_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT100_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_SET_POST_PODF_SHIFT))&CCM_POST_ROOT100_SET_POST_PODF_MASK) -#define CCM_POST_ROOT100_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT100_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT100_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT100_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT100_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT100_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT100_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT100_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT100_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT100_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT100_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT100_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT100_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT100_SET_BUSY2_SHIFT 31 -/* POST_ROOT100_CLR Bit Fields */ -#define CCM_POST_ROOT100_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT100_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT100_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT100_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT100_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT100_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT100_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT100_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT100_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT100_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT100_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT100_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT100_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT100_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT100_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT100_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT100_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT100_CLR_BUSY2_SHIFT 31 -/* POST_ROOT100_TOG Bit Fields */ -#define CCM_POST_ROOT100_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT100_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT100_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT100_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT100_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT100_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT100_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT100_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT100_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT100_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT100_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT100_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT100_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT100_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT100_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT100_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT100_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT100_TOG_BUSY2_SHIFT 31 -/* PRE100 Bit Fields */ -#define CCM_PRE100_PRE_PODF_B_MASK 0x7u -#define CCM_PRE100_PRE_PODF_B_SHIFT 0 -#define CCM_PRE100_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE100_PRE_PODF_B_SHIFT))&CCM_PRE100_PRE_PODF_B_MASK) -#define CCM_PRE100_BUSY0_MASK 0x8u -#define CCM_PRE100_BUSY0_SHIFT 3 -#define CCM_PRE100_MUX_B_MASK 0x700u -#define CCM_PRE100_MUX_B_SHIFT 8 -#define CCM_PRE100_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE100_MUX_B_SHIFT))&CCM_PRE100_MUX_B_MASK) -#define CCM_PRE100_EN_B_MASK 0x1000u -#define CCM_PRE100_EN_B_SHIFT 12 -#define CCM_PRE100_BUSY1_MASK 0x8000u -#define CCM_PRE100_BUSY1_SHIFT 15 -#define CCM_PRE100_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE100_PRE_PODF_A_SHIFT 16 -#define CCM_PRE100_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE100_PRE_PODF_A_SHIFT))&CCM_PRE100_PRE_PODF_A_MASK) -#define CCM_PRE100_BUSY3_MASK 0x80000u -#define CCM_PRE100_BUSY3_SHIFT 19 -#define CCM_PRE100_MUX_A_MASK 0x7000000u -#define CCM_PRE100_MUX_A_SHIFT 24 -#define CCM_PRE100_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE100_MUX_A_SHIFT))&CCM_PRE100_MUX_A_MASK) -#define CCM_PRE100_EN_A_MASK 0x10000000u -#define CCM_PRE100_EN_A_SHIFT 28 -#define CCM_PRE100_BUSY4_MASK 0x80000000u -#define CCM_PRE100_BUSY4_SHIFT 31 -/* PRE_ROOT100_SET Bit Fields */ -#define CCM_PRE_ROOT100_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT100_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT100_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT100_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT100_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT100_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT100_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT100_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT100_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_SET_MUX_B_SHIFT))&CCM_PRE_ROOT100_SET_MUX_B_MASK) -#define CCM_PRE_ROOT100_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT100_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT100_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT100_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT100_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT100_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT100_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT100_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT100_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT100_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT100_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT100_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT100_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_SET_MUX_A_SHIFT))&CCM_PRE_ROOT100_SET_MUX_A_MASK) -#define CCM_PRE_ROOT100_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT100_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT100_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT100_SET_BUSY4_SHIFT 31 -/* PRE_ROOT100_CLR Bit Fields */ -#define CCM_PRE_ROOT100_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT100_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT100_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT100_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT100_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT100_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT100_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT100_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT100_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT100_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT100_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT100_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT100_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT100_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT100_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT100_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT100_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT100_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT100_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT100_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT100_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT100_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT100_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT100_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT100_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT100_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT100_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT100_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT100_TOG Bit Fields */ -#define CCM_PRE_ROOT100_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT100_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT100_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT100_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT100_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT100_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT100_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT100_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT100_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT100_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT100_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT100_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT100_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT100_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT100_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT100_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT100_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT100_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT100_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT100_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT100_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT100_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT100_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT100_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT100_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT100_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT100_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT100_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL100 Bit Fields */ -#define CCM_ACCESS_CTRL100_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL100_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL100_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL100_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL100_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL100_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL100_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL100_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL100_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL100_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL100_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL100_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL100_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL100_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL100_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL100_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL100_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL100_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL100_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL100_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL100_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL100_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL100_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL100_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL100_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL100_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL100_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL100_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL100_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL100_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL100_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL100_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL100_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL100_LOCK_SHIFT 31 -/* ACCESS_CTRL100_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL100_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL100_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL100_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL100_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL100_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL100_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL100_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL100_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL100_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL100_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL100_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL100_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL100_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL100_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL100_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL100_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT101 Bit Fields */ -#define CCM_TARGET_ROOT101_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT101_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT101_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_POST_PODF_SHIFT))&CCM_TARGET_ROOT101_POST_PODF_MASK) -#define CCM_TARGET_ROOT101_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT101_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT101_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT101_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT101_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT101_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT101_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT101_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT101_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT101_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT101_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_PRE_PODF_SHIFT))&CCM_TARGET_ROOT101_PRE_PODF_MASK) -#define CCM_TARGET_ROOT101_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT101_MUX_SHIFT 24 -#define CCM_TARGET_ROOT101_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_MUX_SHIFT))&CCM_TARGET_ROOT101_MUX_MASK) -#define CCM_TARGET_ROOT101_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT101_ENABLE_SHIFT 28 -/* TARGET_ROOT101_SET Bit Fields */ -#define CCM_TARGET_ROOT101_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT101_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT101_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT101_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT101_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT101_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT101_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT101_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT101_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT101_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT101_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT101_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT101_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT101_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT101_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT101_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT101_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT101_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT101_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_SET_MUX_SHIFT))&CCM_TARGET_ROOT101_SET_MUX_MASK) -#define CCM_TARGET_ROOT101_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT101_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT101_CLR Bit Fields */ -#define CCM_TARGET_ROOT101_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT101_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT101_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT101_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT101_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT101_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT101_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT101_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT101_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT101_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT101_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT101_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT101_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT101_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT101_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT101_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT101_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT101_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT101_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_CLR_MUX_SHIFT))&CCM_TARGET_ROOT101_CLR_MUX_MASK) -#define CCM_TARGET_ROOT101_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT101_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT101_TOG Bit Fields */ -#define CCM_TARGET_ROOT101_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT101_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT101_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT101_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT101_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT101_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT101_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT101_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT101_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT101_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT101_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT101_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT101_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT101_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT101_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT101_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT101_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT101_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT101_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_TOG_MUX_SHIFT))&CCM_TARGET_ROOT101_TOG_MUX_MASK) -#define CCM_TARGET_ROOT101_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT101_TOG_ENABLE_SHIFT 28 -/* POST101 Bit Fields */ -#define CCM_POST101_POST_PODF_MASK 0x3Fu -#define CCM_POST101_POST_PODF_SHIFT 0 -#define CCM_POST101_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST101_POST_PODF_SHIFT))&CCM_POST101_POST_PODF_MASK) -#define CCM_POST101_BUSY1_MASK 0x80u -#define CCM_POST101_BUSY1_SHIFT 7 -#define CCM_POST101_AUTO_PODF_MASK 0x700u -#define CCM_POST101_AUTO_PODF_SHIFT 8 -#define CCM_POST101_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST101_AUTO_PODF_SHIFT))&CCM_POST101_AUTO_PODF_MASK) -#define CCM_POST101_AUTO_EN_MASK 0x1000u -#define CCM_POST101_AUTO_EN_SHIFT 12 -#define CCM_POST101_SLOW_MASK 0x8000u -#define CCM_POST101_SLOW_SHIFT 15 -#define CCM_POST101_SELECT_MASK 0x10000000u -#define CCM_POST101_SELECT_SHIFT 28 -#define CCM_POST101_BUSY2_MASK 0x80000000u -#define CCM_POST101_BUSY2_SHIFT 31 -/* POST_ROOT101_SET Bit Fields */ -#define CCM_POST_ROOT101_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT101_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT101_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_SET_POST_PODF_SHIFT))&CCM_POST_ROOT101_SET_POST_PODF_MASK) -#define CCM_POST_ROOT101_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT101_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT101_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT101_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT101_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT101_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT101_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT101_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT101_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT101_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT101_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT101_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT101_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT101_SET_BUSY2_SHIFT 31 -/* POST_ROOT101_CLR Bit Fields */ -#define CCM_POST_ROOT101_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT101_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT101_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT101_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT101_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT101_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT101_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT101_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT101_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT101_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT101_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT101_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT101_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT101_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT101_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT101_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT101_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT101_CLR_BUSY2_SHIFT 31 -/* POST_ROOT101_TOG Bit Fields */ -#define CCM_POST_ROOT101_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT101_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT101_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT101_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT101_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT101_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT101_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT101_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT101_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT101_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT101_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT101_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT101_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT101_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT101_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT101_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT101_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT101_TOG_BUSY2_SHIFT 31 -/* PRE101 Bit Fields */ -#define CCM_PRE101_PRE_PODF_B_MASK 0x7u -#define CCM_PRE101_PRE_PODF_B_SHIFT 0 -#define CCM_PRE101_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE101_PRE_PODF_B_SHIFT))&CCM_PRE101_PRE_PODF_B_MASK) -#define CCM_PRE101_BUSY0_MASK 0x8u -#define CCM_PRE101_BUSY0_SHIFT 3 -#define CCM_PRE101_MUX_B_MASK 0x700u -#define CCM_PRE101_MUX_B_SHIFT 8 -#define CCM_PRE101_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE101_MUX_B_SHIFT))&CCM_PRE101_MUX_B_MASK) -#define CCM_PRE101_EN_B_MASK 0x1000u -#define CCM_PRE101_EN_B_SHIFT 12 -#define CCM_PRE101_BUSY1_MASK 0x8000u -#define CCM_PRE101_BUSY1_SHIFT 15 -#define CCM_PRE101_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE101_PRE_PODF_A_SHIFT 16 -#define CCM_PRE101_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE101_PRE_PODF_A_SHIFT))&CCM_PRE101_PRE_PODF_A_MASK) -#define CCM_PRE101_BUSY3_MASK 0x80000u -#define CCM_PRE101_BUSY3_SHIFT 19 -#define CCM_PRE101_MUX_A_MASK 0x7000000u -#define CCM_PRE101_MUX_A_SHIFT 24 -#define CCM_PRE101_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE101_MUX_A_SHIFT))&CCM_PRE101_MUX_A_MASK) -#define CCM_PRE101_EN_A_MASK 0x10000000u -#define CCM_PRE101_EN_A_SHIFT 28 -#define CCM_PRE101_BUSY4_MASK 0x80000000u -#define CCM_PRE101_BUSY4_SHIFT 31 -/* PRE_ROOT101_SET Bit Fields */ -#define CCM_PRE_ROOT101_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT101_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT101_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT101_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT101_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT101_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT101_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT101_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT101_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_SET_MUX_B_SHIFT))&CCM_PRE_ROOT101_SET_MUX_B_MASK) -#define CCM_PRE_ROOT101_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT101_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT101_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT101_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT101_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT101_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT101_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT101_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT101_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT101_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT101_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT101_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT101_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_SET_MUX_A_SHIFT))&CCM_PRE_ROOT101_SET_MUX_A_MASK) -#define CCM_PRE_ROOT101_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT101_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT101_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT101_SET_BUSY4_SHIFT 31 -/* PRE_ROOT101_CLR Bit Fields */ -#define CCM_PRE_ROOT101_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT101_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT101_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT101_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT101_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT101_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT101_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT101_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT101_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT101_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT101_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT101_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT101_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT101_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT101_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT101_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT101_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT101_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT101_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT101_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT101_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT101_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT101_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT101_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT101_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT101_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT101_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT101_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT101_TOG Bit Fields */ -#define CCM_PRE_ROOT101_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT101_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT101_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT101_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT101_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT101_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT101_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT101_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT101_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT101_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT101_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT101_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT101_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT101_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT101_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT101_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT101_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT101_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT101_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT101_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT101_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT101_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT101_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT101_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT101_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT101_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT101_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT101_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL101 Bit Fields */ -#define CCM_ACCESS_CTRL101_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL101_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL101_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL101_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL101_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL101_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL101_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL101_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL101_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL101_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL101_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL101_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL101_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL101_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL101_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL101_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL101_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL101_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL101_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL101_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL101_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL101_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL101_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL101_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL101_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL101_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL101_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL101_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL101_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL101_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL101_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL101_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL101_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL101_LOCK_SHIFT 31 -/* ACCESS_CTRL101_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL101_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL101_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL101_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL101_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL101_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL101_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL101_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL101_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL101_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL101_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL101_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL101_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL101_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL101_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL101_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL101_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT102 Bit Fields */ -#define CCM_TARGET_ROOT102_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT102_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT102_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_POST_PODF_SHIFT))&CCM_TARGET_ROOT102_POST_PODF_MASK) -#define CCM_TARGET_ROOT102_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT102_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT102_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT102_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT102_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT102_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT102_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT102_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT102_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT102_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT102_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_PRE_PODF_SHIFT))&CCM_TARGET_ROOT102_PRE_PODF_MASK) -#define CCM_TARGET_ROOT102_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT102_MUX_SHIFT 24 -#define CCM_TARGET_ROOT102_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_MUX_SHIFT))&CCM_TARGET_ROOT102_MUX_MASK) -#define CCM_TARGET_ROOT102_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT102_ENABLE_SHIFT 28 -/* TARGET_ROOT102_SET Bit Fields */ -#define CCM_TARGET_ROOT102_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT102_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT102_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT102_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT102_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT102_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT102_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT102_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT102_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT102_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT102_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT102_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT102_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT102_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT102_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT102_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT102_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT102_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT102_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_SET_MUX_SHIFT))&CCM_TARGET_ROOT102_SET_MUX_MASK) -#define CCM_TARGET_ROOT102_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT102_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT102_CLR Bit Fields */ -#define CCM_TARGET_ROOT102_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT102_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT102_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT102_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT102_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT102_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT102_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT102_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT102_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT102_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT102_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT102_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT102_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT102_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT102_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT102_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT102_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT102_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT102_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_CLR_MUX_SHIFT))&CCM_TARGET_ROOT102_CLR_MUX_MASK) -#define CCM_TARGET_ROOT102_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT102_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT102_TOG Bit Fields */ -#define CCM_TARGET_ROOT102_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT102_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT102_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT102_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT102_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT102_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT102_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT102_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT102_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT102_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT102_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT102_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT102_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT102_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT102_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT102_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT102_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT102_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT102_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_TOG_MUX_SHIFT))&CCM_TARGET_ROOT102_TOG_MUX_MASK) -#define CCM_TARGET_ROOT102_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT102_TOG_ENABLE_SHIFT 28 -/* POST102 Bit Fields */ -#define CCM_POST102_POST_PODF_MASK 0x3Fu -#define CCM_POST102_POST_PODF_SHIFT 0 -#define CCM_POST102_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST102_POST_PODF_SHIFT))&CCM_POST102_POST_PODF_MASK) -#define CCM_POST102_BUSY1_MASK 0x80u -#define CCM_POST102_BUSY1_SHIFT 7 -#define CCM_POST102_AUTO_PODF_MASK 0x700u -#define CCM_POST102_AUTO_PODF_SHIFT 8 -#define CCM_POST102_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST102_AUTO_PODF_SHIFT))&CCM_POST102_AUTO_PODF_MASK) -#define CCM_POST102_AUTO_EN_MASK 0x1000u -#define CCM_POST102_AUTO_EN_SHIFT 12 -#define CCM_POST102_SLOW_MASK 0x8000u -#define CCM_POST102_SLOW_SHIFT 15 -#define CCM_POST102_SELECT_MASK 0x10000000u -#define CCM_POST102_SELECT_SHIFT 28 -#define CCM_POST102_BUSY2_MASK 0x80000000u -#define CCM_POST102_BUSY2_SHIFT 31 -/* POST_ROOT102_SET Bit Fields */ -#define CCM_POST_ROOT102_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT102_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT102_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_SET_POST_PODF_SHIFT))&CCM_POST_ROOT102_SET_POST_PODF_MASK) -#define CCM_POST_ROOT102_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT102_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT102_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT102_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT102_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT102_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT102_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT102_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT102_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT102_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT102_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT102_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT102_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT102_SET_BUSY2_SHIFT 31 -/* POST_ROOT102_CLR Bit Fields */ -#define CCM_POST_ROOT102_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT102_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT102_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT102_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT102_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT102_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT102_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT102_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT102_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT102_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT102_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT102_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT102_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT102_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT102_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT102_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT102_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT102_CLR_BUSY2_SHIFT 31 -/* POST_ROOT102_TOG Bit Fields */ -#define CCM_POST_ROOT102_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT102_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT102_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT102_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT102_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT102_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT102_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT102_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT102_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT102_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT102_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT102_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT102_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT102_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT102_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT102_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT102_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT102_TOG_BUSY2_SHIFT 31 -/* PRE102 Bit Fields */ -#define CCM_PRE102_PRE_PODF_B_MASK 0x7u -#define CCM_PRE102_PRE_PODF_B_SHIFT 0 -#define CCM_PRE102_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE102_PRE_PODF_B_SHIFT))&CCM_PRE102_PRE_PODF_B_MASK) -#define CCM_PRE102_BUSY0_MASK 0x8u -#define CCM_PRE102_BUSY0_SHIFT 3 -#define CCM_PRE102_MUX_B_MASK 0x700u -#define CCM_PRE102_MUX_B_SHIFT 8 -#define CCM_PRE102_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE102_MUX_B_SHIFT))&CCM_PRE102_MUX_B_MASK) -#define CCM_PRE102_EN_B_MASK 0x1000u -#define CCM_PRE102_EN_B_SHIFT 12 -#define CCM_PRE102_BUSY1_MASK 0x8000u -#define CCM_PRE102_BUSY1_SHIFT 15 -#define CCM_PRE102_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE102_PRE_PODF_A_SHIFT 16 -#define CCM_PRE102_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE102_PRE_PODF_A_SHIFT))&CCM_PRE102_PRE_PODF_A_MASK) -#define CCM_PRE102_BUSY3_MASK 0x80000u -#define CCM_PRE102_BUSY3_SHIFT 19 -#define CCM_PRE102_MUX_A_MASK 0x7000000u -#define CCM_PRE102_MUX_A_SHIFT 24 -#define CCM_PRE102_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE102_MUX_A_SHIFT))&CCM_PRE102_MUX_A_MASK) -#define CCM_PRE102_EN_A_MASK 0x10000000u -#define CCM_PRE102_EN_A_SHIFT 28 -#define CCM_PRE102_BUSY4_MASK 0x80000000u -#define CCM_PRE102_BUSY4_SHIFT 31 -/* PRE_ROOT102_SET Bit Fields */ -#define CCM_PRE_ROOT102_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT102_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT102_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT102_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT102_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT102_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT102_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT102_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT102_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_SET_MUX_B_SHIFT))&CCM_PRE_ROOT102_SET_MUX_B_MASK) -#define CCM_PRE_ROOT102_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT102_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT102_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT102_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT102_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT102_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT102_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT102_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT102_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT102_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT102_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT102_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT102_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_SET_MUX_A_SHIFT))&CCM_PRE_ROOT102_SET_MUX_A_MASK) -#define CCM_PRE_ROOT102_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT102_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT102_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT102_SET_BUSY4_SHIFT 31 -/* PRE_ROOT102_CLR Bit Fields */ -#define CCM_PRE_ROOT102_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT102_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT102_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT102_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT102_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT102_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT102_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT102_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT102_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT102_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT102_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT102_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT102_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT102_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT102_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT102_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT102_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT102_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT102_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT102_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT102_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT102_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT102_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT102_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT102_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT102_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT102_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT102_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT102_TOG Bit Fields */ -#define CCM_PRE_ROOT102_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT102_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT102_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT102_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT102_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT102_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT102_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT102_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT102_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT102_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT102_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT102_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT102_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT102_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT102_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT102_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT102_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT102_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT102_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT102_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT102_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT102_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT102_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT102_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT102_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT102_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT102_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT102_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL102 Bit Fields */ -#define CCM_ACCESS_CTRL102_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL102_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL102_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL102_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL102_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL102_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL102_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL102_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL102_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL102_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL102_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL102_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL102_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL102_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL102_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL102_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL102_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL102_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL102_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL102_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL102_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL102_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL102_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL102_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL102_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL102_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL102_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL102_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL102_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL102_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL102_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL102_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL102_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL102_LOCK_SHIFT 31 -/* ACCESS_CTRL102_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL102_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL102_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL102_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL102_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL102_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL102_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL102_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL102_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL102_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL102_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL102_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL102_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL102_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL102_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL102_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL102_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT103 Bit Fields */ -#define CCM_TARGET_ROOT103_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT103_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT103_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_POST_PODF_SHIFT))&CCM_TARGET_ROOT103_POST_PODF_MASK) -#define CCM_TARGET_ROOT103_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT103_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT103_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT103_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT103_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT103_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT103_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT103_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT103_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT103_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT103_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_PRE_PODF_SHIFT))&CCM_TARGET_ROOT103_PRE_PODF_MASK) -#define CCM_TARGET_ROOT103_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT103_MUX_SHIFT 24 -#define CCM_TARGET_ROOT103_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_MUX_SHIFT))&CCM_TARGET_ROOT103_MUX_MASK) -#define CCM_TARGET_ROOT103_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT103_ENABLE_SHIFT 28 -/* TARGET_ROOT103_SET Bit Fields */ -#define CCM_TARGET_ROOT103_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT103_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT103_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT103_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT103_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT103_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT103_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT103_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT103_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT103_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT103_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT103_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT103_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT103_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT103_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT103_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT103_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT103_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT103_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_SET_MUX_SHIFT))&CCM_TARGET_ROOT103_SET_MUX_MASK) -#define CCM_TARGET_ROOT103_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT103_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT103_CLR Bit Fields */ -#define CCM_TARGET_ROOT103_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT103_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT103_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT103_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT103_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT103_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT103_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT103_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT103_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT103_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT103_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT103_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT103_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT103_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT103_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT103_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT103_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT103_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT103_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_CLR_MUX_SHIFT))&CCM_TARGET_ROOT103_CLR_MUX_MASK) -#define CCM_TARGET_ROOT103_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT103_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT103_TOG Bit Fields */ -#define CCM_TARGET_ROOT103_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT103_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT103_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT103_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT103_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT103_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT103_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT103_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT103_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT103_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT103_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT103_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT103_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT103_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT103_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT103_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT103_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT103_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT103_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_TOG_MUX_SHIFT))&CCM_TARGET_ROOT103_TOG_MUX_MASK) -#define CCM_TARGET_ROOT103_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT103_TOG_ENABLE_SHIFT 28 -/* POST103 Bit Fields */ -#define CCM_POST103_POST_PODF_MASK 0x3Fu -#define CCM_POST103_POST_PODF_SHIFT 0 -#define CCM_POST103_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST103_POST_PODF_SHIFT))&CCM_POST103_POST_PODF_MASK) -#define CCM_POST103_BUSY1_MASK 0x80u -#define CCM_POST103_BUSY1_SHIFT 7 -#define CCM_POST103_AUTO_PODF_MASK 0x700u -#define CCM_POST103_AUTO_PODF_SHIFT 8 -#define CCM_POST103_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST103_AUTO_PODF_SHIFT))&CCM_POST103_AUTO_PODF_MASK) -#define CCM_POST103_AUTO_EN_MASK 0x1000u -#define CCM_POST103_AUTO_EN_SHIFT 12 -#define CCM_POST103_SLOW_MASK 0x8000u -#define CCM_POST103_SLOW_SHIFT 15 -#define CCM_POST103_SELECT_MASK 0x10000000u -#define CCM_POST103_SELECT_SHIFT 28 -#define CCM_POST103_BUSY2_MASK 0x80000000u -#define CCM_POST103_BUSY2_SHIFT 31 -/* POST_ROOT103_SET Bit Fields */ -#define CCM_POST_ROOT103_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT103_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT103_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_SET_POST_PODF_SHIFT))&CCM_POST_ROOT103_SET_POST_PODF_MASK) -#define CCM_POST_ROOT103_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT103_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT103_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT103_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT103_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT103_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT103_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT103_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT103_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT103_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT103_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT103_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT103_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT103_SET_BUSY2_SHIFT 31 -/* POST_ROOT103_CLR Bit Fields */ -#define CCM_POST_ROOT103_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT103_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT103_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT103_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT103_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT103_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT103_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT103_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT103_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT103_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT103_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT103_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT103_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT103_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT103_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT103_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT103_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT103_CLR_BUSY2_SHIFT 31 -/* POST_ROOT103_TOG Bit Fields */ -#define CCM_POST_ROOT103_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT103_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT103_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT103_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT103_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT103_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT103_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT103_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT103_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT103_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT103_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT103_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT103_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT103_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT103_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT103_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT103_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT103_TOG_BUSY2_SHIFT 31 -/* PRE103 Bit Fields */ -#define CCM_PRE103_PRE_PODF_B_MASK 0x7u -#define CCM_PRE103_PRE_PODF_B_SHIFT 0 -#define CCM_PRE103_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE103_PRE_PODF_B_SHIFT))&CCM_PRE103_PRE_PODF_B_MASK) -#define CCM_PRE103_BUSY0_MASK 0x8u -#define CCM_PRE103_BUSY0_SHIFT 3 -#define CCM_PRE103_MUX_B_MASK 0x700u -#define CCM_PRE103_MUX_B_SHIFT 8 -#define CCM_PRE103_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE103_MUX_B_SHIFT))&CCM_PRE103_MUX_B_MASK) -#define CCM_PRE103_EN_B_MASK 0x1000u -#define CCM_PRE103_EN_B_SHIFT 12 -#define CCM_PRE103_BUSY1_MASK 0x8000u -#define CCM_PRE103_BUSY1_SHIFT 15 -#define CCM_PRE103_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE103_PRE_PODF_A_SHIFT 16 -#define CCM_PRE103_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE103_PRE_PODF_A_SHIFT))&CCM_PRE103_PRE_PODF_A_MASK) -#define CCM_PRE103_BUSY3_MASK 0x80000u -#define CCM_PRE103_BUSY3_SHIFT 19 -#define CCM_PRE103_MUX_A_MASK 0x7000000u -#define CCM_PRE103_MUX_A_SHIFT 24 -#define CCM_PRE103_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE103_MUX_A_SHIFT))&CCM_PRE103_MUX_A_MASK) -#define CCM_PRE103_EN_A_MASK 0x10000000u -#define CCM_PRE103_EN_A_SHIFT 28 -#define CCM_PRE103_BUSY4_MASK 0x80000000u -#define CCM_PRE103_BUSY4_SHIFT 31 -/* PRE_ROOT103_SET Bit Fields */ -#define CCM_PRE_ROOT103_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT103_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT103_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT103_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT103_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT103_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT103_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT103_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT103_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_SET_MUX_B_SHIFT))&CCM_PRE_ROOT103_SET_MUX_B_MASK) -#define CCM_PRE_ROOT103_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT103_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT103_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT103_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT103_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT103_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT103_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT103_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT103_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT103_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT103_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT103_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT103_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_SET_MUX_A_SHIFT))&CCM_PRE_ROOT103_SET_MUX_A_MASK) -#define CCM_PRE_ROOT103_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT103_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT103_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT103_SET_BUSY4_SHIFT 31 -/* PRE_ROOT103_CLR Bit Fields */ -#define CCM_PRE_ROOT103_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT103_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT103_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT103_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT103_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT103_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT103_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT103_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT103_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT103_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT103_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT103_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT103_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT103_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT103_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT103_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT103_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT103_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT103_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT103_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT103_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT103_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT103_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT103_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT103_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT103_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT103_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT103_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT103_TOG Bit Fields */ -#define CCM_PRE_ROOT103_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT103_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT103_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT103_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT103_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT103_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT103_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT103_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT103_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT103_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT103_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT103_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT103_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT103_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT103_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT103_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT103_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT103_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT103_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT103_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT103_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT103_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT103_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT103_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT103_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT103_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT103_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT103_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL103 Bit Fields */ -#define CCM_ACCESS_CTRL103_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL103_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL103_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL103_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL103_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL103_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL103_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL103_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL103_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL103_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL103_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL103_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL103_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL103_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL103_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL103_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL103_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL103_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL103_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL103_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL103_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL103_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL103_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL103_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL103_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL103_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL103_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL103_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL103_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL103_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL103_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL103_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL103_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL103_LOCK_SHIFT 31 -/* ACCESS_CTRL103_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL103_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL103_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL103_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL103_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL103_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL103_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL103_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL103_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL103_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL103_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL103_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL103_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL103_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL103_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL103_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL103_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT104 Bit Fields */ -#define CCM_TARGET_ROOT104_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT104_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT104_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_POST_PODF_SHIFT))&CCM_TARGET_ROOT104_POST_PODF_MASK) -#define CCM_TARGET_ROOT104_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT104_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT104_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT104_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT104_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT104_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT104_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT104_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT104_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT104_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT104_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_PRE_PODF_SHIFT))&CCM_TARGET_ROOT104_PRE_PODF_MASK) -#define CCM_TARGET_ROOT104_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT104_MUX_SHIFT 24 -#define CCM_TARGET_ROOT104_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_MUX_SHIFT))&CCM_TARGET_ROOT104_MUX_MASK) -#define CCM_TARGET_ROOT104_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT104_ENABLE_SHIFT 28 -/* TARGET_ROOT104_SET Bit Fields */ -#define CCM_TARGET_ROOT104_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT104_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT104_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT104_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT104_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT104_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT104_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT104_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT104_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT104_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT104_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT104_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT104_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT104_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT104_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT104_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT104_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT104_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT104_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_SET_MUX_SHIFT))&CCM_TARGET_ROOT104_SET_MUX_MASK) -#define CCM_TARGET_ROOT104_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT104_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT104_CLR Bit Fields */ -#define CCM_TARGET_ROOT104_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT104_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT104_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT104_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT104_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT104_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT104_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT104_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT104_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT104_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT104_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT104_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT104_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT104_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT104_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT104_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT104_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT104_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT104_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_CLR_MUX_SHIFT))&CCM_TARGET_ROOT104_CLR_MUX_MASK) -#define CCM_TARGET_ROOT104_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT104_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT104_TOG Bit Fields */ -#define CCM_TARGET_ROOT104_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT104_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT104_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT104_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT104_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT104_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT104_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT104_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT104_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT104_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT104_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT104_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT104_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT104_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT104_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT104_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT104_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT104_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT104_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_TOG_MUX_SHIFT))&CCM_TARGET_ROOT104_TOG_MUX_MASK) -#define CCM_TARGET_ROOT104_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT104_TOG_ENABLE_SHIFT 28 -/* POST104 Bit Fields */ -#define CCM_POST104_POST_PODF_MASK 0x3Fu -#define CCM_POST104_POST_PODF_SHIFT 0 -#define CCM_POST104_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST104_POST_PODF_SHIFT))&CCM_POST104_POST_PODF_MASK) -#define CCM_POST104_BUSY1_MASK 0x80u -#define CCM_POST104_BUSY1_SHIFT 7 -#define CCM_POST104_AUTO_PODF_MASK 0x700u -#define CCM_POST104_AUTO_PODF_SHIFT 8 -#define CCM_POST104_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST104_AUTO_PODF_SHIFT))&CCM_POST104_AUTO_PODF_MASK) -#define CCM_POST104_AUTO_EN_MASK 0x1000u -#define CCM_POST104_AUTO_EN_SHIFT 12 -#define CCM_POST104_SLOW_MASK 0x8000u -#define CCM_POST104_SLOW_SHIFT 15 -#define CCM_POST104_SELECT_MASK 0x10000000u -#define CCM_POST104_SELECT_SHIFT 28 -#define CCM_POST104_BUSY2_MASK 0x80000000u -#define CCM_POST104_BUSY2_SHIFT 31 -/* POST_ROOT104_SET Bit Fields */ -#define CCM_POST_ROOT104_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT104_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT104_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_SET_POST_PODF_SHIFT))&CCM_POST_ROOT104_SET_POST_PODF_MASK) -#define CCM_POST_ROOT104_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT104_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT104_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT104_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT104_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT104_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT104_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT104_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT104_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT104_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT104_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT104_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT104_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT104_SET_BUSY2_SHIFT 31 -/* POST_ROOT104_CLR Bit Fields */ -#define CCM_POST_ROOT104_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT104_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT104_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT104_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT104_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT104_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT104_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT104_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT104_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT104_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT104_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT104_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT104_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT104_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT104_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT104_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT104_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT104_CLR_BUSY2_SHIFT 31 -/* POST_ROOT104_TOG Bit Fields */ -#define CCM_POST_ROOT104_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT104_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT104_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT104_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT104_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT104_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT104_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT104_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT104_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT104_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT104_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT104_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT104_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT104_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT104_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT104_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT104_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT104_TOG_BUSY2_SHIFT 31 -/* PRE104 Bit Fields */ -#define CCM_PRE104_PRE_PODF_B_MASK 0x7u -#define CCM_PRE104_PRE_PODF_B_SHIFT 0 -#define CCM_PRE104_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE104_PRE_PODF_B_SHIFT))&CCM_PRE104_PRE_PODF_B_MASK) -#define CCM_PRE104_BUSY0_MASK 0x8u -#define CCM_PRE104_BUSY0_SHIFT 3 -#define CCM_PRE104_MUX_B_MASK 0x700u -#define CCM_PRE104_MUX_B_SHIFT 8 -#define CCM_PRE104_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE104_MUX_B_SHIFT))&CCM_PRE104_MUX_B_MASK) -#define CCM_PRE104_EN_B_MASK 0x1000u -#define CCM_PRE104_EN_B_SHIFT 12 -#define CCM_PRE104_BUSY1_MASK 0x8000u -#define CCM_PRE104_BUSY1_SHIFT 15 -#define CCM_PRE104_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE104_PRE_PODF_A_SHIFT 16 -#define CCM_PRE104_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE104_PRE_PODF_A_SHIFT))&CCM_PRE104_PRE_PODF_A_MASK) -#define CCM_PRE104_BUSY3_MASK 0x80000u -#define CCM_PRE104_BUSY3_SHIFT 19 -#define CCM_PRE104_MUX_A_MASK 0x7000000u -#define CCM_PRE104_MUX_A_SHIFT 24 -#define CCM_PRE104_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE104_MUX_A_SHIFT))&CCM_PRE104_MUX_A_MASK) -#define CCM_PRE104_EN_A_MASK 0x10000000u -#define CCM_PRE104_EN_A_SHIFT 28 -#define CCM_PRE104_BUSY4_MASK 0x80000000u -#define CCM_PRE104_BUSY4_SHIFT 31 -/* PRE_ROOT104_SET Bit Fields */ -#define CCM_PRE_ROOT104_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT104_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT104_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT104_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT104_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT104_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT104_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT104_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT104_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_SET_MUX_B_SHIFT))&CCM_PRE_ROOT104_SET_MUX_B_MASK) -#define CCM_PRE_ROOT104_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT104_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT104_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT104_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT104_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT104_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT104_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT104_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT104_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT104_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT104_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT104_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT104_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_SET_MUX_A_SHIFT))&CCM_PRE_ROOT104_SET_MUX_A_MASK) -#define CCM_PRE_ROOT104_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT104_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT104_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT104_SET_BUSY4_SHIFT 31 -/* PRE_ROOT104_CLR Bit Fields */ -#define CCM_PRE_ROOT104_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT104_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT104_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT104_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT104_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT104_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT104_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT104_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT104_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT104_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT104_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT104_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT104_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT104_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT104_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT104_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT104_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT104_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT104_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT104_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT104_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT104_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT104_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT104_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT104_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT104_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT104_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT104_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT104_TOG Bit Fields */ -#define CCM_PRE_ROOT104_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT104_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT104_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT104_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT104_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT104_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT104_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT104_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT104_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT104_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT104_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT104_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT104_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT104_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT104_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT104_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT104_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT104_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT104_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT104_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT104_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT104_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT104_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT104_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT104_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT104_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT104_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT104_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL104 Bit Fields */ -#define CCM_ACCESS_CTRL104_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL104_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL104_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL104_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL104_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL104_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL104_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL104_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL104_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL104_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL104_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL104_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL104_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL104_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL104_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL104_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL104_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL104_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL104_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL104_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL104_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL104_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL104_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL104_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL104_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL104_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL104_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL104_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL104_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL104_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL104_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL104_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL104_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL104_LOCK_SHIFT 31 -/* ACCESS_CTRL104_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL104_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL104_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL104_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL104_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL104_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL104_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL104_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL104_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL104_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL104_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL104_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL104_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL104_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL104_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL104_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL104_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT105 Bit Fields */ -#define CCM_TARGET_ROOT105_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT105_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT105_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_POST_PODF_SHIFT))&CCM_TARGET_ROOT105_POST_PODF_MASK) -#define CCM_TARGET_ROOT105_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT105_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT105_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT105_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT105_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT105_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT105_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT105_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT105_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT105_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT105_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_PRE_PODF_SHIFT))&CCM_TARGET_ROOT105_PRE_PODF_MASK) -#define CCM_TARGET_ROOT105_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT105_MUX_SHIFT 24 -#define CCM_TARGET_ROOT105_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_MUX_SHIFT))&CCM_TARGET_ROOT105_MUX_MASK) -#define CCM_TARGET_ROOT105_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT105_ENABLE_SHIFT 28 -/* TARGET_ROOT105_SET Bit Fields */ -#define CCM_TARGET_ROOT105_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT105_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT105_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT105_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT105_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT105_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT105_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT105_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT105_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT105_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT105_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT105_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT105_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT105_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT105_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT105_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT105_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT105_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT105_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_SET_MUX_SHIFT))&CCM_TARGET_ROOT105_SET_MUX_MASK) -#define CCM_TARGET_ROOT105_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT105_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT105_CLR Bit Fields */ -#define CCM_TARGET_ROOT105_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT105_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT105_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT105_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT105_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT105_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT105_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT105_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT105_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT105_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT105_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT105_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT105_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT105_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT105_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT105_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT105_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT105_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT105_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_CLR_MUX_SHIFT))&CCM_TARGET_ROOT105_CLR_MUX_MASK) -#define CCM_TARGET_ROOT105_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT105_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT105_TOG Bit Fields */ -#define CCM_TARGET_ROOT105_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT105_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT105_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT105_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT105_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT105_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT105_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT105_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT105_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT105_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT105_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT105_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT105_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT105_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT105_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT105_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT105_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT105_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT105_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_TOG_MUX_SHIFT))&CCM_TARGET_ROOT105_TOG_MUX_MASK) -#define CCM_TARGET_ROOT105_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT105_TOG_ENABLE_SHIFT 28 -/* POST105 Bit Fields */ -#define CCM_POST105_POST_PODF_MASK 0x3Fu -#define CCM_POST105_POST_PODF_SHIFT 0 -#define CCM_POST105_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST105_POST_PODF_SHIFT))&CCM_POST105_POST_PODF_MASK) -#define CCM_POST105_BUSY1_MASK 0x80u -#define CCM_POST105_BUSY1_SHIFT 7 -#define CCM_POST105_AUTO_PODF_MASK 0x700u -#define CCM_POST105_AUTO_PODF_SHIFT 8 -#define CCM_POST105_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST105_AUTO_PODF_SHIFT))&CCM_POST105_AUTO_PODF_MASK) -#define CCM_POST105_AUTO_EN_MASK 0x1000u -#define CCM_POST105_AUTO_EN_SHIFT 12 -#define CCM_POST105_SLOW_MASK 0x8000u -#define CCM_POST105_SLOW_SHIFT 15 -#define CCM_POST105_SELECT_MASK 0x10000000u -#define CCM_POST105_SELECT_SHIFT 28 -#define CCM_POST105_BUSY2_MASK 0x80000000u -#define CCM_POST105_BUSY2_SHIFT 31 -/* POST_ROOT105_SET Bit Fields */ -#define CCM_POST_ROOT105_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT105_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT105_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_SET_POST_PODF_SHIFT))&CCM_POST_ROOT105_SET_POST_PODF_MASK) -#define CCM_POST_ROOT105_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT105_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT105_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT105_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT105_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT105_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT105_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT105_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT105_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT105_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT105_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT105_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT105_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT105_SET_BUSY2_SHIFT 31 -/* POST_ROOT105_CLR Bit Fields */ -#define CCM_POST_ROOT105_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT105_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT105_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT105_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT105_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT105_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT105_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT105_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT105_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT105_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT105_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT105_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT105_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT105_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT105_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT105_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT105_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT105_CLR_BUSY2_SHIFT 31 -/* POST_ROOT105_TOG Bit Fields */ -#define CCM_POST_ROOT105_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT105_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT105_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT105_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT105_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT105_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT105_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT105_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT105_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT105_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT105_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT105_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT105_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT105_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT105_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT105_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT105_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT105_TOG_BUSY2_SHIFT 31 -/* PRE105 Bit Fields */ -#define CCM_PRE105_PRE_PODF_B_MASK 0x7u -#define CCM_PRE105_PRE_PODF_B_SHIFT 0 -#define CCM_PRE105_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE105_PRE_PODF_B_SHIFT))&CCM_PRE105_PRE_PODF_B_MASK) -#define CCM_PRE105_BUSY0_MASK 0x8u -#define CCM_PRE105_BUSY0_SHIFT 3 -#define CCM_PRE105_MUX_B_MASK 0x700u -#define CCM_PRE105_MUX_B_SHIFT 8 -#define CCM_PRE105_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE105_MUX_B_SHIFT))&CCM_PRE105_MUX_B_MASK) -#define CCM_PRE105_EN_B_MASK 0x1000u -#define CCM_PRE105_EN_B_SHIFT 12 -#define CCM_PRE105_BUSY1_MASK 0x8000u -#define CCM_PRE105_BUSY1_SHIFT 15 -#define CCM_PRE105_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE105_PRE_PODF_A_SHIFT 16 -#define CCM_PRE105_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE105_PRE_PODF_A_SHIFT))&CCM_PRE105_PRE_PODF_A_MASK) -#define CCM_PRE105_BUSY3_MASK 0x80000u -#define CCM_PRE105_BUSY3_SHIFT 19 -#define CCM_PRE105_MUX_A_MASK 0x7000000u -#define CCM_PRE105_MUX_A_SHIFT 24 -#define CCM_PRE105_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE105_MUX_A_SHIFT))&CCM_PRE105_MUX_A_MASK) -#define CCM_PRE105_EN_A_MASK 0x10000000u -#define CCM_PRE105_EN_A_SHIFT 28 -#define CCM_PRE105_BUSY4_MASK 0x80000000u -#define CCM_PRE105_BUSY4_SHIFT 31 -/* PRE_ROOT105_SET Bit Fields */ -#define CCM_PRE_ROOT105_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT105_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT105_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT105_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT105_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT105_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT105_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT105_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT105_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_SET_MUX_B_SHIFT))&CCM_PRE_ROOT105_SET_MUX_B_MASK) -#define CCM_PRE_ROOT105_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT105_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT105_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT105_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT105_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT105_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT105_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT105_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT105_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT105_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT105_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT105_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT105_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_SET_MUX_A_SHIFT))&CCM_PRE_ROOT105_SET_MUX_A_MASK) -#define CCM_PRE_ROOT105_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT105_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT105_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT105_SET_BUSY4_SHIFT 31 -/* PRE_ROOT105_CLR Bit Fields */ -#define CCM_PRE_ROOT105_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT105_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT105_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT105_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT105_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT105_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT105_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT105_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT105_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT105_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT105_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT105_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT105_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT105_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT105_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT105_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT105_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT105_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT105_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT105_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT105_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT105_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT105_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT105_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT105_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT105_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT105_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT105_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT105_TOG Bit Fields */ -#define CCM_PRE_ROOT105_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT105_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT105_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT105_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT105_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT105_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT105_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT105_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT105_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT105_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT105_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT105_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT105_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT105_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT105_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT105_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT105_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT105_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT105_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT105_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT105_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT105_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT105_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT105_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT105_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT105_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT105_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT105_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL105 Bit Fields */ -#define CCM_ACCESS_CTRL105_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL105_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL105_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL105_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL105_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL105_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL105_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL105_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL105_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL105_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL105_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL105_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL105_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL105_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL105_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL105_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL105_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL105_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL105_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL105_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL105_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL105_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL105_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL105_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL105_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL105_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL105_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL105_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL105_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL105_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL105_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL105_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL105_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL105_LOCK_SHIFT 31 -/* ACCESS_CTRL105_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL105_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL105_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL105_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL105_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL105_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL105_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL105_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL105_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL105_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL105_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL105_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL105_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL105_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL105_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL105_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL105_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT106 Bit Fields */ -#define CCM_TARGET_ROOT106_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT106_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT106_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_POST_PODF_SHIFT))&CCM_TARGET_ROOT106_POST_PODF_MASK) -#define CCM_TARGET_ROOT106_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT106_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT106_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT106_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT106_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT106_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT106_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT106_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT106_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT106_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT106_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_PRE_PODF_SHIFT))&CCM_TARGET_ROOT106_PRE_PODF_MASK) -#define CCM_TARGET_ROOT106_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT106_MUX_SHIFT 24 -#define CCM_TARGET_ROOT106_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_MUX_SHIFT))&CCM_TARGET_ROOT106_MUX_MASK) -#define CCM_TARGET_ROOT106_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT106_ENABLE_SHIFT 28 -/* TARGET_ROOT106_SET Bit Fields */ -#define CCM_TARGET_ROOT106_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT106_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT106_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT106_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT106_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT106_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT106_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT106_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT106_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT106_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT106_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT106_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT106_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT106_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT106_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT106_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT106_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT106_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT106_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_SET_MUX_SHIFT))&CCM_TARGET_ROOT106_SET_MUX_MASK) -#define CCM_TARGET_ROOT106_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT106_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT106_CLR Bit Fields */ -#define CCM_TARGET_ROOT106_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT106_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT106_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT106_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT106_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT106_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT106_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT106_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT106_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT106_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT106_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT106_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT106_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT106_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT106_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT106_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT106_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT106_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT106_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_CLR_MUX_SHIFT))&CCM_TARGET_ROOT106_CLR_MUX_MASK) -#define CCM_TARGET_ROOT106_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT106_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT106_TOG Bit Fields */ -#define CCM_TARGET_ROOT106_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT106_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT106_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT106_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT106_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT106_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT106_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT106_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT106_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT106_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT106_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT106_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT106_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT106_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT106_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT106_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT106_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT106_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT106_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_TOG_MUX_SHIFT))&CCM_TARGET_ROOT106_TOG_MUX_MASK) -#define CCM_TARGET_ROOT106_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT106_TOG_ENABLE_SHIFT 28 -/* POST106 Bit Fields */ -#define CCM_POST106_POST_PODF_MASK 0x3Fu -#define CCM_POST106_POST_PODF_SHIFT 0 -#define CCM_POST106_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST106_POST_PODF_SHIFT))&CCM_POST106_POST_PODF_MASK) -#define CCM_POST106_BUSY1_MASK 0x80u -#define CCM_POST106_BUSY1_SHIFT 7 -#define CCM_POST106_AUTO_PODF_MASK 0x700u -#define CCM_POST106_AUTO_PODF_SHIFT 8 -#define CCM_POST106_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST106_AUTO_PODF_SHIFT))&CCM_POST106_AUTO_PODF_MASK) -#define CCM_POST106_AUTO_EN_MASK 0x1000u -#define CCM_POST106_AUTO_EN_SHIFT 12 -#define CCM_POST106_SLOW_MASK 0x8000u -#define CCM_POST106_SLOW_SHIFT 15 -#define CCM_POST106_SELECT_MASK 0x10000000u -#define CCM_POST106_SELECT_SHIFT 28 -#define CCM_POST106_BUSY2_MASK 0x80000000u -#define CCM_POST106_BUSY2_SHIFT 31 -/* POST_ROOT106_SET Bit Fields */ -#define CCM_POST_ROOT106_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT106_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT106_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_SET_POST_PODF_SHIFT))&CCM_POST_ROOT106_SET_POST_PODF_MASK) -#define CCM_POST_ROOT106_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT106_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT106_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT106_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT106_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT106_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT106_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT106_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT106_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT106_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT106_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT106_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT106_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT106_SET_BUSY2_SHIFT 31 -/* POST_ROOT106_CLR Bit Fields */ -#define CCM_POST_ROOT106_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT106_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT106_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT106_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT106_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT106_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT106_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT106_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT106_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT106_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT106_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT106_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT106_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT106_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT106_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT106_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT106_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT106_CLR_BUSY2_SHIFT 31 -/* POST_ROOT106_TOG Bit Fields */ -#define CCM_POST_ROOT106_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT106_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT106_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT106_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT106_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT106_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT106_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT106_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT106_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT106_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT106_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT106_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT106_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT106_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT106_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT106_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT106_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT106_TOG_BUSY2_SHIFT 31 -/* PRE106 Bit Fields */ -#define CCM_PRE106_PRE_PODF_B_MASK 0x7u -#define CCM_PRE106_PRE_PODF_B_SHIFT 0 -#define CCM_PRE106_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE106_PRE_PODF_B_SHIFT))&CCM_PRE106_PRE_PODF_B_MASK) -#define CCM_PRE106_BUSY0_MASK 0x8u -#define CCM_PRE106_BUSY0_SHIFT 3 -#define CCM_PRE106_MUX_B_MASK 0x700u -#define CCM_PRE106_MUX_B_SHIFT 8 -#define CCM_PRE106_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE106_MUX_B_SHIFT))&CCM_PRE106_MUX_B_MASK) -#define CCM_PRE106_EN_B_MASK 0x1000u -#define CCM_PRE106_EN_B_SHIFT 12 -#define CCM_PRE106_BUSY1_MASK 0x8000u -#define CCM_PRE106_BUSY1_SHIFT 15 -#define CCM_PRE106_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE106_PRE_PODF_A_SHIFT 16 -#define CCM_PRE106_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE106_PRE_PODF_A_SHIFT))&CCM_PRE106_PRE_PODF_A_MASK) -#define CCM_PRE106_BUSY3_MASK 0x80000u -#define CCM_PRE106_BUSY3_SHIFT 19 -#define CCM_PRE106_MUX_A_MASK 0x7000000u -#define CCM_PRE106_MUX_A_SHIFT 24 -#define CCM_PRE106_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE106_MUX_A_SHIFT))&CCM_PRE106_MUX_A_MASK) -#define CCM_PRE106_EN_A_MASK 0x10000000u -#define CCM_PRE106_EN_A_SHIFT 28 -#define CCM_PRE106_BUSY4_MASK 0x80000000u -#define CCM_PRE106_BUSY4_SHIFT 31 -/* PRE_ROOT106_SET Bit Fields */ -#define CCM_PRE_ROOT106_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT106_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT106_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT106_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT106_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT106_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT106_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT106_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT106_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_SET_MUX_B_SHIFT))&CCM_PRE_ROOT106_SET_MUX_B_MASK) -#define CCM_PRE_ROOT106_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT106_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT106_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT106_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT106_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT106_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT106_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT106_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT106_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT106_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT106_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT106_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT106_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_SET_MUX_A_SHIFT))&CCM_PRE_ROOT106_SET_MUX_A_MASK) -#define CCM_PRE_ROOT106_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT106_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT106_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT106_SET_BUSY4_SHIFT 31 -/* PRE_ROOT106_CLR Bit Fields */ -#define CCM_PRE_ROOT106_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT106_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT106_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT106_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT106_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT106_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT106_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT106_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT106_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT106_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT106_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT106_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT106_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT106_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT106_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT106_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT106_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT106_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT106_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT106_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT106_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT106_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT106_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT106_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT106_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT106_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT106_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT106_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT106_TOG Bit Fields */ -#define CCM_PRE_ROOT106_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT106_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT106_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT106_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT106_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT106_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT106_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT106_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT106_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT106_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT106_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT106_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT106_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT106_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT106_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT106_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT106_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT106_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT106_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT106_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT106_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT106_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT106_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT106_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT106_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT106_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT106_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT106_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL106 Bit Fields */ -#define CCM_ACCESS_CTRL106_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL106_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL106_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL106_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL106_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL106_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL106_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL106_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL106_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL106_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL106_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL106_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL106_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL106_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL106_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL106_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL106_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL106_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL106_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL106_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL106_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL106_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL106_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL106_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL106_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL106_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL106_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL106_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL106_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL106_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL106_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL106_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL106_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL106_LOCK_SHIFT 31 -/* ACCESS_CTRL106_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL106_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL106_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL106_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL106_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL106_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL106_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL106_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL106_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL106_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL106_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL106_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL106_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL106_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL106_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL106_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL106_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT107 Bit Fields */ -#define CCM_TARGET_ROOT107_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT107_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT107_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_POST_PODF_SHIFT))&CCM_TARGET_ROOT107_POST_PODF_MASK) -#define CCM_TARGET_ROOT107_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT107_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT107_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT107_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT107_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT107_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT107_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT107_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT107_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT107_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT107_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_PRE_PODF_SHIFT))&CCM_TARGET_ROOT107_PRE_PODF_MASK) -#define CCM_TARGET_ROOT107_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT107_MUX_SHIFT 24 -#define CCM_TARGET_ROOT107_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_MUX_SHIFT))&CCM_TARGET_ROOT107_MUX_MASK) -#define CCM_TARGET_ROOT107_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT107_ENABLE_SHIFT 28 -/* TARGET_ROOT107_SET Bit Fields */ -#define CCM_TARGET_ROOT107_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT107_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT107_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT107_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT107_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT107_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT107_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT107_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT107_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT107_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT107_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT107_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT107_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT107_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT107_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT107_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT107_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT107_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT107_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_SET_MUX_SHIFT))&CCM_TARGET_ROOT107_SET_MUX_MASK) -#define CCM_TARGET_ROOT107_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT107_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT107_CLR Bit Fields */ -#define CCM_TARGET_ROOT107_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT107_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT107_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT107_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT107_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT107_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT107_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT107_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT107_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT107_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT107_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT107_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT107_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT107_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT107_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT107_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT107_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT107_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT107_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_CLR_MUX_SHIFT))&CCM_TARGET_ROOT107_CLR_MUX_MASK) -#define CCM_TARGET_ROOT107_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT107_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT107_TOG Bit Fields */ -#define CCM_TARGET_ROOT107_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT107_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT107_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT107_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT107_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT107_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT107_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT107_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT107_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT107_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT107_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT107_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT107_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT107_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT107_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT107_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT107_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT107_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT107_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_TOG_MUX_SHIFT))&CCM_TARGET_ROOT107_TOG_MUX_MASK) -#define CCM_TARGET_ROOT107_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT107_TOG_ENABLE_SHIFT 28 -/* POST107 Bit Fields */ -#define CCM_POST107_POST_PODF_MASK 0x3Fu -#define CCM_POST107_POST_PODF_SHIFT 0 -#define CCM_POST107_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST107_POST_PODF_SHIFT))&CCM_POST107_POST_PODF_MASK) -#define CCM_POST107_BUSY1_MASK 0x80u -#define CCM_POST107_BUSY1_SHIFT 7 -#define CCM_POST107_AUTO_PODF_MASK 0x700u -#define CCM_POST107_AUTO_PODF_SHIFT 8 -#define CCM_POST107_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST107_AUTO_PODF_SHIFT))&CCM_POST107_AUTO_PODF_MASK) -#define CCM_POST107_AUTO_EN_MASK 0x1000u -#define CCM_POST107_AUTO_EN_SHIFT 12 -#define CCM_POST107_SLOW_MASK 0x8000u -#define CCM_POST107_SLOW_SHIFT 15 -#define CCM_POST107_SELECT_MASK 0x10000000u -#define CCM_POST107_SELECT_SHIFT 28 -#define CCM_POST107_BUSY2_MASK 0x80000000u -#define CCM_POST107_BUSY2_SHIFT 31 -/* POST_ROOT107_SET Bit Fields */ -#define CCM_POST_ROOT107_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT107_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT107_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_SET_POST_PODF_SHIFT))&CCM_POST_ROOT107_SET_POST_PODF_MASK) -#define CCM_POST_ROOT107_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT107_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT107_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT107_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT107_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT107_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT107_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT107_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT107_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT107_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT107_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT107_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT107_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT107_SET_BUSY2_SHIFT 31 -/* POST_ROOT107_CLR Bit Fields */ -#define CCM_POST_ROOT107_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT107_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT107_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT107_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT107_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT107_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT107_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT107_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT107_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT107_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT107_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT107_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT107_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT107_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT107_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT107_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT107_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT107_CLR_BUSY2_SHIFT 31 -/* POST_ROOT107_TOG Bit Fields */ -#define CCM_POST_ROOT107_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT107_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT107_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT107_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT107_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT107_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT107_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT107_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT107_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT107_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT107_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT107_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT107_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT107_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT107_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT107_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT107_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT107_TOG_BUSY2_SHIFT 31 -/* PRE107 Bit Fields */ -#define CCM_PRE107_PRE_PODF_B_MASK 0x7u -#define CCM_PRE107_PRE_PODF_B_SHIFT 0 -#define CCM_PRE107_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE107_PRE_PODF_B_SHIFT))&CCM_PRE107_PRE_PODF_B_MASK) -#define CCM_PRE107_BUSY0_MASK 0x8u -#define CCM_PRE107_BUSY0_SHIFT 3 -#define CCM_PRE107_MUX_B_MASK 0x700u -#define CCM_PRE107_MUX_B_SHIFT 8 -#define CCM_PRE107_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE107_MUX_B_SHIFT))&CCM_PRE107_MUX_B_MASK) -#define CCM_PRE107_EN_B_MASK 0x1000u -#define CCM_PRE107_EN_B_SHIFT 12 -#define CCM_PRE107_BUSY1_MASK 0x8000u -#define CCM_PRE107_BUSY1_SHIFT 15 -#define CCM_PRE107_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE107_PRE_PODF_A_SHIFT 16 -#define CCM_PRE107_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE107_PRE_PODF_A_SHIFT))&CCM_PRE107_PRE_PODF_A_MASK) -#define CCM_PRE107_BUSY3_MASK 0x80000u -#define CCM_PRE107_BUSY3_SHIFT 19 -#define CCM_PRE107_MUX_A_MASK 0x7000000u -#define CCM_PRE107_MUX_A_SHIFT 24 -#define CCM_PRE107_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE107_MUX_A_SHIFT))&CCM_PRE107_MUX_A_MASK) -#define CCM_PRE107_EN_A_MASK 0x10000000u -#define CCM_PRE107_EN_A_SHIFT 28 -#define CCM_PRE107_BUSY4_MASK 0x80000000u -#define CCM_PRE107_BUSY4_SHIFT 31 -/* PRE_ROOT107_SET Bit Fields */ -#define CCM_PRE_ROOT107_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT107_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT107_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT107_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT107_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT107_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT107_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT107_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT107_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_SET_MUX_B_SHIFT))&CCM_PRE_ROOT107_SET_MUX_B_MASK) -#define CCM_PRE_ROOT107_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT107_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT107_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT107_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT107_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT107_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT107_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT107_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT107_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT107_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT107_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT107_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT107_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_SET_MUX_A_SHIFT))&CCM_PRE_ROOT107_SET_MUX_A_MASK) -#define CCM_PRE_ROOT107_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT107_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT107_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT107_SET_BUSY4_SHIFT 31 -/* PRE_ROOT107_CLR Bit Fields */ -#define CCM_PRE_ROOT107_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT107_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT107_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT107_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT107_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT107_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT107_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT107_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT107_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT107_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT107_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT107_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT107_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT107_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT107_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT107_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT107_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT107_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT107_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT107_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT107_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT107_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT107_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT107_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT107_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT107_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT107_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT107_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT107_TOG Bit Fields */ -#define CCM_PRE_ROOT107_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT107_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT107_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT107_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT107_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT107_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT107_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT107_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT107_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT107_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT107_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT107_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT107_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT107_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT107_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT107_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT107_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT107_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT107_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT107_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT107_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT107_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT107_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT107_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT107_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT107_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT107_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT107_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL107 Bit Fields */ -#define CCM_ACCESS_CTRL107_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL107_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL107_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL107_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL107_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL107_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL107_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL107_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL107_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL107_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL107_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL107_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL107_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL107_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL107_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL107_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL107_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL107_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL107_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL107_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL107_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL107_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL107_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL107_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL107_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL107_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL107_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL107_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL107_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL107_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL107_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL107_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL107_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL107_LOCK_SHIFT 31 -/* ACCESS_CTRL107_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL107_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL107_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL107_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL107_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL107_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL107_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL107_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL107_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL107_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL107_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL107_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL107_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL107_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL107_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL107_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL107_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT108 Bit Fields */ -#define CCM_TARGET_ROOT108_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT108_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT108_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_POST_PODF_SHIFT))&CCM_TARGET_ROOT108_POST_PODF_MASK) -#define CCM_TARGET_ROOT108_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT108_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT108_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT108_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT108_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT108_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT108_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT108_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT108_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT108_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT108_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_PRE_PODF_SHIFT))&CCM_TARGET_ROOT108_PRE_PODF_MASK) -#define CCM_TARGET_ROOT108_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT108_MUX_SHIFT 24 -#define CCM_TARGET_ROOT108_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_MUX_SHIFT))&CCM_TARGET_ROOT108_MUX_MASK) -#define CCM_TARGET_ROOT108_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT108_ENABLE_SHIFT 28 -/* TARGET_ROOT108_SET Bit Fields */ -#define CCM_TARGET_ROOT108_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT108_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT108_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT108_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT108_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT108_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT108_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT108_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT108_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT108_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT108_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT108_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT108_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT108_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT108_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT108_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT108_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT108_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT108_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_SET_MUX_SHIFT))&CCM_TARGET_ROOT108_SET_MUX_MASK) -#define CCM_TARGET_ROOT108_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT108_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT108_CLR Bit Fields */ -#define CCM_TARGET_ROOT108_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT108_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT108_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT108_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT108_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT108_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT108_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT108_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT108_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT108_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT108_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT108_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT108_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT108_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT108_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT108_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT108_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT108_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT108_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_CLR_MUX_SHIFT))&CCM_TARGET_ROOT108_CLR_MUX_MASK) -#define CCM_TARGET_ROOT108_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT108_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT108_TOG Bit Fields */ -#define CCM_TARGET_ROOT108_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT108_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT108_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT108_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT108_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT108_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT108_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT108_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT108_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT108_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT108_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT108_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT108_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT108_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT108_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT108_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT108_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT108_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT108_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_TOG_MUX_SHIFT))&CCM_TARGET_ROOT108_TOG_MUX_MASK) -#define CCM_TARGET_ROOT108_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT108_TOG_ENABLE_SHIFT 28 -/* POST108 Bit Fields */ -#define CCM_POST108_POST_PODF_MASK 0x3Fu -#define CCM_POST108_POST_PODF_SHIFT 0 -#define CCM_POST108_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST108_POST_PODF_SHIFT))&CCM_POST108_POST_PODF_MASK) -#define CCM_POST108_BUSY1_MASK 0x80u -#define CCM_POST108_BUSY1_SHIFT 7 -#define CCM_POST108_AUTO_PODF_MASK 0x700u -#define CCM_POST108_AUTO_PODF_SHIFT 8 -#define CCM_POST108_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST108_AUTO_PODF_SHIFT))&CCM_POST108_AUTO_PODF_MASK) -#define CCM_POST108_AUTO_EN_MASK 0x1000u -#define CCM_POST108_AUTO_EN_SHIFT 12 -#define CCM_POST108_SLOW_MASK 0x8000u -#define CCM_POST108_SLOW_SHIFT 15 -#define CCM_POST108_SELECT_MASK 0x10000000u -#define CCM_POST108_SELECT_SHIFT 28 -#define CCM_POST108_BUSY2_MASK 0x80000000u -#define CCM_POST108_BUSY2_SHIFT 31 -/* POST_ROOT108_SET Bit Fields */ -#define CCM_POST_ROOT108_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT108_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT108_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_SET_POST_PODF_SHIFT))&CCM_POST_ROOT108_SET_POST_PODF_MASK) -#define CCM_POST_ROOT108_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT108_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT108_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT108_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT108_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT108_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT108_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT108_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT108_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT108_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT108_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT108_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT108_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT108_SET_BUSY2_SHIFT 31 -/* POST_ROOT108_CLR Bit Fields */ -#define CCM_POST_ROOT108_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT108_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT108_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT108_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT108_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT108_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT108_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT108_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT108_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT108_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT108_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT108_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT108_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT108_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT108_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT108_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT108_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT108_CLR_BUSY2_SHIFT 31 -/* POST_ROOT108_TOG Bit Fields */ -#define CCM_POST_ROOT108_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT108_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT108_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT108_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT108_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT108_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT108_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT108_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT108_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT108_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT108_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT108_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT108_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT108_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT108_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT108_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT108_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT108_TOG_BUSY2_SHIFT 31 -/* PRE108 Bit Fields */ -#define CCM_PRE108_PRE_PODF_B_MASK 0x7u -#define CCM_PRE108_PRE_PODF_B_SHIFT 0 -#define CCM_PRE108_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE108_PRE_PODF_B_SHIFT))&CCM_PRE108_PRE_PODF_B_MASK) -#define CCM_PRE108_BUSY0_MASK 0x8u -#define CCM_PRE108_BUSY0_SHIFT 3 -#define CCM_PRE108_MUX_B_MASK 0x700u -#define CCM_PRE108_MUX_B_SHIFT 8 -#define CCM_PRE108_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE108_MUX_B_SHIFT))&CCM_PRE108_MUX_B_MASK) -#define CCM_PRE108_EN_B_MASK 0x1000u -#define CCM_PRE108_EN_B_SHIFT 12 -#define CCM_PRE108_BUSY1_MASK 0x8000u -#define CCM_PRE108_BUSY1_SHIFT 15 -#define CCM_PRE108_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE108_PRE_PODF_A_SHIFT 16 -#define CCM_PRE108_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE108_PRE_PODF_A_SHIFT))&CCM_PRE108_PRE_PODF_A_MASK) -#define CCM_PRE108_BUSY3_MASK 0x80000u -#define CCM_PRE108_BUSY3_SHIFT 19 -#define CCM_PRE108_MUX_A_MASK 0x7000000u -#define CCM_PRE108_MUX_A_SHIFT 24 -#define CCM_PRE108_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE108_MUX_A_SHIFT))&CCM_PRE108_MUX_A_MASK) -#define CCM_PRE108_EN_A_MASK 0x10000000u -#define CCM_PRE108_EN_A_SHIFT 28 -#define CCM_PRE108_BUSY4_MASK 0x80000000u -#define CCM_PRE108_BUSY4_SHIFT 31 -/* PRE_ROOT108_SET Bit Fields */ -#define CCM_PRE_ROOT108_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT108_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT108_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT108_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT108_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT108_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT108_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT108_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT108_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_SET_MUX_B_SHIFT))&CCM_PRE_ROOT108_SET_MUX_B_MASK) -#define CCM_PRE_ROOT108_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT108_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT108_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT108_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT108_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT108_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT108_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT108_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT108_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT108_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT108_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT108_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT108_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_SET_MUX_A_SHIFT))&CCM_PRE_ROOT108_SET_MUX_A_MASK) -#define CCM_PRE_ROOT108_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT108_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT108_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT108_SET_BUSY4_SHIFT 31 -/* PRE_ROOT108_CLR Bit Fields */ -#define CCM_PRE_ROOT108_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT108_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT108_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT108_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT108_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT108_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT108_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT108_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT108_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT108_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT108_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT108_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT108_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT108_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT108_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT108_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT108_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT108_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT108_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT108_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT108_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT108_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT108_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT108_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT108_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT108_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT108_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT108_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT108_TOG Bit Fields */ -#define CCM_PRE_ROOT108_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT108_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT108_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT108_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT108_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT108_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT108_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT108_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT108_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT108_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT108_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT108_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT108_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT108_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT108_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT108_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT108_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT108_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT108_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT108_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT108_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT108_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT108_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT108_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT108_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT108_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT108_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT108_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL108 Bit Fields */ -#define CCM_ACCESS_CTRL108_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL108_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL108_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL108_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL108_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL108_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL108_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL108_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL108_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL108_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL108_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL108_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL108_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL108_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL108_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL108_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL108_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL108_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL108_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL108_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL108_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL108_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL108_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL108_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL108_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL108_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL108_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL108_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL108_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL108_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL108_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL108_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL108_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL108_LOCK_SHIFT 31 -/* ACCESS_CTRL108_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL108_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL108_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL108_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL108_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL108_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL108_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL108_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL108_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL108_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL108_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL108_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL108_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL108_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL108_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL108_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL108_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT109 Bit Fields */ -#define CCM_TARGET_ROOT109_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT109_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT109_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_POST_PODF_SHIFT))&CCM_TARGET_ROOT109_POST_PODF_MASK) -#define CCM_TARGET_ROOT109_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT109_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT109_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT109_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT109_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT109_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT109_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT109_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT109_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT109_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT109_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_PRE_PODF_SHIFT))&CCM_TARGET_ROOT109_PRE_PODF_MASK) -#define CCM_TARGET_ROOT109_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT109_MUX_SHIFT 24 -#define CCM_TARGET_ROOT109_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_MUX_SHIFT))&CCM_TARGET_ROOT109_MUX_MASK) -#define CCM_TARGET_ROOT109_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT109_ENABLE_SHIFT 28 -/* TARGET_ROOT109_SET Bit Fields */ -#define CCM_TARGET_ROOT109_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT109_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT109_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT109_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT109_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT109_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT109_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT109_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT109_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT109_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT109_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT109_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT109_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT109_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT109_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT109_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT109_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT109_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT109_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_SET_MUX_SHIFT))&CCM_TARGET_ROOT109_SET_MUX_MASK) -#define CCM_TARGET_ROOT109_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT109_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT109_CLR Bit Fields */ -#define CCM_TARGET_ROOT109_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT109_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT109_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT109_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT109_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT109_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT109_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT109_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT109_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT109_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT109_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT109_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT109_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT109_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT109_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT109_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT109_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT109_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT109_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_CLR_MUX_SHIFT))&CCM_TARGET_ROOT109_CLR_MUX_MASK) -#define CCM_TARGET_ROOT109_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT109_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT109_TOG Bit Fields */ -#define CCM_TARGET_ROOT109_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT109_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT109_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT109_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT109_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT109_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT109_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT109_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT109_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT109_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT109_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT109_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT109_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT109_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT109_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT109_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT109_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT109_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT109_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_TOG_MUX_SHIFT))&CCM_TARGET_ROOT109_TOG_MUX_MASK) -#define CCM_TARGET_ROOT109_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT109_TOG_ENABLE_SHIFT 28 -/* POST109 Bit Fields */ -#define CCM_POST109_POST_PODF_MASK 0x3Fu -#define CCM_POST109_POST_PODF_SHIFT 0 -#define CCM_POST109_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST109_POST_PODF_SHIFT))&CCM_POST109_POST_PODF_MASK) -#define CCM_POST109_BUSY1_MASK 0x80u -#define CCM_POST109_BUSY1_SHIFT 7 -#define CCM_POST109_AUTO_PODF_MASK 0x700u -#define CCM_POST109_AUTO_PODF_SHIFT 8 -#define CCM_POST109_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST109_AUTO_PODF_SHIFT))&CCM_POST109_AUTO_PODF_MASK) -#define CCM_POST109_AUTO_EN_MASK 0x1000u -#define CCM_POST109_AUTO_EN_SHIFT 12 -#define CCM_POST109_SLOW_MASK 0x8000u -#define CCM_POST109_SLOW_SHIFT 15 -#define CCM_POST109_SELECT_MASK 0x10000000u -#define CCM_POST109_SELECT_SHIFT 28 -#define CCM_POST109_BUSY2_MASK 0x80000000u -#define CCM_POST109_BUSY2_SHIFT 31 -/* POST_ROOT109_SET Bit Fields */ -#define CCM_POST_ROOT109_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT109_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT109_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_SET_POST_PODF_SHIFT))&CCM_POST_ROOT109_SET_POST_PODF_MASK) -#define CCM_POST_ROOT109_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT109_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT109_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT109_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT109_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT109_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT109_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT109_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT109_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT109_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT109_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT109_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT109_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT109_SET_BUSY2_SHIFT 31 -/* POST_ROOT109_CLR Bit Fields */ -#define CCM_POST_ROOT109_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT109_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT109_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT109_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT109_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT109_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT109_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT109_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT109_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT109_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT109_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT109_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT109_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT109_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT109_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT109_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT109_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT109_CLR_BUSY2_SHIFT 31 -/* POST_ROOT109_TOG Bit Fields */ -#define CCM_POST_ROOT109_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT109_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT109_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT109_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT109_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT109_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT109_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT109_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT109_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT109_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT109_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT109_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT109_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT109_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT109_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT109_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT109_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT109_TOG_BUSY2_SHIFT 31 -/* PRE109 Bit Fields */ -#define CCM_PRE109_PRE_PODF_B_MASK 0x7u -#define CCM_PRE109_PRE_PODF_B_SHIFT 0 -#define CCM_PRE109_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE109_PRE_PODF_B_SHIFT))&CCM_PRE109_PRE_PODF_B_MASK) -#define CCM_PRE109_BUSY0_MASK 0x8u -#define CCM_PRE109_BUSY0_SHIFT 3 -#define CCM_PRE109_MUX_B_MASK 0x700u -#define CCM_PRE109_MUX_B_SHIFT 8 -#define CCM_PRE109_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE109_MUX_B_SHIFT))&CCM_PRE109_MUX_B_MASK) -#define CCM_PRE109_EN_B_MASK 0x1000u -#define CCM_PRE109_EN_B_SHIFT 12 -#define CCM_PRE109_BUSY1_MASK 0x8000u -#define CCM_PRE109_BUSY1_SHIFT 15 -#define CCM_PRE109_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE109_PRE_PODF_A_SHIFT 16 -#define CCM_PRE109_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE109_PRE_PODF_A_SHIFT))&CCM_PRE109_PRE_PODF_A_MASK) -#define CCM_PRE109_BUSY3_MASK 0x80000u -#define CCM_PRE109_BUSY3_SHIFT 19 -#define CCM_PRE109_MUX_A_MASK 0x7000000u -#define CCM_PRE109_MUX_A_SHIFT 24 -#define CCM_PRE109_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE109_MUX_A_SHIFT))&CCM_PRE109_MUX_A_MASK) -#define CCM_PRE109_EN_A_MASK 0x10000000u -#define CCM_PRE109_EN_A_SHIFT 28 -#define CCM_PRE109_BUSY4_MASK 0x80000000u -#define CCM_PRE109_BUSY4_SHIFT 31 -/* PRE_ROOT109_SET Bit Fields */ -#define CCM_PRE_ROOT109_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT109_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT109_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT109_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT109_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT109_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT109_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT109_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT109_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_SET_MUX_B_SHIFT))&CCM_PRE_ROOT109_SET_MUX_B_MASK) -#define CCM_PRE_ROOT109_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT109_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT109_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT109_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT109_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT109_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT109_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT109_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT109_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT109_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT109_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT109_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT109_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_SET_MUX_A_SHIFT))&CCM_PRE_ROOT109_SET_MUX_A_MASK) -#define CCM_PRE_ROOT109_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT109_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT109_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT109_SET_BUSY4_SHIFT 31 -/* PRE_ROOT109_CLR Bit Fields */ -#define CCM_PRE_ROOT109_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT109_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT109_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT109_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT109_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT109_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT109_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT109_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT109_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT109_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT109_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT109_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT109_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT109_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT109_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT109_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT109_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT109_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT109_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT109_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT109_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT109_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT109_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT109_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT109_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT109_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT109_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT109_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT109_TOG Bit Fields */ -#define CCM_PRE_ROOT109_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT109_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT109_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT109_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT109_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT109_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT109_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT109_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT109_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT109_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT109_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT109_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT109_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT109_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT109_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT109_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT109_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT109_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT109_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT109_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT109_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT109_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT109_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT109_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT109_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT109_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT109_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT109_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL109 Bit Fields */ -#define CCM_ACCESS_CTRL109_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL109_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL109_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL109_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL109_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL109_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL109_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL109_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL109_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL109_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL109_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL109_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL109_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL109_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL109_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL109_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL109_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL109_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL109_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL109_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL109_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL109_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL109_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL109_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL109_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL109_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL109_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL109_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL109_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL109_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL109_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL109_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL109_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL109_LOCK_SHIFT 31 -/* ACCESS_CTRL109_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL109_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL109_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL109_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL109_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL109_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL109_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL109_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL109_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL109_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL109_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL109_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL109_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL109_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL109_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL109_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL109_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT110 Bit Fields */ -#define CCM_TARGET_ROOT110_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT110_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT110_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_POST_PODF_SHIFT))&CCM_TARGET_ROOT110_POST_PODF_MASK) -#define CCM_TARGET_ROOT110_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT110_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT110_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT110_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT110_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT110_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT110_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT110_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT110_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT110_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT110_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_PRE_PODF_SHIFT))&CCM_TARGET_ROOT110_PRE_PODF_MASK) -#define CCM_TARGET_ROOT110_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT110_MUX_SHIFT 24 -#define CCM_TARGET_ROOT110_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_MUX_SHIFT))&CCM_TARGET_ROOT110_MUX_MASK) -#define CCM_TARGET_ROOT110_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT110_ENABLE_SHIFT 28 -/* TARGET_ROOT110_SET Bit Fields */ -#define CCM_TARGET_ROOT110_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT110_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT110_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT110_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT110_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT110_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT110_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT110_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT110_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT110_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT110_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT110_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT110_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT110_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT110_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT110_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT110_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT110_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT110_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_SET_MUX_SHIFT))&CCM_TARGET_ROOT110_SET_MUX_MASK) -#define CCM_TARGET_ROOT110_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT110_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT110_CLR Bit Fields */ -#define CCM_TARGET_ROOT110_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT110_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT110_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT110_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT110_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT110_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT110_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT110_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT110_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT110_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT110_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT110_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT110_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT110_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT110_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT110_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT110_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT110_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT110_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_CLR_MUX_SHIFT))&CCM_TARGET_ROOT110_CLR_MUX_MASK) -#define CCM_TARGET_ROOT110_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT110_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT110_TOG Bit Fields */ -#define CCM_TARGET_ROOT110_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT110_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT110_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT110_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT110_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT110_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT110_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT110_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT110_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT110_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT110_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT110_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT110_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT110_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT110_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT110_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT110_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT110_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT110_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_TOG_MUX_SHIFT))&CCM_TARGET_ROOT110_TOG_MUX_MASK) -#define CCM_TARGET_ROOT110_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT110_TOG_ENABLE_SHIFT 28 -/* POST110 Bit Fields */ -#define CCM_POST110_POST_PODF_MASK 0x3Fu -#define CCM_POST110_POST_PODF_SHIFT 0 -#define CCM_POST110_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST110_POST_PODF_SHIFT))&CCM_POST110_POST_PODF_MASK) -#define CCM_POST110_BUSY1_MASK 0x80u -#define CCM_POST110_BUSY1_SHIFT 7 -#define CCM_POST110_AUTO_PODF_MASK 0x700u -#define CCM_POST110_AUTO_PODF_SHIFT 8 -#define CCM_POST110_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST110_AUTO_PODF_SHIFT))&CCM_POST110_AUTO_PODF_MASK) -#define CCM_POST110_AUTO_EN_MASK 0x1000u -#define CCM_POST110_AUTO_EN_SHIFT 12 -#define CCM_POST110_SLOW_MASK 0x8000u -#define CCM_POST110_SLOW_SHIFT 15 -#define CCM_POST110_SELECT_MASK 0x10000000u -#define CCM_POST110_SELECT_SHIFT 28 -#define CCM_POST110_BUSY2_MASK 0x80000000u -#define CCM_POST110_BUSY2_SHIFT 31 -/* POST_ROOT110_SET Bit Fields */ -#define CCM_POST_ROOT110_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT110_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT110_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_SET_POST_PODF_SHIFT))&CCM_POST_ROOT110_SET_POST_PODF_MASK) -#define CCM_POST_ROOT110_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT110_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT110_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT110_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT110_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT110_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT110_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT110_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT110_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT110_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT110_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT110_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT110_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT110_SET_BUSY2_SHIFT 31 -/* POST_ROOT110_CLR Bit Fields */ -#define CCM_POST_ROOT110_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT110_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT110_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT110_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT110_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT110_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT110_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT110_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT110_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT110_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT110_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT110_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT110_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT110_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT110_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT110_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT110_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT110_CLR_BUSY2_SHIFT 31 -/* POST_ROOT110_TOG Bit Fields */ -#define CCM_POST_ROOT110_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT110_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT110_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT110_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT110_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT110_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT110_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT110_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT110_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT110_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT110_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT110_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT110_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT110_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT110_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT110_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT110_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT110_TOG_BUSY2_SHIFT 31 -/* PRE110 Bit Fields */ -#define CCM_PRE110_PRE_PODF_B_MASK 0x7u -#define CCM_PRE110_PRE_PODF_B_SHIFT 0 -#define CCM_PRE110_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE110_PRE_PODF_B_SHIFT))&CCM_PRE110_PRE_PODF_B_MASK) -#define CCM_PRE110_BUSY0_MASK 0x8u -#define CCM_PRE110_BUSY0_SHIFT 3 -#define CCM_PRE110_MUX_B_MASK 0x700u -#define CCM_PRE110_MUX_B_SHIFT 8 -#define CCM_PRE110_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE110_MUX_B_SHIFT))&CCM_PRE110_MUX_B_MASK) -#define CCM_PRE110_EN_B_MASK 0x1000u -#define CCM_PRE110_EN_B_SHIFT 12 -#define CCM_PRE110_BUSY1_MASK 0x8000u -#define CCM_PRE110_BUSY1_SHIFT 15 -#define CCM_PRE110_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE110_PRE_PODF_A_SHIFT 16 -#define CCM_PRE110_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE110_PRE_PODF_A_SHIFT))&CCM_PRE110_PRE_PODF_A_MASK) -#define CCM_PRE110_BUSY3_MASK 0x80000u -#define CCM_PRE110_BUSY3_SHIFT 19 -#define CCM_PRE110_MUX_A_MASK 0x7000000u -#define CCM_PRE110_MUX_A_SHIFT 24 -#define CCM_PRE110_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE110_MUX_A_SHIFT))&CCM_PRE110_MUX_A_MASK) -#define CCM_PRE110_EN_A_MASK 0x10000000u -#define CCM_PRE110_EN_A_SHIFT 28 -#define CCM_PRE110_BUSY4_MASK 0x80000000u -#define CCM_PRE110_BUSY4_SHIFT 31 -/* PRE_ROOT110_SET Bit Fields */ -#define CCM_PRE_ROOT110_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT110_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT110_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT110_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT110_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT110_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT110_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT110_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT110_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_SET_MUX_B_SHIFT))&CCM_PRE_ROOT110_SET_MUX_B_MASK) -#define CCM_PRE_ROOT110_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT110_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT110_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT110_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT110_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT110_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT110_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT110_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT110_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT110_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT110_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT110_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT110_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_SET_MUX_A_SHIFT))&CCM_PRE_ROOT110_SET_MUX_A_MASK) -#define CCM_PRE_ROOT110_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT110_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT110_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT110_SET_BUSY4_SHIFT 31 -/* PRE_ROOT110_CLR Bit Fields */ -#define CCM_PRE_ROOT110_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT110_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT110_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT110_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT110_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT110_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT110_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT110_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT110_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT110_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT110_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT110_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT110_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT110_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT110_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT110_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT110_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT110_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT110_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT110_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT110_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT110_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT110_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT110_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT110_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT110_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT110_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT110_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT110_TOG Bit Fields */ -#define CCM_PRE_ROOT110_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT110_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT110_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT110_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT110_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT110_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT110_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT110_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT110_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT110_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT110_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT110_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT110_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT110_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT110_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT110_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT110_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT110_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT110_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT110_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT110_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT110_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT110_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT110_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT110_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT110_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT110_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT110_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL110 Bit Fields */ -#define CCM_ACCESS_CTRL110_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL110_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL110_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL110_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL110_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL110_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL110_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL110_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL110_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL110_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL110_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL110_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL110_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL110_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL110_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL110_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL110_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL110_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL110_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL110_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL110_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL110_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL110_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL110_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL110_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL110_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL110_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL110_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL110_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL110_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL110_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL110_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL110_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL110_LOCK_SHIFT 31 -/* ACCESS_CTRL110_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL110_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL110_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL110_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL110_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL110_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL110_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL110_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL110_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL110_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL110_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL110_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL110_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL110_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL110_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL110_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL110_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT111 Bit Fields */ -#define CCM_TARGET_ROOT111_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT111_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT111_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_POST_PODF_SHIFT))&CCM_TARGET_ROOT111_POST_PODF_MASK) -#define CCM_TARGET_ROOT111_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT111_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT111_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT111_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT111_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT111_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT111_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT111_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT111_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT111_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT111_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_PRE_PODF_SHIFT))&CCM_TARGET_ROOT111_PRE_PODF_MASK) -#define CCM_TARGET_ROOT111_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT111_MUX_SHIFT 24 -#define CCM_TARGET_ROOT111_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_MUX_SHIFT))&CCM_TARGET_ROOT111_MUX_MASK) -#define CCM_TARGET_ROOT111_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT111_ENABLE_SHIFT 28 -/* TARGET_ROOT111_SET Bit Fields */ -#define CCM_TARGET_ROOT111_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT111_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT111_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT111_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT111_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT111_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT111_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT111_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT111_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT111_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT111_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT111_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT111_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT111_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT111_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT111_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT111_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT111_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT111_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_SET_MUX_SHIFT))&CCM_TARGET_ROOT111_SET_MUX_MASK) -#define CCM_TARGET_ROOT111_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT111_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT111_CLR Bit Fields */ -#define CCM_TARGET_ROOT111_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT111_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT111_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT111_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT111_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT111_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT111_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT111_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT111_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT111_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT111_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT111_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT111_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT111_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT111_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT111_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT111_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT111_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT111_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_CLR_MUX_SHIFT))&CCM_TARGET_ROOT111_CLR_MUX_MASK) -#define CCM_TARGET_ROOT111_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT111_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT111_TOG Bit Fields */ -#define CCM_TARGET_ROOT111_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT111_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT111_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT111_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT111_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT111_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT111_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT111_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT111_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT111_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT111_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT111_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT111_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT111_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT111_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT111_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT111_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT111_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT111_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_TOG_MUX_SHIFT))&CCM_TARGET_ROOT111_TOG_MUX_MASK) -#define CCM_TARGET_ROOT111_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT111_TOG_ENABLE_SHIFT 28 -/* POST111 Bit Fields */ -#define CCM_POST111_POST_PODF_MASK 0x3Fu -#define CCM_POST111_POST_PODF_SHIFT 0 -#define CCM_POST111_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST111_POST_PODF_SHIFT))&CCM_POST111_POST_PODF_MASK) -#define CCM_POST111_BUSY1_MASK 0x80u -#define CCM_POST111_BUSY1_SHIFT 7 -#define CCM_POST111_AUTO_PODF_MASK 0x700u -#define CCM_POST111_AUTO_PODF_SHIFT 8 -#define CCM_POST111_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST111_AUTO_PODF_SHIFT))&CCM_POST111_AUTO_PODF_MASK) -#define CCM_POST111_AUTO_EN_MASK 0x1000u -#define CCM_POST111_AUTO_EN_SHIFT 12 -#define CCM_POST111_SLOW_MASK 0x8000u -#define CCM_POST111_SLOW_SHIFT 15 -#define CCM_POST111_SELECT_MASK 0x10000000u -#define CCM_POST111_SELECT_SHIFT 28 -#define CCM_POST111_BUSY2_MASK 0x80000000u -#define CCM_POST111_BUSY2_SHIFT 31 -/* POST_ROOT111_SET Bit Fields */ -#define CCM_POST_ROOT111_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT111_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT111_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_SET_POST_PODF_SHIFT))&CCM_POST_ROOT111_SET_POST_PODF_MASK) -#define CCM_POST_ROOT111_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT111_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT111_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT111_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT111_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT111_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT111_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT111_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT111_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT111_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT111_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT111_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT111_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT111_SET_BUSY2_SHIFT 31 -/* POST_ROOT111_CLR Bit Fields */ -#define CCM_POST_ROOT111_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT111_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT111_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT111_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT111_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT111_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT111_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT111_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT111_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT111_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT111_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT111_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT111_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT111_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT111_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT111_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT111_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT111_CLR_BUSY2_SHIFT 31 -/* POST_ROOT111_TOG Bit Fields */ -#define CCM_POST_ROOT111_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT111_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT111_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT111_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT111_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT111_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT111_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT111_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT111_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT111_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT111_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT111_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT111_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT111_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT111_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT111_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT111_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT111_TOG_BUSY2_SHIFT 31 -/* PRE111 Bit Fields */ -#define CCM_PRE111_PRE_PODF_B_MASK 0x7u -#define CCM_PRE111_PRE_PODF_B_SHIFT 0 -#define CCM_PRE111_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE111_PRE_PODF_B_SHIFT))&CCM_PRE111_PRE_PODF_B_MASK) -#define CCM_PRE111_BUSY0_MASK 0x8u -#define CCM_PRE111_BUSY0_SHIFT 3 -#define CCM_PRE111_MUX_B_MASK 0x700u -#define CCM_PRE111_MUX_B_SHIFT 8 -#define CCM_PRE111_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE111_MUX_B_SHIFT))&CCM_PRE111_MUX_B_MASK) -#define CCM_PRE111_EN_B_MASK 0x1000u -#define CCM_PRE111_EN_B_SHIFT 12 -#define CCM_PRE111_BUSY1_MASK 0x8000u -#define CCM_PRE111_BUSY1_SHIFT 15 -#define CCM_PRE111_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE111_PRE_PODF_A_SHIFT 16 -#define CCM_PRE111_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE111_PRE_PODF_A_SHIFT))&CCM_PRE111_PRE_PODF_A_MASK) -#define CCM_PRE111_BUSY3_MASK 0x80000u -#define CCM_PRE111_BUSY3_SHIFT 19 -#define CCM_PRE111_MUX_A_MASK 0x7000000u -#define CCM_PRE111_MUX_A_SHIFT 24 -#define CCM_PRE111_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE111_MUX_A_SHIFT))&CCM_PRE111_MUX_A_MASK) -#define CCM_PRE111_EN_A_MASK 0x10000000u -#define CCM_PRE111_EN_A_SHIFT 28 -#define CCM_PRE111_BUSY4_MASK 0x80000000u -#define CCM_PRE111_BUSY4_SHIFT 31 -/* PRE_ROOT111_SET Bit Fields */ -#define CCM_PRE_ROOT111_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT111_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT111_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT111_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT111_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT111_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT111_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT111_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT111_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_SET_MUX_B_SHIFT))&CCM_PRE_ROOT111_SET_MUX_B_MASK) -#define CCM_PRE_ROOT111_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT111_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT111_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT111_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT111_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT111_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT111_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT111_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT111_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT111_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT111_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT111_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT111_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_SET_MUX_A_SHIFT))&CCM_PRE_ROOT111_SET_MUX_A_MASK) -#define CCM_PRE_ROOT111_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT111_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT111_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT111_SET_BUSY4_SHIFT 31 -/* PRE_ROOT111_CLR Bit Fields */ -#define CCM_PRE_ROOT111_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT111_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT111_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT111_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT111_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT111_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT111_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT111_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT111_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT111_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT111_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT111_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT111_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT111_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT111_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT111_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT111_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT111_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT111_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT111_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT111_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT111_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT111_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT111_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT111_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT111_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT111_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT111_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT111_TOG Bit Fields */ -#define CCM_PRE_ROOT111_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT111_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT111_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT111_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT111_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT111_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT111_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT111_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT111_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT111_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT111_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT111_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT111_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT111_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT111_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT111_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT111_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT111_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT111_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT111_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT111_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT111_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT111_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT111_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT111_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT111_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT111_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT111_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL111 Bit Fields */ -#define CCM_ACCESS_CTRL111_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL111_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL111_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL111_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL111_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL111_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL111_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL111_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL111_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL111_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL111_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL111_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL111_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL111_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL111_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL111_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL111_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL111_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL111_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL111_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL111_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL111_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL111_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL111_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL111_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL111_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL111_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL111_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL111_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL111_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL111_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL111_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL111_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL111_LOCK_SHIFT 31 -/* ACCESS_CTRL111_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL111_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL111_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL111_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL111_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL111_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL111_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL111_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL111_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL111_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL111_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL111_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL111_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL111_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL111_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL111_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL111_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT112 Bit Fields */ -#define CCM_TARGET_ROOT112_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT112_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT112_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_POST_PODF_SHIFT))&CCM_TARGET_ROOT112_POST_PODF_MASK) -#define CCM_TARGET_ROOT112_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT112_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT112_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT112_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT112_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT112_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT112_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT112_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT112_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT112_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT112_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_PRE_PODF_SHIFT))&CCM_TARGET_ROOT112_PRE_PODF_MASK) -#define CCM_TARGET_ROOT112_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT112_MUX_SHIFT 24 -#define CCM_TARGET_ROOT112_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_MUX_SHIFT))&CCM_TARGET_ROOT112_MUX_MASK) -#define CCM_TARGET_ROOT112_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT112_ENABLE_SHIFT 28 -/* TARGET_ROOT112_SET Bit Fields */ -#define CCM_TARGET_ROOT112_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT112_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT112_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT112_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT112_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT112_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT112_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT112_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT112_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT112_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT112_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT112_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT112_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT112_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT112_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT112_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT112_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT112_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT112_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_SET_MUX_SHIFT))&CCM_TARGET_ROOT112_SET_MUX_MASK) -#define CCM_TARGET_ROOT112_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT112_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT112_CLR Bit Fields */ -#define CCM_TARGET_ROOT112_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT112_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT112_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT112_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT112_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT112_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT112_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT112_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT112_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT112_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT112_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT112_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT112_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT112_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT112_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT112_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT112_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT112_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT112_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_CLR_MUX_SHIFT))&CCM_TARGET_ROOT112_CLR_MUX_MASK) -#define CCM_TARGET_ROOT112_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT112_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT112_TOG Bit Fields */ -#define CCM_TARGET_ROOT112_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT112_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT112_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT112_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT112_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT112_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT112_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT112_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT112_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT112_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT112_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT112_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT112_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT112_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT112_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT112_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT112_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT112_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT112_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_TOG_MUX_SHIFT))&CCM_TARGET_ROOT112_TOG_MUX_MASK) -#define CCM_TARGET_ROOT112_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT112_TOG_ENABLE_SHIFT 28 -/* POST112 Bit Fields */ -#define CCM_POST112_POST_PODF_MASK 0x3Fu -#define CCM_POST112_POST_PODF_SHIFT 0 -#define CCM_POST112_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST112_POST_PODF_SHIFT))&CCM_POST112_POST_PODF_MASK) -#define CCM_POST112_BUSY1_MASK 0x80u -#define CCM_POST112_BUSY1_SHIFT 7 -#define CCM_POST112_AUTO_PODF_MASK 0x700u -#define CCM_POST112_AUTO_PODF_SHIFT 8 -#define CCM_POST112_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST112_AUTO_PODF_SHIFT))&CCM_POST112_AUTO_PODF_MASK) -#define CCM_POST112_AUTO_EN_MASK 0x1000u -#define CCM_POST112_AUTO_EN_SHIFT 12 -#define CCM_POST112_SLOW_MASK 0x8000u -#define CCM_POST112_SLOW_SHIFT 15 -#define CCM_POST112_SELECT_MASK 0x10000000u -#define CCM_POST112_SELECT_SHIFT 28 -#define CCM_POST112_BUSY2_MASK 0x80000000u -#define CCM_POST112_BUSY2_SHIFT 31 -/* POST_ROOT112_SET Bit Fields */ -#define CCM_POST_ROOT112_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT112_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT112_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_SET_POST_PODF_SHIFT))&CCM_POST_ROOT112_SET_POST_PODF_MASK) -#define CCM_POST_ROOT112_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT112_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT112_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT112_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT112_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT112_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT112_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT112_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT112_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT112_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT112_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT112_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT112_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT112_SET_BUSY2_SHIFT 31 -/* POST_ROOT112_CLR Bit Fields */ -#define CCM_POST_ROOT112_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT112_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT112_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT112_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT112_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT112_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT112_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT112_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT112_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT112_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT112_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT112_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT112_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT112_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT112_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT112_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT112_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT112_CLR_BUSY2_SHIFT 31 -/* POST_ROOT112_TOG Bit Fields */ -#define CCM_POST_ROOT112_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT112_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT112_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT112_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT112_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT112_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT112_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT112_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT112_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT112_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT112_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT112_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT112_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT112_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT112_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT112_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT112_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT112_TOG_BUSY2_SHIFT 31 -/* PRE112 Bit Fields */ -#define CCM_PRE112_PRE_PODF_B_MASK 0x7u -#define CCM_PRE112_PRE_PODF_B_SHIFT 0 -#define CCM_PRE112_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE112_PRE_PODF_B_SHIFT))&CCM_PRE112_PRE_PODF_B_MASK) -#define CCM_PRE112_BUSY0_MASK 0x8u -#define CCM_PRE112_BUSY0_SHIFT 3 -#define CCM_PRE112_MUX_B_MASK 0x700u -#define CCM_PRE112_MUX_B_SHIFT 8 -#define CCM_PRE112_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE112_MUX_B_SHIFT))&CCM_PRE112_MUX_B_MASK) -#define CCM_PRE112_EN_B_MASK 0x1000u -#define CCM_PRE112_EN_B_SHIFT 12 -#define CCM_PRE112_BUSY1_MASK 0x8000u -#define CCM_PRE112_BUSY1_SHIFT 15 -#define CCM_PRE112_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE112_PRE_PODF_A_SHIFT 16 -#define CCM_PRE112_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE112_PRE_PODF_A_SHIFT))&CCM_PRE112_PRE_PODF_A_MASK) -#define CCM_PRE112_BUSY3_MASK 0x80000u -#define CCM_PRE112_BUSY3_SHIFT 19 -#define CCM_PRE112_MUX_A_MASK 0x7000000u -#define CCM_PRE112_MUX_A_SHIFT 24 -#define CCM_PRE112_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE112_MUX_A_SHIFT))&CCM_PRE112_MUX_A_MASK) -#define CCM_PRE112_EN_A_MASK 0x10000000u -#define CCM_PRE112_EN_A_SHIFT 28 -#define CCM_PRE112_BUSY4_MASK 0x80000000u -#define CCM_PRE112_BUSY4_SHIFT 31 -/* PRE_ROOT112_SET Bit Fields */ -#define CCM_PRE_ROOT112_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT112_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT112_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT112_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT112_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT112_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT112_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT112_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT112_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_SET_MUX_B_SHIFT))&CCM_PRE_ROOT112_SET_MUX_B_MASK) -#define CCM_PRE_ROOT112_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT112_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT112_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT112_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT112_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT112_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT112_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT112_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT112_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT112_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT112_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT112_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT112_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_SET_MUX_A_SHIFT))&CCM_PRE_ROOT112_SET_MUX_A_MASK) -#define CCM_PRE_ROOT112_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT112_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT112_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT112_SET_BUSY4_SHIFT 31 -/* PRE_ROOT112_CLR Bit Fields */ -#define CCM_PRE_ROOT112_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT112_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT112_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT112_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT112_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT112_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT112_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT112_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT112_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT112_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT112_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT112_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT112_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT112_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT112_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT112_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT112_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT112_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT112_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT112_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT112_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT112_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT112_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT112_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT112_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT112_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT112_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT112_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT112_TOG Bit Fields */ -#define CCM_PRE_ROOT112_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT112_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT112_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT112_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT112_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT112_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT112_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT112_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT112_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT112_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT112_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT112_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT112_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT112_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT112_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT112_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT112_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT112_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT112_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT112_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT112_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT112_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT112_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT112_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT112_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT112_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT112_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT112_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL112 Bit Fields */ -#define CCM_ACCESS_CTRL112_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL112_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL112_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL112_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL112_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL112_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL112_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL112_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL112_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL112_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL112_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL112_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL112_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL112_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL112_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL112_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL112_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL112_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL112_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL112_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL112_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL112_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL112_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL112_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL112_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL112_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL112_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL112_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL112_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL112_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL112_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL112_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL112_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL112_LOCK_SHIFT 31 -/* ACCESS_CTRL112_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL112_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL112_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL112_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL112_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL112_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL112_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL112_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL112_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL112_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL112_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL112_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL112_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL112_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL112_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL112_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL112_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT113 Bit Fields */ -#define CCM_TARGET_ROOT113_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT113_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT113_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_POST_PODF_SHIFT))&CCM_TARGET_ROOT113_POST_PODF_MASK) -#define CCM_TARGET_ROOT113_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT113_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT113_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT113_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT113_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT113_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT113_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT113_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT113_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT113_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT113_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_PRE_PODF_SHIFT))&CCM_TARGET_ROOT113_PRE_PODF_MASK) -#define CCM_TARGET_ROOT113_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT113_MUX_SHIFT 24 -#define CCM_TARGET_ROOT113_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_MUX_SHIFT))&CCM_TARGET_ROOT113_MUX_MASK) -#define CCM_TARGET_ROOT113_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT113_ENABLE_SHIFT 28 -/* TARGET_ROOT113_SET Bit Fields */ -#define CCM_TARGET_ROOT113_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT113_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT113_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT113_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT113_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT113_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT113_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT113_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT113_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT113_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT113_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT113_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT113_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT113_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT113_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT113_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT113_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT113_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT113_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_SET_MUX_SHIFT))&CCM_TARGET_ROOT113_SET_MUX_MASK) -#define CCM_TARGET_ROOT113_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT113_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT113_CLR Bit Fields */ -#define CCM_TARGET_ROOT113_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT113_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT113_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT113_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT113_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT113_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT113_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT113_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT113_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT113_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT113_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT113_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT113_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT113_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT113_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT113_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT113_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT113_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT113_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_CLR_MUX_SHIFT))&CCM_TARGET_ROOT113_CLR_MUX_MASK) -#define CCM_TARGET_ROOT113_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT113_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT113_TOG Bit Fields */ -#define CCM_TARGET_ROOT113_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT113_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT113_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT113_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT113_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT113_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT113_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT113_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT113_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT113_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT113_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT113_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT113_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT113_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT113_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT113_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT113_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT113_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT113_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_TOG_MUX_SHIFT))&CCM_TARGET_ROOT113_TOG_MUX_MASK) -#define CCM_TARGET_ROOT113_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT113_TOG_ENABLE_SHIFT 28 -/* POST113 Bit Fields */ -#define CCM_POST113_POST_PODF_MASK 0x3Fu -#define CCM_POST113_POST_PODF_SHIFT 0 -#define CCM_POST113_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST113_POST_PODF_SHIFT))&CCM_POST113_POST_PODF_MASK) -#define CCM_POST113_BUSY1_MASK 0x80u -#define CCM_POST113_BUSY1_SHIFT 7 -#define CCM_POST113_AUTO_PODF_MASK 0x700u -#define CCM_POST113_AUTO_PODF_SHIFT 8 -#define CCM_POST113_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST113_AUTO_PODF_SHIFT))&CCM_POST113_AUTO_PODF_MASK) -#define CCM_POST113_AUTO_EN_MASK 0x1000u -#define CCM_POST113_AUTO_EN_SHIFT 12 -#define CCM_POST113_SLOW_MASK 0x8000u -#define CCM_POST113_SLOW_SHIFT 15 -#define CCM_POST113_SELECT_MASK 0x10000000u -#define CCM_POST113_SELECT_SHIFT 28 -#define CCM_POST113_BUSY2_MASK 0x80000000u -#define CCM_POST113_BUSY2_SHIFT 31 -/* POST_ROOT113_SET Bit Fields */ -#define CCM_POST_ROOT113_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT113_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT113_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_SET_POST_PODF_SHIFT))&CCM_POST_ROOT113_SET_POST_PODF_MASK) -#define CCM_POST_ROOT113_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT113_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT113_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT113_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT113_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT113_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT113_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT113_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT113_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT113_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT113_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT113_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT113_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT113_SET_BUSY2_SHIFT 31 -/* POST_ROOT113_CLR Bit Fields */ -#define CCM_POST_ROOT113_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT113_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT113_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT113_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT113_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT113_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT113_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT113_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT113_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT113_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT113_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT113_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT113_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT113_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT113_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT113_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT113_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT113_CLR_BUSY2_SHIFT 31 -/* POST_ROOT113_TOG Bit Fields */ -#define CCM_POST_ROOT113_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT113_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT113_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT113_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT113_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT113_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT113_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT113_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT113_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT113_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT113_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT113_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT113_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT113_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT113_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT113_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT113_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT113_TOG_BUSY2_SHIFT 31 -/* PRE113 Bit Fields */ -#define CCM_PRE113_PRE_PODF_B_MASK 0x7u -#define CCM_PRE113_PRE_PODF_B_SHIFT 0 -#define CCM_PRE113_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE113_PRE_PODF_B_SHIFT))&CCM_PRE113_PRE_PODF_B_MASK) -#define CCM_PRE113_BUSY0_MASK 0x8u -#define CCM_PRE113_BUSY0_SHIFT 3 -#define CCM_PRE113_MUX_B_MASK 0x700u -#define CCM_PRE113_MUX_B_SHIFT 8 -#define CCM_PRE113_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE113_MUX_B_SHIFT))&CCM_PRE113_MUX_B_MASK) -#define CCM_PRE113_EN_B_MASK 0x1000u -#define CCM_PRE113_EN_B_SHIFT 12 -#define CCM_PRE113_BUSY1_MASK 0x8000u -#define CCM_PRE113_BUSY1_SHIFT 15 -#define CCM_PRE113_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE113_PRE_PODF_A_SHIFT 16 -#define CCM_PRE113_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE113_PRE_PODF_A_SHIFT))&CCM_PRE113_PRE_PODF_A_MASK) -#define CCM_PRE113_BUSY3_MASK 0x80000u -#define CCM_PRE113_BUSY3_SHIFT 19 -#define CCM_PRE113_MUX_A_MASK 0x7000000u -#define CCM_PRE113_MUX_A_SHIFT 24 -#define CCM_PRE113_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE113_MUX_A_SHIFT))&CCM_PRE113_MUX_A_MASK) -#define CCM_PRE113_EN_A_MASK 0x10000000u -#define CCM_PRE113_EN_A_SHIFT 28 -#define CCM_PRE113_BUSY4_MASK 0x80000000u -#define CCM_PRE113_BUSY4_SHIFT 31 -/* PRE_ROOT113_SET Bit Fields */ -#define CCM_PRE_ROOT113_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT113_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT113_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT113_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT113_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT113_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT113_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT113_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT113_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_SET_MUX_B_SHIFT))&CCM_PRE_ROOT113_SET_MUX_B_MASK) -#define CCM_PRE_ROOT113_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT113_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT113_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT113_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT113_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT113_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT113_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT113_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT113_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT113_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT113_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT113_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT113_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_SET_MUX_A_SHIFT))&CCM_PRE_ROOT113_SET_MUX_A_MASK) -#define CCM_PRE_ROOT113_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT113_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT113_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT113_SET_BUSY4_SHIFT 31 -/* PRE_ROOT113_CLR Bit Fields */ -#define CCM_PRE_ROOT113_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT113_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT113_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT113_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT113_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT113_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT113_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT113_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT113_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT113_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT113_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT113_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT113_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT113_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT113_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT113_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT113_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT113_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT113_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT113_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT113_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT113_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT113_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT113_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT113_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT113_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT113_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT113_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT113_TOG Bit Fields */ -#define CCM_PRE_ROOT113_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT113_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT113_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT113_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT113_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT113_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT113_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT113_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT113_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT113_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT113_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT113_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT113_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT113_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT113_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT113_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT113_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT113_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT113_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT113_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT113_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT113_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT113_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT113_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT113_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT113_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT113_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT113_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL113 Bit Fields */ -#define CCM_ACCESS_CTRL113_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL113_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL113_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL113_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL113_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL113_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL113_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL113_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL113_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL113_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL113_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL113_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL113_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL113_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL113_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL113_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL113_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL113_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL113_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL113_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL113_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL113_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL113_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL113_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL113_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL113_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL113_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL113_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL113_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL113_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL113_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL113_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL113_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL113_LOCK_SHIFT 31 -/* ACCESS_CTRL113_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL113_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL113_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL113_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL113_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL113_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL113_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL113_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL113_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL113_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL113_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL113_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL113_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL113_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL113_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL113_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL113_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT114 Bit Fields */ -#define CCM_TARGET_ROOT114_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT114_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT114_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_POST_PODF_SHIFT))&CCM_TARGET_ROOT114_POST_PODF_MASK) -#define CCM_TARGET_ROOT114_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT114_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT114_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT114_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT114_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT114_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT114_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT114_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT114_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT114_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT114_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_PRE_PODF_SHIFT))&CCM_TARGET_ROOT114_PRE_PODF_MASK) -#define CCM_TARGET_ROOT114_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT114_MUX_SHIFT 24 -#define CCM_TARGET_ROOT114_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_MUX_SHIFT))&CCM_TARGET_ROOT114_MUX_MASK) -#define CCM_TARGET_ROOT114_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT114_ENABLE_SHIFT 28 -/* TARGET_ROOT114_SET Bit Fields */ -#define CCM_TARGET_ROOT114_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT114_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT114_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT114_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT114_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT114_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT114_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT114_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT114_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT114_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT114_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT114_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT114_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT114_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT114_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT114_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT114_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT114_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT114_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_SET_MUX_SHIFT))&CCM_TARGET_ROOT114_SET_MUX_MASK) -#define CCM_TARGET_ROOT114_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT114_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT114_CLR Bit Fields */ -#define CCM_TARGET_ROOT114_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT114_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT114_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT114_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT114_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT114_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT114_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT114_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT114_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT114_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT114_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT114_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT114_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT114_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT114_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT114_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT114_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT114_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT114_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_CLR_MUX_SHIFT))&CCM_TARGET_ROOT114_CLR_MUX_MASK) -#define CCM_TARGET_ROOT114_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT114_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT114_TOG Bit Fields */ -#define CCM_TARGET_ROOT114_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT114_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT114_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT114_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT114_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT114_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT114_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT114_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT114_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT114_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT114_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT114_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT114_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT114_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT114_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT114_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT114_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT114_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT114_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_TOG_MUX_SHIFT))&CCM_TARGET_ROOT114_TOG_MUX_MASK) -#define CCM_TARGET_ROOT114_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT114_TOG_ENABLE_SHIFT 28 -/* POST114 Bit Fields */ -#define CCM_POST114_POST_PODF_MASK 0x3Fu -#define CCM_POST114_POST_PODF_SHIFT 0 -#define CCM_POST114_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST114_POST_PODF_SHIFT))&CCM_POST114_POST_PODF_MASK) -#define CCM_POST114_BUSY1_MASK 0x80u -#define CCM_POST114_BUSY1_SHIFT 7 -#define CCM_POST114_AUTO_PODF_MASK 0x700u -#define CCM_POST114_AUTO_PODF_SHIFT 8 -#define CCM_POST114_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST114_AUTO_PODF_SHIFT))&CCM_POST114_AUTO_PODF_MASK) -#define CCM_POST114_AUTO_EN_MASK 0x1000u -#define CCM_POST114_AUTO_EN_SHIFT 12 -#define CCM_POST114_SLOW_MASK 0x8000u -#define CCM_POST114_SLOW_SHIFT 15 -#define CCM_POST114_SELECT_MASK 0x10000000u -#define CCM_POST114_SELECT_SHIFT 28 -#define CCM_POST114_BUSY2_MASK 0x80000000u -#define CCM_POST114_BUSY2_SHIFT 31 -/* POST_ROOT114_SET Bit Fields */ -#define CCM_POST_ROOT114_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT114_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT114_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_SET_POST_PODF_SHIFT))&CCM_POST_ROOT114_SET_POST_PODF_MASK) -#define CCM_POST_ROOT114_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT114_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT114_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT114_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT114_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT114_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT114_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT114_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT114_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT114_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT114_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT114_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT114_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT114_SET_BUSY2_SHIFT 31 -/* POST_ROOT114_CLR Bit Fields */ -#define CCM_POST_ROOT114_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT114_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT114_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT114_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT114_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT114_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT114_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT114_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT114_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT114_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT114_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT114_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT114_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT114_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT114_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT114_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT114_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT114_CLR_BUSY2_SHIFT 31 -/* POST_ROOT114_TOG Bit Fields */ -#define CCM_POST_ROOT114_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT114_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT114_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT114_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT114_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT114_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT114_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT114_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT114_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT114_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT114_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT114_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT114_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT114_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT114_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT114_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT114_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT114_TOG_BUSY2_SHIFT 31 -/* PRE114 Bit Fields */ -#define CCM_PRE114_PRE_PODF_B_MASK 0x7u -#define CCM_PRE114_PRE_PODF_B_SHIFT 0 -#define CCM_PRE114_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE114_PRE_PODF_B_SHIFT))&CCM_PRE114_PRE_PODF_B_MASK) -#define CCM_PRE114_BUSY0_MASK 0x8u -#define CCM_PRE114_BUSY0_SHIFT 3 -#define CCM_PRE114_MUX_B_MASK 0x700u -#define CCM_PRE114_MUX_B_SHIFT 8 -#define CCM_PRE114_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE114_MUX_B_SHIFT))&CCM_PRE114_MUX_B_MASK) -#define CCM_PRE114_EN_B_MASK 0x1000u -#define CCM_PRE114_EN_B_SHIFT 12 -#define CCM_PRE114_BUSY1_MASK 0x8000u -#define CCM_PRE114_BUSY1_SHIFT 15 -#define CCM_PRE114_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE114_PRE_PODF_A_SHIFT 16 -#define CCM_PRE114_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE114_PRE_PODF_A_SHIFT))&CCM_PRE114_PRE_PODF_A_MASK) -#define CCM_PRE114_BUSY3_MASK 0x80000u -#define CCM_PRE114_BUSY3_SHIFT 19 -#define CCM_PRE114_MUX_A_MASK 0x7000000u -#define CCM_PRE114_MUX_A_SHIFT 24 -#define CCM_PRE114_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE114_MUX_A_SHIFT))&CCM_PRE114_MUX_A_MASK) -#define CCM_PRE114_EN_A_MASK 0x10000000u -#define CCM_PRE114_EN_A_SHIFT 28 -#define CCM_PRE114_BUSY4_MASK 0x80000000u -#define CCM_PRE114_BUSY4_SHIFT 31 -/* PRE_ROOT114_SET Bit Fields */ -#define CCM_PRE_ROOT114_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT114_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT114_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT114_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT114_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT114_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT114_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT114_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT114_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_SET_MUX_B_SHIFT))&CCM_PRE_ROOT114_SET_MUX_B_MASK) -#define CCM_PRE_ROOT114_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT114_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT114_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT114_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT114_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT114_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT114_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT114_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT114_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT114_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT114_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT114_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT114_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_SET_MUX_A_SHIFT))&CCM_PRE_ROOT114_SET_MUX_A_MASK) -#define CCM_PRE_ROOT114_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT114_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT114_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT114_SET_BUSY4_SHIFT 31 -/* PRE_ROOT114_CLR Bit Fields */ -#define CCM_PRE_ROOT114_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT114_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT114_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT114_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT114_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT114_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT114_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT114_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT114_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT114_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT114_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT114_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT114_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT114_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT114_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT114_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT114_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT114_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT114_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT114_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT114_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT114_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT114_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT114_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT114_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT114_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT114_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT114_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT114_TOG Bit Fields */ -#define CCM_PRE_ROOT114_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT114_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT114_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT114_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT114_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT114_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT114_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT114_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT114_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT114_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT114_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT114_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT114_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT114_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT114_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT114_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT114_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT114_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT114_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT114_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT114_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT114_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT114_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT114_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT114_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT114_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT114_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT114_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL114 Bit Fields */ -#define CCM_ACCESS_CTRL114_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL114_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL114_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL114_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL114_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL114_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL114_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL114_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL114_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL114_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL114_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL114_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL114_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL114_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL114_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL114_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL114_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL114_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL114_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL114_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL114_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL114_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL114_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL114_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL114_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL114_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL114_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL114_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL114_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL114_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL114_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL114_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL114_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL114_LOCK_SHIFT 31 -/* ACCESS_CTRL114_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL114_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL114_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL114_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL114_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL114_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL114_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL114_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL114_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL114_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL114_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL114_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL114_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL114_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL114_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL114_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL114_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT115 Bit Fields */ -#define CCM_TARGET_ROOT115_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT115_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT115_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_POST_PODF_SHIFT))&CCM_TARGET_ROOT115_POST_PODF_MASK) -#define CCM_TARGET_ROOT115_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT115_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT115_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT115_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT115_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT115_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT115_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT115_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT115_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT115_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT115_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_PRE_PODF_SHIFT))&CCM_TARGET_ROOT115_PRE_PODF_MASK) -#define CCM_TARGET_ROOT115_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT115_MUX_SHIFT 24 -#define CCM_TARGET_ROOT115_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_MUX_SHIFT))&CCM_TARGET_ROOT115_MUX_MASK) -#define CCM_TARGET_ROOT115_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT115_ENABLE_SHIFT 28 -/* TARGET_ROOT115_SET Bit Fields */ -#define CCM_TARGET_ROOT115_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT115_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT115_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT115_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT115_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT115_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT115_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT115_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT115_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT115_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT115_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT115_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT115_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT115_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT115_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT115_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT115_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT115_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT115_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_SET_MUX_SHIFT))&CCM_TARGET_ROOT115_SET_MUX_MASK) -#define CCM_TARGET_ROOT115_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT115_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT115_CLR Bit Fields */ -#define CCM_TARGET_ROOT115_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT115_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT115_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT115_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT115_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT115_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT115_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT115_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT115_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT115_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT115_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT115_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT115_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT115_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT115_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT115_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT115_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT115_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT115_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_CLR_MUX_SHIFT))&CCM_TARGET_ROOT115_CLR_MUX_MASK) -#define CCM_TARGET_ROOT115_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT115_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT115_TOG Bit Fields */ -#define CCM_TARGET_ROOT115_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT115_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT115_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT115_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT115_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT115_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT115_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT115_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT115_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT115_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT115_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT115_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT115_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT115_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT115_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT115_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT115_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT115_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT115_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_TOG_MUX_SHIFT))&CCM_TARGET_ROOT115_TOG_MUX_MASK) -#define CCM_TARGET_ROOT115_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT115_TOG_ENABLE_SHIFT 28 -/* POST115 Bit Fields */ -#define CCM_POST115_POST_PODF_MASK 0x3Fu -#define CCM_POST115_POST_PODF_SHIFT 0 -#define CCM_POST115_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST115_POST_PODF_SHIFT))&CCM_POST115_POST_PODF_MASK) -#define CCM_POST115_BUSY1_MASK 0x80u -#define CCM_POST115_BUSY1_SHIFT 7 -#define CCM_POST115_AUTO_PODF_MASK 0x700u -#define CCM_POST115_AUTO_PODF_SHIFT 8 -#define CCM_POST115_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST115_AUTO_PODF_SHIFT))&CCM_POST115_AUTO_PODF_MASK) -#define CCM_POST115_AUTO_EN_MASK 0x1000u -#define CCM_POST115_AUTO_EN_SHIFT 12 -#define CCM_POST115_SLOW_MASK 0x8000u -#define CCM_POST115_SLOW_SHIFT 15 -#define CCM_POST115_SELECT_MASK 0x10000000u -#define CCM_POST115_SELECT_SHIFT 28 -#define CCM_POST115_BUSY2_MASK 0x80000000u -#define CCM_POST115_BUSY2_SHIFT 31 -/* POST_ROOT115_SET Bit Fields */ -#define CCM_POST_ROOT115_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT115_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT115_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_SET_POST_PODF_SHIFT))&CCM_POST_ROOT115_SET_POST_PODF_MASK) -#define CCM_POST_ROOT115_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT115_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT115_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT115_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT115_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT115_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT115_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT115_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT115_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT115_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT115_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT115_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT115_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT115_SET_BUSY2_SHIFT 31 -/* POST_ROOT115_CLR Bit Fields */ -#define CCM_POST_ROOT115_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT115_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT115_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT115_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT115_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT115_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT115_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT115_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT115_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT115_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT115_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT115_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT115_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT115_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT115_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT115_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT115_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT115_CLR_BUSY2_SHIFT 31 -/* POST_ROOT115_TOG Bit Fields */ -#define CCM_POST_ROOT115_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT115_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT115_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT115_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT115_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT115_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT115_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT115_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT115_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT115_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT115_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT115_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT115_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT115_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT115_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT115_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT115_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT115_TOG_BUSY2_SHIFT 31 -/* PRE115 Bit Fields */ -#define CCM_PRE115_PRE_PODF_B_MASK 0x7u -#define CCM_PRE115_PRE_PODF_B_SHIFT 0 -#define CCM_PRE115_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE115_PRE_PODF_B_SHIFT))&CCM_PRE115_PRE_PODF_B_MASK) -#define CCM_PRE115_BUSY0_MASK 0x8u -#define CCM_PRE115_BUSY0_SHIFT 3 -#define CCM_PRE115_MUX_B_MASK 0x700u -#define CCM_PRE115_MUX_B_SHIFT 8 -#define CCM_PRE115_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE115_MUX_B_SHIFT))&CCM_PRE115_MUX_B_MASK) -#define CCM_PRE115_EN_B_MASK 0x1000u -#define CCM_PRE115_EN_B_SHIFT 12 -#define CCM_PRE115_BUSY1_MASK 0x8000u -#define CCM_PRE115_BUSY1_SHIFT 15 -#define CCM_PRE115_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE115_PRE_PODF_A_SHIFT 16 -#define CCM_PRE115_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE115_PRE_PODF_A_SHIFT))&CCM_PRE115_PRE_PODF_A_MASK) -#define CCM_PRE115_BUSY3_MASK 0x80000u -#define CCM_PRE115_BUSY3_SHIFT 19 -#define CCM_PRE115_MUX_A_MASK 0x7000000u -#define CCM_PRE115_MUX_A_SHIFT 24 -#define CCM_PRE115_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE115_MUX_A_SHIFT))&CCM_PRE115_MUX_A_MASK) -#define CCM_PRE115_EN_A_MASK 0x10000000u -#define CCM_PRE115_EN_A_SHIFT 28 -#define CCM_PRE115_BUSY4_MASK 0x80000000u -#define CCM_PRE115_BUSY4_SHIFT 31 -/* PRE_ROOT115_SET Bit Fields */ -#define CCM_PRE_ROOT115_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT115_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT115_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT115_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT115_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT115_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT115_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT115_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT115_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_SET_MUX_B_SHIFT))&CCM_PRE_ROOT115_SET_MUX_B_MASK) -#define CCM_PRE_ROOT115_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT115_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT115_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT115_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT115_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT115_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT115_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT115_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT115_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT115_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT115_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT115_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT115_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_SET_MUX_A_SHIFT))&CCM_PRE_ROOT115_SET_MUX_A_MASK) -#define CCM_PRE_ROOT115_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT115_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT115_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT115_SET_BUSY4_SHIFT 31 -/* PRE_ROOT115_CLR Bit Fields */ -#define CCM_PRE_ROOT115_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT115_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT115_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT115_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT115_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT115_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT115_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT115_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT115_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT115_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT115_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT115_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT115_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT115_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT115_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT115_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT115_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT115_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT115_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT115_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT115_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT115_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT115_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT115_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT115_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT115_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT115_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT115_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT115_TOG Bit Fields */ -#define CCM_PRE_ROOT115_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT115_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT115_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT115_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT115_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT115_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT115_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT115_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT115_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT115_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT115_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT115_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT115_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT115_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT115_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT115_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT115_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT115_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT115_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT115_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT115_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT115_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT115_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT115_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT115_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT115_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT115_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT115_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL115 Bit Fields */ -#define CCM_ACCESS_CTRL115_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL115_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL115_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL115_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL115_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL115_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL115_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL115_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL115_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL115_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL115_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL115_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL115_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL115_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL115_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL115_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL115_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL115_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL115_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL115_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL115_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL115_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL115_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL115_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL115_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL115_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL115_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL115_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL115_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL115_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL115_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL115_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL115_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL115_LOCK_SHIFT 31 -/* ACCESS_CTRL115_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL115_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL115_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL115_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL115_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL115_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL115_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL115_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL115_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL115_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL115_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL115_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL115_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL115_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL115_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL115_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL115_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT116 Bit Fields */ -#define CCM_TARGET_ROOT116_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT116_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT116_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_POST_PODF_SHIFT))&CCM_TARGET_ROOT116_POST_PODF_MASK) -#define CCM_TARGET_ROOT116_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT116_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT116_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT116_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT116_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT116_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT116_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT116_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT116_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT116_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT116_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_PRE_PODF_SHIFT))&CCM_TARGET_ROOT116_PRE_PODF_MASK) -#define CCM_TARGET_ROOT116_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT116_MUX_SHIFT 24 -#define CCM_TARGET_ROOT116_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_MUX_SHIFT))&CCM_TARGET_ROOT116_MUX_MASK) -#define CCM_TARGET_ROOT116_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT116_ENABLE_SHIFT 28 -/* TARGET_ROOT116_SET Bit Fields */ -#define CCM_TARGET_ROOT116_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT116_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT116_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT116_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT116_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT116_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT116_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT116_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT116_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT116_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT116_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT116_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT116_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT116_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT116_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT116_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT116_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT116_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT116_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_SET_MUX_SHIFT))&CCM_TARGET_ROOT116_SET_MUX_MASK) -#define CCM_TARGET_ROOT116_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT116_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT116_CLR Bit Fields */ -#define CCM_TARGET_ROOT116_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT116_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT116_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT116_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT116_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT116_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT116_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT116_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT116_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT116_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT116_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT116_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT116_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT116_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT116_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT116_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT116_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT116_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT116_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_CLR_MUX_SHIFT))&CCM_TARGET_ROOT116_CLR_MUX_MASK) -#define CCM_TARGET_ROOT116_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT116_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT116_TOG Bit Fields */ -#define CCM_TARGET_ROOT116_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT116_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT116_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT116_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT116_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT116_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT116_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT116_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT116_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT116_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT116_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT116_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT116_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT116_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT116_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT116_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT116_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT116_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT116_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_TOG_MUX_SHIFT))&CCM_TARGET_ROOT116_TOG_MUX_MASK) -#define CCM_TARGET_ROOT116_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT116_TOG_ENABLE_SHIFT 28 -/* POST116 Bit Fields */ -#define CCM_POST116_POST_PODF_MASK 0x3Fu -#define CCM_POST116_POST_PODF_SHIFT 0 -#define CCM_POST116_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST116_POST_PODF_SHIFT))&CCM_POST116_POST_PODF_MASK) -#define CCM_POST116_BUSY1_MASK 0x80u -#define CCM_POST116_BUSY1_SHIFT 7 -#define CCM_POST116_AUTO_PODF_MASK 0x700u -#define CCM_POST116_AUTO_PODF_SHIFT 8 -#define CCM_POST116_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST116_AUTO_PODF_SHIFT))&CCM_POST116_AUTO_PODF_MASK) -#define CCM_POST116_AUTO_EN_MASK 0x1000u -#define CCM_POST116_AUTO_EN_SHIFT 12 -#define CCM_POST116_SLOW_MASK 0x8000u -#define CCM_POST116_SLOW_SHIFT 15 -#define CCM_POST116_SELECT_MASK 0x10000000u -#define CCM_POST116_SELECT_SHIFT 28 -#define CCM_POST116_BUSY2_MASK 0x80000000u -#define CCM_POST116_BUSY2_SHIFT 31 -/* POST_ROOT116_SET Bit Fields */ -#define CCM_POST_ROOT116_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT116_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT116_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_SET_POST_PODF_SHIFT))&CCM_POST_ROOT116_SET_POST_PODF_MASK) -#define CCM_POST_ROOT116_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT116_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT116_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT116_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT116_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT116_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT116_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT116_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT116_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT116_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT116_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT116_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT116_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT116_SET_BUSY2_SHIFT 31 -/* POST_ROOT116_CLR Bit Fields */ -#define CCM_POST_ROOT116_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT116_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT116_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT116_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT116_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT116_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT116_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT116_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT116_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT116_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT116_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT116_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT116_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT116_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT116_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT116_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT116_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT116_CLR_BUSY2_SHIFT 31 -/* POST_ROOT116_TOG Bit Fields */ -#define CCM_POST_ROOT116_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT116_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT116_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT116_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT116_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT116_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT116_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT116_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT116_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT116_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT116_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT116_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT116_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT116_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT116_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT116_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT116_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT116_TOG_BUSY2_SHIFT 31 -/* PRE116 Bit Fields */ -#define CCM_PRE116_PRE_PODF_B_MASK 0x7u -#define CCM_PRE116_PRE_PODF_B_SHIFT 0 -#define CCM_PRE116_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE116_PRE_PODF_B_SHIFT))&CCM_PRE116_PRE_PODF_B_MASK) -#define CCM_PRE116_BUSY0_MASK 0x8u -#define CCM_PRE116_BUSY0_SHIFT 3 -#define CCM_PRE116_MUX_B_MASK 0x700u -#define CCM_PRE116_MUX_B_SHIFT 8 -#define CCM_PRE116_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE116_MUX_B_SHIFT))&CCM_PRE116_MUX_B_MASK) -#define CCM_PRE116_EN_B_MASK 0x1000u -#define CCM_PRE116_EN_B_SHIFT 12 -#define CCM_PRE116_BUSY1_MASK 0x8000u -#define CCM_PRE116_BUSY1_SHIFT 15 -#define CCM_PRE116_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE116_PRE_PODF_A_SHIFT 16 -#define CCM_PRE116_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE116_PRE_PODF_A_SHIFT))&CCM_PRE116_PRE_PODF_A_MASK) -#define CCM_PRE116_BUSY3_MASK 0x80000u -#define CCM_PRE116_BUSY3_SHIFT 19 -#define CCM_PRE116_MUX_A_MASK 0x7000000u -#define CCM_PRE116_MUX_A_SHIFT 24 -#define CCM_PRE116_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE116_MUX_A_SHIFT))&CCM_PRE116_MUX_A_MASK) -#define CCM_PRE116_EN_A_MASK 0x10000000u -#define CCM_PRE116_EN_A_SHIFT 28 -#define CCM_PRE116_BUSY4_MASK 0x80000000u -#define CCM_PRE116_BUSY4_SHIFT 31 -/* PRE_ROOT116_SET Bit Fields */ -#define CCM_PRE_ROOT116_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT116_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT116_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT116_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT116_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT116_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT116_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT116_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT116_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_SET_MUX_B_SHIFT))&CCM_PRE_ROOT116_SET_MUX_B_MASK) -#define CCM_PRE_ROOT116_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT116_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT116_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT116_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT116_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT116_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT116_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT116_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT116_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT116_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT116_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT116_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT116_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_SET_MUX_A_SHIFT))&CCM_PRE_ROOT116_SET_MUX_A_MASK) -#define CCM_PRE_ROOT116_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT116_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT116_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT116_SET_BUSY4_SHIFT 31 -/* PRE_ROOT116_CLR Bit Fields */ -#define CCM_PRE_ROOT116_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT116_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT116_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT116_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT116_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT116_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT116_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT116_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT116_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT116_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT116_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT116_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT116_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT116_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT116_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT116_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT116_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT116_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT116_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT116_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT116_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT116_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT116_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT116_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT116_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT116_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT116_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT116_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT116_TOG Bit Fields */ -#define CCM_PRE_ROOT116_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT116_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT116_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT116_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT116_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT116_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT116_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT116_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT116_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT116_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT116_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT116_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT116_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT116_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT116_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT116_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT116_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT116_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT116_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT116_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT116_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT116_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT116_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT116_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT116_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT116_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT116_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT116_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL116 Bit Fields */ -#define CCM_ACCESS_CTRL116_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL116_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL116_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL116_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL116_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL116_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL116_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL116_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL116_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL116_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL116_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL116_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL116_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL116_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL116_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL116_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL116_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL116_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL116_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL116_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL116_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL116_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL116_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL116_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL116_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL116_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL116_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL116_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL116_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL116_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL116_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL116_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL116_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL116_LOCK_SHIFT 31 -/* ACCESS_CTRL116_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL116_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL116_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL116_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL116_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL116_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL116_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL116_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL116_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL116_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL116_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL116_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL116_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL116_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL116_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL116_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL116_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT117 Bit Fields */ -#define CCM_TARGET_ROOT117_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT117_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT117_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_POST_PODF_SHIFT))&CCM_TARGET_ROOT117_POST_PODF_MASK) -#define CCM_TARGET_ROOT117_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT117_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT117_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT117_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT117_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT117_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT117_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT117_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT117_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT117_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT117_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_PRE_PODF_SHIFT))&CCM_TARGET_ROOT117_PRE_PODF_MASK) -#define CCM_TARGET_ROOT117_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT117_MUX_SHIFT 24 -#define CCM_TARGET_ROOT117_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_MUX_SHIFT))&CCM_TARGET_ROOT117_MUX_MASK) -#define CCM_TARGET_ROOT117_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT117_ENABLE_SHIFT 28 -/* TARGET_ROOT117_SET Bit Fields */ -#define CCM_TARGET_ROOT117_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT117_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT117_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT117_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT117_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT117_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT117_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT117_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT117_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT117_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT117_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT117_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT117_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT117_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT117_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT117_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT117_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT117_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT117_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_SET_MUX_SHIFT))&CCM_TARGET_ROOT117_SET_MUX_MASK) -#define CCM_TARGET_ROOT117_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT117_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT117_CLR Bit Fields */ -#define CCM_TARGET_ROOT117_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT117_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT117_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT117_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT117_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT117_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT117_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT117_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT117_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT117_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT117_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT117_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT117_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT117_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT117_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT117_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT117_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT117_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT117_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_CLR_MUX_SHIFT))&CCM_TARGET_ROOT117_CLR_MUX_MASK) -#define CCM_TARGET_ROOT117_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT117_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT117_TOG Bit Fields */ -#define CCM_TARGET_ROOT117_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT117_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT117_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT117_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT117_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT117_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT117_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT117_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT117_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT117_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT117_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT117_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT117_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT117_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT117_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT117_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT117_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT117_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT117_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_TOG_MUX_SHIFT))&CCM_TARGET_ROOT117_TOG_MUX_MASK) -#define CCM_TARGET_ROOT117_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT117_TOG_ENABLE_SHIFT 28 -/* POST117 Bit Fields */ -#define CCM_POST117_POST_PODF_MASK 0x3Fu -#define CCM_POST117_POST_PODF_SHIFT 0 -#define CCM_POST117_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST117_POST_PODF_SHIFT))&CCM_POST117_POST_PODF_MASK) -#define CCM_POST117_BUSY1_MASK 0x80u -#define CCM_POST117_BUSY1_SHIFT 7 -#define CCM_POST117_AUTO_PODF_MASK 0x700u -#define CCM_POST117_AUTO_PODF_SHIFT 8 -#define CCM_POST117_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST117_AUTO_PODF_SHIFT))&CCM_POST117_AUTO_PODF_MASK) -#define CCM_POST117_AUTO_EN_MASK 0x1000u -#define CCM_POST117_AUTO_EN_SHIFT 12 -#define CCM_POST117_SLOW_MASK 0x8000u -#define CCM_POST117_SLOW_SHIFT 15 -#define CCM_POST117_SELECT_MASK 0x10000000u -#define CCM_POST117_SELECT_SHIFT 28 -#define CCM_POST117_BUSY2_MASK 0x80000000u -#define CCM_POST117_BUSY2_SHIFT 31 -/* POST_ROOT117_SET Bit Fields */ -#define CCM_POST_ROOT117_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT117_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT117_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_SET_POST_PODF_SHIFT))&CCM_POST_ROOT117_SET_POST_PODF_MASK) -#define CCM_POST_ROOT117_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT117_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT117_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT117_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT117_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT117_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT117_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT117_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT117_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT117_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT117_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT117_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT117_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT117_SET_BUSY2_SHIFT 31 -/* POST_ROOT117_CLR Bit Fields */ -#define CCM_POST_ROOT117_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT117_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT117_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT117_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT117_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT117_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT117_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT117_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT117_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT117_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT117_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT117_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT117_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT117_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT117_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT117_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT117_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT117_CLR_BUSY2_SHIFT 31 -/* POST_ROOT117_TOG Bit Fields */ -#define CCM_POST_ROOT117_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT117_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT117_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT117_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT117_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT117_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT117_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT117_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT117_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT117_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT117_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT117_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT117_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT117_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT117_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT117_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT117_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT117_TOG_BUSY2_SHIFT 31 -/* PRE117 Bit Fields */ -#define CCM_PRE117_PRE_PODF_B_MASK 0x7u -#define CCM_PRE117_PRE_PODF_B_SHIFT 0 -#define CCM_PRE117_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE117_PRE_PODF_B_SHIFT))&CCM_PRE117_PRE_PODF_B_MASK) -#define CCM_PRE117_BUSY0_MASK 0x8u -#define CCM_PRE117_BUSY0_SHIFT 3 -#define CCM_PRE117_MUX_B_MASK 0x700u -#define CCM_PRE117_MUX_B_SHIFT 8 -#define CCM_PRE117_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE117_MUX_B_SHIFT))&CCM_PRE117_MUX_B_MASK) -#define CCM_PRE117_EN_B_MASK 0x1000u -#define CCM_PRE117_EN_B_SHIFT 12 -#define CCM_PRE117_BUSY1_MASK 0x8000u -#define CCM_PRE117_BUSY1_SHIFT 15 -#define CCM_PRE117_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE117_PRE_PODF_A_SHIFT 16 -#define CCM_PRE117_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE117_PRE_PODF_A_SHIFT))&CCM_PRE117_PRE_PODF_A_MASK) -#define CCM_PRE117_BUSY3_MASK 0x80000u -#define CCM_PRE117_BUSY3_SHIFT 19 -#define CCM_PRE117_MUX_A_MASK 0x7000000u -#define CCM_PRE117_MUX_A_SHIFT 24 -#define CCM_PRE117_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE117_MUX_A_SHIFT))&CCM_PRE117_MUX_A_MASK) -#define CCM_PRE117_EN_A_MASK 0x10000000u -#define CCM_PRE117_EN_A_SHIFT 28 -#define CCM_PRE117_BUSY4_MASK 0x80000000u -#define CCM_PRE117_BUSY4_SHIFT 31 -/* PRE_ROOT117_SET Bit Fields */ -#define CCM_PRE_ROOT117_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT117_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT117_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT117_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT117_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT117_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT117_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT117_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT117_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_SET_MUX_B_SHIFT))&CCM_PRE_ROOT117_SET_MUX_B_MASK) -#define CCM_PRE_ROOT117_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT117_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT117_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT117_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT117_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT117_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT117_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT117_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT117_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT117_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT117_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT117_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT117_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_SET_MUX_A_SHIFT))&CCM_PRE_ROOT117_SET_MUX_A_MASK) -#define CCM_PRE_ROOT117_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT117_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT117_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT117_SET_BUSY4_SHIFT 31 -/* PRE_ROOT117_CLR Bit Fields */ -#define CCM_PRE_ROOT117_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT117_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT117_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT117_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT117_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT117_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT117_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT117_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT117_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT117_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT117_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT117_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT117_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT117_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT117_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT117_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT117_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT117_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT117_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT117_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT117_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT117_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT117_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT117_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT117_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT117_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT117_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT117_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT117_TOG Bit Fields */ -#define CCM_PRE_ROOT117_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT117_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT117_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT117_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT117_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT117_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT117_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT117_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT117_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT117_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT117_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT117_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT117_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT117_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT117_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT117_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT117_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT117_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT117_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT117_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT117_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT117_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT117_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT117_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT117_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT117_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT117_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT117_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL117 Bit Fields */ -#define CCM_ACCESS_CTRL117_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL117_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL117_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL117_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL117_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL117_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL117_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL117_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL117_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL117_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL117_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL117_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL117_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL117_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL117_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL117_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL117_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL117_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL117_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL117_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL117_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL117_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL117_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL117_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL117_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL117_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL117_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL117_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL117_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL117_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL117_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL117_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL117_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL117_LOCK_SHIFT 31 -/* ACCESS_CTRL117_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL117_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL117_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL117_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL117_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL117_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL117_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL117_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL117_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL117_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL117_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL117_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL117_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL117_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL117_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL117_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL117_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT118 Bit Fields */ -#define CCM_TARGET_ROOT118_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT118_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT118_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_POST_PODF_SHIFT))&CCM_TARGET_ROOT118_POST_PODF_MASK) -#define CCM_TARGET_ROOT118_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT118_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT118_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT118_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT118_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT118_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT118_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT118_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT118_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT118_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT118_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_PRE_PODF_SHIFT))&CCM_TARGET_ROOT118_PRE_PODF_MASK) -#define CCM_TARGET_ROOT118_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT118_MUX_SHIFT 24 -#define CCM_TARGET_ROOT118_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_MUX_SHIFT))&CCM_TARGET_ROOT118_MUX_MASK) -#define CCM_TARGET_ROOT118_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT118_ENABLE_SHIFT 28 -/* TARGET_ROOT118_SET Bit Fields */ -#define CCM_TARGET_ROOT118_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT118_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT118_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT118_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT118_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT118_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT118_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT118_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT118_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT118_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT118_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT118_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT118_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT118_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT118_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT118_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT118_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT118_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT118_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_SET_MUX_SHIFT))&CCM_TARGET_ROOT118_SET_MUX_MASK) -#define CCM_TARGET_ROOT118_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT118_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT118_CLR Bit Fields */ -#define CCM_TARGET_ROOT118_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT118_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT118_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT118_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT118_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT118_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT118_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT118_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT118_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT118_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT118_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT118_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT118_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT118_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT118_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT118_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT118_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT118_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT118_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_CLR_MUX_SHIFT))&CCM_TARGET_ROOT118_CLR_MUX_MASK) -#define CCM_TARGET_ROOT118_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT118_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT118_TOG Bit Fields */ -#define CCM_TARGET_ROOT118_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT118_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT118_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT118_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT118_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT118_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT118_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT118_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT118_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT118_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT118_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT118_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT118_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT118_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT118_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT118_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT118_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT118_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT118_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_TOG_MUX_SHIFT))&CCM_TARGET_ROOT118_TOG_MUX_MASK) -#define CCM_TARGET_ROOT118_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT118_TOG_ENABLE_SHIFT 28 -/* POST118 Bit Fields */ -#define CCM_POST118_POST_PODF_MASK 0x3Fu -#define CCM_POST118_POST_PODF_SHIFT 0 -#define CCM_POST118_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST118_POST_PODF_SHIFT))&CCM_POST118_POST_PODF_MASK) -#define CCM_POST118_BUSY1_MASK 0x80u -#define CCM_POST118_BUSY1_SHIFT 7 -#define CCM_POST118_AUTO_PODF_MASK 0x700u -#define CCM_POST118_AUTO_PODF_SHIFT 8 -#define CCM_POST118_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST118_AUTO_PODF_SHIFT))&CCM_POST118_AUTO_PODF_MASK) -#define CCM_POST118_AUTO_EN_MASK 0x1000u -#define CCM_POST118_AUTO_EN_SHIFT 12 -#define CCM_POST118_SLOW_MASK 0x8000u -#define CCM_POST118_SLOW_SHIFT 15 -#define CCM_POST118_SELECT_MASK 0x10000000u -#define CCM_POST118_SELECT_SHIFT 28 -#define CCM_POST118_BUSY2_MASK 0x80000000u -#define CCM_POST118_BUSY2_SHIFT 31 -/* POST_ROOT118_SET Bit Fields */ -#define CCM_POST_ROOT118_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT118_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT118_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_SET_POST_PODF_SHIFT))&CCM_POST_ROOT118_SET_POST_PODF_MASK) -#define CCM_POST_ROOT118_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT118_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT118_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT118_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT118_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT118_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT118_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT118_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT118_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT118_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT118_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT118_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT118_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT118_SET_BUSY2_SHIFT 31 -/* POST_ROOT118_CLR Bit Fields */ -#define CCM_POST_ROOT118_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT118_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT118_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT118_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT118_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT118_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT118_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT118_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT118_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT118_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT118_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT118_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT118_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT118_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT118_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT118_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT118_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT118_CLR_BUSY2_SHIFT 31 -/* POST_ROOT118_TOG Bit Fields */ -#define CCM_POST_ROOT118_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT118_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT118_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT118_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT118_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT118_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT118_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT118_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT118_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT118_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT118_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT118_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT118_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT118_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT118_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT118_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT118_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT118_TOG_BUSY2_SHIFT 31 -/* PRE118 Bit Fields */ -#define CCM_PRE118_PRE_PODF_B_MASK 0x7u -#define CCM_PRE118_PRE_PODF_B_SHIFT 0 -#define CCM_PRE118_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE118_PRE_PODF_B_SHIFT))&CCM_PRE118_PRE_PODF_B_MASK) -#define CCM_PRE118_BUSY0_MASK 0x8u -#define CCM_PRE118_BUSY0_SHIFT 3 -#define CCM_PRE118_MUX_B_MASK 0x700u -#define CCM_PRE118_MUX_B_SHIFT 8 -#define CCM_PRE118_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE118_MUX_B_SHIFT))&CCM_PRE118_MUX_B_MASK) -#define CCM_PRE118_EN_B_MASK 0x1000u -#define CCM_PRE118_EN_B_SHIFT 12 -#define CCM_PRE118_BUSY1_MASK 0x8000u -#define CCM_PRE118_BUSY1_SHIFT 15 -#define CCM_PRE118_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE118_PRE_PODF_A_SHIFT 16 -#define CCM_PRE118_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE118_PRE_PODF_A_SHIFT))&CCM_PRE118_PRE_PODF_A_MASK) -#define CCM_PRE118_BUSY3_MASK 0x80000u -#define CCM_PRE118_BUSY3_SHIFT 19 -#define CCM_PRE118_MUX_A_MASK 0x7000000u -#define CCM_PRE118_MUX_A_SHIFT 24 -#define CCM_PRE118_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE118_MUX_A_SHIFT))&CCM_PRE118_MUX_A_MASK) -#define CCM_PRE118_EN_A_MASK 0x10000000u -#define CCM_PRE118_EN_A_SHIFT 28 -#define CCM_PRE118_BUSY4_MASK 0x80000000u -#define CCM_PRE118_BUSY4_SHIFT 31 -/* PRE_ROOT118_SET Bit Fields */ -#define CCM_PRE_ROOT118_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT118_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT118_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT118_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT118_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT118_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT118_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT118_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT118_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_SET_MUX_B_SHIFT))&CCM_PRE_ROOT118_SET_MUX_B_MASK) -#define CCM_PRE_ROOT118_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT118_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT118_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT118_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT118_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT118_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT118_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT118_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT118_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT118_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT118_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT118_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT118_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_SET_MUX_A_SHIFT))&CCM_PRE_ROOT118_SET_MUX_A_MASK) -#define CCM_PRE_ROOT118_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT118_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT118_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT118_SET_BUSY4_SHIFT 31 -/* PRE_ROOT118_CLR Bit Fields */ -#define CCM_PRE_ROOT118_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT118_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT118_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT118_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT118_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT118_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT118_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT118_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT118_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT118_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT118_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT118_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT118_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT118_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT118_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT118_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT118_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT118_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT118_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT118_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT118_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT118_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT118_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT118_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT118_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT118_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT118_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT118_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT118_TOG Bit Fields */ -#define CCM_PRE_ROOT118_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT118_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT118_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT118_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT118_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT118_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT118_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT118_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT118_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT118_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT118_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT118_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT118_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT118_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT118_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT118_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT118_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT118_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT118_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT118_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT118_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT118_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT118_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT118_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT118_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT118_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT118_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT118_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL118 Bit Fields */ -#define CCM_ACCESS_CTRL118_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL118_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL118_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL118_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL118_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL118_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL118_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL118_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL118_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL118_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL118_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL118_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL118_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL118_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL118_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL118_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL118_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL118_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL118_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL118_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL118_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL118_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL118_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL118_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL118_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL118_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL118_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL118_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL118_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL118_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL118_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL118_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL118_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL118_LOCK_SHIFT 31 -/* ACCESS_CTRL118_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL118_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL118_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL118_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL118_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL118_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL118_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL118_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL118_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL118_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL118_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL118_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL118_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL118_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL118_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL118_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL118_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT119 Bit Fields */ -#define CCM_TARGET_ROOT119_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT119_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT119_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_POST_PODF_SHIFT))&CCM_TARGET_ROOT119_POST_PODF_MASK) -#define CCM_TARGET_ROOT119_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT119_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT119_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT119_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT119_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT119_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT119_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT119_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT119_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT119_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT119_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_PRE_PODF_SHIFT))&CCM_TARGET_ROOT119_PRE_PODF_MASK) -#define CCM_TARGET_ROOT119_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT119_MUX_SHIFT 24 -#define CCM_TARGET_ROOT119_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_MUX_SHIFT))&CCM_TARGET_ROOT119_MUX_MASK) -#define CCM_TARGET_ROOT119_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT119_ENABLE_SHIFT 28 -/* TARGET_ROOT119_SET Bit Fields */ -#define CCM_TARGET_ROOT119_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT119_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT119_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT119_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT119_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT119_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT119_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT119_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT119_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT119_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT119_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT119_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT119_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT119_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT119_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT119_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT119_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT119_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT119_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_SET_MUX_SHIFT))&CCM_TARGET_ROOT119_SET_MUX_MASK) -#define CCM_TARGET_ROOT119_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT119_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT119_CLR Bit Fields */ -#define CCM_TARGET_ROOT119_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT119_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT119_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT119_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT119_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT119_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT119_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT119_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT119_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT119_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT119_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT119_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT119_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT119_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT119_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT119_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT119_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT119_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT119_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_CLR_MUX_SHIFT))&CCM_TARGET_ROOT119_CLR_MUX_MASK) -#define CCM_TARGET_ROOT119_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT119_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT119_TOG Bit Fields */ -#define CCM_TARGET_ROOT119_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT119_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT119_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT119_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT119_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT119_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT119_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT119_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT119_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT119_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT119_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT119_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT119_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT119_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT119_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT119_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT119_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT119_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT119_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_TOG_MUX_SHIFT))&CCM_TARGET_ROOT119_TOG_MUX_MASK) -#define CCM_TARGET_ROOT119_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT119_TOG_ENABLE_SHIFT 28 -/* POST119 Bit Fields */ -#define CCM_POST119_POST_PODF_MASK 0x3Fu -#define CCM_POST119_POST_PODF_SHIFT 0 -#define CCM_POST119_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST119_POST_PODF_SHIFT))&CCM_POST119_POST_PODF_MASK) -#define CCM_POST119_BUSY1_MASK 0x80u -#define CCM_POST119_BUSY1_SHIFT 7 -#define CCM_POST119_AUTO_PODF_MASK 0x700u -#define CCM_POST119_AUTO_PODF_SHIFT 8 -#define CCM_POST119_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST119_AUTO_PODF_SHIFT))&CCM_POST119_AUTO_PODF_MASK) -#define CCM_POST119_AUTO_EN_MASK 0x1000u -#define CCM_POST119_AUTO_EN_SHIFT 12 -#define CCM_POST119_SLOW_MASK 0x8000u -#define CCM_POST119_SLOW_SHIFT 15 -#define CCM_POST119_SELECT_MASK 0x10000000u -#define CCM_POST119_SELECT_SHIFT 28 -#define CCM_POST119_BUSY2_MASK 0x80000000u -#define CCM_POST119_BUSY2_SHIFT 31 -/* POST_ROOT119_SET Bit Fields */ -#define CCM_POST_ROOT119_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT119_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT119_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_SET_POST_PODF_SHIFT))&CCM_POST_ROOT119_SET_POST_PODF_MASK) -#define CCM_POST_ROOT119_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT119_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT119_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT119_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT119_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT119_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT119_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT119_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT119_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT119_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT119_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT119_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT119_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT119_SET_BUSY2_SHIFT 31 -/* POST_ROOT119_CLR Bit Fields */ -#define CCM_POST_ROOT119_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT119_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT119_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT119_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT119_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT119_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT119_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT119_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT119_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT119_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT119_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT119_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT119_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT119_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT119_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT119_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT119_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT119_CLR_BUSY2_SHIFT 31 -/* POST_ROOT119_TOG Bit Fields */ -#define CCM_POST_ROOT119_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT119_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT119_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT119_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT119_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT119_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT119_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT119_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT119_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT119_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT119_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT119_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT119_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT119_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT119_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT119_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT119_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT119_TOG_BUSY2_SHIFT 31 -/* PRE119 Bit Fields */ -#define CCM_PRE119_PRE_PODF_B_MASK 0x7u -#define CCM_PRE119_PRE_PODF_B_SHIFT 0 -#define CCM_PRE119_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE119_PRE_PODF_B_SHIFT))&CCM_PRE119_PRE_PODF_B_MASK) -#define CCM_PRE119_BUSY0_MASK 0x8u -#define CCM_PRE119_BUSY0_SHIFT 3 -#define CCM_PRE119_MUX_B_MASK 0x700u -#define CCM_PRE119_MUX_B_SHIFT 8 -#define CCM_PRE119_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE119_MUX_B_SHIFT))&CCM_PRE119_MUX_B_MASK) -#define CCM_PRE119_EN_B_MASK 0x1000u -#define CCM_PRE119_EN_B_SHIFT 12 -#define CCM_PRE119_BUSY1_MASK 0x8000u -#define CCM_PRE119_BUSY1_SHIFT 15 -#define CCM_PRE119_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE119_PRE_PODF_A_SHIFT 16 -#define CCM_PRE119_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE119_PRE_PODF_A_SHIFT))&CCM_PRE119_PRE_PODF_A_MASK) -#define CCM_PRE119_BUSY3_MASK 0x80000u -#define CCM_PRE119_BUSY3_SHIFT 19 -#define CCM_PRE119_MUX_A_MASK 0x7000000u -#define CCM_PRE119_MUX_A_SHIFT 24 -#define CCM_PRE119_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE119_MUX_A_SHIFT))&CCM_PRE119_MUX_A_MASK) -#define CCM_PRE119_EN_A_MASK 0x10000000u -#define CCM_PRE119_EN_A_SHIFT 28 -#define CCM_PRE119_BUSY4_MASK 0x80000000u -#define CCM_PRE119_BUSY4_SHIFT 31 -/* PRE_ROOT119_SET Bit Fields */ -#define CCM_PRE_ROOT119_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT119_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT119_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT119_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT119_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT119_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT119_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT119_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT119_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_SET_MUX_B_SHIFT))&CCM_PRE_ROOT119_SET_MUX_B_MASK) -#define CCM_PRE_ROOT119_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT119_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT119_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT119_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT119_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT119_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT119_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT119_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT119_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT119_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT119_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT119_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT119_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_SET_MUX_A_SHIFT))&CCM_PRE_ROOT119_SET_MUX_A_MASK) -#define CCM_PRE_ROOT119_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT119_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT119_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT119_SET_BUSY4_SHIFT 31 -/* PRE_ROOT119_CLR Bit Fields */ -#define CCM_PRE_ROOT119_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT119_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT119_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT119_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT119_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT119_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT119_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT119_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT119_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT119_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT119_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT119_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT119_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT119_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT119_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT119_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT119_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT119_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT119_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT119_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT119_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT119_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT119_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT119_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT119_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT119_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT119_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT119_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT119_TOG Bit Fields */ -#define CCM_PRE_ROOT119_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT119_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT119_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT119_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT119_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT119_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT119_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT119_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT119_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT119_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT119_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT119_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT119_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT119_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT119_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT119_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT119_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT119_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT119_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT119_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT119_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT119_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT119_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT119_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT119_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT119_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT119_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT119_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL119 Bit Fields */ -#define CCM_ACCESS_CTRL119_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL119_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL119_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL119_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL119_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL119_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL119_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL119_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL119_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL119_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL119_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL119_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL119_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL119_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL119_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL119_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL119_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL119_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL119_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL119_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL119_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL119_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL119_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL119_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL119_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL119_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL119_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL119_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL119_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL119_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL119_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL119_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL119_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL119_LOCK_SHIFT 31 -/* ACCESS_CTRL119_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL119_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL119_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL119_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL119_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL119_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL119_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL119_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL119_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL119_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL119_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL119_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL119_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL119_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL119_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL119_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL119_ROOT_TOG_LOCK_SHIFT 31 -/* TARGET_ROOT120 Bit Fields */ -#define CCM_TARGET_ROOT120_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT120_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT120_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_POST_PODF_SHIFT))&CCM_TARGET_ROOT120_POST_PODF_MASK) -#define CCM_TARGET_ROOT120_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT120_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT120_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT120_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT120_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT120_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT120_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT120_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT120_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT120_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT120_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_PRE_PODF_SHIFT))&CCM_TARGET_ROOT120_PRE_PODF_MASK) -#define CCM_TARGET_ROOT120_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT120_MUX_SHIFT 24 -#define CCM_TARGET_ROOT120_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_MUX_SHIFT))&CCM_TARGET_ROOT120_MUX_MASK) -#define CCM_TARGET_ROOT120_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT120_ENABLE_SHIFT 28 -/* TARGET_ROOT120_SET Bit Fields */ -#define CCM_TARGET_ROOT120_SET_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT120_SET_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT120_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT120_SET_POST_PODF_MASK) -#define CCM_TARGET_ROOT120_SET_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT120_SET_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT120_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT120_SET_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT120_SET_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT120_SET_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT120_SET_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT120_SET_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT120_SET_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT120_SET_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT120_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT120_SET_PRE_PODF_MASK) -#define CCM_TARGET_ROOT120_SET_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT120_SET_MUX_SHIFT 24 -#define CCM_TARGET_ROOT120_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_SET_MUX_SHIFT))&CCM_TARGET_ROOT120_SET_MUX_MASK) -#define CCM_TARGET_ROOT120_SET_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT120_SET_ENABLE_SHIFT 28 -/* TARGET_ROOT120_CLR Bit Fields */ -#define CCM_TARGET_ROOT120_CLR_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT120_CLR_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT120_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT120_CLR_POST_PODF_MASK) -#define CCM_TARGET_ROOT120_CLR_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT120_CLR_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT120_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT120_CLR_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT120_CLR_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT120_CLR_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT120_CLR_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT120_CLR_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT120_CLR_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT120_CLR_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT120_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT120_CLR_PRE_PODF_MASK) -#define CCM_TARGET_ROOT120_CLR_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT120_CLR_MUX_SHIFT 24 -#define CCM_TARGET_ROOT120_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_CLR_MUX_SHIFT))&CCM_TARGET_ROOT120_CLR_MUX_MASK) -#define CCM_TARGET_ROOT120_CLR_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT120_CLR_ENABLE_SHIFT 28 -/* TARGET_ROOT120_TOG Bit Fields */ -#define CCM_TARGET_ROOT120_TOG_POST_PODF_MASK 0x3Fu -#define CCM_TARGET_ROOT120_TOG_POST_PODF_SHIFT 0 -#define CCM_TARGET_ROOT120_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT120_TOG_POST_PODF_MASK) -#define CCM_TARGET_ROOT120_TOG_AUTO_PODF_MASK 0x700u -#define CCM_TARGET_ROOT120_TOG_AUTO_PODF_SHIFT 8 -#define CCM_TARGET_ROOT120_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT120_TOG_AUTO_PODF_MASK) -#define CCM_TARGET_ROOT120_TOG_AUTO_PODF_EN_MASK 0x1000u -#define CCM_TARGET_ROOT120_TOG_AUTO_PODF_EN_SHIFT 12 -#define CCM_TARGET_ROOT120_TOG_SLOW_MASK 0x8000u -#define CCM_TARGET_ROOT120_TOG_SLOW_SHIFT 15 -#define CCM_TARGET_ROOT120_TOG_PRE_PODF_MASK 0x70000u -#define CCM_TARGET_ROOT120_TOG_PRE_PODF_SHIFT 16 -#define CCM_TARGET_ROOT120_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT120_TOG_PRE_PODF_MASK) -#define CCM_TARGET_ROOT120_TOG_MUX_MASK 0x7000000u -#define CCM_TARGET_ROOT120_TOG_MUX_SHIFT 24 -#define CCM_TARGET_ROOT120_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_TOG_MUX_SHIFT))&CCM_TARGET_ROOT120_TOG_MUX_MASK) -#define CCM_TARGET_ROOT120_TOG_ENABLE_MASK 0x10000000u -#define CCM_TARGET_ROOT120_TOG_ENABLE_SHIFT 28 -/* POST120 Bit Fields */ -#define CCM_POST120_POST_PODF_MASK 0x3Fu -#define CCM_POST120_POST_PODF_SHIFT 0 -#define CCM_POST120_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST120_POST_PODF_SHIFT))&CCM_POST120_POST_PODF_MASK) -#define CCM_POST120_BUSY1_MASK 0x80u -#define CCM_POST120_BUSY1_SHIFT 7 -#define CCM_POST120_AUTO_PODF_MASK 0x700u -#define CCM_POST120_AUTO_PODF_SHIFT 8 -#define CCM_POST120_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST120_AUTO_PODF_SHIFT))&CCM_POST120_AUTO_PODF_MASK) -#define CCM_POST120_AUTO_EN_MASK 0x1000u -#define CCM_POST120_AUTO_EN_SHIFT 12 -#define CCM_POST120_SLOW_MASK 0x8000u -#define CCM_POST120_SLOW_SHIFT 15 -#define CCM_POST120_SELECT_MASK 0x10000000u -#define CCM_POST120_SELECT_SHIFT 28 -#define CCM_POST120_BUSY2_MASK 0x80000000u -#define CCM_POST120_BUSY2_SHIFT 31 -/* POST_ROOT120_SET Bit Fields */ -#define CCM_POST_ROOT120_SET_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT120_SET_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT120_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_SET_POST_PODF_SHIFT))&CCM_POST_ROOT120_SET_POST_PODF_MASK) -#define CCM_POST_ROOT120_SET_BUSY1_MASK 0x80u -#define CCM_POST_ROOT120_SET_BUSY1_SHIFT 7 -#define CCM_POST_ROOT120_SET_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT120_SET_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT120_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT120_SET_AUTO_PODF_MASK) -#define CCM_POST_ROOT120_SET_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT120_SET_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT120_SET_SLOW_MASK 0x8000u -#define CCM_POST_ROOT120_SET_SLOW_SHIFT 15 -#define CCM_POST_ROOT120_SET_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT120_SET_SELECT_SHIFT 28 -#define CCM_POST_ROOT120_SET_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT120_SET_BUSY2_SHIFT 31 -/* POST_ROOT120_CLR Bit Fields */ -#define CCM_POST_ROOT120_CLR_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT120_CLR_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT120_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT120_CLR_POST_PODF_MASK) -#define CCM_POST_ROOT120_CLR_BUSY1_MASK 0x80u -#define CCM_POST_ROOT120_CLR_BUSY1_SHIFT 7 -#define CCM_POST_ROOT120_CLR_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT120_CLR_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT120_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT120_CLR_AUTO_PODF_MASK) -#define CCM_POST_ROOT120_CLR_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT120_CLR_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT120_CLR_SLOW_MASK 0x8000u -#define CCM_POST_ROOT120_CLR_SLOW_SHIFT 15 -#define CCM_POST_ROOT120_CLR_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT120_CLR_SELECT_SHIFT 28 -#define CCM_POST_ROOT120_CLR_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT120_CLR_BUSY2_SHIFT 31 -/* POST_ROOT120_TOG Bit Fields */ -#define CCM_POST_ROOT120_TOG_POST_PODF_MASK 0x3Fu -#define CCM_POST_ROOT120_TOG_POST_PODF_SHIFT 0 -#define CCM_POST_ROOT120_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT120_TOG_POST_PODF_MASK) -#define CCM_POST_ROOT120_TOG_BUSY1_MASK 0x80u -#define CCM_POST_ROOT120_TOG_BUSY1_SHIFT 7 -#define CCM_POST_ROOT120_TOG_AUTO_PODF_MASK 0x700u -#define CCM_POST_ROOT120_TOG_AUTO_PODF_SHIFT 8 -#define CCM_POST_ROOT120_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT120_TOG_AUTO_PODF_MASK) -#define CCM_POST_ROOT120_TOG_AUTO_EN_MASK 0x1000u -#define CCM_POST_ROOT120_TOG_AUTO_EN_SHIFT 12 -#define CCM_POST_ROOT120_TOG_SLOW_MASK 0x8000u -#define CCM_POST_ROOT120_TOG_SLOW_SHIFT 15 -#define CCM_POST_ROOT120_TOG_SELECT_MASK 0x10000000u -#define CCM_POST_ROOT120_TOG_SELECT_SHIFT 28 -#define CCM_POST_ROOT120_TOG_BUSY2_MASK 0x80000000u -#define CCM_POST_ROOT120_TOG_BUSY2_SHIFT 31 -/* PRE120 Bit Fields */ -#define CCM_PRE120_PRE_PODF_B_MASK 0x7u -#define CCM_PRE120_PRE_PODF_B_SHIFT 0 -#define CCM_PRE120_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE120_PRE_PODF_B_SHIFT))&CCM_PRE120_PRE_PODF_B_MASK) -#define CCM_PRE120_BUSY0_MASK 0x8u -#define CCM_PRE120_BUSY0_SHIFT 3 -#define CCM_PRE120_MUX_B_MASK 0x700u -#define CCM_PRE120_MUX_B_SHIFT 8 -#define CCM_PRE120_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE120_MUX_B_SHIFT))&CCM_PRE120_MUX_B_MASK) -#define CCM_PRE120_EN_B_MASK 0x1000u -#define CCM_PRE120_EN_B_SHIFT 12 -#define CCM_PRE120_BUSY1_MASK 0x8000u -#define CCM_PRE120_BUSY1_SHIFT 15 -#define CCM_PRE120_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE120_PRE_PODF_A_SHIFT 16 -#define CCM_PRE120_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE120_PRE_PODF_A_SHIFT))&CCM_PRE120_PRE_PODF_A_MASK) -#define CCM_PRE120_BUSY3_MASK 0x80000u -#define CCM_PRE120_BUSY3_SHIFT 19 -#define CCM_PRE120_MUX_A_MASK 0x7000000u -#define CCM_PRE120_MUX_A_SHIFT 24 -#define CCM_PRE120_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE120_MUX_A_SHIFT))&CCM_PRE120_MUX_A_MASK) -#define CCM_PRE120_EN_A_MASK 0x10000000u -#define CCM_PRE120_EN_A_SHIFT 28 -#define CCM_PRE120_BUSY4_MASK 0x80000000u -#define CCM_PRE120_BUSY4_SHIFT 31 -/* PRE_ROOT120_SET Bit Fields */ -#define CCM_PRE_ROOT120_SET_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT120_SET_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT120_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT120_SET_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT120_SET_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT120_SET_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT120_SET_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT120_SET_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT120_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_SET_MUX_B_SHIFT))&CCM_PRE_ROOT120_SET_MUX_B_MASK) -#define CCM_PRE_ROOT120_SET_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT120_SET_EN_B_SHIFT 12 -#define CCM_PRE_ROOT120_SET_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT120_SET_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT120_SET_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT120_SET_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT120_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT120_SET_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT120_SET_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT120_SET_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT120_SET_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT120_SET_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT120_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_SET_MUX_A_SHIFT))&CCM_PRE_ROOT120_SET_MUX_A_MASK) -#define CCM_PRE_ROOT120_SET_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT120_SET_EN_A_SHIFT 28 -#define CCM_PRE_ROOT120_SET_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT120_SET_BUSY4_SHIFT 31 -/* PRE_ROOT120_CLR Bit Fields */ -#define CCM_PRE_ROOT120_CLR_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT120_CLR_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT120_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT120_CLR_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT120_CLR_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT120_CLR_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT120_CLR_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT120_CLR_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT120_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT120_CLR_MUX_B_MASK) -#define CCM_PRE_ROOT120_CLR_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT120_CLR_EN_B_SHIFT 12 -#define CCM_PRE_ROOT120_CLR_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT120_CLR_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT120_CLR_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT120_CLR_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT120_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT120_CLR_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT120_CLR_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT120_CLR_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT120_CLR_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT120_CLR_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT120_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT120_CLR_MUX_A_MASK) -#define CCM_PRE_ROOT120_CLR_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT120_CLR_EN_A_SHIFT 28 -#define CCM_PRE_ROOT120_CLR_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT120_CLR_BUSY4_SHIFT 31 -/* PRE_ROOT120_TOG Bit Fields */ -#define CCM_PRE_ROOT120_TOG_PRE_PODF_B_MASK 0x7u -#define CCM_PRE_ROOT120_TOG_PRE_PODF_B_SHIFT 0 -#define CCM_PRE_ROOT120_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT120_TOG_PRE_PODF_B_MASK) -#define CCM_PRE_ROOT120_TOG_BUSY0_MASK 0x8u -#define CCM_PRE_ROOT120_TOG_BUSY0_SHIFT 3 -#define CCM_PRE_ROOT120_TOG_MUX_B_MASK 0x700u -#define CCM_PRE_ROOT120_TOG_MUX_B_SHIFT 8 -#define CCM_PRE_ROOT120_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT120_TOG_MUX_B_MASK) -#define CCM_PRE_ROOT120_TOG_EN_B_MASK 0x1000u -#define CCM_PRE_ROOT120_TOG_EN_B_SHIFT 12 -#define CCM_PRE_ROOT120_TOG_BUSY1_MASK 0x8000u -#define CCM_PRE_ROOT120_TOG_BUSY1_SHIFT 15 -#define CCM_PRE_ROOT120_TOG_PRE_PODF_A_MASK 0x70000u -#define CCM_PRE_ROOT120_TOG_PRE_PODF_A_SHIFT 16 -#define CCM_PRE_ROOT120_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT120_TOG_PRE_PODF_A_MASK) -#define CCM_PRE_ROOT120_TOG_BUSY3_MASK 0x80000u -#define CCM_PRE_ROOT120_TOG_BUSY3_SHIFT 19 -#define CCM_PRE_ROOT120_TOG_MUX_A_MASK 0x7000000u -#define CCM_PRE_ROOT120_TOG_MUX_A_SHIFT 24 -#define CCM_PRE_ROOT120_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT120_TOG_MUX_A_MASK) -#define CCM_PRE_ROOT120_TOG_EN_A_MASK 0x10000000u -#define CCM_PRE_ROOT120_TOG_EN_A_SHIFT 28 -#define CCM_PRE_ROOT120_TOG_BUSY4_MASK 0x80000000u -#define CCM_PRE_ROOT120_TOG_BUSY4_SHIFT 31 -/* ACCESS_CTRL120 Bit Fields */ -#define CCM_ACCESS_CTRL120_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL120_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL120_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL120_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL120_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL120_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL120_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL120_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL120_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL120_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL120_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL120_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL120_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL120_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL120_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL120_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL120_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL120_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL120_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL120_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL120_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL120_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL120_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL120_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL120_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL120_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL120_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL120_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL120_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL120_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL120_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL120_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL120_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL120_LOCK_SHIFT 31 -/* ACCESS_CTRL120_ROOT_SET Bit Fields */ -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL120_ROOT_SET_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL120_ROOT_SET_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL120_ROOT_SET_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL120_ROOT_SET_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL120_ROOT_SET_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL120_ROOT_SET_LOCK_SHIFT 31 -/* ACCESS_CTRL120_ROOT_CLR Bit Fields */ -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL120_ROOT_CLR_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL120_ROOT_CLR_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL120_ROOT_CLR_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL120_ROOT_CLR_LOCK_SHIFT 31 -/* ACCESS_CTRL120_ROOT_TOG Bit Fields */ -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_MASK 0xFu -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_SHIFT 0 -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_MASK) -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_MASK 0xF0u -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_SHIFT 4 -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_MASK) -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_MASK 0xF00u -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_SHIFT 8 -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_MASK) -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_MASK 0xF000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_SHIFT 12 -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_MASK) -#define CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID_MASK 0x30000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID_SHIFT 16 -#define CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID_MASK) -#define CCM_ACCESS_CTRL120_ROOT_TOG_MUTEX_MASK 0x100000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_MUTEX_SHIFT 20 -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_1_SHIFT 24 -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_1_SHIFT 25 -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_1_SHIFT 26 -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_1_SHIFT 27 -#define CCM_ACCESS_CTRL120_ROOT_TOG_SEMA_EN_MASK 0x10000000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_SEMA_EN_SHIFT 28 -#define CCM_ACCESS_CTRL120_ROOT_TOG_LOCK_MASK 0x80000000u -#define CCM_ACCESS_CTRL120_ROOT_TOG_LOCK_SHIFT 31 +/* PLL_CTRL Bit Fields */ +#define CCM_PLL_CTRL_SETTING0_MASK 0x3u +#define CCM_PLL_CTRL_SETTING0_SHIFT 0 +#define CCM_PLL_CTRL_SETTING0(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SETTING0_SHIFT))&CCM_PLL_CTRL_SETTING0_MASK) +#define CCM_PLL_CTRL_SETTING1_MASK 0x30u +#define CCM_PLL_CTRL_SETTING1_SHIFT 4 +#define CCM_PLL_CTRL_SETTING1(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SETTING1_SHIFT))&CCM_PLL_CTRL_SETTING1_MASK) +#define CCM_PLL_CTRL_SETTING2_MASK 0x300u +#define CCM_PLL_CTRL_SETTING2_SHIFT 8 +#define CCM_PLL_CTRL_SETTING2(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SETTING2_SHIFT))&CCM_PLL_CTRL_SETTING2_MASK) +#define CCM_PLL_CTRL_SETTING3_MASK 0x3000u +#define CCM_PLL_CTRL_SETTING3_SHIFT 12 +#define CCM_PLL_CTRL_SETTING3(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SETTING3_SHIFT))&CCM_PLL_CTRL_SETTING3_MASK) +/* PLL_CTRL_SET Bit Fields */ +#define CCM_PLL_CTRL_SET_SETTING0_MASK 0x3u +#define CCM_PLL_CTRL_SET_SETTING0_SHIFT 0 +#define CCM_PLL_CTRL_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SET_SETTING0_SHIFT))&CCM_PLL_CTRL_SET_SETTING0_MASK) +#define CCM_PLL_CTRL_SET_SETTING1_MASK 0x30u +#define CCM_PLL_CTRL_SET_SETTING1_SHIFT 4 +#define CCM_PLL_CTRL_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SET_SETTING1_SHIFT))&CCM_PLL_CTRL_SET_SETTING1_MASK) +#define CCM_PLL_CTRL_SET_SETTING2_MASK 0x300u +#define CCM_PLL_CTRL_SET_SETTING2_SHIFT 8 +#define CCM_PLL_CTRL_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SET_SETTING2_SHIFT))&CCM_PLL_CTRL_SET_SETTING2_MASK) +#define CCM_PLL_CTRL_SET_SETTING3_MASK 0x3000u +#define CCM_PLL_CTRL_SET_SETTING3_SHIFT 12 +#define CCM_PLL_CTRL_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_SET_SETTING3_SHIFT))&CCM_PLL_CTRL_SET_SETTING3_MASK) +/* PLL_CTRL_CLR Bit Fields */ +#define CCM_PLL_CTRL_CLR_SETTING0_MASK 0x3u +#define CCM_PLL_CTRL_CLR_SETTING0_SHIFT 0 +#define CCM_PLL_CTRL_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_CLR_SETTING0_SHIFT))&CCM_PLL_CTRL_CLR_SETTING0_MASK) +#define CCM_PLL_CTRL_CLR_SETTING1_MASK 0x30u +#define CCM_PLL_CTRL_CLR_SETTING1_SHIFT 4 +#define CCM_PLL_CTRL_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_CLR_SETTING1_SHIFT))&CCM_PLL_CTRL_CLR_SETTING1_MASK) +#define CCM_PLL_CTRL_CLR_SETTING2_MASK 0x300u +#define CCM_PLL_CTRL_CLR_SETTING2_SHIFT 8 +#define CCM_PLL_CTRL_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_CLR_SETTING2_SHIFT))&CCM_PLL_CTRL_CLR_SETTING2_MASK) +#define CCM_PLL_CTRL_CLR_SETTING3_MASK 0x3000u +#define CCM_PLL_CTRL_CLR_SETTING3_SHIFT 12 +#define CCM_PLL_CTRL_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_CLR_SETTING3_SHIFT))&CCM_PLL_CTRL_CLR_SETTING3_MASK) +/* PLL_CTRL_TOG Bit Fields */ +#define CCM_PLL_CTRL_TOG_SETTING0_MASK 0x3u +#define CCM_PLL_CTRL_TOG_SETTING0_SHIFT 0 +#define CCM_PLL_CTRL_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_TOG_SETTING0_SHIFT))&CCM_PLL_CTRL_TOG_SETTING0_MASK) +#define CCM_PLL_CTRL_TOG_SETTING1_MASK 0x30u +#define CCM_PLL_CTRL_TOG_SETTING1_SHIFT 4 +#define CCM_PLL_CTRL_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_TOG_SETTING1_SHIFT))&CCM_PLL_CTRL_TOG_SETTING1_MASK) +#define CCM_PLL_CTRL_TOG_SETTING2_MASK 0x300u +#define CCM_PLL_CTRL_TOG_SETTING2_SHIFT 8 +#define CCM_PLL_CTRL_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_TOG_SETTING2_SHIFT))&CCM_PLL_CTRL_TOG_SETTING2_MASK) +#define CCM_PLL_CTRL_TOG_SETTING3_MASK 0x3000u +#define CCM_PLL_CTRL_TOG_SETTING3_SHIFT 12 +#define CCM_PLL_CTRL_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL_TOG_SETTING3_SHIFT))&CCM_PLL_CTRL_TOG_SETTING3_MASK) +/* CCGR Bit Fields */ +#define CCM_CCGR_SETTING0_MASK 0x3u +#define CCM_CCGR_SETTING0_SHIFT 0 +#define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SETTING0_SHIFT))&CCM_CCGR_SETTING0_MASK) +#define CCM_CCGR_SETTING1_MASK 0x30u +#define CCM_CCGR_SETTING1_SHIFT 4 +#define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SETTING1_SHIFT))&CCM_CCGR_SETTING1_MASK) +#define CCM_CCGR_SETTING2_MASK 0x300u +#define CCM_CCGR_SETTING2_SHIFT 8 +#define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SETTING2_SHIFT))&CCM_CCGR_SETTING2_MASK) +#define CCM_CCGR_SETTING3_MASK 0x3000u +#define CCM_CCGR_SETTING3_SHIFT 12 +#define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SETTING3_SHIFT))&CCM_CCGR_SETTING3_MASK) +/* CCGR_SET Bit Fields */ +#define CCM_CCGR_SET_SETTING0_MASK 0x3u +#define CCM_CCGR_SET_SETTING0_SHIFT 0 +#define CCM_CCGR_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SET_SETTING0_SHIFT))&CCM_CCGR_SET_SETTING0_MASK) +#define CCM_CCGR_SET_SETTING1_MASK 0x30u +#define CCM_CCGR_SET_SETTING1_SHIFT 4 +#define CCM_CCGR_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SET_SETTING1_SHIFT))&CCM_CCGR_SET_SETTING1_MASK) +#define CCM_CCGR_SET_SETTING2_MASK 0x300u +#define CCM_CCGR_SET_SETTING2_SHIFT 8 +#define CCM_CCGR_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SET_SETTING2_SHIFT))&CCM_CCGR_SET_SETTING2_MASK) +#define CCM_CCGR_SET_SETTING3_MASK 0x3000u +#define CCM_CCGR_SET_SETTING3_SHIFT 12 +#define CCM_CCGR_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_SET_SETTING3_SHIFT))&CCM_CCGR_SET_SETTING3_MASK) +/* CCGR_CLR Bit Fields */ +#define CCM_CCGR_CLR_SETTING0_MASK 0x3u +#define CCM_CCGR_CLR_SETTING0_SHIFT 0 +#define CCM_CCGR_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_CLR_SETTING0_SHIFT))&CCM_CCGR_CLR_SETTING0_MASK) +#define CCM_CCGR_CLR_SETTING1_MASK 0x30u +#define CCM_CCGR_CLR_SETTING1_SHIFT 4 +#define CCM_CCGR_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_CLR_SETTING1_SHIFT))&CCM_CCGR_CLR_SETTING1_MASK) +#define CCM_CCGR_CLR_SETTING2_MASK 0x300u +#define CCM_CCGR_CLR_SETTING2_SHIFT 8 +#define CCM_CCGR_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_CLR_SETTING2_SHIFT))&CCM_CCGR_CLR_SETTING2_MASK) +#define CCM_CCGR_CLR_SETTING3_MASK 0x3000u +#define CCM_CCGR_CLR_SETTING3_SHIFT 12 +#define CCM_CCGR_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_CLR_SETTING3_SHIFT))&CCM_CCGR_CLR_SETTING3_MASK) +/* CCGR_TOG Bit Fields */ +#define CCM_CCGR_TOG_SETTING0_MASK 0x3u +#define CCM_CCGR_TOG_SETTING0_SHIFT 0 +#define CCM_CCGR_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_TOG_SETTING0_SHIFT))&CCM_CCGR_TOG_SETTING0_MASK) +#define CCM_CCGR_TOG_SETTING1_MASK 0x30u +#define CCM_CCGR_TOG_SETTING1_SHIFT 4 +#define CCM_CCGR_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_TOG_SETTING1_SHIFT))&CCM_CCGR_TOG_SETTING1_MASK) +#define CCM_CCGR_TOG_SETTING2_MASK 0x300u +#define CCM_CCGR_TOG_SETTING2_SHIFT 8 +#define CCM_CCGR_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_TOG_SETTING2_SHIFT))&CCM_CCGR_TOG_SETTING2_MASK) +#define CCM_CCGR_TOG_SETTING3_MASK 0x3000u +#define CCM_CCGR_TOG_SETTING3_SHIFT 12 +#define CCM_CCGR_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR_TOG_SETTING3_SHIFT))&CCM_CCGR_TOG_SETTING3_MASK) +/* TARGET_ROOT Bit Fields */ +#define CCM_TARGET_ROOT_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_POST_PODF_SHIFT))&CCM_TARGET_ROOT_POST_PODF_MASK) +#define CCM_TARGET_ROOT_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_PRE_PODF_SHIFT))&CCM_TARGET_ROOT_PRE_PODF_MASK) +#define CCM_TARGET_ROOT_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT_MUX_SHIFT 24 +#define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_MUX_SHIFT))&CCM_TARGET_ROOT_MUX_MASK) +#define CCM_TARGET_ROOT_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT_ENABLE_SHIFT 28 +/* TARGET_ROOT_SET Bit Fields */ +#define CCM_TARGET_ROOT_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_SET_MUX_SHIFT))&CCM_TARGET_ROOT_SET_MUX_MASK) +#define CCM_TARGET_ROOT_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT_CLR Bit Fields */ +#define CCM_TARGET_ROOT_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_CLR_MUX_SHIFT))&CCM_TARGET_ROOT_CLR_MUX_MASK) +#define CCM_TARGET_ROOT_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT_TOG Bit Fields */ +#define CCM_TARGET_ROOT_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT_TOG_MUX_SHIFT))&CCM_TARGET_ROOT_TOG_MUX_MASK) +#define CCM_TARGET_ROOT_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT 28 +/* MISC Bit Fields */ +#define CCM_MISC_AUTHEN_FAIL_MASK 0x1u +#define CCM_MISC_AUTHEN_FAIL_SHIFT 0 +#define CCM_MISC_TIMEOUT_MASK 0x10u +#define CCM_MISC_TIMEOUT_SHIFT 4 +#define CCM_MISC_VIOLATE_MASK 0x100u +#define CCM_MISC_VIOLATE_SHIFT 8 +/* MISC_ROOT_SET Bit Fields */ +#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK 0x1u +#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT 0 +#define CCM_MISC_ROOT_SET_TIMEOUT_MASK 0x10u +#define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT 4 +#define CCM_MISC_ROOT_SET_VIOLATE_MASK 0x100u +#define CCM_MISC_ROOT_SET_VIOLATE_SHIFT 8 +/* MISC_ROOT_CLR Bit Fields */ +#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK 0x1u +#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT 0 +#define CCM_MISC_ROOT_CLR_TIMEOUT_MASK 0x10u +#define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT 4 +#define CCM_MISC_ROOT_CLR_VIOLATE_MASK 0x100u +#define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT 8 +/* MISC_ROOT_TOG Bit Fields */ +#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK 0x1u +#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT 0 +#define CCM_MISC_ROOT_TOG_TIMEOUT_MASK 0x10u +#define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT 4 +#define CCM_MISC_ROOT_TOG_VIOLATE_MASK 0x100u +#define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT 8 +/* POST Bit Fields */ +#define CCM_POST_POST_PODF_MASK 0x3Fu +#define CCM_POST_POST_PODF_SHIFT 0 +#define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_POST_PODF_SHIFT))&CCM_POST_POST_PODF_MASK) +#define CCM_POST_BUSY1_MASK 0x80u +#define CCM_POST_BUSY1_SHIFT 7 +#define CCM_POST_SELECT_MASK 0x10000000u +#define CCM_POST_SELECT_SHIFT 28 +#define CCM_POST_BUSY2_MASK 0x80000000u +#define CCM_POST_BUSY2_SHIFT 31 +/* POST_ROOT_SET Bit Fields */ +#define CCM_POST_ROOT_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT_SET_POST_PODF_SHIFT))&CCM_POST_ROOT_SET_POST_PODF_MASK) +#define CCM_POST_ROOT_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT_SET_BUSY2_SHIFT 31 +/* POST_ROOT_CLR Bit Fields */ +#define CCM_POST_ROOT_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT_CLR_BUSY2_SHIFT 31 +/* POST_ROOT_TOG Bit Fields */ +#define CCM_POST_ROOT_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT_TOG_BUSY2_SHIFT 31 +/* PRE Bit Fields */ +#define CCM_PRE_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_PRE_PODF_B_SHIFT))&CCM_PRE_PRE_PODF_B_MASK) +#define CCM_PRE_BUSY0_MASK 0x8u +#define CCM_PRE_BUSY0_SHIFT 3 +#define CCM_PRE_MUX_B_MASK 0x700u +#define CCM_PRE_MUX_B_SHIFT 8 +#define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_MUX_B_SHIFT))&CCM_PRE_MUX_B_MASK) +#define CCM_PRE_EN_B_MASK 0x1000u +#define CCM_PRE_EN_B_SHIFT 12 +#define CCM_PRE_BUSY1_MASK 0x8000u +#define CCM_PRE_BUSY1_SHIFT 15 +#define CCM_PRE_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_PRE_PODF_A_SHIFT))&CCM_PRE_PRE_PODF_A_MASK) +#define CCM_PRE_BUSY3_MASK 0x80000u +#define CCM_PRE_BUSY3_SHIFT 19 +#define CCM_PRE_MUX_A_MASK 0x7000000u +#define CCM_PRE_MUX_A_SHIFT 24 +#define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_MUX_A_SHIFT))&CCM_PRE_MUX_A_MASK) +#define CCM_PRE_EN_A_MASK 0x10000000u +#define CCM_PRE_EN_A_SHIFT 28 +#define CCM_PRE_BUSY4_MASK 0x80000000u +#define CCM_PRE_BUSY4_SHIFT 31 +/* PRE_ROOT_SET Bit Fields */ +#define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_SET_MUX_B_SHIFT))&CCM_PRE_ROOT_SET_MUX_B_MASK) +#define CCM_PRE_ROOT_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_SET_MUX_A_SHIFT))&CCM_PRE_ROOT_SET_MUX_A_MASK) +#define CCM_PRE_ROOT_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT_SET_BUSY4_SHIFT 31 +/* PRE_ROOT_CLR Bit Fields */ +#define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT_TOG Bit Fields */ +#define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL Bit Fields */ +#define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK 0xFu +#define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT 0 +#define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT))&CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK) +#define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK 0xF0u +#define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT 4 +#define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT))&CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK) +#define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK 0xF00u +#define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT 8 +#define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT))&CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK) +#define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK 0xF000u +#define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT 12 +#define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT))&CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK) +#define CCM_ACCESS_CTRL_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK 0x1000000u +#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT 24 +#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK 0x2000000u +#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT 25 +#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK 0x4000000u +#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT 26 +#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK 0x8000000u +#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT 27 +#define CCM_ACCESS_CTRL_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL_LOCK_SHIFT 31 +/* ACCESS_CTRL_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK 0xFu +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT 0 +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK 0xF0u +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT 4 +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK 0xF00u +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT 8 +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK 0xF000u +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT 12 +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK 0x1000000u +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT 24 +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK 0x2000000u +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT 25 +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK 0x4000000u +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT 26 +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK 0x8000000u +#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT 27 +#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK 0xFu +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT 0 +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK 0xF0u +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT 4 +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK 0xF00u +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT 8 +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK 0xF000u +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT 12 +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK 0x1000000u +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT 24 +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK 0x2000000u +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT 25 +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK 0x4000000u +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT 26 +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK 0x8000000u +#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT 27 +#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK 0xFu +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT 0 +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK 0xF0u +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT 4 +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK 0xF00u +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT 8 +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK 0xF000u +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT 12 +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK) +#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK 0x1000000u +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT 24 +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK 0x2000000u +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT 25 +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK 0x4000000u +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT 26 +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK 0x8000000u +#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT 27 +#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT 31 /*! * @} */ /* end of group CCM_Register_Masks */ - /* CCM - Peripheral instance base addresses */ /** Peripheral CCM base address */ #define CCM_BASE (0x30380000u) /** Peripheral CCM base pointer */ #define CCM ((CCM_Type *)CCM_BASE) #define CCM_BASE_PTR (CCM) -/** Array initializer of CCM peripheral base adresses */ +/** Array initializer of CCM peripheral base addresses */ #define CCM_BASE_ADDRS { CCM_BASE } /** Array initializer of CCM peripheral base pointers */ #define CCM_BASE_PTRS { CCM } - /* ---------------------------------------------------------------------------- -- CCM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -57537,2707 +5116,3431 @@ typedef struct { #define CCM_GPR0_SET CCM_GPR0_SET_REG(CCM_BASE_PTR) #define CCM_GPR0_CLR CCM_GPR0_CLR_REG(CCM_BASE_PTR) #define CCM_GPR0_TOG CCM_GPR0_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR0 CCM_CCGR0_REG(CCM_BASE_PTR) -#define CCM_CCGR0_SET CCM_CCGR0_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR0_CLR CCM_CCGR0_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR0_TOG CCM_CCGR0_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR1 CCM_CCGR1_REG(CCM_BASE_PTR) -#define CCM_CCGR1_SET CCM_CCGR1_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR1_CLR CCM_CCGR1_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR1_TOG CCM_CCGR1_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR2 CCM_CCGR2_REG(CCM_BASE_PTR) -#define CCM_CCGR2_SET CCM_CCGR2_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR2_CLR CCM_CCGR2_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR2_TOG CCM_CCGR2_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR3 CCM_CCGR3_REG(CCM_BASE_PTR) -#define CCM_CCGR3_SET CCM_CCGR3_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR3_CLR CCM_CCGR3_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR3_TOG CCM_CCGR3_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR4 CCM_CCGR4_REG(CCM_BASE_PTR) -#define CCM_CCGR4_SET CCM_CCGR4_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR4_CLR CCM_CCGR4_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR4_TOG CCM_CCGR4_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR5 CCM_CCGR5_REG(CCM_BASE_PTR) -#define CCM_CCGR5_SET CCM_CCGR5_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR5_CLR CCM_CCGR5_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR5_TOG CCM_CCGR5_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR6 CCM_CCGR6_REG(CCM_BASE_PTR) -#define CCM_CCGR6_SET CCM_CCGR6_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR6_CLR CCM_CCGR6_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR6_TOG CCM_CCGR6_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR7 CCM_CCGR7_REG(CCM_BASE_PTR) -#define CCM_CCGR7_SET CCM_CCGR7_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR7_CLR CCM_CCGR7_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR7_TOG CCM_CCGR7_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR8 CCM_CCGR8_REG(CCM_BASE_PTR) -#define CCM_CCGR8_SET CCM_CCGR8_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR8_CLR CCM_CCGR8_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR8_TOG CCM_CCGR8_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR9 CCM_CCGR9_REG(CCM_BASE_PTR) -#define CCM_CCGR9_SET CCM_CCGR9_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR9_CLR CCM_CCGR9_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR9_TOG CCM_CCGR9_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR10 CCM_CCGR10_REG(CCM_BASE_PTR) -#define CCM_CCGR10_SET CCM_CCGR10_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR10_CLR CCM_CCGR10_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR10_TOG CCM_CCGR10_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR11 CCM_CCGR11_REG(CCM_BASE_PTR) -#define CCM_CCGR11_SET CCM_CCGR11_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR11_CLR CCM_CCGR11_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR11_TOG CCM_CCGR11_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR12 CCM_CCGR12_REG(CCM_BASE_PTR) -#define CCM_CCGR12_SET CCM_CCGR12_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR12_CLR CCM_CCGR12_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR12_TOG CCM_CCGR12_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR13 CCM_CCGR13_REG(CCM_BASE_PTR) -#define CCM_CCGR13_SET CCM_CCGR13_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR13_CLR CCM_CCGR13_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR13_TOG CCM_CCGR13_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR14 CCM_CCGR14_REG(CCM_BASE_PTR) -#define CCM_CCGR14_SET CCM_CCGR14_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR14_CLR CCM_CCGR14_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR14_TOG CCM_CCGR14_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR15 CCM_CCGR15_REG(CCM_BASE_PTR) -#define CCM_CCGR15_SET CCM_CCGR15_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR15_CLR CCM_CCGR15_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR15_TOG CCM_CCGR15_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR16 CCM_CCGR16_REG(CCM_BASE_PTR) -#define CCM_CCGR16_SET CCM_CCGR16_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR16_CLR CCM_CCGR16_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR16_TOG CCM_CCGR16_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR17 CCM_CCGR17_REG(CCM_BASE_PTR) -#define CCM_CCGR17_SET CCM_CCGR17_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR17_CLR CCM_CCGR17_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR17_TOG CCM_CCGR17_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR18 CCM_CCGR18_REG(CCM_BASE_PTR) -#define CCM_CCGR18_SET CCM_CCGR18_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR18_CLR CCM_CCGR18_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR18_TOG CCM_CCGR18_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR19 CCM_CCGR19_REG(CCM_BASE_PTR) -#define CCM_CCGR19_SET CCM_CCGR19_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR19_CLR CCM_CCGR19_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR19_TOG CCM_CCGR19_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR20 CCM_CCGR20_REG(CCM_BASE_PTR) -#define CCM_CCGR20_SET CCM_CCGR20_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR20_CLR CCM_CCGR20_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR20_TOG CCM_CCGR20_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR21 CCM_CCGR21_REG(CCM_BASE_PTR) -#define CCM_CCGR21_SET CCM_CCGR21_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR21_CLR CCM_CCGR21_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR21_TOG CCM_CCGR21_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR22 CCM_CCGR22_REG(CCM_BASE_PTR) -#define CCM_CCGR22_SET CCM_CCGR22_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR22_CLR CCM_CCGR22_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR22_TOG CCM_CCGR22_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR23 CCM_CCGR23_REG(CCM_BASE_PTR) -#define CCM_CCGR23_SET CCM_CCGR23_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR23_CLR CCM_CCGR23_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR23_TOG CCM_CCGR23_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR24 CCM_CCGR24_REG(CCM_BASE_PTR) -#define CCM_CCGR24_SET CCM_CCGR24_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR24_CLR CCM_CCGR24_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR24_TOG CCM_CCGR24_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR25 CCM_CCGR25_REG(CCM_BASE_PTR) -#define CCM_CCGR25_SET CCM_CCGR25_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR25_CLR CCM_CCGR25_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR25_TOG CCM_CCGR25_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR26 CCM_CCGR26_REG(CCM_BASE_PTR) -#define CCM_CCGR26_SET CCM_CCGR26_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR26_CLR CCM_CCGR26_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR26_TOG CCM_CCGR26_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR27 CCM_CCGR27_REG(CCM_BASE_PTR) -#define CCM_CCGR27_SET CCM_CCGR27_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR27_CLR CCM_CCGR27_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR27_TOG CCM_CCGR27_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR28 CCM_CCGR28_REG(CCM_BASE_PTR) -#define CCM_CCGR28_SET CCM_CCGR28_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR28_CLR CCM_CCGR28_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR28_TOG CCM_CCGR28_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR29 CCM_CCGR29_REG(CCM_BASE_PTR) -#define CCM_CCGR29_SET CCM_CCGR29_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR29_CLR CCM_CCGR29_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR29_TOG CCM_CCGR29_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR30 CCM_CCGR30_REG(CCM_BASE_PTR) -#define CCM_CCGR30_SET CCM_CCGR30_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR30_CLR CCM_CCGR30_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR30_TOG CCM_CCGR30_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR31 CCM_CCGR31_REG(CCM_BASE_PTR) -#define CCM_CCGR31_SET CCM_CCGR31_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR31_CLR CCM_CCGR31_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR31_TOG CCM_CCGR31_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR32 CCM_CCGR32_REG(CCM_BASE_PTR) -#define CCM_CCGR32_SET CCM_CCGR32_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR32_CLR CCM_CCGR32_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR32_TOG CCM_CCGR32_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR33 CCM_CCGR33_REG(CCM_BASE_PTR) -#define CCM_CCGR33_SET CCM_CCGR33_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR33_CLR CCM_CCGR33_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR33_TOG CCM_CCGR33_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR34 CCM_CCGR34_REG(CCM_BASE_PTR) -#define CCM_CCGR34_SET CCM_CCGR34_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR34_CLR CCM_CCGR34_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR34_TOG CCM_CCGR34_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR35 CCM_CCGR35_REG(CCM_BASE_PTR) -#define CCM_CCGR35_SET CCM_CCGR35_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR35_CLR CCM_CCGR35_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR35_TOG CCM_CCGR35_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR36 CCM_CCGR36_REG(CCM_BASE_PTR) -#define CCM_CCGR36_SET CCM_CCGR36_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR36_CLR CCM_CCGR36_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR36_TOG CCM_CCGR36_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR37 CCM_CCGR37_REG(CCM_BASE_PTR) -#define CCM_CCGR37_SET CCM_CCGR37_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR37_CLR CCM_CCGR37_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR37_TOG CCM_CCGR37_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR38 CCM_CCGR38_REG(CCM_BASE_PTR) -#define CCM_CCGR38_SET CCM_CCGR38_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR38_CLR CCM_CCGR38_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR38_TOG CCM_CCGR38_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR39 CCM_CCGR39_REG(CCM_BASE_PTR) -#define CCM_CCGR39_SET CCM_CCGR39_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR39_CLR CCM_CCGR39_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR39_TOG CCM_CCGR39_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR40 CCM_CCGR40_REG(CCM_BASE_PTR) -#define CCM_CCGR40_SET CCM_CCGR40_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR40_CLR CCM_CCGR40_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR40_TOG CCM_CCGR40_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR41 CCM_CCGR41_REG(CCM_BASE_PTR) -#define CCM_CCGR41_SET CCM_CCGR41_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR41_CLR CCM_CCGR41_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR41_TOG CCM_CCGR41_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR42 CCM_CCGR42_REG(CCM_BASE_PTR) -#define CCM_CCGR42_SET CCM_CCGR42_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR42_CLR CCM_CCGR42_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR42_TOG CCM_CCGR42_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR43 CCM_CCGR43_REG(CCM_BASE_PTR) -#define CCM_CCGR43_SET CCM_CCGR43_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR43_CLR CCM_CCGR43_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR43_TOG CCM_CCGR43_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR44 CCM_CCGR44_REG(CCM_BASE_PTR) -#define CCM_CCGR44_SET CCM_CCGR44_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR44_CLR CCM_CCGR44_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR44_TOG CCM_CCGR44_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR45 CCM_CCGR45_REG(CCM_BASE_PTR) -#define CCM_CCGR45_SET CCM_CCGR45_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR45_CLR CCM_CCGR45_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR45_TOG CCM_CCGR45_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR46 CCM_CCGR46_REG(CCM_BASE_PTR) -#define CCM_CCGR46_SET CCM_CCGR46_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR46_CLR CCM_CCGR46_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR46_TOG CCM_CCGR46_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR47 CCM_CCGR47_REG(CCM_BASE_PTR) -#define CCM_CCGR47_SET CCM_CCGR47_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR47_CLR CCM_CCGR47_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR47_TOG CCM_CCGR47_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR48 CCM_CCGR48_REG(CCM_BASE_PTR) -#define CCM_CCGR48_SET CCM_CCGR48_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR48_CLR CCM_CCGR48_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR48_TOG CCM_CCGR48_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR49 CCM_CCGR49_REG(CCM_BASE_PTR) -#define CCM_CCGR49_SET CCM_CCGR49_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR49_CLR CCM_CCGR49_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR49_TOG CCM_CCGR49_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR50 CCM_CCGR50_REG(CCM_BASE_PTR) -#define CCM_CCGR50_SET CCM_CCGR50_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR50_CLR CCM_CCGR50_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR50_TOG CCM_CCGR50_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR51 CCM_CCGR51_REG(CCM_BASE_PTR) -#define CCM_CCGR51_SET CCM_CCGR51_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR51_CLR CCM_CCGR51_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR51_TOG CCM_CCGR51_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR52 CCM_CCGR52_REG(CCM_BASE_PTR) -#define CCM_CCGR52_SET CCM_CCGR52_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR52_CLR CCM_CCGR52_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR52_TOG CCM_CCGR52_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR53 CCM_CCGR53_REG(CCM_BASE_PTR) -#define CCM_CCGR53_SET CCM_CCGR53_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR53_CLR CCM_CCGR53_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR53_TOG CCM_CCGR53_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR54 CCM_CCGR54_REG(CCM_BASE_PTR) -#define CCM_CCGR54_SET CCM_CCGR54_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR54_CLR CCM_CCGR54_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR54_TOG CCM_CCGR54_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR55 CCM_CCGR55_REG(CCM_BASE_PTR) -#define CCM_CCGR55_SET CCM_CCGR55_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR55_CLR CCM_CCGR55_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR55_TOG CCM_CCGR55_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR56 CCM_CCGR56_REG(CCM_BASE_PTR) -#define CCM_CCGR56_SET CCM_CCGR56_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR56_CLR CCM_CCGR56_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR56_TOG CCM_CCGR56_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR57 CCM_CCGR57_REG(CCM_BASE_PTR) -#define CCM_CCGR57_SET CCM_CCGR57_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR57_CLR CCM_CCGR57_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR57_TOG CCM_CCGR57_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR58 CCM_CCGR58_REG(CCM_BASE_PTR) -#define CCM_CCGR58_SET CCM_CCGR58_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR58_CLR CCM_CCGR58_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR58_TOG CCM_CCGR58_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR59 CCM_CCGR59_REG(CCM_BASE_PTR) -#define CCM_CCGR59_SET CCM_CCGR59_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR59_CLR CCM_CCGR59_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR59_TOG CCM_CCGR59_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR60 CCM_CCGR60_REG(CCM_BASE_PTR) -#define CCM_CCGR60_SET CCM_CCGR60_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR60_CLR CCM_CCGR60_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR60_TOG CCM_CCGR60_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR61 CCM_CCGR61_REG(CCM_BASE_PTR) -#define CCM_CCGR61_SET CCM_CCGR61_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR61_CLR CCM_CCGR61_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR61_TOG CCM_CCGR61_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR62 CCM_CCGR62_REG(CCM_BASE_PTR) -#define CCM_CCGR62_SET CCM_CCGR62_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR62_CLR CCM_CCGR62_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR62_TOG CCM_CCGR62_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR63 CCM_CCGR63_REG(CCM_BASE_PTR) -#define CCM_CCGR63_SET CCM_CCGR63_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR63_CLR CCM_CCGR63_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR63_TOG CCM_CCGR63_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR64 CCM_CCGR64_REG(CCM_BASE_PTR) -#define CCM_CCGR64_SET CCM_CCGR64_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR64_CLR CCM_CCGR64_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR64_TOG CCM_CCGR64_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR65 CCM_CCGR65_REG(CCM_BASE_PTR) -#define CCM_CCGR65_SET CCM_CCGR65_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR65_CLR CCM_CCGR65_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR65_TOG CCM_CCGR65_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR66 CCM_CCGR66_REG(CCM_BASE_PTR) -#define CCM_CCGR66_SET CCM_CCGR66_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR66_CLR CCM_CCGR66_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR66_TOG CCM_CCGR66_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR67 CCM_CCGR67_REG(CCM_BASE_PTR) -#define CCM_CCGR67_SET CCM_CCGR67_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR67_CLR CCM_CCGR67_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR67_TOG CCM_CCGR67_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR68 CCM_CCGR68_REG(CCM_BASE_PTR) -#define CCM_CCGR68_SET CCM_CCGR68_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR68_CLR CCM_CCGR68_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR68_TOG CCM_CCGR68_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR69 CCM_CCGR69_REG(CCM_BASE_PTR) -#define CCM_CCGR69_SET CCM_CCGR69_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR69_CLR CCM_CCGR69_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR69_TOG CCM_CCGR69_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR70 CCM_CCGR70_REG(CCM_BASE_PTR) -#define CCM_CCGR70_SET CCM_CCGR70_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR70_CLR CCM_CCGR70_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR70_TOG CCM_CCGR70_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR71 CCM_CCGR71_REG(CCM_BASE_PTR) -#define CCM_CCGR71_SET CCM_CCGR71_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR71_CLR CCM_CCGR71_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR71_TOG CCM_CCGR71_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR72 CCM_CCGR72_REG(CCM_BASE_PTR) -#define CCM_CCGR72_SET CCM_CCGR72_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR72_CLR CCM_CCGR72_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR72_TOG CCM_CCGR72_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR73 CCM_CCGR73_REG(CCM_BASE_PTR) -#define CCM_CCGR73_SET CCM_CCGR73_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR73_CLR CCM_CCGR73_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR73_TOG CCM_CCGR73_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR74 CCM_CCGR74_REG(CCM_BASE_PTR) -#define CCM_CCGR74_SET CCM_CCGR74_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR74_CLR CCM_CCGR74_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR74_TOG CCM_CCGR74_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR75 CCM_CCGR75_REG(CCM_BASE_PTR) -#define CCM_CCGR75_SET CCM_CCGR75_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR75_CLR CCM_CCGR75_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR75_TOG CCM_CCGR75_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR76 CCM_CCGR76_REG(CCM_BASE_PTR) -#define CCM_CCGR76_SET CCM_CCGR76_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR76_CLR CCM_CCGR76_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR76_TOG CCM_CCGR76_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR77 CCM_CCGR77_REG(CCM_BASE_PTR) -#define CCM_CCGR77_SET CCM_CCGR77_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR77_CLR CCM_CCGR77_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR77_TOG CCM_CCGR77_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR78 CCM_CCGR78_REG(CCM_BASE_PTR) -#define CCM_CCGR78_SET CCM_CCGR78_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR78_CLR CCM_CCGR78_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR78_TOG CCM_CCGR78_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR79 CCM_CCGR79_REG(CCM_BASE_PTR) -#define CCM_CCGR79_SET CCM_CCGR79_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR79_CLR CCM_CCGR79_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR79_TOG CCM_CCGR79_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR80 CCM_CCGR80_REG(CCM_BASE_PTR) -#define CCM_CCGR80_SET CCM_CCGR80_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR80_CLR CCM_CCGR80_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR80_TOG CCM_CCGR80_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR81 CCM_CCGR81_REG(CCM_BASE_PTR) -#define CCM_CCGR81_SET CCM_CCGR81_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR81_CLR CCM_CCGR81_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR81_TOG CCM_CCGR81_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR82 CCM_CCGR82_REG(CCM_BASE_PTR) -#define CCM_CCGR82_SET CCM_CCGR82_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR82_CLR CCM_CCGR82_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR82_TOG CCM_CCGR82_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR83 CCM_CCGR83_REG(CCM_BASE_PTR) -#define CCM_CCGR83_SET CCM_CCGR83_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR83_CLR CCM_CCGR83_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR83_TOG CCM_CCGR83_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR84 CCM_CCGR84_REG(CCM_BASE_PTR) -#define CCM_CCGR84_SET CCM_CCGR84_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR84_CLR CCM_CCGR84_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR84_TOG CCM_CCGR84_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR85 CCM_CCGR85_REG(CCM_BASE_PTR) -#define CCM_CCGR85_SET CCM_CCGR85_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR85_CLR CCM_CCGR85_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR85_TOG CCM_CCGR85_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR86 CCM_CCGR86_REG(CCM_BASE_PTR) -#define CCM_CCGR86_SET CCM_CCGR86_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR86_CLR CCM_CCGR86_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR86_TOG CCM_CCGR86_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR87 CCM_CCGR87_REG(CCM_BASE_PTR) -#define CCM_CCGR87_SET CCM_CCGR87_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR87_CLR CCM_CCGR87_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR87_TOG CCM_CCGR87_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR88 CCM_CCGR88_REG(CCM_BASE_PTR) -#define CCM_CCGR88_SET CCM_CCGR88_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR88_CLR CCM_CCGR88_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR88_TOG CCM_CCGR88_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR89 CCM_CCGR89_REG(CCM_BASE_PTR) -#define CCM_CCGR89_SET CCM_CCGR89_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR89_CLR CCM_CCGR89_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR89_TOG CCM_CCGR89_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR90 CCM_CCGR90_REG(CCM_BASE_PTR) -#define CCM_CCGR90_SET CCM_CCGR90_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR90_CLR CCM_CCGR90_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR90_TOG CCM_CCGR90_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR91 CCM_CCGR91_REG(CCM_BASE_PTR) -#define CCM_CCGR91_SET CCM_CCGR91_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR91_CLR CCM_CCGR91_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR91_TOG CCM_CCGR91_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR92 CCM_CCGR92_REG(CCM_BASE_PTR) -#define CCM_CCGR92_SET CCM_CCGR92_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR92_CLR CCM_CCGR92_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR92_TOG CCM_CCGR92_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR93 CCM_CCGR93_REG(CCM_BASE_PTR) -#define CCM_CCGR93_SET CCM_CCGR93_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR93_CLR CCM_CCGR93_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR93_TOG CCM_CCGR93_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR94 CCM_CCGR94_REG(CCM_BASE_PTR) -#define CCM_CCGR94_SET CCM_CCGR94_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR94_CLR CCM_CCGR94_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR94_TOG CCM_CCGR94_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR95 CCM_CCGR95_REG(CCM_BASE_PTR) -#define CCM_CCGR95_SET CCM_CCGR95_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR95_CLR CCM_CCGR95_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR95_TOG CCM_CCGR95_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR96 CCM_CCGR96_REG(CCM_BASE_PTR) -#define CCM_CCGR96_SET CCM_CCGR96_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR96_CLR CCM_CCGR96_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR96_TOG CCM_CCGR96_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR97 CCM_CCGR97_REG(CCM_BASE_PTR) -#define CCM_CCGR97_SET CCM_CCGR97_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR97_CLR CCM_CCGR97_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR97_TOG CCM_CCGR97_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR98 CCM_CCGR98_REG(CCM_BASE_PTR) -#define CCM_CCGR98_SET CCM_CCGR98_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR98_CLR CCM_CCGR98_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR98_TOG CCM_CCGR98_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR99 CCM_CCGR99_REG(CCM_BASE_PTR) -#define CCM_CCGR99_SET CCM_CCGR99_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR99_CLR CCM_CCGR99_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR99_TOG CCM_CCGR99_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR100 CCM_CCGR100_REG(CCM_BASE_PTR) -#define CCM_CCGR100_SET CCM_CCGR100_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR100_CLR CCM_CCGR100_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR100_TOG CCM_CCGR100_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR101 CCM_CCGR101_REG(CCM_BASE_PTR) -#define CCM_CCGR101_SET CCM_CCGR101_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR101_CLR CCM_CCGR101_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR101_TOG CCM_CCGR101_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR102 CCM_CCGR102_REG(CCM_BASE_PTR) -#define CCM_CCGR102_SET CCM_CCGR102_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR102_CLR CCM_CCGR102_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR102_TOG CCM_CCGR102_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR103 CCM_CCGR103_REG(CCM_BASE_PTR) -#define CCM_CCGR103_SET CCM_CCGR103_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR103_CLR CCM_CCGR103_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR103_TOG CCM_CCGR103_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR104 CCM_CCGR104_REG(CCM_BASE_PTR) -#define CCM_CCGR104_SET CCM_CCGR104_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR104_CLR CCM_CCGR104_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR104_TOG CCM_CCGR104_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR105 CCM_CCGR105_REG(CCM_BASE_PTR) -#define CCM_CCGR105_SET CCM_CCGR105_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR105_CLR CCM_CCGR105_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR105_TOG CCM_CCGR105_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR106 CCM_CCGR106_REG(CCM_BASE_PTR) -#define CCM_CCGR106_SET CCM_CCGR106_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR106_CLR CCM_CCGR106_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR106_TOG CCM_CCGR106_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR107 CCM_CCGR107_REG(CCM_BASE_PTR) -#define CCM_CCGR107_SET CCM_CCGR107_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR107_CLR CCM_CCGR107_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR107_TOG CCM_CCGR107_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR108 CCM_CCGR108_REG(CCM_BASE_PTR) -#define CCM_CCGR108_SET CCM_CCGR108_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR108_CLR CCM_CCGR108_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR108_TOG CCM_CCGR108_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR109 CCM_CCGR109_REG(CCM_BASE_PTR) -#define CCM_CCGR109_SET CCM_CCGR109_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR109_CLR CCM_CCGR109_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR109_TOG CCM_CCGR109_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR110 CCM_CCGR110_REG(CCM_BASE_PTR) -#define CCM_CCGR110_SET CCM_CCGR110_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR110_CLR CCM_CCGR110_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR110_TOG CCM_CCGR110_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR111 CCM_CCGR111_REG(CCM_BASE_PTR) -#define CCM_CCGR111_SET CCM_CCGR111_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR111_CLR CCM_CCGR111_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR111_TOG CCM_CCGR111_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR112 CCM_CCGR112_REG(CCM_BASE_PTR) -#define CCM_CCGR112_SET CCM_CCGR112_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR112_CLR CCM_CCGR112_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR112_TOG CCM_CCGR112_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR113 CCM_CCGR113_REG(CCM_BASE_PTR) -#define CCM_CCGR113_SET CCM_CCGR113_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR113_CLR CCM_CCGR113_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR113_TOG CCM_CCGR113_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR114 CCM_CCGR114_REG(CCM_BASE_PTR) -#define CCM_CCGR114_SET CCM_CCGR114_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR114_CLR CCM_CCGR114_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR114_TOG CCM_CCGR114_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR115 CCM_CCGR115_REG(CCM_BASE_PTR) -#define CCM_CCGR115_SET CCM_CCGR115_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR115_CLR CCM_CCGR115_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR115_TOG CCM_CCGR115_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR116 CCM_CCGR116_REG(CCM_BASE_PTR) -#define CCM_CCGR116_SET CCM_CCGR116_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR116_CLR CCM_CCGR116_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR116_TOG CCM_CCGR116_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR117 CCM_CCGR117_REG(CCM_BASE_PTR) -#define CCM_CCGR117_SET CCM_CCGR117_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR117_CLR CCM_CCGR117_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR117_TOG CCM_CCGR117_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR118 CCM_CCGR118_REG(CCM_BASE_PTR) -#define CCM_CCGR118_SET CCM_CCGR118_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR118_CLR CCM_CCGR118_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR118_TOG CCM_CCGR118_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR119 CCM_CCGR119_REG(CCM_BASE_PTR) -#define CCM_CCGR119_SET CCM_CCGR119_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR119_CLR CCM_CCGR119_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR119_TOG CCM_CCGR119_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR120 CCM_CCGR120_REG(CCM_BASE_PTR) -#define CCM_CCGR120_SET CCM_CCGR120_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR120_CLR CCM_CCGR120_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR120_TOG CCM_CCGR120_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR121 CCM_CCGR121_REG(CCM_BASE_PTR) -#define CCM_CCGR121_SET CCM_CCGR121_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR121_CLR CCM_CCGR121_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR121_TOG CCM_CCGR121_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR122 CCM_CCGR122_REG(CCM_BASE_PTR) -#define CCM_CCGR122_SET CCM_CCGR122_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR122_CLR CCM_CCGR122_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR122_TOG CCM_CCGR122_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR123 CCM_CCGR123_REG(CCM_BASE_PTR) -#define CCM_CCGR123_SET CCM_CCGR123_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR123_CLR CCM_CCGR123_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR123_TOG CCM_CCGR123_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR124 CCM_CCGR124_REG(CCM_BASE_PTR) -#define CCM_CCGR124_SET CCM_CCGR124_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR124_CLR CCM_CCGR124_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR124_TOG CCM_CCGR124_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR125 CCM_CCGR125_REG(CCM_BASE_PTR) -#define CCM_CCGR125_SET CCM_CCGR125_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR125_CLR CCM_CCGR125_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR125_TOG CCM_CCGR125_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR126 CCM_CCGR126_REG(CCM_BASE_PTR) -#define CCM_CCGR126_SET CCM_CCGR126_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR126_CLR CCM_CCGR126_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR126_TOG CCM_CCGR126_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR127 CCM_CCGR127_REG(CCM_BASE_PTR) -#define CCM_CCGR127_SET CCM_CCGR127_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR127_CLR CCM_CCGR127_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR127_TOG CCM_CCGR127_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR128 CCM_CCGR128_REG(CCM_BASE_PTR) -#define CCM_CCGR128_SET CCM_CCGR128_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR128_CLR CCM_CCGR128_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR128_TOG CCM_CCGR128_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR129 CCM_CCGR129_REG(CCM_BASE_PTR) -#define CCM_CCGR129_SET CCM_CCGR129_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR129_CLR CCM_CCGR129_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR129_TOG CCM_CCGR129_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR130 CCM_CCGR130_REG(CCM_BASE_PTR) -#define CCM_CCGR130_SET CCM_CCGR130_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR130_CLR CCM_CCGR130_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR130_TOG CCM_CCGR130_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR131 CCM_CCGR131_REG(CCM_BASE_PTR) -#define CCM_CCGR131_SET CCM_CCGR131_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR131_CLR CCM_CCGR131_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR131_TOG CCM_CCGR131_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR132 CCM_CCGR132_REG(CCM_BASE_PTR) -#define CCM_CCGR132_SET CCM_CCGR132_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR132_CLR CCM_CCGR132_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR132_TOG CCM_CCGR132_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR133 CCM_CCGR133_REG(CCM_BASE_PTR) -#define CCM_CCGR133_SET CCM_CCGR133_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR133_CLR CCM_CCGR133_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR133_TOG CCM_CCGR133_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR134 CCM_CCGR134_REG(CCM_BASE_PTR) -#define CCM_CCGR134_SET CCM_CCGR134_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR134_CLR CCM_CCGR134_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR134_TOG CCM_CCGR134_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR135 CCM_CCGR135_REG(CCM_BASE_PTR) -#define CCM_CCGR135_SET CCM_CCGR135_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR135_CLR CCM_CCGR135_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR135_TOG CCM_CCGR135_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR136 CCM_CCGR136_REG(CCM_BASE_PTR) -#define CCM_CCGR136_SET CCM_CCGR136_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR136_CLR CCM_CCGR136_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR136_TOG CCM_CCGR136_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR137 CCM_CCGR137_REG(CCM_BASE_PTR) -#define CCM_CCGR137_SET CCM_CCGR137_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR137_CLR CCM_CCGR137_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR137_TOG CCM_CCGR137_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR138 CCM_CCGR138_REG(CCM_BASE_PTR) -#define CCM_CCGR138_SET CCM_CCGR138_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR138_CLR CCM_CCGR138_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR138_TOG CCM_CCGR138_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR139 CCM_CCGR139_REG(CCM_BASE_PTR) -#define CCM_CCGR139_SET CCM_CCGR139_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR139_CLR CCM_CCGR139_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR139_TOG CCM_CCGR139_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR140 CCM_CCGR140_REG(CCM_BASE_PTR) -#define CCM_CCGR140_SET CCM_CCGR140_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR140_CLR CCM_CCGR140_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR140_TOG CCM_CCGR140_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR141 CCM_CCGR141_REG(CCM_BASE_PTR) -#define CCM_CCGR141_SET CCM_CCGR141_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR141_CLR CCM_CCGR141_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR141_TOG CCM_CCGR141_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR142 CCM_CCGR142_REG(CCM_BASE_PTR) -#define CCM_CCGR142_SET CCM_CCGR142_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR142_CLR CCM_CCGR142_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR142_TOG CCM_CCGR142_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR143 CCM_CCGR143_REG(CCM_BASE_PTR) -#define CCM_CCGR143_SET CCM_CCGR143_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR143_CLR CCM_CCGR143_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR143_TOG CCM_CCGR143_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR144 CCM_CCGR144_REG(CCM_BASE_PTR) -#define CCM_CCGR144_SET CCM_CCGR144_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR144_CLR CCM_CCGR144_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR144_TOG CCM_CCGR144_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR145 CCM_CCGR145_REG(CCM_BASE_PTR) -#define CCM_CCGR145_SET CCM_CCGR145_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR145_CLR CCM_CCGR145_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR145_TOG CCM_CCGR145_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR146 CCM_CCGR146_REG(CCM_BASE_PTR) -#define CCM_CCGR146_SET CCM_CCGR146_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR146_CLR CCM_CCGR146_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR146_TOG CCM_CCGR146_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR147 CCM_CCGR147_REG(CCM_BASE_PTR) -#define CCM_CCGR147_SET CCM_CCGR147_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR147_CLR CCM_CCGR147_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR147_TOG CCM_CCGR147_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR148 CCM_CCGR148_REG(CCM_BASE_PTR) -#define CCM_CCGR148_SET CCM_CCGR148_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR148_CLR CCM_CCGR148_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR148_TOG CCM_CCGR148_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR149 CCM_CCGR149_REG(CCM_BASE_PTR) -#define CCM_CCGR149_SET CCM_CCGR149_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR149_CLR CCM_CCGR149_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR149_TOG CCM_CCGR149_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR150 CCM_CCGR150_REG(CCM_BASE_PTR) -#define CCM_CCGR150_SET CCM_CCGR150_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR150_CLR CCM_CCGR150_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR150_TOG CCM_CCGR150_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR151 CCM_CCGR151_REG(CCM_BASE_PTR) -#define CCM_CCGR151_SET CCM_CCGR151_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR151_CLR CCM_CCGR151_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR151_TOG CCM_CCGR151_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR152 CCM_CCGR152_REG(CCM_BASE_PTR) -#define CCM_CCGR152_SET CCM_CCGR152_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR152_CLR CCM_CCGR152_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR152_TOG CCM_CCGR152_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR153 CCM_CCGR153_REG(CCM_BASE_PTR) -#define CCM_CCGR153_SET CCM_CCGR153_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR153_CLR CCM_CCGR153_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR153_TOG CCM_CCGR153_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR154 CCM_CCGR154_REG(CCM_BASE_PTR) -#define CCM_CCGR154_SET CCM_CCGR154_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR154_CLR CCM_CCGR154_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR154_TOG CCM_CCGR154_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR155 CCM_CCGR155_REG(CCM_BASE_PTR) -#define CCM_CCGR155_SET CCM_CCGR155_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR155_CLR CCM_CCGR155_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR155_TOG CCM_CCGR155_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR156 CCM_CCGR156_REG(CCM_BASE_PTR) -#define CCM_CCGR156_SET CCM_CCGR156_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR156_CLR CCM_CCGR156_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR156_TOG CCM_CCGR156_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR157 CCM_CCGR157_REG(CCM_BASE_PTR) -#define CCM_CCGR157_SET CCM_CCGR157_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR157_CLR CCM_CCGR157_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR157_TOG CCM_CCGR157_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR158 CCM_CCGR158_REG(CCM_BASE_PTR) -#define CCM_CCGR158_SET CCM_CCGR158_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR158_CLR CCM_CCGR158_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR158_TOG CCM_CCGR158_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR159 CCM_CCGR159_REG(CCM_BASE_PTR) -#define CCM_CCGR159_SET CCM_CCGR159_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR159_CLR CCM_CCGR159_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR159_TOG CCM_CCGR159_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR160 CCM_CCGR160_REG(CCM_BASE_PTR) -#define CCM_CCGR160_SET CCM_CCGR160_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR160_CLR CCM_CCGR160_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR160_TOG CCM_CCGR160_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR161 CCM_CCGR161_REG(CCM_BASE_PTR) -#define CCM_CCGR161_SET CCM_CCGR161_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR161_CLR CCM_CCGR161_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR161_TOG CCM_CCGR161_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR162 CCM_CCGR162_REG(CCM_BASE_PTR) -#define CCM_CCGR162_SET CCM_CCGR162_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR162_CLR CCM_CCGR162_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR162_TOG CCM_CCGR162_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR163 CCM_CCGR163_REG(CCM_BASE_PTR) -#define CCM_CCGR163_SET CCM_CCGR163_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR163_CLR CCM_CCGR163_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR163_TOG CCM_CCGR163_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR164 CCM_CCGR164_REG(CCM_BASE_PTR) -#define CCM_CCGR164_SET CCM_CCGR164_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR164_CLR CCM_CCGR164_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR164_TOG CCM_CCGR164_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR165 CCM_CCGR165_REG(CCM_BASE_PTR) -#define CCM_CCGR165_SET CCM_CCGR165_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR165_CLR CCM_CCGR165_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR165_TOG CCM_CCGR165_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR166 CCM_CCGR166_REG(CCM_BASE_PTR) -#define CCM_CCGR166_SET CCM_CCGR166_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR166_CLR CCM_CCGR166_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR166_TOG CCM_CCGR166_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR167 CCM_CCGR167_REG(CCM_BASE_PTR) -#define CCM_CCGR167_SET CCM_CCGR167_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR167_CLR CCM_CCGR167_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR167_TOG CCM_CCGR167_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR168 CCM_CCGR168_REG(CCM_BASE_PTR) -#define CCM_CCGR168_SET CCM_CCGR168_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR168_CLR CCM_CCGR168_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR168_TOG CCM_CCGR168_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR169 CCM_CCGR169_REG(CCM_BASE_PTR) -#define CCM_CCGR169_SET CCM_CCGR169_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR169_CLR CCM_CCGR169_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR169_TOG CCM_CCGR169_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR170 CCM_CCGR170_REG(CCM_BASE_PTR) -#define CCM_CCGR170_SET CCM_CCGR170_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR170_CLR CCM_CCGR170_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR170_TOG CCM_CCGR170_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR171 CCM_CCGR171_REG(CCM_BASE_PTR) -#define CCM_CCGR171_SET CCM_CCGR171_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR171_CLR CCM_CCGR171_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR171_TOG CCM_CCGR171_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR172 CCM_CCGR172_REG(CCM_BASE_PTR) -#define CCM_CCGR172_SET CCM_CCGR172_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR172_CLR CCM_CCGR172_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR172_TOG CCM_CCGR172_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR173 CCM_CCGR173_REG(CCM_BASE_PTR) -#define CCM_CCGR173_SET CCM_CCGR173_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR173_CLR CCM_CCGR173_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR173_TOG CCM_CCGR173_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR174 CCM_CCGR174_REG(CCM_BASE_PTR) -#define CCM_CCGR174_SET CCM_CCGR174_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR174_CLR CCM_CCGR174_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR174_TOG CCM_CCGR174_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR175 CCM_CCGR175_REG(CCM_BASE_PTR) -#define CCM_CCGR175_SET CCM_CCGR175_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR175_CLR CCM_CCGR175_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR175_TOG CCM_CCGR175_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR176 CCM_CCGR176_REG(CCM_BASE_PTR) -#define CCM_CCGR176_SET CCM_CCGR176_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR176_CLR CCM_CCGR176_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR176_TOG CCM_CCGR176_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR177 CCM_CCGR177_REG(CCM_BASE_PTR) -#define CCM_CCGR177_SET CCM_CCGR177_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR177_CLR CCM_CCGR177_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR177_TOG CCM_CCGR177_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR178 CCM_CCGR178_REG(CCM_BASE_PTR) -#define CCM_CCGR178_SET CCM_CCGR178_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR178_CLR CCM_CCGR178_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR178_TOG CCM_CCGR178_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR179 CCM_CCGR179_REG(CCM_BASE_PTR) -#define CCM_CCGR179_SET CCM_CCGR179_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR179_CLR CCM_CCGR179_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR179_TOG CCM_CCGR179_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR180 CCM_CCGR180_REG(CCM_BASE_PTR) -#define CCM_CCGR180_SET CCM_CCGR180_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR180_CLR CCM_CCGR180_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR180_TOG CCM_CCGR180_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR181 CCM_CCGR181_REG(CCM_BASE_PTR) -#define CCM_CCGR181_SET CCM_CCGR181_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR181_CLR CCM_CCGR181_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR181_TOG CCM_CCGR181_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR182 CCM_CCGR182_REG(CCM_BASE_PTR) -#define CCM_CCGR182_SET CCM_CCGR182_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR182_CLR CCM_CCGR182_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR182_TOG CCM_CCGR182_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR183 CCM_CCGR183_REG(CCM_BASE_PTR) -#define CCM_CCGR183_SET CCM_CCGR183_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR183_CLR CCM_CCGR183_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR183_TOG CCM_CCGR183_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR184 CCM_CCGR184_REG(CCM_BASE_PTR) -#define CCM_CCGR184_SET CCM_CCGR184_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR184_CLR CCM_CCGR184_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR184_TOG CCM_CCGR184_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR185 CCM_CCGR185_REG(CCM_BASE_PTR) -#define CCM_CCGR185_SET CCM_CCGR185_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR185_CLR CCM_CCGR185_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR185_TOG CCM_CCGR185_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR186 CCM_CCGR186_REG(CCM_BASE_PTR) -#define CCM_CCGR186_SET CCM_CCGR186_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR186_CLR CCM_CCGR186_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR186_TOG CCM_CCGR186_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR187 CCM_CCGR187_REG(CCM_BASE_PTR) -#define CCM_CCGR187_SET CCM_CCGR187_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR187_CLR CCM_CCGR187_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR187_TOG CCM_CCGR187_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR188 CCM_CCGR188_REG(CCM_BASE_PTR) -#define CCM_CCGR188_SET CCM_CCGR188_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR188_CLR CCM_CCGR188_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR188_TOG CCM_CCGR188_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR189 CCM_CCGR189_REG(CCM_BASE_PTR) -#define CCM_CCGR189_SET CCM_CCGR189_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR189_CLR CCM_CCGR189_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR189_TOG CCM_CCGR189_TOG_REG(CCM_BASE_PTR) -#define CCM_CCGR190 CCM_CCGR190_REG(CCM_BASE_PTR) -#define CCM_CCGR190_SET CCM_CCGR190_SET_REG(CCM_BASE_PTR) -#define CCM_CCGR190_CLR CCM_CCGR190_CLR_REG(CCM_BASE_PTR) -#define CCM_CCGR190_TOG CCM_CCGR190_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT0 CCM_TARGET_ROOT0_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT0_SET CCM_TARGET_ROOT0_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT0_CLR CCM_TARGET_ROOT0_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT0_TOG CCM_TARGET_ROOT0_TOG_REG(CCM_BASE_PTR) -#define CCM_POST0 CCM_POST0_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT0_SET CCM_POST_ROOT0_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT0_CLR CCM_POST_ROOT0_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT0_TOG CCM_POST_ROOT0_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE0 CCM_PRE0_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT0_SET CCM_PRE_ROOT0_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT0_CLR CCM_PRE_ROOT0_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT0_TOG CCM_PRE_ROOT0_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL0 CCM_ACCESS_CTRL0_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT0_SET CCM_ACCESS_CTRL0_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT0_CLR CCM_ACCESS_CTRL0_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT0_TOG CCM_ACCESS_CTRL0_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT1 CCM_TARGET_ROOT1_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT1_SET CCM_TARGET_ROOT1_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT1_CLR CCM_TARGET_ROOT1_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT1_TOG CCM_TARGET_ROOT1_TOG_REG(CCM_BASE_PTR) -#define CCM_POST1 CCM_POST1_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT1_SET CCM_POST_ROOT1_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT1_CLR CCM_POST_ROOT1_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT1_TOG CCM_POST_ROOT1_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE1 CCM_PRE1_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT1_SET CCM_PRE_ROOT1_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT1_CLR CCM_PRE_ROOT1_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT1_TOG CCM_PRE_ROOT1_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL1 CCM_ACCESS_CTRL1_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT1_SET CCM_ACCESS_CTRL1_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT1_CLR CCM_ACCESS_CTRL1_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT1_TOG CCM_ACCESS_CTRL1_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT2 CCM_TARGET_ROOT2_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT2_SET CCM_TARGET_ROOT2_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT2_CLR CCM_TARGET_ROOT2_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT2_TOG CCM_TARGET_ROOT2_TOG_REG(CCM_BASE_PTR) -#define CCM_POST2 CCM_POST2_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT2_SET CCM_POST_ROOT2_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT2_CLR CCM_POST_ROOT2_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT2_TOG CCM_POST_ROOT2_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE2 CCM_PRE2_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT2_SET CCM_PRE_ROOT2_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT2_CLR CCM_PRE_ROOT2_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT2_TOG CCM_PRE_ROOT2_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL2 CCM_ACCESS_CTRL2_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT2_SET CCM_ACCESS_CTRL2_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT2_CLR CCM_ACCESS_CTRL2_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT2_TOG CCM_ACCESS_CTRL2_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT3 CCM_TARGET_ROOT3_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT3_SET CCM_TARGET_ROOT3_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT3_CLR CCM_TARGET_ROOT3_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT3_TOG CCM_TARGET_ROOT3_TOG_REG(CCM_BASE_PTR) -#define CCM_POST3 CCM_POST3_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT3_SET CCM_POST_ROOT3_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT3_CLR CCM_POST_ROOT3_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT3_TOG CCM_POST_ROOT3_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE3 CCM_PRE3_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT3_SET CCM_PRE_ROOT3_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT3_CLR CCM_PRE_ROOT3_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT3_TOG CCM_PRE_ROOT3_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL3 CCM_ACCESS_CTRL3_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT3_SET CCM_ACCESS_CTRL3_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT3_CLR CCM_ACCESS_CTRL3_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT3_TOG CCM_ACCESS_CTRL3_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT4 CCM_TARGET_ROOT4_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT4_SET CCM_TARGET_ROOT4_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT4_CLR CCM_TARGET_ROOT4_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT4_TOG CCM_TARGET_ROOT4_TOG_REG(CCM_BASE_PTR) -#define CCM_POST4 CCM_POST4_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT4_SET CCM_POST_ROOT4_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT4_CLR CCM_POST_ROOT4_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT4_TOG CCM_POST_ROOT4_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE4 CCM_PRE4_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT4_SET CCM_PRE_ROOT4_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT4_CLR CCM_PRE_ROOT4_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT4_TOG CCM_PRE_ROOT4_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL4 CCM_ACCESS_CTRL4_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT4_SET CCM_ACCESS_CTRL4_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT4_CLR CCM_ACCESS_CTRL4_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT4_TOG CCM_ACCESS_CTRL4_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT5 CCM_TARGET_ROOT5_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT5_SET CCM_TARGET_ROOT5_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT5_CLR CCM_TARGET_ROOT5_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT5_TOG CCM_TARGET_ROOT5_TOG_REG(CCM_BASE_PTR) -#define CCM_POST5 CCM_POST5_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT5_SET CCM_POST_ROOT5_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT5_CLR CCM_POST_ROOT5_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT5_TOG CCM_POST_ROOT5_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE5 CCM_PRE5_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT5_SET CCM_PRE_ROOT5_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT5_CLR CCM_PRE_ROOT5_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT5_TOG CCM_PRE_ROOT5_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL5 CCM_ACCESS_CTRL5_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT5_SET CCM_ACCESS_CTRL5_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT5_CLR CCM_ACCESS_CTRL5_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT5_TOG CCM_ACCESS_CTRL5_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT6 CCM_TARGET_ROOT6_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT6_SET CCM_TARGET_ROOT6_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT6_CLR CCM_TARGET_ROOT6_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT6_TOG CCM_TARGET_ROOT6_TOG_REG(CCM_BASE_PTR) -#define CCM_POST6 CCM_POST6_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT6_SET CCM_POST_ROOT6_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT6_CLR CCM_POST_ROOT6_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT6_TOG CCM_POST_ROOT6_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE6 CCM_PRE6_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT6_SET CCM_PRE_ROOT6_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT6_CLR CCM_PRE_ROOT6_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT6_TOG CCM_PRE_ROOT6_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL6 CCM_ACCESS_CTRL6_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT6_SET CCM_ACCESS_CTRL6_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT6_CLR CCM_ACCESS_CTRL6_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT6_TOG CCM_ACCESS_CTRL6_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT7 CCM_TARGET_ROOT7_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT7_SET CCM_TARGET_ROOT7_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT7_CLR CCM_TARGET_ROOT7_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT7_TOG CCM_TARGET_ROOT7_TOG_REG(CCM_BASE_PTR) -#define CCM_POST7 CCM_POST7_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT7_SET CCM_POST_ROOT7_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT7_CLR CCM_POST_ROOT7_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT7_TOG CCM_POST_ROOT7_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE7 CCM_PRE7_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT7_SET CCM_PRE_ROOT7_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT7_CLR CCM_PRE_ROOT7_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT7_TOG CCM_PRE_ROOT7_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL7 CCM_ACCESS_CTRL7_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT7_SET CCM_ACCESS_CTRL7_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT7_CLR CCM_ACCESS_CTRL7_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT7_TOG CCM_ACCESS_CTRL7_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT8 CCM_TARGET_ROOT8_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT8_SET CCM_TARGET_ROOT8_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT8_CLR CCM_TARGET_ROOT8_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT8_TOG CCM_TARGET_ROOT8_TOG_REG(CCM_BASE_PTR) -#define CCM_POST8 CCM_POST8_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT8_SET CCM_POST_ROOT8_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT8_CLR CCM_POST_ROOT8_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT8_TOG CCM_POST_ROOT8_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE8 CCM_PRE8_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT8_SET CCM_PRE_ROOT8_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT8_CLR CCM_PRE_ROOT8_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT8_TOG CCM_PRE_ROOT8_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL8 CCM_ACCESS_CTRL8_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT8_SET CCM_ACCESS_CTRL8_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT8_CLR CCM_ACCESS_CTRL8_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT8_TOG CCM_ACCESS_CTRL8_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT9 CCM_TARGET_ROOT9_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT9_SET CCM_TARGET_ROOT9_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT9_CLR CCM_TARGET_ROOT9_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT9_TOG CCM_TARGET_ROOT9_TOG_REG(CCM_BASE_PTR) -#define CCM_POST9 CCM_POST9_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT9_SET CCM_POST_ROOT9_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT9_CLR CCM_POST_ROOT9_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT9_TOG CCM_POST_ROOT9_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE9 CCM_PRE9_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT9_SET CCM_PRE_ROOT9_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT9_CLR CCM_PRE_ROOT9_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT9_TOG CCM_PRE_ROOT9_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL9 CCM_ACCESS_CTRL9_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT9_SET CCM_ACCESS_CTRL9_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT9_CLR CCM_ACCESS_CTRL9_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT9_TOG CCM_ACCESS_CTRL9_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT10 CCM_TARGET_ROOT10_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT10_SET CCM_TARGET_ROOT10_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT10_CLR CCM_TARGET_ROOT10_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT10_TOG CCM_TARGET_ROOT10_TOG_REG(CCM_BASE_PTR) -#define CCM_POST10 CCM_POST10_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT10_SET CCM_POST_ROOT10_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT10_CLR CCM_POST_ROOT10_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT10_TOG CCM_POST_ROOT10_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE10 CCM_PRE10_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT10_SET CCM_PRE_ROOT10_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT10_CLR CCM_PRE_ROOT10_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT10_TOG CCM_PRE_ROOT10_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL10 CCM_ACCESS_CTRL10_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT10_SET CCM_ACCESS_CTRL10_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT10_CLR CCM_ACCESS_CTRL10_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT10_TOG CCM_ACCESS_CTRL10_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT11 CCM_TARGET_ROOT11_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT11_SET CCM_TARGET_ROOT11_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT11_CLR CCM_TARGET_ROOT11_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT11_TOG CCM_TARGET_ROOT11_TOG_REG(CCM_BASE_PTR) -#define CCM_POST11 CCM_POST11_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT11_SET CCM_POST_ROOT11_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT11_CLR CCM_POST_ROOT11_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT11_TOG CCM_POST_ROOT11_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE11 CCM_PRE11_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT11_SET CCM_PRE_ROOT11_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT11_CLR CCM_PRE_ROOT11_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT11_TOG CCM_PRE_ROOT11_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL11 CCM_ACCESS_CTRL11_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT11_SET CCM_ACCESS_CTRL11_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT11_CLR CCM_ACCESS_CTRL11_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT11_TOG CCM_ACCESS_CTRL11_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT12 CCM_TARGET_ROOT12_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT12_SET CCM_TARGET_ROOT12_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT12_CLR CCM_TARGET_ROOT12_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT12_TOG CCM_TARGET_ROOT12_TOG_REG(CCM_BASE_PTR) -#define CCM_POST12 CCM_POST12_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT12_SET CCM_POST_ROOT12_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT12_CLR CCM_POST_ROOT12_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT12_TOG CCM_POST_ROOT12_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE12 CCM_PRE12_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT12_SET CCM_PRE_ROOT12_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT12_CLR CCM_PRE_ROOT12_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT12_TOG CCM_PRE_ROOT12_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL12 CCM_ACCESS_CTRL12_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT12_SET CCM_ACCESS_CTRL12_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT12_CLR CCM_ACCESS_CTRL12_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT12_TOG CCM_ACCESS_CTRL12_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT13 CCM_TARGET_ROOT13_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT13_SET CCM_TARGET_ROOT13_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT13_CLR CCM_TARGET_ROOT13_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT13_TOG CCM_TARGET_ROOT13_TOG_REG(CCM_BASE_PTR) -#define CCM_POST13 CCM_POST13_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT13_SET CCM_POST_ROOT13_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT13_CLR CCM_POST_ROOT13_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT13_TOG CCM_POST_ROOT13_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE13 CCM_PRE13_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT13_SET CCM_PRE_ROOT13_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT13_CLR CCM_PRE_ROOT13_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT13_TOG CCM_PRE_ROOT13_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL13 CCM_ACCESS_CTRL13_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT13_SET CCM_ACCESS_CTRL13_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT13_CLR CCM_ACCESS_CTRL13_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT13_TOG CCM_ACCESS_CTRL13_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT14 CCM_TARGET_ROOT14_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT14_SET CCM_TARGET_ROOT14_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT14_CLR CCM_TARGET_ROOT14_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT14_TOG CCM_TARGET_ROOT14_TOG_REG(CCM_BASE_PTR) -#define CCM_POST14 CCM_POST14_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT14_SET CCM_POST_ROOT14_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT14_CLR CCM_POST_ROOT14_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT14_TOG CCM_POST_ROOT14_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE14 CCM_PRE14_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT14_SET CCM_PRE_ROOT14_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT14_CLR CCM_PRE_ROOT14_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT14_TOG CCM_PRE_ROOT14_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL14 CCM_ACCESS_CTRL14_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT14_SET CCM_ACCESS_CTRL14_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT14_CLR CCM_ACCESS_CTRL14_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT14_TOG CCM_ACCESS_CTRL14_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT15 CCM_TARGET_ROOT15_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT15_SET CCM_TARGET_ROOT15_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT15_CLR CCM_TARGET_ROOT15_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT15_TOG CCM_TARGET_ROOT15_TOG_REG(CCM_BASE_PTR) -#define CCM_POST15 CCM_POST15_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT15_SET CCM_POST_ROOT15_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT15_CLR CCM_POST_ROOT15_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT15_TOG CCM_POST_ROOT15_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE15 CCM_PRE15_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT15_SET CCM_PRE_ROOT15_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT15_CLR CCM_PRE_ROOT15_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT15_TOG CCM_PRE_ROOT15_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL15 CCM_ACCESS_CTRL15_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT15_SET CCM_ACCESS_CTRL15_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT15_CLR CCM_ACCESS_CTRL15_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT15_TOG CCM_ACCESS_CTRL15_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT16 CCM_TARGET_ROOT16_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT16_SET CCM_TARGET_ROOT16_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT16_CLR CCM_TARGET_ROOT16_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT16_TOG CCM_TARGET_ROOT16_TOG_REG(CCM_BASE_PTR) -#define CCM_POST16 CCM_POST16_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT16_SET CCM_POST_ROOT16_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT16_CLR CCM_POST_ROOT16_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT16_TOG CCM_POST_ROOT16_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE16 CCM_PRE16_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT16_SET CCM_PRE_ROOT16_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT16_CLR CCM_PRE_ROOT16_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT16_TOG CCM_PRE_ROOT16_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL16 CCM_ACCESS_CTRL16_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT16_SET CCM_ACCESS_CTRL16_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT16_CLR CCM_ACCESS_CTRL16_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT16_TOG CCM_ACCESS_CTRL16_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT17 CCM_TARGET_ROOT17_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT17_SET CCM_TARGET_ROOT17_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT17_CLR CCM_TARGET_ROOT17_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT17_TOG CCM_TARGET_ROOT17_TOG_REG(CCM_BASE_PTR) -#define CCM_POST17 CCM_POST17_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT17_SET CCM_POST_ROOT17_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT17_CLR CCM_POST_ROOT17_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT17_TOG CCM_POST_ROOT17_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE17 CCM_PRE17_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT17_SET CCM_PRE_ROOT17_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT17_CLR CCM_PRE_ROOT17_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT17_TOG CCM_PRE_ROOT17_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL17 CCM_ACCESS_CTRL17_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT17_SET CCM_ACCESS_CTRL17_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT17_CLR CCM_ACCESS_CTRL17_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT17_TOG CCM_ACCESS_CTRL17_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT18 CCM_TARGET_ROOT18_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT18_SET CCM_TARGET_ROOT18_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT18_CLR CCM_TARGET_ROOT18_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT18_TOG CCM_TARGET_ROOT18_TOG_REG(CCM_BASE_PTR) -#define CCM_POST18 CCM_POST18_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT18_SET CCM_POST_ROOT18_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT18_CLR CCM_POST_ROOT18_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT18_TOG CCM_POST_ROOT18_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE18 CCM_PRE18_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT18_SET CCM_PRE_ROOT18_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT18_CLR CCM_PRE_ROOT18_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT18_TOG CCM_PRE_ROOT18_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL18 CCM_ACCESS_CTRL18_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT18_SET CCM_ACCESS_CTRL18_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT18_CLR CCM_ACCESS_CTRL18_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT18_TOG CCM_ACCESS_CTRL18_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT19 CCM_TARGET_ROOT19_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT19_SET CCM_TARGET_ROOT19_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT19_CLR CCM_TARGET_ROOT19_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT19_TOG CCM_TARGET_ROOT19_TOG_REG(CCM_BASE_PTR) -#define CCM_POST19 CCM_POST19_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT19_SET CCM_POST_ROOT19_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT19_CLR CCM_POST_ROOT19_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT19_TOG CCM_POST_ROOT19_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE19 CCM_PRE19_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT19_SET CCM_PRE_ROOT19_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT19_CLR CCM_PRE_ROOT19_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT19_TOG CCM_PRE_ROOT19_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL19 CCM_ACCESS_CTRL19_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT19_SET CCM_ACCESS_CTRL19_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT19_CLR CCM_ACCESS_CTRL19_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT19_TOG CCM_ACCESS_CTRL19_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT20 CCM_TARGET_ROOT20_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT20_SET CCM_TARGET_ROOT20_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT20_CLR CCM_TARGET_ROOT20_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT20_TOG CCM_TARGET_ROOT20_TOG_REG(CCM_BASE_PTR) -#define CCM_POST20 CCM_POST20_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT20_SET CCM_POST_ROOT20_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT20_CLR CCM_POST_ROOT20_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT20_TOG CCM_POST_ROOT20_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE20 CCM_PRE20_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT20_SET CCM_PRE_ROOT20_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT20_CLR CCM_PRE_ROOT20_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT20_TOG CCM_PRE_ROOT20_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL20 CCM_ACCESS_CTRL20_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT20_SET CCM_ACCESS_CTRL20_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT20_CLR CCM_ACCESS_CTRL20_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT20_TOG CCM_ACCESS_CTRL20_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT21 CCM_TARGET_ROOT21_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT21_SET CCM_TARGET_ROOT21_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT21_CLR CCM_TARGET_ROOT21_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT21_TOG CCM_TARGET_ROOT21_TOG_REG(CCM_BASE_PTR) -#define CCM_POST21 CCM_POST21_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT21_SET CCM_POST_ROOT21_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT21_CLR CCM_POST_ROOT21_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT21_TOG CCM_POST_ROOT21_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE21 CCM_PRE21_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT21_SET CCM_PRE_ROOT21_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT21_CLR CCM_PRE_ROOT21_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT21_TOG CCM_PRE_ROOT21_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL21 CCM_ACCESS_CTRL21_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT21_SET CCM_ACCESS_CTRL21_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT21_CLR CCM_ACCESS_CTRL21_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT21_TOG CCM_ACCESS_CTRL21_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT22 CCM_TARGET_ROOT22_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT22_SET CCM_TARGET_ROOT22_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT22_CLR CCM_TARGET_ROOT22_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT22_TOG CCM_TARGET_ROOT22_TOG_REG(CCM_BASE_PTR) -#define CCM_POST22 CCM_POST22_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT22_SET CCM_POST_ROOT22_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT22_CLR CCM_POST_ROOT22_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT22_TOG CCM_POST_ROOT22_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE22 CCM_PRE22_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT22_SET CCM_PRE_ROOT22_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT22_CLR CCM_PRE_ROOT22_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT22_TOG CCM_PRE_ROOT22_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL22 CCM_ACCESS_CTRL22_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT22_SET CCM_ACCESS_CTRL22_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT22_CLR CCM_ACCESS_CTRL22_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT22_TOG CCM_ACCESS_CTRL22_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT23 CCM_TARGET_ROOT23_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT23_SET CCM_TARGET_ROOT23_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT23_CLR CCM_TARGET_ROOT23_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT23_TOG CCM_TARGET_ROOT23_TOG_REG(CCM_BASE_PTR) -#define CCM_POST23 CCM_POST23_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT23_SET CCM_POST_ROOT23_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT23_CLR CCM_POST_ROOT23_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT23_TOG CCM_POST_ROOT23_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE23 CCM_PRE23_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT23_SET CCM_PRE_ROOT23_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT23_CLR CCM_PRE_ROOT23_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT23_TOG CCM_PRE_ROOT23_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL23 CCM_ACCESS_CTRL23_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT23_SET CCM_ACCESS_CTRL23_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT23_CLR CCM_ACCESS_CTRL23_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT23_TOG CCM_ACCESS_CTRL23_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT24 CCM_TARGET_ROOT24_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT24_SET CCM_TARGET_ROOT24_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT24_CLR CCM_TARGET_ROOT24_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT24_TOG CCM_TARGET_ROOT24_TOG_REG(CCM_BASE_PTR) -#define CCM_POST24 CCM_POST24_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT24_SET CCM_POST_ROOT24_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT24_CLR CCM_POST_ROOT24_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT24_TOG CCM_POST_ROOT24_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE24 CCM_PRE24_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT24_SET CCM_PRE_ROOT24_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT24_CLR CCM_PRE_ROOT24_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT24_TOG CCM_PRE_ROOT24_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL24 CCM_ACCESS_CTRL24_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT24_SET CCM_ACCESS_CTRL24_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT24_CLR CCM_ACCESS_CTRL24_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT24_TOG CCM_ACCESS_CTRL24_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT25 CCM_TARGET_ROOT25_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT25_SET CCM_TARGET_ROOT25_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT25_CLR CCM_TARGET_ROOT25_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT25_TOG CCM_TARGET_ROOT25_TOG_REG(CCM_BASE_PTR) -#define CCM_POST25 CCM_POST25_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT25_SET CCM_POST_ROOT25_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT25_CLR CCM_POST_ROOT25_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT25_TOG CCM_POST_ROOT25_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE25 CCM_PRE25_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT25_SET CCM_PRE_ROOT25_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT25_CLR CCM_PRE_ROOT25_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT25_TOG CCM_PRE_ROOT25_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL25 CCM_ACCESS_CTRL25_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT25_SET CCM_ACCESS_CTRL25_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT25_CLR CCM_ACCESS_CTRL25_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT25_TOG CCM_ACCESS_CTRL25_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT26 CCM_TARGET_ROOT26_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT26_SET CCM_TARGET_ROOT26_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT26_CLR CCM_TARGET_ROOT26_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT26_TOG CCM_TARGET_ROOT26_TOG_REG(CCM_BASE_PTR) -#define CCM_POST26 CCM_POST26_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT26_SET CCM_POST_ROOT26_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT26_CLR CCM_POST_ROOT26_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT26_TOG CCM_POST_ROOT26_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE26 CCM_PRE26_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT26_SET CCM_PRE_ROOT26_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT26_CLR CCM_PRE_ROOT26_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT26_TOG CCM_PRE_ROOT26_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL26 CCM_ACCESS_CTRL26_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT26_SET CCM_ACCESS_CTRL26_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT26_CLR CCM_ACCESS_CTRL26_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT26_TOG CCM_ACCESS_CTRL26_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT27 CCM_TARGET_ROOT27_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT27_SET CCM_TARGET_ROOT27_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT27_CLR CCM_TARGET_ROOT27_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT27_TOG CCM_TARGET_ROOT27_TOG_REG(CCM_BASE_PTR) -#define CCM_POST27 CCM_POST27_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT27_SET CCM_POST_ROOT27_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT27_CLR CCM_POST_ROOT27_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT27_TOG CCM_POST_ROOT27_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE27 CCM_PRE27_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT27_SET CCM_PRE_ROOT27_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT27_CLR CCM_PRE_ROOT27_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT27_TOG CCM_PRE_ROOT27_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL27 CCM_ACCESS_CTRL27_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT27_SET CCM_ACCESS_CTRL27_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT27_CLR CCM_ACCESS_CTRL27_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT27_TOG CCM_ACCESS_CTRL27_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT28 CCM_TARGET_ROOT28_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT28_SET CCM_TARGET_ROOT28_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT28_CLR CCM_TARGET_ROOT28_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT28_TOG CCM_TARGET_ROOT28_TOG_REG(CCM_BASE_PTR) -#define CCM_POST28 CCM_POST28_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT28_SET CCM_POST_ROOT28_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT28_CLR CCM_POST_ROOT28_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT28_TOG CCM_POST_ROOT28_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE28 CCM_PRE28_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT28_SET CCM_PRE_ROOT28_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT28_CLR CCM_PRE_ROOT28_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT28_TOG CCM_PRE_ROOT28_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL28 CCM_ACCESS_CTRL28_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT28_SET CCM_ACCESS_CTRL28_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT28_CLR CCM_ACCESS_CTRL28_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT28_TOG CCM_ACCESS_CTRL28_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT29 CCM_TARGET_ROOT29_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT29_SET CCM_TARGET_ROOT29_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT29_CLR CCM_TARGET_ROOT29_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT29_TOG CCM_TARGET_ROOT29_TOG_REG(CCM_BASE_PTR) -#define CCM_POST29 CCM_POST29_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT29_SET CCM_POST_ROOT29_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT29_CLR CCM_POST_ROOT29_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT29_TOG CCM_POST_ROOT29_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE29 CCM_PRE29_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT29_SET CCM_PRE_ROOT29_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT29_CLR CCM_PRE_ROOT29_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT29_TOG CCM_PRE_ROOT29_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL29 CCM_ACCESS_CTRL29_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT29_SET CCM_ACCESS_CTRL29_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT29_CLR CCM_ACCESS_CTRL29_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT29_TOG CCM_ACCESS_CTRL29_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT30 CCM_TARGET_ROOT30_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT30_SET CCM_TARGET_ROOT30_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT30_CLR CCM_TARGET_ROOT30_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT30_TOG CCM_TARGET_ROOT30_TOG_REG(CCM_BASE_PTR) -#define CCM_POST30 CCM_POST30_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT30_SET CCM_POST_ROOT30_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT30_CLR CCM_POST_ROOT30_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT30_TOG CCM_POST_ROOT30_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE30 CCM_PRE30_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT30_SET CCM_PRE_ROOT30_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT30_CLR CCM_PRE_ROOT30_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT30_TOG CCM_PRE_ROOT30_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL30 CCM_ACCESS_CTRL30_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT30_SET CCM_ACCESS_CTRL30_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT30_CLR CCM_ACCESS_CTRL30_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT30_TOG CCM_ACCESS_CTRL30_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT31 CCM_TARGET_ROOT31_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT31_SET CCM_TARGET_ROOT31_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT31_CLR CCM_TARGET_ROOT31_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT31_TOG CCM_TARGET_ROOT31_TOG_REG(CCM_BASE_PTR) -#define CCM_POST31 CCM_POST31_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT31_SET CCM_POST_ROOT31_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT31_CLR CCM_POST_ROOT31_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT31_TOG CCM_POST_ROOT31_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE31 CCM_PRE31_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT31_SET CCM_PRE_ROOT31_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT31_CLR CCM_PRE_ROOT31_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT31_TOG CCM_PRE_ROOT31_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL31 CCM_ACCESS_CTRL31_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT31_SET CCM_ACCESS_CTRL31_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT31_CLR CCM_ACCESS_CTRL31_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT31_TOG CCM_ACCESS_CTRL31_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT32 CCM_TARGET_ROOT32_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT32_SET CCM_TARGET_ROOT32_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT32_CLR CCM_TARGET_ROOT32_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT32_TOG CCM_TARGET_ROOT32_TOG_REG(CCM_BASE_PTR) -#define CCM_POST32 CCM_POST32_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT32_SET CCM_POST_ROOT32_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT32_CLR CCM_POST_ROOT32_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT32_TOG CCM_POST_ROOT32_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE32 CCM_PRE32_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT32_SET CCM_PRE_ROOT32_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT32_CLR CCM_PRE_ROOT32_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT32_TOG CCM_PRE_ROOT32_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL32 CCM_ACCESS_CTRL32_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT32_SET CCM_ACCESS_CTRL32_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT32_CLR CCM_ACCESS_CTRL32_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT32_TOG CCM_ACCESS_CTRL32_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT33 CCM_TARGET_ROOT33_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT33_SET CCM_TARGET_ROOT33_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT33_CLR CCM_TARGET_ROOT33_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT33_TOG CCM_TARGET_ROOT33_TOG_REG(CCM_BASE_PTR) -#define CCM_POST33 CCM_POST33_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT33_SET CCM_POST_ROOT33_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT33_CLR CCM_POST_ROOT33_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT33_TOG CCM_POST_ROOT33_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE33 CCM_PRE33_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT33_SET CCM_PRE_ROOT33_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT33_CLR CCM_PRE_ROOT33_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT33_TOG CCM_PRE_ROOT33_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL33 CCM_ACCESS_CTRL33_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT33_SET CCM_ACCESS_CTRL33_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT33_CLR CCM_ACCESS_CTRL33_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT33_TOG CCM_ACCESS_CTRL33_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT34 CCM_TARGET_ROOT34_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT34_SET CCM_TARGET_ROOT34_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT34_CLR CCM_TARGET_ROOT34_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT34_TOG CCM_TARGET_ROOT34_TOG_REG(CCM_BASE_PTR) -#define CCM_POST34 CCM_POST34_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT34_SET CCM_POST_ROOT34_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT34_CLR CCM_POST_ROOT34_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT34_TOG CCM_POST_ROOT34_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE34 CCM_PRE34_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT34_SET CCM_PRE_ROOT34_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT34_CLR CCM_PRE_ROOT34_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT34_TOG CCM_PRE_ROOT34_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL34 CCM_ACCESS_CTRL34_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT34_SET CCM_ACCESS_CTRL34_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT34_CLR CCM_ACCESS_CTRL34_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT34_TOG CCM_ACCESS_CTRL34_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT35 CCM_TARGET_ROOT35_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT35_SET CCM_TARGET_ROOT35_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT35_CLR CCM_TARGET_ROOT35_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT35_TOG CCM_TARGET_ROOT35_TOG_REG(CCM_BASE_PTR) -#define CCM_POST35 CCM_POST35_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT35_SET CCM_POST_ROOT35_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT35_CLR CCM_POST_ROOT35_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT35_TOG CCM_POST_ROOT35_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE35 CCM_PRE35_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT35_SET CCM_PRE_ROOT35_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT35_CLR CCM_PRE_ROOT35_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT35_TOG CCM_PRE_ROOT35_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL35 CCM_ACCESS_CTRL35_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT35_SET CCM_ACCESS_CTRL35_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT35_CLR CCM_ACCESS_CTRL35_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT35_TOG CCM_ACCESS_CTRL35_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT36 CCM_TARGET_ROOT36_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT36_SET CCM_TARGET_ROOT36_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT36_CLR CCM_TARGET_ROOT36_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT36_TOG CCM_TARGET_ROOT36_TOG_REG(CCM_BASE_PTR) -#define CCM_POST36 CCM_POST36_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT36_SET CCM_POST_ROOT36_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT36_CLR CCM_POST_ROOT36_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT36_TOG CCM_POST_ROOT36_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE36 CCM_PRE36_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT36_SET CCM_PRE_ROOT36_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT36_CLR CCM_PRE_ROOT36_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT36_TOG CCM_PRE_ROOT36_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL36 CCM_ACCESS_CTRL36_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT36_SET CCM_ACCESS_CTRL36_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT36_CLR CCM_ACCESS_CTRL36_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT36_TOG CCM_ACCESS_CTRL36_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT37 CCM_TARGET_ROOT37_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT37_SET CCM_TARGET_ROOT37_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT37_CLR CCM_TARGET_ROOT37_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT37_TOG CCM_TARGET_ROOT37_TOG_REG(CCM_BASE_PTR) -#define CCM_POST37 CCM_POST37_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT37_SET CCM_POST_ROOT37_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT37_CLR CCM_POST_ROOT37_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT37_TOG CCM_POST_ROOT37_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE37 CCM_PRE37_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT37_SET CCM_PRE_ROOT37_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT37_CLR CCM_PRE_ROOT37_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT37_TOG CCM_PRE_ROOT37_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL37 CCM_ACCESS_CTRL37_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT37_SET CCM_ACCESS_CTRL37_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT37_CLR CCM_ACCESS_CTRL37_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT37_TOG CCM_ACCESS_CTRL37_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT38 CCM_TARGET_ROOT38_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT38_SET CCM_TARGET_ROOT38_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT38_CLR CCM_TARGET_ROOT38_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT38_TOG CCM_TARGET_ROOT38_TOG_REG(CCM_BASE_PTR) -#define CCM_POST38 CCM_POST38_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT38_SET CCM_POST_ROOT38_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT38_CLR CCM_POST_ROOT38_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT38_TOG CCM_POST_ROOT38_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE38 CCM_PRE38_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT38_SET CCM_PRE_ROOT38_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT38_CLR CCM_PRE_ROOT38_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT38_TOG CCM_PRE_ROOT38_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL38 CCM_ACCESS_CTRL38_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT38_SET CCM_ACCESS_CTRL38_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT38_CLR CCM_ACCESS_CTRL38_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT38_TOG CCM_ACCESS_CTRL38_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT39 CCM_TARGET_ROOT39_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT39_SET CCM_TARGET_ROOT39_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT39_CLR CCM_TARGET_ROOT39_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT39_TOG CCM_TARGET_ROOT39_TOG_REG(CCM_BASE_PTR) -#define CCM_POST39 CCM_POST39_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT39_SET CCM_POST_ROOT39_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT39_CLR CCM_POST_ROOT39_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT39_TOG CCM_POST_ROOT39_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE39 CCM_PRE39_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT39_SET CCM_PRE_ROOT39_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT39_CLR CCM_PRE_ROOT39_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT39_TOG CCM_PRE_ROOT39_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL39 CCM_ACCESS_CTRL39_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT39_SET CCM_ACCESS_CTRL39_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT39_CLR CCM_ACCESS_CTRL39_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT39_TOG CCM_ACCESS_CTRL39_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT40 CCM_TARGET_ROOT40_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT40_SET CCM_TARGET_ROOT40_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT40_CLR CCM_TARGET_ROOT40_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT40_TOG CCM_TARGET_ROOT40_TOG_REG(CCM_BASE_PTR) -#define CCM_POST40 CCM_POST40_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT40_SET CCM_POST_ROOT40_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT40_CLR CCM_POST_ROOT40_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT40_TOG CCM_POST_ROOT40_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE40 CCM_PRE40_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT40_SET CCM_PRE_ROOT40_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT40_CLR CCM_PRE_ROOT40_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT40_TOG CCM_PRE_ROOT40_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL40 CCM_ACCESS_CTRL40_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT40_SET CCM_ACCESS_CTRL40_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT40_CLR CCM_ACCESS_CTRL40_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT40_TOG CCM_ACCESS_CTRL40_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT41 CCM_TARGET_ROOT41_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT41_SET CCM_TARGET_ROOT41_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT41_CLR CCM_TARGET_ROOT41_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT41_TOG CCM_TARGET_ROOT41_TOG_REG(CCM_BASE_PTR) -#define CCM_POST41 CCM_POST41_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT41_SET CCM_POST_ROOT41_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT41_CLR CCM_POST_ROOT41_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT41_TOG CCM_POST_ROOT41_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE41 CCM_PRE41_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT41_SET CCM_PRE_ROOT41_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT41_CLR CCM_PRE_ROOT41_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT41_TOG CCM_PRE_ROOT41_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL41 CCM_ACCESS_CTRL41_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT41_SET CCM_ACCESS_CTRL41_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT41_CLR CCM_ACCESS_CTRL41_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT41_TOG CCM_ACCESS_CTRL41_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT42 CCM_TARGET_ROOT42_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT42_SET CCM_TARGET_ROOT42_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT42_CLR CCM_TARGET_ROOT42_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT42_TOG CCM_TARGET_ROOT42_TOG_REG(CCM_BASE_PTR) -#define CCM_POST42 CCM_POST42_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT42_SET CCM_POST_ROOT42_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT42_CLR CCM_POST_ROOT42_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT42_TOG CCM_POST_ROOT42_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE42 CCM_PRE42_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT42_SET CCM_PRE_ROOT42_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT42_CLR CCM_PRE_ROOT42_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT42_TOG CCM_PRE_ROOT42_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL42 CCM_ACCESS_CTRL42_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT42_SET CCM_ACCESS_CTRL42_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT42_CLR CCM_ACCESS_CTRL42_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT42_TOG CCM_ACCESS_CTRL42_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT43 CCM_TARGET_ROOT43_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT43_SET CCM_TARGET_ROOT43_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT43_CLR CCM_TARGET_ROOT43_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT43_TOG CCM_TARGET_ROOT43_TOG_REG(CCM_BASE_PTR) -#define CCM_POST43 CCM_POST43_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT43_SET CCM_POST_ROOT43_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT43_CLR CCM_POST_ROOT43_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT43_TOG CCM_POST_ROOT43_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE43 CCM_PRE43_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT43_SET CCM_PRE_ROOT43_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT43_CLR CCM_PRE_ROOT43_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT43_TOG CCM_PRE_ROOT43_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL43 CCM_ACCESS_CTRL43_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT43_SET CCM_ACCESS_CTRL43_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT43_CLR CCM_ACCESS_CTRL43_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT43_TOG CCM_ACCESS_CTRL43_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT44 CCM_TARGET_ROOT44_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT44_SET CCM_TARGET_ROOT44_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT44_CLR CCM_TARGET_ROOT44_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT44_TOG CCM_TARGET_ROOT44_TOG_REG(CCM_BASE_PTR) -#define CCM_POST44 CCM_POST44_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT44_SET CCM_POST_ROOT44_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT44_CLR CCM_POST_ROOT44_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT44_TOG CCM_POST_ROOT44_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE44 CCM_PRE44_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT44_SET CCM_PRE_ROOT44_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT44_CLR CCM_PRE_ROOT44_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT44_TOG CCM_PRE_ROOT44_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL44 CCM_ACCESS_CTRL44_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT44_SET CCM_ACCESS_CTRL44_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT44_CLR CCM_ACCESS_CTRL44_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT44_TOG CCM_ACCESS_CTRL44_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT45 CCM_TARGET_ROOT45_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT45_SET CCM_TARGET_ROOT45_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT45_CLR CCM_TARGET_ROOT45_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT45_TOG CCM_TARGET_ROOT45_TOG_REG(CCM_BASE_PTR) -#define CCM_POST45 CCM_POST45_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT45_SET CCM_POST_ROOT45_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT45_CLR CCM_POST_ROOT45_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT45_TOG CCM_POST_ROOT45_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE45 CCM_PRE45_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT45_SET CCM_PRE_ROOT45_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT45_CLR CCM_PRE_ROOT45_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT45_TOG CCM_PRE_ROOT45_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL45 CCM_ACCESS_CTRL45_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT45_SET CCM_ACCESS_CTRL45_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT45_CLR CCM_ACCESS_CTRL45_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT45_TOG CCM_ACCESS_CTRL45_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT46 CCM_TARGET_ROOT46_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT46_SET CCM_TARGET_ROOT46_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT46_CLR CCM_TARGET_ROOT46_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT46_TOG CCM_TARGET_ROOT46_TOG_REG(CCM_BASE_PTR) -#define CCM_POST46 CCM_POST46_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT46_SET CCM_POST_ROOT46_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT46_CLR CCM_POST_ROOT46_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT46_TOG CCM_POST_ROOT46_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE46 CCM_PRE46_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT46_SET CCM_PRE_ROOT46_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT46_CLR CCM_PRE_ROOT46_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT46_TOG CCM_PRE_ROOT46_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL46 CCM_ACCESS_CTRL46_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT46_SET CCM_ACCESS_CTRL46_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT46_CLR CCM_ACCESS_CTRL46_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT46_TOG CCM_ACCESS_CTRL46_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT47 CCM_TARGET_ROOT47_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT47_SET CCM_TARGET_ROOT47_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT47_CLR CCM_TARGET_ROOT47_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT47_TOG CCM_TARGET_ROOT47_TOG_REG(CCM_BASE_PTR) -#define CCM_POST47 CCM_POST47_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT47_SET CCM_POST_ROOT47_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT47_CLR CCM_POST_ROOT47_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT47_TOG CCM_POST_ROOT47_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE47 CCM_PRE47_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT47_SET CCM_PRE_ROOT47_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT47_CLR CCM_PRE_ROOT47_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT47_TOG CCM_PRE_ROOT47_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL47 CCM_ACCESS_CTRL47_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT47_SET CCM_ACCESS_CTRL47_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT47_CLR CCM_ACCESS_CTRL47_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT47_TOG CCM_ACCESS_CTRL47_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT48 CCM_TARGET_ROOT48_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT48_SET CCM_TARGET_ROOT48_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT48_CLR CCM_TARGET_ROOT48_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT48_TOG CCM_TARGET_ROOT48_TOG_REG(CCM_BASE_PTR) -#define CCM_POST48 CCM_POST48_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT48_SET CCM_POST_ROOT48_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT48_CLR CCM_POST_ROOT48_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT48_TOG CCM_POST_ROOT48_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE48 CCM_PRE48_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT48_SET CCM_PRE_ROOT48_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT48_CLR CCM_PRE_ROOT48_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT48_TOG CCM_PRE_ROOT48_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL48 CCM_ACCESS_CTRL48_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT48_SET CCM_ACCESS_CTRL48_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT48_CLR CCM_ACCESS_CTRL48_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT48_TOG CCM_ACCESS_CTRL48_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT49 CCM_TARGET_ROOT49_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT49_SET CCM_TARGET_ROOT49_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT49_CLR CCM_TARGET_ROOT49_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT49_TOG CCM_TARGET_ROOT49_TOG_REG(CCM_BASE_PTR) -#define CCM_POST49 CCM_POST49_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT49_SET CCM_POST_ROOT49_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT49_CLR CCM_POST_ROOT49_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT49_TOG CCM_POST_ROOT49_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE49 CCM_PRE49_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT49_SET CCM_PRE_ROOT49_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT49_CLR CCM_PRE_ROOT49_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT49_TOG CCM_PRE_ROOT49_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL49 CCM_ACCESS_CTRL49_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT49_SET CCM_ACCESS_CTRL49_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT49_CLR CCM_ACCESS_CTRL49_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT49_TOG CCM_ACCESS_CTRL49_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT50 CCM_TARGET_ROOT50_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT50_SET CCM_TARGET_ROOT50_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT50_CLR CCM_TARGET_ROOT50_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT50_TOG CCM_TARGET_ROOT50_TOG_REG(CCM_BASE_PTR) -#define CCM_POST50 CCM_POST50_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT50_SET CCM_POST_ROOT50_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT50_CLR CCM_POST_ROOT50_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT50_TOG CCM_POST_ROOT50_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE50 CCM_PRE50_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT50_SET CCM_PRE_ROOT50_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT50_CLR CCM_PRE_ROOT50_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT50_TOG CCM_PRE_ROOT50_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL50 CCM_ACCESS_CTRL50_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT50_SET CCM_ACCESS_CTRL50_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT50_CLR CCM_ACCESS_CTRL50_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT50_TOG CCM_ACCESS_CTRL50_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT51 CCM_TARGET_ROOT51_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT51_SET CCM_TARGET_ROOT51_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT51_CLR CCM_TARGET_ROOT51_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT51_TOG CCM_TARGET_ROOT51_TOG_REG(CCM_BASE_PTR) -#define CCM_POST51 CCM_POST51_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT51_SET CCM_POST_ROOT51_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT51_CLR CCM_POST_ROOT51_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT51_TOG CCM_POST_ROOT51_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE51 CCM_PRE51_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT51_SET CCM_PRE_ROOT51_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT51_CLR CCM_PRE_ROOT51_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT51_TOG CCM_PRE_ROOT51_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL51 CCM_ACCESS_CTRL51_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT51_SET CCM_ACCESS_CTRL51_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT51_CLR CCM_ACCESS_CTRL51_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT51_TOG CCM_ACCESS_CTRL51_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT52 CCM_TARGET_ROOT52_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT52_SET CCM_TARGET_ROOT52_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT52_CLR CCM_TARGET_ROOT52_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT52_TOG CCM_TARGET_ROOT52_TOG_REG(CCM_BASE_PTR) -#define CCM_POST52 CCM_POST52_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT52_SET CCM_POST_ROOT52_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT52_CLR CCM_POST_ROOT52_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT52_TOG CCM_POST_ROOT52_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE52 CCM_PRE52_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT52_SET CCM_PRE_ROOT52_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT52_CLR CCM_PRE_ROOT52_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT52_TOG CCM_PRE_ROOT52_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL52 CCM_ACCESS_CTRL52_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT52_SET CCM_ACCESS_CTRL52_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT52_CLR CCM_ACCESS_CTRL52_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT52_TOG CCM_ACCESS_CTRL52_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT53 CCM_TARGET_ROOT53_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT53_SET CCM_TARGET_ROOT53_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT53_CLR CCM_TARGET_ROOT53_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT53_TOG CCM_TARGET_ROOT53_TOG_REG(CCM_BASE_PTR) -#define CCM_POST53 CCM_POST53_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT53_SET CCM_POST_ROOT53_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT53_CLR CCM_POST_ROOT53_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT53_TOG CCM_POST_ROOT53_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE53 CCM_PRE53_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT53_SET CCM_PRE_ROOT53_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT53_CLR CCM_PRE_ROOT53_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT53_TOG CCM_PRE_ROOT53_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL53 CCM_ACCESS_CTRL53_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT53_SET CCM_ACCESS_CTRL53_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT53_CLR CCM_ACCESS_CTRL53_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT53_TOG CCM_ACCESS_CTRL53_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT54 CCM_TARGET_ROOT54_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT54_SET CCM_TARGET_ROOT54_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT54_CLR CCM_TARGET_ROOT54_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT54_TOG CCM_TARGET_ROOT54_TOG_REG(CCM_BASE_PTR) -#define CCM_POST54 CCM_POST54_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT54_SET CCM_POST_ROOT54_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT54_CLR CCM_POST_ROOT54_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT54_TOG CCM_POST_ROOT54_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE54 CCM_PRE54_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT54_SET CCM_PRE_ROOT54_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT54_CLR CCM_PRE_ROOT54_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT54_TOG CCM_PRE_ROOT54_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL54 CCM_ACCESS_CTRL54_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT54_SET CCM_ACCESS_CTRL54_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT54_CLR CCM_ACCESS_CTRL54_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT54_TOG CCM_ACCESS_CTRL54_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT55 CCM_TARGET_ROOT55_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT55_SET CCM_TARGET_ROOT55_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT55_CLR CCM_TARGET_ROOT55_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT55_TOG CCM_TARGET_ROOT55_TOG_REG(CCM_BASE_PTR) -#define CCM_POST55 CCM_POST55_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT55_SET CCM_POST_ROOT55_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT55_CLR CCM_POST_ROOT55_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT55_TOG CCM_POST_ROOT55_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE55 CCM_PRE55_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT55_SET CCM_PRE_ROOT55_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT55_CLR CCM_PRE_ROOT55_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT55_TOG CCM_PRE_ROOT55_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL55 CCM_ACCESS_CTRL55_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT55_SET CCM_ACCESS_CTRL55_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT55_CLR CCM_ACCESS_CTRL55_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT55_TOG CCM_ACCESS_CTRL55_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT56 CCM_TARGET_ROOT56_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT56_SET CCM_TARGET_ROOT56_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT56_CLR CCM_TARGET_ROOT56_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT56_TOG CCM_TARGET_ROOT56_TOG_REG(CCM_BASE_PTR) -#define CCM_POST56 CCM_POST56_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT56_SET CCM_POST_ROOT56_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT56_CLR CCM_POST_ROOT56_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT56_TOG CCM_POST_ROOT56_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE56 CCM_PRE56_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT56_SET CCM_PRE_ROOT56_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT56_CLR CCM_PRE_ROOT56_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT56_TOG CCM_PRE_ROOT56_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL56 CCM_ACCESS_CTRL56_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT56_SET CCM_ACCESS_CTRL56_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT56_CLR CCM_ACCESS_CTRL56_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT56_TOG CCM_ACCESS_CTRL56_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT57 CCM_TARGET_ROOT57_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT57_SET CCM_TARGET_ROOT57_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT57_CLR CCM_TARGET_ROOT57_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT57_TOG CCM_TARGET_ROOT57_TOG_REG(CCM_BASE_PTR) -#define CCM_POST57 CCM_POST57_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT57_SET CCM_POST_ROOT57_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT57_CLR CCM_POST_ROOT57_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT57_TOG CCM_POST_ROOT57_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE57 CCM_PRE57_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT57_SET CCM_PRE_ROOT57_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT57_CLR CCM_PRE_ROOT57_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT57_TOG CCM_PRE_ROOT57_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL57 CCM_ACCESS_CTRL57_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT57_SET CCM_ACCESS_CTRL57_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT57_CLR CCM_ACCESS_CTRL57_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT57_TOG CCM_ACCESS_CTRL57_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT58 CCM_TARGET_ROOT58_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT58_SET CCM_TARGET_ROOT58_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT58_CLR CCM_TARGET_ROOT58_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT58_TOG CCM_TARGET_ROOT58_TOG_REG(CCM_BASE_PTR) -#define CCM_POST58 CCM_POST58_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT58_SET CCM_POST_ROOT58_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT58_CLR CCM_POST_ROOT58_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT58_TOG CCM_POST_ROOT58_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE58 CCM_PRE58_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT58_SET CCM_PRE_ROOT58_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT58_CLR CCM_PRE_ROOT58_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT58_TOG CCM_PRE_ROOT58_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL58 CCM_ACCESS_CTRL58_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT58_SET CCM_ACCESS_CTRL58_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT58_CLR CCM_ACCESS_CTRL58_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT58_TOG CCM_ACCESS_CTRL58_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT59 CCM_TARGET_ROOT59_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT59_SET CCM_TARGET_ROOT59_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT59_CLR CCM_TARGET_ROOT59_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT59_TOG CCM_TARGET_ROOT59_TOG_REG(CCM_BASE_PTR) -#define CCM_POST59 CCM_POST59_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT59_SET CCM_POST_ROOT59_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT59_CLR CCM_POST_ROOT59_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT59_TOG CCM_POST_ROOT59_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE59 CCM_PRE59_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT59_SET CCM_PRE_ROOT59_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT59_CLR CCM_PRE_ROOT59_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT59_TOG CCM_PRE_ROOT59_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL59 CCM_ACCESS_CTRL59_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT59_SET CCM_ACCESS_CTRL59_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT59_CLR CCM_ACCESS_CTRL59_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT59_TOG CCM_ACCESS_CTRL59_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT60 CCM_TARGET_ROOT60_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT60_SET CCM_TARGET_ROOT60_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT60_CLR CCM_TARGET_ROOT60_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT60_TOG CCM_TARGET_ROOT60_TOG_REG(CCM_BASE_PTR) -#define CCM_POST60 CCM_POST60_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT60_SET CCM_POST_ROOT60_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT60_CLR CCM_POST_ROOT60_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT60_TOG CCM_POST_ROOT60_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE60 CCM_PRE60_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT60_SET CCM_PRE_ROOT60_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT60_CLR CCM_PRE_ROOT60_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT60_TOG CCM_PRE_ROOT60_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL60 CCM_ACCESS_CTRL60_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT60_SET CCM_ACCESS_CTRL60_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT60_CLR CCM_ACCESS_CTRL60_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT60_TOG CCM_ACCESS_CTRL60_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT61 CCM_TARGET_ROOT61_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT61_SET CCM_TARGET_ROOT61_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT61_CLR CCM_TARGET_ROOT61_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT61_TOG CCM_TARGET_ROOT61_TOG_REG(CCM_BASE_PTR) -#define CCM_POST61 CCM_POST61_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT61_SET CCM_POST_ROOT61_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT61_CLR CCM_POST_ROOT61_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT61_TOG CCM_POST_ROOT61_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE61 CCM_PRE61_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT61_SET CCM_PRE_ROOT61_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT61_CLR CCM_PRE_ROOT61_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT61_TOG CCM_PRE_ROOT61_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL61 CCM_ACCESS_CTRL61_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT61_SET CCM_ACCESS_CTRL61_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT61_CLR CCM_ACCESS_CTRL61_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT61_TOG CCM_ACCESS_CTRL61_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT62 CCM_TARGET_ROOT62_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT62_SET CCM_TARGET_ROOT62_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT62_CLR CCM_TARGET_ROOT62_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT62_TOG CCM_TARGET_ROOT62_TOG_REG(CCM_BASE_PTR) -#define CCM_POST62 CCM_POST62_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT62_SET CCM_POST_ROOT62_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT62_CLR CCM_POST_ROOT62_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT62_TOG CCM_POST_ROOT62_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE62 CCM_PRE62_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT62_SET CCM_PRE_ROOT62_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT62_CLR CCM_PRE_ROOT62_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT62_TOG CCM_PRE_ROOT62_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL62 CCM_ACCESS_CTRL62_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT62_SET CCM_ACCESS_CTRL62_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT62_CLR CCM_ACCESS_CTRL62_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT62_TOG CCM_ACCESS_CTRL62_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT63 CCM_TARGET_ROOT63_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT63_SET CCM_TARGET_ROOT63_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT63_CLR CCM_TARGET_ROOT63_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT63_TOG CCM_TARGET_ROOT63_TOG_REG(CCM_BASE_PTR) -#define CCM_POST63 CCM_POST63_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT63_SET CCM_POST_ROOT63_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT63_CLR CCM_POST_ROOT63_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT63_TOG CCM_POST_ROOT63_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE63 CCM_PRE63_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT63_SET CCM_PRE_ROOT63_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT63_CLR CCM_PRE_ROOT63_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT63_TOG CCM_PRE_ROOT63_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL63 CCM_ACCESS_CTRL63_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT63_SET CCM_ACCESS_CTRL63_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT63_CLR CCM_ACCESS_CTRL63_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT63_TOG CCM_ACCESS_CTRL63_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT64 CCM_TARGET_ROOT64_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT64_SET CCM_TARGET_ROOT64_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT64_CLR CCM_TARGET_ROOT64_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT64_TOG CCM_TARGET_ROOT64_TOG_REG(CCM_BASE_PTR) -#define CCM_POST64 CCM_POST64_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT64_SET CCM_POST_ROOT64_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT64_CLR CCM_POST_ROOT64_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT64_TOG CCM_POST_ROOT64_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE64 CCM_PRE64_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT64_SET CCM_PRE_ROOT64_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT64_CLR CCM_PRE_ROOT64_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT64_TOG CCM_PRE_ROOT64_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL64 CCM_ACCESS_CTRL64_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT64_SET CCM_ACCESS_CTRL64_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT64_CLR CCM_ACCESS_CTRL64_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT64_TOG CCM_ACCESS_CTRL64_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT65 CCM_TARGET_ROOT65_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT65_SET CCM_TARGET_ROOT65_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT65_CLR CCM_TARGET_ROOT65_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT65_TOG CCM_TARGET_ROOT65_TOG_REG(CCM_BASE_PTR) -#define CCM_POST65 CCM_POST65_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT65_SET CCM_POST_ROOT65_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT65_CLR CCM_POST_ROOT65_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT65_TOG CCM_POST_ROOT65_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE65 CCM_PRE65_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT65_SET CCM_PRE_ROOT65_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT65_CLR CCM_PRE_ROOT65_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT65_TOG CCM_PRE_ROOT65_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL65 CCM_ACCESS_CTRL65_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT65_SET CCM_ACCESS_CTRL65_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT65_CLR CCM_ACCESS_CTRL65_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT65_TOG CCM_ACCESS_CTRL65_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT66 CCM_TARGET_ROOT66_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT66_SET CCM_TARGET_ROOT66_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT66_CLR CCM_TARGET_ROOT66_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT66_TOG CCM_TARGET_ROOT66_TOG_REG(CCM_BASE_PTR) -#define CCM_POST66 CCM_POST66_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT66_SET CCM_POST_ROOT66_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT66_CLR CCM_POST_ROOT66_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT66_TOG CCM_POST_ROOT66_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE66 CCM_PRE66_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT66_SET CCM_PRE_ROOT66_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT66_CLR CCM_PRE_ROOT66_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT66_TOG CCM_PRE_ROOT66_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL66 CCM_ACCESS_CTRL66_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT66_SET CCM_ACCESS_CTRL66_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT66_CLR CCM_ACCESS_CTRL66_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT66_TOG CCM_ACCESS_CTRL66_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT67 CCM_TARGET_ROOT67_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT67_SET CCM_TARGET_ROOT67_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT67_CLR CCM_TARGET_ROOT67_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT67_TOG CCM_TARGET_ROOT67_TOG_REG(CCM_BASE_PTR) -#define CCM_POST67 CCM_POST67_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT67_SET CCM_POST_ROOT67_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT67_CLR CCM_POST_ROOT67_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT67_TOG CCM_POST_ROOT67_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE67 CCM_PRE67_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT67_SET CCM_PRE_ROOT67_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT67_CLR CCM_PRE_ROOT67_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT67_TOG CCM_PRE_ROOT67_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL67 CCM_ACCESS_CTRL67_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT67_SET CCM_ACCESS_CTRL67_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT67_CLR CCM_ACCESS_CTRL67_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT67_TOG CCM_ACCESS_CTRL67_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT68 CCM_TARGET_ROOT68_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT68_SET CCM_TARGET_ROOT68_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT68_CLR CCM_TARGET_ROOT68_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT68_TOG CCM_TARGET_ROOT68_TOG_REG(CCM_BASE_PTR) -#define CCM_POST68 CCM_POST68_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT68_SET CCM_POST_ROOT68_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT68_CLR CCM_POST_ROOT68_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT68_TOG CCM_POST_ROOT68_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE68 CCM_PRE68_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT68_SET CCM_PRE_ROOT68_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT68_CLR CCM_PRE_ROOT68_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT68_TOG CCM_PRE_ROOT68_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL68 CCM_ACCESS_CTRL68_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT68_SET CCM_ACCESS_CTRL68_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT68_CLR CCM_ACCESS_CTRL68_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT68_TOG CCM_ACCESS_CTRL68_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT69 CCM_TARGET_ROOT69_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT69_SET CCM_TARGET_ROOT69_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT69_CLR CCM_TARGET_ROOT69_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT69_TOG CCM_TARGET_ROOT69_TOG_REG(CCM_BASE_PTR) -#define CCM_POST69 CCM_POST69_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT69_SET CCM_POST_ROOT69_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT69_CLR CCM_POST_ROOT69_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT69_TOG CCM_POST_ROOT69_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE69 CCM_PRE69_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT69_SET CCM_PRE_ROOT69_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT69_CLR CCM_PRE_ROOT69_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT69_TOG CCM_PRE_ROOT69_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL69 CCM_ACCESS_CTRL69_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT69_SET CCM_ACCESS_CTRL69_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT69_CLR CCM_ACCESS_CTRL69_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT69_TOG CCM_ACCESS_CTRL69_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT70 CCM_TARGET_ROOT70_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT70_SET CCM_TARGET_ROOT70_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT70_CLR CCM_TARGET_ROOT70_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT70_TOG CCM_TARGET_ROOT70_TOG_REG(CCM_BASE_PTR) -#define CCM_POST70 CCM_POST70_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT70_SET CCM_POST_ROOT70_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT70_CLR CCM_POST_ROOT70_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT70_TOG CCM_POST_ROOT70_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE70 CCM_PRE70_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT70_SET CCM_PRE_ROOT70_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT70_CLR CCM_PRE_ROOT70_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT70_TOG CCM_PRE_ROOT70_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL70 CCM_ACCESS_CTRL70_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT70_SET CCM_ACCESS_CTRL70_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT70_CLR CCM_ACCESS_CTRL70_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT70_TOG CCM_ACCESS_CTRL70_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT71 CCM_TARGET_ROOT71_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT71_SET CCM_TARGET_ROOT71_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT71_CLR CCM_TARGET_ROOT71_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT71_TOG CCM_TARGET_ROOT71_TOG_REG(CCM_BASE_PTR) -#define CCM_POST71 CCM_POST71_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT71_SET CCM_POST_ROOT71_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT71_CLR CCM_POST_ROOT71_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT71_TOG CCM_POST_ROOT71_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE71 CCM_PRE71_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT71_SET CCM_PRE_ROOT71_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT71_CLR CCM_PRE_ROOT71_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT71_TOG CCM_PRE_ROOT71_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL71 CCM_ACCESS_CTRL71_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT71_SET CCM_ACCESS_CTRL71_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT71_CLR CCM_ACCESS_CTRL71_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT71_TOG CCM_ACCESS_CTRL71_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT72 CCM_TARGET_ROOT72_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT72_SET CCM_TARGET_ROOT72_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT72_CLR CCM_TARGET_ROOT72_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT72_TOG CCM_TARGET_ROOT72_TOG_REG(CCM_BASE_PTR) -#define CCM_POST72 CCM_POST72_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT72_SET CCM_POST_ROOT72_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT72_CLR CCM_POST_ROOT72_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT72_TOG CCM_POST_ROOT72_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE72 CCM_PRE72_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT72_SET CCM_PRE_ROOT72_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT72_CLR CCM_PRE_ROOT72_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT72_TOG CCM_PRE_ROOT72_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL72 CCM_ACCESS_CTRL72_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT72_SET CCM_ACCESS_CTRL72_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT72_CLR CCM_ACCESS_CTRL72_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT72_TOG CCM_ACCESS_CTRL72_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT73 CCM_TARGET_ROOT73_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT73_SET CCM_TARGET_ROOT73_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT73_CLR CCM_TARGET_ROOT73_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT73_TOG CCM_TARGET_ROOT73_TOG_REG(CCM_BASE_PTR) -#define CCM_POST73 CCM_POST73_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT73_SET CCM_POST_ROOT73_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT73_CLR CCM_POST_ROOT73_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT73_TOG CCM_POST_ROOT73_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE73 CCM_PRE73_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT73_SET CCM_PRE_ROOT73_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT73_CLR CCM_PRE_ROOT73_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT73_TOG CCM_PRE_ROOT73_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL73 CCM_ACCESS_CTRL73_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT73_SET CCM_ACCESS_CTRL73_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT73_CLR CCM_ACCESS_CTRL73_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT73_TOG CCM_ACCESS_CTRL73_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT74 CCM_TARGET_ROOT74_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT74_SET CCM_TARGET_ROOT74_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT74_CLR CCM_TARGET_ROOT74_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT74_TOG CCM_TARGET_ROOT74_TOG_REG(CCM_BASE_PTR) -#define CCM_POST74 CCM_POST74_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT74_SET CCM_POST_ROOT74_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT74_CLR CCM_POST_ROOT74_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT74_TOG CCM_POST_ROOT74_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE74 CCM_PRE74_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT74_SET CCM_PRE_ROOT74_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT74_CLR CCM_PRE_ROOT74_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT74_TOG CCM_PRE_ROOT74_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL74 CCM_ACCESS_CTRL74_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT74_SET CCM_ACCESS_CTRL74_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT74_CLR CCM_ACCESS_CTRL74_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT74_TOG CCM_ACCESS_CTRL74_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT75 CCM_TARGET_ROOT75_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT75_SET CCM_TARGET_ROOT75_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT75_CLR CCM_TARGET_ROOT75_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT75_TOG CCM_TARGET_ROOT75_TOG_REG(CCM_BASE_PTR) -#define CCM_POST75 CCM_POST75_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT75_SET CCM_POST_ROOT75_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT75_CLR CCM_POST_ROOT75_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT75_TOG CCM_POST_ROOT75_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE75 CCM_PRE75_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT75_SET CCM_PRE_ROOT75_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT75_CLR CCM_PRE_ROOT75_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT75_TOG CCM_PRE_ROOT75_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL75 CCM_ACCESS_CTRL75_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT75_SET CCM_ACCESS_CTRL75_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT75_CLR CCM_ACCESS_CTRL75_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT75_TOG CCM_ACCESS_CTRL75_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT76 CCM_TARGET_ROOT76_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT76_SET CCM_TARGET_ROOT76_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT76_CLR CCM_TARGET_ROOT76_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT76_TOG CCM_TARGET_ROOT76_TOG_REG(CCM_BASE_PTR) -#define CCM_POST76 CCM_POST76_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT76_SET CCM_POST_ROOT76_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT76_CLR CCM_POST_ROOT76_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT76_TOG CCM_POST_ROOT76_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE76 CCM_PRE76_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT76_SET CCM_PRE_ROOT76_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT76_CLR CCM_PRE_ROOT76_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT76_TOG CCM_PRE_ROOT76_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL76 CCM_ACCESS_CTRL76_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT76_SET CCM_ACCESS_CTRL76_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT76_CLR CCM_ACCESS_CTRL76_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT76_TOG CCM_ACCESS_CTRL76_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT77 CCM_TARGET_ROOT77_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT77_SET CCM_TARGET_ROOT77_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT77_CLR CCM_TARGET_ROOT77_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT77_TOG CCM_TARGET_ROOT77_TOG_REG(CCM_BASE_PTR) -#define CCM_POST77 CCM_POST77_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT77_SET CCM_POST_ROOT77_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT77_CLR CCM_POST_ROOT77_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT77_TOG CCM_POST_ROOT77_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE77 CCM_PRE77_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT77_SET CCM_PRE_ROOT77_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT77_CLR CCM_PRE_ROOT77_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT77_TOG CCM_PRE_ROOT77_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL77 CCM_ACCESS_CTRL77_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT77_SET CCM_ACCESS_CTRL77_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT77_CLR CCM_ACCESS_CTRL77_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT77_TOG CCM_ACCESS_CTRL77_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT78 CCM_TARGET_ROOT78_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT78_SET CCM_TARGET_ROOT78_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT78_CLR CCM_TARGET_ROOT78_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT78_TOG CCM_TARGET_ROOT78_TOG_REG(CCM_BASE_PTR) -#define CCM_POST78 CCM_POST78_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT78_SET CCM_POST_ROOT78_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT78_CLR CCM_POST_ROOT78_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT78_TOG CCM_POST_ROOT78_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE78 CCM_PRE78_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT78_SET CCM_PRE_ROOT78_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT78_CLR CCM_PRE_ROOT78_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT78_TOG CCM_PRE_ROOT78_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL78 CCM_ACCESS_CTRL78_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT78_SET CCM_ACCESS_CTRL78_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT78_CLR CCM_ACCESS_CTRL78_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT78_TOG CCM_ACCESS_CTRL78_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT79 CCM_TARGET_ROOT79_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT79_SET CCM_TARGET_ROOT79_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT79_CLR CCM_TARGET_ROOT79_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT79_TOG CCM_TARGET_ROOT79_TOG_REG(CCM_BASE_PTR) -#define CCM_POST79 CCM_POST79_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT79_SET CCM_POST_ROOT79_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT79_CLR CCM_POST_ROOT79_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT79_TOG CCM_POST_ROOT79_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE79 CCM_PRE79_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT79_SET CCM_PRE_ROOT79_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT79_CLR CCM_PRE_ROOT79_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT79_TOG CCM_PRE_ROOT79_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL79 CCM_ACCESS_CTRL79_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT79_SET CCM_ACCESS_CTRL79_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT79_CLR CCM_ACCESS_CTRL79_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT79_TOG CCM_ACCESS_CTRL79_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT80 CCM_TARGET_ROOT80_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT80_SET CCM_TARGET_ROOT80_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT80_CLR CCM_TARGET_ROOT80_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT80_TOG CCM_TARGET_ROOT80_TOG_REG(CCM_BASE_PTR) -#define CCM_POST80 CCM_POST80_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT80_SET CCM_POST_ROOT80_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT80_CLR CCM_POST_ROOT80_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT80_TOG CCM_POST_ROOT80_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE80 CCM_PRE80_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT80_SET CCM_PRE_ROOT80_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT80_CLR CCM_PRE_ROOT80_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT80_TOG CCM_PRE_ROOT80_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL80 CCM_ACCESS_CTRL80_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT80_SET CCM_ACCESS_CTRL80_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT80_CLR CCM_ACCESS_CTRL80_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT80_TOG CCM_ACCESS_CTRL80_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT81 CCM_TARGET_ROOT81_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT81_SET CCM_TARGET_ROOT81_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT81_CLR CCM_TARGET_ROOT81_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT81_TOG CCM_TARGET_ROOT81_TOG_REG(CCM_BASE_PTR) -#define CCM_POST81 CCM_POST81_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT81_SET CCM_POST_ROOT81_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT81_CLR CCM_POST_ROOT81_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT81_TOG CCM_POST_ROOT81_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE81 CCM_PRE81_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT81_SET CCM_PRE_ROOT81_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT81_CLR CCM_PRE_ROOT81_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT81_TOG CCM_PRE_ROOT81_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL81 CCM_ACCESS_CTRL81_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT81_SET CCM_ACCESS_CTRL81_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT81_CLR CCM_ACCESS_CTRL81_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT81_TOG CCM_ACCESS_CTRL81_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT82 CCM_TARGET_ROOT82_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT82_SET CCM_TARGET_ROOT82_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT82_CLR CCM_TARGET_ROOT82_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT82_TOG CCM_TARGET_ROOT82_TOG_REG(CCM_BASE_PTR) -#define CCM_POST82 CCM_POST82_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT82_SET CCM_POST_ROOT82_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT82_CLR CCM_POST_ROOT82_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT82_TOG CCM_POST_ROOT82_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE82 CCM_PRE82_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT82_SET CCM_PRE_ROOT82_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT82_CLR CCM_PRE_ROOT82_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT82_TOG CCM_PRE_ROOT82_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL82 CCM_ACCESS_CTRL82_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT82_SET CCM_ACCESS_CTRL82_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT82_CLR CCM_ACCESS_CTRL82_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT82_TOG CCM_ACCESS_CTRL82_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT83 CCM_TARGET_ROOT83_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT83_SET CCM_TARGET_ROOT83_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT83_CLR CCM_TARGET_ROOT83_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT83_TOG CCM_TARGET_ROOT83_TOG_REG(CCM_BASE_PTR) -#define CCM_POST83 CCM_POST83_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT83_SET CCM_POST_ROOT83_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT83_CLR CCM_POST_ROOT83_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT83_TOG CCM_POST_ROOT83_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE83 CCM_PRE83_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT83_SET CCM_PRE_ROOT83_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT83_CLR CCM_PRE_ROOT83_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT83_TOG CCM_PRE_ROOT83_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL83 CCM_ACCESS_CTRL83_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT83_SET CCM_ACCESS_CTRL83_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT83_CLR CCM_ACCESS_CTRL83_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT83_TOG CCM_ACCESS_CTRL83_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT84 CCM_TARGET_ROOT84_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT84_SET CCM_TARGET_ROOT84_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT84_CLR CCM_TARGET_ROOT84_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT84_TOG CCM_TARGET_ROOT84_TOG_REG(CCM_BASE_PTR) -#define CCM_POST84 CCM_POST84_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT84_SET CCM_POST_ROOT84_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT84_CLR CCM_POST_ROOT84_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT84_TOG CCM_POST_ROOT84_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE84 CCM_PRE84_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT84_SET CCM_PRE_ROOT84_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT84_CLR CCM_PRE_ROOT84_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT84_TOG CCM_PRE_ROOT84_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL84 CCM_ACCESS_CTRL84_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT84_SET CCM_ACCESS_CTRL84_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT84_CLR CCM_ACCESS_CTRL84_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT84_TOG CCM_ACCESS_CTRL84_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT85 CCM_TARGET_ROOT85_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT85_SET CCM_TARGET_ROOT85_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT85_CLR CCM_TARGET_ROOT85_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT85_TOG CCM_TARGET_ROOT85_TOG_REG(CCM_BASE_PTR) -#define CCM_POST85 CCM_POST85_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT85_SET CCM_POST_ROOT85_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT85_CLR CCM_POST_ROOT85_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT85_TOG CCM_POST_ROOT85_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE85 CCM_PRE85_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT85_SET CCM_PRE_ROOT85_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT85_CLR CCM_PRE_ROOT85_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT85_TOG CCM_PRE_ROOT85_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL85 CCM_ACCESS_CTRL85_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT85_SET CCM_ACCESS_CTRL85_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT85_CLR CCM_ACCESS_CTRL85_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT85_TOG CCM_ACCESS_CTRL85_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT86 CCM_TARGET_ROOT86_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT86_SET CCM_TARGET_ROOT86_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT86_CLR CCM_TARGET_ROOT86_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT86_TOG CCM_TARGET_ROOT86_TOG_REG(CCM_BASE_PTR) -#define CCM_POST86 CCM_POST86_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT86_SET CCM_POST_ROOT86_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT86_CLR CCM_POST_ROOT86_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT86_TOG CCM_POST_ROOT86_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE86 CCM_PRE86_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT86_SET CCM_PRE_ROOT86_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT86_CLR CCM_PRE_ROOT86_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT86_TOG CCM_PRE_ROOT86_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL86 CCM_ACCESS_CTRL86_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT86_SET CCM_ACCESS_CTRL86_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT86_CLR CCM_ACCESS_CTRL86_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT86_TOG CCM_ACCESS_CTRL86_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT87 CCM_TARGET_ROOT87_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT87_SET CCM_TARGET_ROOT87_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT87_CLR CCM_TARGET_ROOT87_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT87_TOG CCM_TARGET_ROOT87_TOG_REG(CCM_BASE_PTR) -#define CCM_POST87 CCM_POST87_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT87_SET CCM_POST_ROOT87_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT87_CLR CCM_POST_ROOT87_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT87_TOG CCM_POST_ROOT87_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE87 CCM_PRE87_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT87_SET CCM_PRE_ROOT87_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT87_CLR CCM_PRE_ROOT87_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT87_TOG CCM_PRE_ROOT87_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL87 CCM_ACCESS_CTRL87_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT87_SET CCM_ACCESS_CTRL87_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT87_CLR CCM_ACCESS_CTRL87_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT87_TOG CCM_ACCESS_CTRL87_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT88 CCM_TARGET_ROOT88_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT88_SET CCM_TARGET_ROOT88_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT88_CLR CCM_TARGET_ROOT88_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT88_TOG CCM_TARGET_ROOT88_TOG_REG(CCM_BASE_PTR) -#define CCM_POST88 CCM_POST88_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT88_SET CCM_POST_ROOT88_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT88_CLR CCM_POST_ROOT88_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT88_TOG CCM_POST_ROOT88_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE88 CCM_PRE88_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT88_SET CCM_PRE_ROOT88_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT88_CLR CCM_PRE_ROOT88_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT88_TOG CCM_PRE_ROOT88_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL88 CCM_ACCESS_CTRL88_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT88_SET CCM_ACCESS_CTRL88_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT88_CLR CCM_ACCESS_CTRL88_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT88_TOG CCM_ACCESS_CTRL88_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT89 CCM_TARGET_ROOT89_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT89_SET CCM_TARGET_ROOT89_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT89_CLR CCM_TARGET_ROOT89_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT89_TOG CCM_TARGET_ROOT89_TOG_REG(CCM_BASE_PTR) -#define CCM_POST89 CCM_POST89_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT89_SET CCM_POST_ROOT89_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT89_CLR CCM_POST_ROOT89_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT89_TOG CCM_POST_ROOT89_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE89 CCM_PRE89_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT89_SET CCM_PRE_ROOT89_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT89_CLR CCM_PRE_ROOT89_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT89_TOG CCM_PRE_ROOT89_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL89 CCM_ACCESS_CTRL89_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT89_SET CCM_ACCESS_CTRL89_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT89_CLR CCM_ACCESS_CTRL89_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT89_TOG CCM_ACCESS_CTRL89_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT90 CCM_TARGET_ROOT90_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT90_SET CCM_TARGET_ROOT90_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT90_CLR CCM_TARGET_ROOT90_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT90_TOG CCM_TARGET_ROOT90_TOG_REG(CCM_BASE_PTR) -#define CCM_POST90 CCM_POST90_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT90_SET CCM_POST_ROOT90_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT90_CLR CCM_POST_ROOT90_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT90_TOG CCM_POST_ROOT90_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE90 CCM_PRE90_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT90_SET CCM_PRE_ROOT90_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT90_CLR CCM_PRE_ROOT90_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT90_TOG CCM_PRE_ROOT90_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL90 CCM_ACCESS_CTRL90_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT90_SET CCM_ACCESS_CTRL90_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT90_CLR CCM_ACCESS_CTRL90_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT90_TOG CCM_ACCESS_CTRL90_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT91 CCM_TARGET_ROOT91_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT91_SET CCM_TARGET_ROOT91_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT91_CLR CCM_TARGET_ROOT91_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT91_TOG CCM_TARGET_ROOT91_TOG_REG(CCM_BASE_PTR) -#define CCM_POST91 CCM_POST91_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT91_SET CCM_POST_ROOT91_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT91_CLR CCM_POST_ROOT91_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT91_TOG CCM_POST_ROOT91_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE91 CCM_PRE91_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT91_SET CCM_PRE_ROOT91_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT91_CLR CCM_PRE_ROOT91_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT91_TOG CCM_PRE_ROOT91_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL91 CCM_ACCESS_CTRL91_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT91_SET CCM_ACCESS_CTRL91_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT91_CLR CCM_ACCESS_CTRL91_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT91_TOG CCM_ACCESS_CTRL91_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT92 CCM_TARGET_ROOT92_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT92_SET CCM_TARGET_ROOT92_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT92_CLR CCM_TARGET_ROOT92_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT92_TOG CCM_TARGET_ROOT92_TOG_REG(CCM_BASE_PTR) -#define CCM_POST92 CCM_POST92_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT92_SET CCM_POST_ROOT92_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT92_CLR CCM_POST_ROOT92_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT92_TOG CCM_POST_ROOT92_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE92 CCM_PRE92_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT92_SET CCM_PRE_ROOT92_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT92_CLR CCM_PRE_ROOT92_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT92_TOG CCM_PRE_ROOT92_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL92 CCM_ACCESS_CTRL92_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT92_SET CCM_ACCESS_CTRL92_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT92_CLR CCM_ACCESS_CTRL92_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT92_TOG CCM_ACCESS_CTRL92_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT93 CCM_TARGET_ROOT93_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT93_SET CCM_TARGET_ROOT93_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT93_CLR CCM_TARGET_ROOT93_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT93_TOG CCM_TARGET_ROOT93_TOG_REG(CCM_BASE_PTR) -#define CCM_POST93 CCM_POST93_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT93_SET CCM_POST_ROOT93_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT93_CLR CCM_POST_ROOT93_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT93_TOG CCM_POST_ROOT93_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE93 CCM_PRE93_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT93_SET CCM_PRE_ROOT93_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT93_CLR CCM_PRE_ROOT93_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT93_TOG CCM_PRE_ROOT93_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL93 CCM_ACCESS_CTRL93_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT93_SET CCM_ACCESS_CTRL93_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT93_CLR CCM_ACCESS_CTRL93_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT93_TOG CCM_ACCESS_CTRL93_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT94 CCM_TARGET_ROOT94_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT94_SET CCM_TARGET_ROOT94_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT94_CLR CCM_TARGET_ROOT94_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT94_TOG CCM_TARGET_ROOT94_TOG_REG(CCM_BASE_PTR) -#define CCM_POST94 CCM_POST94_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT94_SET CCM_POST_ROOT94_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT94_CLR CCM_POST_ROOT94_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT94_TOG CCM_POST_ROOT94_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE94 CCM_PRE94_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT94_SET CCM_PRE_ROOT94_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT94_CLR CCM_PRE_ROOT94_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT94_TOG CCM_PRE_ROOT94_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL94 CCM_ACCESS_CTRL94_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT94_SET CCM_ACCESS_CTRL94_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT94_CLR CCM_ACCESS_CTRL94_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT94_TOG CCM_ACCESS_CTRL94_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT95 CCM_TARGET_ROOT95_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT95_SET CCM_TARGET_ROOT95_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT95_CLR CCM_TARGET_ROOT95_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT95_TOG CCM_TARGET_ROOT95_TOG_REG(CCM_BASE_PTR) -#define CCM_POST95 CCM_POST95_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT95_SET CCM_POST_ROOT95_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT95_CLR CCM_POST_ROOT95_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT95_TOG CCM_POST_ROOT95_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE95 CCM_PRE95_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT95_SET CCM_PRE_ROOT95_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT95_CLR CCM_PRE_ROOT95_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT95_TOG CCM_PRE_ROOT95_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL95 CCM_ACCESS_CTRL95_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT95_SET CCM_ACCESS_CTRL95_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT95_CLR CCM_ACCESS_CTRL95_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT95_TOG CCM_ACCESS_CTRL95_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT96 CCM_TARGET_ROOT96_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT96_SET CCM_TARGET_ROOT96_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT96_CLR CCM_TARGET_ROOT96_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT96_TOG CCM_TARGET_ROOT96_TOG_REG(CCM_BASE_PTR) -#define CCM_POST96 CCM_POST96_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT96_SET CCM_POST_ROOT96_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT96_CLR CCM_POST_ROOT96_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT96_TOG CCM_POST_ROOT96_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE96 CCM_PRE96_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT96_SET CCM_PRE_ROOT96_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT96_CLR CCM_PRE_ROOT96_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT96_TOG CCM_PRE_ROOT96_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL96 CCM_ACCESS_CTRL96_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT96_SET CCM_ACCESS_CTRL96_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT96_CLR CCM_ACCESS_CTRL96_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT96_TOG CCM_ACCESS_CTRL96_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT97 CCM_TARGET_ROOT97_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT97_SET CCM_TARGET_ROOT97_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT97_CLR CCM_TARGET_ROOT97_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT97_TOG CCM_TARGET_ROOT97_TOG_REG(CCM_BASE_PTR) -#define CCM_POST97 CCM_POST97_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT97_SET CCM_POST_ROOT97_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT97_CLR CCM_POST_ROOT97_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT97_TOG CCM_POST_ROOT97_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE97 CCM_PRE97_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT97_SET CCM_PRE_ROOT97_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT97_CLR CCM_PRE_ROOT97_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT97_TOG CCM_PRE_ROOT97_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL97 CCM_ACCESS_CTRL97_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT97_SET CCM_ACCESS_CTRL97_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT97_CLR CCM_ACCESS_CTRL97_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT97_TOG CCM_ACCESS_CTRL97_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT98 CCM_TARGET_ROOT98_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT98_SET CCM_TARGET_ROOT98_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT98_CLR CCM_TARGET_ROOT98_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT98_TOG CCM_TARGET_ROOT98_TOG_REG(CCM_BASE_PTR) -#define CCM_POST98 CCM_POST98_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT98_SET CCM_POST_ROOT98_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT98_CLR CCM_POST_ROOT98_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT98_TOG CCM_POST_ROOT98_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE98 CCM_PRE98_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT98_SET CCM_PRE_ROOT98_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT98_CLR CCM_PRE_ROOT98_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT98_TOG CCM_PRE_ROOT98_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL98 CCM_ACCESS_CTRL98_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT98_SET CCM_ACCESS_CTRL98_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT98_CLR CCM_ACCESS_CTRL98_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT98_TOG CCM_ACCESS_CTRL98_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT99 CCM_TARGET_ROOT99_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT99_SET CCM_TARGET_ROOT99_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT99_CLR CCM_TARGET_ROOT99_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT99_TOG CCM_TARGET_ROOT99_TOG_REG(CCM_BASE_PTR) -#define CCM_POST99 CCM_POST99_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT99_SET CCM_POST_ROOT99_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT99_CLR CCM_POST_ROOT99_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT99_TOG CCM_POST_ROOT99_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE99 CCM_PRE99_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT99_SET CCM_PRE_ROOT99_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT99_CLR CCM_PRE_ROOT99_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT99_TOG CCM_PRE_ROOT99_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL99 CCM_ACCESS_CTRL99_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT99_SET CCM_ACCESS_CTRL99_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT99_CLR CCM_ACCESS_CTRL99_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT99_TOG CCM_ACCESS_CTRL99_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT100 CCM_TARGET_ROOT100_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT100_SET CCM_TARGET_ROOT100_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT100_CLR CCM_TARGET_ROOT100_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT100_TOG CCM_TARGET_ROOT100_TOG_REG(CCM_BASE_PTR) -#define CCM_POST100 CCM_POST100_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT100_SET CCM_POST_ROOT100_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT100_CLR CCM_POST_ROOT100_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT100_TOG CCM_POST_ROOT100_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE100 CCM_PRE100_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT100_SET CCM_PRE_ROOT100_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT100_CLR CCM_PRE_ROOT100_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT100_TOG CCM_PRE_ROOT100_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL100 CCM_ACCESS_CTRL100_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT100_SET CCM_ACCESS_CTRL100_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT100_CLR CCM_ACCESS_CTRL100_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT100_TOG CCM_ACCESS_CTRL100_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT101 CCM_TARGET_ROOT101_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT101_SET CCM_TARGET_ROOT101_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT101_CLR CCM_TARGET_ROOT101_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT101_TOG CCM_TARGET_ROOT101_TOG_REG(CCM_BASE_PTR) -#define CCM_POST101 CCM_POST101_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT101_SET CCM_POST_ROOT101_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT101_CLR CCM_POST_ROOT101_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT101_TOG CCM_POST_ROOT101_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE101 CCM_PRE101_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT101_SET CCM_PRE_ROOT101_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT101_CLR CCM_PRE_ROOT101_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT101_TOG CCM_PRE_ROOT101_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL101 CCM_ACCESS_CTRL101_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT101_SET CCM_ACCESS_CTRL101_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT101_CLR CCM_ACCESS_CTRL101_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT101_TOG CCM_ACCESS_CTRL101_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT102 CCM_TARGET_ROOT102_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT102_SET CCM_TARGET_ROOT102_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT102_CLR CCM_TARGET_ROOT102_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT102_TOG CCM_TARGET_ROOT102_TOG_REG(CCM_BASE_PTR) -#define CCM_POST102 CCM_POST102_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT102_SET CCM_POST_ROOT102_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT102_CLR CCM_POST_ROOT102_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT102_TOG CCM_POST_ROOT102_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE102 CCM_PRE102_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT102_SET CCM_PRE_ROOT102_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT102_CLR CCM_PRE_ROOT102_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT102_TOG CCM_PRE_ROOT102_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL102 CCM_ACCESS_CTRL102_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT102_SET CCM_ACCESS_CTRL102_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT102_CLR CCM_ACCESS_CTRL102_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT102_TOG CCM_ACCESS_CTRL102_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT103 CCM_TARGET_ROOT103_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT103_SET CCM_TARGET_ROOT103_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT103_CLR CCM_TARGET_ROOT103_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT103_TOG CCM_TARGET_ROOT103_TOG_REG(CCM_BASE_PTR) -#define CCM_POST103 CCM_POST103_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT103_SET CCM_POST_ROOT103_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT103_CLR CCM_POST_ROOT103_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT103_TOG CCM_POST_ROOT103_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE103 CCM_PRE103_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT103_SET CCM_PRE_ROOT103_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT103_CLR CCM_PRE_ROOT103_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT103_TOG CCM_PRE_ROOT103_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL103 CCM_ACCESS_CTRL103_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT103_SET CCM_ACCESS_CTRL103_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT103_CLR CCM_ACCESS_CTRL103_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT103_TOG CCM_ACCESS_CTRL103_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT104 CCM_TARGET_ROOT104_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT104_SET CCM_TARGET_ROOT104_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT104_CLR CCM_TARGET_ROOT104_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT104_TOG CCM_TARGET_ROOT104_TOG_REG(CCM_BASE_PTR) -#define CCM_POST104 CCM_POST104_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT104_SET CCM_POST_ROOT104_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT104_CLR CCM_POST_ROOT104_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT104_TOG CCM_POST_ROOT104_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE104 CCM_PRE104_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT104_SET CCM_PRE_ROOT104_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT104_CLR CCM_PRE_ROOT104_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT104_TOG CCM_PRE_ROOT104_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL104 CCM_ACCESS_CTRL104_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT104_SET CCM_ACCESS_CTRL104_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT104_CLR CCM_ACCESS_CTRL104_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT104_TOG CCM_ACCESS_CTRL104_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT105 CCM_TARGET_ROOT105_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT105_SET CCM_TARGET_ROOT105_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT105_CLR CCM_TARGET_ROOT105_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT105_TOG CCM_TARGET_ROOT105_TOG_REG(CCM_BASE_PTR) -#define CCM_POST105 CCM_POST105_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT105_SET CCM_POST_ROOT105_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT105_CLR CCM_POST_ROOT105_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT105_TOG CCM_POST_ROOT105_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE105 CCM_PRE105_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT105_SET CCM_PRE_ROOT105_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT105_CLR CCM_PRE_ROOT105_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT105_TOG CCM_PRE_ROOT105_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL105 CCM_ACCESS_CTRL105_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT105_SET CCM_ACCESS_CTRL105_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT105_CLR CCM_ACCESS_CTRL105_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT105_TOG CCM_ACCESS_CTRL105_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT106 CCM_TARGET_ROOT106_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT106_SET CCM_TARGET_ROOT106_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT106_CLR CCM_TARGET_ROOT106_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT106_TOG CCM_TARGET_ROOT106_TOG_REG(CCM_BASE_PTR) -#define CCM_POST106 CCM_POST106_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT106_SET CCM_POST_ROOT106_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT106_CLR CCM_POST_ROOT106_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT106_TOG CCM_POST_ROOT106_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE106 CCM_PRE106_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT106_SET CCM_PRE_ROOT106_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT106_CLR CCM_PRE_ROOT106_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT106_TOG CCM_PRE_ROOT106_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL106 CCM_ACCESS_CTRL106_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT106_SET CCM_ACCESS_CTRL106_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT106_CLR CCM_ACCESS_CTRL106_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT106_TOG CCM_ACCESS_CTRL106_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT107 CCM_TARGET_ROOT107_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT107_SET CCM_TARGET_ROOT107_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT107_CLR CCM_TARGET_ROOT107_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT107_TOG CCM_TARGET_ROOT107_TOG_REG(CCM_BASE_PTR) -#define CCM_POST107 CCM_POST107_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT107_SET CCM_POST_ROOT107_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT107_CLR CCM_POST_ROOT107_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT107_TOG CCM_POST_ROOT107_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE107 CCM_PRE107_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT107_SET CCM_PRE_ROOT107_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT107_CLR CCM_PRE_ROOT107_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT107_TOG CCM_PRE_ROOT107_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL107 CCM_ACCESS_CTRL107_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT107_SET CCM_ACCESS_CTRL107_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT107_CLR CCM_ACCESS_CTRL107_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT107_TOG CCM_ACCESS_CTRL107_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT108 CCM_TARGET_ROOT108_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT108_SET CCM_TARGET_ROOT108_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT108_CLR CCM_TARGET_ROOT108_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT108_TOG CCM_TARGET_ROOT108_TOG_REG(CCM_BASE_PTR) -#define CCM_POST108 CCM_POST108_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT108_SET CCM_POST_ROOT108_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT108_CLR CCM_POST_ROOT108_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT108_TOG CCM_POST_ROOT108_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE108 CCM_PRE108_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT108_SET CCM_PRE_ROOT108_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT108_CLR CCM_PRE_ROOT108_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT108_TOG CCM_PRE_ROOT108_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL108 CCM_ACCESS_CTRL108_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT108_SET CCM_ACCESS_CTRL108_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT108_CLR CCM_ACCESS_CTRL108_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT108_TOG CCM_ACCESS_CTRL108_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT109 CCM_TARGET_ROOT109_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT109_SET CCM_TARGET_ROOT109_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT109_CLR CCM_TARGET_ROOT109_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT109_TOG CCM_TARGET_ROOT109_TOG_REG(CCM_BASE_PTR) -#define CCM_POST109 CCM_POST109_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT109_SET CCM_POST_ROOT109_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT109_CLR CCM_POST_ROOT109_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT109_TOG CCM_POST_ROOT109_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE109 CCM_PRE109_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT109_SET CCM_PRE_ROOT109_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT109_CLR CCM_PRE_ROOT109_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT109_TOG CCM_PRE_ROOT109_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL109 CCM_ACCESS_CTRL109_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT109_SET CCM_ACCESS_CTRL109_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT109_CLR CCM_ACCESS_CTRL109_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT109_TOG CCM_ACCESS_CTRL109_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT110 CCM_TARGET_ROOT110_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT110_SET CCM_TARGET_ROOT110_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT110_CLR CCM_TARGET_ROOT110_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT110_TOG CCM_TARGET_ROOT110_TOG_REG(CCM_BASE_PTR) -#define CCM_POST110 CCM_POST110_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT110_SET CCM_POST_ROOT110_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT110_CLR CCM_POST_ROOT110_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT110_TOG CCM_POST_ROOT110_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE110 CCM_PRE110_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT110_SET CCM_PRE_ROOT110_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT110_CLR CCM_PRE_ROOT110_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT110_TOG CCM_PRE_ROOT110_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL110 CCM_ACCESS_CTRL110_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT110_SET CCM_ACCESS_CTRL110_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT110_CLR CCM_ACCESS_CTRL110_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT110_TOG CCM_ACCESS_CTRL110_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT111 CCM_TARGET_ROOT111_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT111_SET CCM_TARGET_ROOT111_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT111_CLR CCM_TARGET_ROOT111_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT111_TOG CCM_TARGET_ROOT111_TOG_REG(CCM_BASE_PTR) -#define CCM_POST111 CCM_POST111_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT111_SET CCM_POST_ROOT111_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT111_CLR CCM_POST_ROOT111_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT111_TOG CCM_POST_ROOT111_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE111 CCM_PRE111_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT111_SET CCM_PRE_ROOT111_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT111_CLR CCM_PRE_ROOT111_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT111_TOG CCM_PRE_ROOT111_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL111 CCM_ACCESS_CTRL111_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT111_SET CCM_ACCESS_CTRL111_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT111_CLR CCM_ACCESS_CTRL111_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT111_TOG CCM_ACCESS_CTRL111_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT112 CCM_TARGET_ROOT112_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT112_SET CCM_TARGET_ROOT112_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT112_CLR CCM_TARGET_ROOT112_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT112_TOG CCM_TARGET_ROOT112_TOG_REG(CCM_BASE_PTR) -#define CCM_POST112 CCM_POST112_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT112_SET CCM_POST_ROOT112_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT112_CLR CCM_POST_ROOT112_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT112_TOG CCM_POST_ROOT112_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE112 CCM_PRE112_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT112_SET CCM_PRE_ROOT112_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT112_CLR CCM_PRE_ROOT112_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT112_TOG CCM_PRE_ROOT112_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL112 CCM_ACCESS_CTRL112_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT112_SET CCM_ACCESS_CTRL112_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT112_CLR CCM_ACCESS_CTRL112_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT112_TOG CCM_ACCESS_CTRL112_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT113 CCM_TARGET_ROOT113_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT113_SET CCM_TARGET_ROOT113_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT113_CLR CCM_TARGET_ROOT113_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT113_TOG CCM_TARGET_ROOT113_TOG_REG(CCM_BASE_PTR) -#define CCM_POST113 CCM_POST113_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT113_SET CCM_POST_ROOT113_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT113_CLR CCM_POST_ROOT113_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT113_TOG CCM_POST_ROOT113_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE113 CCM_PRE113_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT113_SET CCM_PRE_ROOT113_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT113_CLR CCM_PRE_ROOT113_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT113_TOG CCM_PRE_ROOT113_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL113 CCM_ACCESS_CTRL113_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT113_SET CCM_ACCESS_CTRL113_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT113_CLR CCM_ACCESS_CTRL113_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT113_TOG CCM_ACCESS_CTRL113_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT114 CCM_TARGET_ROOT114_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT114_SET CCM_TARGET_ROOT114_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT114_CLR CCM_TARGET_ROOT114_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT114_TOG CCM_TARGET_ROOT114_TOG_REG(CCM_BASE_PTR) -#define CCM_POST114 CCM_POST114_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT114_SET CCM_POST_ROOT114_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT114_CLR CCM_POST_ROOT114_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT114_TOG CCM_POST_ROOT114_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE114 CCM_PRE114_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT114_SET CCM_PRE_ROOT114_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT114_CLR CCM_PRE_ROOT114_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT114_TOG CCM_PRE_ROOT114_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL114 CCM_ACCESS_CTRL114_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT114_SET CCM_ACCESS_CTRL114_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT114_CLR CCM_ACCESS_CTRL114_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT114_TOG CCM_ACCESS_CTRL114_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT115 CCM_TARGET_ROOT115_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT115_SET CCM_TARGET_ROOT115_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT115_CLR CCM_TARGET_ROOT115_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT115_TOG CCM_TARGET_ROOT115_TOG_REG(CCM_BASE_PTR) -#define CCM_POST115 CCM_POST115_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT115_SET CCM_POST_ROOT115_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT115_CLR CCM_POST_ROOT115_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT115_TOG CCM_POST_ROOT115_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE115 CCM_PRE115_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT115_SET CCM_PRE_ROOT115_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT115_CLR CCM_PRE_ROOT115_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT115_TOG CCM_PRE_ROOT115_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL115 CCM_ACCESS_CTRL115_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT115_SET CCM_ACCESS_CTRL115_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT115_CLR CCM_ACCESS_CTRL115_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT115_TOG CCM_ACCESS_CTRL115_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT116 CCM_TARGET_ROOT116_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT116_SET CCM_TARGET_ROOT116_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT116_CLR CCM_TARGET_ROOT116_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT116_TOG CCM_TARGET_ROOT116_TOG_REG(CCM_BASE_PTR) -#define CCM_POST116 CCM_POST116_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT116_SET CCM_POST_ROOT116_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT116_CLR CCM_POST_ROOT116_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT116_TOG CCM_POST_ROOT116_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE116 CCM_PRE116_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT116_SET CCM_PRE_ROOT116_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT116_CLR CCM_PRE_ROOT116_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT116_TOG CCM_PRE_ROOT116_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL116 CCM_ACCESS_CTRL116_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT116_SET CCM_ACCESS_CTRL116_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT116_CLR CCM_ACCESS_CTRL116_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT116_TOG CCM_ACCESS_CTRL116_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT117 CCM_TARGET_ROOT117_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT117_SET CCM_TARGET_ROOT117_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT117_CLR CCM_TARGET_ROOT117_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT117_TOG CCM_TARGET_ROOT117_TOG_REG(CCM_BASE_PTR) -#define CCM_POST117 CCM_POST117_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT117_SET CCM_POST_ROOT117_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT117_CLR CCM_POST_ROOT117_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT117_TOG CCM_POST_ROOT117_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE117 CCM_PRE117_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT117_SET CCM_PRE_ROOT117_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT117_CLR CCM_PRE_ROOT117_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT117_TOG CCM_PRE_ROOT117_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL117 CCM_ACCESS_CTRL117_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT117_SET CCM_ACCESS_CTRL117_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT117_CLR CCM_ACCESS_CTRL117_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT117_TOG CCM_ACCESS_CTRL117_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT118 CCM_TARGET_ROOT118_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT118_SET CCM_TARGET_ROOT118_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT118_CLR CCM_TARGET_ROOT118_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT118_TOG CCM_TARGET_ROOT118_TOG_REG(CCM_BASE_PTR) -#define CCM_POST118 CCM_POST118_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT118_SET CCM_POST_ROOT118_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT118_CLR CCM_POST_ROOT118_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT118_TOG CCM_POST_ROOT118_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE118 CCM_PRE118_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT118_SET CCM_PRE_ROOT118_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT118_CLR CCM_PRE_ROOT118_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT118_TOG CCM_PRE_ROOT118_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL118 CCM_ACCESS_CTRL118_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT118_SET CCM_ACCESS_CTRL118_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT118_CLR CCM_ACCESS_CTRL118_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT118_TOG CCM_ACCESS_CTRL118_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT119 CCM_TARGET_ROOT119_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT119_SET CCM_TARGET_ROOT119_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT119_CLR CCM_TARGET_ROOT119_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT119_TOG CCM_TARGET_ROOT119_TOG_REG(CCM_BASE_PTR) -#define CCM_POST119 CCM_POST119_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT119_SET CCM_POST_ROOT119_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT119_CLR CCM_POST_ROOT119_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT119_TOG CCM_POST_ROOT119_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE119 CCM_PRE119_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT119_SET CCM_PRE_ROOT119_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT119_CLR CCM_PRE_ROOT119_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT119_TOG CCM_PRE_ROOT119_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL119 CCM_ACCESS_CTRL119_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT119_SET CCM_ACCESS_CTRL119_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT119_CLR CCM_ACCESS_CTRL119_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT119_TOG CCM_ACCESS_CTRL119_ROOT_TOG_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT120 CCM_TARGET_ROOT120_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT120_SET CCM_TARGET_ROOT120_SET_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT120_CLR CCM_TARGET_ROOT120_CLR_REG(CCM_BASE_PTR) -#define CCM_TARGET_ROOT120_TOG CCM_TARGET_ROOT120_TOG_REG(CCM_BASE_PTR) -#define CCM_POST120 CCM_POST120_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT120_SET CCM_POST_ROOT120_SET_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT120_CLR CCM_POST_ROOT120_CLR_REG(CCM_BASE_PTR) -#define CCM_POST_ROOT120_TOG CCM_POST_ROOT120_TOG_REG(CCM_BASE_PTR) -#define CCM_PRE120 CCM_PRE120_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT120_SET CCM_PRE_ROOT120_SET_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT120_CLR CCM_PRE_ROOT120_CLR_REG(CCM_BASE_PTR) -#define CCM_PRE_ROOT120_TOG CCM_PRE_ROOT120_TOG_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL120 CCM_ACCESS_CTRL120_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT120_SET CCM_ACCESS_CTRL120_ROOT_SET_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT120_CLR CCM_ACCESS_CTRL120_ROOT_CLR_REG(CCM_BASE_PTR) -#define CCM_ACCESS_CTRL_ROOT120_TOG CCM_ACCESS_CTRL120_ROOT_TOG_REG(CCM_BASE_PTR) - +#define CCM_PLL_CTRL0 CCM_PLL_CTRL_REG(CCM_BASE_PTR,0) +#define CCM_PLL_CTRL0_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,0) +#define CCM_PLL_CTRL0_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,0) +#define CCM_PLL_CTRL0_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,0) +#define CCM_PLL_CTRL1 CCM_PLL_CTRL_REG(CCM_BASE_PTR,1) +#define CCM_PLL_CTRL1_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,1) +#define CCM_PLL_CTRL1_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,1) +#define CCM_PLL_CTRL1_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,1) +#define CCM_PLL_CTRL2 CCM_PLL_CTRL_REG(CCM_BASE_PTR,2) +#define CCM_PLL_CTRL2_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,2) +#define CCM_PLL_CTRL2_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,2) +#define CCM_PLL_CTRL2_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,2) +#define CCM_PLL_CTRL3 CCM_PLL_CTRL_REG(CCM_BASE_PTR,3) +#define CCM_PLL_CTRL3_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,3) +#define CCM_PLL_CTRL3_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,3) +#define CCM_PLL_CTRL3_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,3) +#define CCM_PLL_CTRL4 CCM_PLL_CTRL_REG(CCM_BASE_PTR,4) +#define CCM_PLL_CTRL4_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,4) +#define CCM_PLL_CTRL4_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,4) +#define CCM_PLL_CTRL4_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,4) +#define CCM_PLL_CTRL5 CCM_PLL_CTRL_REG(CCM_BASE_PTR,5) +#define CCM_PLL_CTRL5_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,5) +#define CCM_PLL_CTRL5_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,5) +#define CCM_PLL_CTRL5_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,5) +#define CCM_PLL_CTRL6 CCM_PLL_CTRL_REG(CCM_BASE_PTR,6) +#define CCM_PLL_CTRL6_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,6) +#define CCM_PLL_CTRL6_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,6) +#define CCM_PLL_CTRL6_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,6) +#define CCM_PLL_CTRL7 CCM_PLL_CTRL_REG(CCM_BASE_PTR,7) +#define CCM_PLL_CTRL7_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,7) +#define CCM_PLL_CTRL7_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,7) +#define CCM_PLL_CTRL7_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,7) +#define CCM_PLL_CTRL8 CCM_PLL_CTRL_REG(CCM_BASE_PTR,8) +#define CCM_PLL_CTRL8_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,8) +#define CCM_PLL_CTRL8_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,8) +#define CCM_PLL_CTRL8_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,8) +#define CCM_PLL_CTRL9 CCM_PLL_CTRL_REG(CCM_BASE_PTR,9) +#define CCM_PLL_CTRL9_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,9) +#define CCM_PLL_CTRL9_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,9) +#define CCM_PLL_CTRL9_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,9) +#define CCM_PLL_CTRL10 CCM_PLL_CTRL_REG(CCM_BASE_PTR,10) +#define CCM_PLL_CTRL10_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,10) +#define CCM_PLL_CTRL10_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,10) +#define CCM_PLL_CTRL10_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,10) +#define CCM_PLL_CTRL11 CCM_PLL_CTRL_REG(CCM_BASE_PTR,11) +#define CCM_PLL_CTRL11_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,11) +#define CCM_PLL_CTRL11_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,11) +#define CCM_PLL_CTRL11_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,11) +#define CCM_PLL_CTRL12 CCM_PLL_CTRL_REG(CCM_BASE_PTR,12) +#define CCM_PLL_CTRL12_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,12) +#define CCM_PLL_CTRL12_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,12) +#define CCM_PLL_CTRL12_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,12) +#define CCM_PLL_CTRL13 CCM_PLL_CTRL_REG(CCM_BASE_PTR,13) +#define CCM_PLL_CTRL13_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,13) +#define CCM_PLL_CTRL13_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,13) +#define CCM_PLL_CTRL13_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,13) +#define CCM_PLL_CTRL14 CCM_PLL_CTRL_REG(CCM_BASE_PTR,14) +#define CCM_PLL_CTRL14_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,14) +#define CCM_PLL_CTRL14_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,14) +#define CCM_PLL_CTRL14_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,14) +#define CCM_PLL_CTRL15 CCM_PLL_CTRL_REG(CCM_BASE_PTR,15) +#define CCM_PLL_CTRL15_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,15) +#define CCM_PLL_CTRL15_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,15) +#define CCM_PLL_CTRL15_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,15) +#define CCM_PLL_CTRL16 CCM_PLL_CTRL_REG(CCM_BASE_PTR,16) +#define CCM_PLL_CTRL16_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,16) +#define CCM_PLL_CTRL16_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,16) +#define CCM_PLL_CTRL16_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,16) +#define CCM_PLL_CTRL17 CCM_PLL_CTRL_REG(CCM_BASE_PTR,17) +#define CCM_PLL_CTRL17_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,17) +#define CCM_PLL_CTRL17_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,17) +#define CCM_PLL_CTRL17_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,17) +#define CCM_PLL_CTRL18 CCM_PLL_CTRL_REG(CCM_BASE_PTR,18) +#define CCM_PLL_CTRL18_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,18) +#define CCM_PLL_CTRL18_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,18) +#define CCM_PLL_CTRL18_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,18) +#define CCM_PLL_CTRL19 CCM_PLL_CTRL_REG(CCM_BASE_PTR,19) +#define CCM_PLL_CTRL19_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,19) +#define CCM_PLL_CTRL19_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,19) +#define CCM_PLL_CTRL19_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,19) +#define CCM_PLL_CTRL20 CCM_PLL_CTRL_REG(CCM_BASE_PTR,20) +#define CCM_PLL_CTRL20_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,20) +#define CCM_PLL_CTRL20_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,20) +#define CCM_PLL_CTRL20_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,20) +#define CCM_PLL_CTRL21 CCM_PLL_CTRL_REG(CCM_BASE_PTR,21) +#define CCM_PLL_CTRL21_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,21) +#define CCM_PLL_CTRL21_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,21) +#define CCM_PLL_CTRL21_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,21) +#define CCM_PLL_CTRL22 CCM_PLL_CTRL_REG(CCM_BASE_PTR,22) +#define CCM_PLL_CTRL22_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,22) +#define CCM_PLL_CTRL22_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,22) +#define CCM_PLL_CTRL22_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,22) +#define CCM_PLL_CTRL23 CCM_PLL_CTRL_REG(CCM_BASE_PTR,23) +#define CCM_PLL_CTRL23_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,23) +#define CCM_PLL_CTRL23_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,23) +#define CCM_PLL_CTRL23_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,23) +#define CCM_PLL_CTRL24 CCM_PLL_CTRL_REG(CCM_BASE_PTR,24) +#define CCM_PLL_CTRL24_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,24) +#define CCM_PLL_CTRL24_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,24) +#define CCM_PLL_CTRL24_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,24) +#define CCM_PLL_CTRL25 CCM_PLL_CTRL_REG(CCM_BASE_PTR,25) +#define CCM_PLL_CTRL25_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,25) +#define CCM_PLL_CTRL25_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,25) +#define CCM_PLL_CTRL25_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,25) +#define CCM_PLL_CTRL26 CCM_PLL_CTRL_REG(CCM_BASE_PTR,26) +#define CCM_PLL_CTRL26_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,26) +#define CCM_PLL_CTRL26_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,26) +#define CCM_PLL_CTRL26_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,26) +#define CCM_PLL_CTRL27 CCM_PLL_CTRL_REG(CCM_BASE_PTR,27) +#define CCM_PLL_CTRL27_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,27) +#define CCM_PLL_CTRL27_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,27) +#define CCM_PLL_CTRL27_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,27) +#define CCM_PLL_CTRL28 CCM_PLL_CTRL_REG(CCM_BASE_PTR,28) +#define CCM_PLL_CTRL28_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,28) +#define CCM_PLL_CTRL28_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,28) +#define CCM_PLL_CTRL28_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,28) +#define CCM_PLL_CTRL29 CCM_PLL_CTRL_REG(CCM_BASE_PTR,29) +#define CCM_PLL_CTRL29_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,29) +#define CCM_PLL_CTRL29_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,29) +#define CCM_PLL_CTRL29_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,29) +#define CCM_PLL_CTRL30 CCM_PLL_CTRL_REG(CCM_BASE_PTR,30) +#define CCM_PLL_CTRL30_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,30) +#define CCM_PLL_CTRL30_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,30) +#define CCM_PLL_CTRL30_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,30) +#define CCM_PLL_CTRL31 CCM_PLL_CTRL_REG(CCM_BASE_PTR,31) +#define CCM_PLL_CTRL31_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,31) +#define CCM_PLL_CTRL31_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,31) +#define CCM_PLL_CTRL31_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,31) +#define CCM_PLL_CTRL32 CCM_PLL_CTRL_REG(CCM_BASE_PTR,32) +#define CCM_PLL_CTRL32_SET CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,32) +#define CCM_PLL_CTRL32_CLR CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,32) +#define CCM_PLL_CTRL32_TOG CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,32) +#define CCM_CCGR0 CCM_CCGR_REG(CCM_BASE_PTR,0) +#define CCM_CCGR0_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,0) +#define CCM_CCGR0_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,0) +#define CCM_CCGR0_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,0) +#define CCM_CCGR1 CCM_CCGR_REG(CCM_BASE_PTR,1) +#define CCM_CCGR1_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,1) +#define CCM_CCGR1_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,1) +#define CCM_CCGR1_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,1) +#define CCM_CCGR2 CCM_CCGR_REG(CCM_BASE_PTR,2) +#define CCM_CCGR2_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,2) +#define CCM_CCGR2_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,2) +#define CCM_CCGR2_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,2) +#define CCM_CCGR3 CCM_CCGR_REG(CCM_BASE_PTR,3) +#define CCM_CCGR3_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,3) +#define CCM_CCGR3_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,3) +#define CCM_CCGR3_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,3) +#define CCM_CCGR4 CCM_CCGR_REG(CCM_BASE_PTR,4) +#define CCM_CCGR4_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,4) +#define CCM_CCGR4_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,4) +#define CCM_CCGR4_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,4) +#define CCM_CCGR5 CCM_CCGR_REG(CCM_BASE_PTR,5) +#define CCM_CCGR5_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,5) +#define CCM_CCGR5_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,5) +#define CCM_CCGR5_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,5) +#define CCM_CCGR6 CCM_CCGR_REG(CCM_BASE_PTR,6) +#define CCM_CCGR6_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,6) +#define CCM_CCGR6_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,6) +#define CCM_CCGR6_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,6) +#define CCM_CCGR7 CCM_CCGR_REG(CCM_BASE_PTR,7) +#define CCM_CCGR7_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,7) +#define CCM_CCGR7_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,7) +#define CCM_CCGR7_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,7) +#define CCM_CCGR8 CCM_CCGR_REG(CCM_BASE_PTR,8) +#define CCM_CCGR8_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,8) +#define CCM_CCGR8_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,8) +#define CCM_CCGR8_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,8) +#define CCM_CCGR9 CCM_CCGR_REG(CCM_BASE_PTR,9) +#define CCM_CCGR9_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,9) +#define CCM_CCGR9_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,9) +#define CCM_CCGR9_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,9) +#define CCM_CCGR10 CCM_CCGR_REG(CCM_BASE_PTR,10) +#define CCM_CCGR10_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,10) +#define CCM_CCGR10_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,10) +#define CCM_CCGR10_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,10) +#define CCM_CCGR11 CCM_CCGR_REG(CCM_BASE_PTR,11) +#define CCM_CCGR11_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,11) +#define CCM_CCGR11_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,11) +#define CCM_CCGR11_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,11) +#define CCM_CCGR12 CCM_CCGR_REG(CCM_BASE_PTR,12) +#define CCM_CCGR12_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,12) +#define CCM_CCGR12_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,12) +#define CCM_CCGR12_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,12) +#define CCM_CCGR13 CCM_CCGR_REG(CCM_BASE_PTR,13) +#define CCM_CCGR13_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,13) +#define CCM_CCGR13_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,13) +#define CCM_CCGR13_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,13) +#define CCM_CCGR14 CCM_CCGR_REG(CCM_BASE_PTR,14) +#define CCM_CCGR14_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,14) +#define CCM_CCGR14_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,14) +#define CCM_CCGR14_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,14) +#define CCM_CCGR15 CCM_CCGR_REG(CCM_BASE_PTR,15) +#define CCM_CCGR15_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,15) +#define CCM_CCGR15_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,15) +#define CCM_CCGR15_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,15) +#define CCM_CCGR16 CCM_CCGR_REG(CCM_BASE_PTR,16) +#define CCM_CCGR16_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,16) +#define CCM_CCGR16_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,16) +#define CCM_CCGR16_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,16) +#define CCM_CCGR17 CCM_CCGR_REG(CCM_BASE_PTR,17) +#define CCM_CCGR17_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,17) +#define CCM_CCGR17_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,17) +#define CCM_CCGR17_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,17) +#define CCM_CCGR18 CCM_CCGR_REG(CCM_BASE_PTR,18) +#define CCM_CCGR18_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,18) +#define CCM_CCGR18_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,18) +#define CCM_CCGR18_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,18) +#define CCM_CCGR19 CCM_CCGR_REG(CCM_BASE_PTR,19) +#define CCM_CCGR19_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,19) +#define CCM_CCGR19_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,19) +#define CCM_CCGR19_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,19) +#define CCM_CCGR20 CCM_CCGR_REG(CCM_BASE_PTR,20) +#define CCM_CCGR20_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,20) +#define CCM_CCGR20_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,20) +#define CCM_CCGR20_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,20) +#define CCM_CCGR21 CCM_CCGR_REG(CCM_BASE_PTR,21) +#define CCM_CCGR21_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,21) +#define CCM_CCGR21_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,21) +#define CCM_CCGR21_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,21) +#define CCM_CCGR22 CCM_CCGR_REG(CCM_BASE_PTR,22) +#define CCM_CCGR22_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,22) +#define CCM_CCGR22_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,22) +#define CCM_CCGR22_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,22) +#define CCM_CCGR23 CCM_CCGR_REG(CCM_BASE_PTR,23) +#define CCM_CCGR23_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,23) +#define CCM_CCGR23_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,23) +#define CCM_CCGR23_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,23) +#define CCM_CCGR24 CCM_CCGR_REG(CCM_BASE_PTR,24) +#define CCM_CCGR24_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,24) +#define CCM_CCGR24_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,24) +#define CCM_CCGR24_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,24) +#define CCM_CCGR25 CCM_CCGR_REG(CCM_BASE_PTR,25) +#define CCM_CCGR25_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,25) +#define CCM_CCGR25_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,25) +#define CCM_CCGR25_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,25) +#define CCM_CCGR26 CCM_CCGR_REG(CCM_BASE_PTR,26) +#define CCM_CCGR26_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,26) +#define CCM_CCGR26_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,26) +#define CCM_CCGR26_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,26) +#define CCM_CCGR27 CCM_CCGR_REG(CCM_BASE_PTR,27) +#define CCM_CCGR27_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,27) +#define CCM_CCGR27_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,27) +#define CCM_CCGR27_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,27) +#define CCM_CCGR28 CCM_CCGR_REG(CCM_BASE_PTR,28) +#define CCM_CCGR28_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,28) +#define CCM_CCGR28_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,28) +#define CCM_CCGR28_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,28) +#define CCM_CCGR29 CCM_CCGR_REG(CCM_BASE_PTR,29) +#define CCM_CCGR29_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,29) +#define CCM_CCGR29_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,29) +#define CCM_CCGR29_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,29) +#define CCM_CCGR30 CCM_CCGR_REG(CCM_BASE_PTR,30) +#define CCM_CCGR30_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,30) +#define CCM_CCGR30_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,30) +#define CCM_CCGR30_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,30) +#define CCM_CCGR31 CCM_CCGR_REG(CCM_BASE_PTR,31) +#define CCM_CCGR31_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,31) +#define CCM_CCGR31_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,31) +#define CCM_CCGR31_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,31) +#define CCM_CCGR32 CCM_CCGR_REG(CCM_BASE_PTR,32) +#define CCM_CCGR32_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,32) +#define CCM_CCGR32_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,32) +#define CCM_CCGR32_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,32) +#define CCM_CCGR33 CCM_CCGR_REG(CCM_BASE_PTR,33) +#define CCM_CCGR33_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,33) +#define CCM_CCGR33_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,33) +#define CCM_CCGR33_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,33) +#define CCM_CCGR34 CCM_CCGR_REG(CCM_BASE_PTR,34) +#define CCM_CCGR34_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,34) +#define CCM_CCGR34_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,34) +#define CCM_CCGR34_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,34) +#define CCM_CCGR35 CCM_CCGR_REG(CCM_BASE_PTR,35) +#define CCM_CCGR35_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,35) +#define CCM_CCGR35_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,35) +#define CCM_CCGR35_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,35) +#define CCM_CCGR36 CCM_CCGR_REG(CCM_BASE_PTR,36) +#define CCM_CCGR36_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,36) +#define CCM_CCGR36_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,36) +#define CCM_CCGR36_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,36) +#define CCM_CCGR37 CCM_CCGR_REG(CCM_BASE_PTR,37) +#define CCM_CCGR37_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,37) +#define CCM_CCGR37_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,37) +#define CCM_CCGR37_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,37) +#define CCM_CCGR38 CCM_CCGR_REG(CCM_BASE_PTR,38) +#define CCM_CCGR38_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,38) +#define CCM_CCGR38_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,38) +#define CCM_CCGR38_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,38) +#define CCM_CCGR39 CCM_CCGR_REG(CCM_BASE_PTR,39) +#define CCM_CCGR39_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,39) +#define CCM_CCGR39_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,39) +#define CCM_CCGR39_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,39) +#define CCM_CCGR40 CCM_CCGR_REG(CCM_BASE_PTR,40) +#define CCM_CCGR40_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,40) +#define CCM_CCGR40_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,40) +#define CCM_CCGR40_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,40) +#define CCM_CCGR41 CCM_CCGR_REG(CCM_BASE_PTR,41) +#define CCM_CCGR41_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,41) +#define CCM_CCGR41_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,41) +#define CCM_CCGR41_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,41) +#define CCM_CCGR42 CCM_CCGR_REG(CCM_BASE_PTR,42) +#define CCM_CCGR42_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,42) +#define CCM_CCGR42_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,42) +#define CCM_CCGR42_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,42) +#define CCM_CCGR43 CCM_CCGR_REG(CCM_BASE_PTR,43) +#define CCM_CCGR43_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,43) +#define CCM_CCGR43_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,43) +#define CCM_CCGR43_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,43) +#define CCM_CCGR44 CCM_CCGR_REG(CCM_BASE_PTR,44) +#define CCM_CCGR44_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,44) +#define CCM_CCGR44_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,44) +#define CCM_CCGR44_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,44) +#define CCM_CCGR45 CCM_CCGR_REG(CCM_BASE_PTR,45) +#define CCM_CCGR45_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,45) +#define CCM_CCGR45_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,45) +#define CCM_CCGR45_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,45) +#define CCM_CCGR46 CCM_CCGR_REG(CCM_BASE_PTR,46) +#define CCM_CCGR46_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,46) +#define CCM_CCGR46_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,46) +#define CCM_CCGR46_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,46) +#define CCM_CCGR47 CCM_CCGR_REG(CCM_BASE_PTR,47) +#define CCM_CCGR47_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,47) +#define CCM_CCGR47_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,47) +#define CCM_CCGR47_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,47) +#define CCM_CCGR48 CCM_CCGR_REG(CCM_BASE_PTR,48) +#define CCM_CCGR48_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,48) +#define CCM_CCGR48_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,48) +#define CCM_CCGR48_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,48) +#define CCM_CCGR49 CCM_CCGR_REG(CCM_BASE_PTR,49) +#define CCM_CCGR49_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,49) +#define CCM_CCGR49_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,49) +#define CCM_CCGR49_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,49) +#define CCM_CCGR50 CCM_CCGR_REG(CCM_BASE_PTR,50) +#define CCM_CCGR50_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,50) +#define CCM_CCGR50_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,50) +#define CCM_CCGR50_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,50) +#define CCM_CCGR51 CCM_CCGR_REG(CCM_BASE_PTR,51) +#define CCM_CCGR51_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,51) +#define CCM_CCGR51_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,51) +#define CCM_CCGR51_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,51) +#define CCM_CCGR52 CCM_CCGR_REG(CCM_BASE_PTR,52) +#define CCM_CCGR52_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,52) +#define CCM_CCGR52_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,52) +#define CCM_CCGR52_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,52) +#define CCM_CCGR53 CCM_CCGR_REG(CCM_BASE_PTR,53) +#define CCM_CCGR53_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,53) +#define CCM_CCGR53_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,53) +#define CCM_CCGR53_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,53) +#define CCM_CCGR54 CCM_CCGR_REG(CCM_BASE_PTR,54) +#define CCM_CCGR54_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,54) +#define CCM_CCGR54_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,54) +#define CCM_CCGR54_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,54) +#define CCM_CCGR55 CCM_CCGR_REG(CCM_BASE_PTR,55) +#define CCM_CCGR55_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,55) +#define CCM_CCGR55_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,55) +#define CCM_CCGR55_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,55) +#define CCM_CCGR56 CCM_CCGR_REG(CCM_BASE_PTR,56) +#define CCM_CCGR56_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,56) +#define CCM_CCGR56_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,56) +#define CCM_CCGR56_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,56) +#define CCM_CCGR57 CCM_CCGR_REG(CCM_BASE_PTR,57) +#define CCM_CCGR57_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,57) +#define CCM_CCGR57_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,57) +#define CCM_CCGR57_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,57) +#define CCM_CCGR58 CCM_CCGR_REG(CCM_BASE_PTR,58) +#define CCM_CCGR58_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,58) +#define CCM_CCGR58_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,58) +#define CCM_CCGR58_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,58) +#define CCM_CCGR59 CCM_CCGR_REG(CCM_BASE_PTR,59) +#define CCM_CCGR59_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,59) +#define CCM_CCGR59_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,59) +#define CCM_CCGR59_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,59) +#define CCM_CCGR60 CCM_CCGR_REG(CCM_BASE_PTR,60) +#define CCM_CCGR60_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,60) +#define CCM_CCGR60_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,60) +#define CCM_CCGR60_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,60) +#define CCM_CCGR61 CCM_CCGR_REG(CCM_BASE_PTR,61) +#define CCM_CCGR61_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,61) +#define CCM_CCGR61_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,61) +#define CCM_CCGR61_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,61) +#define CCM_CCGR62 CCM_CCGR_REG(CCM_BASE_PTR,62) +#define CCM_CCGR62_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,62) +#define CCM_CCGR62_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,62) +#define CCM_CCGR62_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,62) +#define CCM_CCGR63 CCM_CCGR_REG(CCM_BASE_PTR,63) +#define CCM_CCGR63_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,63) +#define CCM_CCGR63_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,63) +#define CCM_CCGR63_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,63) +#define CCM_CCGR64 CCM_CCGR_REG(CCM_BASE_PTR,64) +#define CCM_CCGR64_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,64) +#define CCM_CCGR64_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,64) +#define CCM_CCGR64_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,64) +#define CCM_CCGR65 CCM_CCGR_REG(CCM_BASE_PTR,65) +#define CCM_CCGR65_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,65) +#define CCM_CCGR65_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,65) +#define CCM_CCGR65_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,65) +#define CCM_CCGR66 CCM_CCGR_REG(CCM_BASE_PTR,66) +#define CCM_CCGR66_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,66) +#define CCM_CCGR66_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,66) +#define CCM_CCGR66_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,66) +#define CCM_CCGR67 CCM_CCGR_REG(CCM_BASE_PTR,67) +#define CCM_CCGR67_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,67) +#define CCM_CCGR67_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,67) +#define CCM_CCGR67_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,67) +#define CCM_CCGR68 CCM_CCGR_REG(CCM_BASE_PTR,68) +#define CCM_CCGR68_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,68) +#define CCM_CCGR68_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,68) +#define CCM_CCGR68_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,68) +#define CCM_CCGR69 CCM_CCGR_REG(CCM_BASE_PTR,69) +#define CCM_CCGR69_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,69) +#define CCM_CCGR69_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,69) +#define CCM_CCGR69_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,69) +#define CCM_CCGR70 CCM_CCGR_REG(CCM_BASE_PTR,70) +#define CCM_CCGR70_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,70) +#define CCM_CCGR70_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,70) +#define CCM_CCGR70_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,70) +#define CCM_CCGR71 CCM_CCGR_REG(CCM_BASE_PTR,71) +#define CCM_CCGR71_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,71) +#define CCM_CCGR71_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,71) +#define CCM_CCGR71_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,71) +#define CCM_CCGR72 CCM_CCGR_REG(CCM_BASE_PTR,72) +#define CCM_CCGR72_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,72) +#define CCM_CCGR72_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,72) +#define CCM_CCGR72_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,72) +#define CCM_CCGR73 CCM_CCGR_REG(CCM_BASE_PTR,73) +#define CCM_CCGR73_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,73) +#define CCM_CCGR73_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,73) +#define CCM_CCGR73_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,73) +#define CCM_CCGR74 CCM_CCGR_REG(CCM_BASE_PTR,74) +#define CCM_CCGR74_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,74) +#define CCM_CCGR74_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,74) +#define CCM_CCGR74_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,74) +#define CCM_CCGR75 CCM_CCGR_REG(CCM_BASE_PTR,75) +#define CCM_CCGR75_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,75) +#define CCM_CCGR75_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,75) +#define CCM_CCGR75_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,75) +#define CCM_CCGR76 CCM_CCGR_REG(CCM_BASE_PTR,76) +#define CCM_CCGR76_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,76) +#define CCM_CCGR76_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,76) +#define CCM_CCGR76_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,76) +#define CCM_CCGR77 CCM_CCGR_REG(CCM_BASE_PTR,77) +#define CCM_CCGR77_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,77) +#define CCM_CCGR77_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,77) +#define CCM_CCGR77_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,77) +#define CCM_CCGR78 CCM_CCGR_REG(CCM_BASE_PTR,78) +#define CCM_CCGR78_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,78) +#define CCM_CCGR78_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,78) +#define CCM_CCGR78_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,78) +#define CCM_CCGR79 CCM_CCGR_REG(CCM_BASE_PTR,79) +#define CCM_CCGR79_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,79) +#define CCM_CCGR79_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,79) +#define CCM_CCGR79_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,79) +#define CCM_CCGR80 CCM_CCGR_REG(CCM_BASE_PTR,80) +#define CCM_CCGR80_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,80) +#define CCM_CCGR80_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,80) +#define CCM_CCGR80_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,80) +#define CCM_CCGR81 CCM_CCGR_REG(CCM_BASE_PTR,81) +#define CCM_CCGR81_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,81) +#define CCM_CCGR81_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,81) +#define CCM_CCGR81_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,81) +#define CCM_CCGR82 CCM_CCGR_REG(CCM_BASE_PTR,82) +#define CCM_CCGR82_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,82) +#define CCM_CCGR82_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,82) +#define CCM_CCGR82_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,82) +#define CCM_CCGR83 CCM_CCGR_REG(CCM_BASE_PTR,83) +#define CCM_CCGR83_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,83) +#define CCM_CCGR83_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,83) +#define CCM_CCGR83_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,83) +#define CCM_CCGR84 CCM_CCGR_REG(CCM_BASE_PTR,84) +#define CCM_CCGR84_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,84) +#define CCM_CCGR84_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,84) +#define CCM_CCGR84_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,84) +#define CCM_CCGR85 CCM_CCGR_REG(CCM_BASE_PTR,85) +#define CCM_CCGR85_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,85) +#define CCM_CCGR85_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,85) +#define CCM_CCGR85_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,85) +#define CCM_CCGR86 CCM_CCGR_REG(CCM_BASE_PTR,86) +#define CCM_CCGR86_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,86) +#define CCM_CCGR86_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,86) +#define CCM_CCGR86_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,86) +#define CCM_CCGR87 CCM_CCGR_REG(CCM_BASE_PTR,87) +#define CCM_CCGR87_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,87) +#define CCM_CCGR87_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,87) +#define CCM_CCGR87_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,87) +#define CCM_CCGR88 CCM_CCGR_REG(CCM_BASE_PTR,88) +#define CCM_CCGR88_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,88) +#define CCM_CCGR88_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,88) +#define CCM_CCGR88_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,88) +#define CCM_CCGR89 CCM_CCGR_REG(CCM_BASE_PTR,89) +#define CCM_CCGR89_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,89) +#define CCM_CCGR89_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,89) +#define CCM_CCGR89_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,89) +#define CCM_CCGR90 CCM_CCGR_REG(CCM_BASE_PTR,90) +#define CCM_CCGR90_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,90) +#define CCM_CCGR90_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,90) +#define CCM_CCGR90_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,90) +#define CCM_CCGR91 CCM_CCGR_REG(CCM_BASE_PTR,91) +#define CCM_CCGR91_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,91) +#define CCM_CCGR91_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,91) +#define CCM_CCGR91_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,91) +#define CCM_CCGR92 CCM_CCGR_REG(CCM_BASE_PTR,92) +#define CCM_CCGR92_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,92) +#define CCM_CCGR92_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,92) +#define CCM_CCGR92_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,92) +#define CCM_CCGR93 CCM_CCGR_REG(CCM_BASE_PTR,93) +#define CCM_CCGR93_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,93) +#define CCM_CCGR93_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,93) +#define CCM_CCGR93_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,93) +#define CCM_CCGR94 CCM_CCGR_REG(CCM_BASE_PTR,94) +#define CCM_CCGR94_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,94) +#define CCM_CCGR94_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,94) +#define CCM_CCGR94_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,94) +#define CCM_CCGR95 CCM_CCGR_REG(CCM_BASE_PTR,95) +#define CCM_CCGR95_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,95) +#define CCM_CCGR95_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,95) +#define CCM_CCGR95_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,95) +#define CCM_CCGR96 CCM_CCGR_REG(CCM_BASE_PTR,96) +#define CCM_CCGR96_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,96) +#define CCM_CCGR96_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,96) +#define CCM_CCGR96_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,96) +#define CCM_CCGR97 CCM_CCGR_REG(CCM_BASE_PTR,97) +#define CCM_CCGR97_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,97) +#define CCM_CCGR97_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,97) +#define CCM_CCGR97_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,97) +#define CCM_CCGR98 CCM_CCGR_REG(CCM_BASE_PTR,98) +#define CCM_CCGR98_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,98) +#define CCM_CCGR98_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,98) +#define CCM_CCGR98_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,98) +#define CCM_CCGR99 CCM_CCGR_REG(CCM_BASE_PTR,99) +#define CCM_CCGR99_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,99) +#define CCM_CCGR99_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,99) +#define CCM_CCGR99_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,99) +#define CCM_CCGR100 CCM_CCGR_REG(CCM_BASE_PTR,100) +#define CCM_CCGR100_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,100) +#define CCM_CCGR100_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,100) +#define CCM_CCGR100_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,100) +#define CCM_CCGR101 CCM_CCGR_REG(CCM_BASE_PTR,101) +#define CCM_CCGR101_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,101) +#define CCM_CCGR101_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,101) +#define CCM_CCGR101_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,101) +#define CCM_CCGR102 CCM_CCGR_REG(CCM_BASE_PTR,102) +#define CCM_CCGR102_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,102) +#define CCM_CCGR102_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,102) +#define CCM_CCGR102_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,102) +#define CCM_CCGR103 CCM_CCGR_REG(CCM_BASE_PTR,103) +#define CCM_CCGR103_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,103) +#define CCM_CCGR103_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,103) +#define CCM_CCGR103_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,103) +#define CCM_CCGR104 CCM_CCGR_REG(CCM_BASE_PTR,104) +#define CCM_CCGR104_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,104) +#define CCM_CCGR104_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,104) +#define CCM_CCGR104_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,104) +#define CCM_CCGR105 CCM_CCGR_REG(CCM_BASE_PTR,105) +#define CCM_CCGR105_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,105) +#define CCM_CCGR105_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,105) +#define CCM_CCGR105_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,105) +#define CCM_CCGR106 CCM_CCGR_REG(CCM_BASE_PTR,106) +#define CCM_CCGR106_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,106) +#define CCM_CCGR106_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,106) +#define CCM_CCGR106_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,106) +#define CCM_CCGR107 CCM_CCGR_REG(CCM_BASE_PTR,107) +#define CCM_CCGR107_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,107) +#define CCM_CCGR107_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,107) +#define CCM_CCGR107_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,107) +#define CCM_CCGR108 CCM_CCGR_REG(CCM_BASE_PTR,108) +#define CCM_CCGR108_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,108) +#define CCM_CCGR108_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,108) +#define CCM_CCGR108_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,108) +#define CCM_CCGR109 CCM_CCGR_REG(CCM_BASE_PTR,109) +#define CCM_CCGR109_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,109) +#define CCM_CCGR109_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,109) +#define CCM_CCGR109_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,109) +#define CCM_CCGR110 CCM_CCGR_REG(CCM_BASE_PTR,110) +#define CCM_CCGR110_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,110) +#define CCM_CCGR110_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,110) +#define CCM_CCGR110_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,110) +#define CCM_CCGR111 CCM_CCGR_REG(CCM_BASE_PTR,111) +#define CCM_CCGR111_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,111) +#define CCM_CCGR111_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,111) +#define CCM_CCGR111_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,111) +#define CCM_CCGR112 CCM_CCGR_REG(CCM_BASE_PTR,112) +#define CCM_CCGR112_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,112) +#define CCM_CCGR112_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,112) +#define CCM_CCGR112_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,112) +#define CCM_CCGR113 CCM_CCGR_REG(CCM_BASE_PTR,113) +#define CCM_CCGR113_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,113) +#define CCM_CCGR113_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,113) +#define CCM_CCGR113_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,113) +#define CCM_CCGR114 CCM_CCGR_REG(CCM_BASE_PTR,114) +#define CCM_CCGR114_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,114) +#define CCM_CCGR114_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,114) +#define CCM_CCGR114_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,114) +#define CCM_CCGR115 CCM_CCGR_REG(CCM_BASE_PTR,115) +#define CCM_CCGR115_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,115) +#define CCM_CCGR115_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,115) +#define CCM_CCGR115_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,115) +#define CCM_CCGR116 CCM_CCGR_REG(CCM_BASE_PTR,116) +#define CCM_CCGR116_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,116) +#define CCM_CCGR116_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,116) +#define CCM_CCGR116_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,116) +#define CCM_CCGR117 CCM_CCGR_REG(CCM_BASE_PTR,117) +#define CCM_CCGR117_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,117) +#define CCM_CCGR117_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,117) +#define CCM_CCGR117_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,117) +#define CCM_CCGR118 CCM_CCGR_REG(CCM_BASE_PTR,118) +#define CCM_CCGR118_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,118) +#define CCM_CCGR118_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,118) +#define CCM_CCGR118_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,118) +#define CCM_CCGR119 CCM_CCGR_REG(CCM_BASE_PTR,119) +#define CCM_CCGR119_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,119) +#define CCM_CCGR119_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,119) +#define CCM_CCGR119_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,119) +#define CCM_CCGR120 CCM_CCGR_REG(CCM_BASE_PTR,120) +#define CCM_CCGR120_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,120) +#define CCM_CCGR120_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,120) +#define CCM_CCGR120_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,120) +#define CCM_CCGR121 CCM_CCGR_REG(CCM_BASE_PTR,121) +#define CCM_CCGR121_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,121) +#define CCM_CCGR121_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,121) +#define CCM_CCGR121_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,121) +#define CCM_CCGR122 CCM_CCGR_REG(CCM_BASE_PTR,122) +#define CCM_CCGR122_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,122) +#define CCM_CCGR122_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,122) +#define CCM_CCGR122_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,122) +#define CCM_CCGR123 CCM_CCGR_REG(CCM_BASE_PTR,123) +#define CCM_CCGR123_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,123) +#define CCM_CCGR123_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,123) +#define CCM_CCGR123_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,123) +#define CCM_CCGR124 CCM_CCGR_REG(CCM_BASE_PTR,124) +#define CCM_CCGR124_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,124) +#define CCM_CCGR124_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,124) +#define CCM_CCGR124_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,124) +#define CCM_CCGR125 CCM_CCGR_REG(CCM_BASE_PTR,125) +#define CCM_CCGR125_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,125) +#define CCM_CCGR125_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,125) +#define CCM_CCGR125_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,125) +#define CCM_CCGR126 CCM_CCGR_REG(CCM_BASE_PTR,126) +#define CCM_CCGR126_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,126) +#define CCM_CCGR126_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,126) +#define CCM_CCGR126_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,126) +#define CCM_CCGR127 CCM_CCGR_REG(CCM_BASE_PTR,127) +#define CCM_CCGR127_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,127) +#define CCM_CCGR127_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,127) +#define CCM_CCGR127_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,127) +#define CCM_CCGR128 CCM_CCGR_REG(CCM_BASE_PTR,128) +#define CCM_CCGR128_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,128) +#define CCM_CCGR128_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,128) +#define CCM_CCGR128_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,128) +#define CCM_CCGR129 CCM_CCGR_REG(CCM_BASE_PTR,129) +#define CCM_CCGR129_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,129) +#define CCM_CCGR129_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,129) +#define CCM_CCGR129_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,129) +#define CCM_CCGR130 CCM_CCGR_REG(CCM_BASE_PTR,130) +#define CCM_CCGR130_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,130) +#define CCM_CCGR130_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,130) +#define CCM_CCGR130_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,130) +#define CCM_CCGR131 CCM_CCGR_REG(CCM_BASE_PTR,131) +#define CCM_CCGR131_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,131) +#define CCM_CCGR131_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,131) +#define CCM_CCGR131_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,131) +#define CCM_CCGR132 CCM_CCGR_REG(CCM_BASE_PTR,132) +#define CCM_CCGR132_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,132) +#define CCM_CCGR132_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,132) +#define CCM_CCGR132_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,132) +#define CCM_CCGR133 CCM_CCGR_REG(CCM_BASE_PTR,133) +#define CCM_CCGR133_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,133) +#define CCM_CCGR133_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,133) +#define CCM_CCGR133_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,133) +#define CCM_CCGR134 CCM_CCGR_REG(CCM_BASE_PTR,134) +#define CCM_CCGR134_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,134) +#define CCM_CCGR134_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,134) +#define CCM_CCGR134_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,134) +#define CCM_CCGR135 CCM_CCGR_REG(CCM_BASE_PTR,135) +#define CCM_CCGR135_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,135) +#define CCM_CCGR135_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,135) +#define CCM_CCGR135_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,135) +#define CCM_CCGR136 CCM_CCGR_REG(CCM_BASE_PTR,136) +#define CCM_CCGR136_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,136) +#define CCM_CCGR136_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,136) +#define CCM_CCGR136_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,136) +#define CCM_CCGR137 CCM_CCGR_REG(CCM_BASE_PTR,137) +#define CCM_CCGR137_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,137) +#define CCM_CCGR137_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,137) +#define CCM_CCGR137_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,137) +#define CCM_CCGR138 CCM_CCGR_REG(CCM_BASE_PTR,138) +#define CCM_CCGR138_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,138) +#define CCM_CCGR138_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,138) +#define CCM_CCGR138_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,138) +#define CCM_CCGR139 CCM_CCGR_REG(CCM_BASE_PTR,139) +#define CCM_CCGR139_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,139) +#define CCM_CCGR139_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,139) +#define CCM_CCGR139_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,139) +#define CCM_CCGR140 CCM_CCGR_REG(CCM_BASE_PTR,140) +#define CCM_CCGR140_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,140) +#define CCM_CCGR140_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,140) +#define CCM_CCGR140_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,140) +#define CCM_CCGR141 CCM_CCGR_REG(CCM_BASE_PTR,141) +#define CCM_CCGR141_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,141) +#define CCM_CCGR141_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,141) +#define CCM_CCGR141_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,141) +#define CCM_CCGR142 CCM_CCGR_REG(CCM_BASE_PTR,142) +#define CCM_CCGR142_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,142) +#define CCM_CCGR142_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,142) +#define CCM_CCGR142_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,142) +#define CCM_CCGR143 CCM_CCGR_REG(CCM_BASE_PTR,143) +#define CCM_CCGR143_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,143) +#define CCM_CCGR143_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,143) +#define CCM_CCGR143_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,143) +#define CCM_CCGR144 CCM_CCGR_REG(CCM_BASE_PTR,144) +#define CCM_CCGR144_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,144) +#define CCM_CCGR144_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,144) +#define CCM_CCGR144_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,144) +#define CCM_CCGR145 CCM_CCGR_REG(CCM_BASE_PTR,145) +#define CCM_CCGR145_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,145) +#define CCM_CCGR145_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,145) +#define CCM_CCGR145_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,145) +#define CCM_CCGR146 CCM_CCGR_REG(CCM_BASE_PTR,146) +#define CCM_CCGR146_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,146) +#define CCM_CCGR146_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,146) +#define CCM_CCGR146_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,146) +#define CCM_CCGR147 CCM_CCGR_REG(CCM_BASE_PTR,147) +#define CCM_CCGR147_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,147) +#define CCM_CCGR147_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,147) +#define CCM_CCGR147_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,147) +#define CCM_CCGR148 CCM_CCGR_REG(CCM_BASE_PTR,148) +#define CCM_CCGR148_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,148) +#define CCM_CCGR148_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,148) +#define CCM_CCGR148_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,148) +#define CCM_CCGR149 CCM_CCGR_REG(CCM_BASE_PTR,149) +#define CCM_CCGR149_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,149) +#define CCM_CCGR149_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,149) +#define CCM_CCGR149_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,149) +#define CCM_CCGR150 CCM_CCGR_REG(CCM_BASE_PTR,150) +#define CCM_CCGR150_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,150) +#define CCM_CCGR150_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,150) +#define CCM_CCGR150_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,150) +#define CCM_CCGR151 CCM_CCGR_REG(CCM_BASE_PTR,151) +#define CCM_CCGR151_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,151) +#define CCM_CCGR151_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,151) +#define CCM_CCGR151_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,151) +#define CCM_CCGR152 CCM_CCGR_REG(CCM_BASE_PTR,152) +#define CCM_CCGR152_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,152) +#define CCM_CCGR152_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,152) +#define CCM_CCGR152_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,152) +#define CCM_CCGR153 CCM_CCGR_REG(CCM_BASE_PTR,153) +#define CCM_CCGR153_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,153) +#define CCM_CCGR153_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,153) +#define CCM_CCGR153_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,153) +#define CCM_CCGR154 CCM_CCGR_REG(CCM_BASE_PTR,154) +#define CCM_CCGR154_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,154) +#define CCM_CCGR154_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,154) +#define CCM_CCGR154_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,154) +#define CCM_CCGR155 CCM_CCGR_REG(CCM_BASE_PTR,155) +#define CCM_CCGR155_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,155) +#define CCM_CCGR155_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,155) +#define CCM_CCGR155_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,155) +#define CCM_CCGR156 CCM_CCGR_REG(CCM_BASE_PTR,156) +#define CCM_CCGR156_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,156) +#define CCM_CCGR156_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,156) +#define CCM_CCGR156_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,156) +#define CCM_CCGR157 CCM_CCGR_REG(CCM_BASE_PTR,157) +#define CCM_CCGR157_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,157) +#define CCM_CCGR157_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,157) +#define CCM_CCGR157_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,157) +#define CCM_CCGR158 CCM_CCGR_REG(CCM_BASE_PTR,158) +#define CCM_CCGR158_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,158) +#define CCM_CCGR158_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,158) +#define CCM_CCGR158_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,158) +#define CCM_CCGR159 CCM_CCGR_REG(CCM_BASE_PTR,159) +#define CCM_CCGR159_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,159) +#define CCM_CCGR159_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,159) +#define CCM_CCGR159_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,159) +#define CCM_CCGR160 CCM_CCGR_REG(CCM_BASE_PTR,160) +#define CCM_CCGR160_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,160) +#define CCM_CCGR160_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,160) +#define CCM_CCGR160_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,160) +#define CCM_CCGR161 CCM_CCGR_REG(CCM_BASE_PTR,161) +#define CCM_CCGR161_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,161) +#define CCM_CCGR161_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,161) +#define CCM_CCGR161_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,161) +#define CCM_CCGR162 CCM_CCGR_REG(CCM_BASE_PTR,162) +#define CCM_CCGR162_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,162) +#define CCM_CCGR162_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,162) +#define CCM_CCGR162_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,162) +#define CCM_CCGR163 CCM_CCGR_REG(CCM_BASE_PTR,163) +#define CCM_CCGR163_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,163) +#define CCM_CCGR163_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,163) +#define CCM_CCGR163_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,163) +#define CCM_CCGR164 CCM_CCGR_REG(CCM_BASE_PTR,164) +#define CCM_CCGR164_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,164) +#define CCM_CCGR164_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,164) +#define CCM_CCGR164_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,164) +#define CCM_CCGR165 CCM_CCGR_REG(CCM_BASE_PTR,165) +#define CCM_CCGR165_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,165) +#define CCM_CCGR165_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,165) +#define CCM_CCGR165_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,165) +#define CCM_CCGR166 CCM_CCGR_REG(CCM_BASE_PTR,166) +#define CCM_CCGR166_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,166) +#define CCM_CCGR166_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,166) +#define CCM_CCGR166_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,166) +#define CCM_CCGR167 CCM_CCGR_REG(CCM_BASE_PTR,167) +#define CCM_CCGR167_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,167) +#define CCM_CCGR167_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,167) +#define CCM_CCGR167_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,167) +#define CCM_CCGR168 CCM_CCGR_REG(CCM_BASE_PTR,168) +#define CCM_CCGR168_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,168) +#define CCM_CCGR168_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,168) +#define CCM_CCGR168_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,168) +#define CCM_CCGR169 CCM_CCGR_REG(CCM_BASE_PTR,169) +#define CCM_CCGR169_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,169) +#define CCM_CCGR169_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,169) +#define CCM_CCGR169_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,169) +#define CCM_CCGR170 CCM_CCGR_REG(CCM_BASE_PTR,170) +#define CCM_CCGR170_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,170) +#define CCM_CCGR170_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,170) +#define CCM_CCGR170_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,170) +#define CCM_CCGR171 CCM_CCGR_REG(CCM_BASE_PTR,171) +#define CCM_CCGR171_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,171) +#define CCM_CCGR171_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,171) +#define CCM_CCGR171_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,171) +#define CCM_CCGR172 CCM_CCGR_REG(CCM_BASE_PTR,172) +#define CCM_CCGR172_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,172) +#define CCM_CCGR172_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,172) +#define CCM_CCGR172_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,172) +#define CCM_CCGR173 CCM_CCGR_REG(CCM_BASE_PTR,173) +#define CCM_CCGR173_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,173) +#define CCM_CCGR173_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,173) +#define CCM_CCGR173_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,173) +#define CCM_CCGR174 CCM_CCGR_REG(CCM_BASE_PTR,174) +#define CCM_CCGR174_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,174) +#define CCM_CCGR174_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,174) +#define CCM_CCGR174_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,174) +#define CCM_CCGR175 CCM_CCGR_REG(CCM_BASE_PTR,175) +#define CCM_CCGR175_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,175) +#define CCM_CCGR175_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,175) +#define CCM_CCGR175_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,175) +#define CCM_CCGR176 CCM_CCGR_REG(CCM_BASE_PTR,176) +#define CCM_CCGR176_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,176) +#define CCM_CCGR176_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,176) +#define CCM_CCGR176_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,176) +#define CCM_CCGR177 CCM_CCGR_REG(CCM_BASE_PTR,177) +#define CCM_CCGR177_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,177) +#define CCM_CCGR177_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,177) +#define CCM_CCGR177_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,177) +#define CCM_CCGR178 CCM_CCGR_REG(CCM_BASE_PTR,178) +#define CCM_CCGR178_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,178) +#define CCM_CCGR178_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,178) +#define CCM_CCGR178_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,178) +#define CCM_CCGR179 CCM_CCGR_REG(CCM_BASE_PTR,179) +#define CCM_CCGR179_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,179) +#define CCM_CCGR179_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,179) +#define CCM_CCGR179_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,179) +#define CCM_CCGR180 CCM_CCGR_REG(CCM_BASE_PTR,180) +#define CCM_CCGR180_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,180) +#define CCM_CCGR180_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,180) +#define CCM_CCGR180_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,180) +#define CCM_CCGR181 CCM_CCGR_REG(CCM_BASE_PTR,181) +#define CCM_CCGR181_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,181) +#define CCM_CCGR181_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,181) +#define CCM_CCGR181_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,181) +#define CCM_CCGR182 CCM_CCGR_REG(CCM_BASE_PTR,182) +#define CCM_CCGR182_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,182) +#define CCM_CCGR182_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,182) +#define CCM_CCGR182_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,182) +#define CCM_CCGR183 CCM_CCGR_REG(CCM_BASE_PTR,183) +#define CCM_CCGR183_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,183) +#define CCM_CCGR183_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,183) +#define CCM_CCGR183_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,183) +#define CCM_CCGR184 CCM_CCGR_REG(CCM_BASE_PTR,184) +#define CCM_CCGR184_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,184) +#define CCM_CCGR184_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,184) +#define CCM_CCGR184_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,184) +#define CCM_CCGR185 CCM_CCGR_REG(CCM_BASE_PTR,185) +#define CCM_CCGR185_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,185) +#define CCM_CCGR185_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,185) +#define CCM_CCGR185_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,185) +#define CCM_CCGR186 CCM_CCGR_REG(CCM_BASE_PTR,186) +#define CCM_CCGR186_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,186) +#define CCM_CCGR186_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,186) +#define CCM_CCGR186_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,186) +#define CCM_CCGR187 CCM_CCGR_REG(CCM_BASE_PTR,187) +#define CCM_CCGR187_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,187) +#define CCM_CCGR187_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,187) +#define CCM_CCGR187_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,187) +#define CCM_CCGR188 CCM_CCGR_REG(CCM_BASE_PTR,188) +#define CCM_CCGR188_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,188) +#define CCM_CCGR188_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,188) +#define CCM_CCGR188_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,188) +#define CCM_CCGR189 CCM_CCGR_REG(CCM_BASE_PTR,189) +#define CCM_CCGR189_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,189) +#define CCM_CCGR189_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,189) +#define CCM_CCGR189_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,189) +#define CCM_CCGR190 CCM_CCGR_REG(CCM_BASE_PTR,190) +#define CCM_CCGR190_SET CCM_CCGR_SET_REG(CCM_BASE_PTR,190) +#define CCM_CCGR190_CLR CCM_CCGR_CLR_REG(CCM_BASE_PTR,190) +#define CCM_CCGR190_TOG CCM_CCGR_TOG_REG(CCM_BASE_PTR,190) +#define CCM_TARGET_ROOT0 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,0) +#define CCM_TARGET_ROOT0_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,0) +#define CCM_TARGET_ROOT0_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,0) +#define CCM_TARGET_ROOT0_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,0) +#define CCM_MISC0 CCM_MISC_REG(CCM_BASE_PTR,0) +#define CCM_MISC_ROOT0_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,0) +#define CCM_MISC_ROOT0_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,0) +#define CCM_MISC_ROOT0_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,0) +#define CCM_POST0 CCM_POST_REG(CCM_BASE_PTR,0) +#define CCM_POST_ROOT0_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,0) +#define CCM_POST_ROOT0_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,0) +#define CCM_POST_ROOT0_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,0) +#define CCM_PRE0 CCM_PRE_REG(CCM_BASE_PTR,0) +#define CCM_PRE_ROOT0_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,0) +#define CCM_PRE_ROOT0_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,0) +#define CCM_PRE_ROOT0_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,0) +#define CCM_ACCESS_CTRL0 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,0) +#define CCM_ACCESS_CTRL_ROOT0_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,0) +#define CCM_ACCESS_CTRL_ROOT0_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,0) +#define CCM_ACCESS_CTRL_ROOT0_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,0) +#define CCM_TARGET_ROOT1 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,1) +#define CCM_TARGET_ROOT1_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,1) +#define CCM_TARGET_ROOT1_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,1) +#define CCM_TARGET_ROOT1_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,1) +#define CCM_MISC1 CCM_MISC_REG(CCM_BASE_PTR,1) +#define CCM_MISC_ROOT1_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,1) +#define CCM_MISC_ROOT1_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,1) +#define CCM_MISC_ROOT1_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,1) +#define CCM_POST1 CCM_POST_REG(CCM_BASE_PTR,1) +#define CCM_POST_ROOT1_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,1) +#define CCM_POST_ROOT1_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,1) +#define CCM_POST_ROOT1_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,1) +#define CCM_PRE1 CCM_PRE_REG(CCM_BASE_PTR,1) +#define CCM_PRE_ROOT1_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,1) +#define CCM_PRE_ROOT1_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,1) +#define CCM_PRE_ROOT1_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,1) +#define CCM_ACCESS_CTRL1 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,1) +#define CCM_ACCESS_CTRL_ROOT1_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,1) +#define CCM_ACCESS_CTRL_ROOT1_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,1) +#define CCM_ACCESS_CTRL_ROOT1_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,1) +#define CCM_TARGET_ROOT2 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,2) +#define CCM_TARGET_ROOT2_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,2) +#define CCM_TARGET_ROOT2_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,2) +#define CCM_TARGET_ROOT2_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,2) +#define CCM_MISC2 CCM_MISC_REG(CCM_BASE_PTR,2) +#define CCM_MISC_ROOT2_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,2) +#define CCM_MISC_ROOT2_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,2) +#define CCM_MISC_ROOT2_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,2) +#define CCM_POST2 CCM_POST_REG(CCM_BASE_PTR,2) +#define CCM_POST_ROOT2_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,2) +#define CCM_POST_ROOT2_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,2) +#define CCM_POST_ROOT2_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,2) +#define CCM_PRE2 CCM_PRE_REG(CCM_BASE_PTR,2) +#define CCM_PRE_ROOT2_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,2) +#define CCM_PRE_ROOT2_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,2) +#define CCM_PRE_ROOT2_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,2) +#define CCM_ACCESS_CTRL2 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,2) +#define CCM_ACCESS_CTRL_ROOT2_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,2) +#define CCM_ACCESS_CTRL_ROOT2_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,2) +#define CCM_ACCESS_CTRL_ROOT2_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,2) +#define CCM_TARGET_ROOT3 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,3) +#define CCM_TARGET_ROOT3_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,3) +#define CCM_TARGET_ROOT3_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,3) +#define CCM_TARGET_ROOT3_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,3) +#define CCM_MISC3 CCM_MISC_REG(CCM_BASE_PTR,3) +#define CCM_MISC_ROOT3_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,3) +#define CCM_MISC_ROOT3_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,3) +#define CCM_MISC_ROOT3_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,3) +#define CCM_POST3 CCM_POST_REG(CCM_BASE_PTR,3) +#define CCM_POST_ROOT3_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,3) +#define CCM_POST_ROOT3_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,3) +#define CCM_POST_ROOT3_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,3) +#define CCM_PRE3 CCM_PRE_REG(CCM_BASE_PTR,3) +#define CCM_PRE_ROOT3_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,3) +#define CCM_PRE_ROOT3_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,3) +#define CCM_PRE_ROOT3_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,3) +#define CCM_ACCESS_CTRL3 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,3) +#define CCM_ACCESS_CTRL_ROOT3_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,3) +#define CCM_ACCESS_CTRL_ROOT3_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,3) +#define CCM_ACCESS_CTRL_ROOT3_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,3) +#define CCM_TARGET_ROOT4 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,4) +#define CCM_TARGET_ROOT4_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,4) +#define CCM_TARGET_ROOT4_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,4) +#define CCM_TARGET_ROOT4_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,4) +#define CCM_MISC4 CCM_MISC_REG(CCM_BASE_PTR,4) +#define CCM_MISC_ROOT4_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,4) +#define CCM_MISC_ROOT4_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,4) +#define CCM_MISC_ROOT4_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,4) +#define CCM_POST4 CCM_POST_REG(CCM_BASE_PTR,4) +#define CCM_POST_ROOT4_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,4) +#define CCM_POST_ROOT4_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,4) +#define CCM_POST_ROOT4_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,4) +#define CCM_PRE4 CCM_PRE_REG(CCM_BASE_PTR,4) +#define CCM_PRE_ROOT4_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,4) +#define CCM_PRE_ROOT4_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,4) +#define CCM_PRE_ROOT4_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,4) +#define CCM_ACCESS_CTRL4 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,4) +#define CCM_ACCESS_CTRL_ROOT4_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,4) +#define CCM_ACCESS_CTRL_ROOT4_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,4) +#define CCM_ACCESS_CTRL_ROOT4_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,4) +#define CCM_TARGET_ROOT5 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,5) +#define CCM_TARGET_ROOT5_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,5) +#define CCM_TARGET_ROOT5_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,5) +#define CCM_TARGET_ROOT5_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,5) +#define CCM_MISC5 CCM_MISC_REG(CCM_BASE_PTR,5) +#define CCM_MISC_ROOT5_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,5) +#define CCM_MISC_ROOT5_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,5) +#define CCM_MISC_ROOT5_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,5) +#define CCM_POST5 CCM_POST_REG(CCM_BASE_PTR,5) +#define CCM_POST_ROOT5_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,5) +#define CCM_POST_ROOT5_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,5) +#define CCM_POST_ROOT5_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,5) +#define CCM_PRE5 CCM_PRE_REG(CCM_BASE_PTR,5) +#define CCM_PRE_ROOT5_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,5) +#define CCM_PRE_ROOT5_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,5) +#define CCM_PRE_ROOT5_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,5) +#define CCM_ACCESS_CTRL5 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,5) +#define CCM_ACCESS_CTRL_ROOT5_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,5) +#define CCM_ACCESS_CTRL_ROOT5_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,5) +#define CCM_ACCESS_CTRL_ROOT5_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,5) +#define CCM_TARGET_ROOT6 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,6) +#define CCM_TARGET_ROOT6_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,6) +#define CCM_TARGET_ROOT6_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,6) +#define CCM_TARGET_ROOT6_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,6) +#define CCM_MISC6 CCM_MISC_REG(CCM_BASE_PTR,6) +#define CCM_MISC_ROOT6_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,6) +#define CCM_MISC_ROOT6_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,6) +#define CCM_MISC_ROOT6_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,6) +#define CCM_POST6 CCM_POST_REG(CCM_BASE_PTR,6) +#define CCM_POST_ROOT6_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,6) +#define CCM_POST_ROOT6_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,6) +#define CCM_POST_ROOT6_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,6) +#define CCM_PRE6 CCM_PRE_REG(CCM_BASE_PTR,6) +#define CCM_PRE_ROOT6_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,6) +#define CCM_PRE_ROOT6_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,6) +#define CCM_PRE_ROOT6_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,6) +#define CCM_ACCESS_CTRL6 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,6) +#define CCM_ACCESS_CTRL_ROOT6_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,6) +#define CCM_ACCESS_CTRL_ROOT6_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,6) +#define CCM_ACCESS_CTRL_ROOT6_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,6) +#define CCM_TARGET_ROOT7 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,7) +#define CCM_TARGET_ROOT7_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,7) +#define CCM_TARGET_ROOT7_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,7) +#define CCM_TARGET_ROOT7_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,7) +#define CCM_MISC7 CCM_MISC_REG(CCM_BASE_PTR,7) +#define CCM_MISC_ROOT7_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,7) +#define CCM_MISC_ROOT7_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,7) +#define CCM_MISC_ROOT7_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,7) +#define CCM_POST7 CCM_POST_REG(CCM_BASE_PTR,7) +#define CCM_POST_ROOT7_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,7) +#define CCM_POST_ROOT7_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,7) +#define CCM_POST_ROOT7_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,7) +#define CCM_PRE7 CCM_PRE_REG(CCM_BASE_PTR,7) +#define CCM_PRE_ROOT7_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,7) +#define CCM_PRE_ROOT7_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,7) +#define CCM_PRE_ROOT7_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,7) +#define CCM_ACCESS_CTRL7 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,7) +#define CCM_ACCESS_CTRL_ROOT7_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,7) +#define CCM_ACCESS_CTRL_ROOT7_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,7) +#define CCM_ACCESS_CTRL_ROOT7_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,7) +#define CCM_TARGET_ROOT8 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,8) +#define CCM_TARGET_ROOT8_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,8) +#define CCM_TARGET_ROOT8_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,8) +#define CCM_TARGET_ROOT8_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,8) +#define CCM_MISC8 CCM_MISC_REG(CCM_BASE_PTR,8) +#define CCM_MISC_ROOT8_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,8) +#define CCM_MISC_ROOT8_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,8) +#define CCM_MISC_ROOT8_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,8) +#define CCM_POST8 CCM_POST_REG(CCM_BASE_PTR,8) +#define CCM_POST_ROOT8_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,8) +#define CCM_POST_ROOT8_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,8) +#define CCM_POST_ROOT8_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,8) +#define CCM_PRE8 CCM_PRE_REG(CCM_BASE_PTR,8) +#define CCM_PRE_ROOT8_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,8) +#define CCM_PRE_ROOT8_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,8) +#define CCM_PRE_ROOT8_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,8) +#define CCM_ACCESS_CTRL8 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,8) +#define CCM_ACCESS_CTRL_ROOT8_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,8) +#define CCM_ACCESS_CTRL_ROOT8_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,8) +#define CCM_ACCESS_CTRL_ROOT8_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,8) +#define CCM_TARGET_ROOT9 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,9) +#define CCM_TARGET_ROOT9_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,9) +#define CCM_TARGET_ROOT9_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,9) +#define CCM_TARGET_ROOT9_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,9) +#define CCM_MISC9 CCM_MISC_REG(CCM_BASE_PTR,9) +#define CCM_MISC_ROOT9_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,9) +#define CCM_MISC_ROOT9_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,9) +#define CCM_MISC_ROOT9_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,9) +#define CCM_POST9 CCM_POST_REG(CCM_BASE_PTR,9) +#define CCM_POST_ROOT9_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,9) +#define CCM_POST_ROOT9_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,9) +#define CCM_POST_ROOT9_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,9) +#define CCM_PRE9 CCM_PRE_REG(CCM_BASE_PTR,9) +#define CCM_PRE_ROOT9_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,9) +#define CCM_PRE_ROOT9_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,9) +#define CCM_PRE_ROOT9_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,9) +#define CCM_ACCESS_CTRL9 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,9) +#define CCM_ACCESS_CTRL_ROOT9_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,9) +#define CCM_ACCESS_CTRL_ROOT9_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,9) +#define CCM_ACCESS_CTRL_ROOT9_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,9) +#define CCM_TARGET_ROOT10 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,10) +#define CCM_TARGET_ROOT10_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,10) +#define CCM_TARGET_ROOT10_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,10) +#define CCM_TARGET_ROOT10_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,10) +#define CCM_MISC10 CCM_MISC_REG(CCM_BASE_PTR,10) +#define CCM_MISC_ROOT10_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,10) +#define CCM_MISC_ROOT10_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,10) +#define CCM_MISC_ROOT10_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,10) +#define CCM_POST10 CCM_POST_REG(CCM_BASE_PTR,10) +#define CCM_POST_ROOT10_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,10) +#define CCM_POST_ROOT10_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,10) +#define CCM_POST_ROOT10_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,10) +#define CCM_PRE10 CCM_PRE_REG(CCM_BASE_PTR,10) +#define CCM_PRE_ROOT10_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,10) +#define CCM_PRE_ROOT10_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,10) +#define CCM_PRE_ROOT10_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,10) +#define CCM_ACCESS_CTRL10 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,10) +#define CCM_ACCESS_CTRL_ROOT10_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,10) +#define CCM_ACCESS_CTRL_ROOT10_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,10) +#define CCM_ACCESS_CTRL_ROOT10_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,10) +#define CCM_TARGET_ROOT11 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,11) +#define CCM_TARGET_ROOT11_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,11) +#define CCM_TARGET_ROOT11_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,11) +#define CCM_TARGET_ROOT11_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,11) +#define CCM_MISC11 CCM_MISC_REG(CCM_BASE_PTR,11) +#define CCM_MISC_ROOT11_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,11) +#define CCM_MISC_ROOT11_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,11) +#define CCM_MISC_ROOT11_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,11) +#define CCM_POST11 CCM_POST_REG(CCM_BASE_PTR,11) +#define CCM_POST_ROOT11_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,11) +#define CCM_POST_ROOT11_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,11) +#define CCM_POST_ROOT11_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,11) +#define CCM_PRE11 CCM_PRE_REG(CCM_BASE_PTR,11) +#define CCM_PRE_ROOT11_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,11) +#define CCM_PRE_ROOT11_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,11) +#define CCM_PRE_ROOT11_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,11) +#define CCM_ACCESS_CTRL11 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,11) +#define CCM_ACCESS_CTRL_ROOT11_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,11) +#define CCM_ACCESS_CTRL_ROOT11_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,11) +#define CCM_ACCESS_CTRL_ROOT11_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,11) +#define CCM_TARGET_ROOT12 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,12) +#define CCM_TARGET_ROOT12_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,12) +#define CCM_TARGET_ROOT12_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,12) +#define CCM_TARGET_ROOT12_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,12) +#define CCM_MISC12 CCM_MISC_REG(CCM_BASE_PTR,12) +#define CCM_MISC_ROOT12_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,12) +#define CCM_MISC_ROOT12_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,12) +#define CCM_MISC_ROOT12_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,12) +#define CCM_POST12 CCM_POST_REG(CCM_BASE_PTR,12) +#define CCM_POST_ROOT12_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,12) +#define CCM_POST_ROOT12_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,12) +#define CCM_POST_ROOT12_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,12) +#define CCM_PRE12 CCM_PRE_REG(CCM_BASE_PTR,12) +#define CCM_PRE_ROOT12_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,12) +#define CCM_PRE_ROOT12_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,12) +#define CCM_PRE_ROOT12_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,12) +#define CCM_ACCESS_CTRL12 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,12) +#define CCM_ACCESS_CTRL_ROOT12_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,12) +#define CCM_ACCESS_CTRL_ROOT12_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,12) +#define CCM_ACCESS_CTRL_ROOT12_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,12) +#define CCM_TARGET_ROOT13 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,13) +#define CCM_TARGET_ROOT13_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,13) +#define CCM_TARGET_ROOT13_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,13) +#define CCM_TARGET_ROOT13_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,13) +#define CCM_MISC13 CCM_MISC_REG(CCM_BASE_PTR,13) +#define CCM_MISC_ROOT13_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,13) +#define CCM_MISC_ROOT13_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,13) +#define CCM_MISC_ROOT13_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,13) +#define CCM_POST13 CCM_POST_REG(CCM_BASE_PTR,13) +#define CCM_POST_ROOT13_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,13) +#define CCM_POST_ROOT13_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,13) +#define CCM_POST_ROOT13_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,13) +#define CCM_PRE13 CCM_PRE_REG(CCM_BASE_PTR,13) +#define CCM_PRE_ROOT13_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,13) +#define CCM_PRE_ROOT13_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,13) +#define CCM_PRE_ROOT13_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,13) +#define CCM_ACCESS_CTRL13 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,13) +#define CCM_ACCESS_CTRL_ROOT13_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,13) +#define CCM_ACCESS_CTRL_ROOT13_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,13) +#define CCM_ACCESS_CTRL_ROOT13_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,13) +#define CCM_TARGET_ROOT14 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,14) +#define CCM_TARGET_ROOT14_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,14) +#define CCM_TARGET_ROOT14_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,14) +#define CCM_TARGET_ROOT14_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,14) +#define CCM_MISC14 CCM_MISC_REG(CCM_BASE_PTR,14) +#define CCM_MISC_ROOT14_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,14) +#define CCM_MISC_ROOT14_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,14) +#define CCM_MISC_ROOT14_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,14) +#define CCM_POST14 CCM_POST_REG(CCM_BASE_PTR,14) +#define CCM_POST_ROOT14_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,14) +#define CCM_POST_ROOT14_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,14) +#define CCM_POST_ROOT14_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,14) +#define CCM_PRE14 CCM_PRE_REG(CCM_BASE_PTR,14) +#define CCM_PRE_ROOT14_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,14) +#define CCM_PRE_ROOT14_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,14) +#define CCM_PRE_ROOT14_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,14) +#define CCM_ACCESS_CTRL14 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,14) +#define CCM_ACCESS_CTRL_ROOT14_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,14) +#define CCM_ACCESS_CTRL_ROOT14_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,14) +#define CCM_ACCESS_CTRL_ROOT14_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,14) +#define CCM_TARGET_ROOT15 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,15) +#define CCM_TARGET_ROOT15_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,15) +#define CCM_TARGET_ROOT15_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,15) +#define CCM_TARGET_ROOT15_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,15) +#define CCM_MISC15 CCM_MISC_REG(CCM_BASE_PTR,15) +#define CCM_MISC_ROOT15_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,15) +#define CCM_MISC_ROOT15_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,15) +#define CCM_MISC_ROOT15_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,15) +#define CCM_POST15 CCM_POST_REG(CCM_BASE_PTR,15) +#define CCM_POST_ROOT15_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,15) +#define CCM_POST_ROOT15_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,15) +#define CCM_POST_ROOT15_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,15) +#define CCM_PRE15 CCM_PRE_REG(CCM_BASE_PTR,15) +#define CCM_PRE_ROOT15_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,15) +#define CCM_PRE_ROOT15_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,15) +#define CCM_PRE_ROOT15_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,15) +#define CCM_ACCESS_CTRL15 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,15) +#define CCM_ACCESS_CTRL_ROOT15_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,15) +#define CCM_ACCESS_CTRL_ROOT15_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,15) +#define CCM_ACCESS_CTRL_ROOT15_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,15) +#define CCM_TARGET_ROOT16 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,16) +#define CCM_TARGET_ROOT16_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,16) +#define CCM_TARGET_ROOT16_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,16) +#define CCM_TARGET_ROOT16_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,16) +#define CCM_MISC16 CCM_MISC_REG(CCM_BASE_PTR,16) +#define CCM_MISC_ROOT16_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,16) +#define CCM_MISC_ROOT16_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,16) +#define CCM_MISC_ROOT16_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,16) +#define CCM_POST16 CCM_POST_REG(CCM_BASE_PTR,16) +#define CCM_POST_ROOT16_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,16) +#define CCM_POST_ROOT16_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,16) +#define CCM_POST_ROOT16_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,16) +#define CCM_PRE16 CCM_PRE_REG(CCM_BASE_PTR,16) +#define CCM_PRE_ROOT16_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,16) +#define CCM_PRE_ROOT16_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,16) +#define CCM_PRE_ROOT16_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,16) +#define CCM_ACCESS_CTRL16 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,16) +#define CCM_ACCESS_CTRL_ROOT16_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,16) +#define CCM_ACCESS_CTRL_ROOT16_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,16) +#define CCM_ACCESS_CTRL_ROOT16_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,16) +#define CCM_TARGET_ROOT17 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,17) +#define CCM_TARGET_ROOT17_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,17) +#define CCM_TARGET_ROOT17_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,17) +#define CCM_TARGET_ROOT17_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,17) +#define CCM_MISC17 CCM_MISC_REG(CCM_BASE_PTR,17) +#define CCM_MISC_ROOT17_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,17) +#define CCM_MISC_ROOT17_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,17) +#define CCM_MISC_ROOT17_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,17) +#define CCM_POST17 CCM_POST_REG(CCM_BASE_PTR,17) +#define CCM_POST_ROOT17_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,17) +#define CCM_POST_ROOT17_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,17) +#define CCM_POST_ROOT17_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,17) +#define CCM_PRE17 CCM_PRE_REG(CCM_BASE_PTR,17) +#define CCM_PRE_ROOT17_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,17) +#define CCM_PRE_ROOT17_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,17) +#define CCM_PRE_ROOT17_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,17) +#define CCM_ACCESS_CTRL17 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,17) +#define CCM_ACCESS_CTRL_ROOT17_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,17) +#define CCM_ACCESS_CTRL_ROOT17_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,17) +#define CCM_ACCESS_CTRL_ROOT17_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,17) +#define CCM_TARGET_ROOT18 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,18) +#define CCM_TARGET_ROOT18_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,18) +#define CCM_TARGET_ROOT18_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,18) +#define CCM_TARGET_ROOT18_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,18) +#define CCM_MISC18 CCM_MISC_REG(CCM_BASE_PTR,18) +#define CCM_MISC_ROOT18_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,18) +#define CCM_MISC_ROOT18_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,18) +#define CCM_MISC_ROOT18_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,18) +#define CCM_POST18 CCM_POST_REG(CCM_BASE_PTR,18) +#define CCM_POST_ROOT18_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,18) +#define CCM_POST_ROOT18_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,18) +#define CCM_POST_ROOT18_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,18) +#define CCM_PRE18 CCM_PRE_REG(CCM_BASE_PTR,18) +#define CCM_PRE_ROOT18_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,18) +#define CCM_PRE_ROOT18_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,18) +#define CCM_PRE_ROOT18_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,18) +#define CCM_ACCESS_CTRL18 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,18) +#define CCM_ACCESS_CTRL_ROOT18_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,18) +#define CCM_ACCESS_CTRL_ROOT18_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,18) +#define CCM_ACCESS_CTRL_ROOT18_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,18) +#define CCM_TARGET_ROOT19 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,19) +#define CCM_TARGET_ROOT19_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,19) +#define CCM_TARGET_ROOT19_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,19) +#define CCM_TARGET_ROOT19_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,19) +#define CCM_MISC19 CCM_MISC_REG(CCM_BASE_PTR,19) +#define CCM_MISC_ROOT19_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,19) +#define CCM_MISC_ROOT19_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,19) +#define CCM_MISC_ROOT19_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,19) +#define CCM_POST19 CCM_POST_REG(CCM_BASE_PTR,19) +#define CCM_POST_ROOT19_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,19) +#define CCM_POST_ROOT19_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,19) +#define CCM_POST_ROOT19_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,19) +#define CCM_PRE19 CCM_PRE_REG(CCM_BASE_PTR,19) +#define CCM_PRE_ROOT19_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,19) +#define CCM_PRE_ROOT19_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,19) +#define CCM_PRE_ROOT19_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,19) +#define CCM_ACCESS_CTRL19 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,19) +#define CCM_ACCESS_CTRL_ROOT19_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,19) +#define CCM_ACCESS_CTRL_ROOT19_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,19) +#define CCM_ACCESS_CTRL_ROOT19_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,19) +#define CCM_TARGET_ROOT20 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,20) +#define CCM_TARGET_ROOT20_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,20) +#define CCM_TARGET_ROOT20_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,20) +#define CCM_TARGET_ROOT20_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,20) +#define CCM_MISC20 CCM_MISC_REG(CCM_BASE_PTR,20) +#define CCM_MISC_ROOT20_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,20) +#define CCM_MISC_ROOT20_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,20) +#define CCM_MISC_ROOT20_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,20) +#define CCM_POST20 CCM_POST_REG(CCM_BASE_PTR,20) +#define CCM_POST_ROOT20_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,20) +#define CCM_POST_ROOT20_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,20) +#define CCM_POST_ROOT20_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,20) +#define CCM_PRE20 CCM_PRE_REG(CCM_BASE_PTR,20) +#define CCM_PRE_ROOT20_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,20) +#define CCM_PRE_ROOT20_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,20) +#define CCM_PRE_ROOT20_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,20) +#define CCM_ACCESS_CTRL20 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,20) +#define CCM_ACCESS_CTRL_ROOT20_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,20) +#define CCM_ACCESS_CTRL_ROOT20_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,20) +#define CCM_ACCESS_CTRL_ROOT20_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,20) +#define CCM_TARGET_ROOT21 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,21) +#define CCM_TARGET_ROOT21_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,21) +#define CCM_TARGET_ROOT21_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,21) +#define CCM_TARGET_ROOT21_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,21) +#define CCM_MISC21 CCM_MISC_REG(CCM_BASE_PTR,21) +#define CCM_MISC_ROOT21_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,21) +#define CCM_MISC_ROOT21_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,21) +#define CCM_MISC_ROOT21_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,21) +#define CCM_POST21 CCM_POST_REG(CCM_BASE_PTR,21) +#define CCM_POST_ROOT21_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,21) +#define CCM_POST_ROOT21_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,21) +#define CCM_POST_ROOT21_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,21) +#define CCM_PRE21 CCM_PRE_REG(CCM_BASE_PTR,21) +#define CCM_PRE_ROOT21_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,21) +#define CCM_PRE_ROOT21_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,21) +#define CCM_PRE_ROOT21_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,21) +#define CCM_ACCESS_CTRL21 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,21) +#define CCM_ACCESS_CTRL_ROOT21_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,21) +#define CCM_ACCESS_CTRL_ROOT21_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,21) +#define CCM_ACCESS_CTRL_ROOT21_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,21) +#define CCM_TARGET_ROOT22 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,22) +#define CCM_TARGET_ROOT22_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,22) +#define CCM_TARGET_ROOT22_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,22) +#define CCM_TARGET_ROOT22_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,22) +#define CCM_MISC22 CCM_MISC_REG(CCM_BASE_PTR,22) +#define CCM_MISC_ROOT22_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,22) +#define CCM_MISC_ROOT22_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,22) +#define CCM_MISC_ROOT22_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,22) +#define CCM_POST22 CCM_POST_REG(CCM_BASE_PTR,22) +#define CCM_POST_ROOT22_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,22) +#define CCM_POST_ROOT22_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,22) +#define CCM_POST_ROOT22_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,22) +#define CCM_PRE22 CCM_PRE_REG(CCM_BASE_PTR,22) +#define CCM_PRE_ROOT22_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,22) +#define CCM_PRE_ROOT22_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,22) +#define CCM_PRE_ROOT22_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,22) +#define CCM_ACCESS_CTRL22 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,22) +#define CCM_ACCESS_CTRL_ROOT22_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,22) +#define CCM_ACCESS_CTRL_ROOT22_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,22) +#define CCM_ACCESS_CTRL_ROOT22_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,22) +#define CCM_TARGET_ROOT23 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,23) +#define CCM_TARGET_ROOT23_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,23) +#define CCM_TARGET_ROOT23_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,23) +#define CCM_TARGET_ROOT23_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,23) +#define CCM_MISC23 CCM_MISC_REG(CCM_BASE_PTR,23) +#define CCM_MISC_ROOT23_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,23) +#define CCM_MISC_ROOT23_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,23) +#define CCM_MISC_ROOT23_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,23) +#define CCM_POST23 CCM_POST_REG(CCM_BASE_PTR,23) +#define CCM_POST_ROOT23_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,23) +#define CCM_POST_ROOT23_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,23) +#define CCM_POST_ROOT23_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,23) +#define CCM_PRE23 CCM_PRE_REG(CCM_BASE_PTR,23) +#define CCM_PRE_ROOT23_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,23) +#define CCM_PRE_ROOT23_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,23) +#define CCM_PRE_ROOT23_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,23) +#define CCM_ACCESS_CTRL23 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,23) +#define CCM_ACCESS_CTRL_ROOT23_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,23) +#define CCM_ACCESS_CTRL_ROOT23_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,23) +#define CCM_ACCESS_CTRL_ROOT23_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,23) +#define CCM_TARGET_ROOT24 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,24) +#define CCM_TARGET_ROOT24_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,24) +#define CCM_TARGET_ROOT24_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,24) +#define CCM_TARGET_ROOT24_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,24) +#define CCM_MISC24 CCM_MISC_REG(CCM_BASE_PTR,24) +#define CCM_MISC_ROOT24_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,24) +#define CCM_MISC_ROOT24_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,24) +#define CCM_MISC_ROOT24_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,24) +#define CCM_POST24 CCM_POST_REG(CCM_BASE_PTR,24) +#define CCM_POST_ROOT24_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,24) +#define CCM_POST_ROOT24_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,24) +#define CCM_POST_ROOT24_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,24) +#define CCM_PRE24 CCM_PRE_REG(CCM_BASE_PTR,24) +#define CCM_PRE_ROOT24_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,24) +#define CCM_PRE_ROOT24_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,24) +#define CCM_PRE_ROOT24_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,24) +#define CCM_ACCESS_CTRL24 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,24) +#define CCM_ACCESS_CTRL_ROOT24_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,24) +#define CCM_ACCESS_CTRL_ROOT24_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,24) +#define CCM_ACCESS_CTRL_ROOT24_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,24) +#define CCM_TARGET_ROOT25 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,25) +#define CCM_TARGET_ROOT25_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,25) +#define CCM_TARGET_ROOT25_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,25) +#define CCM_TARGET_ROOT25_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,25) +#define CCM_MISC25 CCM_MISC_REG(CCM_BASE_PTR,25) +#define CCM_MISC_ROOT25_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,25) +#define CCM_MISC_ROOT25_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,25) +#define CCM_MISC_ROOT25_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,25) +#define CCM_POST25 CCM_POST_REG(CCM_BASE_PTR,25) +#define CCM_POST_ROOT25_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,25) +#define CCM_POST_ROOT25_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,25) +#define CCM_POST_ROOT25_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,25) +#define CCM_PRE25 CCM_PRE_REG(CCM_BASE_PTR,25) +#define CCM_PRE_ROOT25_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,25) +#define CCM_PRE_ROOT25_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,25) +#define CCM_PRE_ROOT25_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,25) +#define CCM_ACCESS_CTRL25 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,25) +#define CCM_ACCESS_CTRL_ROOT25_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,25) +#define CCM_ACCESS_CTRL_ROOT25_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,25) +#define CCM_ACCESS_CTRL_ROOT25_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,25) +#define CCM_TARGET_ROOT26 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,26) +#define CCM_TARGET_ROOT26_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,26) +#define CCM_TARGET_ROOT26_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,26) +#define CCM_TARGET_ROOT26_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,26) +#define CCM_MISC26 CCM_MISC_REG(CCM_BASE_PTR,26) +#define CCM_MISC_ROOT26_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,26) +#define CCM_MISC_ROOT26_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,26) +#define CCM_MISC_ROOT26_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,26) +#define CCM_POST26 CCM_POST_REG(CCM_BASE_PTR,26) +#define CCM_POST_ROOT26_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,26) +#define CCM_POST_ROOT26_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,26) +#define CCM_POST_ROOT26_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,26) +#define CCM_PRE26 CCM_PRE_REG(CCM_BASE_PTR,26) +#define CCM_PRE_ROOT26_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,26) +#define CCM_PRE_ROOT26_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,26) +#define CCM_PRE_ROOT26_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,26) +#define CCM_ACCESS_CTRL26 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,26) +#define CCM_ACCESS_CTRL_ROOT26_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,26) +#define CCM_ACCESS_CTRL_ROOT26_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,26) +#define CCM_ACCESS_CTRL_ROOT26_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,26) +#define CCM_TARGET_ROOT27 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,27) +#define CCM_TARGET_ROOT27_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,27) +#define CCM_TARGET_ROOT27_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,27) +#define CCM_TARGET_ROOT27_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,27) +#define CCM_MISC27 CCM_MISC_REG(CCM_BASE_PTR,27) +#define CCM_MISC_ROOT27_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,27) +#define CCM_MISC_ROOT27_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,27) +#define CCM_MISC_ROOT27_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,27) +#define CCM_POST27 CCM_POST_REG(CCM_BASE_PTR,27) +#define CCM_POST_ROOT27_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,27) +#define CCM_POST_ROOT27_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,27) +#define CCM_POST_ROOT27_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,27) +#define CCM_PRE27 CCM_PRE_REG(CCM_BASE_PTR,27) +#define CCM_PRE_ROOT27_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,27) +#define CCM_PRE_ROOT27_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,27) +#define CCM_PRE_ROOT27_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,27) +#define CCM_ACCESS_CTRL27 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,27) +#define CCM_ACCESS_CTRL_ROOT27_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,27) +#define CCM_ACCESS_CTRL_ROOT27_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,27) +#define CCM_ACCESS_CTRL_ROOT27_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,27) +#define CCM_TARGET_ROOT28 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,28) +#define CCM_TARGET_ROOT28_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,28) +#define CCM_TARGET_ROOT28_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,28) +#define CCM_TARGET_ROOT28_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,28) +#define CCM_MISC28 CCM_MISC_REG(CCM_BASE_PTR,28) +#define CCM_MISC_ROOT28_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,28) +#define CCM_MISC_ROOT28_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,28) +#define CCM_MISC_ROOT28_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,28) +#define CCM_POST28 CCM_POST_REG(CCM_BASE_PTR,28) +#define CCM_POST_ROOT28_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,28) +#define CCM_POST_ROOT28_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,28) +#define CCM_POST_ROOT28_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,28) +#define CCM_PRE28 CCM_PRE_REG(CCM_BASE_PTR,28) +#define CCM_PRE_ROOT28_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,28) +#define CCM_PRE_ROOT28_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,28) +#define CCM_PRE_ROOT28_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,28) +#define CCM_ACCESS_CTRL28 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,28) +#define CCM_ACCESS_CTRL_ROOT28_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,28) +#define CCM_ACCESS_CTRL_ROOT28_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,28) +#define CCM_ACCESS_CTRL_ROOT28_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,28) +#define CCM_TARGET_ROOT29 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,29) +#define CCM_TARGET_ROOT29_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,29) +#define CCM_TARGET_ROOT29_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,29) +#define CCM_TARGET_ROOT29_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,29) +#define CCM_MISC29 CCM_MISC_REG(CCM_BASE_PTR,29) +#define CCM_MISC_ROOT29_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,29) +#define CCM_MISC_ROOT29_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,29) +#define CCM_MISC_ROOT29_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,29) +#define CCM_POST29 CCM_POST_REG(CCM_BASE_PTR,29) +#define CCM_POST_ROOT29_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,29) +#define CCM_POST_ROOT29_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,29) +#define CCM_POST_ROOT29_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,29) +#define CCM_PRE29 CCM_PRE_REG(CCM_BASE_PTR,29) +#define CCM_PRE_ROOT29_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,29) +#define CCM_PRE_ROOT29_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,29) +#define CCM_PRE_ROOT29_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,29) +#define CCM_ACCESS_CTRL29 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,29) +#define CCM_ACCESS_CTRL_ROOT29_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,29) +#define CCM_ACCESS_CTRL_ROOT29_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,29) +#define CCM_ACCESS_CTRL_ROOT29_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,29) +#define CCM_TARGET_ROOT30 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,30) +#define CCM_TARGET_ROOT30_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,30) +#define CCM_TARGET_ROOT30_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,30) +#define CCM_TARGET_ROOT30_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,30) +#define CCM_MISC30 CCM_MISC_REG(CCM_BASE_PTR,30) +#define CCM_MISC_ROOT30_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,30) +#define CCM_MISC_ROOT30_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,30) +#define CCM_MISC_ROOT30_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,30) +#define CCM_POST30 CCM_POST_REG(CCM_BASE_PTR,30) +#define CCM_POST_ROOT30_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,30) +#define CCM_POST_ROOT30_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,30) +#define CCM_POST_ROOT30_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,30) +#define CCM_PRE30 CCM_PRE_REG(CCM_BASE_PTR,30) +#define CCM_PRE_ROOT30_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,30) +#define CCM_PRE_ROOT30_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,30) +#define CCM_PRE_ROOT30_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,30) +#define CCM_ACCESS_CTRL30 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,30) +#define CCM_ACCESS_CTRL_ROOT30_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,30) +#define CCM_ACCESS_CTRL_ROOT30_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,30) +#define CCM_ACCESS_CTRL_ROOT30_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,30) +#define CCM_TARGET_ROOT31 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,31) +#define CCM_TARGET_ROOT31_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,31) +#define CCM_TARGET_ROOT31_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,31) +#define CCM_TARGET_ROOT31_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,31) +#define CCM_MISC31 CCM_MISC_REG(CCM_BASE_PTR,31) +#define CCM_MISC_ROOT31_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,31) +#define CCM_MISC_ROOT31_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,31) +#define CCM_MISC_ROOT31_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,31) +#define CCM_POST31 CCM_POST_REG(CCM_BASE_PTR,31) +#define CCM_POST_ROOT31_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,31) +#define CCM_POST_ROOT31_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,31) +#define CCM_POST_ROOT31_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,31) +#define CCM_PRE31 CCM_PRE_REG(CCM_BASE_PTR,31) +#define CCM_PRE_ROOT31_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,31) +#define CCM_PRE_ROOT31_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,31) +#define CCM_PRE_ROOT31_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,31) +#define CCM_ACCESS_CTRL31 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,31) +#define CCM_ACCESS_CTRL_ROOT31_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,31) +#define CCM_ACCESS_CTRL_ROOT31_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,31) +#define CCM_ACCESS_CTRL_ROOT31_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,31) +#define CCM_TARGET_ROOT32 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,32) +#define CCM_TARGET_ROOT32_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,32) +#define CCM_TARGET_ROOT32_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,32) +#define CCM_TARGET_ROOT32_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,32) +#define CCM_MISC32 CCM_MISC_REG(CCM_BASE_PTR,32) +#define CCM_MISC_ROOT32_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,32) +#define CCM_MISC_ROOT32_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,32) +#define CCM_MISC_ROOT32_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,32) +#define CCM_POST32 CCM_POST_REG(CCM_BASE_PTR,32) +#define CCM_POST_ROOT32_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,32) +#define CCM_POST_ROOT32_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,32) +#define CCM_POST_ROOT32_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,32) +#define CCM_PRE32 CCM_PRE_REG(CCM_BASE_PTR,32) +#define CCM_PRE_ROOT32_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,32) +#define CCM_PRE_ROOT32_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,32) +#define CCM_PRE_ROOT32_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,32) +#define CCM_ACCESS_CTRL32 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,32) +#define CCM_ACCESS_CTRL_ROOT32_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,32) +#define CCM_ACCESS_CTRL_ROOT32_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,32) +#define CCM_ACCESS_CTRL_ROOT32_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,32) +#define CCM_TARGET_ROOT33 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,33) +#define CCM_TARGET_ROOT33_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,33) +#define CCM_TARGET_ROOT33_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,33) +#define CCM_TARGET_ROOT33_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,33) +#define CCM_MISC33 CCM_MISC_REG(CCM_BASE_PTR,33) +#define CCM_MISC_ROOT33_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,33) +#define CCM_MISC_ROOT33_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,33) +#define CCM_MISC_ROOT33_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,33) +#define CCM_POST33 CCM_POST_REG(CCM_BASE_PTR,33) +#define CCM_POST_ROOT33_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,33) +#define CCM_POST_ROOT33_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,33) +#define CCM_POST_ROOT33_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,33) +#define CCM_PRE33 CCM_PRE_REG(CCM_BASE_PTR,33) +#define CCM_PRE_ROOT33_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,33) +#define CCM_PRE_ROOT33_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,33) +#define CCM_PRE_ROOT33_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,33) +#define CCM_ACCESS_CTRL33 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,33) +#define CCM_ACCESS_CTRL_ROOT33_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,33) +#define CCM_ACCESS_CTRL_ROOT33_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,33) +#define CCM_ACCESS_CTRL_ROOT33_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,33) +#define CCM_TARGET_ROOT34 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,34) +#define CCM_TARGET_ROOT34_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,34) +#define CCM_TARGET_ROOT34_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,34) +#define CCM_TARGET_ROOT34_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,34) +#define CCM_MISC34 CCM_MISC_REG(CCM_BASE_PTR,34) +#define CCM_MISC_ROOT34_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,34) +#define CCM_MISC_ROOT34_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,34) +#define CCM_MISC_ROOT34_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,34) +#define CCM_POST34 CCM_POST_REG(CCM_BASE_PTR,34) +#define CCM_POST_ROOT34_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,34) +#define CCM_POST_ROOT34_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,34) +#define CCM_POST_ROOT34_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,34) +#define CCM_PRE34 CCM_PRE_REG(CCM_BASE_PTR,34) +#define CCM_PRE_ROOT34_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,34) +#define CCM_PRE_ROOT34_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,34) +#define CCM_PRE_ROOT34_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,34) +#define CCM_ACCESS_CTRL34 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,34) +#define CCM_ACCESS_CTRL_ROOT34_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,34) +#define CCM_ACCESS_CTRL_ROOT34_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,34) +#define CCM_ACCESS_CTRL_ROOT34_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,34) +#define CCM_TARGET_ROOT35 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,35) +#define CCM_TARGET_ROOT35_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,35) +#define CCM_TARGET_ROOT35_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,35) +#define CCM_TARGET_ROOT35_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,35) +#define CCM_MISC35 CCM_MISC_REG(CCM_BASE_PTR,35) +#define CCM_MISC_ROOT35_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,35) +#define CCM_MISC_ROOT35_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,35) +#define CCM_MISC_ROOT35_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,35) +#define CCM_POST35 CCM_POST_REG(CCM_BASE_PTR,35) +#define CCM_POST_ROOT35_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,35) +#define CCM_POST_ROOT35_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,35) +#define CCM_POST_ROOT35_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,35) +#define CCM_PRE35 CCM_PRE_REG(CCM_BASE_PTR,35) +#define CCM_PRE_ROOT35_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,35) +#define CCM_PRE_ROOT35_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,35) +#define CCM_PRE_ROOT35_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,35) +#define CCM_ACCESS_CTRL35 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,35) +#define CCM_ACCESS_CTRL_ROOT35_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,35) +#define CCM_ACCESS_CTRL_ROOT35_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,35) +#define CCM_ACCESS_CTRL_ROOT35_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,35) +#define CCM_TARGET_ROOT36 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,36) +#define CCM_TARGET_ROOT36_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,36) +#define CCM_TARGET_ROOT36_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,36) +#define CCM_TARGET_ROOT36_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,36) +#define CCM_MISC36 CCM_MISC_REG(CCM_BASE_PTR,36) +#define CCM_MISC_ROOT36_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,36) +#define CCM_MISC_ROOT36_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,36) +#define CCM_MISC_ROOT36_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,36) +#define CCM_POST36 CCM_POST_REG(CCM_BASE_PTR,36) +#define CCM_POST_ROOT36_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,36) +#define CCM_POST_ROOT36_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,36) +#define CCM_POST_ROOT36_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,36) +#define CCM_PRE36 CCM_PRE_REG(CCM_BASE_PTR,36) +#define CCM_PRE_ROOT36_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,36) +#define CCM_PRE_ROOT36_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,36) +#define CCM_PRE_ROOT36_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,36) +#define CCM_ACCESS_CTRL36 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,36) +#define CCM_ACCESS_CTRL_ROOT36_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,36) +#define CCM_ACCESS_CTRL_ROOT36_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,36) +#define CCM_ACCESS_CTRL_ROOT36_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,36) +#define CCM_TARGET_ROOT37 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,37) +#define CCM_TARGET_ROOT37_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,37) +#define CCM_TARGET_ROOT37_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,37) +#define CCM_TARGET_ROOT37_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,37) +#define CCM_MISC37 CCM_MISC_REG(CCM_BASE_PTR,37) +#define CCM_MISC_ROOT37_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,37) +#define CCM_MISC_ROOT37_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,37) +#define CCM_MISC_ROOT37_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,37) +#define CCM_POST37 CCM_POST_REG(CCM_BASE_PTR,37) +#define CCM_POST_ROOT37_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,37) +#define CCM_POST_ROOT37_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,37) +#define CCM_POST_ROOT37_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,37) +#define CCM_PRE37 CCM_PRE_REG(CCM_BASE_PTR,37) +#define CCM_PRE_ROOT37_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,37) +#define CCM_PRE_ROOT37_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,37) +#define CCM_PRE_ROOT37_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,37) +#define CCM_ACCESS_CTRL37 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,37) +#define CCM_ACCESS_CTRL_ROOT37_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,37) +#define CCM_ACCESS_CTRL_ROOT37_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,37) +#define CCM_ACCESS_CTRL_ROOT37_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,37) +#define CCM_TARGET_ROOT38 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,38) +#define CCM_TARGET_ROOT38_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,38) +#define CCM_TARGET_ROOT38_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,38) +#define CCM_TARGET_ROOT38_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,38) +#define CCM_MISC38 CCM_MISC_REG(CCM_BASE_PTR,38) +#define CCM_MISC_ROOT38_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,38) +#define CCM_MISC_ROOT38_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,38) +#define CCM_MISC_ROOT38_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,38) +#define CCM_POST38 CCM_POST_REG(CCM_BASE_PTR,38) +#define CCM_POST_ROOT38_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,38) +#define CCM_POST_ROOT38_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,38) +#define CCM_POST_ROOT38_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,38) +#define CCM_PRE38 CCM_PRE_REG(CCM_BASE_PTR,38) +#define CCM_PRE_ROOT38_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,38) +#define CCM_PRE_ROOT38_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,38) +#define CCM_PRE_ROOT38_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,38) +#define CCM_ACCESS_CTRL38 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,38) +#define CCM_ACCESS_CTRL_ROOT38_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,38) +#define CCM_ACCESS_CTRL_ROOT38_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,38) +#define CCM_ACCESS_CTRL_ROOT38_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,38) +#define CCM_TARGET_ROOT39 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,39) +#define CCM_TARGET_ROOT39_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,39) +#define CCM_TARGET_ROOT39_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,39) +#define CCM_TARGET_ROOT39_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,39) +#define CCM_MISC39 CCM_MISC_REG(CCM_BASE_PTR,39) +#define CCM_MISC_ROOT39_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,39) +#define CCM_MISC_ROOT39_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,39) +#define CCM_MISC_ROOT39_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,39) +#define CCM_POST39 CCM_POST_REG(CCM_BASE_PTR,39) +#define CCM_POST_ROOT39_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,39) +#define CCM_POST_ROOT39_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,39) +#define CCM_POST_ROOT39_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,39) +#define CCM_PRE39 CCM_PRE_REG(CCM_BASE_PTR,39) +#define CCM_PRE_ROOT39_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,39) +#define CCM_PRE_ROOT39_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,39) +#define CCM_PRE_ROOT39_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,39) +#define CCM_ACCESS_CTRL39 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,39) +#define CCM_ACCESS_CTRL_ROOT39_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,39) +#define CCM_ACCESS_CTRL_ROOT39_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,39) +#define CCM_ACCESS_CTRL_ROOT39_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,39) +#define CCM_TARGET_ROOT40 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,40) +#define CCM_TARGET_ROOT40_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,40) +#define CCM_TARGET_ROOT40_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,40) +#define CCM_TARGET_ROOT40_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,40) +#define CCM_MISC40 CCM_MISC_REG(CCM_BASE_PTR,40) +#define CCM_MISC_ROOT40_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,40) +#define CCM_MISC_ROOT40_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,40) +#define CCM_MISC_ROOT40_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,40) +#define CCM_POST40 CCM_POST_REG(CCM_BASE_PTR,40) +#define CCM_POST_ROOT40_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,40) +#define CCM_POST_ROOT40_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,40) +#define CCM_POST_ROOT40_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,40) +#define CCM_PRE40 CCM_PRE_REG(CCM_BASE_PTR,40) +#define CCM_PRE_ROOT40_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,40) +#define CCM_PRE_ROOT40_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,40) +#define CCM_PRE_ROOT40_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,40) +#define CCM_ACCESS_CTRL40 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,40) +#define CCM_ACCESS_CTRL_ROOT40_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,40) +#define CCM_ACCESS_CTRL_ROOT40_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,40) +#define CCM_ACCESS_CTRL_ROOT40_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,40) +#define CCM_TARGET_ROOT41 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,41) +#define CCM_TARGET_ROOT41_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,41) +#define CCM_TARGET_ROOT41_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,41) +#define CCM_TARGET_ROOT41_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,41) +#define CCM_MISC41 CCM_MISC_REG(CCM_BASE_PTR,41) +#define CCM_MISC_ROOT41_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,41) +#define CCM_MISC_ROOT41_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,41) +#define CCM_MISC_ROOT41_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,41) +#define CCM_POST41 CCM_POST_REG(CCM_BASE_PTR,41) +#define CCM_POST_ROOT41_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,41) +#define CCM_POST_ROOT41_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,41) +#define CCM_POST_ROOT41_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,41) +#define CCM_PRE41 CCM_PRE_REG(CCM_BASE_PTR,41) +#define CCM_PRE_ROOT41_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,41) +#define CCM_PRE_ROOT41_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,41) +#define CCM_PRE_ROOT41_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,41) +#define CCM_ACCESS_CTRL41 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,41) +#define CCM_ACCESS_CTRL_ROOT41_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,41) +#define CCM_ACCESS_CTRL_ROOT41_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,41) +#define CCM_ACCESS_CTRL_ROOT41_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,41) +#define CCM_TARGET_ROOT42 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,42) +#define CCM_TARGET_ROOT42_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,42) +#define CCM_TARGET_ROOT42_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,42) +#define CCM_TARGET_ROOT42_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,42) +#define CCM_MISC42 CCM_MISC_REG(CCM_BASE_PTR,42) +#define CCM_MISC_ROOT42_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,42) +#define CCM_MISC_ROOT42_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,42) +#define CCM_MISC_ROOT42_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,42) +#define CCM_POST42 CCM_POST_REG(CCM_BASE_PTR,42) +#define CCM_POST_ROOT42_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,42) +#define CCM_POST_ROOT42_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,42) +#define CCM_POST_ROOT42_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,42) +#define CCM_PRE42 CCM_PRE_REG(CCM_BASE_PTR,42) +#define CCM_PRE_ROOT42_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,42) +#define CCM_PRE_ROOT42_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,42) +#define CCM_PRE_ROOT42_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,42) +#define CCM_ACCESS_CTRL42 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,42) +#define CCM_ACCESS_CTRL_ROOT42_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,42) +#define CCM_ACCESS_CTRL_ROOT42_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,42) +#define CCM_ACCESS_CTRL_ROOT42_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,42) +#define CCM_TARGET_ROOT43 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,43) +#define CCM_TARGET_ROOT43_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,43) +#define CCM_TARGET_ROOT43_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,43) +#define CCM_TARGET_ROOT43_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,43) +#define CCM_MISC43 CCM_MISC_REG(CCM_BASE_PTR,43) +#define CCM_MISC_ROOT43_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,43) +#define CCM_MISC_ROOT43_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,43) +#define CCM_MISC_ROOT43_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,43) +#define CCM_POST43 CCM_POST_REG(CCM_BASE_PTR,43) +#define CCM_POST_ROOT43_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,43) +#define CCM_POST_ROOT43_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,43) +#define CCM_POST_ROOT43_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,43) +#define CCM_PRE43 CCM_PRE_REG(CCM_BASE_PTR,43) +#define CCM_PRE_ROOT43_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,43) +#define CCM_PRE_ROOT43_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,43) +#define CCM_PRE_ROOT43_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,43) +#define CCM_ACCESS_CTRL43 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,43) +#define CCM_ACCESS_CTRL_ROOT43_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,43) +#define CCM_ACCESS_CTRL_ROOT43_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,43) +#define CCM_ACCESS_CTRL_ROOT43_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,43) +#define CCM_TARGET_ROOT44 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,44) +#define CCM_TARGET_ROOT44_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,44) +#define CCM_TARGET_ROOT44_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,44) +#define CCM_TARGET_ROOT44_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,44) +#define CCM_MISC44 CCM_MISC_REG(CCM_BASE_PTR,44) +#define CCM_MISC_ROOT44_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,44) +#define CCM_MISC_ROOT44_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,44) +#define CCM_MISC_ROOT44_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,44) +#define CCM_POST44 CCM_POST_REG(CCM_BASE_PTR,44) +#define CCM_POST_ROOT44_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,44) +#define CCM_POST_ROOT44_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,44) +#define CCM_POST_ROOT44_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,44) +#define CCM_PRE44 CCM_PRE_REG(CCM_BASE_PTR,44) +#define CCM_PRE_ROOT44_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,44) +#define CCM_PRE_ROOT44_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,44) +#define CCM_PRE_ROOT44_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,44) +#define CCM_ACCESS_CTRL44 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,44) +#define CCM_ACCESS_CTRL_ROOT44_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,44) +#define CCM_ACCESS_CTRL_ROOT44_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,44) +#define CCM_ACCESS_CTRL_ROOT44_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,44) +#define CCM_TARGET_ROOT45 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,45) +#define CCM_TARGET_ROOT45_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,45) +#define CCM_TARGET_ROOT45_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,45) +#define CCM_TARGET_ROOT45_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,45) +#define CCM_MISC45 CCM_MISC_REG(CCM_BASE_PTR,45) +#define CCM_MISC_ROOT45_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,45) +#define CCM_MISC_ROOT45_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,45) +#define CCM_MISC_ROOT45_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,45) +#define CCM_POST45 CCM_POST_REG(CCM_BASE_PTR,45) +#define CCM_POST_ROOT45_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,45) +#define CCM_POST_ROOT45_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,45) +#define CCM_POST_ROOT45_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,45) +#define CCM_PRE45 CCM_PRE_REG(CCM_BASE_PTR,45) +#define CCM_PRE_ROOT45_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,45) +#define CCM_PRE_ROOT45_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,45) +#define CCM_PRE_ROOT45_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,45) +#define CCM_ACCESS_CTRL45 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,45) +#define CCM_ACCESS_CTRL_ROOT45_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,45) +#define CCM_ACCESS_CTRL_ROOT45_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,45) +#define CCM_ACCESS_CTRL_ROOT45_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,45) +#define CCM_TARGET_ROOT46 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,46) +#define CCM_TARGET_ROOT46_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,46) +#define CCM_TARGET_ROOT46_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,46) +#define CCM_TARGET_ROOT46_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,46) +#define CCM_MISC46 CCM_MISC_REG(CCM_BASE_PTR,46) +#define CCM_MISC_ROOT46_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,46) +#define CCM_MISC_ROOT46_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,46) +#define CCM_MISC_ROOT46_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,46) +#define CCM_POST46 CCM_POST_REG(CCM_BASE_PTR,46) +#define CCM_POST_ROOT46_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,46) +#define CCM_POST_ROOT46_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,46) +#define CCM_POST_ROOT46_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,46) +#define CCM_PRE46 CCM_PRE_REG(CCM_BASE_PTR,46) +#define CCM_PRE_ROOT46_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,46) +#define CCM_PRE_ROOT46_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,46) +#define CCM_PRE_ROOT46_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,46) +#define CCM_ACCESS_CTRL46 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,46) +#define CCM_ACCESS_CTRL_ROOT46_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,46) +#define CCM_ACCESS_CTRL_ROOT46_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,46) +#define CCM_ACCESS_CTRL_ROOT46_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,46) +#define CCM_TARGET_ROOT47 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,47) +#define CCM_TARGET_ROOT47_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,47) +#define CCM_TARGET_ROOT47_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,47) +#define CCM_TARGET_ROOT47_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,47) +#define CCM_MISC47 CCM_MISC_REG(CCM_BASE_PTR,47) +#define CCM_MISC_ROOT47_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,47) +#define CCM_MISC_ROOT47_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,47) +#define CCM_MISC_ROOT47_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,47) +#define CCM_POST47 CCM_POST_REG(CCM_BASE_PTR,47) +#define CCM_POST_ROOT47_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,47) +#define CCM_POST_ROOT47_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,47) +#define CCM_POST_ROOT47_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,47) +#define CCM_PRE47 CCM_PRE_REG(CCM_BASE_PTR,47) +#define CCM_PRE_ROOT47_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,47) +#define CCM_PRE_ROOT47_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,47) +#define CCM_PRE_ROOT47_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,47) +#define CCM_ACCESS_CTRL47 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,47) +#define CCM_ACCESS_CTRL_ROOT47_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,47) +#define CCM_ACCESS_CTRL_ROOT47_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,47) +#define CCM_ACCESS_CTRL_ROOT47_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,47) +#define CCM_TARGET_ROOT48 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,48) +#define CCM_TARGET_ROOT48_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,48) +#define CCM_TARGET_ROOT48_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,48) +#define CCM_TARGET_ROOT48_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,48) +#define CCM_MISC48 CCM_MISC_REG(CCM_BASE_PTR,48) +#define CCM_MISC_ROOT48_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,48) +#define CCM_MISC_ROOT48_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,48) +#define CCM_MISC_ROOT48_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,48) +#define CCM_POST48 CCM_POST_REG(CCM_BASE_PTR,48) +#define CCM_POST_ROOT48_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,48) +#define CCM_POST_ROOT48_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,48) +#define CCM_POST_ROOT48_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,48) +#define CCM_PRE48 CCM_PRE_REG(CCM_BASE_PTR,48) +#define CCM_PRE_ROOT48_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,48) +#define CCM_PRE_ROOT48_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,48) +#define CCM_PRE_ROOT48_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,48) +#define CCM_ACCESS_CTRL48 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,48) +#define CCM_ACCESS_CTRL_ROOT48_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,48) +#define CCM_ACCESS_CTRL_ROOT48_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,48) +#define CCM_ACCESS_CTRL_ROOT48_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,48) +#define CCM_TARGET_ROOT49 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,49) +#define CCM_TARGET_ROOT49_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,49) +#define CCM_TARGET_ROOT49_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,49) +#define CCM_TARGET_ROOT49_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,49) +#define CCM_MISC49 CCM_MISC_REG(CCM_BASE_PTR,49) +#define CCM_MISC_ROOT49_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,49) +#define CCM_MISC_ROOT49_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,49) +#define CCM_MISC_ROOT49_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,49) +#define CCM_POST49 CCM_POST_REG(CCM_BASE_PTR,49) +#define CCM_POST_ROOT49_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,49) +#define CCM_POST_ROOT49_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,49) +#define CCM_POST_ROOT49_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,49) +#define CCM_PRE49 CCM_PRE_REG(CCM_BASE_PTR,49) +#define CCM_PRE_ROOT49_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,49) +#define CCM_PRE_ROOT49_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,49) +#define CCM_PRE_ROOT49_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,49) +#define CCM_ACCESS_CTRL49 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,49) +#define CCM_ACCESS_CTRL_ROOT49_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,49) +#define CCM_ACCESS_CTRL_ROOT49_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,49) +#define CCM_ACCESS_CTRL_ROOT49_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,49) +#define CCM_TARGET_ROOT50 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,50) +#define CCM_TARGET_ROOT50_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,50) +#define CCM_TARGET_ROOT50_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,50) +#define CCM_TARGET_ROOT50_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,50) +#define CCM_MISC50 CCM_MISC_REG(CCM_BASE_PTR,50) +#define CCM_MISC_ROOT50_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,50) +#define CCM_MISC_ROOT50_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,50) +#define CCM_MISC_ROOT50_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,50) +#define CCM_POST50 CCM_POST_REG(CCM_BASE_PTR,50) +#define CCM_POST_ROOT50_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,50) +#define CCM_POST_ROOT50_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,50) +#define CCM_POST_ROOT50_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,50) +#define CCM_PRE50 CCM_PRE_REG(CCM_BASE_PTR,50) +#define CCM_PRE_ROOT50_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,50) +#define CCM_PRE_ROOT50_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,50) +#define CCM_PRE_ROOT50_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,50) +#define CCM_ACCESS_CTRL50 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,50) +#define CCM_ACCESS_CTRL_ROOT50_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,50) +#define CCM_ACCESS_CTRL_ROOT50_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,50) +#define CCM_ACCESS_CTRL_ROOT50_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,50) +#define CCM_TARGET_ROOT51 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,51) +#define CCM_TARGET_ROOT51_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,51) +#define CCM_TARGET_ROOT51_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,51) +#define CCM_TARGET_ROOT51_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,51) +#define CCM_MISC51 CCM_MISC_REG(CCM_BASE_PTR,51) +#define CCM_MISC_ROOT51_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,51) +#define CCM_MISC_ROOT51_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,51) +#define CCM_MISC_ROOT51_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,51) +#define CCM_POST51 CCM_POST_REG(CCM_BASE_PTR,51) +#define CCM_POST_ROOT51_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,51) +#define CCM_POST_ROOT51_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,51) +#define CCM_POST_ROOT51_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,51) +#define CCM_PRE51 CCM_PRE_REG(CCM_BASE_PTR,51) +#define CCM_PRE_ROOT51_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,51) +#define CCM_PRE_ROOT51_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,51) +#define CCM_PRE_ROOT51_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,51) +#define CCM_ACCESS_CTRL51 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,51) +#define CCM_ACCESS_CTRL_ROOT51_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,51) +#define CCM_ACCESS_CTRL_ROOT51_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,51) +#define CCM_ACCESS_CTRL_ROOT51_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,51) +#define CCM_TARGET_ROOT52 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,52) +#define CCM_TARGET_ROOT52_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,52) +#define CCM_TARGET_ROOT52_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,52) +#define CCM_TARGET_ROOT52_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,52) +#define CCM_MISC52 CCM_MISC_REG(CCM_BASE_PTR,52) +#define CCM_MISC_ROOT52_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,52) +#define CCM_MISC_ROOT52_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,52) +#define CCM_MISC_ROOT52_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,52) +#define CCM_POST52 CCM_POST_REG(CCM_BASE_PTR,52) +#define CCM_POST_ROOT52_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,52) +#define CCM_POST_ROOT52_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,52) +#define CCM_POST_ROOT52_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,52) +#define CCM_PRE52 CCM_PRE_REG(CCM_BASE_PTR,52) +#define CCM_PRE_ROOT52_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,52) +#define CCM_PRE_ROOT52_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,52) +#define CCM_PRE_ROOT52_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,52) +#define CCM_ACCESS_CTRL52 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,52) +#define CCM_ACCESS_CTRL_ROOT52_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,52) +#define CCM_ACCESS_CTRL_ROOT52_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,52) +#define CCM_ACCESS_CTRL_ROOT52_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,52) +#define CCM_TARGET_ROOT53 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,53) +#define CCM_TARGET_ROOT53_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,53) +#define CCM_TARGET_ROOT53_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,53) +#define CCM_TARGET_ROOT53_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,53) +#define CCM_MISC53 CCM_MISC_REG(CCM_BASE_PTR,53) +#define CCM_MISC_ROOT53_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,53) +#define CCM_MISC_ROOT53_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,53) +#define CCM_MISC_ROOT53_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,53) +#define CCM_POST53 CCM_POST_REG(CCM_BASE_PTR,53) +#define CCM_POST_ROOT53_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,53) +#define CCM_POST_ROOT53_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,53) +#define CCM_POST_ROOT53_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,53) +#define CCM_PRE53 CCM_PRE_REG(CCM_BASE_PTR,53) +#define CCM_PRE_ROOT53_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,53) +#define CCM_PRE_ROOT53_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,53) +#define CCM_PRE_ROOT53_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,53) +#define CCM_ACCESS_CTRL53 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,53) +#define CCM_ACCESS_CTRL_ROOT53_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,53) +#define CCM_ACCESS_CTRL_ROOT53_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,53) +#define CCM_ACCESS_CTRL_ROOT53_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,53) +#define CCM_TARGET_ROOT54 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,54) +#define CCM_TARGET_ROOT54_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,54) +#define CCM_TARGET_ROOT54_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,54) +#define CCM_TARGET_ROOT54_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,54) +#define CCM_MISC54 CCM_MISC_REG(CCM_BASE_PTR,54) +#define CCM_MISC_ROOT54_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,54) +#define CCM_MISC_ROOT54_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,54) +#define CCM_MISC_ROOT54_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,54) +#define CCM_POST54 CCM_POST_REG(CCM_BASE_PTR,54) +#define CCM_POST_ROOT54_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,54) +#define CCM_POST_ROOT54_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,54) +#define CCM_POST_ROOT54_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,54) +#define CCM_PRE54 CCM_PRE_REG(CCM_BASE_PTR,54) +#define CCM_PRE_ROOT54_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,54) +#define CCM_PRE_ROOT54_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,54) +#define CCM_PRE_ROOT54_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,54) +#define CCM_ACCESS_CTRL54 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,54) +#define CCM_ACCESS_CTRL_ROOT54_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,54) +#define CCM_ACCESS_CTRL_ROOT54_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,54) +#define CCM_ACCESS_CTRL_ROOT54_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,54) +#define CCM_TARGET_ROOT55 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,55) +#define CCM_TARGET_ROOT55_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,55) +#define CCM_TARGET_ROOT55_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,55) +#define CCM_TARGET_ROOT55_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,55) +#define CCM_MISC55 CCM_MISC_REG(CCM_BASE_PTR,55) +#define CCM_MISC_ROOT55_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,55) +#define CCM_MISC_ROOT55_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,55) +#define CCM_MISC_ROOT55_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,55) +#define CCM_POST55 CCM_POST_REG(CCM_BASE_PTR,55) +#define CCM_POST_ROOT55_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,55) +#define CCM_POST_ROOT55_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,55) +#define CCM_POST_ROOT55_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,55) +#define CCM_PRE55 CCM_PRE_REG(CCM_BASE_PTR,55) +#define CCM_PRE_ROOT55_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,55) +#define CCM_PRE_ROOT55_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,55) +#define CCM_PRE_ROOT55_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,55) +#define CCM_ACCESS_CTRL55 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,55) +#define CCM_ACCESS_CTRL_ROOT55_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,55) +#define CCM_ACCESS_CTRL_ROOT55_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,55) +#define CCM_ACCESS_CTRL_ROOT55_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,55) +#define CCM_TARGET_ROOT56 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,56) +#define CCM_TARGET_ROOT56_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,56) +#define CCM_TARGET_ROOT56_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,56) +#define CCM_TARGET_ROOT56_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,56) +#define CCM_MISC56 CCM_MISC_REG(CCM_BASE_PTR,56) +#define CCM_MISC_ROOT56_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,56) +#define CCM_MISC_ROOT56_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,56) +#define CCM_MISC_ROOT56_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,56) +#define CCM_POST56 CCM_POST_REG(CCM_BASE_PTR,56) +#define CCM_POST_ROOT56_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,56) +#define CCM_POST_ROOT56_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,56) +#define CCM_POST_ROOT56_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,56) +#define CCM_PRE56 CCM_PRE_REG(CCM_BASE_PTR,56) +#define CCM_PRE_ROOT56_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,56) +#define CCM_PRE_ROOT56_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,56) +#define CCM_PRE_ROOT56_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,56) +#define CCM_ACCESS_CTRL56 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,56) +#define CCM_ACCESS_CTRL_ROOT56_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,56) +#define CCM_ACCESS_CTRL_ROOT56_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,56) +#define CCM_ACCESS_CTRL_ROOT56_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,56) +#define CCM_TARGET_ROOT57 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,57) +#define CCM_TARGET_ROOT57_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,57) +#define CCM_TARGET_ROOT57_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,57) +#define CCM_TARGET_ROOT57_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,57) +#define CCM_MISC57 CCM_MISC_REG(CCM_BASE_PTR,57) +#define CCM_MISC_ROOT57_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,57) +#define CCM_MISC_ROOT57_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,57) +#define CCM_MISC_ROOT57_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,57) +#define CCM_POST57 CCM_POST_REG(CCM_BASE_PTR,57) +#define CCM_POST_ROOT57_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,57) +#define CCM_POST_ROOT57_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,57) +#define CCM_POST_ROOT57_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,57) +#define CCM_PRE57 CCM_PRE_REG(CCM_BASE_PTR,57) +#define CCM_PRE_ROOT57_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,57) +#define CCM_PRE_ROOT57_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,57) +#define CCM_PRE_ROOT57_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,57) +#define CCM_ACCESS_CTRL57 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,57) +#define CCM_ACCESS_CTRL_ROOT57_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,57) +#define CCM_ACCESS_CTRL_ROOT57_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,57) +#define CCM_ACCESS_CTRL_ROOT57_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,57) +#define CCM_TARGET_ROOT58 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,58) +#define CCM_TARGET_ROOT58_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,58) +#define CCM_TARGET_ROOT58_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,58) +#define CCM_TARGET_ROOT58_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,58) +#define CCM_MISC58 CCM_MISC_REG(CCM_BASE_PTR,58) +#define CCM_MISC_ROOT58_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,58) +#define CCM_MISC_ROOT58_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,58) +#define CCM_MISC_ROOT58_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,58) +#define CCM_POST58 CCM_POST_REG(CCM_BASE_PTR,58) +#define CCM_POST_ROOT58_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,58) +#define CCM_POST_ROOT58_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,58) +#define CCM_POST_ROOT58_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,58) +#define CCM_PRE58 CCM_PRE_REG(CCM_BASE_PTR,58) +#define CCM_PRE_ROOT58_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,58) +#define CCM_PRE_ROOT58_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,58) +#define CCM_PRE_ROOT58_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,58) +#define CCM_ACCESS_CTRL58 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,58) +#define CCM_ACCESS_CTRL_ROOT58_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,58) +#define CCM_ACCESS_CTRL_ROOT58_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,58) +#define CCM_ACCESS_CTRL_ROOT58_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,58) +#define CCM_TARGET_ROOT59 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,59) +#define CCM_TARGET_ROOT59_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,59) +#define CCM_TARGET_ROOT59_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,59) +#define CCM_TARGET_ROOT59_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,59) +#define CCM_MISC59 CCM_MISC_REG(CCM_BASE_PTR,59) +#define CCM_MISC_ROOT59_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,59) +#define CCM_MISC_ROOT59_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,59) +#define CCM_MISC_ROOT59_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,59) +#define CCM_POST59 CCM_POST_REG(CCM_BASE_PTR,59) +#define CCM_POST_ROOT59_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,59) +#define CCM_POST_ROOT59_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,59) +#define CCM_POST_ROOT59_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,59) +#define CCM_PRE59 CCM_PRE_REG(CCM_BASE_PTR,59) +#define CCM_PRE_ROOT59_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,59) +#define CCM_PRE_ROOT59_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,59) +#define CCM_PRE_ROOT59_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,59) +#define CCM_ACCESS_CTRL59 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,59) +#define CCM_ACCESS_CTRL_ROOT59_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,59) +#define CCM_ACCESS_CTRL_ROOT59_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,59) +#define CCM_ACCESS_CTRL_ROOT59_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,59) +#define CCM_TARGET_ROOT60 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,60) +#define CCM_TARGET_ROOT60_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,60) +#define CCM_TARGET_ROOT60_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,60) +#define CCM_TARGET_ROOT60_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,60) +#define CCM_MISC60 CCM_MISC_REG(CCM_BASE_PTR,60) +#define CCM_MISC_ROOT60_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,60) +#define CCM_MISC_ROOT60_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,60) +#define CCM_MISC_ROOT60_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,60) +#define CCM_POST60 CCM_POST_REG(CCM_BASE_PTR,60) +#define CCM_POST_ROOT60_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,60) +#define CCM_POST_ROOT60_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,60) +#define CCM_POST_ROOT60_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,60) +#define CCM_PRE60 CCM_PRE_REG(CCM_BASE_PTR,60) +#define CCM_PRE_ROOT60_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,60) +#define CCM_PRE_ROOT60_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,60) +#define CCM_PRE_ROOT60_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,60) +#define CCM_ACCESS_CTRL60 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,60) +#define CCM_ACCESS_CTRL_ROOT60_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,60) +#define CCM_ACCESS_CTRL_ROOT60_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,60) +#define CCM_ACCESS_CTRL_ROOT60_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,60) +#define CCM_TARGET_ROOT61 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,61) +#define CCM_TARGET_ROOT61_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,61) +#define CCM_TARGET_ROOT61_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,61) +#define CCM_TARGET_ROOT61_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,61) +#define CCM_MISC61 CCM_MISC_REG(CCM_BASE_PTR,61) +#define CCM_MISC_ROOT61_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,61) +#define CCM_MISC_ROOT61_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,61) +#define CCM_MISC_ROOT61_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,61) +#define CCM_POST61 CCM_POST_REG(CCM_BASE_PTR,61) +#define CCM_POST_ROOT61_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,61) +#define CCM_POST_ROOT61_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,61) +#define CCM_POST_ROOT61_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,61) +#define CCM_PRE61 CCM_PRE_REG(CCM_BASE_PTR,61) +#define CCM_PRE_ROOT61_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,61) +#define CCM_PRE_ROOT61_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,61) +#define CCM_PRE_ROOT61_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,61) +#define CCM_ACCESS_CTRL61 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,61) +#define CCM_ACCESS_CTRL_ROOT61_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,61) +#define CCM_ACCESS_CTRL_ROOT61_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,61) +#define CCM_ACCESS_CTRL_ROOT61_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,61) +#define CCM_TARGET_ROOT62 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,62) +#define CCM_TARGET_ROOT62_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,62) +#define CCM_TARGET_ROOT62_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,62) +#define CCM_TARGET_ROOT62_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,62) +#define CCM_MISC62 CCM_MISC_REG(CCM_BASE_PTR,62) +#define CCM_MISC_ROOT62_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,62) +#define CCM_MISC_ROOT62_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,62) +#define CCM_MISC_ROOT62_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,62) +#define CCM_POST62 CCM_POST_REG(CCM_BASE_PTR,62) +#define CCM_POST_ROOT62_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,62) +#define CCM_POST_ROOT62_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,62) +#define CCM_POST_ROOT62_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,62) +#define CCM_PRE62 CCM_PRE_REG(CCM_BASE_PTR,62) +#define CCM_PRE_ROOT62_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,62) +#define CCM_PRE_ROOT62_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,62) +#define CCM_PRE_ROOT62_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,62) +#define CCM_ACCESS_CTRL62 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,62) +#define CCM_ACCESS_CTRL_ROOT62_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,62) +#define CCM_ACCESS_CTRL_ROOT62_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,62) +#define CCM_ACCESS_CTRL_ROOT62_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,62) +#define CCM_TARGET_ROOT63 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,63) +#define CCM_TARGET_ROOT63_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,63) +#define CCM_TARGET_ROOT63_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,63) +#define CCM_TARGET_ROOT63_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,63) +#define CCM_MISC63 CCM_MISC_REG(CCM_BASE_PTR,63) +#define CCM_MISC_ROOT63_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,63) +#define CCM_MISC_ROOT63_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,63) +#define CCM_MISC_ROOT63_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,63) +#define CCM_POST63 CCM_POST_REG(CCM_BASE_PTR,63) +#define CCM_POST_ROOT63_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,63) +#define CCM_POST_ROOT63_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,63) +#define CCM_POST_ROOT63_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,63) +#define CCM_PRE63 CCM_PRE_REG(CCM_BASE_PTR,63) +#define CCM_PRE_ROOT63_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,63) +#define CCM_PRE_ROOT63_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,63) +#define CCM_PRE_ROOT63_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,63) +#define CCM_ACCESS_CTRL63 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,63) +#define CCM_ACCESS_CTRL_ROOT63_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,63) +#define CCM_ACCESS_CTRL_ROOT63_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,63) +#define CCM_ACCESS_CTRL_ROOT63_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,63) +#define CCM_TARGET_ROOT64 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,64) +#define CCM_TARGET_ROOT64_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,64) +#define CCM_TARGET_ROOT64_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,64) +#define CCM_TARGET_ROOT64_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,64) +#define CCM_MISC64 CCM_MISC_REG(CCM_BASE_PTR,64) +#define CCM_MISC_ROOT64_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,64) +#define CCM_MISC_ROOT64_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,64) +#define CCM_MISC_ROOT64_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,64) +#define CCM_POST64 CCM_POST_REG(CCM_BASE_PTR,64) +#define CCM_POST_ROOT64_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,64) +#define CCM_POST_ROOT64_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,64) +#define CCM_POST_ROOT64_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,64) +#define CCM_PRE64 CCM_PRE_REG(CCM_BASE_PTR,64) +#define CCM_PRE_ROOT64_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,64) +#define CCM_PRE_ROOT64_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,64) +#define CCM_PRE_ROOT64_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,64) +#define CCM_ACCESS_CTRL64 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,64) +#define CCM_ACCESS_CTRL_ROOT64_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,64) +#define CCM_ACCESS_CTRL_ROOT64_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,64) +#define CCM_ACCESS_CTRL_ROOT64_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,64) +#define CCM_TARGET_ROOT65 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,65) +#define CCM_TARGET_ROOT65_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,65) +#define CCM_TARGET_ROOT65_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,65) +#define CCM_TARGET_ROOT65_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,65) +#define CCM_MISC65 CCM_MISC_REG(CCM_BASE_PTR,65) +#define CCM_MISC_ROOT65_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,65) +#define CCM_MISC_ROOT65_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,65) +#define CCM_MISC_ROOT65_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,65) +#define CCM_POST65 CCM_POST_REG(CCM_BASE_PTR,65) +#define CCM_POST_ROOT65_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,65) +#define CCM_POST_ROOT65_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,65) +#define CCM_POST_ROOT65_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,65) +#define CCM_PRE65 CCM_PRE_REG(CCM_BASE_PTR,65) +#define CCM_PRE_ROOT65_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,65) +#define CCM_PRE_ROOT65_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,65) +#define CCM_PRE_ROOT65_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,65) +#define CCM_ACCESS_CTRL65 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,65) +#define CCM_ACCESS_CTRL_ROOT65_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,65) +#define CCM_ACCESS_CTRL_ROOT65_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,65) +#define CCM_ACCESS_CTRL_ROOT65_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,65) +#define CCM_TARGET_ROOT66 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,66) +#define CCM_TARGET_ROOT66_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,66) +#define CCM_TARGET_ROOT66_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,66) +#define CCM_TARGET_ROOT66_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,66) +#define CCM_MISC66 CCM_MISC_REG(CCM_BASE_PTR,66) +#define CCM_MISC_ROOT66_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,66) +#define CCM_MISC_ROOT66_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,66) +#define CCM_MISC_ROOT66_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,66) +#define CCM_POST66 CCM_POST_REG(CCM_BASE_PTR,66) +#define CCM_POST_ROOT66_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,66) +#define CCM_POST_ROOT66_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,66) +#define CCM_POST_ROOT66_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,66) +#define CCM_PRE66 CCM_PRE_REG(CCM_BASE_PTR,66) +#define CCM_PRE_ROOT66_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,66) +#define CCM_PRE_ROOT66_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,66) +#define CCM_PRE_ROOT66_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,66) +#define CCM_ACCESS_CTRL66 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,66) +#define CCM_ACCESS_CTRL_ROOT66_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,66) +#define CCM_ACCESS_CTRL_ROOT66_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,66) +#define CCM_ACCESS_CTRL_ROOT66_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,66) +#define CCM_TARGET_ROOT67 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,67) +#define CCM_TARGET_ROOT67_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,67) +#define CCM_TARGET_ROOT67_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,67) +#define CCM_TARGET_ROOT67_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,67) +#define CCM_MISC67 CCM_MISC_REG(CCM_BASE_PTR,67) +#define CCM_MISC_ROOT67_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,67) +#define CCM_MISC_ROOT67_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,67) +#define CCM_MISC_ROOT67_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,67) +#define CCM_POST67 CCM_POST_REG(CCM_BASE_PTR,67) +#define CCM_POST_ROOT67_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,67) +#define CCM_POST_ROOT67_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,67) +#define CCM_POST_ROOT67_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,67) +#define CCM_PRE67 CCM_PRE_REG(CCM_BASE_PTR,67) +#define CCM_PRE_ROOT67_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,67) +#define CCM_PRE_ROOT67_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,67) +#define CCM_PRE_ROOT67_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,67) +#define CCM_ACCESS_CTRL67 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,67) +#define CCM_ACCESS_CTRL_ROOT67_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,67) +#define CCM_ACCESS_CTRL_ROOT67_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,67) +#define CCM_ACCESS_CTRL_ROOT67_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,67) +#define CCM_TARGET_ROOT68 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,68) +#define CCM_TARGET_ROOT68_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,68) +#define CCM_TARGET_ROOT68_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,68) +#define CCM_TARGET_ROOT68_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,68) +#define CCM_MISC68 CCM_MISC_REG(CCM_BASE_PTR,68) +#define CCM_MISC_ROOT68_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,68) +#define CCM_MISC_ROOT68_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,68) +#define CCM_MISC_ROOT68_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,68) +#define CCM_POST68 CCM_POST_REG(CCM_BASE_PTR,68) +#define CCM_POST_ROOT68_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,68) +#define CCM_POST_ROOT68_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,68) +#define CCM_POST_ROOT68_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,68) +#define CCM_PRE68 CCM_PRE_REG(CCM_BASE_PTR,68) +#define CCM_PRE_ROOT68_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,68) +#define CCM_PRE_ROOT68_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,68) +#define CCM_PRE_ROOT68_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,68) +#define CCM_ACCESS_CTRL68 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,68) +#define CCM_ACCESS_CTRL_ROOT68_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,68) +#define CCM_ACCESS_CTRL_ROOT68_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,68) +#define CCM_ACCESS_CTRL_ROOT68_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,68) +#define CCM_TARGET_ROOT69 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,69) +#define CCM_TARGET_ROOT69_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,69) +#define CCM_TARGET_ROOT69_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,69) +#define CCM_TARGET_ROOT69_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,69) +#define CCM_MISC69 CCM_MISC_REG(CCM_BASE_PTR,69) +#define CCM_MISC_ROOT69_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,69) +#define CCM_MISC_ROOT69_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,69) +#define CCM_MISC_ROOT69_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,69) +#define CCM_POST69 CCM_POST_REG(CCM_BASE_PTR,69) +#define CCM_POST_ROOT69_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,69) +#define CCM_POST_ROOT69_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,69) +#define CCM_POST_ROOT69_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,69) +#define CCM_PRE69 CCM_PRE_REG(CCM_BASE_PTR,69) +#define CCM_PRE_ROOT69_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,69) +#define CCM_PRE_ROOT69_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,69) +#define CCM_PRE_ROOT69_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,69) +#define CCM_ACCESS_CTRL69 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,69) +#define CCM_ACCESS_CTRL_ROOT69_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,69) +#define CCM_ACCESS_CTRL_ROOT69_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,69) +#define CCM_ACCESS_CTRL_ROOT69_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,69) +#define CCM_TARGET_ROOT70 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,70) +#define CCM_TARGET_ROOT70_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,70) +#define CCM_TARGET_ROOT70_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,70) +#define CCM_TARGET_ROOT70_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,70) +#define CCM_MISC70 CCM_MISC_REG(CCM_BASE_PTR,70) +#define CCM_MISC_ROOT70_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,70) +#define CCM_MISC_ROOT70_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,70) +#define CCM_MISC_ROOT70_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,70) +#define CCM_POST70 CCM_POST_REG(CCM_BASE_PTR,70) +#define CCM_POST_ROOT70_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,70) +#define CCM_POST_ROOT70_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,70) +#define CCM_POST_ROOT70_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,70) +#define CCM_PRE70 CCM_PRE_REG(CCM_BASE_PTR,70) +#define CCM_PRE_ROOT70_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,70) +#define CCM_PRE_ROOT70_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,70) +#define CCM_PRE_ROOT70_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,70) +#define CCM_ACCESS_CTRL70 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,70) +#define CCM_ACCESS_CTRL_ROOT70_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,70) +#define CCM_ACCESS_CTRL_ROOT70_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,70) +#define CCM_ACCESS_CTRL_ROOT70_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,70) +#define CCM_TARGET_ROOT71 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,71) +#define CCM_TARGET_ROOT71_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,71) +#define CCM_TARGET_ROOT71_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,71) +#define CCM_TARGET_ROOT71_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,71) +#define CCM_MISC71 CCM_MISC_REG(CCM_BASE_PTR,71) +#define CCM_MISC_ROOT71_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,71) +#define CCM_MISC_ROOT71_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,71) +#define CCM_MISC_ROOT71_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,71) +#define CCM_POST71 CCM_POST_REG(CCM_BASE_PTR,71) +#define CCM_POST_ROOT71_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,71) +#define CCM_POST_ROOT71_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,71) +#define CCM_POST_ROOT71_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,71) +#define CCM_PRE71 CCM_PRE_REG(CCM_BASE_PTR,71) +#define CCM_PRE_ROOT71_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,71) +#define CCM_PRE_ROOT71_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,71) +#define CCM_PRE_ROOT71_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,71) +#define CCM_ACCESS_CTRL71 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,71) +#define CCM_ACCESS_CTRL_ROOT71_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,71) +#define CCM_ACCESS_CTRL_ROOT71_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,71) +#define CCM_ACCESS_CTRL_ROOT71_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,71) +#define CCM_TARGET_ROOT72 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,72) +#define CCM_TARGET_ROOT72_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,72) +#define CCM_TARGET_ROOT72_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,72) +#define CCM_TARGET_ROOT72_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,72) +#define CCM_MISC72 CCM_MISC_REG(CCM_BASE_PTR,72) +#define CCM_MISC_ROOT72_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,72) +#define CCM_MISC_ROOT72_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,72) +#define CCM_MISC_ROOT72_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,72) +#define CCM_POST72 CCM_POST_REG(CCM_BASE_PTR,72) +#define CCM_POST_ROOT72_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,72) +#define CCM_POST_ROOT72_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,72) +#define CCM_POST_ROOT72_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,72) +#define CCM_PRE72 CCM_PRE_REG(CCM_BASE_PTR,72) +#define CCM_PRE_ROOT72_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,72) +#define CCM_PRE_ROOT72_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,72) +#define CCM_PRE_ROOT72_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,72) +#define CCM_ACCESS_CTRL72 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,72) +#define CCM_ACCESS_CTRL_ROOT72_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,72) +#define CCM_ACCESS_CTRL_ROOT72_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,72) +#define CCM_ACCESS_CTRL_ROOT72_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,72) +#define CCM_TARGET_ROOT73 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,73) +#define CCM_TARGET_ROOT73_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,73) +#define CCM_TARGET_ROOT73_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,73) +#define CCM_TARGET_ROOT73_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,73) +#define CCM_MISC73 CCM_MISC_REG(CCM_BASE_PTR,73) +#define CCM_MISC_ROOT73_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,73) +#define CCM_MISC_ROOT73_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,73) +#define CCM_MISC_ROOT73_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,73) +#define CCM_POST73 CCM_POST_REG(CCM_BASE_PTR,73) +#define CCM_POST_ROOT73_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,73) +#define CCM_POST_ROOT73_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,73) +#define CCM_POST_ROOT73_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,73) +#define CCM_PRE73 CCM_PRE_REG(CCM_BASE_PTR,73) +#define CCM_PRE_ROOT73_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,73) +#define CCM_PRE_ROOT73_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,73) +#define CCM_PRE_ROOT73_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,73) +#define CCM_ACCESS_CTRL73 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,73) +#define CCM_ACCESS_CTRL_ROOT73_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,73) +#define CCM_ACCESS_CTRL_ROOT73_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,73) +#define CCM_ACCESS_CTRL_ROOT73_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,73) +#define CCM_TARGET_ROOT74 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,74) +#define CCM_TARGET_ROOT74_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,74) +#define CCM_TARGET_ROOT74_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,74) +#define CCM_TARGET_ROOT74_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,74) +#define CCM_MISC74 CCM_MISC_REG(CCM_BASE_PTR,74) +#define CCM_MISC_ROOT74_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,74) +#define CCM_MISC_ROOT74_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,74) +#define CCM_MISC_ROOT74_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,74) +#define CCM_POST74 CCM_POST_REG(CCM_BASE_PTR,74) +#define CCM_POST_ROOT74_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,74) +#define CCM_POST_ROOT74_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,74) +#define CCM_POST_ROOT74_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,74) +#define CCM_PRE74 CCM_PRE_REG(CCM_BASE_PTR,74) +#define CCM_PRE_ROOT74_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,74) +#define CCM_PRE_ROOT74_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,74) +#define CCM_PRE_ROOT74_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,74) +#define CCM_ACCESS_CTRL74 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,74) +#define CCM_ACCESS_CTRL_ROOT74_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,74) +#define CCM_ACCESS_CTRL_ROOT74_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,74) +#define CCM_ACCESS_CTRL_ROOT74_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,74) +#define CCM_TARGET_ROOT75 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,75) +#define CCM_TARGET_ROOT75_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,75) +#define CCM_TARGET_ROOT75_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,75) +#define CCM_TARGET_ROOT75_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,75) +#define CCM_MISC75 CCM_MISC_REG(CCM_BASE_PTR,75) +#define CCM_MISC_ROOT75_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,75) +#define CCM_MISC_ROOT75_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,75) +#define CCM_MISC_ROOT75_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,75) +#define CCM_POST75 CCM_POST_REG(CCM_BASE_PTR,75) +#define CCM_POST_ROOT75_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,75) +#define CCM_POST_ROOT75_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,75) +#define CCM_POST_ROOT75_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,75) +#define CCM_PRE75 CCM_PRE_REG(CCM_BASE_PTR,75) +#define CCM_PRE_ROOT75_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,75) +#define CCM_PRE_ROOT75_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,75) +#define CCM_PRE_ROOT75_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,75) +#define CCM_ACCESS_CTRL75 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,75) +#define CCM_ACCESS_CTRL_ROOT75_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,75) +#define CCM_ACCESS_CTRL_ROOT75_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,75) +#define CCM_ACCESS_CTRL_ROOT75_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,75) +#define CCM_TARGET_ROOT76 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,76) +#define CCM_TARGET_ROOT76_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,76) +#define CCM_TARGET_ROOT76_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,76) +#define CCM_TARGET_ROOT76_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,76) +#define CCM_MISC76 CCM_MISC_REG(CCM_BASE_PTR,76) +#define CCM_MISC_ROOT76_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,76) +#define CCM_MISC_ROOT76_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,76) +#define CCM_MISC_ROOT76_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,76) +#define CCM_POST76 CCM_POST_REG(CCM_BASE_PTR,76) +#define CCM_POST_ROOT76_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,76) +#define CCM_POST_ROOT76_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,76) +#define CCM_POST_ROOT76_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,76) +#define CCM_PRE76 CCM_PRE_REG(CCM_BASE_PTR,76) +#define CCM_PRE_ROOT76_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,76) +#define CCM_PRE_ROOT76_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,76) +#define CCM_PRE_ROOT76_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,76) +#define CCM_ACCESS_CTRL76 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,76) +#define CCM_ACCESS_CTRL_ROOT76_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,76) +#define CCM_ACCESS_CTRL_ROOT76_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,76) +#define CCM_ACCESS_CTRL_ROOT76_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,76) +#define CCM_TARGET_ROOT77 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,77) +#define CCM_TARGET_ROOT77_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,77) +#define CCM_TARGET_ROOT77_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,77) +#define CCM_TARGET_ROOT77_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,77) +#define CCM_MISC77 CCM_MISC_REG(CCM_BASE_PTR,77) +#define CCM_MISC_ROOT77_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,77) +#define CCM_MISC_ROOT77_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,77) +#define CCM_MISC_ROOT77_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,77) +#define CCM_POST77 CCM_POST_REG(CCM_BASE_PTR,77) +#define CCM_POST_ROOT77_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,77) +#define CCM_POST_ROOT77_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,77) +#define CCM_POST_ROOT77_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,77) +#define CCM_PRE77 CCM_PRE_REG(CCM_BASE_PTR,77) +#define CCM_PRE_ROOT77_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,77) +#define CCM_PRE_ROOT77_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,77) +#define CCM_PRE_ROOT77_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,77) +#define CCM_ACCESS_CTRL77 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,77) +#define CCM_ACCESS_CTRL_ROOT77_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,77) +#define CCM_ACCESS_CTRL_ROOT77_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,77) +#define CCM_ACCESS_CTRL_ROOT77_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,77) +#define CCM_TARGET_ROOT78 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,78) +#define CCM_TARGET_ROOT78_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,78) +#define CCM_TARGET_ROOT78_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,78) +#define CCM_TARGET_ROOT78_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,78) +#define CCM_MISC78 CCM_MISC_REG(CCM_BASE_PTR,78) +#define CCM_MISC_ROOT78_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,78) +#define CCM_MISC_ROOT78_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,78) +#define CCM_MISC_ROOT78_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,78) +#define CCM_POST78 CCM_POST_REG(CCM_BASE_PTR,78) +#define CCM_POST_ROOT78_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,78) +#define CCM_POST_ROOT78_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,78) +#define CCM_POST_ROOT78_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,78) +#define CCM_PRE78 CCM_PRE_REG(CCM_BASE_PTR,78) +#define CCM_PRE_ROOT78_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,78) +#define CCM_PRE_ROOT78_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,78) +#define CCM_PRE_ROOT78_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,78) +#define CCM_ACCESS_CTRL78 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,78) +#define CCM_ACCESS_CTRL_ROOT78_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,78) +#define CCM_ACCESS_CTRL_ROOT78_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,78) +#define CCM_ACCESS_CTRL_ROOT78_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,78) +#define CCM_TARGET_ROOT79 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,79) +#define CCM_TARGET_ROOT79_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,79) +#define CCM_TARGET_ROOT79_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,79) +#define CCM_TARGET_ROOT79_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,79) +#define CCM_MISC79 CCM_MISC_REG(CCM_BASE_PTR,79) +#define CCM_MISC_ROOT79_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,79) +#define CCM_MISC_ROOT79_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,79) +#define CCM_MISC_ROOT79_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,79) +#define CCM_POST79 CCM_POST_REG(CCM_BASE_PTR,79) +#define CCM_POST_ROOT79_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,79) +#define CCM_POST_ROOT79_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,79) +#define CCM_POST_ROOT79_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,79) +#define CCM_PRE79 CCM_PRE_REG(CCM_BASE_PTR,79) +#define CCM_PRE_ROOT79_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,79) +#define CCM_PRE_ROOT79_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,79) +#define CCM_PRE_ROOT79_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,79) +#define CCM_ACCESS_CTRL79 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,79) +#define CCM_ACCESS_CTRL_ROOT79_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,79) +#define CCM_ACCESS_CTRL_ROOT79_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,79) +#define CCM_ACCESS_CTRL_ROOT79_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,79) +#define CCM_TARGET_ROOT80 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,80) +#define CCM_TARGET_ROOT80_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,80) +#define CCM_TARGET_ROOT80_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,80) +#define CCM_TARGET_ROOT80_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,80) +#define CCM_MISC80 CCM_MISC_REG(CCM_BASE_PTR,80) +#define CCM_MISC_ROOT80_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,80) +#define CCM_MISC_ROOT80_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,80) +#define CCM_MISC_ROOT80_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,80) +#define CCM_POST80 CCM_POST_REG(CCM_BASE_PTR,80) +#define CCM_POST_ROOT80_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,80) +#define CCM_POST_ROOT80_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,80) +#define CCM_POST_ROOT80_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,80) +#define CCM_PRE80 CCM_PRE_REG(CCM_BASE_PTR,80) +#define CCM_PRE_ROOT80_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,80) +#define CCM_PRE_ROOT80_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,80) +#define CCM_PRE_ROOT80_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,80) +#define CCM_ACCESS_CTRL80 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,80) +#define CCM_ACCESS_CTRL_ROOT80_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,80) +#define CCM_ACCESS_CTRL_ROOT80_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,80) +#define CCM_ACCESS_CTRL_ROOT80_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,80) +#define CCM_TARGET_ROOT81 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,81) +#define CCM_TARGET_ROOT81_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,81) +#define CCM_TARGET_ROOT81_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,81) +#define CCM_TARGET_ROOT81_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,81) +#define CCM_MISC81 CCM_MISC_REG(CCM_BASE_PTR,81) +#define CCM_MISC_ROOT81_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,81) +#define CCM_MISC_ROOT81_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,81) +#define CCM_MISC_ROOT81_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,81) +#define CCM_POST81 CCM_POST_REG(CCM_BASE_PTR,81) +#define CCM_POST_ROOT81_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,81) +#define CCM_POST_ROOT81_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,81) +#define CCM_POST_ROOT81_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,81) +#define CCM_PRE81 CCM_PRE_REG(CCM_BASE_PTR,81) +#define CCM_PRE_ROOT81_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,81) +#define CCM_PRE_ROOT81_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,81) +#define CCM_PRE_ROOT81_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,81) +#define CCM_ACCESS_CTRL81 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,81) +#define CCM_ACCESS_CTRL_ROOT81_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,81) +#define CCM_ACCESS_CTRL_ROOT81_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,81) +#define CCM_ACCESS_CTRL_ROOT81_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,81) +#define CCM_TARGET_ROOT82 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,82) +#define CCM_TARGET_ROOT82_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,82) +#define CCM_TARGET_ROOT82_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,82) +#define CCM_TARGET_ROOT82_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,82) +#define CCM_MISC82 CCM_MISC_REG(CCM_BASE_PTR,82) +#define CCM_MISC_ROOT82_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,82) +#define CCM_MISC_ROOT82_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,82) +#define CCM_MISC_ROOT82_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,82) +#define CCM_POST82 CCM_POST_REG(CCM_BASE_PTR,82) +#define CCM_POST_ROOT82_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,82) +#define CCM_POST_ROOT82_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,82) +#define CCM_POST_ROOT82_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,82) +#define CCM_PRE82 CCM_PRE_REG(CCM_BASE_PTR,82) +#define CCM_PRE_ROOT82_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,82) +#define CCM_PRE_ROOT82_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,82) +#define CCM_PRE_ROOT82_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,82) +#define CCM_ACCESS_CTRL82 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,82) +#define CCM_ACCESS_CTRL_ROOT82_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,82) +#define CCM_ACCESS_CTRL_ROOT82_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,82) +#define CCM_ACCESS_CTRL_ROOT82_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,82) +#define CCM_TARGET_ROOT83 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,83) +#define CCM_TARGET_ROOT83_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,83) +#define CCM_TARGET_ROOT83_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,83) +#define CCM_TARGET_ROOT83_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,83) +#define CCM_MISC83 CCM_MISC_REG(CCM_BASE_PTR,83) +#define CCM_MISC_ROOT83_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,83) +#define CCM_MISC_ROOT83_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,83) +#define CCM_MISC_ROOT83_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,83) +#define CCM_POST83 CCM_POST_REG(CCM_BASE_PTR,83) +#define CCM_POST_ROOT83_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,83) +#define CCM_POST_ROOT83_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,83) +#define CCM_POST_ROOT83_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,83) +#define CCM_PRE83 CCM_PRE_REG(CCM_BASE_PTR,83) +#define CCM_PRE_ROOT83_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,83) +#define CCM_PRE_ROOT83_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,83) +#define CCM_PRE_ROOT83_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,83) +#define CCM_ACCESS_CTRL83 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,83) +#define CCM_ACCESS_CTRL_ROOT83_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,83) +#define CCM_ACCESS_CTRL_ROOT83_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,83) +#define CCM_ACCESS_CTRL_ROOT83_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,83) +#define CCM_TARGET_ROOT84 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,84) +#define CCM_TARGET_ROOT84_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,84) +#define CCM_TARGET_ROOT84_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,84) +#define CCM_TARGET_ROOT84_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,84) +#define CCM_MISC84 CCM_MISC_REG(CCM_BASE_PTR,84) +#define CCM_MISC_ROOT84_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,84) +#define CCM_MISC_ROOT84_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,84) +#define CCM_MISC_ROOT84_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,84) +#define CCM_POST84 CCM_POST_REG(CCM_BASE_PTR,84) +#define CCM_POST_ROOT84_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,84) +#define CCM_POST_ROOT84_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,84) +#define CCM_POST_ROOT84_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,84) +#define CCM_PRE84 CCM_PRE_REG(CCM_BASE_PTR,84) +#define CCM_PRE_ROOT84_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,84) +#define CCM_PRE_ROOT84_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,84) +#define CCM_PRE_ROOT84_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,84) +#define CCM_ACCESS_CTRL84 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,84) +#define CCM_ACCESS_CTRL_ROOT84_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,84) +#define CCM_ACCESS_CTRL_ROOT84_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,84) +#define CCM_ACCESS_CTRL_ROOT84_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,84) +#define CCM_TARGET_ROOT85 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,85) +#define CCM_TARGET_ROOT85_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,85) +#define CCM_TARGET_ROOT85_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,85) +#define CCM_TARGET_ROOT85_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,85) +#define CCM_MISC85 CCM_MISC_REG(CCM_BASE_PTR,85) +#define CCM_MISC_ROOT85_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,85) +#define CCM_MISC_ROOT85_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,85) +#define CCM_MISC_ROOT85_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,85) +#define CCM_POST85 CCM_POST_REG(CCM_BASE_PTR,85) +#define CCM_POST_ROOT85_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,85) +#define CCM_POST_ROOT85_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,85) +#define CCM_POST_ROOT85_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,85) +#define CCM_PRE85 CCM_PRE_REG(CCM_BASE_PTR,85) +#define CCM_PRE_ROOT85_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,85) +#define CCM_PRE_ROOT85_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,85) +#define CCM_PRE_ROOT85_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,85) +#define CCM_ACCESS_CTRL85 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,85) +#define CCM_ACCESS_CTRL_ROOT85_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,85) +#define CCM_ACCESS_CTRL_ROOT85_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,85) +#define CCM_ACCESS_CTRL_ROOT85_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,85) +#define CCM_TARGET_ROOT86 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,86) +#define CCM_TARGET_ROOT86_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,86) +#define CCM_TARGET_ROOT86_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,86) +#define CCM_TARGET_ROOT86_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,86) +#define CCM_MISC86 CCM_MISC_REG(CCM_BASE_PTR,86) +#define CCM_MISC_ROOT86_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,86) +#define CCM_MISC_ROOT86_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,86) +#define CCM_MISC_ROOT86_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,86) +#define CCM_POST86 CCM_POST_REG(CCM_BASE_PTR,86) +#define CCM_POST_ROOT86_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,86) +#define CCM_POST_ROOT86_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,86) +#define CCM_POST_ROOT86_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,86) +#define CCM_PRE86 CCM_PRE_REG(CCM_BASE_PTR,86) +#define CCM_PRE_ROOT86_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,86) +#define CCM_PRE_ROOT86_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,86) +#define CCM_PRE_ROOT86_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,86) +#define CCM_ACCESS_CTRL86 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,86) +#define CCM_ACCESS_CTRL_ROOT86_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,86) +#define CCM_ACCESS_CTRL_ROOT86_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,86) +#define CCM_ACCESS_CTRL_ROOT86_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,86) +#define CCM_TARGET_ROOT87 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,87) +#define CCM_TARGET_ROOT87_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,87) +#define CCM_TARGET_ROOT87_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,87) +#define CCM_TARGET_ROOT87_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,87) +#define CCM_MISC87 CCM_MISC_REG(CCM_BASE_PTR,87) +#define CCM_MISC_ROOT87_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,87) +#define CCM_MISC_ROOT87_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,87) +#define CCM_MISC_ROOT87_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,87) +#define CCM_POST87 CCM_POST_REG(CCM_BASE_PTR,87) +#define CCM_POST_ROOT87_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,87) +#define CCM_POST_ROOT87_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,87) +#define CCM_POST_ROOT87_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,87) +#define CCM_PRE87 CCM_PRE_REG(CCM_BASE_PTR,87) +#define CCM_PRE_ROOT87_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,87) +#define CCM_PRE_ROOT87_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,87) +#define CCM_PRE_ROOT87_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,87) +#define CCM_ACCESS_CTRL87 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,87) +#define CCM_ACCESS_CTRL_ROOT87_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,87) +#define CCM_ACCESS_CTRL_ROOT87_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,87) +#define CCM_ACCESS_CTRL_ROOT87_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,87) +#define CCM_TARGET_ROOT88 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,88) +#define CCM_TARGET_ROOT88_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,88) +#define CCM_TARGET_ROOT88_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,88) +#define CCM_TARGET_ROOT88_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,88) +#define CCM_MISC88 CCM_MISC_REG(CCM_BASE_PTR,88) +#define CCM_MISC_ROOT88_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,88) +#define CCM_MISC_ROOT88_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,88) +#define CCM_MISC_ROOT88_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,88) +#define CCM_POST88 CCM_POST_REG(CCM_BASE_PTR,88) +#define CCM_POST_ROOT88_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,88) +#define CCM_POST_ROOT88_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,88) +#define CCM_POST_ROOT88_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,88) +#define CCM_PRE88 CCM_PRE_REG(CCM_BASE_PTR,88) +#define CCM_PRE_ROOT88_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,88) +#define CCM_PRE_ROOT88_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,88) +#define CCM_PRE_ROOT88_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,88) +#define CCM_ACCESS_CTRL88 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,88) +#define CCM_ACCESS_CTRL_ROOT88_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,88) +#define CCM_ACCESS_CTRL_ROOT88_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,88) +#define CCM_ACCESS_CTRL_ROOT88_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,88) +#define CCM_TARGET_ROOT89 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,89) +#define CCM_TARGET_ROOT89_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,89) +#define CCM_TARGET_ROOT89_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,89) +#define CCM_TARGET_ROOT89_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,89) +#define CCM_MISC89 CCM_MISC_REG(CCM_BASE_PTR,89) +#define CCM_MISC_ROOT89_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,89) +#define CCM_MISC_ROOT89_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,89) +#define CCM_MISC_ROOT89_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,89) +#define CCM_POST89 CCM_POST_REG(CCM_BASE_PTR,89) +#define CCM_POST_ROOT89_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,89) +#define CCM_POST_ROOT89_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,89) +#define CCM_POST_ROOT89_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,89) +#define CCM_PRE89 CCM_PRE_REG(CCM_BASE_PTR,89) +#define CCM_PRE_ROOT89_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,89) +#define CCM_PRE_ROOT89_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,89) +#define CCM_PRE_ROOT89_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,89) +#define CCM_ACCESS_CTRL89 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,89) +#define CCM_ACCESS_CTRL_ROOT89_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,89) +#define CCM_ACCESS_CTRL_ROOT89_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,89) +#define CCM_ACCESS_CTRL_ROOT89_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,89) +#define CCM_TARGET_ROOT90 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,90) +#define CCM_TARGET_ROOT90_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,90) +#define CCM_TARGET_ROOT90_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,90) +#define CCM_TARGET_ROOT90_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,90) +#define CCM_MISC90 CCM_MISC_REG(CCM_BASE_PTR,90) +#define CCM_MISC_ROOT90_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,90) +#define CCM_MISC_ROOT90_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,90) +#define CCM_MISC_ROOT90_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,90) +#define CCM_POST90 CCM_POST_REG(CCM_BASE_PTR,90) +#define CCM_POST_ROOT90_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,90) +#define CCM_POST_ROOT90_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,90) +#define CCM_POST_ROOT90_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,90) +#define CCM_PRE90 CCM_PRE_REG(CCM_BASE_PTR,90) +#define CCM_PRE_ROOT90_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,90) +#define CCM_PRE_ROOT90_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,90) +#define CCM_PRE_ROOT90_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,90) +#define CCM_ACCESS_CTRL90 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,90) +#define CCM_ACCESS_CTRL_ROOT90_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,90) +#define CCM_ACCESS_CTRL_ROOT90_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,90) +#define CCM_ACCESS_CTRL_ROOT90_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,90) +#define CCM_TARGET_ROOT91 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,91) +#define CCM_TARGET_ROOT91_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,91) +#define CCM_TARGET_ROOT91_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,91) +#define CCM_TARGET_ROOT91_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,91) +#define CCM_MISC91 CCM_MISC_REG(CCM_BASE_PTR,91) +#define CCM_MISC_ROOT91_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,91) +#define CCM_MISC_ROOT91_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,91) +#define CCM_MISC_ROOT91_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,91) +#define CCM_POST91 CCM_POST_REG(CCM_BASE_PTR,91) +#define CCM_POST_ROOT91_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,91) +#define CCM_POST_ROOT91_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,91) +#define CCM_POST_ROOT91_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,91) +#define CCM_PRE91 CCM_PRE_REG(CCM_BASE_PTR,91) +#define CCM_PRE_ROOT91_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,91) +#define CCM_PRE_ROOT91_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,91) +#define CCM_PRE_ROOT91_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,91) +#define CCM_ACCESS_CTRL91 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,91) +#define CCM_ACCESS_CTRL_ROOT91_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,91) +#define CCM_ACCESS_CTRL_ROOT91_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,91) +#define CCM_ACCESS_CTRL_ROOT91_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,91) +#define CCM_TARGET_ROOT92 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,92) +#define CCM_TARGET_ROOT92_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,92) +#define CCM_TARGET_ROOT92_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,92) +#define CCM_TARGET_ROOT92_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,92) +#define CCM_MISC92 CCM_MISC_REG(CCM_BASE_PTR,92) +#define CCM_MISC_ROOT92_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,92) +#define CCM_MISC_ROOT92_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,92) +#define CCM_MISC_ROOT92_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,92) +#define CCM_POST92 CCM_POST_REG(CCM_BASE_PTR,92) +#define CCM_POST_ROOT92_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,92) +#define CCM_POST_ROOT92_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,92) +#define CCM_POST_ROOT92_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,92) +#define CCM_PRE92 CCM_PRE_REG(CCM_BASE_PTR,92) +#define CCM_PRE_ROOT92_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,92) +#define CCM_PRE_ROOT92_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,92) +#define CCM_PRE_ROOT92_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,92) +#define CCM_ACCESS_CTRL92 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,92) +#define CCM_ACCESS_CTRL_ROOT92_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,92) +#define CCM_ACCESS_CTRL_ROOT92_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,92) +#define CCM_ACCESS_CTRL_ROOT92_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,92) +#define CCM_TARGET_ROOT93 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,93) +#define CCM_TARGET_ROOT93_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,93) +#define CCM_TARGET_ROOT93_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,93) +#define CCM_TARGET_ROOT93_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,93) +#define CCM_MISC93 CCM_MISC_REG(CCM_BASE_PTR,93) +#define CCM_MISC_ROOT93_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,93) +#define CCM_MISC_ROOT93_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,93) +#define CCM_MISC_ROOT93_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,93) +#define CCM_POST93 CCM_POST_REG(CCM_BASE_PTR,93) +#define CCM_POST_ROOT93_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,93) +#define CCM_POST_ROOT93_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,93) +#define CCM_POST_ROOT93_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,93) +#define CCM_PRE93 CCM_PRE_REG(CCM_BASE_PTR,93) +#define CCM_PRE_ROOT93_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,93) +#define CCM_PRE_ROOT93_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,93) +#define CCM_PRE_ROOT93_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,93) +#define CCM_ACCESS_CTRL93 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,93) +#define CCM_ACCESS_CTRL_ROOT93_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,93) +#define CCM_ACCESS_CTRL_ROOT93_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,93) +#define CCM_ACCESS_CTRL_ROOT93_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,93) +#define CCM_TARGET_ROOT94 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,94) +#define CCM_TARGET_ROOT94_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,94) +#define CCM_TARGET_ROOT94_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,94) +#define CCM_TARGET_ROOT94_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,94) +#define CCM_MISC94 CCM_MISC_REG(CCM_BASE_PTR,94) +#define CCM_MISC_ROOT94_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,94) +#define CCM_MISC_ROOT94_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,94) +#define CCM_MISC_ROOT94_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,94) +#define CCM_POST94 CCM_POST_REG(CCM_BASE_PTR,94) +#define CCM_POST_ROOT94_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,94) +#define CCM_POST_ROOT94_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,94) +#define CCM_POST_ROOT94_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,94) +#define CCM_PRE94 CCM_PRE_REG(CCM_BASE_PTR,94) +#define CCM_PRE_ROOT94_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,94) +#define CCM_PRE_ROOT94_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,94) +#define CCM_PRE_ROOT94_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,94) +#define CCM_ACCESS_CTRL94 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,94) +#define CCM_ACCESS_CTRL_ROOT94_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,94) +#define CCM_ACCESS_CTRL_ROOT94_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,94) +#define CCM_ACCESS_CTRL_ROOT94_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,94) +#define CCM_TARGET_ROOT95 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,95) +#define CCM_TARGET_ROOT95_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,95) +#define CCM_TARGET_ROOT95_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,95) +#define CCM_TARGET_ROOT95_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,95) +#define CCM_MISC95 CCM_MISC_REG(CCM_BASE_PTR,95) +#define CCM_MISC_ROOT95_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,95) +#define CCM_MISC_ROOT95_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,95) +#define CCM_MISC_ROOT95_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,95) +#define CCM_POST95 CCM_POST_REG(CCM_BASE_PTR,95) +#define CCM_POST_ROOT95_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,95) +#define CCM_POST_ROOT95_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,95) +#define CCM_POST_ROOT95_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,95) +#define CCM_PRE95 CCM_PRE_REG(CCM_BASE_PTR,95) +#define CCM_PRE_ROOT95_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,95) +#define CCM_PRE_ROOT95_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,95) +#define CCM_PRE_ROOT95_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,95) +#define CCM_ACCESS_CTRL95 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,95) +#define CCM_ACCESS_CTRL_ROOT95_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,95) +#define CCM_ACCESS_CTRL_ROOT95_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,95) +#define CCM_ACCESS_CTRL_ROOT95_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,95) +#define CCM_TARGET_ROOT96 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,96) +#define CCM_TARGET_ROOT96_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,96) +#define CCM_TARGET_ROOT96_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,96) +#define CCM_TARGET_ROOT96_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,96) +#define CCM_MISC96 CCM_MISC_REG(CCM_BASE_PTR,96) +#define CCM_MISC_ROOT96_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,96) +#define CCM_MISC_ROOT96_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,96) +#define CCM_MISC_ROOT96_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,96) +#define CCM_POST96 CCM_POST_REG(CCM_BASE_PTR,96) +#define CCM_POST_ROOT96_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,96) +#define CCM_POST_ROOT96_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,96) +#define CCM_POST_ROOT96_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,96) +#define CCM_PRE96 CCM_PRE_REG(CCM_BASE_PTR,96) +#define CCM_PRE_ROOT96_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,96) +#define CCM_PRE_ROOT96_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,96) +#define CCM_PRE_ROOT96_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,96) +#define CCM_ACCESS_CTRL96 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,96) +#define CCM_ACCESS_CTRL_ROOT96_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,96) +#define CCM_ACCESS_CTRL_ROOT96_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,96) +#define CCM_ACCESS_CTRL_ROOT96_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,96) +#define CCM_TARGET_ROOT97 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,97) +#define CCM_TARGET_ROOT97_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,97) +#define CCM_TARGET_ROOT97_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,97) +#define CCM_TARGET_ROOT97_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,97) +#define CCM_MISC97 CCM_MISC_REG(CCM_BASE_PTR,97) +#define CCM_MISC_ROOT97_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,97) +#define CCM_MISC_ROOT97_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,97) +#define CCM_MISC_ROOT97_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,97) +#define CCM_POST97 CCM_POST_REG(CCM_BASE_PTR,97) +#define CCM_POST_ROOT97_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,97) +#define CCM_POST_ROOT97_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,97) +#define CCM_POST_ROOT97_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,97) +#define CCM_PRE97 CCM_PRE_REG(CCM_BASE_PTR,97) +#define CCM_PRE_ROOT97_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,97) +#define CCM_PRE_ROOT97_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,97) +#define CCM_PRE_ROOT97_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,97) +#define CCM_ACCESS_CTRL97 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,97) +#define CCM_ACCESS_CTRL_ROOT97_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,97) +#define CCM_ACCESS_CTRL_ROOT97_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,97) +#define CCM_ACCESS_CTRL_ROOT97_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,97) +#define CCM_TARGET_ROOT98 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,98) +#define CCM_TARGET_ROOT98_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,98) +#define CCM_TARGET_ROOT98_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,98) +#define CCM_TARGET_ROOT98_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,98) +#define CCM_MISC98 CCM_MISC_REG(CCM_BASE_PTR,98) +#define CCM_MISC_ROOT98_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,98) +#define CCM_MISC_ROOT98_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,98) +#define CCM_MISC_ROOT98_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,98) +#define CCM_POST98 CCM_POST_REG(CCM_BASE_PTR,98) +#define CCM_POST_ROOT98_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,98) +#define CCM_POST_ROOT98_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,98) +#define CCM_POST_ROOT98_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,98) +#define CCM_PRE98 CCM_PRE_REG(CCM_BASE_PTR,98) +#define CCM_PRE_ROOT98_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,98) +#define CCM_PRE_ROOT98_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,98) +#define CCM_PRE_ROOT98_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,98) +#define CCM_ACCESS_CTRL98 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,98) +#define CCM_ACCESS_CTRL_ROOT98_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,98) +#define CCM_ACCESS_CTRL_ROOT98_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,98) +#define CCM_ACCESS_CTRL_ROOT98_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,98) +#define CCM_TARGET_ROOT99 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,99) +#define CCM_TARGET_ROOT99_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,99) +#define CCM_TARGET_ROOT99_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,99) +#define CCM_TARGET_ROOT99_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,99) +#define CCM_MISC99 CCM_MISC_REG(CCM_BASE_PTR,99) +#define CCM_MISC_ROOT99_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,99) +#define CCM_MISC_ROOT99_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,99) +#define CCM_MISC_ROOT99_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,99) +#define CCM_POST99 CCM_POST_REG(CCM_BASE_PTR,99) +#define CCM_POST_ROOT99_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,99) +#define CCM_POST_ROOT99_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,99) +#define CCM_POST_ROOT99_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,99) +#define CCM_PRE99 CCM_PRE_REG(CCM_BASE_PTR,99) +#define CCM_PRE_ROOT99_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,99) +#define CCM_PRE_ROOT99_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,99) +#define CCM_PRE_ROOT99_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,99) +#define CCM_ACCESS_CTRL99 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,99) +#define CCM_ACCESS_CTRL_ROOT99_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,99) +#define CCM_ACCESS_CTRL_ROOT99_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,99) +#define CCM_ACCESS_CTRL_ROOT99_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,99) +#define CCM_TARGET_ROOT100 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,100) +#define CCM_TARGET_ROOT100_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,100) +#define CCM_TARGET_ROOT100_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,100) +#define CCM_TARGET_ROOT100_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,100) +#define CCM_MISC100 CCM_MISC_REG(CCM_BASE_PTR,100) +#define CCM_MISC_ROOT100_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,100) +#define CCM_MISC_ROOT100_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,100) +#define CCM_MISC_ROOT100_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,100) +#define CCM_POST100 CCM_POST_REG(CCM_BASE_PTR,100) +#define CCM_POST_ROOT100_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,100) +#define CCM_POST_ROOT100_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,100) +#define CCM_POST_ROOT100_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,100) +#define CCM_PRE100 CCM_PRE_REG(CCM_BASE_PTR,100) +#define CCM_PRE_ROOT100_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,100) +#define CCM_PRE_ROOT100_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,100) +#define CCM_PRE_ROOT100_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,100) +#define CCM_ACCESS_CTRL100 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,100) +#define CCM_ACCESS_CTRL_ROOT100_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,100) +#define CCM_ACCESS_CTRL_ROOT100_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,100) +#define CCM_ACCESS_CTRL_ROOT100_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,100) +#define CCM_TARGET_ROOT101 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,101) +#define CCM_TARGET_ROOT101_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,101) +#define CCM_TARGET_ROOT101_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,101) +#define CCM_TARGET_ROOT101_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,101) +#define CCM_MISC101 CCM_MISC_REG(CCM_BASE_PTR,101) +#define CCM_MISC_ROOT101_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,101) +#define CCM_MISC_ROOT101_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,101) +#define CCM_MISC_ROOT101_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,101) +#define CCM_POST101 CCM_POST_REG(CCM_BASE_PTR,101) +#define CCM_POST_ROOT101_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,101) +#define CCM_POST_ROOT101_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,101) +#define CCM_POST_ROOT101_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,101) +#define CCM_PRE101 CCM_PRE_REG(CCM_BASE_PTR,101) +#define CCM_PRE_ROOT101_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,101) +#define CCM_PRE_ROOT101_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,101) +#define CCM_PRE_ROOT101_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,101) +#define CCM_ACCESS_CTRL101 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,101) +#define CCM_ACCESS_CTRL_ROOT101_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,101) +#define CCM_ACCESS_CTRL_ROOT101_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,101) +#define CCM_ACCESS_CTRL_ROOT101_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,101) +#define CCM_TARGET_ROOT102 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,102) +#define CCM_TARGET_ROOT102_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,102) +#define CCM_TARGET_ROOT102_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,102) +#define CCM_TARGET_ROOT102_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,102) +#define CCM_MISC102 CCM_MISC_REG(CCM_BASE_PTR,102) +#define CCM_MISC_ROOT102_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,102) +#define CCM_MISC_ROOT102_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,102) +#define CCM_MISC_ROOT102_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,102) +#define CCM_POST102 CCM_POST_REG(CCM_BASE_PTR,102) +#define CCM_POST_ROOT102_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,102) +#define CCM_POST_ROOT102_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,102) +#define CCM_POST_ROOT102_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,102) +#define CCM_PRE102 CCM_PRE_REG(CCM_BASE_PTR,102) +#define CCM_PRE_ROOT102_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,102) +#define CCM_PRE_ROOT102_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,102) +#define CCM_PRE_ROOT102_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,102) +#define CCM_ACCESS_CTRL102 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,102) +#define CCM_ACCESS_CTRL_ROOT102_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,102) +#define CCM_ACCESS_CTRL_ROOT102_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,102) +#define CCM_ACCESS_CTRL_ROOT102_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,102) +#define CCM_TARGET_ROOT103 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,103) +#define CCM_TARGET_ROOT103_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,103) +#define CCM_TARGET_ROOT103_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,103) +#define CCM_TARGET_ROOT103_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,103) +#define CCM_MISC103 CCM_MISC_REG(CCM_BASE_PTR,103) +#define CCM_MISC_ROOT103_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,103) +#define CCM_MISC_ROOT103_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,103) +#define CCM_MISC_ROOT103_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,103) +#define CCM_POST103 CCM_POST_REG(CCM_BASE_PTR,103) +#define CCM_POST_ROOT103_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,103) +#define CCM_POST_ROOT103_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,103) +#define CCM_POST_ROOT103_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,103) +#define CCM_PRE103 CCM_PRE_REG(CCM_BASE_PTR,103) +#define CCM_PRE_ROOT103_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,103) +#define CCM_PRE_ROOT103_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,103) +#define CCM_PRE_ROOT103_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,103) +#define CCM_ACCESS_CTRL103 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,103) +#define CCM_ACCESS_CTRL_ROOT103_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,103) +#define CCM_ACCESS_CTRL_ROOT103_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,103) +#define CCM_ACCESS_CTRL_ROOT103_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,103) +#define CCM_TARGET_ROOT104 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,104) +#define CCM_TARGET_ROOT104_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,104) +#define CCM_TARGET_ROOT104_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,104) +#define CCM_TARGET_ROOT104_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,104) +#define CCM_MISC104 CCM_MISC_REG(CCM_BASE_PTR,104) +#define CCM_MISC_ROOT104_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,104) +#define CCM_MISC_ROOT104_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,104) +#define CCM_MISC_ROOT104_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,104) +#define CCM_POST104 CCM_POST_REG(CCM_BASE_PTR,104) +#define CCM_POST_ROOT104_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,104) +#define CCM_POST_ROOT104_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,104) +#define CCM_POST_ROOT104_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,104) +#define CCM_PRE104 CCM_PRE_REG(CCM_BASE_PTR,104) +#define CCM_PRE_ROOT104_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,104) +#define CCM_PRE_ROOT104_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,104) +#define CCM_PRE_ROOT104_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,104) +#define CCM_ACCESS_CTRL104 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,104) +#define CCM_ACCESS_CTRL_ROOT104_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,104) +#define CCM_ACCESS_CTRL_ROOT104_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,104) +#define CCM_ACCESS_CTRL_ROOT104_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,104) +#define CCM_TARGET_ROOT105 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,105) +#define CCM_TARGET_ROOT105_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,105) +#define CCM_TARGET_ROOT105_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,105) +#define CCM_TARGET_ROOT105_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,105) +#define CCM_MISC105 CCM_MISC_REG(CCM_BASE_PTR,105) +#define CCM_MISC_ROOT105_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,105) +#define CCM_MISC_ROOT105_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,105) +#define CCM_MISC_ROOT105_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,105) +#define CCM_POST105 CCM_POST_REG(CCM_BASE_PTR,105) +#define CCM_POST_ROOT105_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,105) +#define CCM_POST_ROOT105_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,105) +#define CCM_POST_ROOT105_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,105) +#define CCM_PRE105 CCM_PRE_REG(CCM_BASE_PTR,105) +#define CCM_PRE_ROOT105_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,105) +#define CCM_PRE_ROOT105_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,105) +#define CCM_PRE_ROOT105_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,105) +#define CCM_ACCESS_CTRL105 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,105) +#define CCM_ACCESS_CTRL_ROOT105_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,105) +#define CCM_ACCESS_CTRL_ROOT105_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,105) +#define CCM_ACCESS_CTRL_ROOT105_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,105) +#define CCM_TARGET_ROOT106 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,106) +#define CCM_TARGET_ROOT106_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,106) +#define CCM_TARGET_ROOT106_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,106) +#define CCM_TARGET_ROOT106_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,106) +#define CCM_MISC106 CCM_MISC_REG(CCM_BASE_PTR,106) +#define CCM_MISC_ROOT106_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,106) +#define CCM_MISC_ROOT106_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,106) +#define CCM_MISC_ROOT106_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,106) +#define CCM_POST106 CCM_POST_REG(CCM_BASE_PTR,106) +#define CCM_POST_ROOT106_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,106) +#define CCM_POST_ROOT106_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,106) +#define CCM_POST_ROOT106_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,106) +#define CCM_PRE106 CCM_PRE_REG(CCM_BASE_PTR,106) +#define CCM_PRE_ROOT106_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,106) +#define CCM_PRE_ROOT106_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,106) +#define CCM_PRE_ROOT106_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,106) +#define CCM_ACCESS_CTRL106 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,106) +#define CCM_ACCESS_CTRL_ROOT106_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,106) +#define CCM_ACCESS_CTRL_ROOT106_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,106) +#define CCM_ACCESS_CTRL_ROOT106_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,106) +#define CCM_TARGET_ROOT107 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,107) +#define CCM_TARGET_ROOT107_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,107) +#define CCM_TARGET_ROOT107_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,107) +#define CCM_TARGET_ROOT107_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,107) +#define CCM_MISC107 CCM_MISC_REG(CCM_BASE_PTR,107) +#define CCM_MISC_ROOT107_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,107) +#define CCM_MISC_ROOT107_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,107) +#define CCM_MISC_ROOT107_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,107) +#define CCM_POST107 CCM_POST_REG(CCM_BASE_PTR,107) +#define CCM_POST_ROOT107_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,107) +#define CCM_POST_ROOT107_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,107) +#define CCM_POST_ROOT107_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,107) +#define CCM_PRE107 CCM_PRE_REG(CCM_BASE_PTR,107) +#define CCM_PRE_ROOT107_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,107) +#define CCM_PRE_ROOT107_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,107) +#define CCM_PRE_ROOT107_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,107) +#define CCM_ACCESS_CTRL107 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,107) +#define CCM_ACCESS_CTRL_ROOT107_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,107) +#define CCM_ACCESS_CTRL_ROOT107_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,107) +#define CCM_ACCESS_CTRL_ROOT107_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,107) +#define CCM_TARGET_ROOT108 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,108) +#define CCM_TARGET_ROOT108_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,108) +#define CCM_TARGET_ROOT108_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,108) +#define CCM_TARGET_ROOT108_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,108) +#define CCM_MISC108 CCM_MISC_REG(CCM_BASE_PTR,108) +#define CCM_MISC_ROOT108_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,108) +#define CCM_MISC_ROOT108_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,108) +#define CCM_MISC_ROOT108_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,108) +#define CCM_POST108 CCM_POST_REG(CCM_BASE_PTR,108) +#define CCM_POST_ROOT108_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,108) +#define CCM_POST_ROOT108_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,108) +#define CCM_POST_ROOT108_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,108) +#define CCM_PRE108 CCM_PRE_REG(CCM_BASE_PTR,108) +#define CCM_PRE_ROOT108_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,108) +#define CCM_PRE_ROOT108_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,108) +#define CCM_PRE_ROOT108_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,108) +#define CCM_ACCESS_CTRL108 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,108) +#define CCM_ACCESS_CTRL_ROOT108_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,108) +#define CCM_ACCESS_CTRL_ROOT108_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,108) +#define CCM_ACCESS_CTRL_ROOT108_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,108) +#define CCM_TARGET_ROOT109 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,109) +#define CCM_TARGET_ROOT109_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,109) +#define CCM_TARGET_ROOT109_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,109) +#define CCM_TARGET_ROOT109_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,109) +#define CCM_MISC109 CCM_MISC_REG(CCM_BASE_PTR,109) +#define CCM_MISC_ROOT109_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,109) +#define CCM_MISC_ROOT109_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,109) +#define CCM_MISC_ROOT109_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,109) +#define CCM_POST109 CCM_POST_REG(CCM_BASE_PTR,109) +#define CCM_POST_ROOT109_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,109) +#define CCM_POST_ROOT109_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,109) +#define CCM_POST_ROOT109_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,109) +#define CCM_PRE109 CCM_PRE_REG(CCM_BASE_PTR,109) +#define CCM_PRE_ROOT109_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,109) +#define CCM_PRE_ROOT109_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,109) +#define CCM_PRE_ROOT109_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,109) +#define CCM_ACCESS_CTRL109 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,109) +#define CCM_ACCESS_CTRL_ROOT109_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,109) +#define CCM_ACCESS_CTRL_ROOT109_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,109) +#define CCM_ACCESS_CTRL_ROOT109_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,109) +#define CCM_TARGET_ROOT110 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,110) +#define CCM_TARGET_ROOT110_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,110) +#define CCM_TARGET_ROOT110_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,110) +#define CCM_TARGET_ROOT110_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,110) +#define CCM_MISC110 CCM_MISC_REG(CCM_BASE_PTR,110) +#define CCM_MISC_ROOT110_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,110) +#define CCM_MISC_ROOT110_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,110) +#define CCM_MISC_ROOT110_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,110) +#define CCM_POST110 CCM_POST_REG(CCM_BASE_PTR,110) +#define CCM_POST_ROOT110_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,110) +#define CCM_POST_ROOT110_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,110) +#define CCM_POST_ROOT110_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,110) +#define CCM_PRE110 CCM_PRE_REG(CCM_BASE_PTR,110) +#define CCM_PRE_ROOT110_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,110) +#define CCM_PRE_ROOT110_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,110) +#define CCM_PRE_ROOT110_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,110) +#define CCM_ACCESS_CTRL110 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,110) +#define CCM_ACCESS_CTRL_ROOT110_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,110) +#define CCM_ACCESS_CTRL_ROOT110_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,110) +#define CCM_ACCESS_CTRL_ROOT110_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,110) +#define CCM_TARGET_ROOT111 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,111) +#define CCM_TARGET_ROOT111_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,111) +#define CCM_TARGET_ROOT111_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,111) +#define CCM_TARGET_ROOT111_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,111) +#define CCM_MISC111 CCM_MISC_REG(CCM_BASE_PTR,111) +#define CCM_MISC_ROOT111_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,111) +#define CCM_MISC_ROOT111_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,111) +#define CCM_MISC_ROOT111_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,111) +#define CCM_POST111 CCM_POST_REG(CCM_BASE_PTR,111) +#define CCM_POST_ROOT111_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,111) +#define CCM_POST_ROOT111_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,111) +#define CCM_POST_ROOT111_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,111) +#define CCM_PRE111 CCM_PRE_REG(CCM_BASE_PTR,111) +#define CCM_PRE_ROOT111_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,111) +#define CCM_PRE_ROOT111_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,111) +#define CCM_PRE_ROOT111_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,111) +#define CCM_ACCESS_CTRL111 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,111) +#define CCM_ACCESS_CTRL_ROOT111_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,111) +#define CCM_ACCESS_CTRL_ROOT111_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,111) +#define CCM_ACCESS_CTRL_ROOT111_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,111) +#define CCM_TARGET_ROOT112 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,112) +#define CCM_TARGET_ROOT112_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,112) +#define CCM_TARGET_ROOT112_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,112) +#define CCM_TARGET_ROOT112_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,112) +#define CCM_MISC112 CCM_MISC_REG(CCM_BASE_PTR,112) +#define CCM_MISC_ROOT112_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,112) +#define CCM_MISC_ROOT112_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,112) +#define CCM_MISC_ROOT112_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,112) +#define CCM_POST112 CCM_POST_REG(CCM_BASE_PTR,112) +#define CCM_POST_ROOT112_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,112) +#define CCM_POST_ROOT112_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,112) +#define CCM_POST_ROOT112_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,112) +#define CCM_PRE112 CCM_PRE_REG(CCM_BASE_PTR,112) +#define CCM_PRE_ROOT112_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,112) +#define CCM_PRE_ROOT112_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,112) +#define CCM_PRE_ROOT112_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,112) +#define CCM_ACCESS_CTRL112 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,112) +#define CCM_ACCESS_CTRL_ROOT112_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,112) +#define CCM_ACCESS_CTRL_ROOT112_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,112) +#define CCM_ACCESS_CTRL_ROOT112_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,112) +#define CCM_TARGET_ROOT113 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,113) +#define CCM_TARGET_ROOT113_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,113) +#define CCM_TARGET_ROOT113_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,113) +#define CCM_TARGET_ROOT113_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,113) +#define CCM_MISC113 CCM_MISC_REG(CCM_BASE_PTR,113) +#define CCM_MISC_ROOT113_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,113) +#define CCM_MISC_ROOT113_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,113) +#define CCM_MISC_ROOT113_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,113) +#define CCM_POST113 CCM_POST_REG(CCM_BASE_PTR,113) +#define CCM_POST_ROOT113_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,113) +#define CCM_POST_ROOT113_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,113) +#define CCM_POST_ROOT113_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,113) +#define CCM_PRE113 CCM_PRE_REG(CCM_BASE_PTR,113) +#define CCM_PRE_ROOT113_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,113) +#define CCM_PRE_ROOT113_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,113) +#define CCM_PRE_ROOT113_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,113) +#define CCM_ACCESS_CTRL113 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,113) +#define CCM_ACCESS_CTRL_ROOT113_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,113) +#define CCM_ACCESS_CTRL_ROOT113_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,113) +#define CCM_ACCESS_CTRL_ROOT113_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,113) +#define CCM_TARGET_ROOT114 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,114) +#define CCM_TARGET_ROOT114_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,114) +#define CCM_TARGET_ROOT114_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,114) +#define CCM_TARGET_ROOT114_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,114) +#define CCM_MISC114 CCM_MISC_REG(CCM_BASE_PTR,114) +#define CCM_MISC_ROOT114_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,114) +#define CCM_MISC_ROOT114_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,114) +#define CCM_MISC_ROOT114_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,114) +#define CCM_POST114 CCM_POST_REG(CCM_BASE_PTR,114) +#define CCM_POST_ROOT114_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,114) +#define CCM_POST_ROOT114_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,114) +#define CCM_POST_ROOT114_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,114) +#define CCM_PRE114 CCM_PRE_REG(CCM_BASE_PTR,114) +#define CCM_PRE_ROOT114_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,114) +#define CCM_PRE_ROOT114_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,114) +#define CCM_PRE_ROOT114_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,114) +#define CCM_ACCESS_CTRL114 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,114) +#define CCM_ACCESS_CTRL_ROOT114_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,114) +#define CCM_ACCESS_CTRL_ROOT114_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,114) +#define CCM_ACCESS_CTRL_ROOT114_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,114) +#define CCM_TARGET_ROOT115 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,115) +#define CCM_TARGET_ROOT115_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,115) +#define CCM_TARGET_ROOT115_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,115) +#define CCM_TARGET_ROOT115_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,115) +#define CCM_MISC115 CCM_MISC_REG(CCM_BASE_PTR,115) +#define CCM_MISC_ROOT115_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,115) +#define CCM_MISC_ROOT115_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,115) +#define CCM_MISC_ROOT115_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,115) +#define CCM_POST115 CCM_POST_REG(CCM_BASE_PTR,115) +#define CCM_POST_ROOT115_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,115) +#define CCM_POST_ROOT115_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,115) +#define CCM_POST_ROOT115_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,115) +#define CCM_PRE115 CCM_PRE_REG(CCM_BASE_PTR,115) +#define CCM_PRE_ROOT115_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,115) +#define CCM_PRE_ROOT115_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,115) +#define CCM_PRE_ROOT115_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,115) +#define CCM_ACCESS_CTRL115 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,115) +#define CCM_ACCESS_CTRL_ROOT115_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,115) +#define CCM_ACCESS_CTRL_ROOT115_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,115) +#define CCM_ACCESS_CTRL_ROOT115_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,115) +#define CCM_TARGET_ROOT116 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,116) +#define CCM_TARGET_ROOT116_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,116) +#define CCM_TARGET_ROOT116_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,116) +#define CCM_TARGET_ROOT116_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,116) +#define CCM_MISC116 CCM_MISC_REG(CCM_BASE_PTR,116) +#define CCM_MISC_ROOT116_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,116) +#define CCM_MISC_ROOT116_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,116) +#define CCM_MISC_ROOT116_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,116) +#define CCM_POST116 CCM_POST_REG(CCM_BASE_PTR,116) +#define CCM_POST_ROOT116_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,116) +#define CCM_POST_ROOT116_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,116) +#define CCM_POST_ROOT116_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,116) +#define CCM_PRE116 CCM_PRE_REG(CCM_BASE_PTR,116) +#define CCM_PRE_ROOT116_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,116) +#define CCM_PRE_ROOT116_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,116) +#define CCM_PRE_ROOT116_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,116) +#define CCM_ACCESS_CTRL116 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,116) +#define CCM_ACCESS_CTRL_ROOT116_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,116) +#define CCM_ACCESS_CTRL_ROOT116_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,116) +#define CCM_ACCESS_CTRL_ROOT116_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,116) +#define CCM_TARGET_ROOT117 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,117) +#define CCM_TARGET_ROOT117_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,117) +#define CCM_TARGET_ROOT117_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,117) +#define CCM_TARGET_ROOT117_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,117) +#define CCM_MISC117 CCM_MISC_REG(CCM_BASE_PTR,117) +#define CCM_MISC_ROOT117_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,117) +#define CCM_MISC_ROOT117_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,117) +#define CCM_MISC_ROOT117_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,117) +#define CCM_POST117 CCM_POST_REG(CCM_BASE_PTR,117) +#define CCM_POST_ROOT117_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,117) +#define CCM_POST_ROOT117_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,117) +#define CCM_POST_ROOT117_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,117) +#define CCM_PRE117 CCM_PRE_REG(CCM_BASE_PTR,117) +#define CCM_PRE_ROOT117_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,117) +#define CCM_PRE_ROOT117_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,117) +#define CCM_PRE_ROOT117_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,117) +#define CCM_ACCESS_CTRL117 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,117) +#define CCM_ACCESS_CTRL_ROOT117_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,117) +#define CCM_ACCESS_CTRL_ROOT117_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,117) +#define CCM_ACCESS_CTRL_ROOT117_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,117) +#define CCM_TARGET_ROOT118 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,118) +#define CCM_TARGET_ROOT118_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,118) +#define CCM_TARGET_ROOT118_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,118) +#define CCM_TARGET_ROOT118_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,118) +#define CCM_MISC118 CCM_MISC_REG(CCM_BASE_PTR,118) +#define CCM_MISC_ROOT118_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,118) +#define CCM_MISC_ROOT118_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,118) +#define CCM_MISC_ROOT118_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,118) +#define CCM_POST118 CCM_POST_REG(CCM_BASE_PTR,118) +#define CCM_POST_ROOT118_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,118) +#define CCM_POST_ROOT118_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,118) +#define CCM_POST_ROOT118_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,118) +#define CCM_PRE118 CCM_PRE_REG(CCM_BASE_PTR,118) +#define CCM_PRE_ROOT118_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,118) +#define CCM_PRE_ROOT118_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,118) +#define CCM_PRE_ROOT118_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,118) +#define CCM_ACCESS_CTRL118 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,118) +#define CCM_ACCESS_CTRL_ROOT118_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,118) +#define CCM_ACCESS_CTRL_ROOT118_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,118) +#define CCM_ACCESS_CTRL_ROOT118_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,118) +#define CCM_TARGET_ROOT119 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,119) +#define CCM_TARGET_ROOT119_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,119) +#define CCM_TARGET_ROOT119_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,119) +#define CCM_TARGET_ROOT119_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,119) +#define CCM_MISC119 CCM_MISC_REG(CCM_BASE_PTR,119) +#define CCM_MISC_ROOT119_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,119) +#define CCM_MISC_ROOT119_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,119) +#define CCM_MISC_ROOT119_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,119) +#define CCM_POST119 CCM_POST_REG(CCM_BASE_PTR,119) +#define CCM_POST_ROOT119_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,119) +#define CCM_POST_ROOT119_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,119) +#define CCM_POST_ROOT119_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,119) +#define CCM_PRE119 CCM_PRE_REG(CCM_BASE_PTR,119) +#define CCM_PRE_ROOT119_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,119) +#define CCM_PRE_ROOT119_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,119) +#define CCM_PRE_ROOT119_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,119) +#define CCM_ACCESS_CTRL119 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,119) +#define CCM_ACCESS_CTRL_ROOT119_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,119) +#define CCM_ACCESS_CTRL_ROOT119_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,119) +#define CCM_ACCESS_CTRL_ROOT119_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,119) +#define CCM_TARGET_ROOT120 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,120) +#define CCM_TARGET_ROOT120_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,120) +#define CCM_TARGET_ROOT120_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,120) +#define CCM_TARGET_ROOT120_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,120) +#define CCM_MISC120 CCM_MISC_REG(CCM_BASE_PTR,120) +#define CCM_MISC_ROOT120_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,120) +#define CCM_MISC_ROOT120_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,120) +#define CCM_MISC_ROOT120_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,120) +#define CCM_POST120 CCM_POST_REG(CCM_BASE_PTR,120) +#define CCM_POST_ROOT120_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,120) +#define CCM_POST_ROOT120_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,120) +#define CCM_POST_ROOT120_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,120) +#define CCM_PRE120 CCM_PRE_REG(CCM_BASE_PTR,120) +#define CCM_PRE_ROOT120_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,120) +#define CCM_PRE_ROOT120_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,120) +#define CCM_PRE_ROOT120_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,120) +#define CCM_ACCESS_CTRL120 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,120) +#define CCM_ACCESS_CTRL_ROOT120_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,120) +#define CCM_ACCESS_CTRL_ROOT120_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,120) +#define CCM_ACCESS_CTRL_ROOT120_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,120) +#define CCM_TARGET_ROOT121 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,121) +#define CCM_TARGET_ROOT121_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,121) +#define CCM_TARGET_ROOT121_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,121) +#define CCM_TARGET_ROOT121_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,121) +#define CCM_MISC121 CCM_MISC_REG(CCM_BASE_PTR,121) +#define CCM_MISC_ROOT121_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,121) +#define CCM_MISC_ROOT121_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,121) +#define CCM_MISC_ROOT121_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,121) +#define CCM_POST121 CCM_POST_REG(CCM_BASE_PTR,121) +#define CCM_POST_ROOT121_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,121) +#define CCM_POST_ROOT121_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,121) +#define CCM_POST_ROOT121_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,121) +#define CCM_PRE121 CCM_PRE_REG(CCM_BASE_PTR,121) +#define CCM_PRE_ROOT121_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,121) +#define CCM_PRE_ROOT121_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,121) +#define CCM_PRE_ROOT121_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,121) +#define CCM_ACCESS_CTRL121 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,121) +#define CCM_ACCESS_CTRL_ROOT121_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,121) +#define CCM_ACCESS_CTRL_ROOT121_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,121) +#define CCM_ACCESS_CTRL_ROOT121_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,121) +#define CCM_TARGET_ROOT122 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,122) +#define CCM_TARGET_ROOT122_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,122) +#define CCM_TARGET_ROOT122_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,122) +#define CCM_TARGET_ROOT122_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,122) +#define CCM_MISC122 CCM_MISC_REG(CCM_BASE_PTR,122) +#define CCM_MISC_ROOT122_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,122) +#define CCM_MISC_ROOT122_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,122) +#define CCM_MISC_ROOT122_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,122) +#define CCM_POST122 CCM_POST_REG(CCM_BASE_PTR,122) +#define CCM_POST_ROOT122_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,122) +#define CCM_POST_ROOT122_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,122) +#define CCM_POST_ROOT122_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,122) +#define CCM_PRE122 CCM_PRE_REG(CCM_BASE_PTR,122) +#define CCM_PRE_ROOT122_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,122) +#define CCM_PRE_ROOT122_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,122) +#define CCM_PRE_ROOT122_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,122) +#define CCM_ACCESS_CTRL122 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,122) +#define CCM_ACCESS_CTRL_ROOT122_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,122) +#define CCM_ACCESS_CTRL_ROOT122_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,122) +#define CCM_ACCESS_CTRL_ROOT122_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,122) +#define CCM_TARGET_ROOT123 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,123) +#define CCM_TARGET_ROOT123_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,123) +#define CCM_TARGET_ROOT123_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,123) +#define CCM_TARGET_ROOT123_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,123) +#define CCM_MISC123 CCM_MISC_REG(CCM_BASE_PTR,123) +#define CCM_MISC_ROOT123_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,123) +#define CCM_MISC_ROOT123_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,123) +#define CCM_MISC_ROOT123_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,123) +#define CCM_POST123 CCM_POST_REG(CCM_BASE_PTR,123) +#define CCM_POST_ROOT123_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,123) +#define CCM_POST_ROOT123_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,123) +#define CCM_POST_ROOT123_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,123) +#define CCM_PRE123 CCM_PRE_REG(CCM_BASE_PTR,123) +#define CCM_PRE_ROOT123_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,123) +#define CCM_PRE_ROOT123_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,123) +#define CCM_PRE_ROOT123_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,123) +#define CCM_ACCESS_CTRL123 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,123) +#define CCM_ACCESS_CTRL_ROOT123_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,123) +#define CCM_ACCESS_CTRL_ROOT123_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,123) +#define CCM_ACCESS_CTRL_ROOT123_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,123) +#define CCM_TARGET_ROOT124 CCM_TARGET_ROOT_REG(CCM_BASE_PTR,124) +#define CCM_TARGET_ROOT124_SET CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,124) +#define CCM_TARGET_ROOT124_CLR CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,124) +#define CCM_TARGET_ROOT124_TOG CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,124) +#define CCM_MISC124 CCM_MISC_REG(CCM_BASE_PTR,124) +#define CCM_MISC_ROOT124_SET CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,124) +#define CCM_MISC_ROOT124_CLR CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,124) +#define CCM_MISC_ROOT124_TOG CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,124) +#define CCM_POST124 CCM_POST_REG(CCM_BASE_PTR,124) +#define CCM_POST_ROOT124_SET CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,124) +#define CCM_POST_ROOT124_CLR CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,124) +#define CCM_POST_ROOT124_TOG CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,124) +#define CCM_PRE124 CCM_PRE_REG(CCM_BASE_PTR,124) +#define CCM_PRE_ROOT124_SET CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,124) +#define CCM_PRE_ROOT124_CLR CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,124) +#define CCM_PRE_ROOT124_TOG CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,124) +#define CCM_ACCESS_CTRL124 CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,124) +#define CCM_ACCESS_CTRL_ROOT124_SET CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,124) +#define CCM_ACCESS_CTRL_ROOT124_CLR CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,124) +#define CCM_ACCESS_CTRL_ROOT124_TOG CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,124) +/* CCM - Register array accessors */ +#define CCM_PLL_CTRL(index) CCM_PLL_CTRL_REG(CCM_BASE_PTR,index) +#define CCM_PLL_CTRL_SET(index) CCM_PLL_CTRL_SET_REG(CCM_BASE_PTR,index) +#define CCM_PLL_CTRL_CLR(index) CCM_PLL_CTRL_CLR_REG(CCM_BASE_PTR,index) +#define CCM_PLL_CTRL_TOG(index) CCM_PLL_CTRL_TOG_REG(CCM_BASE_PTR,index) +#define CCM_CCGR(index) CCM_CCGR_REG(CCM_BASE_PTR,index) +#define CCM_CCGR_SET(index) CCM_CCGR_SET_REG(CCM_BASE_PTR,index) +#define CCM_CCGR_CLR(index) CCM_CCGR_CLR_REG(CCM_BASE_PTR,index) +#define CCM_CCGR_TOG(index) CCM_CCGR_TOG_REG(CCM_BASE_PTR,index) +#define CCM_TARGET_ROOT(index) CCM_TARGET_ROOT_REG(CCM_BASE_PTR,index) +#define CCM_TARGET_ROOT_SET(index) CCM_TARGET_ROOT_SET_REG(CCM_BASE_PTR,index) +#define CCM_TARGET_ROOT_CLR(index) CCM_TARGET_ROOT_CLR_REG(CCM_BASE_PTR,index) +#define CCM_TARGET_ROOT_TOG(index) CCM_TARGET_ROOT_TOG_REG(CCM_BASE_PTR,index) +#define CCM_MISC(index) CCM_MISC_REG(CCM_BASE_PTR,index) +#define CCM_MISC_ROOT_SET(index) CCM_MISC_ROOT_SET_REG(CCM_BASE_PTR,index) +#define CCM_MISC_ROOT_CLR(index) CCM_MISC_ROOT_CLR_REG(CCM_BASE_PTR,index) +#define CCM_MISC_ROOT_TOG(index) CCM_MISC_ROOT_TOG_REG(CCM_BASE_PTR,index) +#define CCM_POST(index) CCM_POST_REG(CCM_BASE_PTR,index) +#define CCM_POST_ROOT_SET(index) CCM_POST_ROOT_SET_REG(CCM_BASE_PTR,index) +#define CCM_POST_ROOT_CLR(index) CCM_POST_ROOT_CLR_REG(CCM_BASE_PTR,index) +#define CCM_POST_ROOT_TOG(index) CCM_POST_ROOT_TOG_REG(CCM_BASE_PTR,index) +#define CCM_PRE(index) CCM_PRE_REG(CCM_BASE_PTR,index) +#define CCM_PRE_ROOT_SET(index) CCM_PRE_ROOT_SET_REG(CCM_BASE_PTR,index) +#define CCM_PRE_ROOT_CLR(index) CCM_PRE_ROOT_CLR_REG(CCM_BASE_PTR,index) +#define CCM_PRE_ROOT_TOG(index) CCM_PRE_ROOT_TOG_REG(CCM_BASE_PTR,index) +#define CCM_ACCESS_CTRL(index) CCM_ACCESS_CTRL_REG(CCM_BASE_PTR,index) +#define CCM_ACCESS_CTRL_ROOT_SET(index) CCM_ACCESS_CTRL_ROOT_SET_REG(CCM_BASE_PTR,index) +#define CCM_ACCESS_CTRL_ROOT_CLR(index) CCM_ACCESS_CTRL_ROOT_CLR_REG(CCM_BASE_PTR,index) +#define CCM_ACCESS_CTRL_ROOT_TOG(index) CCM_ACCESS_CTRL_ROOT_TOG_REG(CCM_BASE_PTR,index) /*! * @} */ /* end of group CCM_Register_Accessor_Macros */ @@ -60247,7 +8550,6 @@ typedef struct { * @} */ /* end of group CCM_Peripheral */ - /* ---------------------------------------------------------------------------- -- CCM_ANALOG Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -60315,7 +8617,6 @@ typedef struct { __IO uint32_t CLK_MISC0_CLR; /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x178 */ __IO uint32_t CLK_MISC0_TOG; /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x17C */ } CCM_ANALOG_Type, *CCM_ANALOG_MemMapPtr; - /* ---------------------------------------------------------------------------- -- CCM_ANALOG - Register accessor macros ---------------------------------------------------------------------------- */ @@ -60376,8 +8677,6 @@ typedef struct { /*! * @} */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- CCM_ANALOG Register Masks ---------------------------------------------------------------------------- */ @@ -61793,18 +10092,16 @@ typedef struct { * @} */ /* end of group CCM_ANALOG_Register_Masks */ - /* CCM_ANALOG - Peripheral instance base addresses */ /** Peripheral CCM_ANALOG base address */ #define CCM_ANALOG_BASE (0x30360000u) /** Peripheral CCM_ANALOG base pointer */ #define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) #define CCM_ANALOG_BASE_PTR (CCM_ANALOG) -/** Array initializer of CCM_ANALOG peripheral base adresses */ +/** Array initializer of CCM_ANALOG peripheral base addresses */ #define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } /** Array initializer of CCM_ANALOG peripheral base pointers */ #define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } - /* ---------------------------------------------------------------------------- -- CCM_ANALOG - Register accessor macros ---------------------------------------------------------------------------- */ @@ -61862,7 +10159,6 @@ typedef struct { #define CCM_ANALOG_CLK_MISC0_SET CCM_ANALOG_CLK_MISC0_SET_REG(CCM_ANALOG_BASE_PTR) #define CCM_ANALOG_CLK_MISC0_CLR CCM_ANALOG_CLK_MISC0_CLR_REG(CCM_ANALOG_BASE_PTR) #define CCM_ANALOG_CLK_MISC0_TOG CCM_ANALOG_CLK_MISC0_TOG_REG(CCM_ANALOG_BASE_PTR) - /*! * @} */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ @@ -61872,7 +10168,6 @@ typedef struct { * @} */ /* end of group CCM_ANALOG_Peripheral */ - /* ---------------------------------------------------------------------------- -- CSI Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -61900,9 +10195,7 @@ typedef struct { __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ uint8_t RESERVED_1[16]; __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ - __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ } CSI_Type, *CSI_MemMapPtr; - /* ---------------------------------------------------------------------------- -- CSI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -61928,13 +10221,10 @@ typedef struct { #define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) #define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) #define CSI_CSICR18_REG(base) ((base)->CSICR18) -#define CSI_CSICR19_REG(base) ((base)->CSICR19) /*! * @} */ /* end of group CSI_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- CSI Register Masks ---------------------------------------------------------------------------- */ @@ -62122,6 +10412,9 @@ typedef struct { #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK 0xFFFFu #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT 0 #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT))&CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK 0xFFFF0000u +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT 16 +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT))&CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) /* CSIIMAG_PARA Bit Fields */ #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK 0xFFFFu #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT 0 @@ -62170,16 +10463,11 @@ typedef struct { #define CSI_CSICR18_MIPI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT))&CSI_CSICR18_MIPI_DATA_FORMAT_MASK) #define CSI_CSICR18_CSI_ENABLE_MASK 0x80000000u #define CSI_CSICR18_CSI_ENABLE_SHIFT 31 -/* CSICR19 Bit Fields */ -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK 0xFFu -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT 0 -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT))&CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) /*! * @} */ /* end of group CSI_Register_Masks */ - /* CSI - Peripheral instance base addresses */ /** Peripheral CSI1 base address */ #define CSI1_BASE (0x30710000u) @@ -62191,11 +10479,10 @@ typedef struct { /** Peripheral CSI2 base pointer */ #define CSI2 ((CSI_Type *)CSI2_BASE) #define CSI2_BASE_PTR (CSI2) -/** Array initializer of CSI peripheral base adresses */ +/** Array initializer of CSI peripheral base addresses */ #define CSI_BASE_ADDRS { CSI1_BASE, CSI2_BASE } /** Array initializer of CSI peripheral base pointers */ #define CSI_BASE_PTRS { CSI1, CSI2 } - /* ---------------------------------------------------------------------------- -- CSI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -62222,7 +10509,6 @@ typedef struct { #define CSI1_CSIFBUF_PARA CSI_CSIFBUF_PARA_REG(CSI1_BASE_PTR) #define CSI1_CSIIMAG_PARA CSI_CSIIMAG_PARA_REG(CSI1_BASE_PTR) #define CSI1_CSICR18 CSI_CSICR18_REG(CSI1_BASE_PTR) -#define CSI1_CSICR19 CSI_CSICR19_REG(CSI1_BASE_PTR) /* CSI2 */ #define CSI2_CSICR1 CSI_CSICR1_REG(CSI2_BASE_PTR) #define CSI2_CSICR2 CSI_CSICR2_REG(CSI2_BASE_PTR) @@ -62238,8 +10524,6 @@ typedef struct { #define CSI2_CSIFBUF_PARA CSI_CSIFBUF_PARA_REG(CSI2_BASE_PTR) #define CSI2_CSIIMAG_PARA CSI_CSIIMAG_PARA_REG(CSI2_BASE_PTR) #define CSI2_CSICR18 CSI_CSICR18_REG(CSI2_BASE_PTR) -#define CSI2_CSICR19 CSI_CSICR19_REG(CSI2_BASE_PTR) - /*! * @} */ /* end of group CSI_Register_Accessor_Macros */ @@ -62249,7 +10533,6 @@ typedef struct { * @} */ /* end of group CSI_Peripheral */ - /* ---------------------------------------------------------------------------- -- DDRC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -62287,7 +10570,9 @@ typedef struct { __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */ __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */ __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */ - uint8_t RESERVED_6[24]; + uint8_t RESERVED_6[12]; + __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */ + uint8_t RESERVED_7[8]; __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */ __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */ __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */ @@ -62297,7 +10582,7 @@ typedef struct { __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */ __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */ __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */ - uint8_t RESERVED_7[92]; + uint8_t RESERVED_8[92]; __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */ __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */ @@ -62305,13 +10590,13 @@ typedef struct { __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */ __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */ __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */ - uint8_t RESERVED_8[4]; + uint8_t RESERVED_9[4]; __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */ __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */ __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */ __IO uint32_t DFIUPD3; /**< DFI Update Register 3, offset: 0x1AC */ __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */ - uint8_t RESERVED_9[76]; + uint8_t RESERVED_10[76]; __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */ __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */ __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */ @@ -62319,32 +10604,31 @@ typedef struct { __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */ __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */ __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */ - uint8_t RESERVED_10[36]; + uint8_t RESERVED_11[36]; __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */ __IO uint32_t ODTMAP; /**< ODT / Rank Map Register, offset: 0x244 */ - uint8_t RESERVED_11[8]; + uint8_t RESERVED_12[8]; __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */ __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */ - uint8_t RESERVED_12[4]; - __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */ uint8_t RESERVED_13[4]; - __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */ + __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */ uint8_t RESERVED_14[4]; - __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */ + __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */ uint8_t RESERVED_15[4]; + __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */ + uint8_t RESERVED_16[4]; __IO uint32_t PERFVPR1; /**< Variable Priority Read CAM Register 1, offset: 0x274 */ __IO uint32_t PERFVPW1; /**< Variable Priority Write CAM Register 1, offset: 0x278 */ - uint8_t RESERVED_16[132]; + uint8_t RESERVED_17[132]; __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */ __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */ __IO uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */ __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */ __IO uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */ - uint8_t RESERVED_17[12]; + uint8_t RESERVED_18[12]; __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */ __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */ } DDRC_Type, *DDRC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- DDRC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -62376,6 +10660,7 @@ typedef struct { #define DDRC_INIT3_REG(base) ((base)->INIT3) #define DDRC_INIT4_REG(base) ((base)->INIT4) #define DDRC_INIT5_REG(base) ((base)->INIT5) +#define DDRC_RANKCTL_REG(base) ((base)->RANKCTL) #define DDRC_DRAMTMG0_REG(base) ((base)->DRAMTMG0) #define DDRC_DRAMTMG1_REG(base) ((base)->DRAMTMG1) #define DDRC_DRAMTMG2_REG(base) ((base)->DRAMTMG2) @@ -62424,8 +10709,6 @@ typedef struct { /*! * @} */ /* end of group DDRC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- DDRC Register Masks ---------------------------------------------------------------------------- */ @@ -62464,6 +10747,9 @@ typedef struct { #define DDRC_STAT_SELFREF_TYPE_MASK 0x30u #define DDRC_STAT_SELFREF_TYPE_SHIFT 4 #define DDRC_STAT_SELFREF_TYPE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_STAT_SELFREF_TYPE_SHIFT))&DDRC_STAT_SELFREF_TYPE_MASK) +#define DDRC_STAT_SELFREF_STATE_MASK 0x300u +#define DDRC_STAT_SELFREF_STATE_SHIFT 8 +#define DDRC_STAT_SELFREF_STATE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_STAT_SELFREF_STATE_SHIFT))&DDRC_STAT_SELFREF_STATE_MASK) /* MRCTRL0 Bit Fields */ #define DDRC_MRCTRL0_MR_TYPE_MASK 0x1u #define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 @@ -62487,6 +10773,9 @@ typedef struct { #define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 #define DDRC_DERATEEN_DERATE_VALUE_MASK 0x2u #define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 +#define DDRC_DERATEEN_DERATE_BYTE_MASK 0xF0u +#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 +#define DDRC_DERATEEN_DERATE_BYTE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DERATEEN_DERATE_BYTE_SHIFT))&DDRC_DERATEEN_DERATE_BYTE_MASK) /* DERATEINT Bit Fields */ #define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFu #define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 @@ -62552,7 +10841,7 @@ typedef struct { #define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 #define DDRC_RFSHTMG_T_RFC_NOM_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT))&DDRC_RFSHTMG_T_RFC_NOM_X32_MASK) /* INIT0 Bit Fields */ -#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x3FFu +#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x7FFu #define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 #define DDRC_INIT0_PRE_CKE_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT0_PRE_CKE_X1024_SHIFT))&DDRC_INIT0_PRE_CKE_X1024_MASK) #define DDRC_INIT0_POST_CKE_X1024_MASK 0x3FF0000u @@ -62599,6 +10888,13 @@ typedef struct { #define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0xFF0000u #define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 #define DDRC_INIT5_DEV_ZQINIT_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT5_DEV_ZQINIT_X32_SHIFT))&DDRC_INIT5_DEV_ZQINIT_X32_MASK) +/* RANKCTL Bit Fields */ +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0xF0u +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT))&DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK) +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0xF00u +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT))&DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK) /* DRAMTMG0 Bit Fields */ #define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x3Fu #define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 @@ -62626,7 +10922,7 @@ typedef struct { #define DDRC_DRAMTMG2_WR2RD_MASK 0x3Fu #define DDRC_DRAMTMG2_WR2RD_SHIFT 0 #define DDRC_DRAMTMG2_WR2RD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_WR2RD_SHIFT))&DDRC_DRAMTMG2_WR2RD_MASK) -#define DDRC_DRAMTMG2_RD2WR_MASK 0x1F00u +#define DDRC_DRAMTMG2_RD2WR_MASK 0x3F00u #define DDRC_DRAMTMG2_RD2WR_SHIFT 8 #define DDRC_DRAMTMG2_RD2WR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_RD2WR_SHIFT))&DDRC_DRAMTMG2_RD2WR_MASK) #define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x3F0000u @@ -62652,7 +10948,7 @@ typedef struct { #define DDRC_DRAMTMG4_T_RRD_MASK 0xF00u #define DDRC_DRAMTMG4_T_RRD_SHIFT 8 #define DDRC_DRAMTMG4_T_RRD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_RRD_SHIFT))&DDRC_DRAMTMG4_T_RRD_MASK) -#define DDRC_DRAMTMG4_T_CCD_MASK 0x70000u +#define DDRC_DRAMTMG4_T_CCD_MASK 0xF0000u #define DDRC_DRAMTMG4_T_CCD_SHIFT 16 #define DDRC_DRAMTMG4_T_CCD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_CCD_SHIFT))&DDRC_DRAMTMG4_T_CCD_MASK) #define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000u @@ -63017,18 +11313,16 @@ typedef struct { * @} */ /* end of group DDRC_Register_Masks */ - /* DDRC - Peripheral instance base addresses */ /** Peripheral DDRC base address */ #define DDRC_BASE (0x307A0000u) /** Peripheral DDRC base pointer */ #define DDRC ((DDRC_Type *)DDRC_BASE) #define DDRC_BASE_PTR (DDRC) -/** Array initializer of DDRC peripheral base adresses */ +/** Array initializer of DDRC peripheral base addresses */ #define DDRC_BASE_ADDRS { DDRC_BASE } /** Array initializer of DDRC peripheral base pointers */ #define DDRC_BASE_PTRS { DDRC } - /* ---------------------------------------------------------------------------- -- DDRC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -63061,6 +11355,7 @@ typedef struct { #define DDRC_INIT3 DDRC_INIT3_REG(DDRC_BASE_PTR) #define DDRC_INIT4 DDRC_INIT4_REG(DDRC_BASE_PTR) #define DDRC_INIT5 DDRC_INIT5_REG(DDRC_BASE_PTR) +#define DDRC_RANKCTL DDRC_RANKCTL_REG(DDRC_BASE_PTR) #define DDRC_DRAMTMG0 DDRC_DRAMTMG0_REG(DDRC_BASE_PTR) #define DDRC_DRAMTMG1 DDRC_DRAMTMG1_REG(DDRC_BASE_PTR) #define DDRC_DRAMTMG2 DDRC_DRAMTMG2_REG(DDRC_BASE_PTR) @@ -63105,7 +11400,6 @@ typedef struct { #define DDRC_DBGSTAT DDRC_DBGSTAT_REG(DDRC_BASE_PTR) #define DDRC_SWCTL DDRC_SWCTL_REG(DDRC_BASE_PTR) #define DDRC_SWSTAT DDRC_SWSTAT_REG(DDRC_BASE_PTR) - /*! * @} */ /* end of group DDRC_Register_Accessor_Macros */ @@ -63115,7 +11409,6 @@ typedef struct { * @} */ /* end of group DDRC_Peripheral */ - /* ---------------------------------------------------------------------------- -- DDRC_MP Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -63136,7 +11429,7 @@ typedef struct { struct { /* offset: 0x410, array step: 0x8 */ __IO uint32_t PCFGIDMASKCH_0; /**< Port n Channel m Configuration ID Mask Register, array offset: 0x410, array step: 0x8 */ __IO uint32_t PCFGIDVALUECH_0; /**< Port n Channel m Configuration ID Value Register, array offset: 0x414, array step: 0x8 */ - } PCFGID[16]; + } PCFGID[16]; __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */ __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */ __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */ @@ -63146,9 +11439,8 @@ typedef struct { struct { /* offset: 0xF04, array step: 0x8 */ __IO uint32_t SARBASE; /**< SAR Base Address Register n, array offset: 0xF04, array step: 0x8 */ __IO uint32_t SARSIZE; /**< SAR Size Register n, array offset: 0xF08, array step: 0x8 */ - } SAR[4]; + } SAR[4]; } DDRC_MP_Type, *DDRC_MP_MemMapPtr; - /* ---------------------------------------------------------------------------- -- DDRC_MP - Register accessor macros ---------------------------------------------------------------------------- */ @@ -63177,8 +11469,6 @@ typedef struct { /*! * @} */ /* end of group DDRC_MP_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- DDRC_MP Register Masks ---------------------------------------------------------------------------- */ @@ -63281,18 +11571,16 @@ typedef struct { * @} */ /* end of group DDRC_MP_Register_Masks */ - /* DDRC_MP - Peripheral instance base addresses */ /** Peripheral DDRC_MP base address */ #define DDRC_MP_BASE (0x307A0000u) /** Peripheral DDRC_MP base pointer */ #define DDRC_MP ((DDRC_MP_Type *)DDRC_MP_BASE) #define DDRC_MP_BASE_PTR (DDRC_MP) -/** Array initializer of DDRC_MP peripheral base adresses */ +/** Array initializer of DDRC_MP peripheral base addresses */ #define DDRC_MP_BASE_ADDRS { DDRC_MP_BASE } /** Array initializer of DDRC_MP peripheral base pointers */ #define DDRC_MP_BASE_PTRS { DDRC_MP } - /* ---------------------------------------------------------------------------- -- DDRC_MP - Register accessor macros ---------------------------------------------------------------------------- */ @@ -63354,13 +11642,11 @@ typedef struct { #define DDRC_MP_SARSIZE2 DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,2) #define DDRC_MP_SARBASE3 DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,3) #define DDRC_MP_SARSIZE3 DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,3) - /* DDRC_MP - Register array accessors */ #define DDRC_MP_PCFGIDMASKCH_0(index) DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,index) #define DDRC_MP_PCFGIDVALUECH_0(index) DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,index) #define DDRC_MP_SARBASE(index) DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,index) #define DDRC_MP_SARSIZE(index) DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,index) - /*! * @} */ /* end of group DDRC_MP_Register_Accessor_Macros */ @@ -63370,7 +11656,6 @@ typedef struct { * @} */ /* end of group DDRC_MP_Peripheral */ - /* ---------------------------------------------------------------------------- -- DDR_PHY Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -63386,11 +11671,11 @@ typedef struct { __IO uint32_t PHY_CON1; /**< , offset: 0x4 */ __IO uint32_t PHY_CON2; /**< , offset: 0x8 */ __IO uint32_t PHY_CON3; /**< , offset: 0xC */ - __IO uint32_t CON4; /**< , offset: 0x10 */ + __IO uint32_t PHY_CON4; /**< , offset: 0x10 */ __IO uint32_t PHY_CON5; /**< , offset: 0x14 */ union { /* offset: 0x18 */ - __IO uint32_t LP_CON0; /**< , offset: 0x18 */ - __IO uint32_t RODT_CON0; /**< , offset: 0x18 */ + __IO uint32_t LP_CON0; /**< ,offset: 0x18 */ + __IO uint32_t RODT_CON0; /**< ,offset: 0x18 */ }; uint8_t RESERVED_0[4]; __IO uint32_t OFFSET_RD_CON0; /**< , offset: 0x20 */ @@ -63459,7 +11744,6 @@ typedef struct { uint8_t RESERVED_28[8]; __IO uint32_t STAT0; /**< , offset: 0x3AC */ } DDR_PHY_Type, *DDR_PHY_MemMapPtr; - /* ---------------------------------------------------------------------------- -- DDR_PHY - Register accessor macros ---------------------------------------------------------------------------- */ @@ -63475,7 +11759,7 @@ typedef struct { #define DDR_PHY_PHY_CON1_REG(base) ((base)->PHY_CON1) #define DDR_PHY_PHY_CON2_REG(base) ((base)->PHY_CON2) #define DDR_PHY_PHY_CON3_REG(base) ((base)->PHY_CON3) -#define DDR_PHY_CON4_REG(base) ((base)->CON4) +#define DDR_PHY_PHY_CON4_REG(base) ((base)->PHY_CON4) #define DDR_PHY_PHY_CON5_REG(base) ((base)->PHY_CON5) #define DDR_PHY_LP_CON0_REG(base) ((base)->LP_CON0) #define DDR_PHY_RODT_CON0_REG(base) ((base)->RODT_CON0) @@ -63520,8 +11804,6 @@ typedef struct { /*! * @} */ /* end of group DDR_PHY_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- DDR_PHY Register Masks ---------------------------------------------------------------------------- */ @@ -63586,16 +11868,16 @@ typedef struct { #define DDR_PHY_PHY_CON3_WRLVL_RESP_SHIFT 24 #define DDR_PHY_PHY_CON3_WL_CAL_RESP_MASK 0x8000000u #define DDR_PHY_PHY_CON3_WL_CAL_RESP_SHIFT 27 -/* CON4 Bit Fields */ -#define DDR_PHY_CON4_CTRL_RDLAT_MASK 0x1Fu -#define DDR_PHY_CON4_CTRL_RDLAT_SHIFT 0 -#define DDR_PHY_CON4_CTRL_RDLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CON4_CTRL_RDLAT_SHIFT))&DDR_PHY_CON4_CTRL_RDLAT_MASK) -#define DDR_PHY_CON4_CTRL_BSTLEN_MASK 0x1F00u -#define DDR_PHY_CON4_CTRL_BSTLEN_SHIFT 8 -#define DDR_PHY_CON4_CTRL_BSTLEN(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CON4_CTRL_BSTLEN_SHIFT))&DDR_PHY_CON4_CTRL_BSTLEN_MASK) -#define DDR_PHY_CON4_CTRL_WRLAT_MASK 0x1F0000u -#define DDR_PHY_CON4_CTRL_WRLAT_SHIFT 16 -#define DDR_PHY_CON4_CTRL_WRLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CON4_CTRL_WRLAT_SHIFT))&DDR_PHY_CON4_CTRL_WRLAT_MASK) +/* PHY_CON4 Bit Fields */ +#define DDR_PHY_PHY_CON4_CTRL_RDLAT_MASK 0x1Fu +#define DDR_PHY_PHY_CON4_CTRL_RDLAT_SHIFT 0 +#define DDR_PHY_PHY_CON4_CTRL_RDLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON4_CTRL_RDLAT_SHIFT))&DDR_PHY_PHY_CON4_CTRL_RDLAT_MASK) +#define DDR_PHY_PHY_CON4_CTRL_BSTLEN_MASK 0x1F00u +#define DDR_PHY_PHY_CON4_CTRL_BSTLEN_SHIFT 8 +#define DDR_PHY_PHY_CON4_CTRL_BSTLEN(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON4_CTRL_BSTLEN_SHIFT))&DDR_PHY_PHY_CON4_CTRL_BSTLEN_MASK) +#define DDR_PHY_PHY_CON4_CTRL_WRLAT_MASK 0x1F0000u +#define DDR_PHY_PHY_CON4_CTRL_WRLAT_SHIFT 16 +#define DDR_PHY_PHY_CON4_CTRL_WRLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON4_CTRL_WRLAT_SHIFT))&DDR_PHY_PHY_CON4_CTRL_WRLAT_MASK) /* PHY_CON5 Bit Fields */ #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_MASK 0x7u #define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_SHIFT 0 @@ -64079,18 +12361,16 @@ typedef struct { * @} */ /* end of group DDR_PHY_Register_Masks */ - /* DDR_PHY - Peripheral instance base addresses */ /** Peripheral DDR_PHY base address */ #define DDR_PHY_BASE (0x30790000u) /** Peripheral DDR_PHY base pointer */ #define DDR_PHY ((DDR_PHY_Type *)DDR_PHY_BASE) #define DDR_PHY_BASE_PTR (DDR_PHY) -/** Array initializer of DDR_PHY peripheral base adresses */ +/** Array initializer of DDR_PHY peripheral base addresses */ #define DDR_PHY_BASE_ADDRS { DDR_PHY_BASE } /** Array initializer of DDR_PHY peripheral base pointers */ #define DDR_PHY_BASE_PTRS { DDR_PHY } - /* ---------------------------------------------------------------------------- -- DDR_PHY - Register accessor macros ---------------------------------------------------------------------------- */ @@ -64107,7 +12387,7 @@ typedef struct { #define DDR_PHY_PHY_CON1 DDR_PHY_PHY_CON1_REG(DDR_PHY_BASE_PTR) #define DDR_PHY_PHY_CON2 DDR_PHY_PHY_CON2_REG(DDR_PHY_BASE_PTR) #define DDR_PHY_PHY_CON3 DDR_PHY_PHY_CON3_REG(DDR_PHY_BASE_PTR) -#define DDR_PHY_CON4 DDR_PHY_CON4_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_PHY_CON4 DDR_PHY_PHY_CON4_REG(DDR_PHY_BASE_PTR) #define DDR_PHY_PHY_CON5 DDR_PHY_PHY_CON5_REG(DDR_PHY_BASE_PTR) #define DDR_PHY_LP_CON0 DDR_PHY_LP_CON0_REG(DDR_PHY_BASE_PTR) #define DDR_PHY_RODT_CON0 DDR_PHY_RODT_CON0_REG(DDR_PHY_BASE_PTR) @@ -64148,7 +12428,6 @@ typedef struct { #define DDR_PHY_DM_DESKEW_CON DDR_PHY_DM_DESKEW_CON_REG(DDR_PHY_BASE_PTR) #define DDR_PHY_RDATA0 DDR_PHY_RDATA0_REG(DDR_PHY_BASE_PTR) #define DDR_PHY_STAT0 DDR_PHY_STAT0_REG(DDR_PHY_BASE_PTR) - /*! * @} */ /* end of group DDR_PHY_Register_Accessor_Macros */ @@ -64158,7 +12437,6 @@ typedef struct { * @} */ /* end of group DDR_PHY_Peripheral */ - /* ---------------------------------------------------------------------------- -- ECSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -64182,7 +12460,6 @@ typedef struct { uint8_t RESERVED_0[28]; __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ } ECSPI_Type, *ECSPI_MemMapPtr; - /* ---------------------------------------------------------------------------- -- ECSPI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -64208,8 +12485,6 @@ typedef struct { /*! * @} */ /* end of group ECSPI_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- ECSPI Register Masks ---------------------------------------------------------------------------- */ @@ -64353,7 +12628,6 @@ typedef struct { * @} */ /* end of group ECSPI_Register_Masks */ - /* ECSPI - Peripheral instance base addresses */ /** Peripheral ECSPI1 base address */ #define ECSPI1_BASE (0x30820000u) @@ -64375,11 +12649,12 @@ typedef struct { /** Peripheral ECSPI4 base pointer */ #define ECSPI4 ((ECSPI_Type *)ECSPI4_BASE) #define ECSPI4_BASE_PTR (ECSPI4) -/** Array initializer of ECSPI peripheral base adresses */ +/** Array initializer of ECSPI peripheral base addresses */ #define ECSPI_BASE_ADDRS { ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE } /** Array initializer of ECSPI peripheral base pointers */ #define ECSPI_BASE_PTRS { ECSPI1, ECSPI2, ECSPI3, ECSPI4 } - +/** Interrupt vectors for the ECSPI peripheral type */ +#define ECSPI_IRQS { eCSPI1_IRQn, eCSPI2_IRQn, eCSPI3_IRQn, eCSPI4_IRQn } /* ---------------------------------------------------------------------------- -- ECSPI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -64435,7 +12710,6 @@ typedef struct { #define ECSPI4_PERIODREG ECSPI_PERIODREG_REG(ECSPI4_BASE_PTR) #define ECSPI4_TESTREG ECSPI_TESTREG_REG(ECSPI4_BASE_PTR) #define ECSPI4_MSGDATA ECSPI_MSGDATA_REG(ECSPI4_BASE_PTR) - /*! * @} */ /* end of group ECSPI_Register_Accessor_Macros */ @@ -64445,7 +12719,6 @@ typedef struct { * @} */ /* end of group ECSPI_Peripheral */ - /* ---------------------------------------------------------------------------- -- EIM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -64464,14 +12737,13 @@ typedef struct { __IO uint32_t CSRCR2; /**< Chip Select n Read Configuration Register 2, array offset: 0xC, array step: 0x18 */ __IO uint32_t CSWCR1; /**< Chip Select n Write Configuration Register 1, array offset: 0x10, array step: 0x18 */ __IO uint32_t CSWCR2; /**< Chip Select n Write Configuration Register 2, array offset: 0x14, array step: 0x18 */ - } CSCR[6]; + } CS[6]; __IO uint32_t WCR; /**< EIM Configuration Register, offset: 0x90 */ __IO uint32_t DCR; /**< DLL Control Register, offset: 0x94 */ __I uint32_t DSR; /**< DLL Status Register, offset: 0x98 */ __IO uint32_t WIAR; /**< EIM IP Access Register, offset: 0x9C */ __IO uint32_t EAR; /**< Error Address Register, offset: 0xA0 */ } EIM_Type, *EIM_MemMapPtr; - /* ---------------------------------------------------------------------------- -- EIM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -64483,12 +12755,12 @@ typedef struct { /* EIM - Register accessors */ -#define EIM_CSGCR1_REG(base,index) ((base)->CSCR[index].CSGCR1) -#define EIM_CSGCR2_REG(base,index) ((base)->CSCR[index].CSGCR2) -#define EIM_CSRCR1_REG(base,index) ((base)->CSCR[index].CSRCR1) -#define EIM_CSRCR2_REG(base,index) ((base)->CSCR[index].CSRCR2) -#define EIM_CSWCR1_REG(base,index) ((base)->CSCR[index].CSWCR1) -#define EIM_CSWCR2_REG(base,index) ((base)->CSCR[index].CSWCR2) +#define EIM_CSGCR1_REG(base,index) ((base)->CS[index].CSGCR1) +#define EIM_CSGCR2_REG(base,index) ((base)->CS[index].CSGCR2) +#define EIM_CSRCR1_REG(base,index) ((base)->CS[index].CSRCR1) +#define EIM_CSRCR2_REG(base,index) ((base)->CS[index].CSRCR2) +#define EIM_CSWCR1_REG(base,index) ((base)->CS[index].CSWCR1) +#define EIM_CSWCR2_REG(base,index) ((base)->CS[index].CSWCR2) #define EIM_WCR_REG(base) ((base)->WCR) #define EIM_DCR_REG(base) ((base)->DCR) #define EIM_DSR_REG(base) ((base)->DSR) @@ -64498,8 +12770,6 @@ typedef struct { /*! * @} */ /* end of group EIM_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- EIM Register Masks ---------------------------------------------------------------------------- */ @@ -64722,18 +12992,18 @@ typedef struct { * @} */ /* end of group EIM_Register_Masks */ - /* EIM - Peripheral instance base addresses */ /** Peripheral EIM base address */ #define EIM_BASE (0x30BC0000u) /** Peripheral EIM base pointer */ #define EIM ((EIM_Type *)EIM_BASE) #define EIM_BASE_PTR (EIM) -/** Array initializer of EIM peripheral base adresses */ +/** Array initializer of EIM peripheral base addresses */ #define EIM_BASE_ADDRS { EIM_BASE } /** Array initializer of EIM peripheral base pointers */ #define EIM_BASE_PTRS { EIM } - +/** Interrupt vectors for the EIM peripheral type */ +#define EIM_IRQS { EIM_IRQn } /* ---------------------------------------------------------------------------- -- EIM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -64787,7 +13057,6 @@ typedef struct { #define EIM_DSR EIM_DSR_REG(EIM_BASE_PTR) #define EIM_WIAR EIM_WIAR_REG(EIM_BASE_PTR) #define EIM_EAR EIM_EAR_REG(EIM_BASE_PTR) - /* EIM - Register array accessors */ #define EIM_CSGCR1(index) EIM_CSGCR1_REG(EIM_BASE_PTR,index) #define EIM_CSGCR2(index) EIM_CSGCR2_REG(EIM_BASE_PTR,index) @@ -64795,7 +13064,6 @@ typedef struct { #define EIM_CSRCR2(index) EIM_CSRCR2_REG(EIM_BASE_PTR,index) #define EIM_CSWCR1(index) EIM_CSWCR1_REG(EIM_BASE_PTR,index) #define EIM_CSWCR2(index) EIM_CSWCR2_REG(EIM_BASE_PTR,index) - /*! * @} */ /* end of group EIM_Register_Accessor_Macros */ @@ -64805,392 +13073,6 @@ typedef struct { * @} */ /* end of group EIM_Peripheral */ - -/* ---------------------------------------------------------------------------- - -- EMVSIM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer - * @{ - */ - -/** EMVSIM - Register Layout Typedef */ -typedef struct { - __IO uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */ - __IO uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */ - __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */ - __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ - __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ - __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ - __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */ - __I uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ - __I uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */ - __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */ - __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */ - __O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */ - __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */ - __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */ - __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */ - __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */ - __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */ - __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */ -} EMVSIM_Type, *EMVSIM_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- EMVSIM - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMVSIM_Register_Accessor_Macros EMVSIM - Register accessor macros - * @{ - */ - - -/* EMVSIM - Register accessors */ -#define EMVSIM_VER_ID_REG(base) ((base)->VER_ID) -#define EMVSIM_PARAM_REG(base) ((base)->PARAM) -#define EMVSIM_CLKCFG_REG(base) ((base)->CLKCFG) -#define EMVSIM_DIVISOR_REG(base) ((base)->DIVISOR) -#define EMVSIM_CTRL_REG(base) ((base)->CTRL) -#define EMVSIM_INT_MASK_REG(base) ((base)->INT_MASK) -#define EMVSIM_RX_THD_REG(base) ((base)->RX_THD) -#define EMVSIM_TX_THD_REG(base) ((base)->TX_THD) -#define EMVSIM_RX_STATUS_REG(base) ((base)->RX_STATUS) -#define EMVSIM_TX_STATUS_REG(base) ((base)->TX_STATUS) -#define EMVSIM_PCSR_REG(base) ((base)->PCSR) -#define EMVSIM_RX_BUF_REG(base) ((base)->RX_BUF) -#define EMVSIM_TX_BUF_REG(base) ((base)->TX_BUF) -#define EMVSIM_TX_GETU_REG(base) ((base)->TX_GETU) -#define EMVSIM_CWT_VAL_REG(base) ((base)->CWT_VAL) -#define EMVSIM_BWT_VAL_REG(base) ((base)->BWT_VAL) -#define EMVSIM_BGT_VAL_REG(base) ((base)->BGT_VAL) -#define EMVSIM_GPCNT0_VAL_REG(base) ((base)->GPCNT0_VAL) -#define EMVSIM_GPCNT1_VAL_REG(base) ((base)->GPCNT1_VAL) - -/*! - * @} - */ /* end of group EMVSIM_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- EMVSIM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks - * @{ - */ - -/* VER_ID Bit Fields */ -#define EMVSIM_VER_ID_VER_MASK 0xFFFFFFFFu -#define EMVSIM_VER_ID_VER_SHIFT 0 -#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_VER_ID_VER_SHIFT))&EMVSIM_VER_ID_VER_MASK) -/* PARAM Bit Fields */ -#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK 0xFFu -#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT 0 -#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT))&EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) -#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK 0xFF00u -#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT 8 -#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT))&EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) -/* CLKCFG Bit Fields */ -#define EMVSIM_CLKCFG_CLK_PRSC_MASK 0xFFu -#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT 0 -#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_CLK_PRSC_SHIFT))&EMVSIM_CLKCFG_CLK_PRSC_MASK) -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK 0x300u -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT 8 -#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT))&EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK 0xC00u -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT 10 -#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT))&EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) -/* DIVISOR Bit Fields */ -#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK 0x1FFu -#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT 0 -#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT))&EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) -/* CTRL Bit Fields */ -#define EMVSIM_CTRL_IC_MASK 0x1u -#define EMVSIM_CTRL_IC_SHIFT 0 -#define EMVSIM_CTRL_ICM_MASK 0x2u -#define EMVSIM_CTRL_ICM_SHIFT 1 -#define EMVSIM_CTRL_ANACK_MASK 0x4u -#define EMVSIM_CTRL_ANACK_SHIFT 2 -#define EMVSIM_CTRL_ONACK_MASK 0x8u -#define EMVSIM_CTRL_ONACK_SHIFT 3 -#define EMVSIM_CTRL_FLSH_RX_MASK 0x100u -#define EMVSIM_CTRL_FLSH_RX_SHIFT 8 -#define EMVSIM_CTRL_FLSH_TX_MASK 0x200u -#define EMVSIM_CTRL_FLSH_TX_SHIFT 9 -#define EMVSIM_CTRL_SW_RST_MASK 0x400u -#define EMVSIM_CTRL_SW_RST_SHIFT 10 -#define EMVSIM_CTRL_KILL_CLOCKS_MASK 0x800u -#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT 11 -#define EMVSIM_CTRL_DOZE_EN_MASK 0x1000u -#define EMVSIM_CTRL_DOZE_EN_SHIFT 12 -#define EMVSIM_CTRL_STOP_EN_MASK 0x2000u -#define EMVSIM_CTRL_STOP_EN_SHIFT 13 -#define EMVSIM_CTRL_RCV_EN_MASK 0x10000u -#define EMVSIM_CTRL_RCV_EN_SHIFT 16 -#define EMVSIM_CTRL_XMT_EN_MASK 0x20000u -#define EMVSIM_CTRL_XMT_EN_SHIFT 17 -#define EMVSIM_CTRL_RCVR_11_MASK 0x40000u -#define EMVSIM_CTRL_RCVR_11_SHIFT 18 -#define EMVSIM_CTRL_RX_DMA_EN_MASK 0x80000u -#define EMVSIM_CTRL_RX_DMA_EN_SHIFT 19 -#define EMVSIM_CTRL_TX_DMA_EN_MASK 0x100000u -#define EMVSIM_CTRL_TX_DMA_EN_SHIFT 20 -#define EMVSIM_CTRL_INV_CRC_VAL_MASK 0x1000000u -#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT 24 -#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK 0x2000000u -#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT 25 -#define EMVSIM_CTRL_CRC_IN_FLIP_MASK 0x4000000u -#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT 26 -#define EMVSIM_CTRL_CWT_EN_MASK 0x8000000u -#define EMVSIM_CTRL_CWT_EN_SHIFT 27 -#define EMVSIM_CTRL_LRC_EN_MASK 0x10000000u -#define EMVSIM_CTRL_LRC_EN_SHIFT 28 -#define EMVSIM_CTRL_CRC_EN_MASK 0x20000000u -#define EMVSIM_CTRL_CRC_EN_SHIFT 29 -#define EMVSIM_CTRL_XMT_CRC_LRC_MASK 0x40000000u -#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT 30 -#define EMVSIM_CTRL_BWT_EN_MASK 0x80000000u -#define EMVSIM_CTRL_BWT_EN_SHIFT 31 -/* INT_MASK Bit Fields */ -#define EMVSIM_INT_MASK_RDT_IM_MASK 0x1u -#define EMVSIM_INT_MASK_RDT_IM_SHIFT 0 -#define EMVSIM_INT_MASK_TC_IM_MASK 0x2u -#define EMVSIM_INT_MASK_TC_IM_SHIFT 1 -#define EMVSIM_INT_MASK_RFO_IM_MASK 0x4u -#define EMVSIM_INT_MASK_RFO_IM_SHIFT 2 -#define EMVSIM_INT_MASK_ETC_IM_MASK 0x8u -#define EMVSIM_INT_MASK_ETC_IM_SHIFT 3 -#define EMVSIM_INT_MASK_TFE_IM_MASK 0x10u -#define EMVSIM_INT_MASK_TFE_IM_SHIFT 4 -#define EMVSIM_INT_MASK_TNACK_IM_MASK 0x20u -#define EMVSIM_INT_MASK_TNACK_IM_SHIFT 5 -#define EMVSIM_INT_MASK_TFF_IM_MASK 0x40u -#define EMVSIM_INT_MASK_TFF_IM_SHIFT 6 -#define EMVSIM_INT_MASK_TDT_IM_MASK 0x80u -#define EMVSIM_INT_MASK_TDT_IM_SHIFT 7 -#define EMVSIM_INT_MASK_GPCNT0_IM_MASK 0x100u -#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT 8 -#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK 0x200u -#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT 9 -#define EMVSIM_INT_MASK_RNACK_IM_MASK 0x400u -#define EMVSIM_INT_MASK_RNACK_IM_SHIFT 10 -#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK 0x800u -#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT 11 -#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK 0x1000u -#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT 12 -#define EMVSIM_INT_MASK_GPCNT1_IM_MASK 0x2000u -#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT 13 -#define EMVSIM_INT_MASK_RX_DATA_IM_MASK 0x4000u -#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT 14 -/* RX_THD Bit Fields */ -#define EMVSIM_RX_THD_RDT_MASK 0xFu -#define EMVSIM_RX_THD_RDT_SHIFT 0 -#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_THD_RDT_SHIFT))&EMVSIM_RX_THD_RDT_MASK) -#define EMVSIM_RX_THD_RNCK_THD_MASK 0xF00u -#define EMVSIM_RX_THD_RNCK_THD_SHIFT 8 -#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_THD_RNCK_THD_SHIFT))&EMVSIM_RX_THD_RNCK_THD_MASK) -/* TX_THD Bit Fields */ -#define EMVSIM_TX_THD_TDT_MASK 0xFu -#define EMVSIM_TX_THD_TDT_SHIFT 0 -#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_THD_TDT_SHIFT))&EMVSIM_TX_THD_TDT_MASK) -#define EMVSIM_TX_THD_TNCK_THD_MASK 0xF00u -#define EMVSIM_TX_THD_TNCK_THD_SHIFT 8 -#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_THD_TNCK_THD_SHIFT))&EMVSIM_TX_THD_TNCK_THD_MASK) -/* RX_STATUS Bit Fields */ -#define EMVSIM_RX_STATUS_RFO_MASK 0x1u -#define EMVSIM_RX_STATUS_RFO_SHIFT 0 -#define EMVSIM_RX_STATUS_RX_DATA_MASK 0x10u -#define EMVSIM_RX_STATUS_RX_DATA_SHIFT 4 -#define EMVSIM_RX_STATUS_RDTF_MASK 0x20u -#define EMVSIM_RX_STATUS_RDTF_SHIFT 5 -#define EMVSIM_RX_STATUS_LRC_OK_MASK 0x40u -#define EMVSIM_RX_STATUS_LRC_OK_SHIFT 6 -#define EMVSIM_RX_STATUS_CRC_OK_MASK 0x80u -#define EMVSIM_RX_STATUS_CRC_OK_SHIFT 7 -#define EMVSIM_RX_STATUS_CWT_ERR_MASK 0x100u -#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT 8 -#define EMVSIM_RX_STATUS_RTE_MASK 0x200u -#define EMVSIM_RX_STATUS_RTE_SHIFT 9 -#define EMVSIM_RX_STATUS_BWT_ERR_MASK 0x400u -#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT 10 -#define EMVSIM_RX_STATUS_BGT_ERR_MASK 0x800u -#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT 11 -#define EMVSIM_RX_STATUS_PEF_MASK 0x1000u -#define EMVSIM_RX_STATUS_PEF_SHIFT 12 -#define EMVSIM_RX_STATUS_FEF_MASK 0x2000u -#define EMVSIM_RX_STATUS_FEF_SHIFT 13 -#define EMVSIM_RX_STATUS_RX_WPTR_MASK 0xF0000u -#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT 16 -#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RX_WPTR_SHIFT))&EMVSIM_RX_STATUS_RX_WPTR_MASK) -#define EMVSIM_RX_STATUS_RX_CNT_MASK 0x1F000000u -#define EMVSIM_RX_STATUS_RX_CNT_SHIFT 24 -#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RX_CNT_SHIFT))&EMVSIM_RX_STATUS_RX_CNT_MASK) -/* TX_STATUS Bit Fields */ -#define EMVSIM_TX_STATUS_TNTE_MASK 0x1u -#define EMVSIM_TX_STATUS_TNTE_SHIFT 0 -#define EMVSIM_TX_STATUS_TFE_MASK 0x8u -#define EMVSIM_TX_STATUS_TFE_SHIFT 3 -#define EMVSIM_TX_STATUS_ETCF_MASK 0x10u -#define EMVSIM_TX_STATUS_ETCF_SHIFT 4 -#define EMVSIM_TX_STATUS_TCF_MASK 0x20u -#define EMVSIM_TX_STATUS_TCF_SHIFT 5 -#define EMVSIM_TX_STATUS_TFF_MASK 0x40u -#define EMVSIM_TX_STATUS_TFF_SHIFT 6 -#define EMVSIM_TX_STATUS_TDTF_MASK 0x80u -#define EMVSIM_TX_STATUS_TDTF_SHIFT 7 -#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK 0x100u -#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT 8 -#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK 0x200u -#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT 9 -#define EMVSIM_TX_STATUS_TX_RPTR_MASK 0xF0000u -#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT 16 -#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TX_RPTR_SHIFT))&EMVSIM_TX_STATUS_TX_RPTR_MASK) -#define EMVSIM_TX_STATUS_TX_CNT_MASK 0x1F000000u -#define EMVSIM_TX_STATUS_TX_CNT_SHIFT 24 -#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TX_CNT_SHIFT))&EMVSIM_TX_STATUS_TX_CNT_MASK) -/* PCSR Bit Fields */ -#define EMVSIM_PCSR_SAPD_MASK 0x1u -#define EMVSIM_PCSR_SAPD_SHIFT 0 -#define EMVSIM_PCSR_SVCC_EN_MASK 0x2u -#define EMVSIM_PCSR_SVCC_EN_SHIFT 1 -#define EMVSIM_PCSR_VCCENP_MASK 0x4u -#define EMVSIM_PCSR_VCCENP_SHIFT 2 -#define EMVSIM_PCSR_SRST_MASK 0x8u -#define EMVSIM_PCSR_SRST_SHIFT 3 -#define EMVSIM_PCSR_SCEN_MASK 0x10u -#define EMVSIM_PCSR_SCEN_SHIFT 4 -#define EMVSIM_PCSR_SCSP_MASK 0x20u -#define EMVSIM_PCSR_SCSP_SHIFT 5 -#define EMVSIM_PCSR_SPD_MASK 0x80u -#define EMVSIM_PCSR_SPD_SHIFT 7 -#define EMVSIM_PCSR_SPDIM_MASK 0x1000000u -#define EMVSIM_PCSR_SPDIM_SHIFT 24 -#define EMVSIM_PCSR_SPDIF_MASK 0x2000000u -#define EMVSIM_PCSR_SPDIF_SHIFT 25 -#define EMVSIM_PCSR_SPDP_MASK 0x4000000u -#define EMVSIM_PCSR_SPDP_SHIFT 26 -#define EMVSIM_PCSR_SPDES_MASK 0x8000000u -#define EMVSIM_PCSR_SPDES_SHIFT 27 -/* RX_BUF Bit Fields */ -#define EMVSIM_RX_BUF_RX_BYTE_MASK 0xFFu -#define EMVSIM_RX_BUF_RX_BYTE_SHIFT 0 -#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_BUF_RX_BYTE_SHIFT))&EMVSIM_RX_BUF_RX_BYTE_MASK) -/* TX_BUF Bit Fields */ -#define EMVSIM_TX_BUF_TX_BYTE_MASK 0xFFu -#define EMVSIM_TX_BUF_TX_BYTE_SHIFT 0 -#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_BUF_TX_BYTE_SHIFT))&EMVSIM_TX_BUF_TX_BYTE_MASK) -/* TX_GETU Bit Fields */ -#define EMVSIM_TX_GETU_GETU_MASK 0xFFu -#define EMVSIM_TX_GETU_GETU_SHIFT 0 -#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_GETU_GETU_SHIFT))&EMVSIM_TX_GETU_GETU_MASK) -/* CWT_VAL Bit Fields */ -#define EMVSIM_CWT_VAL_CWT_MASK 0xFFFFu -#define EMVSIM_CWT_VAL_CWT_SHIFT 0 -#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CWT_VAL_CWT_SHIFT))&EMVSIM_CWT_VAL_CWT_MASK) -/* BWT_VAL Bit Fields */ -#define EMVSIM_BWT_VAL_BWT_MASK 0xFFFFFFFFu -#define EMVSIM_BWT_VAL_BWT_SHIFT 0 -#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_BWT_VAL_BWT_SHIFT))&EMVSIM_BWT_VAL_BWT_MASK) -/* BGT_VAL Bit Fields */ -#define EMVSIM_BGT_VAL_BGT_MASK 0xFFFFu -#define EMVSIM_BGT_VAL_BGT_SHIFT 0 -#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_BGT_VAL_BGT_SHIFT))&EMVSIM_BGT_VAL_BGT_MASK) -/* GPCNT0_VAL Bit Fields */ -#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK 0xFFFFu -#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT 0 -#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT))&EMVSIM_GPCNT0_VAL_GPCNT0_MASK) -/* GPCNT1_VAL Bit Fields */ -#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK 0xFFFFu -#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT 0 -#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT))&EMVSIM_GPCNT1_VAL_GPCNT1_MASK) - -/*! - * @} - */ /* end of group EMVSIM_Register_Masks */ - - -/* EMVSIM - Peripheral instance base addresses */ -/** Peripheral EMVSIM1 base address */ -#define EMVSIM1_BASE (0x30B90000u) -/** Peripheral EMVSIM1 base pointer */ -#define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) -#define EMVSIM1_BASE_PTR (EMVSIM1) -/** Peripheral EMVSIM2 base address */ -#define EMVSIM2_BASE (0x30BA0000u) -/** Peripheral EMVSIM2 base pointer */ -#define EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE) -#define EMVSIM2_BASE_PTR (EMVSIM2) -/** Array initializer of EMVSIM peripheral base adresses */ -#define EMVSIM_BASE_ADDRS { EMVSIM1_BASE, EMVSIM2_BASE } -/** Array initializer of EMVSIM peripheral base pointers */ -#define EMVSIM_BASE_PTRS { EMVSIM1, EMVSIM2 } - -/* ---------------------------------------------------------------------------- - -- EMVSIM - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EMVSIM_Register_Accessor_Macros EMVSIM - Register accessor macros - * @{ - */ - - -/* EMVSIM - Register instance definitions */ -/* EMVSIM1 */ -#define EMVSIM1_VER_ID EMVSIM_VER_ID_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_PARAM EMVSIM_PARAM_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_CLKCFG EMVSIM_CLKCFG_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_DIVISOR EMVSIM_DIVISOR_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_CTRL EMVSIM_CTRL_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_INT_MASK EMVSIM_INT_MASK_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_RX_THD EMVSIM_RX_THD_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_TX_THD EMVSIM_TX_THD_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_RX_STATUS EMVSIM_RX_STATUS_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_TX_STATUS EMVSIM_TX_STATUS_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_PCSR EMVSIM_PCSR_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_RX_BUF EMVSIM_RX_BUF_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_TX_BUF EMVSIM_TX_BUF_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_TX_GETU EMVSIM_TX_GETU_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_CWT_VAL EMVSIM_CWT_VAL_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_BWT_VAL EMVSIM_BWT_VAL_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_BGT_VAL EMVSIM_BGT_VAL_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_GPCNT0_VAL EMVSIM_GPCNT0_VAL_REG(EMVSIM1_BASE_PTR) -#define EMVSIM1_GPCNT1_VAL EMVSIM_GPCNT1_VAL_REG(EMVSIM1_BASE_PTR) -/* EMVSIM2 */ -#define EMVSIM2_VER_ID EMVSIM_VER_ID_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_PARAM EMVSIM_PARAM_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_CLKCFG EMVSIM_CLKCFG_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_DIVISOR EMVSIM_DIVISOR_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_CTRL EMVSIM_CTRL_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_INT_MASK EMVSIM_INT_MASK_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_RX_THD EMVSIM_RX_THD_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_TX_THD EMVSIM_TX_THD_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_RX_STATUS EMVSIM_RX_STATUS_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_TX_STATUS EMVSIM_TX_STATUS_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_PCSR EMVSIM_PCSR_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_RX_BUF EMVSIM_RX_BUF_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_TX_BUF EMVSIM_TX_BUF_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_TX_GETU EMVSIM_TX_GETU_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_CWT_VAL EMVSIM_CWT_VAL_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_BWT_VAL EMVSIM_BWT_VAL_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_BGT_VAL EMVSIM_BGT_VAL_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_GPCNT0_VAL EMVSIM_GPCNT0_VAL_REG(EMVSIM2_BASE_PTR) -#define EMVSIM2_GPCNT1_VAL EMVSIM_GPCNT1_VAL_REG(EMVSIM2_BASE_PTR) - -/*! - * @} - */ /* end of group EMVSIM_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group EMVSIM_Peripheral */ - - /* ---------------------------------------------------------------------------- -- ENET Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -65206,8 +13088,8 @@ typedef struct { __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ uint8_t RESERVED_1[4]; - __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */ - __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */ + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ uint8_t RESERVED_2[12]; __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ uint8_t RESERVED_3[24]; @@ -65241,9 +13123,9 @@ typedef struct { __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ uint8_t RESERVED_12[8]; - __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */ - __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */ - __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */ + __IO uint32_t RDSR; /**< Receive Descriptor Ring , offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring , offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ uint8_t RESERVED_13[4]; __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ @@ -65266,7 +13148,7 @@ typedef struct { __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ uint8_t RESERVED_16[12]; - __I uint32_t RMON_T_DROP; /**< Incorrectly Counted Frames Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ @@ -65284,7 +13166,7 @@ typedef struct { __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ - __I uint32_t IEEE_T_DROP; /**< IEEE_T_DROP Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_DROP; /**< IEEE_T_DROP Reserved Statistic Register, offset: 0x248 */ __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ @@ -65305,7 +13187,7 @@ typedef struct { __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ - __I uint32_t RMON_R_RESVD_0; /**< RMON Reserved Register, offset: 0x2A4 */ + __I uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ @@ -65334,9 +13216,8 @@ typedef struct { struct { /* offset: 0x608, array step: 0x8 */ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ - } CHANNEL[4]; + } TC[4]; } ENET_Type, *ENET_MemMapPtr; - /* ---------------------------------------------------------------------------- -- ENET - Register accessor macros ---------------------------------------------------------------------------- */ @@ -65457,14 +13338,12 @@ typedef struct { #define ENET_ATINC_REG(base) ((base)->ATINC) #define ENET_ATSTMP_REG(base) ((base)->ATSTMP) #define ENET_TGSR_REG(base) ((base)->TGSR) -#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) -#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) +#define ENET_TCSR_REG(base,index) ((base)->TC[index].TCSR) +#define ENET_TCCR_REG(base,index) ((base)->TC[index].TCCR) /*! * @} */ /* end of group ENET_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ @@ -65769,7 +13648,7 @@ typedef struct { #define ENET_TDSR1_X_DES_START_SHIFT 3 #define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR1_X_DES_START_SHIFT))&ENET_TDSR1_X_DES_START_MASK) /* MRBR1 Bit Fields */ -#define ENET_MRBR1_R_BUF_SIZE_MASK 0x3FF0u +#define ENET_MRBR1_R_BUF_SIZE_MASK 0x7F0u #define ENET_MRBR1_R_BUF_SIZE_SHIFT 4 #define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR1_R_BUF_SIZE_SHIFT))&ENET_MRBR1_R_BUF_SIZE_MASK) /* RDSR2 Bit Fields */ @@ -65781,7 +13660,7 @@ typedef struct { #define ENET_TDSR2_X_DES_START_SHIFT 3 #define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR2_X_DES_START_SHIFT))&ENET_TDSR2_X_DES_START_MASK) /* MRBR2 Bit Fields */ -#define ENET_MRBR2_R_BUF_SIZE_MASK 0x3FF0u +#define ENET_MRBR2_R_BUF_SIZE_MASK 0x7F0u #define ENET_MRBR2_R_BUF_SIZE_SHIFT 4 #define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR2_R_BUF_SIZE_SHIFT))&ENET_MRBR2_R_BUF_SIZE_MASK) /* RDSR Bit Fields */ @@ -65793,7 +13672,7 @@ typedef struct { #define ENET_TDSR_X_DES_START_SHIFT 3 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK) /* MRBR Bit Fields */ -#define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u +#define ENET_MRBR_R_BUF_SIZE_MASK 0x7F0u #define ENET_MRBR_R_BUF_SIZE_SHIFT 4 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK) /* RSFL Bit Fields */ @@ -65899,9 +13778,6 @@ typedef struct { #define ENET_QOS_RX_FLUSH2_MASK 0x20u #define ENET_QOS_RX_FLUSH2_SHIFT 5 /* RMON_T_DROP Bit Fields */ -#define ENET_RMON_T_DROP_INCCNTF_MASK 0xFFFFu -#define ENET_RMON_T_DROP_INCCNTF_SHIFT 0 -#define ENET_RMON_T_DROP_INCCNTF(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_DROP_INCCNTF_SHIFT))&ENET_RMON_T_DROP_INCCNTF_MASK) /* RMON_T_PACKETS Bit Fields */ #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0 @@ -65971,9 +13847,6 @@ typedef struct { #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK) /* IEEE_T_DROP Bit Fields */ -#define ENET_IEEE_T_DROP_COUNT_MASK 0xFFFFu -#define ENET_IEEE_T_DROP_COUNT_SHIFT 0 -#define ENET_IEEE_T_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DROP_COUNT_SHIFT))&ENET_IEEE_T_DROP_COUNT_MASK) /* IEEE_T_FRAME_OK Bit Fields */ #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0 @@ -66050,6 +13923,7 @@ typedef struct { #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu #define ENET_RMON_R_JAB_COUNT_SHIFT 0 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK) +/* RMON_R_RESVD_0 Bit Fields */ /* RMON_R_P64 Bit Fields */ #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu #define ENET_RMON_R_P64_COUNT_SHIFT 0 @@ -66182,7 +14056,6 @@ typedef struct { * @} */ /* end of group ENET_Register_Masks */ - /* ENET - Peripheral instance base addresses */ /** Peripheral ENET1 base address */ #define ENET1_BASE (0x30BE0000u) @@ -66194,11 +14067,10 @@ typedef struct { /** Peripheral ENET2 base pointer */ #define ENET2 ((ENET_Type *)ENET2_BASE) #define ENET2_BASE_PTR (ENET2) -/** Array initializer of ENET peripheral base adresses */ +/** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS { ENET1_BASE, ENET2_BASE } /** Array initializer of ENET peripheral base pointers */ #define ENET_BASE_PTRS { ENET1, ENET2 } - /* ---------------------------------------------------------------------------- -- ENET - Register accessor macros ---------------------------------------------------------------------------- */ @@ -66458,7 +14330,6 @@ typedef struct { #define ENET2_TCCR2 ENET_TCCR_REG(ENET2_BASE_PTR,2) #define ENET2_TCSR3 ENET_TCSR_REG(ENET2_BASE_PTR,3) #define ENET2_TCCR3 ENET_TCCR_REG(ENET2_BASE_PTR,3) - /* ENET - Register array accessors */ #define ENET1_TXIC(index) ENET_TXIC_REG(ENET1_BASE_PTR,index) #define ENET2_TXIC(index) ENET_TXIC_REG(ENET2_BASE_PTR,index) @@ -66472,7 +14343,6 @@ typedef struct { #define ENET2_TCSR(index) ENET_TCSR_REG(ENET2_BASE_PTR,index) #define ENET1_TCCR(index) ENET_TCCR_REG(ENET1_BASE_PTR,index) #define ENET2_TCCR(index) ENET_TCCR_REG(ENET2_BASE_PTR,index) - /*! * @} */ /* end of group ENET_Register_Accessor_Macros */ @@ -66482,7 +14352,6 @@ typedef struct { * @} */ /* end of group ENET_Peripheral */ - /* ---------------------------------------------------------------------------- -- EPDC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -66498,7 +14367,8 @@ typedef struct { __IO uint32_t CTRL_SET; /**< EPDC Control Register, offset: 0x4 */ __IO uint32_t CTRL_CLR; /**< EPDC Control Register, offset: 0x8 */ __IO uint32_t CTRL_TOG; /**< EPDC Control Register, offset: 0xC */ - uint8_t RESERVED_0[16]; + __IO uint32_t WB_ADDR_TCE; /**< EPDC Working Buffer Address for TCE, offset: 0x10 */ + uint8_t RESERVED_0[12]; __IO uint32_t WVADDR; /**< EPDC Waveform Address Pointer, offset: 0x20 */ uint8_t RESERVED_1[12]; __IO uint32_t WB_ADDR; /**< EPDC Working Buffer Address, offset: 0x30 */ @@ -66509,74 +14379,89 @@ typedef struct { __IO uint32_t FORMAT_SET; /**< EPDC Format Control Register, offset: 0x54 */ __IO uint32_t FORMAT_CLR; /**< EPDC Format Control Register, offset: 0x58 */ __IO uint32_t FORMAT_TOG; /**< EPDC Format Control Register, offset: 0x5C */ - uint8_t RESERVED_4[64]; + __IO uint32_t WB_FIELD0; /**< Working Buffer Field Setting, offset: 0x60 */ + uint8_t RESERVED_4[12]; + __IO uint32_t WB_FIELD1; /**< Working Buffer Field Setting, offset: 0x70 */ + uint8_t RESERVED_5[12]; + __IO uint32_t WB_FIELD2; /**< Working Buffer Field Setting, offset: 0x80 */ + uint8_t RESERVED_6[12]; + __IO uint32_t WB_FIELD3; /**< Working Buffer Field Setting, offset: 0x90 */ + uint8_t RESERVED_7[12]; __IO uint32_t FIFOCTRL; /**< EPDC FIFO control register, offset: 0xA0 */ __IO uint32_t FIFOCTRL_SET; /**< EPDC FIFO control register, offset: 0xA4 */ __IO uint32_t FIFOCTRL_CLR; /**< EPDC FIFO control register, offset: 0xA8 */ __IO uint32_t FIFOCTRL_TOG; /**< EPDC FIFO control register, offset: 0xAC */ - uint8_t RESERVED_5[80]; + uint8_t RESERVED_8[80]; __IO uint32_t UPD_ADDR; /**< EPDC Update Region Address, offset: 0x100 */ - uint8_t RESERVED_6[12]; + uint8_t RESERVED_9[12]; __IO uint32_t UPD_STRIDE; /**< EPDC Update Region Stride, offset: 0x110 */ - uint8_t RESERVED_7[12]; + uint8_t RESERVED_10[12]; __IO uint32_t UPD_CORD; /**< EPDC Update Command Co-ordinate, offset: 0x120 */ - uint8_t RESERVED_8[28]; + uint8_t RESERVED_11[28]; __IO uint32_t UPD_SIZE; /**< EPDC Update Command Size, offset: 0x140 */ - uint8_t RESERVED_9[28]; + uint8_t RESERVED_12[28]; __IO uint32_t UPD_CTRL; /**< EPDC Update Command Control, offset: 0x160 */ __IO uint32_t UPD_CTRL_SET; /**< EPDC Update Command Control, offset: 0x164 */ __IO uint32_t UPD_CTRL_CLR; /**< EPDC Update Command Control, offset: 0x168 */ __IO uint32_t UPD_CTRL_TOG; /**< EPDC Update Command Control, offset: 0x16C */ - uint8_t RESERVED_10[16]; + uint8_t RESERVED_13[16]; __IO uint32_t UPD_FIXED; /**< EPDC Update Fixed Pixel Control, offset: 0x180 */ __IO uint32_t UPD_FIXED_SET; /**< EPDC Update Fixed Pixel Control, offset: 0x184 */ __IO uint32_t UPD_FIXED_CLR; /**< EPDC Update Fixed Pixel Control, offset: 0x188 */ __IO uint32_t UPD_FIXED_TOG; /**< EPDC Update Fixed Pixel Control, offset: 0x18C */ - uint8_t RESERVED_11[16]; + uint8_t RESERVED_14[16]; __IO uint32_t TEMP; /**< EPDC Temperature Register, offset: 0x1A0 */ - uint8_t RESERVED_12[28]; + uint8_t RESERVED_15[28]; __IO uint32_t AUTOWV_LUT; /**< Waveform Mode Lookup Table Control Register., offset: 0x1C0 */ - uint8_t RESERVED_13[60]; + uint8_t RESERVED_16[28]; + __IO uint32_t LUT_STANDBY1; /**< EPDC LUT Standby Register for LUT 31~0, offset: 0x1E0 */ + __IO uint32_t LUT_STANDBY1_SET; /**< EPDC LUT Standby Register for LUT 31~0, offset: 0x1E4 */ + __IO uint32_t LUT_STANDBY1_CLR; /**< EPDC LUT Standby Register for LUT 31~0, offset: 0x1E8 */ + __IO uint32_t LUT_STANDBY1_TOG; /**< EPDC LUT Standby Register for LUT 31~0, offset: 0x1EC */ + __IO uint32_t LUT_STANDBY2; /**< EPDC LUT Standby Registerr for LUT 63~32, offset: 0x1F0 */ + __IO uint32_t LUT_STANDBY2_SET; /**< EPDC LUT Standby Registerr for LUT 63~32, offset: 0x1F4 */ + __IO uint32_t LUT_STANDBY2_CLR; /**< EPDC LUT Standby Registerr for LUT 63~32, offset: 0x1F8 */ + __IO uint32_t LUT_STANDBY2_TOG; /**< EPDC LUT Standby Registerr for LUT 63~32, offset: 0x1FC */ __IO uint32_t TCE_CTRL; /**< EPDC Timing Control Engine Control Register, offset: 0x200 */ __IO uint32_t TCE_CTRL_SET; /**< EPDC Timing Control Engine Control Register, offset: 0x204 */ __IO uint32_t TCE_CTRL_CLR; /**< EPDC Timing Control Engine Control Register, offset: 0x208 */ __IO uint32_t TCE_CTRL_TOG; /**< EPDC Timing Control Engine Control Register, offset: 0x20C */ - uint8_t RESERVED_14[16]; + uint8_t RESERVED_17[16]; __IO uint32_t TCE_SDCFG; /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x220 */ __IO uint32_t TCE_SDCFG_SET; /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x224 */ __IO uint32_t TCE_SDCFG_CLR; /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x228 */ __IO uint32_t TCE_SDCFG_TOG; /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x22C */ - uint8_t RESERVED_15[16]; + uint8_t RESERVED_18[16]; __IO uint32_t TCE_GDCFG; /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x240 */ __IO uint32_t TCE_GDCFG_SET; /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x244 */ __IO uint32_t TCE_GDCFG_CLR; /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x248 */ __IO uint32_t TCE_GDCFG_TOG; /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x24C */ - uint8_t RESERVED_16[16]; + uint8_t RESERVED_19[16]; __IO uint32_t TCE_HSCAN1; /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x260 */ __IO uint32_t TCE_HSCAN1_SET; /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x264 */ __IO uint32_t TCE_HSCAN1_CLR; /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x268 */ __IO uint32_t TCE_HSCAN1_TOG; /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x26C */ - uint8_t RESERVED_17[16]; + uint8_t RESERVED_20[16]; __IO uint32_t TCE_HSCAN2; /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x280 */ __IO uint32_t TCE_HSCAN2_SET; /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x284 */ __IO uint32_t TCE_HSCAN2_CLR; /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x288 */ __IO uint32_t TCE_HSCAN2_TOG; /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x28C */ - uint8_t RESERVED_18[16]; + uint8_t RESERVED_21[16]; __IO uint32_t TCE_VSCAN; /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A0 */ __IO uint32_t TCE_VSCAN_SET; /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A4 */ __IO uint32_t TCE_VSCAN_CLR; /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A8 */ __IO uint32_t TCE_VSCAN_TOG; /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2AC */ - uint8_t RESERVED_19[16]; + uint8_t RESERVED_22[16]; __IO uint32_t TCE_OE; /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C0 */ __IO uint32_t TCE_OE_SET; /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C4 */ __IO uint32_t TCE_OE_CLR; /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C8 */ __IO uint32_t TCE_OE_TOG; /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2CC */ - uint8_t RESERVED_20[16]; + uint8_t RESERVED_23[16]; __IO uint32_t TCE_POLARITY; /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E0 */ __IO uint32_t TCE_POLARITY_SET; /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E4 */ __IO uint32_t TCE_POLARITY_CLR; /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E8 */ __IO uint32_t TCE_POLARITY_TOG; /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2EC */ - uint8_t RESERVED_21[16]; + uint8_t RESERVED_24[16]; __IO uint32_t TCE_TIMING1; /**< EPDC Timing Control Engine Timing Register 1, offset: 0x300 */ __IO uint32_t TCE_TIMING1_SET; /**< EPDC Timing Control Engine Timing Register 1, offset: 0x304 */ __IO uint32_t TCE_TIMING1_CLR; /**< EPDC Timing Control Engine Timing Register 1, offset: 0x308 */ @@ -66589,7 +14474,7 @@ typedef struct { __IO uint32_t TCE_TIMING3_SET; /**< EPDC Timing Control Engine Timing Register 3, offset: 0x324 */ __IO uint32_t TCE_TIMING3_CLR; /**< EPDC Timing Control Engine Timing Register 3, offset: 0x328 */ __IO uint32_t TCE_TIMING3_TOG; /**< EPDC Timing Control Engine Timing Register 3, offset: 0x32C */ - uint8_t RESERVED_22[80]; + uint8_t RESERVED_25[80]; __IO uint32_t PIGEON_CTRL0; /**< EPDC Pigeon Mode Control Register 0, offset: 0x380 */ __IO uint32_t PIGEON_CTRL0_SET; /**< EPDC Pigeon Mode Control Register 0, offset: 0x384 */ __IO uint32_t PIGEON_CTRL0_CLR; /**< EPDC Pigeon Mode Control Register 0, offset: 0x388 */ @@ -66598,7 +14483,7 @@ typedef struct { __IO uint32_t PIGEON_CTRL1_SET; /**< EPDC Pigeon Mode Control Register 1, offset: 0x394 */ __IO uint32_t PIGEON_CTRL1_CLR; /**< EPDC Pigeon Mode Control Register 1, offset: 0x398 */ __IO uint32_t PIGEON_CTRL1_TOG; /**< EPDC Pigeon Mode Control Register 1, offset: 0x39C */ - uint8_t RESERVED_23[32]; + uint8_t RESERVED_26[32]; __IO uint32_t IRQ_MASK1; /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C0 */ __IO uint32_t IRQ_MASK1_SET; /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C4 */ __IO uint32_t IRQ_MASK1_CLR; /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C8 */ @@ -66619,12 +14504,12 @@ typedef struct { __IO uint32_t IRQ_MASK_SET; /**< EPDC IRQ Mask Register, offset: 0x404 */ __IO uint32_t IRQ_MASK_CLR; /**< EPDC IRQ Mask Register, offset: 0x408 */ __IO uint32_t IRQ_MASK_TOG; /**< EPDC IRQ Mask Register, offset: 0x40C */ - uint8_t RESERVED_24[16]; + uint8_t RESERVED_27[16]; __IO uint32_t IRQ; /**< EPDC Interrupt Register, offset: 0x420 */ __IO uint32_t IRQ_SET; /**< EPDC Interrupt Register, offset: 0x424 */ __IO uint32_t IRQ_CLR; /**< EPDC Interrupt Register, offset: 0x428 */ __IO uint32_t IRQ_TOG; /**< EPDC Interrupt Register, offset: 0x42C */ - uint8_t RESERVED_25[16]; + uint8_t RESERVED_28[16]; __IO uint32_t STATUS_LUTS1; /**< EPDC Status Register - LUTs, offset: 0x440 */ __IO uint32_t STATUS_LUTS1_SET; /**< EPDC Status Register - LUTs, offset: 0x444 */ __IO uint32_t STATUS_LUTS1_CLR; /**< EPDC Status Register - LUTs, offset: 0x448 */ @@ -66634,7 +14519,7 @@ typedef struct { __IO uint32_t STATUS_LUTS2_CLR; /**< EPDC Status Register - LUTs, offset: 0x458 */ __IO uint32_t STATUS_LUTS2_TOG; /**< EPDC Status Register - LUTs, offset: 0x45C */ __IO uint32_t STATUS_NEXTLUT; /**< EPDC Status Register - Next Available LUT, offset: 0x460 */ - uint8_t RESERVED_26[28]; + uint8_t RESERVED_29[28]; __IO uint32_t STATUS_COL1; /**< EPDC LUT Collision Status, offset: 0x480 */ __IO uint32_t STATUS_COL1_SET; /**< EPDC LUT Collision Status, offset: 0x484 */ __IO uint32_t STATUS_COL1_CLR; /**< EPDC LUT Collision Status, offset: 0x488 */ @@ -66643,146 +14528,142 @@ typedef struct { __IO uint32_t STATUS_COL2_SET; /**< EPDC LUT Collision Status, offset: 0x494 */ __IO uint32_t STATUS_COL2_CLR; /**< EPDC LUT Collision Status, offset: 0x498 */ __IO uint32_t STATUS_COL2_TOG; /**< EPDC LUT Collision Status, offset: 0x49C */ - __IO uint32_t STATUS; /**< EPDC General Status Register, offset: 0x4A0 */ - __IO uint32_t STATUS_SET; /**< EPDC General Status Register, offset: 0x4A4 */ - __IO uint32_t STATUS_CLR; /**< EPDC General Status Register, offset: 0x4A8 */ - __IO uint32_t STATUS_TOG; /**< EPDC General Status Register, offset: 0x4AC */ - uint8_t RESERVED_27[16]; + __I uint32_t STATUS; /**< EPDC General Status Register, offset: 0x4A0 */ + __I uint32_t STATUS_SET; /**< EPDC General Status Register, offset: 0x4A4 */ + __I uint32_t STATUS_CLR; /**< EPDC General Status Register, offset: 0x4A8 */ + __I uint32_t STATUS_TOG; /**< EPDC General Status Register, offset: 0x4AC */ + uint8_t RESERVED_30[16]; __IO uint32_t UPD_COL_CORD; /**< EPDC Collision Region Co-ordinate, offset: 0x4C0 */ - uint8_t RESERVED_28[28]; + uint8_t RESERVED_31[28]; __IO uint32_t UPD_COL_SIZE; /**< EPDC Collision Region Size, offset: 0x4E0 */ - uint8_t RESERVED_29[284]; + uint8_t RESERVED_32[284]; __IO uint32_t HIST1_PARAM; /**< 1-level Histogram Parameter Register., offset: 0x600 */ - uint8_t RESERVED_30[12]; + uint8_t RESERVED_33[12]; __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x610 */ - uint8_t RESERVED_31[12]; + uint8_t RESERVED_34[12]; __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x620 */ - uint8_t RESERVED_32[12]; + uint8_t RESERVED_35[12]; __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x630 */ - uint8_t RESERVED_33[12]; + uint8_t RESERVED_36[12]; __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x640 */ - uint8_t RESERVED_34[12]; + uint8_t RESERVED_37[12]; __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x650 */ - uint8_t RESERVED_35[12]; + uint8_t RESERVED_38[12]; __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter Register., offset: 0x660 */ - uint8_t RESERVED_36[12]; + uint8_t RESERVED_39[12]; __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter Register., offset: 0x670 */ - uint8_t RESERVED_37[12]; + uint8_t RESERVED_40[12]; __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter Register., offset: 0x680 */ - uint8_t RESERVED_38[124]; + uint8_t RESERVED_41[124]; __IO uint32_t GPIO; /**< EPDC General Purpose I/O Debug register, offset: 0x700 */ __IO uint32_t GPIO_SET; /**< EPDC General Purpose I/O Debug register, offset: 0x704 */ __IO uint32_t GPIO_CLR; /**< EPDC General Purpose I/O Debug register, offset: 0x708 */ __IO uint32_t GPIO_TOG; /**< EPDC General Purpose I/O Debug register, offset: 0x70C */ - uint8_t RESERVED_39[224]; + uint8_t RESERVED_42[224]; __IO uint32_t VERSION; /**< EPDC Version Register, offset: 0x7F0 */ - uint8_t RESERVED_40[12]; + uint8_t RESERVED_43[12]; __IO uint32_t PIGEON_0_0; /**< Panel Interface Signal Generator Register 0_0, offset: 0x800 */ - uint8_t RESERVED_41[12]; + uint8_t RESERVED_44[12]; __IO uint32_t PIGEON_0_1; /**< Panel Interface Signal Generator Register 0_1, offset: 0x810 */ - uint8_t RESERVED_42[12]; + uint8_t RESERVED_45[12]; __IO uint32_t PIGEON_0_2; /**< Panel Interface Signal Generator Register 0_1, offset: 0x820 */ - uint8_t RESERVED_43[28]; + uint8_t RESERVED_46[28]; __IO uint32_t PIGEON_1_0; /**< Panel Interface Signal Generator Register 1_0, offset: 0x840 */ - uint8_t RESERVED_44[12]; + uint8_t RESERVED_47[12]; __IO uint32_t PIGEON_1_1; /**< Panel Interface Signal Generator Register 1_1, offset: 0x850 */ - uint8_t RESERVED_45[12]; + uint8_t RESERVED_48[12]; __IO uint32_t PIGEON_1_2; /**< Panel Interface Signal Generator Register 1_1, offset: 0x860 */ - uint8_t RESERVED_46[28]; + uint8_t RESERVED_49[28]; __IO uint32_t PIGEON_2_0; /**< Panel Interface Signal Generator Register 2_0, offset: 0x880 */ - uint8_t RESERVED_47[12]; + uint8_t RESERVED_50[12]; __IO uint32_t PIGEON_2_1; /**< Panel Interface Signal Generator Register 2_1, offset: 0x890 */ - uint8_t RESERVED_48[12]; + uint8_t RESERVED_51[12]; __IO uint32_t PIGEON_2_2; /**< Panel Interface Signal Generator Register 2_1, offset: 0x8A0 */ - uint8_t RESERVED_49[28]; + uint8_t RESERVED_52[28]; __IO uint32_t PIGEON_3_0; /**< Panel Interface Signal Generator Register 3_0, offset: 0x8C0 */ - uint8_t RESERVED_50[12]; + uint8_t RESERVED_53[12]; __IO uint32_t PIGEON_3_1; /**< Panel Interface Signal Generator Register 3_1, offset: 0x8D0 */ - uint8_t RESERVED_51[12]; + uint8_t RESERVED_54[12]; __IO uint32_t PIGEON_3_2; /**< Panel Interface Signal Generator Register 3_1, offset: 0x8E0 */ - uint8_t RESERVED_52[28]; + uint8_t RESERVED_55[28]; __IO uint32_t PIGEON_4_0; /**< Panel Interface Signal Generator Register 4_0, offset: 0x900 */ - uint8_t RESERVED_53[12]; + uint8_t RESERVED_56[12]; __IO uint32_t PIGEON_4_1; /**< Panel Interface Signal Generator Register 4_1, offset: 0x910 */ - uint8_t RESERVED_54[12]; + uint8_t RESERVED_57[12]; __IO uint32_t PIGEON_4_2; /**< Panel Interface Signal Generator Register 4_1, offset: 0x920 */ - uint8_t RESERVED_55[28]; + uint8_t RESERVED_58[28]; __IO uint32_t PIGEON_5_0; /**< Panel Interface Signal Generator Register 5_0, offset: 0x940 */ - uint8_t RESERVED_56[12]; + uint8_t RESERVED_59[12]; __IO uint32_t PIGEON_5_1; /**< Panel Interface Signal Generator Register 5_1, offset: 0x950 */ - uint8_t RESERVED_57[12]; + uint8_t RESERVED_60[12]; __IO uint32_t PIGEON_5_2; /**< Panel Interface Signal Generator Register 5_1, offset: 0x960 */ - uint8_t RESERVED_58[28]; + uint8_t RESERVED_61[28]; __IO uint32_t PIGEON_6_0; /**< Panel Interface Signal Generator Register 6_0, offset: 0x980 */ - uint8_t RESERVED_59[12]; + uint8_t RESERVED_62[12]; __IO uint32_t PIGEON_6_1; /**< Panel Interface Signal Generator Register 6_1, offset: 0x990 */ - uint8_t RESERVED_60[12]; + uint8_t RESERVED_63[12]; __IO uint32_t PIGEON_6_2; /**< Panel Interface Signal Generator Register 6_1, offset: 0x9A0 */ - uint8_t RESERVED_61[28]; + uint8_t RESERVED_64[28]; __IO uint32_t PIGEON_7_0; /**< Panel Interface Signal Generator Register 7_0, offset: 0x9C0 */ - uint8_t RESERVED_62[12]; + uint8_t RESERVED_65[12]; __IO uint32_t PIGEON_7_1; /**< Panel Interface Signal Generator Register 7_1, offset: 0x9D0 */ - uint8_t RESERVED_63[12]; + uint8_t RESERVED_66[12]; __IO uint32_t PIGEON_7_2; /**< Panel Interface Signal Generator Register 7_1, offset: 0x9E0 */ - uint8_t RESERVED_64[28]; + uint8_t RESERVED_67[28]; __IO uint32_t PIGEON_8_0; /**< Panel Interface Signal Generator Register 8_0, offset: 0xA00 */ - uint8_t RESERVED_65[12]; + uint8_t RESERVED_68[12]; __IO uint32_t PIGEON_8_1; /**< Panel Interface Signal Generator Register 8_1, offset: 0xA10 */ - uint8_t RESERVED_66[12]; + uint8_t RESERVED_69[12]; __IO uint32_t PIGEON_8_2; /**< Panel Interface Signal Generator Register 8_1, offset: 0xA20 */ - uint8_t RESERVED_67[28]; + uint8_t RESERVED_70[28]; __IO uint32_t PIGEON_9_0; /**< Panel Interface Signal Generator Register 9_0, offset: 0xA40 */ - uint8_t RESERVED_68[12]; + uint8_t RESERVED_71[12]; __IO uint32_t PIGEON_9_1; /**< Panel Interface Signal Generator Register 9_1, offset: 0xA50 */ - uint8_t RESERVED_69[12]; + uint8_t RESERVED_72[12]; __IO uint32_t PIGEON_9_2; /**< Panel Interface Signal Generator Register 9_1, offset: 0xA60 */ - uint8_t RESERVED_70[28]; + uint8_t RESERVED_73[28]; __IO uint32_t PIGEON_10_0; /**< Panel Interface Signal Generator Register 10_0, offset: 0xA80 */ - uint8_t RESERVED_71[12]; + uint8_t RESERVED_74[12]; __IO uint32_t PIGEON_10_1; /**< Panel Interface Signal Generator Register 10_1, offset: 0xA90 */ - uint8_t RESERVED_72[12]; + uint8_t RESERVED_75[12]; __IO uint32_t PIGEON_10_2; /**< Panel Interface Signal Generator Register 10_1, offset: 0xAA0 */ - uint8_t RESERVED_73[28]; + uint8_t RESERVED_76[28]; __IO uint32_t PIGEON_11_0; /**< Panel Interface Signal Generator Register 11_0, offset: 0xAC0 */ - uint8_t RESERVED_74[12]; + uint8_t RESERVED_77[12]; __IO uint32_t PIGEON_11_1; /**< Panel Interface Signal Generator Register 11_1, offset: 0xAD0 */ - uint8_t RESERVED_75[12]; + uint8_t RESERVED_78[12]; __IO uint32_t PIGEON_11_2; /**< Panel Interface Signal Generator Register 11_1, offset: 0xAE0 */ - uint8_t RESERVED_76[28]; + uint8_t RESERVED_79[28]; __IO uint32_t PIGEON_12_0; /**< Panel Interface Signal Generator Register 12_0, offset: 0xB00 */ - uint8_t RESERVED_77[12]; + uint8_t RESERVED_80[12]; __IO uint32_t PIGEON_12_1; /**< Panel Interface Signal Generator Register 12_1, offset: 0xB10 */ - uint8_t RESERVED_78[12]; + uint8_t RESERVED_81[12]; __IO uint32_t PIGEON_12_2; /**< Panel Interface Signal Generator Register 12_1, offset: 0xB20 */ - uint8_t RESERVED_79[28]; + uint8_t RESERVED_82[28]; __IO uint32_t PIGEON_13_0; /**< Panel Interface Signal Generator Register 13_0, offset: 0xB40 */ - uint8_t RESERVED_80[12]; + uint8_t RESERVED_83[12]; __IO uint32_t PIGEON_13_1; /**< Panel Interface Signal Generator Register 13_1, offset: 0xB50 */ - uint8_t RESERVED_81[12]; + uint8_t RESERVED_84[12]; __IO uint32_t PIGEON_13_2; /**< Panel Interface Signal Generator Register 13_1, offset: 0xB60 */ - uint8_t RESERVED_82[28]; + uint8_t RESERVED_85[28]; __IO uint32_t PIGEON_14_0; /**< Panel Interface Signal Generator Register 14_0, offset: 0xB80 */ - uint8_t RESERVED_83[12]; + uint8_t RESERVED_86[12]; __IO uint32_t PIGEON_14_1; /**< Panel Interface Signal Generator Register 14_1, offset: 0xB90 */ - uint8_t RESERVED_84[12]; + uint8_t RESERVED_87[12]; __IO uint32_t PIGEON_14_2; /**< Panel Interface Signal Generator Register 14_1, offset: 0xBA0 */ - uint8_t RESERVED_85[28]; + uint8_t RESERVED_88[28]; __IO uint32_t PIGEON_15_0; /**< Panel Interface Signal Generator Register 15_0, offset: 0xBC0 */ - uint8_t RESERVED_86[12]; + uint8_t RESERVED_89[12]; __IO uint32_t PIGEON_15_1; /**< Panel Interface Signal Generator Register 15_1, offset: 0xBD0 */ - uint8_t RESERVED_87[12]; + uint8_t RESERVED_90[12]; __IO uint32_t PIGEON_15_2; /**< Panel Interface Signal Generator Register 15_1, offset: 0xBE0 */ - uint8_t RESERVED_88[28]; + uint8_t RESERVED_91[28]; __IO uint32_t PIGEON_16_0; /**< Panel Interface Signal Generator Register 16_0, offset: 0xC00 */ - uint8_t RESERVED_89[12]; - union { /* offset: 0xC10 */ - __IO uint32_t PIGEON_16_1; /**< Panel Interface Signal Generator Register 16_1, offset: 0xC10 */ - __IO uint32_t WB_ADDR_TCE; /**< EPDC Working Buffer Address for TCE, offset: 0xC10 */ - }; - uint8_t RESERVED_90[12]; + uint8_t RESERVED_92[12]; + __IO uint32_t PIGEON_16_1; /**< Panel Interface Signal Generator Register 16_1, offset: 0xC10 */ + uint8_t RESERVED_93[12]; __IO uint32_t PIGEON_16_2; /**< Panel Interface Signal Generator Register 16_1, offset: 0xC20 */ } EPDC_Type, *EPDC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- EPDC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -66798,6 +14679,7 @@ typedef struct { #define EPDC_CTRL_SET_REG(base) ((base)->CTRL_SET) #define EPDC_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define EPDC_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define EPDC_WB_ADDR_TCE_REG(base) ((base)->WB_ADDR_TCE) #define EPDC_WVADDR_REG(base) ((base)->WVADDR) #define EPDC_WB_ADDR_REG(base) ((base)->WB_ADDR) #define EPDC_RES_REG(base) ((base)->RES) @@ -66805,6 +14687,10 @@ typedef struct { #define EPDC_FORMAT_SET_REG(base) ((base)->FORMAT_SET) #define EPDC_FORMAT_CLR_REG(base) ((base)->FORMAT_CLR) #define EPDC_FORMAT_TOG_REG(base) ((base)->FORMAT_TOG) +#define EPDC_WB_FIELD0_REG(base) ((base)->WB_FIELD0) +#define EPDC_WB_FIELD1_REG(base) ((base)->WB_FIELD1) +#define EPDC_WB_FIELD2_REG(base) ((base)->WB_FIELD2) +#define EPDC_WB_FIELD3_REG(base) ((base)->WB_FIELD3) #define EPDC_FIFOCTRL_REG(base) ((base)->FIFOCTRL) #define EPDC_FIFOCTRL_SET_REG(base) ((base)->FIFOCTRL_SET) #define EPDC_FIFOCTRL_CLR_REG(base) ((base)->FIFOCTRL_CLR) @@ -66823,6 +14709,14 @@ typedef struct { #define EPDC_UPD_FIXED_TOG_REG(base) ((base)->UPD_FIXED_TOG) #define EPDC_TEMP_REG(base) ((base)->TEMP) #define EPDC_AUTOWV_LUT_REG(base) ((base)->AUTOWV_LUT) +#define EPDC_LUT_STANDBY1_REG(base) ((base)->LUT_STANDBY1) +#define EPDC_LUT_STANDBY1_SET_REG(base) ((base)->LUT_STANDBY1_SET) +#define EPDC_LUT_STANDBY1_CLR_REG(base) ((base)->LUT_STANDBY1_CLR) +#define EPDC_LUT_STANDBY1_TOG_REG(base) ((base)->LUT_STANDBY1_TOG) +#define EPDC_LUT_STANDBY2_REG(base) ((base)->LUT_STANDBY2) +#define EPDC_LUT_STANDBY2_SET_REG(base) ((base)->LUT_STANDBY2_SET) +#define EPDC_LUT_STANDBY2_CLR_REG(base) ((base)->LUT_STANDBY2_CLR) +#define EPDC_LUT_STANDBY2_TOG_REG(base) ((base)->LUT_STANDBY2_TOG) #define EPDC_TCE_CTRL_REG(base) ((base)->TCE_CTRL) #define EPDC_TCE_CTRL_SET_REG(base) ((base)->TCE_CTRL_SET) #define EPDC_TCE_CTRL_CLR_REG(base) ((base)->TCE_CTRL_CLR) @@ -66986,14 +14880,11 @@ typedef struct { #define EPDC_PIGEON_15_2_REG(base) ((base)->PIGEON_15_2) #define EPDC_PIGEON_16_0_REG(base) ((base)->PIGEON_16_0) #define EPDC_PIGEON_16_1_REG(base) ((base)->PIGEON_16_1) -#define EPDC_WB_ADDR_TCE_REG(base) ((base)->WB_ADDR_TCE) #define EPDC_PIGEON_16_2_REG(base) ((base)->PIGEON_16_2) /*! * @} */ /* end of group EPDC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- EPDC Register Masks ---------------------------------------------------------------------------- */ @@ -67004,8 +14895,6 @@ typedef struct { */ /* CTRL Bit Fields */ -#define EPDC_CTRL_BURST_LEN_8_MASK 0x1u -#define EPDC_CTRL_BURST_LEN_8_SHIFT 0 #define EPDC_CTRL_LUT_DATA_SWIZZLE_MASK 0x30u #define EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT 4 #define EPDC_CTRL_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_LUT_DATA_SWIZZLE_MASK) @@ -67017,8 +14906,6 @@ typedef struct { #define EPDC_CTRL_SFTRST_MASK 0x80000000u #define EPDC_CTRL_SFTRST_SHIFT 31 /* CTRL_SET Bit Fields */ -#define EPDC_CTRL_SET_BURST_LEN_8_MASK 0x1u -#define EPDC_CTRL_SET_BURST_LEN_8_SHIFT 0 #define EPDC_CTRL_SET_LUT_DATA_SWIZZLE_MASK 0x30u #define EPDC_CTRL_SET_LUT_DATA_SWIZZLE_SHIFT 4 #define EPDC_CTRL_SET_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_SET_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_SET_LUT_DATA_SWIZZLE_MASK) @@ -67030,8 +14917,6 @@ typedef struct { #define EPDC_CTRL_SET_SFTRST_MASK 0x80000000u #define EPDC_CTRL_SET_SFTRST_SHIFT 31 /* CTRL_CLR Bit Fields */ -#define EPDC_CTRL_CLR_BURST_LEN_8_MASK 0x1u -#define EPDC_CTRL_CLR_BURST_LEN_8_SHIFT 0 #define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_MASK 0x30u #define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_SHIFT 4 #define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_MASK) @@ -67043,8 +14928,6 @@ typedef struct { #define EPDC_CTRL_CLR_SFTRST_MASK 0x80000000u #define EPDC_CTRL_CLR_SFTRST_SHIFT 31 /* CTRL_TOG Bit Fields */ -#define EPDC_CTRL_TOG_BURST_LEN_8_MASK 0x1u -#define EPDC_CTRL_TOG_BURST_LEN_8_SHIFT 0 #define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_MASK 0x30u #define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_SHIFT 4 #define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_MASK) @@ -67055,6 +14938,10 @@ typedef struct { #define EPDC_CTRL_TOG_CLKGATE_SHIFT 30 #define EPDC_CTRL_TOG_SFTRST_MASK 0x80000000u #define EPDC_CTRL_TOG_SFTRST_SHIFT 31 +/* WB_ADDR_TCE Bit Fields */ +#define EPDC_WB_ADDR_TCE_ADDR_MASK 0xFFFFFFFFu +#define EPDC_WB_ADDR_TCE_ADDR_SHIFT 0 +#define EPDC_WB_ADDR_TCE_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_ADDR_TCE_ADDR_SHIFT))&EPDC_WB_ADDR_TCE_ADDR_MASK) /* WVADDR Bit Fields */ #define EPDC_WVADDR_ADDR_MASK 0xFFFFFFFFu #define EPDC_WVADDR_ADDR_SHIFT 0 @@ -67077,6 +14964,13 @@ typedef struct { #define EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK 0x700u #define EPDC_FORMAT_BUF_PIXEL_FORMAT_SHIFT 8 #define EPDC_FORMAT_BUF_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_WB_COMPRESS_MASK 0x800u +#define EPDC_FORMAT_WB_COMPRESS_SHIFT 11 +#define EPDC_FORMAT_WB_TYPE_MASK 0x3000u +#define EPDC_FORMAT_WB_TYPE_SHIFT 12 +#define EPDC_FORMAT_WB_TYPE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_WB_TYPE_SHIFT))&EPDC_FORMAT_WB_TYPE_MASK) +#define EPDC_FORMAT_WB_ADDR_NO_COPY_MASK 0x4000u +#define EPDC_FORMAT_WB_ADDR_NO_COPY_SHIFT 14 #define EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK 0xFF0000u #define EPDC_FORMAT_DEFAULT_TFT_PIXEL_SHIFT 16 #define EPDC_FORMAT_DEFAULT_TFT_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK) @@ -67089,6 +14983,13 @@ typedef struct { #define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_MASK 0x700u #define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_SHIFT 8 #define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_SET_WB_COMPRESS_MASK 0x800u +#define EPDC_FORMAT_SET_WB_COMPRESS_SHIFT 11 +#define EPDC_FORMAT_SET_WB_TYPE_MASK 0x3000u +#define EPDC_FORMAT_SET_WB_TYPE_SHIFT 12 +#define EPDC_FORMAT_SET_WB_TYPE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_WB_TYPE_SHIFT))&EPDC_FORMAT_SET_WB_TYPE_MASK) +#define EPDC_FORMAT_SET_WB_ADDR_NO_COPY_MASK 0x4000u +#define EPDC_FORMAT_SET_WB_ADDR_NO_COPY_SHIFT 14 #define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_MASK 0xFF0000u #define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_SHIFT 16 #define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_MASK) @@ -67101,6 +15002,13 @@ typedef struct { #define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_MASK 0x700u #define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_SHIFT 8 #define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_CLR_WB_COMPRESS_MASK 0x800u +#define EPDC_FORMAT_CLR_WB_COMPRESS_SHIFT 11 +#define EPDC_FORMAT_CLR_WB_TYPE_MASK 0x3000u +#define EPDC_FORMAT_CLR_WB_TYPE_SHIFT 12 +#define EPDC_FORMAT_CLR_WB_TYPE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_WB_TYPE_SHIFT))&EPDC_FORMAT_CLR_WB_TYPE_MASK) +#define EPDC_FORMAT_CLR_WB_ADDR_NO_COPY_MASK 0x4000u +#define EPDC_FORMAT_CLR_WB_ADDR_NO_COPY_SHIFT 14 #define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_MASK 0xFF0000u #define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_SHIFT 16 #define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_MASK) @@ -67113,11 +15021,94 @@ typedef struct { #define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_MASK 0x700u #define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_SHIFT 8 #define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_TOG_WB_COMPRESS_MASK 0x800u +#define EPDC_FORMAT_TOG_WB_COMPRESS_SHIFT 11 +#define EPDC_FORMAT_TOG_WB_TYPE_MASK 0x3000u +#define EPDC_FORMAT_TOG_WB_TYPE_SHIFT 12 +#define EPDC_FORMAT_TOG_WB_TYPE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_WB_TYPE_SHIFT))&EPDC_FORMAT_TOG_WB_TYPE_MASK) +#define EPDC_FORMAT_TOG_WB_ADDR_NO_COPY_MASK 0x4000u +#define EPDC_FORMAT_TOG_WB_ADDR_NO_COPY_SHIFT 14 #define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_MASK 0xFF0000u #define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_SHIFT 16 #define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_MASK) #define EPDC_FORMAT_TOG_BUF_PIXEL_SCALE_MASK 0x1000000u #define EPDC_FORMAT_TOG_BUF_PIXEL_SCALE_SHIFT 24 +/* WB_FIELD0 Bit Fields */ +#define EPDC_WB_FIELD0_LEN_MASK 0xFu +#define EPDC_WB_FIELD0_LEN_SHIFT 0 +#define EPDC_WB_FIELD0_LEN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_LEN_SHIFT))&EPDC_WB_FIELD0_LEN_MASK) +#define EPDC_WB_FIELD0_TO_MASK 0xF0u +#define EPDC_WB_FIELD0_TO_SHIFT 4 +#define EPDC_WB_FIELD0_TO(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_TO_SHIFT))&EPDC_WB_FIELD0_TO_MASK) +#define EPDC_WB_FIELD0_FROM_MASK 0x1F00u +#define EPDC_WB_FIELD0_FROM_SHIFT 8 +#define EPDC_WB_FIELD0_FROM(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_FROM_SHIFT))&EPDC_WB_FIELD0_FROM_MASK) +#define EPDC_WB_FIELD0_USAGE_MASK 0xE000u +#define EPDC_WB_FIELD0_USAGE_SHIFT 13 +#define EPDC_WB_FIELD0_USAGE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_USAGE_SHIFT))&EPDC_WB_FIELD0_USAGE_MASK) +#define EPDC_WB_FIELD0_USE_FIXED_MASK 0x30000u +#define EPDC_WB_FIELD0_USE_FIXED_SHIFT 16 +#define EPDC_WB_FIELD0_USE_FIXED(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_USE_FIXED_SHIFT))&EPDC_WB_FIELD0_USE_FIXED_MASK) +#define EPDC_WB_FIELD0_FIXED_MASK 0xFF000000u +#define EPDC_WB_FIELD0_FIXED_SHIFT 24 +#define EPDC_WB_FIELD0_FIXED(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD0_FIXED_SHIFT))&EPDC_WB_FIELD0_FIXED_MASK) +/* WB_FIELD1 Bit Fields */ +#define EPDC_WB_FIELD1_LEN_MASK 0xFu +#define EPDC_WB_FIELD1_LEN_SHIFT 0 +#define EPDC_WB_FIELD1_LEN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_LEN_SHIFT))&EPDC_WB_FIELD1_LEN_MASK) +#define EPDC_WB_FIELD1_TO_MASK 0xF0u +#define EPDC_WB_FIELD1_TO_SHIFT 4 +#define EPDC_WB_FIELD1_TO(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_TO_SHIFT))&EPDC_WB_FIELD1_TO_MASK) +#define EPDC_WB_FIELD1_FROM_MASK 0x1F00u +#define EPDC_WB_FIELD1_FROM_SHIFT 8 +#define EPDC_WB_FIELD1_FROM(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_FROM_SHIFT))&EPDC_WB_FIELD1_FROM_MASK) +#define EPDC_WB_FIELD1_USAGE_MASK 0xE000u +#define EPDC_WB_FIELD1_USAGE_SHIFT 13 +#define EPDC_WB_FIELD1_USAGE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_USAGE_SHIFT))&EPDC_WB_FIELD1_USAGE_MASK) +#define EPDC_WB_FIELD1_USE_FIXED_MASK 0x30000u +#define EPDC_WB_FIELD1_USE_FIXED_SHIFT 16 +#define EPDC_WB_FIELD1_USE_FIXED(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_USE_FIXED_SHIFT))&EPDC_WB_FIELD1_USE_FIXED_MASK) +#define EPDC_WB_FIELD1_FIXED_MASK 0xFF000000u +#define EPDC_WB_FIELD1_FIXED_SHIFT 24 +#define EPDC_WB_FIELD1_FIXED(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD1_FIXED_SHIFT))&EPDC_WB_FIELD1_FIXED_MASK) +/* WB_FIELD2 Bit Fields */ +#define EPDC_WB_FIELD2_LEN_MASK 0xFu +#define EPDC_WB_FIELD2_LEN_SHIFT 0 +#define EPDC_WB_FIELD2_LEN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_LEN_SHIFT))&EPDC_WB_FIELD2_LEN_MASK) +#define EPDC_WB_FIELD2_TO_MASK 0xF0u +#define EPDC_WB_FIELD2_TO_SHIFT 4 +#define EPDC_WB_FIELD2_TO(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_TO_SHIFT))&EPDC_WB_FIELD2_TO_MASK) +#define EPDC_WB_FIELD2_FROM_MASK 0x1F00u +#define EPDC_WB_FIELD2_FROM_SHIFT 8 +#define EPDC_WB_FIELD2_FROM(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_FROM_SHIFT))&EPDC_WB_FIELD2_FROM_MASK) +#define EPDC_WB_FIELD2_USAGE_MASK 0xE000u +#define EPDC_WB_FIELD2_USAGE_SHIFT 13 +#define EPDC_WB_FIELD2_USAGE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_USAGE_SHIFT))&EPDC_WB_FIELD2_USAGE_MASK) +#define EPDC_WB_FIELD2_USE_FIXED_MASK 0x30000u +#define EPDC_WB_FIELD2_USE_FIXED_SHIFT 16 +#define EPDC_WB_FIELD2_USE_FIXED(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_USE_FIXED_SHIFT))&EPDC_WB_FIELD2_USE_FIXED_MASK) +#define EPDC_WB_FIELD2_FIXED_MASK 0xFF000000u +#define EPDC_WB_FIELD2_FIXED_SHIFT 24 +#define EPDC_WB_FIELD2_FIXED(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD2_FIXED_SHIFT))&EPDC_WB_FIELD2_FIXED_MASK) +/* WB_FIELD3 Bit Fields */ +#define EPDC_WB_FIELD3_LEN_MASK 0xFu +#define EPDC_WB_FIELD3_LEN_SHIFT 0 +#define EPDC_WB_FIELD3_LEN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_LEN_SHIFT))&EPDC_WB_FIELD3_LEN_MASK) +#define EPDC_WB_FIELD3_TO_MASK 0xF0u +#define EPDC_WB_FIELD3_TO_SHIFT 4 +#define EPDC_WB_FIELD3_TO(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_TO_SHIFT))&EPDC_WB_FIELD3_TO_MASK) +#define EPDC_WB_FIELD3_FROM_MASK 0x1F00u +#define EPDC_WB_FIELD3_FROM_SHIFT 8 +#define EPDC_WB_FIELD3_FROM(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_FROM_SHIFT))&EPDC_WB_FIELD3_FROM_MASK) +#define EPDC_WB_FIELD3_USAGE_MASK 0xE000u +#define EPDC_WB_FIELD3_USAGE_SHIFT 13 +#define EPDC_WB_FIELD3_USAGE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_USAGE_SHIFT))&EPDC_WB_FIELD3_USAGE_MASK) +#define EPDC_WB_FIELD3_USE_FIXED_MASK 0x30000u +#define EPDC_WB_FIELD3_USE_FIXED_SHIFT 16 +#define EPDC_WB_FIELD3_USE_FIXED(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_USE_FIXED_SHIFT))&EPDC_WB_FIELD3_USE_FIXED_MASK) +#define EPDC_WB_FIELD3_FIXED_MASK 0xFF000000u +#define EPDC_WB_FIELD3_FIXED_SHIFT 24 +#define EPDC_WB_FIELD3_FIXED(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_FIELD3_FIXED_SHIFT))&EPDC_WB_FIELD3_FIXED_MASK) /* FIFOCTRL Bit Fields */ #define EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK 0xFFu #define EPDC_FIFOCTRL_FIFO_L_LEVEL_SHIFT 0 @@ -67195,10 +15186,12 @@ typedef struct { #define EPDC_UPD_CTRL_DRY_RUN_SHIFT 1 #define EPDC_UPD_CTRL_AUTOWV_MASK 0x4u #define EPDC_UPD_CTRL_AUTOWV_SHIFT 2 -#define EPDC_UPD_CTRL_AUTOWV_PAUSE_MASK 0x8u -#define EPDC_UPD_CTRL_AUTOWV_PAUSE_SHIFT 3 +#define EPDC_UPD_CTRL_PAUSE_MASK 0x8u +#define EPDC_UPD_CTRL_PAUSE_SHIFT 3 #define EPDC_UPD_CTRL_NO_LUT_CANCEL_MASK 0x10u #define EPDC_UPD_CTRL_NO_LUT_CANCEL_SHIFT 4 +#define EPDC_UPD_CTRL_STANDBY_MASK 0x20u +#define EPDC_UPD_CTRL_STANDBY_SHIFT 5 #define EPDC_UPD_CTRL_WAVEFORM_MODE_MASK 0xFF00u #define EPDC_UPD_CTRL_WAVEFORM_MODE_SHIFT 8 #define EPDC_UPD_CTRL_WAVEFORM_MODE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) @@ -67214,10 +15207,12 @@ typedef struct { #define EPDC_UPD_CTRL_SET_DRY_RUN_SHIFT 1 #define EPDC_UPD_CTRL_SET_AUTOWV_MASK 0x4u #define EPDC_UPD_CTRL_SET_AUTOWV_SHIFT 2 -#define EPDC_UPD_CTRL_SET_AUTOWV_PAUSE_MASK 0x8u -#define EPDC_UPD_CTRL_SET_AUTOWV_PAUSE_SHIFT 3 +#define EPDC_UPD_CTRL_SET_PAUSE_MASK 0x8u +#define EPDC_UPD_CTRL_SET_PAUSE_SHIFT 3 #define EPDC_UPD_CTRL_SET_NO_LUT_CANCEL_MASK 0x10u #define EPDC_UPD_CTRL_SET_NO_LUT_CANCEL_SHIFT 4 +#define EPDC_UPD_CTRL_SET_STANDBY_MASK 0x20u +#define EPDC_UPD_CTRL_SET_STANDBY_SHIFT 5 #define EPDC_UPD_CTRL_SET_WAVEFORM_MODE_MASK 0xFF00u #define EPDC_UPD_CTRL_SET_WAVEFORM_MODE_SHIFT 8 #define EPDC_UPD_CTRL_SET_WAVEFORM_MODE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_SET_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_SET_WAVEFORM_MODE_MASK) @@ -67233,10 +15228,12 @@ typedef struct { #define EPDC_UPD_CTRL_CLR_DRY_RUN_SHIFT 1 #define EPDC_UPD_CTRL_CLR_AUTOWV_MASK 0x4u #define EPDC_UPD_CTRL_CLR_AUTOWV_SHIFT 2 -#define EPDC_UPD_CTRL_CLR_AUTOWV_PAUSE_MASK 0x8u -#define EPDC_UPD_CTRL_CLR_AUTOWV_PAUSE_SHIFT 3 +#define EPDC_UPD_CTRL_CLR_PAUSE_MASK 0x8u +#define EPDC_UPD_CTRL_CLR_PAUSE_SHIFT 3 #define EPDC_UPD_CTRL_CLR_NO_LUT_CANCEL_MASK 0x10u #define EPDC_UPD_CTRL_CLR_NO_LUT_CANCEL_SHIFT 4 +#define EPDC_UPD_CTRL_CLR_STANDBY_MASK 0x20u +#define EPDC_UPD_CTRL_CLR_STANDBY_SHIFT 5 #define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_MASK 0xFF00u #define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_SHIFT 8 #define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_MASK) @@ -67252,10 +15249,12 @@ typedef struct { #define EPDC_UPD_CTRL_TOG_DRY_RUN_SHIFT 1 #define EPDC_UPD_CTRL_TOG_AUTOWV_MASK 0x4u #define EPDC_UPD_CTRL_TOG_AUTOWV_SHIFT 2 -#define EPDC_UPD_CTRL_TOG_AUTOWV_PAUSE_MASK 0x8u -#define EPDC_UPD_CTRL_TOG_AUTOWV_PAUSE_SHIFT 3 +#define EPDC_UPD_CTRL_TOG_PAUSE_MASK 0x8u +#define EPDC_UPD_CTRL_TOG_PAUSE_SHIFT 3 #define EPDC_UPD_CTRL_TOG_NO_LUT_CANCEL_MASK 0x10u #define EPDC_UPD_CTRL_TOG_NO_LUT_CANCEL_SHIFT 4 +#define EPDC_UPD_CTRL_TOG_STANDBY_MASK 0x20u +#define EPDC_UPD_CTRL_TOG_STANDBY_SHIFT 5 #define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_MASK 0xFF00u #define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_SHIFT 8 #define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_MASK) @@ -67319,6 +15318,38 @@ typedef struct { #define EPDC_AUTOWV_LUT_DATA_MASK 0xFF0000u #define EPDC_AUTOWV_LUT_DATA_SHIFT 16 #define EPDC_AUTOWV_LUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<EPDC_AUTOWV_LUT_DATA_SHIFT))&EPDC_AUTOWV_LUT_DATA_MASK) +/* LUT_STANDBY1 Bit Fields */ +#define EPDC_LUT_STANDBY1_LUTN_MASK 0xFFFFFFFFu +#define EPDC_LUT_STANDBY1_LUTN_SHIFT 0 +#define EPDC_LUT_STANDBY1_LUTN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY1_LUTN_SHIFT))&EPDC_LUT_STANDBY1_LUTN_MASK) +/* LUT_STANDBY1_SET Bit Fields */ +#define EPDC_LUT_STANDBY1_SET_LUTN_MASK 0xFFFFFFFFu +#define EPDC_LUT_STANDBY1_SET_LUTN_SHIFT 0 +#define EPDC_LUT_STANDBY1_SET_LUTN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY1_SET_LUTN_SHIFT))&EPDC_LUT_STANDBY1_SET_LUTN_MASK) +/* LUT_STANDBY1_CLR Bit Fields */ +#define EPDC_LUT_STANDBY1_CLR_LUTN_MASK 0xFFFFFFFFu +#define EPDC_LUT_STANDBY1_CLR_LUTN_SHIFT 0 +#define EPDC_LUT_STANDBY1_CLR_LUTN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY1_CLR_LUTN_SHIFT))&EPDC_LUT_STANDBY1_CLR_LUTN_MASK) +/* LUT_STANDBY1_TOG Bit Fields */ +#define EPDC_LUT_STANDBY1_TOG_LUTN_MASK 0xFFFFFFFFu +#define EPDC_LUT_STANDBY1_TOG_LUTN_SHIFT 0 +#define EPDC_LUT_STANDBY1_TOG_LUTN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY1_TOG_LUTN_SHIFT))&EPDC_LUT_STANDBY1_TOG_LUTN_MASK) +/* LUT_STANDBY2 Bit Fields */ +#define EPDC_LUT_STANDBY2_LUTN_MASK 0xFFFFFFFFu +#define EPDC_LUT_STANDBY2_LUTN_SHIFT 0 +#define EPDC_LUT_STANDBY2_LUTN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY2_LUTN_SHIFT))&EPDC_LUT_STANDBY2_LUTN_MASK) +/* LUT_STANDBY2_SET Bit Fields */ +#define EPDC_LUT_STANDBY2_SET_LUTN_MASK 0xFFFFFFFFu +#define EPDC_LUT_STANDBY2_SET_LUTN_SHIFT 0 +#define EPDC_LUT_STANDBY2_SET_LUTN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY2_SET_LUTN_SHIFT))&EPDC_LUT_STANDBY2_SET_LUTN_MASK) +/* LUT_STANDBY2_CLR Bit Fields */ +#define EPDC_LUT_STANDBY2_CLR_LUTN_MASK 0xFFFFFFFFu +#define EPDC_LUT_STANDBY2_CLR_LUTN_SHIFT 0 +#define EPDC_LUT_STANDBY2_CLR_LUTN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY2_CLR_LUTN_SHIFT))&EPDC_LUT_STANDBY2_CLR_LUTN_MASK) +/* LUT_STANDBY2_TOG Bit Fields */ +#define EPDC_LUT_STANDBY2_TOG_LUTN_MASK 0xFFFFFFFFu +#define EPDC_LUT_STANDBY2_TOG_LUTN_SHIFT 0 +#define EPDC_LUT_STANDBY2_TOG_LUTN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_LUT_STANDBY2_TOG_LUTN_SHIFT))&EPDC_LUT_STANDBY2_TOG_LUTN_MASK) /* TCE_CTRL Bit Fields */ #define EPDC_TCE_CTRL_PIXELS_PER_SDCLK_MASK 0x3u #define EPDC_TCE_CTRL_PIXELS_PER_SDCLK_SHIFT 0 @@ -68952,10 +16983,6 @@ typedef struct { #define EPDC_PIGEON_16_1_CLR_CNT_MASK 0xFFFF0000u #define EPDC_PIGEON_16_1_CLR_CNT_SHIFT 16 #define EPDC_PIGEON_16_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_1_CLR_CNT_SHIFT))&EPDC_PIGEON_16_1_CLR_CNT_MASK) -/* WB_ADDR_TCE Bit Fields */ -#define EPDC_WB_ADDR_TCE_ADDR_MASK 0xFFFFFFFFu -#define EPDC_WB_ADDR_TCE_ADDR_SHIFT 0 -#define EPDC_WB_ADDR_TCE_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_ADDR_TCE_ADDR_SHIFT))&EPDC_WB_ADDR_TCE_ADDR_MASK) /* PIGEON_16_2 Bit Fields */ #define EPDC_PIGEON_16_2_SIG_LOGIC_MASK 0xFu #define EPDC_PIGEON_16_2_SIG_LOGIC_SHIFT 0 @@ -68968,18 +16995,18 @@ typedef struct { * @} */ /* end of group EPDC_Register_Masks */ - /* EPDC - Peripheral instance base addresses */ /** Peripheral EPDC base address */ #define EPDC_BASE (0x306F0000u) /** Peripheral EPDC base pointer */ #define EPDC ((EPDC_Type *)EPDC_BASE) #define EPDC_BASE_PTR (EPDC) -/** Array initializer of EPDC peripheral base adresses */ +/** Array initializer of EPDC peripheral base addresses */ #define EPDC_BASE_ADDRS { EPDC_BASE } /** Array initializer of EPDC peripheral base pointers */ #define EPDC_BASE_PTRS { EPDC } - +/** Interrupt vectors for the EPDC peripheral type */ +#define EPDC_IRQS { EPDC_IRQn } /* ---------------------------------------------------------------------------- -- EPDC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -68996,6 +17023,7 @@ typedef struct { #define EPDC_CTRL_SET EPDC_CTRL_SET_REG(EPDC_BASE_PTR) #define EPDC_CTRL_CLR EPDC_CTRL_CLR_REG(EPDC_BASE_PTR) #define EPDC_CTRL_TOG EPDC_CTRL_TOG_REG(EPDC_BASE_PTR) +#define EPDC_WB_ADDR_TCE EPDC_WB_ADDR_TCE_REG(EPDC_BASE_PTR) #define EPDC_WVADDR EPDC_WVADDR_REG(EPDC_BASE_PTR) #define EPDC_WB_ADDR EPDC_WB_ADDR_REG(EPDC_BASE_PTR) #define EPDC_RES EPDC_RES_REG(EPDC_BASE_PTR) @@ -69003,6 +17031,10 @@ typedef struct { #define EPDC_FORMAT_SET EPDC_FORMAT_SET_REG(EPDC_BASE_PTR) #define EPDC_FORMAT_CLR EPDC_FORMAT_CLR_REG(EPDC_BASE_PTR) #define EPDC_FORMAT_TOG EPDC_FORMAT_TOG_REG(EPDC_BASE_PTR) +#define EPDC_WB_FIELD0 EPDC_WB_FIELD0_REG(EPDC_BASE_PTR) +#define EPDC_WB_FIELD1 EPDC_WB_FIELD1_REG(EPDC_BASE_PTR) +#define EPDC_WB_FIELD2 EPDC_WB_FIELD2_REG(EPDC_BASE_PTR) +#define EPDC_WB_FIELD3 EPDC_WB_FIELD3_REG(EPDC_BASE_PTR) #define EPDC_FIFOCTRL EPDC_FIFOCTRL_REG(EPDC_BASE_PTR) #define EPDC_FIFOCTRL_SET EPDC_FIFOCTRL_SET_REG(EPDC_BASE_PTR) #define EPDC_FIFOCTRL_CLR EPDC_FIFOCTRL_CLR_REG(EPDC_BASE_PTR) @@ -69021,6 +17053,14 @@ typedef struct { #define EPDC_UPD_FIXED_TOG EPDC_UPD_FIXED_TOG_REG(EPDC_BASE_PTR) #define EPDC_TEMP EPDC_TEMP_REG(EPDC_BASE_PTR) #define EPDC_AUTOWV_LUT EPDC_AUTOWV_LUT_REG(EPDC_BASE_PTR) +#define EPDC_LUT_STANDBY1 EPDC_LUT_STANDBY1_REG(EPDC_BASE_PTR) +#define EPDC_LUT_STANDBY1_SET EPDC_LUT_STANDBY1_SET_REG(EPDC_BASE_PTR) +#define EPDC_LUT_STANDBY1_CLR EPDC_LUT_STANDBY1_CLR_REG(EPDC_BASE_PTR) +#define EPDC_LUT_STANDBY1_TOG EPDC_LUT_STANDBY1_TOG_REG(EPDC_BASE_PTR) +#define EPDC_LUT_STANDBY2 EPDC_LUT_STANDBY2_REG(EPDC_BASE_PTR) +#define EPDC_LUT_STANDBY2_SET EPDC_LUT_STANDBY2_SET_REG(EPDC_BASE_PTR) +#define EPDC_LUT_STANDBY2_CLR EPDC_LUT_STANDBY2_CLR_REG(EPDC_BASE_PTR) +#define EPDC_LUT_STANDBY2_TOG EPDC_LUT_STANDBY2_TOG_REG(EPDC_BASE_PTR) #define EPDC_TCE_CTRL EPDC_TCE_CTRL_REG(EPDC_BASE_PTR) #define EPDC_TCE_CTRL_SET EPDC_TCE_CTRL_SET_REG(EPDC_BASE_PTR) #define EPDC_TCE_CTRL_CLR EPDC_TCE_CTRL_CLR_REG(EPDC_BASE_PTR) @@ -69184,9 +17224,7 @@ typedef struct { #define EPDC_PIGEON_15_2 EPDC_PIGEON_15_2_REG(EPDC_BASE_PTR) #define EPDC_PIGEON_16_0 EPDC_PIGEON_16_0_REG(EPDC_BASE_PTR) #define EPDC_PIGEON_16_1 EPDC_PIGEON_16_1_REG(EPDC_BASE_PTR) -#define EPDC_WB_ADDR_TCE EPDC_WB_ADDR_TCE_REG(EPDC_BASE_PTR) #define EPDC_PIGEON_16_2 EPDC_PIGEON_16_2_REG(EPDC_BASE_PTR) - /*! * @} */ /* end of group EPDC_Register_Accessor_Macros */ @@ -69196,6 +17234,472 @@ typedef struct { * @} */ /* end of group EPDC_Peripheral */ +/* ---------------------------------------------------------------------------- + -- SIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer + * @{ + */ + +/** SIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PORT1_CNTL; /**< SIM Port1 Control Register, offset: 0x0 */ + __IO uint32_t SETUP; /**< SIM Setup Register, offset: 0x4 */ + __IO uint32_t PORT1_DETECT; /**< SIM Port 1 Detect Register, offset: 0x8 */ + __IO uint32_t XMT_BUF; /**< SIM Transmit Buffer Register, offset: 0xC */ + __I uint32_t RCV_BUF; /**< SIM Receive Buffer Register, offset: 0x10 */ + __IO uint32_t PORT0_CNTL; /**< SIM Port0 Control Register, offset: 0x14 */ + __IO uint32_t CNTL; /**< SIM Control Register, offset: 0x18 */ + __IO uint32_t CLK_PRESCALER; /**< SIM Clock Prescaler Register, offset: 0x1C */ + __IO uint32_t RCV_THRESHOLD; /**< SIM Receive Threshold Register, offset: 0x20 */ + __IO uint32_t ENABLE; /**< SIM Enable Register, offset: 0x24 */ + __IO uint32_t XMT_STATUS; /**< SIM Transmit Status Register, offset: 0x28 */ + __IO uint32_t RCV_STATUS; /**< SIM Receive Status Register, offset: 0x2C */ + __IO uint32_t INT_MASK; /**< SIM Interrupt Mask Register, offset: 0x30 */ + uint8_t RESERVED_0[8]; + __IO uint32_t PORT0_DETECT; /**< SIM Port0 Detect Register, offset: 0x3C */ + __IO uint32_t DATA_FORMAT; /**< SIM Data Format Register, offset: 0x40 */ + __IO uint32_t XMT_THRESHOLD; /**< SIM Transmit Threshold Register, offset: 0x44 */ + __IO uint32_t GUARD_CNTL; /**< SIM Transmit Guard Control Register, offset: 0x48 */ + __IO uint32_t OD_CONFIG; /**< SIM Open Drain Configuration Control Register, offset: 0x4C */ + __IO uint32_t RESET_CNTL; /**< SIM Reset Control Register, offset: 0x50 */ + __IO uint32_t CHAR_WAIT; /**< SIM Character Wait Time Register, offset: 0x54 */ + __IO uint32_t GPCNT; /**< SIM General Purpose Counter Register, offset: 0x58 */ + __IO uint32_t DIVISOR; /**< SIM Divisor Register, offset: 0x5C */ + __IO uint32_t BWT; /**< SIM Block Wait Time Register, offset: 0x60 */ + __IO uint32_t BGT; /**< SIM Block Guard Time Register, offset: 0x64 */ + __IO uint32_t BWT_H; /**< SIM Block Wait Time Register HIGH, offset: 0x68 */ + __I uint32_t XMT_FIFO_STAT; /**< SIM Transmit FIFO Status Register, offset: 0x6C */ + __I uint32_t RCV_FIFO_CNT; /**< SIM Receive FIFO Counter Register, offset: 0x70 */ + __I uint32_t RCV_FIFO_WPTR; /**< SIM Receive FIFO Write Pointer Register, offset: 0x74 */ + __I uint32_t RCV_FIFO_RPTR; /**< SIM Receive FIFO Read Pointer Register, offset: 0x78 */ +} SIM_Type, *SIM_MemMapPtr; +/* ---------------------------------------------------------------------------- + -- SIM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros + * @{ + */ + + +/* SIM - Register accessors */ +#define SIM_PORT1_CNTL_REG(base) ((base)->PORT1_CNTL) +#define SIM_SETUP_REG(base) ((base)->SETUP) +#define SIM_PORT1_DETECT_REG(base) ((base)->PORT1_DETECT) +#define SIM_XMT_BUF_REG(base) ((base)->XMT_BUF) +#define SIM_RCV_BUF_REG(base) ((base)->RCV_BUF) +#define SIM_PORT0_CNTL_REG(base) ((base)->PORT0_CNTL) +#define SIM_CNTL_REG(base) ((base)->CNTL) +#define SIM_CLK_PRESCALER_REG(base) ((base)->CLK_PRESCALER) +#define SIM_RCV_THRESHOLD_REG(base) ((base)->RCV_THRESHOLD) +#define SIM_ENABLE_REG(base) ((base)->ENABLE) +#define SIM_XMT_STATUS_REG(base) ((base)->XMT_STATUS) +#define SIM_RCV_STATUS_REG(base) ((base)->RCV_STATUS) +#define SIM_INT_MASK_REG(base) ((base)->INT_MASK) +#define SIM_PORT0_DETECT_REG(base) ((base)->PORT0_DETECT) +#define SIM_DATA_FORMAT_REG(base) ((base)->DATA_FORMAT) +#define SIM_XMT_THRESHOLD_REG(base) ((base)->XMT_THRESHOLD) +#define SIM_GUARD_CNTL_REG(base) ((base)->GUARD_CNTL) +#define SIM_OD_CONFIG_REG(base) ((base)->OD_CONFIG) +#define SIM_RESET_CNTL_REG(base) ((base)->RESET_CNTL) +#define SIM_CHAR_WAIT_REG(base) ((base)->CHAR_WAIT) +#define SIM_GPCNT_REG(base) ((base)->GPCNT) +#define SIM_DIVISOR_REG(base) ((base)->DIVISOR) +#define SIM_BWT_REG(base) ((base)->BWT) +#define SIM_BGT_REG(base) ((base)->BGT) +#define SIM_BWT_H_REG(base) ((base)->BWT_H) +#define SIM_XMT_FIFO_STAT_REG(base) ((base)->XMT_FIFO_STAT) +#define SIM_RCV_FIFO_CNT_REG(base) ((base)->RCV_FIFO_CNT) +#define SIM_RCV_FIFO_WPTR_REG(base) ((base)->RCV_FIFO_WPTR) +#define SIM_RCV_FIFO_RPTR_REG(base) ((base)->RCV_FIFO_RPTR) + +/*! + * @} + */ /* end of group SIM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/* PORT1_CNTL Bit Fields */ +#define SIM_PORT1_CNTL_SAPD1_MASK 0x1u +#define SIM_PORT1_CNTL_SAPD1_SHIFT 0 +#define SIM_PORT1_CNTL_SVEN1_MASK 0x2u +#define SIM_PORT1_CNTL_SVEN1_SHIFT 1 +#define SIM_PORT1_CNTL_STEN1_MASK 0x4u +#define SIM_PORT1_CNTL_STEN1_SHIFT 2 +#define SIM_PORT1_CNTL_SRST1_MASK 0x8u +#define SIM_PORT1_CNTL_SRST1_SHIFT 3 +#define SIM_PORT1_CNTL_SCEN1_MASK 0x10u +#define SIM_PORT1_CNTL_SCEN1_SHIFT 4 +#define SIM_PORT1_CNTL_SCSP1_MASK 0x20u +#define SIM_PORT1_CNTL_SCSP1_SHIFT 5 +#define SIM_PORT1_CNTL_VOLT3_1_MASK 0x40u +#define SIM_PORT1_CNTL_VOLT3_1_SHIFT 6 +#define SIM_PORT1_CNTL_SFPD1_MASK 0x80u +#define SIM_PORT1_CNTL_SFPD1_SHIFT 7 +/* SETUP Bit Fields */ +#define SIM_SETUP_AMODE_MASK 0x1u +#define SIM_SETUP_AMODE_SHIFT 0 +#define SIM_SETUP_SPS_MASK 0x2u +#define SIM_SETUP_SPS_SHIFT 1 +/* PORT1_DETECT Bit Fields */ +#define SIM_PORT1_DETECT_SDIM1_MASK 0x1u +#define SIM_PORT1_DETECT_SDIM1_SHIFT 0 +#define SIM_PORT1_DETECT_SDI1_MASK 0x2u +#define SIM_PORT1_DETECT_SDI1_SHIFT 1 +#define SIM_PORT1_DETECT_SPDP1_MASK 0x4u +#define SIM_PORT1_DETECT_SPDP1_SHIFT 2 +#define SIM_PORT1_DETECT_SPDS1_MASK 0x8u +#define SIM_PORT1_DETECT_SPDS1_SHIFT 3 +/* XMT_BUF Bit Fields */ +#define SIM_XMT_BUF_XMT_MASK 0xFFu +#define SIM_XMT_BUF_XMT_SHIFT 0 +#define SIM_XMT_BUF_XMT(x) (((uint32_t)(((uint32_t)(x))<<SIM_XMT_BUF_XMT_SHIFT))&SIM_XMT_BUF_XMT_MASK) +/* RCV_BUF Bit Fields */ +#define SIM_RCV_BUF_RCV_MASK 0xFFu +#define SIM_RCV_BUF_RCV_SHIFT 0 +#define SIM_RCV_BUF_RCV(x) (((uint32_t)(((uint32_t)(x))<<SIM_RCV_BUF_RCV_SHIFT))&SIM_RCV_BUF_RCV_MASK) +#define SIM_RCV_BUF_PE_MASK 0x100u +#define SIM_RCV_BUF_PE_SHIFT 8 +#define SIM_RCV_BUF_FE_MASK 0x200u +#define SIM_RCV_BUF_FE_SHIFT 9 +#define SIM_RCV_BUF_CWT_MASK 0x400u +#define SIM_RCV_BUF_CWT_SHIFT 10 +/* PORT0_CNTL Bit Fields */ +#define SIM_PORT0_CNTL_SAPD0_MASK 0x1u +#define SIM_PORT0_CNTL_SAPD0_SHIFT 0 +#define SIM_PORT0_CNTL_SVEN0_MASK 0x2u +#define SIM_PORT0_CNTL_SVEN0_SHIFT 1 +#define SIM_PORT0_CNTL_STEN0_MASK 0x4u +#define SIM_PORT0_CNTL_STEN0_SHIFT 2 +#define SIM_PORT0_CNTL_SRST0_MASK 0x8u +#define SIM_PORT0_CNTL_SRST0_SHIFT 3 +#define SIM_PORT0_CNTL_SCEN0_MASK 0x10u +#define SIM_PORT0_CNTL_SCEN0_SHIFT 4 +#define SIM_PORT0_CNTL_SCSP0_MASK 0x20u +#define SIM_PORT0_CNTL_SCSP0_SHIFT 5 +#define SIM_PORT0_CNTL_VOLT3_0_MASK 0x40u +#define SIM_PORT0_CNTL_VOLT3_0_SHIFT 6 +#define SIM_PORT0_CNTL_SFPD0_MASK 0x80u +#define SIM_PORT0_CNTL_SFPD0_SHIFT 7 +/* CNTL Bit Fields */ +#define SIM_CNTL_ICM_MASK 0x2u +#define SIM_CNTL_ICM_SHIFT 1 +#define SIM_CNTL_ANACK_MASK 0x4u +#define SIM_CNTL_ANACK_SHIFT 2 +#define SIM_CNTL_ONACK_MASK 0x8u +#define SIM_CNTL_ONACK_SHIFT 3 +#define SIM_CNTL_Sample12_MASK 0x20u +#define SIM_CNTL_Sample12_SHIFT 5 +#define SIM_CNTL_baud_sel_MASK 0x1C0u +#define SIM_CNTL_baud_sel_SHIFT 6 +#define SIM_CNTL_baud_sel(x) (((uint32_t)(((uint32_t)(x))<<SIM_CNTL_baud_sel_SHIFT))&SIM_CNTL_baud_sel_MASK) +#define SIM_CNTL_gpcnt_clk_sel_MASK 0x600u +#define SIM_CNTL_gpcnt_clk_sel_SHIFT 9 +#define SIM_CNTL_gpcnt_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<SIM_CNTL_gpcnt_clk_sel_SHIFT))&SIM_CNTL_gpcnt_clk_sel_MASK) +#define SIM_CNTL_CWTEN_MASK 0x800u +#define SIM_CNTL_CWTEN_SHIFT 11 +#define SIM_CNTL_LRCEN_MASK 0x1000u +#define SIM_CNTL_LRCEN_SHIFT 12 +#define SIM_CNTL_CRCEN_MASK 0x2000u +#define SIM_CNTL_CRCEN_SHIFT 13 +#define SIM_CNTL_xmt_crc_lrc_MASK 0x4000u +#define SIM_CNTL_xmt_crc_lrc_SHIFT 14 +#define SIM_CNTL_BWTEN_MASK 0x8000u +#define SIM_CNTL_BWTEN_SHIFT 15 +/* CLK_PRESCALER Bit Fields */ +#define SIM_CLK_PRESCALER_CLK_PRESCALER_MASK 0xFFu +#define SIM_CLK_PRESCALER_CLK_PRESCALER_SHIFT 0 +#define SIM_CLK_PRESCALER_CLK_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLK_PRESCALER_CLK_PRESCALER_SHIFT))&SIM_CLK_PRESCALER_CLK_PRESCALER_MASK) +/* RCV_THRESHOLD Bit Fields */ +#define SIM_RCV_THRESHOLD_RDT_MASK 0x1FFu +#define SIM_RCV_THRESHOLD_RDT_SHIFT 0 +#define SIM_RCV_THRESHOLD_RDT(x) (((uint32_t)(((uint32_t)(x))<<SIM_RCV_THRESHOLD_RDT_SHIFT))&SIM_RCV_THRESHOLD_RDT_MASK) +#define SIM_RCV_THRESHOLD_RTH_MASK 0x1E00u +#define SIM_RCV_THRESHOLD_RTH_SHIFT 9 +#define SIM_RCV_THRESHOLD_RTH(x) (((uint32_t)(((uint32_t)(x))<<SIM_RCV_THRESHOLD_RTH_SHIFT))&SIM_RCV_THRESHOLD_RTH_MASK) +/* ENABLE Bit Fields */ +#define SIM_ENABLE_RCV_EN_MASK 0x1u +#define SIM_ENABLE_RCV_EN_SHIFT 0 +#define SIM_ENABLE_XMT_EN_MASK 0x2u +#define SIM_ENABLE_XMT_EN_SHIFT 1 +#define SIM_ENABLE_RXDMA_EN_MASK 0x4u +#define SIM_ENABLE_RXDMA_EN_SHIFT 2 +#define SIM_ENABLE_TXDMA_EN_MASK 0x8u +#define SIM_ENABLE_TXDMA_EN_SHIFT 3 +#define SIM_ENABLE_NACK_DD_EN_MASK 0x10u +#define SIM_ENABLE_NACK_DD_EN_SHIFT 4 +#define SIM_ENABLE_ESTOP_EN_MASK 0x20u +#define SIM_ENABLE_ESTOP_EN_SHIFT 5 +#define SIM_ENABLE_ESTOP_EXE_MASK 0x40u +#define SIM_ENABLE_ESTOP_EXE_SHIFT 6 +#define SIM_ENABLE_RXCL_MASK 0x80u +#define SIM_ENABLE_RXCL_SHIFT 7 +/* XMT_STATUS Bit Fields */ +#define SIM_XMT_STATUS_XTE_MASK 0x1u +#define SIM_XMT_STATUS_XTE_SHIFT 0 +#define SIM_XMT_STATUS_TFE_MASK 0x8u +#define SIM_XMT_STATUS_TFE_SHIFT 3 +#define SIM_XMT_STATUS_ETC_MASK 0x10u +#define SIM_XMT_STATUS_ETC_SHIFT 4 +#define SIM_XMT_STATUS_TC_MASK 0x20u +#define SIM_XMT_STATUS_TC_SHIFT 5 +#define SIM_XMT_STATUS_TFO_MASK 0x40u +#define SIM_XMT_STATUS_TFO_SHIFT 6 +#define SIM_XMT_STATUS_TDTF_MASK 0x80u +#define SIM_XMT_STATUS_TDTF_SHIFT 7 +#define SIM_XMT_STATUS_GPCNT_MASK 0x100u +#define SIM_XMT_STATUS_GPCNT_SHIFT 8 +/* RCV_STATUS Bit Fields */ +#define SIM_RCV_STATUS_OEF_MASK 0x1u +#define SIM_RCV_STATUS_OEF_SHIFT 0 +#define SIM_RCV_STATUS_RFE_MASK 0x2u +#define SIM_RCV_STATUS_RFE_SHIFT 1 +#define SIM_RCV_STATUS_RFD_MASK 0x10u +#define SIM_RCV_STATUS_RFD_SHIFT 4 +#define SIM_RCV_STATUS_RDRF_MASK 0x20u +#define SIM_RCV_STATUS_RDRF_SHIFT 5 +#define SIM_RCV_STATUS_LRCOK_MASK 0x40u +#define SIM_RCV_STATUS_LRCOK_SHIFT 6 +#define SIM_RCV_STATUS_CRCOK_MASK 0x80u +#define SIM_RCV_STATUS_CRCOK_SHIFT 7 +#define SIM_RCV_STATUS_CWT_MASK 0x100u +#define SIM_RCV_STATUS_CWT_SHIFT 8 +#define SIM_RCV_STATUS_RTE_MASK 0x200u +#define SIM_RCV_STATUS_RTE_SHIFT 9 +#define SIM_RCV_STATUS_BWT_MASK 0x400u +#define SIM_RCV_STATUS_BWT_SHIFT 10 +#define SIM_RCV_STATUS_BGT_MASK 0x800u +#define SIM_RCV_STATUS_BGT_SHIFT 11 +/* INT_MASK Bit Fields */ +#define SIM_INT_MASK_RIM_MASK 0x1u +#define SIM_INT_MASK_RIM_SHIFT 0 +#define SIM_INT_MASK_TCIM_MASK 0x2u +#define SIM_INT_MASK_TCIM_SHIFT 1 +#define SIM_INT_MASK_OIM_MASK 0x4u +#define SIM_INT_MASK_OIM_SHIFT 2 +#define SIM_INT_MASK_ETCIM_MASK 0x8u +#define SIM_INT_MASK_ETCIM_SHIFT 3 +#define SIM_INT_MASK_TFEIM_MASK 0x10u +#define SIM_INT_MASK_TFEIM_SHIFT 4 +#define SIM_INT_MASK_XTM_MASK 0x20u +#define SIM_INT_MASK_XTM_SHIFT 5 +#define SIM_INT_MASK_TFOM_MASK 0x40u +#define SIM_INT_MASK_TFOM_SHIFT 6 +#define SIM_INT_MASK_TDTFM_MASK 0x80u +#define SIM_INT_MASK_TDTFM_SHIFT 7 +#define SIM_INT_MASK_GPCNTM_MASK 0x100u +#define SIM_INT_MASK_GPCNTM_SHIFT 8 +#define SIM_INT_MASK_CWTM_MASK 0x200u +#define SIM_INT_MASK_CWTM_SHIFT 9 +#define SIM_INT_MASK_RTM_MASK 0x400u +#define SIM_INT_MASK_RTM_SHIFT 10 +#define SIM_INT_MASK_BWTM_MASK 0x800u +#define SIM_INT_MASK_BWTM_SHIFT 11 +#define SIM_INT_MASK_BGTM_MASK 0x1000u +#define SIM_INT_MASK_BGTM_SHIFT 12 +#define SIM_INT_MASK_RFEM_MASK 0x2000u +#define SIM_INT_MASK_RFEM_SHIFT 13 +/* PORT0_DETECT Bit Fields */ +#define SIM_PORT0_DETECT_SDIM0_MASK 0x1u +#define SIM_PORT0_DETECT_SDIM0_SHIFT 0 +#define SIM_PORT0_DETECT_SDI0_MASK 0x2u +#define SIM_PORT0_DETECT_SDI0_SHIFT 1 +#define SIM_PORT0_DETECT_SPDP0_MASK 0x4u +#define SIM_PORT0_DETECT_SPDP0_SHIFT 2 +#define SIM_PORT0_DETECT_SPDS0_MASK 0x8u +#define SIM_PORT0_DETECT_SPDS0_SHIFT 3 +/* DATA_FORMAT Bit Fields */ +#define SIM_DATA_FORMAT_IC_MASK 0x1u +#define SIM_DATA_FORMAT_IC_SHIFT 0 +/* XMT_THRESHOLD Bit Fields */ +#define SIM_XMT_THRESHOLD_TDT_MASK 0xFu +#define SIM_XMT_THRESHOLD_TDT_SHIFT 0 +#define SIM_XMT_THRESHOLD_TDT(x) (((uint32_t)(((uint32_t)(x))<<SIM_XMT_THRESHOLD_TDT_SHIFT))&SIM_XMT_THRESHOLD_TDT_MASK) +#define SIM_XMT_THRESHOLD_XTH_MASK 0xF0u +#define SIM_XMT_THRESHOLD_XTH_SHIFT 4 +#define SIM_XMT_THRESHOLD_XTH(x) (((uint32_t)(((uint32_t)(x))<<SIM_XMT_THRESHOLD_XTH_SHIFT))&SIM_XMT_THRESHOLD_XTH_MASK) +/* GUARD_CNTL Bit Fields */ +#define SIM_GUARD_CNTL_GETU_MASK 0xFFu +#define SIM_GUARD_CNTL_GETU_SHIFT 0 +#define SIM_GUARD_CNTL_GETU(x) (((uint32_t)(((uint32_t)(x))<<SIM_GUARD_CNTL_GETU_SHIFT))&SIM_GUARD_CNTL_GETU_MASK) +#define SIM_GUARD_CNTL_RCVR11_MASK 0x100u +#define SIM_GUARD_CNTL_RCVR11_SHIFT 8 +/* OD_CONFIG Bit Fields */ +#define SIM_OD_CONFIG_OD_P0_MASK 0x1u +#define SIM_OD_CONFIG_OD_P0_SHIFT 0 +#define SIM_OD_CONFIG_OD_P1_MASK 0x2u +#define SIM_OD_CONFIG_OD_P1_SHIFT 1 +/* RESET_CNTL Bit Fields */ +#define SIM_RESET_CNTL_FLUSH_RCV_MASK 0x1u +#define SIM_RESET_CNTL_FLUSH_RCV_SHIFT 0 +#define SIM_RESET_CNTL_FLUSH_XMT_MASK 0x2u +#define SIM_RESET_CNTL_FLUSH_XMT_SHIFT 1 +#define SIM_RESET_CNTL_SOFT_RST_MASK 0x4u +#define SIM_RESET_CNTL_SOFT_RST_SHIFT 2 +#define SIM_RESET_CNTL_KILL_CLOCK_MASK 0x8u +#define SIM_RESET_CNTL_KILL_CLOCK_SHIFT 3 +#define SIM_RESET_CNTL_DOZE_MASK 0x10u +#define SIM_RESET_CNTL_DOZE_SHIFT 4 +#define SIM_RESET_CNTL_STOP_MASK 0x20u +#define SIM_RESET_CNTL_STOP_SHIFT 5 +/* CHAR_WAIT Bit Fields */ +#define SIM_CHAR_WAIT_CWT_MASK 0xFFFFu +#define SIM_CHAR_WAIT_CWT_SHIFT 0 +#define SIM_CHAR_WAIT_CWT(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHAR_WAIT_CWT_SHIFT))&SIM_CHAR_WAIT_CWT_MASK) +/* GPCNT Bit Fields */ +#define SIM_GPCNT_GPCNT_MASK 0xFFFFu +#define SIM_GPCNT_GPCNT_SHIFT 0 +#define SIM_GPCNT_GPCNT(x) (((uint32_t)(((uint32_t)(x))<<SIM_GPCNT_GPCNT_SHIFT))&SIM_GPCNT_GPCNT_MASK) +/* DIVISOR Bit Fields */ +#define SIM_DIVISOR_DIVISOR_MASK 0xFFu +#define SIM_DIVISOR_DIVISOR_SHIFT 0 +#define SIM_DIVISOR_DIVISOR(x) (((uint32_t)(((uint32_t)(x))<<SIM_DIVISOR_DIVISOR_SHIFT))&SIM_DIVISOR_DIVISOR_MASK) +/* BWT Bit Fields */ +#define SIM_BWT_BWT_MASK 0xFFFFu +#define SIM_BWT_BWT_SHIFT 0 +#define SIM_BWT_BWT(x) (((uint32_t)(((uint32_t)(x))<<SIM_BWT_BWT_SHIFT))&SIM_BWT_BWT_MASK) +/* BGT Bit Fields */ +#define SIM_BGT_BGT_MASK 0xFFFFu +#define SIM_BGT_BGT_SHIFT 0 +#define SIM_BGT_BGT(x) (((uint32_t)(((uint32_t)(x))<<SIM_BGT_BGT_SHIFT))&SIM_BGT_BGT_MASK) +/* BWT_H Bit Fields */ +#define SIM_BWT_H_BWT_H_MASK 0xFFFFu +#define SIM_BWT_H_BWT_H_SHIFT 0 +#define SIM_BWT_H_BWT_H(x) (((uint32_t)(((uint32_t)(x))<<SIM_BWT_H_BWT_H_SHIFT))&SIM_BWT_H_BWT_H_MASK) +/* XMT_FIFO_STAT Bit Fields */ +#define SIM_XMT_FIFO_STAT_XMT_RPTR_MASK 0xFu +#define SIM_XMT_FIFO_STAT_XMT_RPTR_SHIFT 0 +#define SIM_XMT_FIFO_STAT_XMT_RPTR(x) (((uint32_t)(((uint32_t)(x))<<SIM_XMT_FIFO_STAT_XMT_RPTR_SHIFT))&SIM_XMT_FIFO_STAT_XMT_RPTR_MASK) +#define SIM_XMT_FIFO_STAT_XMT_WPTR_MASK 0xF0u +#define SIM_XMT_FIFO_STAT_XMT_WPTR_SHIFT 4 +#define SIM_XMT_FIFO_STAT_XMT_WPTR(x) (((uint32_t)(((uint32_t)(x))<<SIM_XMT_FIFO_STAT_XMT_WPTR_SHIFT))&SIM_XMT_FIFO_STAT_XMT_WPTR_MASK) +#define SIM_XMT_FIFO_STAT_XMT_CNT_MASK 0xF00u +#define SIM_XMT_FIFO_STAT_XMT_CNT_SHIFT 8 +#define SIM_XMT_FIFO_STAT_XMT_CNT(x) (((uint32_t)(((uint32_t)(x))<<SIM_XMT_FIFO_STAT_XMT_CNT_SHIFT))&SIM_XMT_FIFO_STAT_XMT_CNT_MASK) +/* RCV_FIFO_CNT Bit Fields */ +#define SIM_RCV_FIFO_CNT_RCV_CNT_MASK 0x1FFu +#define SIM_RCV_FIFO_CNT_RCV_CNT_SHIFT 0 +#define SIM_RCV_FIFO_CNT_RCV_CNT(x) (((uint32_t)(((uint32_t)(x))<<SIM_RCV_FIFO_CNT_RCV_CNT_SHIFT))&SIM_RCV_FIFO_CNT_RCV_CNT_MASK) +/* RCV_FIFO_WPTR Bit Fields */ +#define SIM_RCV_FIFO_WPTR_RCV_WPTR_MASK 0x1FFu +#define SIM_RCV_FIFO_WPTR_RCV_WPTR_SHIFT 0 +#define SIM_RCV_FIFO_WPTR_RCV_WPTR(x) (((uint32_t)(((uint32_t)(x))<<SIM_RCV_FIFO_WPTR_RCV_WPTR_SHIFT))&SIM_RCV_FIFO_WPTR_RCV_WPTR_MASK) +/* RCV_FIFO_RPTR Bit Fields */ +#define SIM_RCV_FIFO_RPTR_RCV_RPTR_MASK 0x1FFu +#define SIM_RCV_FIFO_RPTR_RCV_RPTR_SHIFT 0 +#define SIM_RCV_FIFO_RPTR_RCV_RPTR(x) (((uint32_t)(((uint32_t)(x))<<SIM_RCV_FIFO_RPTR_RCV_RPTR_SHIFT))&SIM_RCV_FIFO_RPTR_RCV_RPTR_MASK) + +/*! + * @} + */ /* end of group SIM_Register_Masks */ + +/* SIM - Peripheral instance base addresses */ +/** Peripheral SIM1 base address */ +#define SIM1_BASE (0x30B90000u) +/** Peripheral SIM1 base pointer */ +#define SIM1 ((SIM_Type *)SIM1_BASE) +#define SIM1_BASE_PTR (SIM1) +/** Peripheral SIM2 base address */ +#define SIM2_BASE (0x30BA0000u) +/** Peripheral SIM2 base pointer */ +#define SIM2 ((SIM_Type *)SIM2_BASE) +#define SIM2_BASE_PTR (SIM2) +/** Array initializer of SIM peripheral base addresses */ +#define SIM_BASE_ADDRS { SIM1_BASE, SIM2_BASE } +/** Array initializer of SIM peripheral base pointers */ +#define SIM_BASE_PTRS { SIM1, SIM2 } +/** Interrupt vectors for the SIM peripheral type */ +#define SCTR_IRQS { SCTR1_IRQn, SCTR2_IRQn } +#define SIM_IRQS { SIM1_IRQn, SIM2_IRQn } +/* ---------------------------------------------------------------------------- + -- SIM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros + * @{ + */ + + +/* SIM - Register instance definitions */ +/* SIM1 */ +#define SIM1_PORT1_CNTL SIM_PORT1_CNTL_REG(SIM1_BASE_PTR) +#define SIM1_SETUP SIM_SETUP_REG(SIM1_BASE_PTR) +#define SIM1_PORT1_DETECT SIM_PORT1_DETECT_REG(SIM1_BASE_PTR) +#define SIM1_XMT_BUF SIM_XMT_BUF_REG(SIM1_BASE_PTR) +#define SIM1_RCV_BUF SIM_RCV_BUF_REG(SIM1_BASE_PTR) +#define SIM1_PORT0_CNTL SIM_PORT0_CNTL_REG(SIM1_BASE_PTR) +#define SIM1_CNTL SIM_CNTL_REG(SIM1_BASE_PTR) +#define SIM1_CLK_PRESCALER SIM_CLK_PRESCALER_REG(SIM1_BASE_PTR) +#define SIM1_RCV_THRESHOLD SIM_RCV_THRESHOLD_REG(SIM1_BASE_PTR) +#define SIM1_ENABLE SIM_ENABLE_REG(SIM1_BASE_PTR) +#define SIM1_XMT_STATUS SIM_XMT_STATUS_REG(SIM1_BASE_PTR) +#define SIM1_RCV_STATUS SIM_RCV_STATUS_REG(SIM1_BASE_PTR) +#define SIM1_INT_MASK SIM_INT_MASK_REG(SIM1_BASE_PTR) +#define SIM1_PORT0_DETECT SIM_PORT0_DETECT_REG(SIM1_BASE_PTR) +#define SIM1_DATA_FORMAT SIM_DATA_FORMAT_REG(SIM1_BASE_PTR) +#define SIM1_XMT_THRESHOLD SIM_XMT_THRESHOLD_REG(SIM1_BASE_PTR) +#define SIM1_GUARD_CNTL SIM_GUARD_CNTL_REG(SIM1_BASE_PTR) +#define SIM1_OD_CONFIG SIM_OD_CONFIG_REG(SIM1_BASE_PTR) +#define SIM1_RESET_CNTL SIM_RESET_CNTL_REG(SIM1_BASE_PTR) +#define SIM1_CHAR_WAIT SIM_CHAR_WAIT_REG(SIM1_BASE_PTR) +#define SIM1_GPCNT SIM_GPCNT_REG(SIM1_BASE_PTR) +#define SIM1_DIVISOR SIM_DIVISOR_REG(SIM1_BASE_PTR) +#define SIM1_BWT SIM_BWT_REG(SIM1_BASE_PTR) +#define SIM1_BGT SIM_BGT_REG(SIM1_BASE_PTR) +#define SIM1_BWT_H SIM_BWT_H_REG(SIM1_BASE_PTR) +#define SIM1_XMT_FIFO_STAT SIM_XMT_FIFO_STAT_REG(SIM1_BASE_PTR) +#define SIM1_RCV_FIFO_CNT SIM_RCV_FIFO_CNT_REG(SIM1_BASE_PTR) +#define SIM1_RCV_FIFO_WPTR SIM_RCV_FIFO_WPTR_REG(SIM1_BASE_PTR) +#define SIM1_RCV_FIFO_RPTR SIM_RCV_FIFO_RPTR_REG(SIM1_BASE_PTR) +/* SIM2 */ +#define SIM2_PORT1_CNTL SIM_PORT1_CNTL_REG(SIM2_BASE_PTR) +#define SIM2_SETUP SIM_SETUP_REG(SIM2_BASE_PTR) +#define SIM2_PORT1_DETECT SIM_PORT1_DETECT_REG(SIM2_BASE_PTR) +#define SIM2_XMT_BUF SIM_XMT_BUF_REG(SIM2_BASE_PTR) +#define SIM2_RCV_BUF SIM_RCV_BUF_REG(SIM2_BASE_PTR) +#define SIM2_PORT0_CNTL SIM_PORT0_CNTL_REG(SIM2_BASE_PTR) +#define SIM2_CNTL SIM_CNTL_REG(SIM2_BASE_PTR) +#define SIM2_CLK_PRESCALER SIM_CLK_PRESCALER_REG(SIM2_BASE_PTR) +#define SIM2_RCV_THRESHOLD SIM_RCV_THRESHOLD_REG(SIM2_BASE_PTR) +#define SIM2_ENABLE SIM_ENABLE_REG(SIM2_BASE_PTR) +#define SIM2_XMT_STATUS SIM_XMT_STATUS_REG(SIM2_BASE_PTR) +#define SIM2_RCV_STATUS SIM_RCV_STATUS_REG(SIM2_BASE_PTR) +#define SIM2_INT_MASK SIM_INT_MASK_REG(SIM2_BASE_PTR) +#define SIM2_PORT0_DETECT SIM_PORT0_DETECT_REG(SIM2_BASE_PTR) +#define SIM2_DATA_FORMAT SIM_DATA_FORMAT_REG(SIM2_BASE_PTR) +#define SIM2_XMT_THRESHOLD SIM_XMT_THRESHOLD_REG(SIM2_BASE_PTR) +#define SIM2_GUARD_CNTL SIM_GUARD_CNTL_REG(SIM2_BASE_PTR) +#define SIM2_OD_CONFIG SIM_OD_CONFIG_REG(SIM2_BASE_PTR) +#define SIM2_RESET_CNTL SIM_RESET_CNTL_REG(SIM2_BASE_PTR) +#define SIM2_CHAR_WAIT SIM_CHAR_WAIT_REG(SIM2_BASE_PTR) +#define SIM2_GPCNT SIM_GPCNT_REG(SIM2_BASE_PTR) +#define SIM2_DIVISOR SIM_DIVISOR_REG(SIM2_BASE_PTR) +#define SIM2_BWT SIM_BWT_REG(SIM2_BASE_PTR) +#define SIM2_BGT SIM_BGT_REG(SIM2_BASE_PTR) +#define SIM2_BWT_H SIM_BWT_H_REG(SIM2_BASE_PTR) +#define SIM2_XMT_FIFO_STAT SIM_XMT_FIFO_STAT_REG(SIM2_BASE_PTR) +#define SIM2_RCV_FIFO_CNT SIM_RCV_FIFO_CNT_REG(SIM2_BASE_PTR) +#define SIM2_RCV_FIFO_WPTR SIM_RCV_FIFO_WPTR_REG(SIM2_BASE_PTR) +#define SIM2_RCV_FIFO_RPTR SIM_RCV_FIFO_RPTR_REG(SIM2_BASE_PTR) +/*! + * @} + */ /* end of group SIM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SIM_Peripheral */ /* ---------------------------------------------------------------------------- -- FTM Peripheral Access Layer @@ -69214,7 +17718,7 @@ typedef struct { struct { /* offset: 0xC, array step: 0x8 */ __IO uint32_t CSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ __IO uint32_t CV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ - } C[8]; + } C[8]; __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ @@ -69225,18 +17729,17 @@ typedef struct { __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ - __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ + uint8_t RESERVED_0[4]; __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ - __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ + uint8_t RESERVED_1[4]; __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ - __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ + uint8_t RESERVED_2[4]; __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ } FTM_Type, *FTM_MemMapPtr; - /* ---------------------------------------------------------------------------- -- FTM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -69263,12 +17766,9 @@ typedef struct { #define FTM_DEADTIME_REG(base) ((base)->DEADTIME) #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) #define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) #define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) #define FTM_QDCTRL_REG(base) ((base)->QDCTRL) #define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) #define FTM_SYNCONF_REG(base) ((base)->SYNCONF) #define FTM_INVCTRL_REG(base) ((base)->INVCTRL) #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) @@ -69277,8 +17777,6 @@ typedef struct { /*! * @} */ /* end of group FTM_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- FTM Register Masks ---------------------------------------------------------------------------- */ @@ -69312,6 +17810,8 @@ typedef struct { /* CSC Bit Fields */ #define FTM_CSC_DMA_MASK 0x1u #define FTM_CSC_DMA_SHIFT 0 +#define FTM_CSC_ICRST_MASK 0x2u +#define FTM_CSC_ICRST_SHIFT 1 #define FTM_CSC_ELSA_MASK 0x4u #define FTM_CSC_ELSA_SHIFT 2 #define FTM_CSC_ELSB_MASK 0x8u @@ -69360,11 +17860,6 @@ typedef struct { #define FTM_MODE_PWMSYNC_SHIFT 3 #define FTM_MODE_CAPTEST_MASK 0x10u #define FTM_MODE_CAPTEST_SHIFT 4 -#define FTM_MODE_FAULTM_MASK 0x60u -#define FTM_MODE_FAULTM_SHIFT 5 -#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) -#define FTM_MODE_FAULTIE_MASK 0x80u -#define FTM_MODE_FAULTIE_SHIFT 7 /* SYNC Bit Fields */ #define FTM_SYNC_CNTMIN_MASK 0x1u #define FTM_SYNC_CNTMIN_SHIFT 0 @@ -69429,8 +17924,6 @@ typedef struct { #define FTM_COMBINE_DTEN0_SHIFT 4 #define FTM_COMBINE_SYNCEN0_MASK 0x20u #define FTM_COMBINE_SYNCEN0_SHIFT 5 -#define FTM_COMBINE_FAULTEN0_MASK 0x40u -#define FTM_COMBINE_FAULTEN0_SHIFT 6 #define FTM_COMBINE_COMBINE1_MASK 0x100u #define FTM_COMBINE_COMBINE1_SHIFT 8 #define FTM_COMBINE_COMP1_MASK 0x200u @@ -69443,8 +17936,6 @@ typedef struct { #define FTM_COMBINE_DTEN1_SHIFT 12 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u #define FTM_COMBINE_SYNCEN1_SHIFT 13 -#define FTM_COMBINE_FAULTEN1_MASK 0x4000u -#define FTM_COMBINE_FAULTEN1_SHIFT 14 #define FTM_COMBINE_COMBINE2_MASK 0x10000u #define FTM_COMBINE_COMBINE2_SHIFT 16 #define FTM_COMBINE_COMP2_MASK 0x20000u @@ -69457,8 +17948,6 @@ typedef struct { #define FTM_COMBINE_DTEN2_SHIFT 20 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u #define FTM_COMBINE_SYNCEN2_SHIFT 21 -#define FTM_COMBINE_FAULTEN2_MASK 0x400000u -#define FTM_COMBINE_FAULTEN2_SHIFT 22 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u #define FTM_COMBINE_COMBINE3_SHIFT 24 #define FTM_COMBINE_COMP3_MASK 0x2000000u @@ -69471,8 +17960,6 @@ typedef struct { #define FTM_COMBINE_DTEN3_SHIFT 28 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u #define FTM_COMBINE_SYNCEN3_SHIFT 29 -#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u -#define FTM_COMBINE_FAULTEN3_SHIFT 30 /* DEADTIME Bit Fields */ #define FTM_DEADTIME_DTVAL_MASK 0x3Fu #define FTM_DEADTIME_DTVAL_SHIFT 0 @@ -69514,21 +18001,6 @@ typedef struct { #define FTM_POL_POL6_SHIFT 6 #define FTM_POL_POL7_MASK 0x80u #define FTM_POL_POL7_SHIFT 7 -/* FMS Bit Fields */ -#define FTM_FMS_FAULTF0_MASK 0x1u -#define FTM_FMS_FAULTF0_SHIFT 0 -#define FTM_FMS_FAULTF1_MASK 0x2u -#define FTM_FMS_FAULTF1_SHIFT 1 -#define FTM_FMS_FAULTF2_MASK 0x4u -#define FTM_FMS_FAULTF2_SHIFT 2 -#define FTM_FMS_FAULTF3_MASK 0x8u -#define FTM_FMS_FAULTF3_SHIFT 3 -#define FTM_FMS_FAULTIN_MASK 0x20u -#define FTM_FMS_FAULTIN_SHIFT 5 -#define FTM_FMS_WPEN_MASK 0x40u -#define FTM_FMS_WPEN_SHIFT 6 -#define FTM_FMS_FAULTF_MASK 0x80u -#define FTM_FMS_FAULTF_SHIFT 7 /* FILTER Bit Fields */ #define FTM_FILTER_CH0FVAL_MASK 0xFu #define FTM_FILTER_CH0FVAL_SHIFT 0 @@ -69542,26 +18014,6 @@ typedef struct { #define FTM_FILTER_CH3FVAL_MASK 0xF000u #define FTM_FILTER_CH3FVAL_SHIFT 12 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) -/* FLTCTRL Bit Fields */ -#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u -#define FTM_FLTCTRL_FAULT0EN_SHIFT 0 -#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u -#define FTM_FLTCTRL_FAULT1EN_SHIFT 1 -#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u -#define FTM_FLTCTRL_FAULT2EN_SHIFT 2 -#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u -#define FTM_FLTCTRL_FAULT3EN_SHIFT 3 -#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u -#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 -#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u -#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 -#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u -#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 -#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u -#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 -#define FTM_FLTCTRL_FFVAL_MASK 0xF00u -#define FTM_FLTCTRL_FFVAL_SHIFT 8 -#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) /* QDCTRL Bit Fields */ #define FTM_QDCTRL_QUADEN_MASK 0x1u #define FTM_QDCTRL_QUADEN_SHIFT 0 @@ -69590,15 +18042,6 @@ typedef struct { #define FTM_CONF_GTBEEN_SHIFT 9 #define FTM_CONF_GTBEOUT_MASK 0x400u #define FTM_CONF_GTBEOUT_SHIFT 10 -/* FLTPOL Bit Fields */ -#define FTM_FLTPOL_FLT0POL_MASK 0x1u -#define FTM_FLTPOL_FLT0POL_SHIFT 0 -#define FTM_FLTPOL_FLT1POL_MASK 0x2u -#define FTM_FLTPOL_FLT1POL_SHIFT 1 -#define FTM_FLTPOL_FLT2POL_MASK 0x4u -#define FTM_FLTPOL_FLT2POL_SHIFT 2 -#define FTM_FLTPOL_FLT3POL_MASK 0x8u -#define FTM_FLTPOL_FLT3POL_SHIFT 3 /* SYNCONF Bit Fields */ #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 @@ -69696,19 +18139,23 @@ typedef struct { * @} */ /* end of group FTM_Register_Masks */ - /* FTM - Peripheral instance base addresses */ -/** Peripheral FTM base address */ -/* TODO: FTM1, FTM2 */ -#define FTM_BASE (0x30640000u) -/** Peripheral FTM base pointer */ -#define FTM ((FTM_Type *)FTM_BASE) -#define FTM_BASE_PTR (FTM) -/** Array initializer of FTM peripheral base adresses */ -#define FTM_BASE_ADDRS { FTM_BASE } +/** Peripheral FTM1 base address */ +#define FTM1_BASE (0x30640000u) +/** Peripheral FTM1 base pointer */ +#define FTM1 ((FTM_Type *)FTM1_BASE) +#define FTM1_BASE_PTR (FTM1) +/** Peripheral FTM2 base address */ +#define FTM2_BASE (0x30650000u) +/** Peripheral FTM2 base pointer */ +#define FTM2 ((FTM_Type *)FTM2_BASE) +#define FTM2_BASE_PTR (FTM2) +/** Array initializer of FTM peripheral base addresses */ +#define FTM_BASE_ADDRS { FTM1_BASE, FTM2_BASE } /** Array initializer of FTM peripheral base pointers */ -#define FTM_BASE_PTRS { FTM } - +#define FTM_BASE_PTRS { FTM1, FTM2 } +/** Interrupt vectors for the FTM peripheral type */ +#define FTM_IRQS { FTM1_IRQn, FTM2_IRQn } /* ---------------------------------------------------------------------------- -- FTM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -69720,51 +18167,85 @@ typedef struct { /* FTM - Register instance definitions */ -/* FTM */ -#define FTM_SC FTM_SC_REG(FTM_BASE_PTR) -#define FTM_CNT FTM_CNT_REG(FTM_BASE_PTR) -#define FTM_MOD FTM_MOD_REG(FTM_BASE_PTR) -#define FTM_C0SC FTM_CSC_REG(FTM_BASE_PTR,0) -#define FTM_C0V FTM_CV_REG(FTM_BASE_PTR,0) -#define FTM_C1SC FTM_CSC_REG(FTM_BASE_PTR,1) -#define FTM_C1V FTM_CV_REG(FTM_BASE_PTR,1) -#define FTM_C2SC FTM_CSC_REG(FTM_BASE_PTR,2) -#define FTM_C2V FTM_CV_REG(FTM_BASE_PTR,2) -#define FTM_C3SC FTM_CSC_REG(FTM_BASE_PTR,3) -#define FTM_C3V FTM_CV_REG(FTM_BASE_PTR,3) -#define FTM_C4SC FTM_CSC_REG(FTM_BASE_PTR,4) -#define FTM_C4V FTM_CV_REG(FTM_BASE_PTR,4) -#define FTM_C5SC FTM_CSC_REG(FTM_BASE_PTR,5) -#define FTM_C5V FTM_CV_REG(FTM_BASE_PTR,5) -#define FTM_C6SC FTM_CSC_REG(FTM_BASE_PTR,6) -#define FTM_C6V FTM_CV_REG(FTM_BASE_PTR,6) -#define FTM_C7SC FTM_CSC_REG(FTM_BASE_PTR,7) -#define FTM_C7V FTM_CV_REG(FTM_BASE_PTR,7) -#define FTM_CNTIN FTM_CNTIN_REG(FTM_BASE_PTR) -#define FTM_STATUS FTM_STATUS_REG(FTM_BASE_PTR) -#define FTM_MODE FTM_MODE_REG(FTM_BASE_PTR) -#define FTM_SYNC FTM_SYNC_REG(FTM_BASE_PTR) -#define FTM_OUTINIT FTM_OUTINIT_REG(FTM_BASE_PTR) -#define FTM_OUTMASK FTM_OUTMASK_REG(FTM_BASE_PTR) -#define FTM_COMBINE FTM_COMBINE_REG(FTM_BASE_PTR) -#define FTM_DEADTIME FTM_DEADTIME_REG(FTM_BASE_PTR) -#define FTM_EXTTRIG FTM_EXTTRIG_REG(FTM_BASE_PTR) -#define FTM_POL FTM_POL_REG(FTM_BASE_PTR) -#define FTM_FMS FTM_FMS_REG(FTM_BASE_PTR) -#define FTM_FILTER FTM_FILTER_REG(FTM_BASE_PTR) -#define FTM_FLTCTRL FTM_FLTCTRL_REG(FTM_BASE_PTR) -#define FTM_QDCTRL FTM_QDCTRL_REG(FTM_BASE_PTR) -#define FTM_CONF FTM_CONF_REG(FTM_BASE_PTR) -#define FTM_FLTPOL FTM_FLTPOL_REG(FTM_BASE_PTR) -#define FTM_SYNCONF FTM_SYNCONF_REG(FTM_BASE_PTR) -#define FTM_INVCTRL FTM_INVCTRL_REG(FTM_BASE_PTR) -#define FTM_SWOCTRL FTM_SWOCTRL_REG(FTM_BASE_PTR) -#define FTM_PWMLOAD FTM_PWMLOAD_REG(FTM_BASE_PTR) - +/* FTM1 */ +#define FTM1_SC FTM_SC_REG(FTM1_BASE_PTR) +#define FTM1_CNT FTM_CNT_REG(FTM1_BASE_PTR) +#define FTM1_MOD FTM_MOD_REG(FTM1_BASE_PTR) +#define FTM1_C0SC FTM_CSC_REG(FTM1_BASE_PTR,0) +#define FTM1_C0V FTM_CV_REG(FTM1_BASE_PTR,0) +#define FTM1_C1SC FTM_CSC_REG(FTM1_BASE_PTR,1) +#define FTM1_C1V FTM_CV_REG(FTM1_BASE_PTR,1) +#define FTM1_C2SC FTM_CSC_REG(FTM1_BASE_PTR,2) +#define FTM1_C2V FTM_CV_REG(FTM1_BASE_PTR,2) +#define FTM1_C3SC FTM_CSC_REG(FTM1_BASE_PTR,3) +#define FTM1_C3V FTM_CV_REG(FTM1_BASE_PTR,3) +#define FTM1_C4SC FTM_CSC_REG(FTM1_BASE_PTR,4) +#define FTM1_C4V FTM_CV_REG(FTM1_BASE_PTR,4) +#define FTM1_C5SC FTM_CSC_REG(FTM1_BASE_PTR,5) +#define FTM1_C5V FTM_CV_REG(FTM1_BASE_PTR,5) +#define FTM1_C6SC FTM_CSC_REG(FTM1_BASE_PTR,6) +#define FTM1_C6V FTM_CV_REG(FTM1_BASE_PTR,6) +#define FTM1_C7SC FTM_CSC_REG(FTM1_BASE_PTR,7) +#define FTM1_C7V FTM_CV_REG(FTM1_BASE_PTR,7) +#define FTM1_CNTIN FTM_CNTIN_REG(FTM1_BASE_PTR) +#define FTM1_STATUS FTM_STATUS_REG(FTM1_BASE_PTR) +#define FTM1_MODE FTM_MODE_REG(FTM1_BASE_PTR) +#define FTM1_SYNC FTM_SYNC_REG(FTM1_BASE_PTR) +#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1_BASE_PTR) +#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1_BASE_PTR) +#define FTM1_COMBINE FTM_COMBINE_REG(FTM1_BASE_PTR) +#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1_BASE_PTR) +#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1_BASE_PTR) +#define FTM1_POL FTM_POL_REG(FTM1_BASE_PTR) +#define FTM1_FILTER FTM_FILTER_REG(FTM1_BASE_PTR) +#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1_BASE_PTR) +#define FTM1_CONF FTM_CONF_REG(FTM1_BASE_PTR) +#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1_BASE_PTR) +#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1_BASE_PTR) +#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1_BASE_PTR) +#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1_BASE_PTR) +/* FTM2 */ +#define FTM2_SC FTM_SC_REG(FTM2_BASE_PTR) +#define FTM2_CNT FTM_CNT_REG(FTM2_BASE_PTR) +#define FTM2_MOD FTM_MOD_REG(FTM2_BASE_PTR) +#define FTM2_C0SC FTM_CSC_REG(FTM2_BASE_PTR,0) +#define FTM2_C0V FTM_CV_REG(FTM2_BASE_PTR,0) +#define FTM2_C1SC FTM_CSC_REG(FTM2_BASE_PTR,1) +#define FTM2_C1V FTM_CV_REG(FTM2_BASE_PTR,1) +#define FTM2_C2SC FTM_CSC_REG(FTM2_BASE_PTR,2) +#define FTM2_C2V FTM_CV_REG(FTM2_BASE_PTR,2) +#define FTM2_C3SC FTM_CSC_REG(FTM2_BASE_PTR,3) +#define FTM2_C3V FTM_CV_REG(FTM2_BASE_PTR,3) +#define FTM2_C4SC FTM_CSC_REG(FTM2_BASE_PTR,4) +#define FTM2_C4V FTM_CV_REG(FTM2_BASE_PTR,4) +#define FTM2_C5SC FTM_CSC_REG(FTM2_BASE_PTR,5) +#define FTM2_C5V FTM_CV_REG(FTM2_BASE_PTR,5) +#define FTM2_C6SC FTM_CSC_REG(FTM2_BASE_PTR,6) +#define FTM2_C6V FTM_CV_REG(FTM2_BASE_PTR,6) +#define FTM2_C7SC FTM_CSC_REG(FTM2_BASE_PTR,7) +#define FTM2_C7V FTM_CV_REG(FTM2_BASE_PTR,7) +#define FTM2_CNTIN FTM_CNTIN_REG(FTM2_BASE_PTR) +#define FTM2_STATUS FTM_STATUS_REG(FTM2_BASE_PTR) +#define FTM2_MODE FTM_MODE_REG(FTM2_BASE_PTR) +#define FTM2_SYNC FTM_SYNC_REG(FTM2_BASE_PTR) +#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2_BASE_PTR) +#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2_BASE_PTR) +#define FTM2_COMBINE FTM_COMBINE_REG(FTM2_BASE_PTR) +#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2_BASE_PTR) +#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2_BASE_PTR) +#define FTM2_POL FTM_POL_REG(FTM2_BASE_PTR) +#define FTM2_FILTER FTM_FILTER_REG(FTM2_BASE_PTR) +#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2_BASE_PTR) +#define FTM2_CONF FTM_CONF_REG(FTM2_BASE_PTR) +#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2_BASE_PTR) +#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2_BASE_PTR) +#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2_BASE_PTR) +#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2_BASE_PTR) /* FTM - Register array accessors */ -#define FTM_CSC(index) FTM_CSC_REG(FTM_BASE_PTR,index) -#define FTM_CV(index) FTM_CV_REG(FTM_BASE_PTR,index) - +#define FTM1_CSC(index) FTM_CSC_REG(FTM1_BASE_PTR,index) +#define FTM2_CSC(index) FTM_CSC_REG(FTM2_BASE_PTR,index) +#define FTM1_CV(index) FTM_CV_REG(FTM1_BASE_PTR,index) +#define FTM2_CV(index) FTM_CV_REG(FTM2_BASE_PTR,index) /*! * @} */ /* end of group FTM_Register_Accessor_Macros */ @@ -69774,7 +18255,6 @@ typedef struct { * @} */ /* end of group FTM_Peripheral */ - /* ---------------------------------------------------------------------------- -- GPC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -69786,21 +18266,69 @@ typedef struct { /** GPC - Register Layout Typedef */ typedef struct { - __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ - __IO uint32_t PGR; /**< GPC Power Gating Register, offset: 0x4 */ - __IO uint32_t IMR1; /**< IRQ masking register 1, offset: 0x8 */ - __IO uint32_t IMR2; /**< IRQ masking register 2, offset: 0xC */ - __IO uint32_t IMR3; /**< IRQ masking register 3, offset: 0x10 */ - __IO uint32_t IMR4; /**< IRQ masking register 4, offset: 0x14 */ - __I uint32_t ISR1; /**< IRQ status resister 1, offset: 0x18 */ - __I uint32_t ISR2; /**< IRQ status resister 2, offset: 0x1C */ - __I uint32_t ISR3; /**< IRQ status resister 3, offset: 0x20 */ - __I uint32_t ISR4; /**< IRQ status resister 4, offset: 0x24 */ - __IO uint32_t A9_LPSR; /**< A9 Low Power Status Register, offset: 0x28 */ - __IO uint32_t M4_LPSR; /**< M4 Low Power Status Register, offset: 0x2C */ - __I uint32_t DR; /**< GPC Debug Register, offset: 0x30 */ + __IO uint32_t LPCR_A7_BSC; /**< Basic Low power control register of A7 platform, offset: 0x0 */ + __IO uint32_t LPCR_A7_AD; /**< Advanced Low power control register of A7 platform, offset: 0x4 */ + __IO uint32_t LPCR_M4; /**< Low power control register of CPU1, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SLPCR; /**< System low power control register, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t MLPCR; /**< Memory low power control register, offset: 0x20 */ + __IO uint32_t PGC_ACK_SEL_A7; /**< PGC acknowledge signal selection of A7 platform, offset: 0x24 */ + __IO uint32_t PGC_ACK_SEL_M4; /**< PGC acknowledge signal selection of M4 platform, offset: 0x28 */ + __IO uint32_t MISC; /**< GPC Miscellaneous register, offset: 0x2C */ + __IO uint32_t IMR1_CORE0_A7; /**< IRQ masking register 1 of A7 core0, offset: 0x30 */ + __IO uint32_t IMR2_CORE0_A7; /**< IRQ masking register 2 of A7 core0, offset: 0x34 */ + __IO uint32_t IMR3_CORE0_A7; /**< IRQ masking register 3 of A7 core0, offset: 0x38 */ + __IO uint32_t IMR4_CORE0_A7; /**< IRQ masking register 4 of A7 core0, offset: 0x3C */ + __IO uint32_t IMR1_CORE1_A7; /**< IRQ masking register 1 of A7 core1, offset: 0x40 */ + __IO uint32_t IMR2_CORE1_A7; /**< IRQ masking register 2 of A7 core1, offset: 0x44 */ + __IO uint32_t IMR3_CORE1_A7; /**< IRQ masking register 3 of A7 core1, offset: 0x48 */ + __IO uint32_t IMR4_CORE1_A7; /**< IRQ masking register 4 of A7 core1, offset: 0x4C */ + __IO uint32_t IMR1_M4; /**< IRQ masking register 1 of M4, offset: 0x50 */ + __IO uint32_t IMR2_M4; /**< IRQ masking register 2 of M4, offset: 0x54 */ + __IO uint32_t IMR3_M4; /**< IRQ masking register 3 of M4, offset: 0x58 */ + __IO uint32_t IMR4_M4; /**< IRQ masking register 4 of M4, offset: 0x5C */ + uint8_t RESERVED_2[16]; + __I uint32_t ISR1_A7; /**< IRQ status register 1 of A7, offset: 0x70 */ + __I uint32_t ISR2_A7; /**< IRQ status register 2 of A7, offset: 0x74 */ + __I uint32_t ISR3_A7; /**< IRQ status register 3 of A7, offset: 0x78 */ + __I uint32_t ISR4_A7; /**< IRQ status register 4 of A7, offset: 0x7C */ + __I uint32_t ISR1_M4; /**< IRQ status register 1 of M4, offset: 0x80 */ + __I uint32_t ISR2_M4; /**< IRQ status register 2 of M4, offset: 0x84 */ + __I uint32_t ISR3_M4; /**< IRQ status register 3 of M4, offset: 0x88 */ + __I uint32_t ISR4_M4; /**< IRQ status register 4 of M4, offset: 0x8C */ + uint8_t RESERVED_3[32]; + __IO uint32_t SLT_CFG[10]; /**< Slot configure register, array offset: 0xB0, array step: 0x4 */ + uint8_t RESERVED_4[20]; + __IO uint32_t PGC_CPU_MAPPING; /**< PGC CPU mapping, offset: 0xEC */ + __IO uint32_t CPU_PGC_SW_PUP_REQ; /**< CPU PGC software up trigger, offset: 0xF0 */ + uint8_t RESERVED_5[4]; + __IO uint32_t PU_PGC_SW_PUP_REQ; /**< PU PGC software up trigger, offset: 0xF8 */ + __IO uint32_t CPU_PGC_SW_PDN_REQ; /**< CPU PGC software down trigger, offset: 0xFC */ + uint8_t RESERVED_6[4]; + __IO uint32_t PU_PGC_SW_PDN_REQ; /**< PU PGC software down trigger, offset: 0x104 */ + uint8_t RESERVED_7[8]; + __I uint32_t LPS_A7; /**< Low power status of A7 platform, offset: 0x110 */ + __IO uint32_t LPS_M4; /**< Low power status of M4 platform, offset: 0x114 */ + uint8_t RESERVED_8[8]; + __IO uint32_t GPC_GPR; /**< GPC general purpose register , offset: 0x120 */ + __IO uint32_t GTOR; /**< GPC testing observe register, offset: 0x124 */ + __I uint32_t DEBUG_ADDR1; /**< DEBUG ADDR1, offset: 0x128 */ + __I uint32_t DEBUG_ADDR2; /**< DEBUG ADDR2, offset: 0x12C */ + __I uint32_t CPU_PGC_PUP_STATUS1; /**< CPU PGC software up trigger status1, offset: 0x130 */ + __I uint32_t A7_PU_PGC_PUP_STATUS[3]; /**< A7 PU software up trigger status register, array offset: 0x134, array step: 0x4 */ + __I uint32_t M4_PU_PGC_PUP_STATUS[3]; /**< A7 MIX PGC software up trigger status1, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_9[36]; + __I uint32_t CPU_PGC_PDN_STATUS1; /**< CPU PGC software dn trigger status1, offset: 0x170 */ + uint8_t RESERVED_10[24]; + __I uint32_t A7_PU_PGC_PDN_STATUS[3]; /**< A7 PU PGC software down trigger status, array offset: 0x18C, array step: 0x4 */ + __I uint32_t M4_PU_PGC_PDN_STATUS[3]; /**< M4 PU PGC software down trigger status, array offset: 0x198, array step: 0x4 */ + uint8_t RESERVED_11[12]; + __IO uint32_t A7_MIX_PDN_FLG; /**< A7 MIX PDN FLG, offset: 0x1B0 */ + __I uint32_t A7_PU_PDN_FLG; /**< A7 PU PDN FLG, offset: 0x1B4 */ + __IO uint32_t M4_MIX_PDN_FLG; /**< M4 MIX PDN FLG, offset: 0x1B8 */ + __I uint32_t M4_PU_PDN_FLG; /**< M4 PU PDN FLG, offset: 0x1BC */ } GPC_Type, *GPC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- GPC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -69812,25 +18340,60 @@ typedef struct { /* GPC - Register accessors */ -#define GPC_CNTR_REG(base) ((base)->CNTR) -#define GPC_PGR_REG(base) ((base)->PGR) -#define GPC_IMR1_REG(base) ((base)->IMR1) -#define GPC_IMR2_REG(base) ((base)->IMR2) -#define GPC_IMR3_REG(base) ((base)->IMR3) -#define GPC_IMR4_REG(base) ((base)->IMR4) -#define GPC_ISR1_REG(base) ((base)->ISR1) -#define GPC_ISR2_REG(base) ((base)->ISR2) -#define GPC_ISR3_REG(base) ((base)->ISR3) -#define GPC_ISR4_REG(base) ((base)->ISR4) -#define GPC_A9_LPSR_REG(base) ((base)->A9_LPSR) -#define GPC_M4_LPSR_REG(base) ((base)->M4_LPSR) -#define GPC_DR_REG(base) ((base)->DR) +#define GPC_LPCR_A7_BSC_REG(base) ((base)->LPCR_A7_BSC) +#define GPC_LPCR_A7_AD_REG(base) ((base)->LPCR_A7_AD) +#define GPC_LPCR_M4_REG(base) ((base)->LPCR_M4) +#define GPC_SLPCR_REG(base) ((base)->SLPCR) +#define GPC_MLPCR_REG(base) ((base)->MLPCR) +#define GPC_PGC_ACK_SEL_A7_REG(base) ((base)->PGC_ACK_SEL_A7) +#define GPC_PGC_ACK_SEL_M4_REG(base) ((base)->PGC_ACK_SEL_M4) +#define GPC_MISC_REG(base) ((base)->MISC) +#define GPC_IMR1_CORE0_A7_REG(base) ((base)->IMR1_CORE0_A7) +#define GPC_IMR2_CORE0_A7_REG(base) ((base)->IMR2_CORE0_A7) +#define GPC_IMR3_CORE0_A7_REG(base) ((base)->IMR3_CORE0_A7) +#define GPC_IMR4_CORE0_A7_REG(base) ((base)->IMR4_CORE0_A7) +#define GPC_IMR1_CORE1_A7_REG(base) ((base)->IMR1_CORE1_A7) +#define GPC_IMR2_CORE1_A7_REG(base) ((base)->IMR2_CORE1_A7) +#define GPC_IMR3_CORE1_A7_REG(base) ((base)->IMR3_CORE1_A7) +#define GPC_IMR4_CORE1_A7_REG(base) ((base)->IMR4_CORE1_A7) +#define GPC_IMR1_M4_REG(base) ((base)->IMR1_M4) +#define GPC_IMR2_M4_REG(base) ((base)->IMR2_M4) +#define GPC_IMR3_M4_REG(base) ((base)->IMR3_M4) +#define GPC_IMR4_M4_REG(base) ((base)->IMR4_M4) +#define GPC_ISR1_A7_REG(base) ((base)->ISR1_A7) +#define GPC_ISR2_A7_REG(base) ((base)->ISR2_A7) +#define GPC_ISR3_A7_REG(base) ((base)->ISR3_A7) +#define GPC_ISR4_A7_REG(base) ((base)->ISR4_A7) +#define GPC_ISR1_M4_REG(base) ((base)->ISR1_M4) +#define GPC_ISR2_M4_REG(base) ((base)->ISR2_M4) +#define GPC_ISR3_M4_REG(base) ((base)->ISR3_M4) +#define GPC_ISR4_M4_REG(base) ((base)->ISR4_M4) +#define GPC_SLT_CFG_REG(base,index) ((base)->SLT_CFG[index]) +#define GPC_PGC_CPU_MAPPING_REG(base) ((base)->PGC_CPU_MAPPING) +#define GPC_CPU_PGC_SW_PUP_REQ_REG(base) ((base)->CPU_PGC_SW_PUP_REQ) +#define GPC_PU_PGC_SW_PUP_REQ_REG(base) ((base)->PU_PGC_SW_PUP_REQ) +#define GPC_CPU_PGC_SW_PDN_REQ_REG(base) ((base)->CPU_PGC_SW_PDN_REQ) +#define GPC_PU_PGC_SW_PDN_REQ_REG(base) ((base)->PU_PGC_SW_PDN_REQ) +#define GPC_LPS_A7_REG(base) ((base)->LPS_A7) +#define GPC_LPS_M4_REG(base) ((base)->LPS_M4) +#define GPC_GPC_GPR_REG(base) ((base)->GPC_GPR) +#define GPC_GTOR_REG(base) ((base)->GTOR) +#define GPC_DEBUG_ADDR1_REG(base) ((base)->DEBUG_ADDR1) +#define GPC_DEBUG_ADDR2_REG(base) ((base)->DEBUG_ADDR2) +#define GPC_CPU_PGC_PUP_STATUS1_REG(base) ((base)->CPU_PGC_PUP_STATUS1) +#define GPC_A7_PU_PGC_PUP_STATUS_REG(base,index) ((base)->A7_PU_PGC_PUP_STATUS[index]) +#define GPC_M4_PU_PGC_PUP_STATUS_REG(base,index) ((base)->M4_PU_PGC_PUP_STATUS[index]) +#define GPC_CPU_PGC_PDN_STATUS1_REG(base) ((base)->CPU_PGC_PDN_STATUS1) +#define GPC_A7_PU_PGC_PDN_STATUS_REG(base,index) ((base)->A7_PU_PGC_PDN_STATUS[index]) +#define GPC_M4_PU_PGC_PDN_STATUS_REG(base,index) ((base)->M4_PU_PGC_PDN_STATUS[index]) +#define GPC_A7_MIX_PDN_FLG_REG(base) ((base)->A7_MIX_PDN_FLG) +#define GPC_A7_PU_PDN_FLG_REG(base) ((base)->A7_PU_PDN_FLG) +#define GPC_M4_MIX_PDN_FLG_REG(base) ((base)->M4_MIX_PDN_FLG) +#define GPC_M4_PU_PDN_FLG_REG(base) ((base)->M4_PU_PDN_FLG) /*! * @} */ /* end of group GPC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- GPC Register Masks ---------------------------------------------------------------------------- */ @@ -69840,165 +18403,629 @@ typedef struct { * @{ */ -/* CNTR Bit Fields */ -#define GPC_CNTR_gpu_vpu_pdn_req_MASK 0x1u -#define GPC_CNTR_gpu_vpu_pdn_req_SHIFT 0 -#define GPC_CNTR_gpu_vpu_pup_req_MASK 0x2u -#define GPC_CNTR_gpu_vpu_pup_req_SHIFT 1 -#define GPC_CNTR_MEGA_PDN_REQ_MASK 0x4u -#define GPC_CNTR_MEGA_PDN_REQ_SHIFT 2 -#define GPC_CNTR_MEGA_PUP_REQ_MASK 0x8u -#define GPC_CNTR_MEGA_PUP_REQ_SHIFT 3 -#define GPC_CNTR_DISPLAY_PDN_REQ_MASK 0x10u -#define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT 4 -#define GPC_CNTR_DISPLAY_PUP_REQ_MASK 0x20u -#define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT 5 -#define GPC_CNTR_PCIE_PHY_PDN_REQ_MASK 0x40u -#define GPC_CNTR_PCIE_PHY_PDN_REQ_SHIFT 6 -#define GPC_CNTR_PCIE_PHY_PUP_REQ_MASK 0x80u -#define GPC_CNTR_PCIE_PHY_PUP_REQ_SHIFT 7 -#define GPC_CNTR_DVFS0CR_MASK 0x10000u -#define GPC_CNTR_DVFS0CR_SHIFT 16 -#define GPC_CNTR_VADC_ANALOG_OFF_MASK 0x20000u -#define GPC_CNTR_VADC_ANALOG_OFF_SHIFT 17 -#define GPC_CNTR_VADC_EXT_PWD_N_MASK 0x40000u -#define GPC_CNTR_VADC_EXT_PWD_N_SHIFT 18 -#define GPC_CNTR_GPCIRQM_MASK 0x200000u -#define GPC_CNTR_GPCIRQM_SHIFT 21 -#define GPC_CNTR_L2_PGE_MASK 0x400000u -#define GPC_CNTR_L2_PGE_SHIFT 22 -/* PGR Bit Fields */ -#define GPC_PGR_DRCIC_MASK 0x60000000u -#define GPC_PGR_DRCIC_SHIFT 29 -#define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGR_DRCIC_SHIFT))&GPC_PGR_DRCIC_MASK) -/* IMR1 Bit Fields */ -#define GPC_IMR1_IMR1_MASK 0xFFFFFFFFu -#define GPC_IMR1_IMR1_SHIFT 0 -#define GPC_IMR1_IMR1(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_IMR1_SHIFT))&GPC_IMR1_IMR1_MASK) -/* IMR2 Bit Fields */ -#define GPC_IMR2_IMR2_MASK 0xFFFFFFFFu -#define GPC_IMR2_IMR2_SHIFT 0 -#define GPC_IMR2_IMR2(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_IMR2_SHIFT))&GPC_IMR2_IMR2_MASK) -/* IMR3 Bit Fields */ -#define GPC_IMR3_IMR3_MASK 0xFFFFFFFFu -#define GPC_IMR3_IMR3_SHIFT 0 -#define GPC_IMR3_IMR3(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_IMR3_SHIFT))&GPC_IMR3_IMR3_MASK) -/* IMR4 Bit Fields */ -#define GPC_IMR4_IMR4_MASK 0xFFFFFFFFu -#define GPC_IMR4_IMR4_SHIFT 0 -#define GPC_IMR4_IMR4(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_IMR4_SHIFT))&GPC_IMR4_IMR4_MASK) -/* ISR1 Bit Fields */ -#define GPC_ISR1_ISR1_MASK 0xFFFFFFFFu -#define GPC_ISR1_ISR1_SHIFT 0 -#define GPC_ISR1_ISR1(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR1_ISR1_SHIFT))&GPC_ISR1_ISR1_MASK) -/* ISR2 Bit Fields */ -#define GPC_ISR2_ISR2_MASK 0xFFFFFFFFu -#define GPC_ISR2_ISR2_SHIFT 0 -#define GPC_ISR2_ISR2(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_ISR2_SHIFT))&GPC_ISR2_ISR2_MASK) -/* ISR3 Bit Fields */ -#define GPC_ISR3_ISR3_MASK 0xFFFFFFFFu -#define GPC_ISR3_ISR3_SHIFT 0 -#define GPC_ISR3_ISR3(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_ISR3_SHIFT))&GPC_ISR3_ISR3_MASK) -/* ISR4 Bit Fields */ -#define GPC_ISR4_ISR4_MASK 0xFFFFFFFFu -#define GPC_ISR4_ISR4_SHIFT 0 -#define GPC_ISR4_ISR4(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR4_ISR4_SHIFT))&GPC_ISR4_ISR4_MASK) -/* A9_LPSR Bit Fields */ -#define GPC_A9_LPSR_A9_STANDBY_WFI_MASK 0x1u -#define GPC_A9_LPSR_A9_STANDBY_WFI_SHIFT 0 -#define GPC_A9_LPSR_A9_SCU_IDLE_MASK 0x10u -#define GPC_A9_LPSR_A9_SCU_IDLE_SHIFT 4 -#define GPC_A9_LPSR_A9_L2CC_IDLE_MASK 0x20u -#define GPC_A9_LPSR_A9_L2CC_IDLE_SHIFT 5 -#define GPC_A9_LPSR_A9_CLK_ENABLE_MASK 0x40u -#define GPC_A9_LPSR_A9_CLK_ENABLE_SHIFT 6 -#define GPC_A9_LPSR_SYSTEM_IN_WAIT_MODE_MASK 0x80u -#define GPC_A9_LPSR_SYSTEM_IN_WAIT_MODE_SHIFT 7 -#define GPC_A9_LPSR_SYSTEM_IN_STOP_MODE_MASK 0x100u -#define GPC_A9_LPSR_SYSTEM_IN_STOP_MODE_SHIFT 8 -#define GPC_A9_LPSR_A9_DBG_ACK_MASK 0x200u -#define GPC_A9_LPSR_A9_DBG_ACK_SHIFT 9 -#define GPC_A9_LPSR_A9_RST_MASK 0x400u -#define GPC_A9_LPSR_A9_RST_SHIFT 10 -/* M4_LPSR Bit Fields */ -#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_B_MASK 0x1u -#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_B_SHIFT 0 -#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_B_MASK 0x2u -#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_B_SHIFT 1 -#define GPC_M4_LPSR_M4_GATE_HCLK_MASK 0x4u -#define GPC_M4_LPSR_M4_GATE_HCLK_SHIFT 2 -#define GPC_M4_LPSR_M4_SLEEP_DEEP_MASK 0x8u -#define GPC_M4_LPSR_M4_SLEEP_DEEP_SHIFT 3 -#define GPC_M4_LPSR_M4_SLEEPING_MASK 0x10u -#define GPC_M4_LPSR_M4_SLEEPING_SHIFT 4 -#define GPC_M4_LPSR_M4_LOCKUP_MASK 0x20u -#define GPC_M4_LPSR_M4_LOCKUP_SHIFT 5 -#define GPC_M4_LPSR_M4_HALTED_MASK 0x40u -#define GPC_M4_LPSR_M4_HALTED_SHIFT 6 -#define GPC_M4_LPSR_M4_PLATFORM_RESET_B_MASK 0x80u -#define GPC_M4_LPSR_M4_PLATFORM_RESET_B_SHIFT 7 -#define GPC_M4_LPSR_M4_CORE_RESET_B_MASK 0x100u -#define GPC_M4_LPSR_M4_CORE_RESET_B_SHIFT 8 -/* DR Bit Fields */ -#define GPC_DR_PCIE_PHY_RESET_B_MASK 0x1u -#define GPC_DR_PCIE_PHY_RESET_B_SHIFT 0 -#define GPC_DR_PCIE_PHY_ISO_MASK 0x2u -#define GPC_DR_PCIE_PHY_ISO_SHIFT 1 -#define GPC_DR_MEGA_RESET_B_MASK 0x4u -#define GPC_DR_MEGA_RESET_B_SHIFT 2 -#define GPC_DR_MEGA_SWITCH_B_MASK 0x8u -#define GPC_DR_MEGA_SWITCH_B_SHIFT 3 -#define GPC_DR_MEGA_ISO_MASK 0x10u -#define GPC_DR_MEGA_ISO_SHIFT 4 -#define GPC_DR_GPC_PUP_ACK_MASK 0x20u -#define GPC_DR_GPC_PUP_ACK_SHIFT 5 -#define GPC_DR_GPC_PDN_ACK_MASK 0x40u -#define GPC_DR_GPC_PDN_ACK_SHIFT 6 -#define GPC_DR_GPC_DISP_RESET_B_MASK 0x80u -#define GPC_DR_GPC_DISP_RESET_B_SHIFT 7 -#define GPC_DR_GPC_DISP_SWITCH_B_MASK 0x100u -#define GPC_DR_GPC_DISP_SWITCH_B_SHIFT 8 -#define GPC_DR_GPC_DISP_ISO_MASK 0x200u -#define GPC_DR_GPC_DISP_ISO_SHIFT 9 -#define GPC_DR_GPC_GPU_RESET_B_MASK 0x400u -#define GPC_DR_GPC_GPU_RESET_B_SHIFT 10 -#define GPC_DR_GPC_GPU_SWITCH_B_MASK 0x800u -#define GPC_DR_GPC_GPU_SWITCH_B_SHIFT 11 -#define GPC_DR_GPC_GPU_ISO_MASK 0x1000u -#define GPC_DR_GPC_GPU_ISO_SHIFT 12 -#define GPC_DR_GPC_L2SOC_ISO_MASK 0x2000u -#define GPC_DR_GPC_L2SOC_ISO_SHIFT 13 -#define GPC_DR_GPC_L2CPU_ISO_MASK 0x4000u -#define GPC_DR_GPC_L2CPU_ISO_SHIFT 14 -#define GPC_DR_GPC_L2_SWITCH_B_MASK 0x8000u -#define GPC_DR_GPC_L2_SWITCH_B_SHIFT 15 -#define GPC_DR_GPC_CPU_RESET_B_MASK 0x10000u -#define GPC_DR_GPC_CPU_RESET_B_SHIFT 16 -#define GPC_DR_GPC_CPU_SWITCH_B_MASK 0x20000u -#define GPC_DR_GPC_CPU_SWITCH_B_SHIFT 17 -#define GPC_DR_GPC_CPU_ISO_MASK 0x40000u -#define GPC_DR_GPC_CPU_ISO_SHIFT 18 -#define GPC_DR_IPG_STOP_MASK 0x80000u -#define GPC_DR_IPG_STOP_SHIFT 19 -#define GPC_DR_IPG_WAIT_MASK 0x100000u -#define GPC_DR_IPG_WAIT_SHIFT 20 +/* LPCR_A7_BSC Bit Fields */ +#define GPC_LPCR_A7_BSC_LPM0_MASK 0x3u +#define GPC_LPCR_A7_BSC_LPM0_SHIFT 0 +#define GPC_LPCR_A7_BSC_LPM0(x) (((uint32_t)(((uint32_t)(x))<<GPC_LPCR_A7_BSC_LPM0_SHIFT))&GPC_LPCR_A7_BSC_LPM0_MASK) +#define GPC_LPCR_A7_BSC_LPM1_MASK 0xCu +#define GPC_LPCR_A7_BSC_LPM1_SHIFT 2 +#define GPC_LPCR_A7_BSC_LPM1(x) (((uint32_t)(((uint32_t)(x))<<GPC_LPCR_A7_BSC_LPM1_SHIFT))&GPC_LPCR_A7_BSC_LPM1_MASK) +#define GPC_LPCR_A7_BSC_CPU_CLK_ON_LPM_MASK 0x4000u +#define GPC_LPCR_A7_BSC_CPU_CLK_ON_LPM_SHIFT 14 +#define GPC_LPCR_A7_BSC_MASK_CORE0_WFI_MASK 0x10000u +#define GPC_LPCR_A7_BSC_MASK_CORE0_WFI_SHIFT 16 +#define GPC_LPCR_A7_BSC_MASK_CORE1_WFI_MASK 0x20000u +#define GPC_LPCR_A7_BSC_MASK_CORE1_WFI_SHIFT 17 +#define GPC_LPCR_A7_BSC_MASK_L2CC_WFI_MASK 0x4000000u +#define GPC_LPCR_A7_BSC_MASK_L2CC_WFI_SHIFT 26 +#define GPC_LPCR_A7_BSC_IRQ_SRC_C0_MASK 0x10000000u +#define GPC_LPCR_A7_BSC_IRQ_SRC_C0_SHIFT 28 +#define GPC_LPCR_A7_BSC_IRQ_SRC_C1_MASK 0x20000000u +#define GPC_LPCR_A7_BSC_IRQ_SRC_C1_SHIFT 29 +#define GPC_LPCR_A7_BSC_IRQ_SRC_A7_WUP_MASK 0x40000000u +#define GPC_LPCR_A7_BSC_IRQ_SRC_A7_WUP_SHIFT 30 +#define GPC_LPCR_A7_BSC_MASK_DSM_TRIGGER_MASK 0x80000000u +#define GPC_LPCR_A7_BSC_MASK_DSM_TRIGGER_SHIFT 31 +/* LPCR_A7_AD Bit Fields */ +#define GPC_LPCR_A7_AD_EN_C0_WFI_PDN_MASK 0x1u +#define GPC_LPCR_A7_AD_EN_C0_WFI_PDN_SHIFT 0 +#define GPC_LPCR_A7_AD_EN_C0_PDN_MASK 0x2u +#define GPC_LPCR_A7_AD_EN_C0_PDN_SHIFT 1 +#define GPC_LPCR_A7_AD_EN_C1_WFI_PDN_MASK 0x4u +#define GPC_LPCR_A7_AD_EN_C1_WFI_PDN_SHIFT 2 +#define GPC_LPCR_A7_AD_EN_C1_PDN_MASK 0x8u +#define GPC_LPCR_A7_AD_EN_C1_PDN_SHIFT 3 +#define GPC_LPCR_A7_AD_EN_PLAT_PDN_MASK 0x10u +#define GPC_LPCR_A7_AD_EN_PLAT_PDN_SHIFT 4 +#define GPC_LPCR_A7_AD_EN_C0_IRQ_PUP_MASK 0x100u +#define GPC_LPCR_A7_AD_EN_C0_IRQ_PUP_SHIFT 8 +#define GPC_LPCR_A7_AD_EN_C0_PUP_MASK 0x200u +#define GPC_LPCR_A7_AD_EN_C0_PUP_SHIFT 9 +#define GPC_LPCR_A7_AD_EN_C1_IRQ_PUP_MASK 0x400u +#define GPC_LPCR_A7_AD_EN_C1_IRQ_PUP_SHIFT 10 +#define GPC_LPCR_A7_AD_EN_C1_PUP_MASK 0x800u +#define GPC_LPCR_A7_AD_EN_C1_PUP_SHIFT 11 +#define GPC_LPCR_A7_AD_L2_PGE_MASK 0x10000u +#define GPC_LPCR_A7_AD_L2_PGE_SHIFT 16 +/* LPCR_M4 Bit Fields */ +#define GPC_LPCR_M4_LPM0_MASK 0x3u +#define GPC_LPCR_M4_LPM0_SHIFT 0 +#define GPC_LPCR_M4_LPM0(x) (((uint32_t)(((uint32_t)(x))<<GPC_LPCR_M4_LPM0_SHIFT))&GPC_LPCR_M4_LPM0_MASK) +#define GPC_LPCR_M4_EN_M4_PDN_MASK 0x4u +#define GPC_LPCR_M4_EN_M4_PDN_SHIFT 2 +#define GPC_LPCR_M4_EN_M4_PUP_MASK 0x8u +#define GPC_LPCR_M4_EN_M4_PUP_SHIFT 3 +#define GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK 0x4000u +#define GPC_LPCR_M4_CPU_CLK_ON_LPM_SHIFT 14 +#define GPC_LPCR_M4_MASK_M4_WFI_MASK 0x10000u +#define GPC_LPCR_M4_MASK_M4_WFI_SHIFT 16 +#define GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK 0x80000000u +#define GPC_LPCR_M4_MASK_DSM_TRIGGER_SHIFT 31 +/* SLPCR Bit Fields */ +#define GPC_SLPCR_BYPASS_PMIC_READY_MASK 0x1u +#define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT 0 +#define GPC_SLPCR_SBYOS_MASK 0x2u +#define GPC_SLPCR_SBYOS_SHIFT 1 +#define GPC_SLPCR_VSTBY_MASK 0x4u +#define GPC_SLPCR_VSTBY_SHIFT 2 +#define GPC_SLPCR_STBY_COUNT_MASK 0x38u +#define GPC_SLPCR_STBY_COUNT_SHIFT 3 +#define GPC_SLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_SLPCR_STBY_COUNT_SHIFT))&GPC_SLPCR_STBY_COUNT_MASK) +#define GPC_SLPCR_COSC_PWRDOWN_MASK 0x40u +#define GPC_SLPCR_COSC_PWRDOWN_SHIFT 6 +#define GPC_SLPCR_COSC_EN_MASK 0x80u +#define GPC_SLPCR_COSC_EN_SHIFT 7 +#define GPC_SLPCR_OSCCNT_MASK 0xFF00u +#define GPC_SLPCR_OSCCNT_SHIFT 8 +#define GPC_SLPCR_OSCCNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_SLPCR_OSCCNT_SHIFT))&GPC_SLPCR_OSCCNT_MASK) +#define GPC_SLPCR_EN_A7_FASTWUP_WAIT_MODE_MASK 0x10000u +#define GPC_SLPCR_EN_A7_FASTWUP_WAIT_MODE_SHIFT 16 +#define GPC_SLPCR_EN_A7_FASTWUP_STOP_MODE_MASK 0x20000u +#define GPC_SLPCR_EN_A7_FASTWUP_STOP_MODE_SHIFT 17 +#define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK 0x40000u +#define GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_SHIFT 18 +#define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK 0x80000u +#define GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_SHIFT 19 +#define GPC_SLPCR_DISABLE_A7_IS_DSM_MASK 0x800000u +#define GPC_SLPCR_DISABLE_A7_IS_DSM_SHIFT 23 +#define GPC_SLPCR_REG_BYPASS_COUNT_MASK 0x3F000000u +#define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT 24 +#define GPC_SLPCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_SLPCR_REG_BYPASS_COUNT_SHIFT))&GPC_SLPCR_REG_BYPASS_COUNT_MASK) +#define GPC_SLPCR_RBC_EN_MASK 0x40000000u +#define GPC_SLPCR_RBC_EN_SHIFT 30 +#define GPC_SLPCR_EN_DSM_MASK 0x80000000u +#define GPC_SLPCR_EN_DSM_SHIFT 31 +/* MLPCR Bit Fields */ +#define GPC_MLPCR_MEMLP_CTL_DIS_MASK 0x1u +#define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT 0 +#define GPC_MLPCR_MEMLP_RET_SEL_MASK 0x2u +#define GPC_MLPCR_MEMLP_RET_SEL_SHIFT 1 +#define GPC_MLPCR_ROMLP_PDN_DIS_MASK 0x4u +#define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT 2 +#define GPC_MLPCR_MEMLP_ENT_CNT_MASK 0xFF00u +#define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT 8 +#define GPC_MLPCR_MEMLP_ENT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_MLPCR_MEMLP_ENT_CNT_SHIFT))&GPC_MLPCR_MEMLP_ENT_CNT_MASK) +#define GPC_MLPCR_MEM_EXT_CNT_MASK 0xFF0000u +#define GPC_MLPCR_MEM_EXT_CNT_SHIFT 16 +#define GPC_MLPCR_MEM_EXT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_MLPCR_MEM_EXT_CNT_SHIFT))&GPC_MLPCR_MEM_EXT_CNT_MASK) +#define GPC_MLPCR_MEMLP_RET_PGEN_MASK 0xFF000000u +#define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT 24 +#define GPC_MLPCR_MEMLP_RET_PGEN(x) (((uint32_t)(((uint32_t)(x))<<GPC_MLPCR_MEMLP_RET_PGEN_SHIFT))&GPC_MLPCR_MEMLP_RET_PGEN_MASK) +/* PGC_ACK_SEL_A7 Bit Fields */ +#define GPC_PGC_ACK_SEL_A7_A7_C0_PGC_PDN_ACK_MASK 0x1u +#define GPC_PGC_ACK_SEL_A7_A7_C0_PGC_PDN_ACK_SHIFT 0 +#define GPC_PGC_ACK_SEL_A7_A7_C1_PGC_PDN_ACK_MASK 0x2u +#define GPC_PGC_ACK_SEL_A7_A7_C1_PGC_PDN_ACK_SHIFT 1 +#define GPC_PGC_ACK_SEL_A7_A7_PLAT_PGC_PDN_ACK_MASK 0x4u +#define GPC_PGC_ACK_SEL_A7_A7_PLAT_PGC_PDN_ACK_SHIFT 2 +#define GPC_PGC_ACK_SEL_A7_MF_PGC_PDN_ACK_MASK 0x8u +#define GPC_PGC_ACK_SEL_A7_MF_PGC_PDN_ACK_SHIFT 3 +#define GPC_PGC_ACK_SEL_A7_MIPI_PGC_PDN_ACK_MASK 0x10u +#define GPC_PGC_ACK_SEL_A7_MIPI_PGC_PDN_ACK_SHIFT 4 +#define GPC_PGC_ACK_SEL_A7_PCIE_PGC_PDN_ACK_MASK 0x20u +#define GPC_PGC_ACK_SEL_A7_PCIE_PGC_PDN_ACK_SHIFT 5 +#define GPC_PGC_ACK_SEL_A7_USB_OTG1_PGC_PDN_ACK_MASK 0x40u +#define GPC_PGC_ACK_SEL_A7_USB_OTG1_PGC_PDN_ACK_SHIFT 6 +#define GPC_PGC_ACK_SEL_A7_USB_OTG2_PGC_PDN_ACK_MASK 0x80u +#define GPC_PGC_ACK_SEL_A7_USB_OTG2_PGC_PDN_ACK_SHIFT 7 +#define GPC_PGC_ACK_SEL_A7_USB_HSIC_PGC_PDN_ACK_MASK 0x100u +#define GPC_PGC_ACK_SEL_A7_USB_HSIC_PGC_PDN_ACK_SHIFT 8 +#define GPC_PGC_ACK_SEL_A7_A7_PGC_PDN_ACK_MASK 0x8000u +#define GPC_PGC_ACK_SEL_A7_A7_PGC_PDN_ACK_SHIFT 15 +#define GPC_PGC_ACK_SEL_A7_A7_C0_PGC_PUP_ACK_MASK 0x10000u +#define GPC_PGC_ACK_SEL_A7_A7_C0_PGC_PUP_ACK_SHIFT 16 +#define GPC_PGC_ACK_SEL_A7_A7_C1_PGC_PUP_ACK_MASK 0x20000u +#define GPC_PGC_ACK_SEL_A7_A7_C1_PGC_PUP_ACK_SHIFT 17 +#define GPC_PGC_ACK_SEL_A7_A7_PLAT_PGC_PUP_ACK_MASK 0x40000u +#define GPC_PGC_ACK_SEL_A7_A7_PLAT_PGC_PUP_ACK_SHIFT 18 +#define GPC_PGC_ACK_SEL_A7_MF_PGC_PUP_ACK_MASK 0x80000u +#define GPC_PGC_ACK_SEL_A7_MF_PGC_PUP_ACK_SHIFT 19 +#define GPC_PGC_ACK_SEL_A7_MIPI_PGC_PUP_ACK_MASK 0x100000u +#define GPC_PGC_ACK_SEL_A7_MIPI_PGC_PUP_ACK_SHIFT 20 +#define GPC_PGC_ACK_SEL_A7_PCIE_PGC_PUP_ACK_MASK 0x200000u +#define GPC_PGC_ACK_SEL_A7_PCIE_PGC_PUP_ACK_SHIFT 21 +#define GPC_PGC_ACK_SEL_A7_USB_OTG1_PGC_PUP_ACK_MASK 0x400000u +#define GPC_PGC_ACK_SEL_A7_USB_OTG1_PGC_PUP_ACK_SHIFT 22 +#define GPC_PGC_ACK_SEL_A7_USB_OTG2_PGC_PUP_ACK_MASK 0x800000u +#define GPC_PGC_ACK_SEL_A7_USB_OTG2_PGC_PUP_ACK_SHIFT 23 +#define GPC_PGC_ACK_SEL_A7_USB_HSIC_PGC_PUP_ACK_MASK 0x1000000u +#define GPC_PGC_ACK_SEL_A7_USB_HSIC_PGC_PUP_ACK_SHIFT 24 +#define GPC_PGC_ACK_SEL_A7_A7_PGC_PUP_ACK_MASK 0x80000000u +#define GPC_PGC_ACK_SEL_A7_A7_PGC_PUP_ACK_SHIFT 31 +/* PGC_ACK_SEL_M4 Bit Fields */ +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK 0x1u +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_SHIFT 0 +#define GPC_PGC_ACK_SEL_M4_MF_PGC_PDN_ACK_MASK 0x8u +#define GPC_PGC_ACK_SEL_M4_MF_PGC_PDN_ACK_SHIFT 3 +#define GPC_PGC_ACK_SEL_M4_MIPI_PGC_PDN_ACK_MASK 0x10u +#define GPC_PGC_ACK_SEL_M4_MIPI_PGC_PDN_ACK_SHIFT 4 +#define GPC_PGC_ACK_SEL_M4_PCIE_PGC_PDN_ACK_MASK 0x20u +#define GPC_PGC_ACK_SEL_M4_PCIE_PGC_PDN_ACK_SHIFT 5 +#define GPC_PGC_ACK_SEL_M4_USB_OTG1_PGC_PDN_ACK_MASK 0x40u +#define GPC_PGC_ACK_SEL_M4_USB_OTG1_PGC_PDN_ACK_SHIFT 6 +#define GPC_PGC_ACK_SEL_M4_USB_OTG2_PGC_PDN_ACK_MASK 0x80u +#define GPC_PGC_ACK_SEL_M4_USB_OTG2_PGC_PDN_ACK_SHIFT 7 +#define GPC_PGC_ACK_SEL_M4_USB_HSIC_PGC_PDN_ACK_MASK 0x100u +#define GPC_PGC_ACK_SEL_M4_USB_HSIC_PGC_PDN_ACK_SHIFT 8 +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK 0x8000u +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_SHIFT 15 +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK 0x10000u +#define GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_SHIFT 16 +#define GPC_PGC_ACK_SEL_M4_MF_PGC_PUP_ACK_MASK 0x80000u +#define GPC_PGC_ACK_SEL_M4_MF_PGC_PUP_ACK_SHIFT 19 +#define GPC_PGC_ACK_SEL_M4_MIPI_PGC_PUP_ACK_MASK 0x100000u +#define GPC_PGC_ACK_SEL_M4_MIPI_PGC_PUP_ACK_SHIFT 20 +#define GPC_PGC_ACK_SEL_M4_PCIE_PGC_PUP_ACK_MASK 0x200000u +#define GPC_PGC_ACK_SEL_M4_PCIE_PGC_PUP_ACK_SHIFT 21 +#define GPC_PGC_ACK_SEL_M4_USB_OTG1_PGC_PUP_ACK_MASK 0x400000u +#define GPC_PGC_ACK_SEL_M4_USB_OTG1_PGC_PUP_ACK_SHIFT 22 +#define GPC_PGC_ACK_SEL_M4_USB_OTG2_PGC_PUP_ACK_MASK 0x800000u +#define GPC_PGC_ACK_SEL_M4_USB_OTG2_PGC_PUP_ACK_SHIFT 23 +#define GPC_PGC_ACK_SEL_M4_USB_HSIC_PGC_PUP_ACK_MASK 0x1000000u +#define GPC_PGC_ACK_SEL_M4_USB_HSIC_PGC_PUP_ACK_SHIFT 24 +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK 0x80000000u +#define GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_SHIFT 31 +/* MISC Bit Fields */ +#define GPC_MISC_M4_SLEEP_HOLD_REQ_B_MASK 0x1u +#define GPC_MISC_M4_SLEEP_HOLD_REQ_B_SHIFT 0 +#define GPC_MISC_GPC_IRQ_MASK_MASK 0x20u +#define GPC_MISC_GPC_IRQ_MASK_SHIFT 5 +#define GPC_MISC_M4_PDN_REQ_MASK_MASK 0x100u +#define GPC_MISC_M4_PDN_REQ_MASK_SHIFT 8 +/* IMR1_CORE0_A7 Bit Fields */ +#define GPC_IMR1_CORE0_A7_IMR1_CORE0_A7_MASK 0xFFFFFFFFu +#define GPC_IMR1_CORE0_A7_IMR1_CORE0_A7_SHIFT 0 +#define GPC_IMR1_CORE0_A7_IMR1_CORE0_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_CORE0_A7_IMR1_CORE0_A7_SHIFT))&GPC_IMR1_CORE0_A7_IMR1_CORE0_A7_MASK) +/* IMR2_CORE0_A7 Bit Fields */ +#define GPC_IMR2_CORE0_A7_IMR2_CORE0_A7_MASK 0xFFFFFFFFu +#define GPC_IMR2_CORE0_A7_IMR2_CORE0_A7_SHIFT 0 +#define GPC_IMR2_CORE0_A7_IMR2_CORE0_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_CORE0_A7_IMR2_CORE0_A7_SHIFT))&GPC_IMR2_CORE0_A7_IMR2_CORE0_A7_MASK) +/* IMR3_CORE0_A7 Bit Fields */ +#define GPC_IMR3_CORE0_A7_IMR3_CORE0_A7_MASK 0xFFFFFFFFu +#define GPC_IMR3_CORE0_A7_IMR3_CORE0_A7_SHIFT 0 +#define GPC_IMR3_CORE0_A7_IMR3_CORE0_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_CORE0_A7_IMR3_CORE0_A7_SHIFT))&GPC_IMR3_CORE0_A7_IMR3_CORE0_A7_MASK) +/* IMR4_CORE0_A7 Bit Fields */ +#define GPC_IMR4_CORE0_A7_IMR4_CORE0_A7_MASK 0xFFFFFFFFu +#define GPC_IMR4_CORE0_A7_IMR4_CORE0_A7_SHIFT 0 +#define GPC_IMR4_CORE0_A7_IMR4_CORE0_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_CORE0_A7_IMR4_CORE0_A7_SHIFT))&GPC_IMR4_CORE0_A7_IMR4_CORE0_A7_MASK) +/* IMR1_CORE1_A7 Bit Fields */ +#define GPC_IMR1_CORE1_A7_IMR1_CORE1_A7_MASK 0xFFFFFFFFu +#define GPC_IMR1_CORE1_A7_IMR1_CORE1_A7_SHIFT 0 +#define GPC_IMR1_CORE1_A7_IMR1_CORE1_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_CORE1_A7_IMR1_CORE1_A7_SHIFT))&GPC_IMR1_CORE1_A7_IMR1_CORE1_A7_MASK) +/* IMR2_CORE1_A7 Bit Fields */ +#define GPC_IMR2_CORE1_A7_IMR2_CORE1_A7_MASK 0xFFFFFFFFu +#define GPC_IMR2_CORE1_A7_IMR2_CORE1_A7_SHIFT 0 +#define GPC_IMR2_CORE1_A7_IMR2_CORE1_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_CORE1_A7_IMR2_CORE1_A7_SHIFT))&GPC_IMR2_CORE1_A7_IMR2_CORE1_A7_MASK) +/* IMR3_CORE1_A7 Bit Fields */ +#define GPC_IMR3_CORE1_A7_IMR3_CORE1_A7_MASK 0xFFFFFFFFu +#define GPC_IMR3_CORE1_A7_IMR3_CORE1_A7_SHIFT 0 +#define GPC_IMR3_CORE1_A7_IMR3_CORE1_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_CORE1_A7_IMR3_CORE1_A7_SHIFT))&GPC_IMR3_CORE1_A7_IMR3_CORE1_A7_MASK) +/* IMR4_CORE1_A7 Bit Fields */ +#define GPC_IMR4_CORE1_A7_IMR4_CORE1_A7_MASK 0xFFFFFFFFu +#define GPC_IMR4_CORE1_A7_IMR4_CORE1_A7_SHIFT 0 +#define GPC_IMR4_CORE1_A7_IMR4_CORE1_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_CORE1_A7_IMR4_CORE1_A7_SHIFT))&GPC_IMR4_CORE1_A7_IMR4_CORE1_A7_MASK) +/* IMR1_M4 Bit Fields */ +#define GPC_IMR1_M4_IMR1_M4_MASK 0xFFFFFFFFu +#define GPC_IMR1_M4_IMR1_M4_SHIFT 0 +#define GPC_IMR1_M4_IMR1_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_M4_IMR1_M4_SHIFT))&GPC_IMR1_M4_IMR1_M4_MASK) +/* IMR2_M4 Bit Fields */ +#define GPC_IMR2_M4_IMR2_M4_MASK 0xFFFFFFFFu +#define GPC_IMR2_M4_IMR2_M4_SHIFT 0 +#define GPC_IMR2_M4_IMR2_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_M4_IMR2_M4_SHIFT))&GPC_IMR2_M4_IMR2_M4_MASK) +/* IMR3_M4 Bit Fields */ +#define GPC_IMR3_M4_IMR3_M4_MASK 0xFFFFFFFFu +#define GPC_IMR3_M4_IMR3_M4_SHIFT 0 +#define GPC_IMR3_M4_IMR3_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_M4_IMR3_M4_SHIFT))&GPC_IMR3_M4_IMR3_M4_MASK) +/* IMR4_M4 Bit Fields */ +#define GPC_IMR4_M4_IMR4_M4_MASK 0xFFFFFFFFu +#define GPC_IMR4_M4_IMR4_M4_SHIFT 0 +#define GPC_IMR4_M4_IMR4_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_M4_IMR4_M4_SHIFT))&GPC_IMR4_M4_IMR4_M4_MASK) +/* ISR1_A7 Bit Fields */ +#define GPC_ISR1_A7_ISR1_A7_MASK 0xFFFFFFFFu +#define GPC_ISR1_A7_ISR1_A7_SHIFT 0 +#define GPC_ISR1_A7_ISR1_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR1_A7_ISR1_A7_SHIFT))&GPC_ISR1_A7_ISR1_A7_MASK) +/* ISR2_A7 Bit Fields */ +#define GPC_ISR2_A7_ISR2_A7_MASK 0xFFFFFFFFu +#define GPC_ISR2_A7_ISR2_A7_SHIFT 0 +#define GPC_ISR2_A7_ISR2_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_A7_ISR2_A7_SHIFT))&GPC_ISR2_A7_ISR2_A7_MASK) +/* ISR3_A7 Bit Fields */ +#define GPC_ISR3_A7_ISR3_A7_MASK 0xFFFFFFFFu +#define GPC_ISR3_A7_ISR3_A7_SHIFT 0 +#define GPC_ISR3_A7_ISR3_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_A7_ISR3_A7_SHIFT))&GPC_ISR3_A7_ISR3_A7_MASK) +/* ISR4_A7 Bit Fields */ +#define GPC_ISR4_A7_ISR4_A7_MASK 0xFFFFFFFFu +#define GPC_ISR4_A7_ISR4_A7_SHIFT 0 +#define GPC_ISR4_A7_ISR4_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR4_A7_ISR4_A7_SHIFT))&GPC_ISR4_A7_ISR4_A7_MASK) +/* ISR1_M4 Bit Fields */ +#define GPC_ISR1_M4_ISR1_M4_MASK 0xFFFFFFFFu +#define GPC_ISR1_M4_ISR1_M4_SHIFT 0 +#define GPC_ISR1_M4_ISR1_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR1_M4_ISR1_M4_SHIFT))&GPC_ISR1_M4_ISR1_M4_MASK) +/* ISR2_M4 Bit Fields */ +#define GPC_ISR2_M4_ISR2_M4_MASK 0xFFFFFFFFu +#define GPC_ISR2_M4_ISR2_M4_SHIFT 0 +#define GPC_ISR2_M4_ISR2_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_M4_ISR2_M4_SHIFT))&GPC_ISR2_M4_ISR2_M4_MASK) +/* ISR3_M4 Bit Fields */ +#define GPC_ISR3_M4_ISR3_M4_MASK 0xFFFFFFFFu +#define GPC_ISR3_M4_ISR3_M4_SHIFT 0 +#define GPC_ISR3_M4_ISR3_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_M4_ISR3_M4_SHIFT))&GPC_ISR3_M4_ISR3_M4_MASK) +/* ISR4_M4 Bit Fields */ +#define GPC_ISR4_M4_ISR4_M4_MASK 0xFFFFFFFFu +#define GPC_ISR4_M4_ISR4_M4_SHIFT 0 +#define GPC_ISR4_M4_ISR4_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR4_M4_ISR4_M4_SHIFT))&GPC_ISR4_M4_ISR4_M4_MASK) +/* SLT_CFG Bit Fields */ +#define GPC_SLT_CFG_CORE0_A7_PDN_SLOT_CONTROL_MASK 0x1u +#define GPC_SLT_CFG_CORE0_A7_PDN_SLOT_CONTROL_SHIFT 0 +#define GPC_SLT_CFG_CORE0_A7_PUP_SLOT_CONTROL_MASK 0x2u +#define GPC_SLT_CFG_CORE0_A7_PUP_SLOT_CONTROL_SHIFT 1 +#define GPC_SLT_CFG_CORE1_A7_PDN_SLOT_CONTROL_MASK 0x4u +#define GPC_SLT_CFG_CORE1_A7_PDN_SLOT_CONTROL_SHIFT 2 +#define GPC_SLT_CFG_CORE1_A7_PUP_SLOT_CONTROL_MASK 0x8u +#define GPC_SLT_CFG_CORE1_A7_PUP_SLOT_CONTROL_SHIFT 3 +#define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_MASK 0x10u +#define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_SHIFT 4 +#define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_MASK 0x20u +#define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_SHIFT 5 +#define GPC_SLT_CFG_FASTMEGA_PDN_SLOT_CONTROL_MASK 0x40u +#define GPC_SLT_CFG_FASTMEGA_PDN_SLOT_CONTROL_SHIFT 6 +#define GPC_SLT_CFG_FASTMEGA_PUP_SLOT_CONTROL_MASK 0x80u +#define GPC_SLT_CFG_FASTMEGA_PUP_SLOT_CONTROL_SHIFT 7 +#define GPC_SLT_CFG_MIPI_PHY_PDN_SLOT_CONTROL_MASK 0x100u +#define GPC_SLT_CFG_MIPI_PHY_PDN_SLOT_CONTROL_SHIFT 8 +#define GPC_SLT_CFG_MIPI_PHY_PUP_SLOT_CONTROL_MASK 0x200u +#define GPC_SLT_CFG_MIPI_PHY_PUP_SLOT_CONTROL_SHIFT 9 +#define GPC_SLT_CFG_PCIE_PHY_PDN_SLOT_CONTROL_MASK 0x400u +#define GPC_SLT_CFG_PCIE_PHY_PDN_SLOT_CONTROL_SHIFT 10 +#define GPC_SLT_CFG_PCIE_PHY_PUP_SLOT_CONTROL_MASK 0x800u +#define GPC_SLT_CFG_PCIE_PHY_PUP_SLOT_CONTROL_SHIFT 11 +#define GPC_SLT_CFG_USB_OTG1_PDN_SLOT_CONTROL_MASK 0x1000u +#define GPC_SLT_CFG_USB_OTG1_PDN_SLOT_CONTROL_SHIFT 12 +#define GPC_SLT_CFG_USB_OTG1_PUP_SLOT_CONTROL_MASK 0x2000u +#define GPC_SLT_CFG_USB_OTG1_PUP_SLOT_CONTROL_SHIFT 13 +#define GPC_SLT_CFG_USB_OTG2_PDN_SLOT_CONTROL_MASK 0x4000u +#define GPC_SLT_CFG_USB_OTG2_PDN_SLOT_CONTROL_SHIFT 14 +#define GPC_SLT_CFG_USB_OTG2_PUP_SLOT_CONTROL_MASK 0x8000u +#define GPC_SLT_CFG_USB_OTG2_PUP_SLOT_CONTROL_SHIFT 15 +#define GPC_SLT_CFG_USB_HSIC_PDN_SLOT_CONTROL_MASK 0x10000u +#define GPC_SLT_CFG_USB_HSIC_PDN_SLOT_CONTROL_SHIFT 16 +#define GPC_SLT_CFG_USB_HSIC_PUP_SLOT_CONTROL_MASK 0x20000u +#define GPC_SLT_CFG_USB_HSIC_PUP_SLOT_CONTROL_SHIFT 17 +#define GPC_SLT_CFG_M4_VIRTUAL_PDN_SLOT_CONTROL_MASK 0x40000u +#define GPC_SLT_CFG_M4_VIRTUAL_PDN_SLOT_CONTROL_SHIFT 18 +#define GPC_SLT_CFG_M4_VIRTUAL_PUP_SLOT_CONTROL_MASK 0x80000u +#define GPC_SLT_CFG_M4_VIRTUAL_PUP_SLOT_CONTROL_SHIFT 19 +/* PGC_CPU_MAPPING Bit Fields */ +#define GPC_PGC_CPU_MAPPING_FASTMEGA_A7_DOMAIN_MASK 0x1u +#define GPC_PGC_CPU_MAPPING_FASTMEGA_A7_DOMAIN_SHIFT 0 +#define GPC_PGC_CPU_MAPPING_MIPI_PHY_A7_DOMAIN_MASK 0x4u +#define GPC_PGC_CPU_MAPPING_MIPI_PHY_A7_DOMAIN_SHIFT 2 +#define GPC_PGC_CPU_MAPPING_PCIE_PHY_A7_DOMAIN_MASK 0x8u +#define GPC_PGC_CPU_MAPPING_PCIE_PHY_A7_DOMAIN_SHIFT 3 +#define GPC_PGC_CPU_MAPPING_USB_OTG1_PHY_A7_DOMAIN_MASK 0x10u +#define GPC_PGC_CPU_MAPPING_USB_OTG1_PHY_A7_DOMAIN_SHIFT 4 +#define GPC_PGC_CPU_MAPPING_USB_OTG2_PHY_A7_DOMAIN_MASK 0x20u +#define GPC_PGC_CPU_MAPPING_USB_OTG2_PHY_A7_DOMAIN_SHIFT 5 +#define GPC_PGC_CPU_MAPPING_USB_HSIC_PHY_A7_DOMAIN_MASK 0x40u +#define GPC_PGC_CPU_MAPPING_USB_HSIC_PHY_A7_DOMAIN_SHIFT 6 +#define GPC_PGC_CPU_MAPPING_FASTMEGA_M4_DOMAIN_MASK 0x100u +#define GPC_PGC_CPU_MAPPING_FASTMEGA_M4_DOMAIN_SHIFT 8 +#define GPC_PGC_CPU_MAPPING_MIPI_PHY_M4_DOMAIN_MASK 0x400u +#define GPC_PGC_CPU_MAPPING_MIPI_PHY_M4_DOMAIN_SHIFT 10 +#define GPC_PGC_CPU_MAPPING_PCIE_PHY_M4_DOMAIN_MASK 0x800u +#define GPC_PGC_CPU_MAPPING_PCIE_PHY_M4_DOMAIN_SHIFT 11 +#define GPC_PGC_CPU_MAPPING_USB_OTG1_PHY_M4_DOMAIN_MASK 0x1000u +#define GPC_PGC_CPU_MAPPING_USB_OTG1_PHY_M4_DOMAIN_SHIFT 12 +#define GPC_PGC_CPU_MAPPING_USB_OTG2_PHY_M4_DOMAIN_MASK 0x2000u +#define GPC_PGC_CPU_MAPPING_USB_OTG2_PHY_M4_DOMAIN_SHIFT 13 +#define GPC_PGC_CPU_MAPPING_USB_HSIC_PHY_M4_DOMAIN_MASK 0x4000u +#define GPC_PGC_CPU_MAPPING_USB_HSIC_PHY_M4_DOMAIN_SHIFT 14 +/* CPU_PGC_SW_PUP_REQ Bit Fields */ +#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A7_SW_PUP_REQ_MASK 0x1u +#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A7_SW_PUP_REQ_SHIFT 0 +#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A7_SW_PUP_REQ_MASK 0x2u +#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A7_SW_PUP_REQ_SHIFT 1 +#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A7_SW_PUP_REQ_MASK 0x4u +#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A7_SW_PUP_REQ_SHIFT 2 +/* PU_PGC_SW_PUP_REQ Bit Fields */ +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY_SW_PUP_REQ_MASK 0x1u +#define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY_SW_PUP_REQ_SHIFT 0 +#define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_MASK 0x2u +#define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_SHIFT 1 +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_PHY_SW_PUP_REQ_MASK 0x4u +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_PHY_SW_PUP_REQ_SHIFT 2 +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_PHY_SW_PUP_REQ_MASK 0x8u +#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG2_PHY_SW_PUP_REQ_SHIFT 3 +#define GPC_PU_PGC_SW_PUP_REQ_USB_HSIC_PHY_SW_PUP_REQ_MASK 0x10u +#define GPC_PU_PGC_SW_PUP_REQ_USB_HSIC_PHY_SW_PUP_REQ_SHIFT 4 +/* CPU_PGC_SW_PDN_REQ Bit Fields */ +#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A7_SW_PDN_REQ_MASK 0x1u +#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A7_SW_PDN_REQ_SHIFT 0 +#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A7_SW_PDN_REQ_MASK 0x2u +#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A7_SW_PDN_REQ_SHIFT 1 +#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A7_SW_PDN_REQ_MASK 0x4u +#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A7_SW_PDN_REQ_SHIFT 2 +/* PU_PGC_SW_PDN_REQ Bit Fields */ +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY_SW_PDN_REQ_MASK 0x1u +#define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY_SW_PDN_REQ_SHIFT 0 +#define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_MASK 0x2u +#define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_SHIFT 1 +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_PHY_SW_PDN_REQ_MASK 0x4u +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_PHY_SW_PDN_REQ_SHIFT 2 +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_PHY_SW_PDN_REQ_MASK 0x8u +#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG2_PHY_SW_PDN_REQ_SHIFT 3 +#define GPC_PU_PGC_SW_PDN_REQ_USB_HSIC_PHY_SW_PDN_REQ_MASK 0x10u +#define GPC_PU_PGC_SW_PDN_REQ_USB_HSIC_PHY_SW_PDN_REQ_SHIFT 4 +/* LPS_A7 Bit Fields */ +#define GPC_LPS_A7_SRC_A7_CORES_SW_RESET_DONE0_MASK 0x1u +#define GPC_LPS_A7_SRC_A7_CORES_SW_RESET_DONE0_SHIFT 0 +#define GPC_LPS_A7_SRC_A7_CORES_SW_RESET_DONE1_MASK 0x2u +#define GPC_LPS_A7_SRC_A7_CORES_SW_RESET_DONE1_SHIFT 1 +#define GPC_LPS_A7_SRC_GPC_ARM_CPU0_RST_SYS_N_MASK 0x4u +#define GPC_LPS_A7_SRC_GPC_ARM_CPU0_RST_SYS_N_SHIFT 2 +#define GPC_LPS_A7_SRC_GPC_ARM_CPU1_RST_SYS_N_MASK 0x8u +#define GPC_LPS_A7_SRC_GPC_ARM_CPU1_RST_SYS_N_SHIFT 3 +#define GPC_LPS_A7_A7_START_ARM_RESET0_MASK 0x10u +#define GPC_LPS_A7_A7_START_ARM_RESET0_SHIFT 4 +#define GPC_LPS_A7_A7_START_ARM_RESET2_MASK 0x20u +#define GPC_LPS_A7_A7_START_ARM_RESET2_SHIFT 5 +#define GPC_LPS_A7_GPC_CA7_C0_ISO_MASK 0x40u +#define GPC_LPS_A7_GPC_CA7_C0_ISO_SHIFT 6 +#define GPC_LPS_A7_GPC_CA7_C1_ISO_MASK 0x80u +#define GPC_LPS_A7_GPC_CA7_C1_ISO_SHIFT 7 +#define GPC_LPS_A7_GPC_CA7_C0_SWITCH_B_MASK 0x100u +#define GPC_LPS_A7_GPC_CA7_C0_SWITCH_B_SHIFT 8 +#define GPC_LPS_A7_GPC_CA7_C1_SWITCH_B_MASK 0x200u +#define GPC_LPS_A7_GPC_CA7_C1_SWITCH_B_SHIFT 9 +#define GPC_LPS_A7_SRC_CA7_L2_RESET_N_MASK 0x400u +#define GPC_LPS_A7_SRC_CA7_L2_RESET_N_SHIFT 10 +#define GPC_LPS_A7_SRC_A7_PLATFORM_SW_RESET_DONE_MASK 0x800u +#define GPC_LPS_A7_SRC_A7_PLATFORM_SW_RESET_DONE_SHIFT 11 +#define GPC_LPS_A7_GPC_DAP_PUP_REQ_MASK 0x1000u +#define GPC_LPS_A7_GPC_DAP_PUP_REQ_SHIFT 12 +#define GPC_LPS_A7_START_SCU_RESET_MASK 0x2000u +#define GPC_LPS_A7_START_SCU_RESET_SHIFT 13 +#define GPC_LPS_A7_GPC_CA7_SCU_ISO_MASK 0x4000u +#define GPC_LPS_A7_GPC_CA7_SCU_ISO_SHIFT 14 +#define GPC_LPS_A7_GPC_CA7_SCU_SWITCH_B_MASK 0x8000u +#define GPC_LPS_A7_GPC_CA7_SCU_SWITCH_B_SHIFT 15 +#define GPC_LPS_A7_GPC_CA7_ACINACTM_MASK 0x10000u +#define GPC_LPS_A7_GPC_CA7_ACINACTM_SHIFT 16 +#define GPC_LPS_A7_GPC_CA7_L2RETENTION_MASK 0x20000u +#define GPC_LPS_A7_GPC_CA7_L2RETENTION_SHIFT 17 +#define GPC_LPS_A7_GPC_CA7_L2STDISABLE_MASK 0x40000u +#define GPC_LPS_A7_GPC_CA7_L2STDISABLE_SHIFT 18 +#define GPC_LPS_A7_GPC_CA7_L2_SWITCH_B_MASK 0x80000u +#define GPC_LPS_A7_GPC_CA7_L2_SWITCH_B_SHIFT 19 +#define GPC_LPS_A7_LPG_WAIT_MASK 0x1000000u +#define GPC_LPS_A7_LPG_WAIT_SHIFT 24 +#define GPC_LPS_A7_LPG_STOP_MASK 0x2000000u +#define GPC_LPS_A7_LPG_STOP_SHIFT 25 +#define GPC_LPS_A7_SHD_CURRENT_STATE_A7_MASK 0xC000000u +#define GPC_LPS_A7_SHD_CURRENT_STATE_A7_SHIFT 26 +#define GPC_LPS_A7_SHD_CURRENT_STATE_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_LPS_A7_SHD_CURRENT_STATE_A7_SHIFT))&GPC_LPS_A7_SHD_CURRENT_STATE_A7_MASK) +#define GPC_LPS_A7_LPM_CURRENT_STATE_A7_MASK 0x70000000u +#define GPC_LPS_A7_LPM_CURRENT_STATE_A7_SHIFT 28 +#define GPC_LPS_A7_LPM_CURRENT_STATE_A7(x) (((uint32_t)(((uint32_t)(x))<<GPC_LPS_A7_LPM_CURRENT_STATE_A7_SHIFT))&GPC_LPS_A7_LPM_CURRENT_STATE_A7_MASK) +/* LPS_M4 Bit Fields */ +#define GPC_LPS_M4_LOW_POWER_CTRL_M4_MASK 0x1u +#define GPC_LPS_M4_LOW_POWER_CTRL_M4_SHIFT 0 +#define GPC_LPS_M4_CM4_SLEEP_HOLD_ACK_B_MASK 0x2u +#define GPC_LPS_M4_CM4_SLEEP_HOLD_ACK_B_SHIFT 1 +#define GPC_LPS_M4_CM4_GATE_HCLK_MASK 0x4u +#define GPC_LPS_M4_CM4_GATE_HCLK_SHIFT 2 +#define GPC_LPS_M4_CM4_SLEEP_DEEP_MASK 0x8u +#define GPC_LPS_M4_CM4_SLEEP_DEEP_SHIFT 3 +#define GPC_LPS_M4_CM4_SLEEP_MASK 0x10u +#define GPC_LPS_M4_CM4_SLEEP_SHIFT 4 +#define GPC_LPS_M4_CM4_LOCKUP_MASK 0x20u +#define GPC_LPS_M4_CM4_LOCKUP_SHIFT 5 +#define GPC_LPS_M4_CM4_HALTED_MASK 0x40u +#define GPC_LPS_M4_CM4_HALTED_SHIFT 6 +#define GPC_LPS_M4_M4_PLATFORM_RESET_B_MASK 0x80u +#define GPC_LPS_M4_M4_PLATFORM_RESET_B_SHIFT 7 +#define GPC_LPS_M4_M4_CORE_RESET_B_MASK 0x100u +#define GPC_LPS_M4_M4_CORE_RESET_B_SHIFT 8 +#define GPC_LPS_M4_LPG_WAIT_MASK 0x1000000u +#define GPC_LPS_M4_LPG_WAIT_SHIFT 24 +#define GPC_LPS_M4_LPG_STOP_MASK 0x2000000u +#define GPC_LPS_M4_LPG_STOP_SHIFT 25 +#define GPC_LPS_M4_SHD_CURRENT_STATE_M4_MASK 0xC000000u +#define GPC_LPS_M4_SHD_CURRENT_STATE_M4_SHIFT 26 +#define GPC_LPS_M4_SHD_CURRENT_STATE_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_LPS_M4_SHD_CURRENT_STATE_M4_SHIFT))&GPC_LPS_M4_SHD_CURRENT_STATE_M4_MASK) +#define GPC_LPS_M4_LPM_CURRENT_STATE_M4_MASK 0x70000000u +#define GPC_LPS_M4_LPM_CURRENT_STATE_M4_SHIFT 28 +#define GPC_LPS_M4_LPM_CURRENT_STATE_M4(x) (((uint32_t)(((uint32_t)(x))<<GPC_LPS_M4_LPM_CURRENT_STATE_M4_SHIFT))&GPC_LPS_M4_LPM_CURRENT_STATE_M4_MASK) +/* GPC_GPR Bit Fields */ +#define GPC_GPC_GPR_A7_CORE_DBG_RST_MSK_PG_MASK 0x10000u +#define GPC_GPC_GPR_A7_CORE_DBG_RST_MSK_PG_SHIFT 16 +/* GTOR Bit Fields */ +#define GPC_GTOR_OBS_OUTPUT_0_SEL_MASK 0x1Fu +#define GPC_GTOR_OBS_OUTPUT_0_SEL_SHIFT 0 +#define GPC_GTOR_OBS_OUTPUT_0_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_GTOR_OBS_OUTPUT_0_SEL_SHIFT))&GPC_GTOR_OBS_OUTPUT_0_SEL_MASK) +#define GPC_GTOR_OBS_OUTPUT_1_SEL_MASK 0x1F00u +#define GPC_GTOR_OBS_OUTPUT_1_SEL_SHIFT 8 +#define GPC_GTOR_OBS_OUTPUT_1_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_GTOR_OBS_OUTPUT_1_SEL_SHIFT))&GPC_GTOR_OBS_OUTPUT_1_SEL_MASK) +#define GPC_GTOR_OBS_OUTPUT_2_SEL_MASK 0x1F0000u +#define GPC_GTOR_OBS_OUTPUT_2_SEL_SHIFT 16 +#define GPC_GTOR_OBS_OUTPUT_2_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_GTOR_OBS_OUTPUT_2_SEL_SHIFT))&GPC_GTOR_OBS_OUTPUT_2_SEL_MASK) +#define GPC_GTOR_OBS_EN_MASK 0x80000000u +#define GPC_GTOR_OBS_EN_SHIFT 31 +/* DEBUG_ADDR1 Bit Fields */ +#define GPC_DEBUG_ADDR1_GPC_INT_MASK 0x1u +#define GPC_DEBUG_ADDR1_GPC_INT_SHIFT 0 +#define GPC_DEBUG_ADDR1_WFI_A7_CORE0_MASK 0x10u +#define GPC_DEBUG_ADDR1_WFI_A7_CORE0_SHIFT 4 +#define GPC_DEBUG_ADDR1_WFI_A7_CORE1_MASK 0x20u +#define GPC_DEBUG_ADDR1_WFI_A7_CORE1_SHIFT 5 +#define GPC_DEBUG_ADDR1_WFI_A7_SCU_MASK 0x40u +#define GPC_DEBUG_ADDR1_WFI_A7_SCU_SHIFT 6 +#define GPC_DEBUG_ADDR1_WFI_M4_MASK 0x100u +#define GPC_DEBUG_ADDR1_WFI_M4_SHIFT 8 +#define GPC_DEBUG_ADDR1_nFIQ0_MASK 0x10000u +#define GPC_DEBUG_ADDR1_nFIQ0_SHIFT 16 +#define GPC_DEBUG_ADDR1_nFIQ1_MASK 0x20000u +#define GPC_DEBUG_ADDR1_nFIQ1_SHIFT 17 +#define GPC_DEBUG_ADDR1_nFIQ2_MASK 0x40000u +#define GPC_DEBUG_ADDR1_nFIQ2_SHIFT 18 +#define GPC_DEBUG_ADDR1_nFIQ3_MASK 0x80000u +#define GPC_DEBUG_ADDR1_nFIQ3_SHIFT 19 +#define GPC_DEBUG_ADDR1_nIRQ0_MASK 0x100000u +#define GPC_DEBUG_ADDR1_nIRQ0_SHIFT 20 +#define GPC_DEBUG_ADDR1_nIRQ1_MASK 0x200000u +#define GPC_DEBUG_ADDR1_nIRQ1_SHIFT 21 +#define GPC_DEBUG_ADDR1_nIRQ2_MASK 0x400000u +#define GPC_DEBUG_ADDR1_nIRQ2_SHIFT 22 +#define GPC_DEBUG_ADDR1_nIRQ3_MASK 0x800000u +#define GPC_DEBUG_ADDR1_nIRQ3_SHIFT 23 +/* DEBUG_ADDR2 Bit Fields */ +#define GPC_DEBUG_ADDR2_MIX_RESET_PENETRATED_MASK 0x1u +#define GPC_DEBUG_ADDR2_MIX_RESET_PENETRATED_SHIFT 0 +#define GPC_DEBUG_ADDR2_GPC_MIX_ISO_MASK 0x2u +#define GPC_DEBUG_ADDR2_GPC_MIX_ISO_SHIFT 1 +#define GPC_DEBUG_ADDR2_GPC_MIX_SWITCH_B_MASK 0x4u +#define GPC_DEBUG_ADDR2_GPC_MIX_SWITCH_B_SHIFT 2 +#define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_OUT0_MASK 0x8u +#define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_OUT0_SHIFT 3 +#define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_OUT1_MASK 0x10u +#define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_OUT1_SHIFT 4 +#define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_MASK 0x20u +#define GPC_DEBUG_ADDR2_GPC_MIX_SCALL_SHIFT 5 +#define GPC_DEBUG_ADDR2_GPC_MIX_RESET_B_MASK 0x40u +#define GPC_DEBUG_ADDR2_GPC_MIX_RESET_B_SHIFT 6 +#define GPC_DEBUG_ADDR2_SRC_EN_MIX_CLK_MASK 0x80u +#define GPC_DEBUG_ADDR2_SRC_EN_MIX_CLK_SHIFT 7 +#define GPC_DEBUG_ADDR2_GPC_MIX_RDY_MASK 0x100u +#define GPC_DEBUG_ADDR2_GPC_MIX_RDY_SHIFT 8 +#define GPC_DEBUG_ADDR2_PU_RESET_PENETRATED_MASK 0x1F000u +#define GPC_DEBUG_ADDR2_PU_RESET_PENETRATED_SHIFT 12 +#define GPC_DEBUG_ADDR2_PU_RESET_PENETRATED(x) (((uint32_t)(((uint32_t)(x))<<GPC_DEBUG_ADDR2_PU_RESET_PENETRATED_SHIFT))&GPC_DEBUG_ADDR2_PU_RESET_PENETRATED_MASK) +#define GPC_DEBUG_ADDR2_GPC_PU_ISO_MASK 0x3E0000u +#define GPC_DEBUG_ADDR2_GPC_PU_ISO_SHIFT 17 +#define GPC_DEBUG_ADDR2_GPC_PU_ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_DEBUG_ADDR2_GPC_PU_ISO_SHIFT))&GPC_DEBUG_ADDR2_GPC_PU_ISO_MASK) +#define GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B_MASK 0x7C00000u +#define GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B_SHIFT 22 +#define GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B(x) (((uint32_t)(((uint32_t)(x))<<GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B_SHIFT))&GPC_DEBUG_ADDR2_GPC_PU_SWITCH_B_MASK) +#define GPC_DEBUG_ADDR2_GPC_PU_RESET_B_MASK 0xF8000000u +#define GPC_DEBUG_ADDR2_GPC_PU_RESET_B_SHIFT 27 +#define GPC_DEBUG_ADDR2_GPC_PU_RESET_B(x) (((uint32_t)(((uint32_t)(x))<<GPC_DEBUG_ADDR2_GPC_PU_RESET_B_SHIFT))&GPC_DEBUG_ADDR2_GPC_PU_RESET_B_MASK) +/* CPU_PGC_PUP_STATUS1 Bit Fields */ +#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A7_PUP_STATUS_MASK 0x1u +#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A7_PUP_STATUS_SHIFT 0 +#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A7_PUP_STATUS_MASK 0x2u +#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A7_PUP_STATUS_SHIFT 1 +#define GPC_CPU_PGC_PUP_STATUS1_SCU_A7_PUP_STATUS_MASK 0x4u +#define GPC_CPU_PGC_PUP_STATUS1_SCU_A7_PUP_STATUS_SHIFT 2 +/* A7_PU_PGC_PUP_STATUS Bit Fields */ +#define GPC_A7_PU_PGC_PUP_STATUS_A7_MIPI_PHY_PGC_PUP_STATUS_MASK 0x1u +#define GPC_A7_PU_PGC_PUP_STATUS_A7_MIPI_PHY_PGC_PUP_STATUS_SHIFT 0 +#define GPC_A7_PU_PGC_PUP_STATUS_A7_PCIE_PHY_PGC_PUP_STATUS_MASK 0x2u +#define GPC_A7_PU_PGC_PUP_STATUS_A7_PCIE_PHY_PGC_PUP_STATUS_SHIFT 1 +#define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_OTG1_PHY_PGC_PUP_STATUS_MASK 0x4u +#define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_OTG1_PHY_PGC_PUP_STATUS_SHIFT 2 +#define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_OTG2_PHY_PGC_PUP_STATUS_MASK 0x8u +#define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_OTG2_PHY_PGC_PUP_STATUS_SHIFT 3 +#define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_HSIC_PHY_PGC_PUP_STATUS_MASK 0x10u +#define GPC_A7_PU_PGC_PUP_STATUS_A7_USB_HSIC_PHY_PGC_PUP_STATUS_SHIFT 4 +/* M4_PU_PGC_PUP_STATUS Bit Fields */ +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PHY_PGC_PUP_STATUS_MASK 0x1u +#define GPC_M4_PU_PGC_PUP_STATUS_M4_MIPI_PHY_PGC_PUP_STATUS_SHIFT 0 +#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PHY_PGC_PUP_STATUS_MASK 0x2u +#define GPC_M4_PU_PGC_PUP_STATUS_M4_PCIE_PHY_PGC_PUP_STATUS_SHIFT 1 +#define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_OTG1_PHY_PGC_PUP_STATUS_MASK 0x4u +#define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_OTG1_PHY_PGC_PUP_STATUS_SHIFT 2 +#define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_OTG2_PHY_PGC_PUP_STATUS_MASK 0x8u +#define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_OTG2_PHY_PGC_PUP_STATUS_SHIFT 3 +#define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_HSIC_PHY_PGC_PUP_STATUS_MASK 0x10u +#define GPC_M4_PU_PGC_PUP_STATUS_M4_USB_HSIC_PHY_PGC_PUP_STATUS_SHIFT 4 +/* CPU_PGC_PDN_STATUS1 Bit Fields */ +#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A7_PDN_STATUS_MASK 0x1u +#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A7_PDN_STATUS_SHIFT 0 +#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A7_PDN_STATUS_MASK 0x2u +#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A7_PDN_STATUS_SHIFT 1 +#define GPC_CPU_PGC_PDN_STATUS1_SCU_A7_PDN_STATUS_MASK 0x4u +#define GPC_CPU_PGC_PDN_STATUS1_SCU_A7_PDN_STATUS_SHIFT 2 +/* A7_PU_PGC_PDN_STATUS Bit Fields */ +#define GPC_A7_PU_PGC_PDN_STATUS_CORE0_A7_PDN_STATUS_MASK 0x1u +#define GPC_A7_PU_PGC_PDN_STATUS_CORE0_A7_PDN_STATUS_SHIFT 0 +#define GPC_A7_PU_PGC_PDN_STATUS_CORE1_A7_PDN_STATUS_MASK 0x2u +#define GPC_A7_PU_PGC_PDN_STATUS_CORE1_A7_PDN_STATUS_SHIFT 1 +#define GPC_A7_PU_PGC_PDN_STATUS_SCU_A7_PDN_STATUS_MASK 0x4u +#define GPC_A7_PU_PGC_PDN_STATUS_SCU_A7_PDN_STATUS_SHIFT 2 +/* M4_PU_PGC_PDN_STATUS Bit Fields */ +#define GPC_M4_PU_PGC_PDN_STATUS_A7_MIPI_PHY_PGC_PDN_STATUS_MASK 0x1u +#define GPC_M4_PU_PGC_PDN_STATUS_A7_MIPI_PHY_PGC_PDN_STATUS_SHIFT 0 +#define GPC_M4_PU_PGC_PDN_STATUS_A7_PCIE_PHY_PGC_PDN_STATUS_MASK 0x2u +#define GPC_M4_PU_PGC_PDN_STATUS_A7_PCIE_PHY_PGC_PDN_STATUS_SHIFT 1 +#define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_OTG1_PHY_PGC_PDN_STATUS_MASK 0x4u +#define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_OTG1_PHY_PGC_PDN_STATUS_SHIFT 2 +#define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_OTG2_PHY_PGC_PDN_STATUS_MASK 0x8u +#define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_OTG2_PHY_PGC_PDN_STATUS_SHIFT 3 +#define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_HSIC_PHY_PGC_PDN_STATUS_MASK 0x10u +#define GPC_M4_PU_PGC_PDN_STATUS_A7_USB_HSIC_PHY_PGC_PDN_STATUS_SHIFT 4 +/* A7_MIX_PDN_FLG Bit Fields */ +#define GPC_A7_MIX_PDN_FLG_A7_MIX_PDN_FLAG_MASK 0x1u +#define GPC_A7_MIX_PDN_FLG_A7_MIX_PDN_FLAG_SHIFT 0 +/* A7_PU_PDN_FLG Bit Fields */ +#define GPC_A7_PU_PDN_FLG_A7_MIPI_PHY_PGC_PDN_FLG_MASK 0x1u +#define GPC_A7_PU_PDN_FLG_A7_MIPI_PHY_PGC_PDN_FLG_SHIFT 0 +#define GPC_A7_PU_PDN_FLG_A7_PCIE_PHY_PGC_PDN_FLG_MASK 0x2u +#define GPC_A7_PU_PDN_FLG_A7_PCIE_PHY_PGC_PDN_FLG_SHIFT 1 +#define GPC_A7_PU_PDN_FLG_A7_USB_OTG1_PHY_PGC_PDN_FLG_MASK 0x4u +#define GPC_A7_PU_PDN_FLG_A7_USB_OTG1_PHY_PGC_PDN_FLG_SHIFT 2 +#define GPC_A7_PU_PDN_FLG_A7_USB_OTG2_PHY_PGC_PDN_FLG_MASK 0x8u +#define GPC_A7_PU_PDN_FLG_A7_USB_OTG2_PHY_PGC_PDN_FLG_SHIFT 3 +#define GPC_A7_PU_PDN_FLG_A7_USB_HSIC_PHY_PGC_PDN_FLG_MASK 0x10u +#define GPC_A7_PU_PDN_FLG_A7_USB_HSIC_PHY_PGC_PDN_FLG_SHIFT 4 +/* M4_MIX_PDN_FLG Bit Fields */ +#define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_MASK 0x1u +#define GPC_M4_MIX_PDN_FLG_M4_MIX_PDN_FLAG_SHIFT 0 +/* M4_PU_PDN_FLG Bit Fields */ +#define GPC_M4_PU_PDN_FLG_M4_MIPI_PHY_PGC_PDN_FLG_MASK 0x1u +#define GPC_M4_PU_PDN_FLG_M4_MIPI_PHY_PGC_PDN_FLG_SHIFT 0 +#define GPC_M4_PU_PDN_FLG_M4_PCIE_PHY_PGC_PDN_FLG_MASK 0x2u +#define GPC_M4_PU_PDN_FLG_M4_PCIE_PHY_PGC_PDN_FLG_SHIFT 1 +#define GPC_M4_PU_PDN_FLG_M4_USB_OTG1_PHY_PGC_PDN_FLG_MASK 0x4u +#define GPC_M4_PU_PDN_FLG_M4_USB_OTG1_PHY_PGC_PDN_FLG_SHIFT 2 +#define GPC_M4_PU_PDN_FLG_M4_USB_OTG2_PHY_PGC_PDN_FLG_MASK 0x8u +#define GPC_M4_PU_PDN_FLG_M4_USB_OTG2_PHY_PGC_PDN_FLG_SHIFT 3 +#define GPC_M4_PU_PDN_FLG_M4_USB_HSIC_PHY_PGC_PDN_FLG_MASK 0x10u +#define GPC_M4_PU_PDN_FLG_M4_USB_HSIC_PHY_PGC_PDN_FLG_SHIFT 4 /*! * @} */ /* end of group GPC_Register_Masks */ - /* GPC - Peripheral instance base addresses */ /** Peripheral GPC base address */ #define GPC_BASE (0x303A0000u) /** Peripheral GPC base pointer */ #define GPC ((GPC_Type *)GPC_BASE) #define GPC_BASE_PTR (GPC) -/** Array initializer of GPC peripheral base adresses */ +/** Array initializer of GPC peripheral base addresses */ #define GPC_BASE_ADDRS { GPC_BASE } /** Array initializer of GPC peripheral base pointers */ #define GPC_BASE_PTRS { GPC } - +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } /* ---------------------------------------------------------------------------- -- GPC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -70011,20 +19038,79 @@ typedef struct { /* GPC - Register instance definitions */ /* GPC */ -#define GPC_CNTR GPC_CNTR_REG(GPC_BASE_PTR) -#define GPC_PGR GPC_PGR_REG(GPC_BASE_PTR) -#define GPC_IMR1 GPC_IMR1_REG(GPC_BASE_PTR) -#define GPC_IMR2 GPC_IMR2_REG(GPC_BASE_PTR) -#define GPC_IMR3 GPC_IMR3_REG(GPC_BASE_PTR) -#define GPC_IMR4 GPC_IMR4_REG(GPC_BASE_PTR) -#define GPC_ISR1 GPC_ISR1_REG(GPC_BASE_PTR) -#define GPC_ISR2 GPC_ISR2_REG(GPC_BASE_PTR) -#define GPC_ISR3 GPC_ISR3_REG(GPC_BASE_PTR) -#define GPC_ISR4 GPC_ISR4_REG(GPC_BASE_PTR) -#define GPC_A9_LPSR GPC_A9_LPSR_REG(GPC_BASE_PTR) -#define GPC_M4_LPSR GPC_M4_LPSR_REG(GPC_BASE_PTR) -#define GPC_DR GPC_DR_REG(GPC_BASE_PTR) - +#define GPC_LPCR_A7_BSC GPC_LPCR_A7_BSC_REG(GPC_BASE_PTR) +#define GPC_LPCR_A7_AD GPC_LPCR_A7_AD_REG(GPC_BASE_PTR) +#define GPC_LPCR_M4 GPC_LPCR_M4_REG(GPC_BASE_PTR) +#define GPC_SLPCR GPC_SLPCR_REG(GPC_BASE_PTR) +#define GPC_MLPCR GPC_MLPCR_REG(GPC_BASE_PTR) +#define GPC_PGC_ACK_SEL_A7 GPC_PGC_ACK_SEL_A7_REG(GPC_BASE_PTR) +#define GPC_PGC_ACK_SEL_M4 GPC_PGC_ACK_SEL_M4_REG(GPC_BASE_PTR) +#define GPC_MISC GPC_MISC_REG(GPC_BASE_PTR) +#define GPC_IMR1_CORE0_A7 GPC_IMR1_CORE0_A7_REG(GPC_BASE_PTR) +#define GPC_IMR2_CORE0_A7 GPC_IMR2_CORE0_A7_REG(GPC_BASE_PTR) +#define GPC_IMR3_CORE0_A7 GPC_IMR3_CORE0_A7_REG(GPC_BASE_PTR) +#define GPC_IMR4_CORE0_A7 GPC_IMR4_CORE0_A7_REG(GPC_BASE_PTR) +#define GPC_IMR1_CORE1_A7 GPC_IMR1_CORE1_A7_REG(GPC_BASE_PTR) +#define GPC_IMR2_CORE1_A7 GPC_IMR2_CORE1_A7_REG(GPC_BASE_PTR) +#define GPC_IMR3_CORE1_A7 GPC_IMR3_CORE1_A7_REG(GPC_BASE_PTR) +#define GPC_IMR4_CORE1_A7 GPC_IMR4_CORE1_A7_REG(GPC_BASE_PTR) +#define GPC_IMR1_M4 GPC_IMR1_M4_REG(GPC_BASE_PTR) +#define GPC_IMR2_M4 GPC_IMR2_M4_REG(GPC_BASE_PTR) +#define GPC_IMR3_M4 GPC_IMR3_M4_REG(GPC_BASE_PTR) +#define GPC_IMR4_M4 GPC_IMR4_M4_REG(GPC_BASE_PTR) +#define GPC_ISR1_A7 GPC_ISR1_A7_REG(GPC_BASE_PTR) +#define GPC_ISR2_A7 GPC_ISR2_A7_REG(GPC_BASE_PTR) +#define GPC_ISR3_A7 GPC_ISR3_A7_REG(GPC_BASE_PTR) +#define GPC_ISR4_A7 GPC_ISR4_A7_REG(GPC_BASE_PTR) +#define GPC_ISR1_M4 GPC_ISR1_M4_REG(GPC_BASE_PTR) +#define GPC_ISR2_M4 GPC_ISR2_M4_REG(GPC_BASE_PTR) +#define GPC_ISR3_M4 GPC_ISR3_M4_REG(GPC_BASE_PTR) +#define GPC_ISR4_M4 GPC_ISR4_M4_REG(GPC_BASE_PTR) +#define GPC_SLT0_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,0) +#define GPC_SLT1_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,1) +#define GPC_SLT2_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,2) +#define GPC_SLT3_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,3) +#define GPC_SLT4_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,4) +#define GPC_SLT5_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,5) +#define GPC_SLT6_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,6) +#define GPC_SLT7_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,7) +#define GPC_SLT8_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,8) +#define GPC_SLT9_CFG GPC_SLT_CFG_REG(GPC_BASE_PTR,9) +#define GPC_PGC_CPU_MAPPING GPC_PGC_CPU_MAPPING_REG(GPC_BASE_PTR) +#define GPC_CPU_PGC_SW_PUP_REQ GPC_CPU_PGC_SW_PUP_REQ_REG(GPC_BASE_PTR) +#define GPC_PU_PGC_SW_PUP_REQ GPC_PU_PGC_SW_PUP_REQ_REG(GPC_BASE_PTR) +#define GPC_CPU_PGC_SW_PDN_REQ GPC_CPU_PGC_SW_PDN_REQ_REG(GPC_BASE_PTR) +#define GPC_PU_PGC_SW_PDN_REQ GPC_PU_PGC_SW_PDN_REQ_REG(GPC_BASE_PTR) +#define GPC_LPS_A7 GPC_LPS_A7_REG(GPC_BASE_PTR) +#define GPC_LPS_M4 GPC_LPS_M4_REG(GPC_BASE_PTR) +#define GPC_GPC_GPR GPC_GPC_GPR_REG(GPC_BASE_PTR) +#define GPC_GTOR GPC_GTOR_REG(GPC_BASE_PTR) +#define GPC_DEBUG_ADDR1 GPC_DEBUG_ADDR1_REG(GPC_BASE_PTR) +#define GPC_DEBUG_ADDR2 GPC_DEBUG_ADDR2_REG(GPC_BASE_PTR) +#define GPC_CPU_PGC_PUP_STATUS1 GPC_CPU_PGC_PUP_STATUS1_REG(GPC_BASE_PTR) +#define GPC_A7_PU_PGC_PUP_STATUS0 GPC_A7_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,0) +#define GPC_A7_PU_PGC_PUP_STATUS1 GPC_A7_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,1) +#define GPC_A7_PU_PGC_PUP_STATUS2 GPC_A7_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,2) +#define GPC_M4_PU_PGC_PUP_STATUS0 GPC_M4_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,0) +#define GPC_M4_PU_PGC_PUP_STATUS1 GPC_M4_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,1) +#define GPC_M4_PU_PGC_PUP_STATUS2 GPC_M4_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,2) +#define GPC_CPU_PGC_PDN_STATUS1 GPC_CPU_PGC_PDN_STATUS1_REG(GPC_BASE_PTR) +#define GPC_A7_PU_PGC_PDN_STATUS0 GPC_A7_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,0) +#define GPC_A7_PU_PGC_PDN_STATUS1 GPC_A7_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,1) +#define GPC_A7_PU_PGC_PDN_STATUS2 GPC_A7_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,2) +#define GPC_M4_PU_PGC_PDN_STATUS0 GPC_M4_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,0) +#define GPC_M4_PU_PGC_PDN_STATUS1 GPC_M4_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,1) +#define GPC_M4_PU_PGC_PDN_STATUS2 GPC_M4_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,2) +#define GPC_A7_MIX_PDN_FLG GPC_A7_MIX_PDN_FLG_REG(GPC_BASE_PTR) +#define GPC_A7_PU_PDN_FLG GPC_A7_PU_PDN_FLG_REG(GPC_BASE_PTR) +#define GPC_M4_MIX_PDN_FLG GPC_M4_MIX_PDN_FLG_REG(GPC_BASE_PTR) +#define GPC_M4_PU_PDN_FLG GPC_M4_PU_PDN_FLG_REG(GPC_BASE_PTR) +/* GPC - Register array accessors */ +#define GPC_SLT_CFG(index) GPC_SLT_CFG_REG(GPC_BASE_PTR,index) +#define GPC_A7_PU_PGC_PUP_STATUS(index) GPC_A7_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,index) +#define GPC_M4_PU_PGC_PUP_STATUS(index) GPC_M4_PU_PGC_PUP_STATUS_REG(GPC_BASE_PTR,index) +#define GPC_A7_PU_PGC_PDN_STATUS(index) GPC_A7_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,index) +#define GPC_M4_PU_PGC_PDN_STATUS(index) GPC_M4_PU_PGC_PDN_STATUS_REG(GPC_BASE_PTR,index) /*! * @} */ /* end of group GPC_Register_Accessor_Macros */ @@ -70034,6 +19120,592 @@ typedef struct { * @} */ /* end of group GPC_Peripheral */ +/* ---------------------------------------------------------------------------- + -- GPC_PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer + * @{ + */ + +/** GPC_PGC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t A7CORE0_CTRL; /**< GPC PGC Control Register, offset: 0x800 */ + __IO uint32_t A7CORE0_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x804 */ + __IO uint32_t A7CORE0_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x808 */ + __IO uint32_t A7CORE0_SR; /**< GPC PGC Status Register, offset: 0x80C */ + uint8_t RESERVED_1[48]; + __IO uint32_t A7CORE1_CTRL; /**< GPC PGC Control Register, offset: 0x840 */ + __IO uint32_t A7CORE1_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x844 */ + __IO uint32_t A7CORE1_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x848 */ + __IO uint32_t A7CORE1_SR; /**< GPC PGC Status Register, offset: 0x84C */ + uint8_t RESERVED_2[48]; + __IO uint32_t A7SCU_CTRL; /**< GPC PGC Control Register, offset: 0x880 */ + __IO uint32_t A7SCU_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x884 */ + __IO uint32_t A7SCU_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x888 */ + __IO uint32_t A7SCU_SR; /**< GPC PGC Status Register, offset: 0x88C */ + __IO uint32_t SCU_AUXSW; /**< GPC PGC Auxiliary Power Switch SCU Control Register, offset: 0x890 */ + uint8_t RESERVED_3[364]; + __IO uint32_t MIX_CTRL; /**< GPC PGC Control Register, offset: 0xA00 */ + __IO uint32_t MIX_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xA04 */ + __IO uint32_t MIX_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xA08 */ + __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0xA0C */ + uint8_t RESERVED_4[496]; + __IO uint32_t MIPI_CTRL; /**< GPC PGC Control Register, offset: 0xC00 */ + __IO uint32_t MIPI_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xC04 */ + __IO uint32_t MIPI_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xC08 */ + __IO uint32_t MIPI_SR; /**< GPC PGC Status Register, offset: 0xC0C */ + __IO uint32_t MIPI_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0xC10 */ + uint8_t RESERVED_5[44]; + __IO uint32_t PCIE_CTRL; /**< GPC PGC Control Register, offset: 0xC40 */ + __IO uint32_t PCIE_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xC44 */ + __IO uint32_t PCIE_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xC48 */ + __IO uint32_t PCIE_SR; /**< GPC PGC Status Register, offset: 0xC4C */ + __IO uint32_t PCIE_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0xC50 */ + uint8_t RESERVED_6[172]; + __IO uint32_t HSIC_CTRL; /**< GPC PGC Control Register, offset: 0xD00 */ + __IO uint32_t HSIC_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xD04 */ + __IO uint32_t HSIC_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xD08 */ + __IO uint32_t HSIC_SR; /**< GPC PGC Status Register, offset: 0xD0C */ +} GPC_PGC_Type, *GPC_PGC_MemMapPtr; +/* ---------------------------------------------------------------------------- + -- GPC_PGC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_PGC_Register_Accessor_Macros GPC_PGC - Register accessor macros + * @{ + */ + + +/* GPC_PGC - Register accessors */ +#define GPC_PGC_A7CORE0_CTRL_REG(base) ((base)->A7CORE0_CTRL) +#define GPC_PGC_A7CORE0_PUPSCR_REG(base) ((base)->A7CORE0_PUPSCR) +#define GPC_PGC_A7CORE0_PDNSCR_REG(base) ((base)->A7CORE0_PDNSCR) +#define GPC_PGC_A7CORE0_SR_REG(base) ((base)->A7CORE0_SR) +#define GPC_PGC_A7CORE1_CTRL_REG(base) ((base)->A7CORE1_CTRL) +#define GPC_PGC_A7CORE1_PUPSCR_REG(base) ((base)->A7CORE1_PUPSCR) +#define GPC_PGC_A7CORE1_PDNSCR_REG(base) ((base)->A7CORE1_PDNSCR) +#define GPC_PGC_A7CORE1_SR_REG(base) ((base)->A7CORE1_SR) +#define GPC_PGC_A7SCU_CTRL_REG(base) ((base)->A7SCU_CTRL) +#define GPC_PGC_A7SCU_PUPSCR_REG(base) ((base)->A7SCU_PUPSCR) +#define GPC_PGC_A7SCU_PDNSCR_REG(base) ((base)->A7SCU_PDNSCR) +#define GPC_PGC_A7SCU_SR_REG(base) ((base)->A7SCU_SR) +#define GPC_PGC_SCU_AUXSW_REG(base) ((base)->SCU_AUXSW) +#define GPC_PGC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) +#define GPC_PGC_MIX_PUPSCR_REG(base) ((base)->MIX_PUPSCR) +#define GPC_PGC_MIX_PDNSCR_REG(base) ((base)->MIX_PDNSCR) +#define GPC_PGC_MIX_SR_REG(base) ((base)->MIX_SR) +#define GPC_PGC_MIPI_CTRL_REG(base) ((base)->MIPI_CTRL) +#define GPC_PGC_MIPI_PUPSCR_REG(base) ((base)->MIPI_PUPSCR) +#define GPC_PGC_MIPI_PDNSCR_REG(base) ((base)->MIPI_PDNSCR) +#define GPC_PGC_MIPI_SR_REG(base) ((base)->MIPI_SR) +#define GPC_PGC_MIPI_AUXSW_REG(base) ((base)->MIPI_AUXSW) +#define GPC_PGC_PCIE_CTRL_REG(base) ((base)->PCIE_CTRL) +#define GPC_PGC_PCIE_PUPSCR_REG(base) ((base)->PCIE_PUPSCR) +#define GPC_PGC_PCIE_PDNSCR_REG(base) ((base)->PCIE_PDNSCR) +#define GPC_PGC_PCIE_SR_REG(base) ((base)->PCIE_SR) +#define GPC_PGC_PCIE_AUXSW_REG(base) ((base)->PCIE_AUXSW) +#define GPC_PGC_HSIC_CTRL_REG(base) ((base)->HSIC_CTRL) +#define GPC_PGC_HSIC_PUPSCR_REG(base) ((base)->HSIC_PUPSCR) +#define GPC_PGC_HSIC_PDNSCR_REG(base) ((base)->HSIC_PDNSCR) +#define GPC_PGC_HSIC_SR_REG(base) ((base)->HSIC_SR) + +/*! + * @} + */ /* end of group GPC_PGC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPC_PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks + * @{ + */ + +/* A7CORE0_CTRL Bit Fields */ +#define GPC_PGC_A7CORE0_CTRL_PCR_MASK 0x1u +#define GPC_PGC_A7CORE0_CTRL_PCR_SHIFT 0 +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_A7CORE0_CTRL_L2RSTDIS_MASK) +#define GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1_MASK 0x3F00u +#define GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1_SHIFT 8 +#define GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_A7CORE0_CTRL_DFTRAM_TCD1_MASK) +#define GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u +#define GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT 16 +#define GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_A7CORE0_CTRL_L2RETN_TCD1_TDR_MASK) +#define GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u +#define GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24 +#define GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_A7CORE0_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/* A7CORE0_PUPSCR Bit Fields */ +#define GPC_PGC_A7CORE0_PUPSCR_SW_MASK 0x3Fu +#define GPC_PGC_A7CORE0_PUPSCR_SW_SHIFT 0 +#define GPC_PGC_A7CORE0_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PUPSCR_SW_SHIFT))&GPC_PGC_A7CORE0_PUPSCR_SW_MASK) +#define GPC_PGC_A7CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u +#define GPC_PGC_A7CORE0_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6 +#define GPC_PGC_A7CORE0_PUPSCR_SW2ISO_MASK 0x7FFF80u +#define GPC_PGC_A7CORE0_PUPSCR_SW2ISO_SHIFT 7 +#define GPC_PGC_A7CORE0_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_A7CORE0_PUPSCR_SW2ISO_MASK) +#define GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u +#define GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23 +#define GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7CORE0_PUPSCR_PUP_SCALLOUT_CNT_MASK) +/* A7CORE0_PDNSCR Bit Fields */ +#define GPC_PGC_A7CORE0_PDNSCR_ISO_MASK 0x3Fu +#define GPC_PGC_A7CORE0_PDNSCR_ISO_SHIFT 0 +#define GPC_PGC_A7CORE0_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PDNSCR_ISO_SHIFT))&GPC_PGC_A7CORE0_PDNSCR_ISO_MASK) +#define GPC_PGC_A7CORE0_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u +#define GPC_PGC_A7CORE0_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7 +#define GPC_PGC_A7CORE0_PDNSCR_ISO2SW_MASK 0x3F00u +#define GPC_PGC_A7CORE0_PDNSCR_ISO2SW_SHIFT 8 +#define GPC_PGC_A7CORE0_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_A7CORE0_PDNSCR_ISO2SW_MASK) +#define GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u +#define GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16 +#define GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7CORE0_PDNSCR_PUP_SCALLOUT_CNT_MASK) +#define GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u +#define GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24 +#define GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_A7CORE0_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/* A7CORE0_SR Bit Fields */ +#define GPC_PGC_A7CORE0_SR_PSR_MASK 0x1u +#define GPC_PGC_A7CORE0_SR_PSR_SHIFT 0 +#define GPC_PGC_A7CORE0_SR_L2RETN_FLAG_MASK 0x2u +#define GPC_PGC_A7CORE0_SR_L2RETN_FLAG_SHIFT 1 +#define GPC_PGC_A7CORE0_SR_ALLOFF_FLAG_MASK 0x4u +#define GPC_PGC_A7CORE0_SR_ALLOFF_FLAG_SHIFT 2 +#define GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL_MASK 0x78u +#define GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL_SHIFT 3 +#define GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_A7CORE0_SR_PUP_CLK_DIV_SEL_MASK) +#define GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u +#define GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8 +#define GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_A7CORE0_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/* A7CORE1_CTRL Bit Fields */ +#define GPC_PGC_A7CORE1_CTRL_PCR_MASK 0x1u +#define GPC_PGC_A7CORE1_CTRL_PCR_SHIFT 0 +#define GPC_PGC_A7CORE1_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_A7CORE1_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_A7CORE1_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_A7CORE1_CTRL_L2RSTDIS_MASK) +#define GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1_MASK 0x3F00u +#define GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1_SHIFT 8 +#define GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_A7CORE1_CTRL_DFTRAM_TCD1_MASK) +#define GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u +#define GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT 16 +#define GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_A7CORE1_CTRL_L2RETN_TCD1_TDR_MASK) +#define GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u +#define GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24 +#define GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_A7CORE1_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/* A7CORE1_PUPSCR Bit Fields */ +#define GPC_PGC_A7CORE1_PUPSCR_SW_MASK 0x3Fu +#define GPC_PGC_A7CORE1_PUPSCR_SW_SHIFT 0 +#define GPC_PGC_A7CORE1_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PUPSCR_SW_SHIFT))&GPC_PGC_A7CORE1_PUPSCR_SW_MASK) +#define GPC_PGC_A7CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u +#define GPC_PGC_A7CORE1_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6 +#define GPC_PGC_A7CORE1_PUPSCR_SW2ISO_MASK 0x7FFF80u +#define GPC_PGC_A7CORE1_PUPSCR_SW2ISO_SHIFT 7 +#define GPC_PGC_A7CORE1_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_A7CORE1_PUPSCR_SW2ISO_MASK) +#define GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u +#define GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23 +#define GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7CORE1_PUPSCR_PUP_SCALLOUT_CNT_MASK) +/* A7CORE1_PDNSCR Bit Fields */ +#define GPC_PGC_A7CORE1_PDNSCR_ISO_MASK 0x3Fu +#define GPC_PGC_A7CORE1_PDNSCR_ISO_SHIFT 0 +#define GPC_PGC_A7CORE1_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PDNSCR_ISO_SHIFT))&GPC_PGC_A7CORE1_PDNSCR_ISO_MASK) +#define GPC_PGC_A7CORE1_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u +#define GPC_PGC_A7CORE1_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7 +#define GPC_PGC_A7CORE1_PDNSCR_ISO2SW_MASK 0x3F00u +#define GPC_PGC_A7CORE1_PDNSCR_ISO2SW_SHIFT 8 +#define GPC_PGC_A7CORE1_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_A7CORE1_PDNSCR_ISO2SW_MASK) +#define GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u +#define GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16 +#define GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7CORE1_PDNSCR_PUP_SCALLOUT_CNT_MASK) +#define GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u +#define GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24 +#define GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_A7CORE1_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/* A7CORE1_SR Bit Fields */ +#define GPC_PGC_A7CORE1_SR_PSR_MASK 0x1u +#define GPC_PGC_A7CORE1_SR_PSR_SHIFT 0 +#define GPC_PGC_A7CORE1_SR_L2RETN_FLAG_MASK 0x2u +#define GPC_PGC_A7CORE1_SR_L2RETN_FLAG_SHIFT 1 +#define GPC_PGC_A7CORE1_SR_ALLOFF_FLAG_MASK 0x4u +#define GPC_PGC_A7CORE1_SR_ALLOFF_FLAG_SHIFT 2 +#define GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL_MASK 0x78u +#define GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL_SHIFT 3 +#define GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_A7CORE1_SR_PUP_CLK_DIV_SEL_MASK) +#define GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u +#define GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8 +#define GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_A7CORE1_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/* A7SCU_CTRL Bit Fields */ +#define GPC_PGC_A7SCU_CTRL_PCR_MASK 0x1u +#define GPC_PGC_A7SCU_CTRL_PCR_SHIFT 0 +#define GPC_PGC_A7SCU_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_A7SCU_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_A7SCU_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_A7SCU_CTRL_L2RSTDIS_MASK) +#define GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1_MASK 0x3F00u +#define GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1_SHIFT 8 +#define GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_A7SCU_CTRL_DFTRAM_TCD1_MASK) +#define GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u +#define GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR_SHIFT 16 +#define GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_A7SCU_CTRL_L2RETN_TCD1_TDR_MASK) +#define GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u +#define GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24 +#define GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_A7SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/* A7SCU_PUPSCR Bit Fields */ +#define GPC_PGC_A7SCU_PUPSCR_SW_MASK 0x3Fu +#define GPC_PGC_A7SCU_PUPSCR_SW_SHIFT 0 +#define GPC_PGC_A7SCU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PUPSCR_SW_SHIFT))&GPC_PGC_A7SCU_PUPSCR_SW_MASK) +#define GPC_PGC_A7SCU_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u +#define GPC_PGC_A7SCU_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6 +#define GPC_PGC_A7SCU_PUPSCR_SW2ISO_MASK 0x7FFF80u +#define GPC_PGC_A7SCU_PUPSCR_SW2ISO_SHIFT 7 +#define GPC_PGC_A7SCU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_A7SCU_PUPSCR_SW2ISO_MASK) +#define GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u +#define GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23 +#define GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7SCU_PUPSCR_PUP_SCALLOUT_CNT_MASK) +/* A7SCU_PDNSCR Bit Fields */ +#define GPC_PGC_A7SCU_PDNSCR_ISO_MASK 0x3Fu +#define GPC_PGC_A7SCU_PDNSCR_ISO_SHIFT 0 +#define GPC_PGC_A7SCU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PDNSCR_ISO_SHIFT))&GPC_PGC_A7SCU_PDNSCR_ISO_MASK) +#define GPC_PGC_A7SCU_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u +#define GPC_PGC_A7SCU_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7 +#define GPC_PGC_A7SCU_PDNSCR_ISO2SW_MASK 0x3F00u +#define GPC_PGC_A7SCU_PDNSCR_ISO2SW_SHIFT 8 +#define GPC_PGC_A7SCU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_A7SCU_PDNSCR_ISO2SW_MASK) +#define GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u +#define GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16 +#define GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_A7SCU_PDNSCR_PUP_SCALLOUT_CNT_MASK) +#define GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u +#define GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24 +#define GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_A7SCU_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/* A7SCU_SR Bit Fields */ +#define GPC_PGC_A7SCU_SR_PSR_MASK 0x1u +#define GPC_PGC_A7SCU_SR_PSR_SHIFT 0 +#define GPC_PGC_A7SCU_SR_L2RETN_FLAG_MASK 0x2u +#define GPC_PGC_A7SCU_SR_L2RETN_FLAG_SHIFT 1 +#define GPC_PGC_A7SCU_SR_ALLOFF_FLAG_MASK 0x4u +#define GPC_PGC_A7SCU_SR_ALLOFF_FLAG_SHIFT 2 +#define GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL_MASK 0x78u +#define GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL_SHIFT 3 +#define GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_A7SCU_SR_PUP_CLK_DIV_SEL_MASK) +#define GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u +#define GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8 +#define GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_A7SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/* SCU_AUXSW Bit Fields */ +#define GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_MASK 0x3FFu +#define GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_SHIFT 0 +#define GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_SHIFT))&GPC_PGC_SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_MASK) +#define GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR_MASK 0xFFC00u +#define GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR_SHIFT 10 +#define GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR_SHIFT))&GPC_PGC_SCU_AUXSW_L2RETN_TRC1_TMC_TMR_MASK) +#define GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC_MASK 0x3FF00000u +#define GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC_SHIFT 20 +#define GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC_SHIFT))&GPC_PGC_SCU_AUXSW_MEMPWR_TRC1_TMC_MASK) +/* MIX_CTRL Bit Fields */ +#define GPC_PGC_MIX_CTRL_PCR_MASK 0x1u +#define GPC_PGC_MIX_CTRL_PCR_SHIFT 0 +#define GPC_PGC_MIX_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_MIX_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_MIX_CTRL_L2RSTDIS_MASK) +#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK 0x3F00u +#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT 8 +#define GPC_PGC_MIX_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_MIX_CTRL_DFTRAM_TCD1_MASK) +#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u +#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT 16 +#define GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_MIX_CTRL_L2RETN_TCD1_TDR_MASK) +#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u +#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24 +#define GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/* MIX_PUPSCR Bit Fields */ +#define GPC_PGC_MIX_PUPSCR_SW_MASK 0x3Fu +#define GPC_PGC_MIX_PUPSCR_SW_SHIFT 0 +#define GPC_PGC_MIX_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PUPSCR_SW_SHIFT))&GPC_PGC_MIX_PUPSCR_SW_MASK) +#define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u +#define GPC_PGC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6 +#define GPC_PGC_MIX_PUPSCR_SW2ISO_MASK 0x7FFF80u +#define GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT 7 +#define GPC_PGC_MIX_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_MIX_PUPSCR_SW2ISO_MASK) +#define GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u +#define GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23 +#define GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_MIX_PUPSCR_PUP_SCALLOUT_CNT_MASK) +/* MIX_PDNSCR Bit Fields */ +#define GPC_PGC_MIX_PDNSCR_ISO_MASK 0x3Fu +#define GPC_PGC_MIX_PDNSCR_ISO_SHIFT 0 +#define GPC_PGC_MIX_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PDNSCR_ISO_SHIFT))&GPC_PGC_MIX_PDNSCR_ISO_MASK) +#define GPC_PGC_MIX_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u +#define GPC_PGC_MIX_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7 +#define GPC_PGC_MIX_PDNSCR_ISO2SW_MASK 0x3F00u +#define GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT 8 +#define GPC_PGC_MIX_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_MIX_PDNSCR_ISO2SW_MASK) +#define GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u +#define GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16 +#define GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_MIX_PDNSCR_PUP_SCALLOUT_CNT_MASK) +#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u +#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24 +#define GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_MIX_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/* MIX_SR Bit Fields */ +#define GPC_PGC_MIX_SR_PSR_MASK 0x1u +#define GPC_PGC_MIX_SR_PSR_SHIFT 0 +#define GPC_PGC_MIX_SR_L2RETN_FLAG_MASK 0x2u +#define GPC_PGC_MIX_SR_L2RETN_FLAG_SHIFT 1 +#define GPC_PGC_MIX_SR_ALLOFF_FLAG_MASK 0x4u +#define GPC_PGC_MIX_SR_ALLOFF_FLAG_SHIFT 2 +#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK 0x78u +#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT 3 +#define GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_MIX_SR_PUP_CLK_DIV_SEL_MASK) +#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u +#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8 +#define GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/* MIPI_CTRL Bit Fields */ +#define GPC_PGC_MIPI_CTRL_PCR_MASK 0x1u +#define GPC_PGC_MIPI_CTRL_PCR_SHIFT 0 +#define GPC_PGC_MIPI_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_MIPI_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_MIPI_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_MIPI_CTRL_L2RSTDIS_MASK) +#define GPC_PGC_MIPI_CTRL_DFTRAM_TCD1_MASK 0x3F00u +#define GPC_PGC_MIPI_CTRL_DFTRAM_TCD1_SHIFT 8 +#define GPC_PGC_MIPI_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_MIPI_CTRL_DFTRAM_TCD1_MASK) +#define GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u +#define GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR_SHIFT 16 +#define GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_MIPI_CTRL_L2RETN_TCD1_TDR_MASK) +#define GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u +#define GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24 +#define GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_MIPI_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/* MIPI_PUPSCR Bit Fields */ +#define GPC_PGC_MIPI_PUPSCR_SW_MASK 0x3Fu +#define GPC_PGC_MIPI_PUPSCR_SW_SHIFT 0 +#define GPC_PGC_MIPI_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PUPSCR_SW_SHIFT))&GPC_PGC_MIPI_PUPSCR_SW_MASK) +#define GPC_PGC_MIPI_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u +#define GPC_PGC_MIPI_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6 +#define GPC_PGC_MIPI_PUPSCR_SW2ISO_MASK 0x7FFF80u +#define GPC_PGC_MIPI_PUPSCR_SW2ISO_SHIFT 7 +#define GPC_PGC_MIPI_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_MIPI_PUPSCR_SW2ISO_MASK) +#define GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u +#define GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23 +#define GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_MIPI_PUPSCR_PUP_SCALLOUT_CNT_MASK) +/* MIPI_PDNSCR Bit Fields */ +#define GPC_PGC_MIPI_PDNSCR_ISO_MASK 0x3Fu +#define GPC_PGC_MIPI_PDNSCR_ISO_SHIFT 0 +#define GPC_PGC_MIPI_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PDNSCR_ISO_SHIFT))&GPC_PGC_MIPI_PDNSCR_ISO_MASK) +#define GPC_PGC_MIPI_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u +#define GPC_PGC_MIPI_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7 +#define GPC_PGC_MIPI_PDNSCR_ISO2SW_MASK 0x3F00u +#define GPC_PGC_MIPI_PDNSCR_ISO2SW_SHIFT 8 +#define GPC_PGC_MIPI_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_MIPI_PDNSCR_ISO2SW_MASK) +#define GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u +#define GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16 +#define GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_MIPI_PDNSCR_PUP_SCALLOUT_CNT_MASK) +#define GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u +#define GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24 +#define GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_MIPI_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/* MIPI_SR Bit Fields */ +#define GPC_PGC_MIPI_SR_PSR_MASK 0x1u +#define GPC_PGC_MIPI_SR_PSR_SHIFT 0 +#define GPC_PGC_MIPI_SR_L2RETN_FLAG_MASK 0x2u +#define GPC_PGC_MIPI_SR_L2RETN_FLAG_SHIFT 1 +#define GPC_PGC_MIPI_SR_ALLOFF_FLAG_MASK 0x4u +#define GPC_PGC_MIPI_SR_ALLOFF_FLAG_SHIFT 2 +#define GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL_MASK 0x78u +#define GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL_SHIFT 3 +#define GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_MIPI_SR_PUP_CLK_DIV_SEL_MASK) +#define GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u +#define GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8 +#define GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_MIPI_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/* MIPI_AUXSW Bit Fields */ +#define GPC_PGC_MIPI_AUXSW_SW2_MASK 0x3Fu +#define GPC_PGC_MIPI_AUXSW_SW2_SHIFT 0 +#define GPC_PGC_MIPI_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_AUXSW_SW2_SHIFT))&GPC_PGC_MIPI_AUXSW_SW2_MASK) +#define GPC_PGC_MIPI_AUXSW_ISO2SW2_MASK 0x3F00u +#define GPC_PGC_MIPI_AUXSW_ISO2SW2_SHIFT 8 +#define GPC_PGC_MIPI_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_AUXSW_ISO2SW2_SHIFT))&GPC_PGC_MIPI_AUXSW_ISO2SW2_MASK) +#define GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL_MASK 0xF0000u +#define GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL_SHIFT 16 +#define GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL_SHIFT))&GPC_PGC_MIPI_AUXSW_PDN_CLK_DIV_SEL_MASK) +/* PCIE_CTRL Bit Fields */ +#define GPC_PGC_PCIE_CTRL_PCR_MASK 0x1u +#define GPC_PGC_PCIE_CTRL_PCR_SHIFT 0 +#define GPC_PGC_PCIE_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_PCIE_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_PCIE_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_PCIE_CTRL_L2RSTDIS_MASK) +#define GPC_PGC_PCIE_CTRL_DFTRAM_TCD1_MASK 0x3F00u +#define GPC_PGC_PCIE_CTRL_DFTRAM_TCD1_SHIFT 8 +#define GPC_PGC_PCIE_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_PCIE_CTRL_DFTRAM_TCD1_MASK) +#define GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u +#define GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR_SHIFT 16 +#define GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_PCIE_CTRL_L2RETN_TCD1_TDR_MASK) +#define GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u +#define GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24 +#define GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_PCIE_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/* PCIE_PUPSCR Bit Fields */ +#define GPC_PGC_PCIE_PUPSCR_SW_MASK 0x3Fu +#define GPC_PGC_PCIE_PUPSCR_SW_SHIFT 0 +#define GPC_PGC_PCIE_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PUPSCR_SW_SHIFT))&GPC_PGC_PCIE_PUPSCR_SW_MASK) +#define GPC_PGC_PCIE_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u +#define GPC_PGC_PCIE_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6 +#define GPC_PGC_PCIE_PUPSCR_SW2ISO_MASK 0x7FFF80u +#define GPC_PGC_PCIE_PUPSCR_SW2ISO_SHIFT 7 +#define GPC_PGC_PCIE_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_PCIE_PUPSCR_SW2ISO_MASK) +#define GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u +#define GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23 +#define GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_PCIE_PUPSCR_PUP_SCALLOUT_CNT_MASK) +/* PCIE_PDNSCR Bit Fields */ +#define GPC_PGC_PCIE_PDNSCR_ISO_MASK 0x3Fu +#define GPC_PGC_PCIE_PDNSCR_ISO_SHIFT 0 +#define GPC_PGC_PCIE_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PDNSCR_ISO_SHIFT))&GPC_PGC_PCIE_PDNSCR_ISO_MASK) +#define GPC_PGC_PCIE_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u +#define GPC_PGC_PCIE_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7 +#define GPC_PGC_PCIE_PDNSCR_ISO2SW_MASK 0x3F00u +#define GPC_PGC_PCIE_PDNSCR_ISO2SW_SHIFT 8 +#define GPC_PGC_PCIE_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_PCIE_PDNSCR_ISO2SW_MASK) +#define GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u +#define GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16 +#define GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_PCIE_PDNSCR_PUP_SCALLOUT_CNT_MASK) +#define GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u +#define GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24 +#define GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_PCIE_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/* PCIE_SR Bit Fields */ +#define GPC_PGC_PCIE_SR_PSR_MASK 0x1u +#define GPC_PGC_PCIE_SR_PSR_SHIFT 0 +#define GPC_PGC_PCIE_SR_L2RETN_FLAG_MASK 0x2u +#define GPC_PGC_PCIE_SR_L2RETN_FLAG_SHIFT 1 +#define GPC_PGC_PCIE_SR_ALLOFF_FLAG_MASK 0x4u +#define GPC_PGC_PCIE_SR_ALLOFF_FLAG_SHIFT 2 +#define GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL_MASK 0x78u +#define GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL_SHIFT 3 +#define GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_PCIE_SR_PUP_CLK_DIV_SEL_MASK) +#define GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u +#define GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8 +#define GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_PCIE_SR_L2RSTDIS_DEASSERT_CNT_MASK) +/* PCIE_AUXSW Bit Fields */ +#define GPC_PGC_PCIE_AUXSW_SW2_MASK 0x3Fu +#define GPC_PGC_PCIE_AUXSW_SW2_SHIFT 0 +#define GPC_PGC_PCIE_AUXSW_SW2(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_AUXSW_SW2_SHIFT))&GPC_PGC_PCIE_AUXSW_SW2_MASK) +#define GPC_PGC_PCIE_AUXSW_ISO2SW2_MASK 0x3F00u +#define GPC_PGC_PCIE_AUXSW_ISO2SW2_SHIFT 8 +#define GPC_PGC_PCIE_AUXSW_ISO2SW2(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_AUXSW_ISO2SW2_SHIFT))&GPC_PGC_PCIE_AUXSW_ISO2SW2_MASK) +#define GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL_MASK 0xF0000u +#define GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL_SHIFT 16 +#define GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL_SHIFT))&GPC_PGC_PCIE_AUXSW_PDN_CLK_DIV_SEL_MASK) +/* HSIC_CTRL Bit Fields */ +#define GPC_PGC_HSIC_CTRL_PCR_MASK 0x1u +#define GPC_PGC_HSIC_CTRL_PCR_SHIFT 0 +#define GPC_PGC_HSIC_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_HSIC_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_HSIC_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_CTRL_L2RSTDIS_SHIFT))&GPC_PGC_HSIC_CTRL_L2RSTDIS_MASK) +#define GPC_PGC_HSIC_CTRL_DFTRAM_TCD1_MASK 0x3F00u +#define GPC_PGC_HSIC_CTRL_DFTRAM_TCD1_SHIFT 8 +#define GPC_PGC_HSIC_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_CTRL_DFTRAM_TCD1_SHIFT))&GPC_PGC_HSIC_CTRL_DFTRAM_TCD1_MASK) +#define GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR_MASK 0x3F0000u +#define GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR_SHIFT 16 +#define GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR_SHIFT))&GPC_PGC_HSIC_CTRL_L2RETN_TCD1_TDR_MASK) +#define GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK 0x3F000000u +#define GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT 24 +#define GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT))&GPC_PGC_HSIC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK) +/* HSIC_PUPSCR Bit Fields */ +#define GPC_PGC_HSIC_PUPSCR_SW_MASK 0x3Fu +#define GPC_PGC_HSIC_PUPSCR_SW_SHIFT 0 +#define GPC_PGC_HSIC_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PUPSCR_SW_SHIFT))&GPC_PGC_HSIC_PUPSCR_SW_MASK) +#define GPC_PGC_HSIC_PUPSCR_PUP_WAIT_SCALL_OUT_MASK 0x40u +#define GPC_PGC_HSIC_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT 6 +#define GPC_PGC_HSIC_PUPSCR_SW2ISO_MASK 0x7FFF80u +#define GPC_PGC_HSIC_PUPSCR_SW2ISO_SHIFT 7 +#define GPC_PGC_HSIC_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PUPSCR_SW2ISO_SHIFT))&GPC_PGC_HSIC_PUPSCR_SW2ISO_MASK) +#define GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT_MASK 0xFF800000u +#define GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT_SHIFT 23 +#define GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_HSIC_PUPSCR_PUP_SCALLOUT_CNT_MASK) +/* HSIC_PDNSCR Bit Fields */ +#define GPC_PGC_HSIC_PDNSCR_ISO_MASK 0x3Fu +#define GPC_PGC_HSIC_PDNSCR_ISO_SHIFT 0 +#define GPC_PGC_HSIC_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PDNSCR_ISO_SHIFT))&GPC_PGC_HSIC_PDNSCR_ISO_MASK) +#define GPC_PGC_HSIC_PDNSCR_PUP_WAIT_SCALL_OUT_MASK 0x80u +#define GPC_PGC_HSIC_PDNSCR_PUP_WAIT_SCALL_OUT_SHIFT 7 +#define GPC_PGC_HSIC_PDNSCR_ISO2SW_MASK 0x3F00u +#define GPC_PGC_HSIC_PDNSCR_ISO2SW_SHIFT 8 +#define GPC_PGC_HSIC_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PDNSCR_ISO2SW_SHIFT))&GPC_PGC_HSIC_PDNSCR_ISO2SW_MASK) +#define GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT_MASK 0xFF0000u +#define GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT_SHIFT 16 +#define GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT_SHIFT))&GPC_PGC_HSIC_PDNSCR_PUP_SCALLOUT_CNT_MASK) +#define GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK 0xFF000000u +#define GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT 24 +#define GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT_SHIFT))&GPC_PGC_HSIC_PDNSCR_PUP_SCPRE_SCALL_CNT_MASK) +/* HSIC_SR Bit Fields */ +#define GPC_PGC_HSIC_SR_PSR_MASK 0x1u +#define GPC_PGC_HSIC_SR_PSR_SHIFT 0 +#define GPC_PGC_HSIC_SR_L2RETN_FLAG_MASK 0x2u +#define GPC_PGC_HSIC_SR_L2RETN_FLAG_SHIFT 1 +#define GPC_PGC_HSIC_SR_ALLOFF_FLAG_MASK 0x4u +#define GPC_PGC_HSIC_SR_ALLOFF_FLAG_SHIFT 2 +#define GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL_MASK 0x78u +#define GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL_SHIFT 3 +#define GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL_SHIFT))&GPC_PGC_HSIC_SR_PUP_CLK_DIV_SEL_MASK) +#define GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT_MASK 0x3FF00u +#define GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT 8 +#define GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT))&GPC_PGC_HSIC_SR_L2RSTDIS_DEASSERT_CNT_MASK) + +/*! + * @} + */ /* end of group GPC_PGC_Register_Masks */ + +/* GPC_PGC - Peripheral instance base addresses */ +/** Peripheral GPC_PGC base address */ +#define GPC_PGC_BASE (0x303A0000u) +/** Peripheral GPC_PGC base pointer */ +#define GPC_PGC ((GPC_PGC_Type *)GPC_PGC_BASE) +#define GPC_PGC_BASE_PTR (GPC_PGC) +/** Array initializer of GPC_PGC peripheral base addresses */ +#define GPC_PGC_BASE_ADDRS { GPC_PGC_BASE } +/** Array initializer of GPC_PGC peripheral base pointers */ +#define GPC_PGC_BASE_PTRS { GPC_PGC } +/* ---------------------------------------------------------------------------- + -- GPC_PGC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_PGC_Register_Accessor_Macros GPC_PGC - Register accessor macros + * @{ + */ + + +/* GPC_PGC - Register instance definitions */ +/* GPC_PGC */ +#define GPC_PGC_A7CORE0_CTRL GPC_PGC_A7CORE0_CTRL_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7CORE0_PUPSCR GPC_PGC_A7CORE0_PUPSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7CORE0_PDNSCR GPC_PGC_A7CORE0_PDNSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7CORE0_SR GPC_PGC_A7CORE0_SR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7CORE1_CTRL GPC_PGC_A7CORE1_CTRL_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7CORE1_PUPSCR GPC_PGC_A7CORE1_PUPSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7CORE1_PDNSCR GPC_PGC_A7CORE1_PDNSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7CORE1_SR GPC_PGC_A7CORE1_SR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7SCU_CTRL GPC_PGC_A7SCU_CTRL_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7SCU_PUPSCR GPC_PGC_A7SCU_PUPSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7SCU_PDNSCR GPC_PGC_A7SCU_PDNSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_A7SCU_SR GPC_PGC_A7SCU_SR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_SCU_AUXSW GPC_PGC_SCU_AUXSW_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIX_CTRL GPC_PGC_MIX_CTRL_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIX_PUPSCR GPC_PGC_MIX_PUPSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIX_PDNSCR GPC_PGC_MIX_PDNSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIX_SR GPC_PGC_MIX_SR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIPI_CTRL GPC_PGC_MIPI_CTRL_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIPI_PUPSCR GPC_PGC_MIPI_PUPSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIPI_PDNSCR GPC_PGC_MIPI_PDNSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIPI_SR GPC_PGC_MIPI_SR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_MIPI_AUXSW GPC_PGC_MIPI_AUXSW_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_PCIE_CTRL GPC_PGC_PCIE_CTRL_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_PCIE_PUPSCR GPC_PGC_PCIE_PUPSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_PCIE_PDNSCR GPC_PGC_PCIE_PDNSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_PCIE_SR GPC_PGC_PCIE_SR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_PCIE_AUXSW GPC_PGC_PCIE_AUXSW_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_HSIC_CTRL GPC_PGC_HSIC_CTRL_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_HSIC_PUPSCR GPC_PGC_HSIC_PUPSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_HSIC_PDNSCR GPC_PGC_HSIC_PDNSCR_REG(GPC_PGC_BASE_PTR) +#define GPC_PGC_HSIC_SR GPC_PGC_HSIC_SR_REG(GPC_PGC_BASE_PTR) +/*! + * @} + */ /* end of group GPC_PGC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group GPC_PGC_Peripheral */ /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer @@ -70055,7 +19727,6 @@ typedef struct { __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ } GPIO_Type, *GPIO_MemMapPtr; - /* ---------------------------------------------------------------------------- -- GPIO - Register accessor macros ---------------------------------------------------------------------------- */ @@ -70079,8 +19750,6 @@ typedef struct { /*! * @} */ /* end of group GPIO_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ @@ -70217,7 +19886,6 @@ typedef struct { * @} */ /* end of group GPIO_Register_Masks */ - /* GPIO - Peripheral instance base addresses */ /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x30200000u) @@ -70254,11 +19922,10 @@ typedef struct { /** Peripheral GPIO7 base pointer */ #define GPIO7 ((GPIO_Type *)GPIO7_BASE) #define GPIO7_BASE_PTR (GPIO7) -/** Array initializer of GPIO peripheral base adresses */ +/** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS { GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7 } - /* ---------------------------------------------------------------------------- -- GPIO - Register accessor macros ---------------------------------------------------------------------------- */ @@ -70333,7 +20000,6 @@ typedef struct { #define GPIO7_IMR GPIO_IMR_REG(GPIO7_BASE_PTR) #define GPIO7_ISR GPIO_ISR_REG(GPIO7_BASE_PTR) #define GPIO7_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO7_BASE_PTR) - /*! * @} */ /* end of group GPIO_Register_Accessor_Macros */ @@ -70343,7 +20009,6 @@ typedef struct { * @} */ /* end of group GPIO_Peripheral */ - /* ---------------------------------------------------------------------------- -- GPMI Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -70389,7 +20054,7 @@ typedef struct { uint8_t RESERVED_9[12]; __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ uint8_t RESERVED_10[12]; - __I uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ + __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ uint8_t RESERVED_11[12]; __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ uint8_t RESERVED_12[12]; @@ -70397,7 +20062,6 @@ typedef struct { uint8_t RESERVED_13[28]; __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ } GPMI_Type, *GPMI_MemMapPtr; - /* ---------------------------------------------------------------------------- -- GPMI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -70440,8 +20104,6 @@ typedef struct { /*! * @} */ /* end of group GPMI_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- GPMI Register Masks ---------------------------------------------------------------------------- */ @@ -71085,18 +20747,18 @@ typedef struct { * @} */ /* end of group GPMI_Register_Masks */ - /* GPMI - Peripheral instance base addresses */ /** Peripheral GPMI base address */ #define GPMI_BASE (0x33002000u) /** Peripheral GPMI base pointer */ #define GPMI ((GPMI_Type *)GPMI_BASE) #define GPMI_BASE_PTR (GPMI) -/** Array initializer of GPMI peripheral base adresses */ +/** Array initializer of GPMI peripheral base addresses */ #define GPMI_BASE_ADDRS { GPMI_BASE } /** Array initializer of GPMI peripheral base pointers */ #define GPMI_BASE_PTRS { GPMI } - +/** Interrupt vectors for the GPMI peripheral type */ +#define GPMI_IRQS { GPMI_IRQn } /* ---------------------------------------------------------------------------- -- GPMI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -71136,7 +20798,6 @@ typedef struct { #define GPMI_DEBUG3 GPMI_DEBUG3_REG(GPMI_BASE_PTR) #define GPMI_READ_DDR_DLL_CTRL GPMI_READ_DDR_DLL_CTRL_REG(GPMI_BASE_PTR) #define GPMI_READ_DDR_DLL_STS GPMI_READ_DDR_DLL_STS_REG(GPMI_BASE_PTR) - /*! * @} */ /* end of group GPMI_Register_Accessor_Macros */ @@ -71146,7 +20807,6 @@ typedef struct { * @} */ /* end of group GPMI_Peripheral */ - /* ---------------------------------------------------------------------------- -- GPT Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -71169,7 +20829,6 @@ typedef struct { __I uint32_t ICR2; /**< GPT Input Capture Register 2, offset: 0x20 */ __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ } GPT_Type, *GPT_MemMapPtr; - /* ---------------------------------------------------------------------------- -- GPT - Register accessor macros ---------------------------------------------------------------------------- */ @@ -71195,8 +20854,6 @@ typedef struct { /*! * @} */ /* end of group GPT_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- GPT Register Masks ---------------------------------------------------------------------------- */ @@ -71224,8 +20881,8 @@ typedef struct { #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_CLKSRC_SHIFT))&GPT_CR_CLKSRC_MASK) #define GPT_CR_FRR_MASK 0x200u #define GPT_CR_FRR_SHIFT 9 -#define GPT_CR_ENABLE_24MHZ_MASK 0x400u -#define GPT_CR_ENABLE_24MHZ_SHIFT 10 +#define GPT_CR_EN_24M_MASK 0x400u +#define GPT_CR_EN_24M_SHIFT 10 #define GPT_CR_SWR_MASK 0x8000u #define GPT_CR_SWR_SHIFT 15 #define GPT_CR_IM1_MASK 0x30000u @@ -71311,7 +20968,6 @@ typedef struct { * @} */ /* end of group GPT_Register_Masks */ - /* GPT - Peripheral instance base addresses */ /** Peripheral GPT1 base address */ #define GPT1_BASE (0x302D0000u) @@ -71333,11 +20989,12 @@ typedef struct { /** Peripheral GPT4 base pointer */ #define GPT4 ((GPT_Type *)GPT4_BASE) #define GPT4_BASE_PTR (GPT4) -/** Array initializer of GPT peripheral base adresses */ +/** Array initializer of GPT peripheral base addresses */ #define GPT_BASE_ADDRS { GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE } /** Array initializer of GPT peripheral base pointers */ #define GPT_BASE_PTRS { GPT1, GPT2, GPT3, GPT4 } - +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn } /* ---------------------------------------------------------------------------- -- GPT - Register accessor macros ---------------------------------------------------------------------------- */ @@ -71393,7 +21050,6 @@ typedef struct { #define GPT4_ICR1 GPT_ICR1_REG(GPT4_BASE_PTR) #define GPT4_ICR2 GPT_ICR2_REG(GPT4_BASE_PTR) #define GPT4_CNT GPT_CNT_REG(GPT4_BASE_PTR) - /*! * @} */ /* end of group GPT_Register_Accessor_Macros */ @@ -71403,7 +21059,6 @@ typedef struct { * @} */ /* end of group GPT_Peripheral */ - /* ---------------------------------------------------------------------------- -- I2C Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -71415,17 +21070,16 @@ typedef struct { /** I2C - Register Layout Typedef */ typedef struct { - __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ + __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ uint8_t RESERVED_0[2]; - __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ + __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ uint8_t RESERVED_1[2]; - __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ + __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ uint8_t RESERVED_2[2]; - __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ + __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ uint8_t RESERVED_3[2]; - __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ + __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ } I2C_Type, *I2C_MemMapPtr; - /* ---------------------------------------------------------------------------- -- I2C - Register accessor macros ---------------------------------------------------------------------------- */ @@ -71446,8 +21100,6 @@ typedef struct { /*! * @} */ /* end of group I2C_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ @@ -71502,7 +21154,6 @@ typedef struct { * @} */ /* end of group I2C_Register_Masks */ - /* I2C - Peripheral instance base addresses */ /** Peripheral I2C1 base address */ #define I2C1_BASE (0x30A20000u) @@ -71524,11 +21175,12 @@ typedef struct { /** Peripheral I2C4 base pointer */ #define I2C4 ((I2C_Type *)I2C4_BASE) #define I2C4_BASE_PTR (I2C4) -/** Array initializer of I2C peripheral base adresses */ +/** Array initializer of I2C peripheral base addresses */ #define I2C_BASE_ADDRS { I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } /** Array initializer of I2C peripheral base pointers */ #define I2C_BASE_PTRS { I2C1, I2C2, I2C3, I2C4 } - +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn } /* ---------------------------------------------------------------------------- -- I2C - Register accessor macros ---------------------------------------------------------------------------- */ @@ -71564,7 +21216,6 @@ typedef struct { #define I2C4_I2CR I2C_I2CR_REG(I2C4_BASE_PTR) #define I2C4_I2SR I2C_I2SR_REG(I2C4_BASE_PTR) #define I2C4_I2DR I2C_I2DR_REG(I2C4_BASE_PTR) - /*! * @} */ /* end of group I2C_Register_Accessor_Macros */ @@ -71574,7 +21225,6 @@ typedef struct { * @} */ /* end of group I2C_Peripheral */ - /* ---------------------------------------------------------------------------- -- I2S Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -71586,33 +21236,32 @@ typedef struct { /** I2S - Register Layout Typedef */ typedef struct { - __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ - __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ - __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ - __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ - __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ - __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ uint8_t RESERVED_0[8]; - __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[28]; - __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ uint8_t RESERVED_2[28]; - __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ uint8_t RESERVED_3[28]; - __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ - __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ - __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ - __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ - __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ - __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ uint8_t RESERVED_4[8]; - __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_5[28]; - __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_6[28]; - __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ } I2S_Type, *I2S_MemMapPtr; - /* ---------------------------------------------------------------------------- -- I2S - Register accessor macros ---------------------------------------------------------------------------- */ @@ -71646,8 +21295,6 @@ typedef struct { /*! * @} */ /* end of group I2S_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ @@ -71872,7 +21519,6 @@ typedef struct { * @} */ /* end of group I2S_Register_Masks */ - /* I2S - Peripheral instance base addresses */ /** Peripheral I2S1 base address */ #define I2S1_BASE (0x308A0000u) @@ -71889,11 +21535,12 @@ typedef struct { /** Peripheral I2S3 base pointer */ #define I2S3 ((I2S_Type *)I2S3_BASE) #define I2S3_BASE_PTR (I2S3) -/** Array initializer of I2S peripheral base adresses */ +/** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS { I2S1_BASE, I2S2_BASE, I2S3_BASE } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS { I2S1, I2S2, I2S3 } - +/** Interrupt vectors for the I2S peripheral type */ +#define SAI_IRQS { SAI1_IRQn, SAI2_IRQn, SAI3_IRQn } /* ---------------------------------------------------------------------------- -- I2S - Register accessor macros ---------------------------------------------------------------------------- */ @@ -71962,7 +21609,6 @@ typedef struct { #define I2S3_RDR0 I2S_RDR_REG(I2S3_BASE_PTR,0) #define I2S3_RFR0 I2S_RFR_REG(I2S3_BASE_PTR,0) #define I2S3_RMR I2S_RMR_REG(I2S3_BASE_PTR) - /* I2S - Register array accessors */ #define I2S1_TDR(index) I2S_TDR_REG(I2S1_BASE_PTR,index) #define I2S2_TDR(index) I2S_TDR_REG(I2S2_BASE_PTR,index) @@ -71976,7 +21622,6 @@ typedef struct { #define I2S1_RFR(index) I2S_RFR_REG(I2S1_BASE_PTR,index) #define I2S2_RFR(index) I2S_RFR_REG(I2S2_BASE_PTR,index) #define I2S3_RFR(index) I2S_RFR_REG(I2S3_BASE_PTR,index) - /*! * @} */ /* end of group I2S_Register_Accessor_Macros */ @@ -71986,7 +21631,6 @@ typedef struct { * @} */ /* end of group I2S_Peripheral */ - /* ---------------------------------------------------------------------------- -- IOMUXC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -72230,8 +21874,8 @@ typedef struct { __IO uint32_t SW_PAD_CTL_PAD_UART2_TX_DATA; /**< SW_PAD_CTL_PAD_UART2_TX_DATA SW PAD Control Register, offset: 0x3A4 */ __IO uint32_t SW_PAD_CTL_PAD_UART3_RX_DATA; /**< SW_PAD_CTL_PAD_UART3_RX_DATA SW PAD Control Register, offset: 0x3A8 */ __IO uint32_t SW_PAD_CTL_PAD_UART3_TX_DATA; /**< SW_PAD_CTL_PAD_UART3_TX_DATA SW PAD Control Register, offset: 0x3AC */ - __IO uint32_t SW_PAD_CTL_PAD_UART3_RTS; /**< SW_PAD_CTL_PAD_UART3_RTS SW PAD Control Register, offset: 0x3B0 */ - __IO uint32_t SW_PAD_CTL_PAD_UART3_CTS; /**< SW_PAD_CTL_PAD_UART3_CTS SW PAD Control Register, offset: 0x3B4 */ + __IO uint32_t SW_PAD_CTL_PAD_UART3_RTS_B; /**< SW_PAD_CTL_PAD_UART3_RTS_B SW PAD Control Register, offset: 0x3B0 */ + __IO uint32_t SW_PAD_CTL_PAD_UART3_CTS_B; /**< SW_PAD_CTL_PAD_UART3_CTS_B SW PAD Control Register, offset: 0x3B4 */ __IO uint32_t SW_PAD_CTL_PAD_I2C1_SCL; /**< SW_PAD_CTL_PAD_I2C1_SCL SW PAD Control Register, offset: 0x3B8 */ __IO uint32_t SW_PAD_CTL_PAD_I2C1_SDA; /**< SW_PAD_CTL_PAD_I2C1_SDA SW PAD Control Register, offset: 0x3BC */ __IO uint32_t SW_PAD_CTL_PAD_I2C2_SCL; /**< SW_PAD_CTL_PAD_I2C2_SCL SW PAD Control Register, offset: 0x3C0 */ @@ -72339,10 +21983,10 @@ typedef struct { __IO uint32_t ECSPI4_MISO_SELECT_INPUT; /**< ECSPI4_MISO_SELECT_INPUT DAISY Register, offset: 0x558 */ __IO uint32_t ECSPI4_MOSI_SELECT_INPUT; /**< ECSPI4_MOSI_SELECT_INPUT DAISY Register, offset: 0x55C */ __IO uint32_t ECSPI4_SS0_B_SELECT_INPUT; /**< ECSPI4_SS0_B_SELECT_INPUT DAISY Register, offset: 0x560 */ - __IO uint32_t CCM_ENET_REF_CLK1_SELECT_INPUT; /**< CCM_ENET_REF_CLK1_SELECT_INPUT DAISY Register, offset: 0x564 */ + __IO uint32_t CCM_ENET1_REF_CLK_SELECT_INPUT; /**< CCM_ENET1_REF_CLK_SELECT_INPUT DAISY Register, offset: 0x564 */ __IO uint32_t ENET1_MDIO_SELECT_INPUT; /**< ENET1_MDIO_SELECT_INPUT DAISY Register, offset: 0x568 */ __IO uint32_t ENET1_RX_CLK_SELECT_INPUT; /**< ENET1_RX_CLK_SELECT_INPUT DAISY Register, offset: 0x56C */ - __IO uint32_t CCM_ENET_REF_CLK2_SELECT_INPUT; /**< CCM_ENET_REF_CLK2_SELECT_INPUT DAISY Register, offset: 0x570 */ + __IO uint32_t CCM_ENET2_REF_CLK_SELECT_INPUT; /**< CCM_ENET2_REF_CLK_SELECT_INPUT DAISY Register, offset: 0x570 */ __IO uint32_t ENET2_MDIO_SELECT_INPUT; /**< ENET2_MDIO_SELECT_INPUT DAISY Register, offset: 0x574 */ __IO uint32_t ENET2_RX_CLK_SELECT_INPUT; /**< ENET2_RX_CLK_SELECT_INPUT DAISY Register, offset: 0x578 */ __IO uint32_t EPDC_PWR_IRQ_SELECT_INPUT; /**< EPDC_PWR_IRQ_SELECT_INPUT DAISY Register, offset: 0x57C */ @@ -72459,7 +22103,6 @@ typedef struct { __IO uint32_t SD3_CD_B_SELECT_INPUT; /**< SD3_CD_B_SELECT_INPUT DAISY Register, offset: 0x738 */ __IO uint32_t SD3_WP_SELECT_INPUT; /**< SD3_WP_SELECT_INPUT DAISY Register, offset: 0x73C */ } IOMUXC_Type, *IOMUXC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- IOMUXC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -72702,8 +22345,8 @@ typedef struct { #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_TX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_TX_DATA) -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RTS) -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_CTS) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RTS_B) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_CTS_B) #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SCL) #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SDA) #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SCL) @@ -72811,10 +22454,10 @@ typedef struct { #define IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_MISO_SELECT_INPUT) #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI4_SS0_B_SELECT_INPUT) -#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_REG(base) ((base)->CCM_ENET_REF_CLK1_SELECT_INPUT) +#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_REG(base) ((base)->CCM_ENET1_REF_CLK_SELECT_INPUT) #define IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_MDIO_SELECT_INPUT) #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET1_RX_CLK_SELECT_INPUT) -#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_REG(base) ((base)->CCM_ENET_REF_CLK2_SELECT_INPUT) +#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_REG(base) ((base)->CCM_ENET2_REF_CLK_SELECT_INPUT) #define IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_MDIO_SELECT_INPUT) #define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET2_RX_CLK_SELECT_INPUT) #define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_IRQ_SELECT_INPUT) @@ -72934,8 +22577,6 @@ typedef struct { /*! * @} */ /* end of group IOMUXC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- IOMUXC Register Masks ---------------------------------------------------------------------------- */ @@ -74898,32 +24539,32 @@ typedef struct { #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_MASK 0x60u #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_SHIFT 5 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_MASK) -/* SW_PAD_CTL_PAD_UART3_RTS Bit Fields */ -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE_MASK 0x3u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE_SHIFT 0 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_SRE_MASK 0x4u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_SRE_SHIFT 2 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_HYS_MASK 0x8u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_HYS_SHIFT 3 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PE_MASK 0x10u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PE_SHIFT 4 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS_MASK 0x60u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS_SHIFT 5 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS_MASK) -/* SW_PAD_CTL_PAD_UART3_CTS Bit Fields */ -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE_MASK 0x3u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE_SHIFT 0 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE_MASK) -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_SRE_MASK 0x4u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_SRE_SHIFT 2 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_HYS_MASK 0x8u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_HYS_SHIFT 3 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PE_MASK 0x10u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PE_SHIFT 4 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS_MASK 0x60u -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS_SHIFT 5 -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS_MASK) +/* SW_PAD_CTL_PAD_UART3_RTS_B Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_PS_MASK) +/* SW_PAD_CTL_PAD_UART3_CTS_B Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_PS_MASK) /* SW_PAD_CTL_PAD_I2C1_SCL Bit Fields */ #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_MASK 0x3u #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_SHIFT 0 @@ -75986,10 +25627,10 @@ typedef struct { #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_MASK 0x3u #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_SHIFT 0 #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_MASK) -/* CCM_ENET_REF_CLK1_SELECT_INPUT Bit Fields */ -#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY_MASK 0x3u -#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY_SHIFT 0 -#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY_MASK) +/* CCM_ENET1_REF_CLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_DAISY_MASK) /* ENET1_MDIO_SELECT_INPUT Bit Fields */ #define IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_MASK 0x3u #define IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_SHIFT 0 @@ -75997,10 +25638,10 @@ typedef struct { /* ENET1_RX_CLK_SELECT_INPUT Bit Fields */ #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_DAISY_MASK 0x1u #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_DAISY_SHIFT 0 -/* CCM_ENET_REF_CLK2_SELECT_INPUT Bit Fields */ -#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY_MASK 0x3u -#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY_SHIFT 0 -#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY_MASK) +/* CCM_ENET2_REF_CLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_DAISY_MASK) /* ENET2_MDIO_SELECT_INPUT Bit Fields */ #define IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_MASK 0x3u #define IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_SHIFT 0 @@ -76410,18 +26051,16 @@ typedef struct { * @} */ /* end of group IOMUXC_Register_Masks */ - /* IOMUXC - Peripheral instance base addresses */ /** Peripheral IOMUXC base address */ #define IOMUXC_BASE (0x30330000u) /** Peripheral IOMUXC base pointer */ #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) #define IOMUXC_BASE_PTR (IOMUXC) -/** Array initializer of IOMUXC peripheral base adresses */ +/** Array initializer of IOMUXC peripheral base addresses */ #define IOMUXC_BASE_ADDRS { IOMUXC_BASE } /** Array initializer of IOMUXC peripheral base pointers */ #define IOMUXC_BASE_PTRS { IOMUXC } - /* ---------------------------------------------------------------------------- -- IOMUXC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -76665,8 +26304,8 @@ typedef struct { #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(IOMUXC_BASE_PTR) #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(IOMUXC_BASE_PTR) #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(IOMUXC_BASE_PTR) -#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_REG(IOMUXC_BASE_PTR) -#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_REG(IOMUXC_BASE_PTR) #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(IOMUXC_BASE_PTR) #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(IOMUXC_BASE_PTR) #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(IOMUXC_BASE_PTR) @@ -76774,10 +26413,10 @@ typedef struct { #define IOMUXC_ECSPI4_MISO_SELECT_INPUT IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) -#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ENET1_MDIO_SELECT_INPUT IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) -#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ENET2_MDIO_SELECT_INPUT IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_ENET2_RX_CLK_SELECT_INPUT IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(IOMUXC_BASE_PTR) @@ -76893,7 +26532,6 @@ typedef struct { #define IOMUXC_USB_OTG1_ID_SELECT_INPUT IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SD3_CD_B_SELECT_INPUT IOMUXC_SD3_CD_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) #define IOMUXC_SD3_WP_SELECT_INPUT IOMUXC_SD3_WP_SELECT_INPUT_REG(IOMUXC_BASE_PTR) - /*! * @} */ /* end of group IOMUXC_Register_Accessor_Macros */ @@ -76903,7 +26541,6 @@ typedef struct { * @} */ /* end of group IOMUXC_Peripheral */ - /* ---------------------------------------------------------------------------- -- IOMUXC_GPR Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -76934,12 +26571,11 @@ typedef struct { __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ - __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ + __I uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ - __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ + __I uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ } IOMUXC_GPR_Type, *IOMUXC_GPR_MemMapPtr; - /* ---------------------------------------------------------------------------- -- IOMUXC_GPR - Register accessor macros ---------------------------------------------------------------------------- */ @@ -76978,8 +26614,6 @@ typedef struct { /*! * @} */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- IOMUXC_GPR Register Masks ---------------------------------------------------------------------------- */ @@ -77005,557 +26639,541 @@ typedef struct { #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 /* GPR1 Bit Fields */ -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK) -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK) -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK) -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10 -#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK) -#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u -#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12 -#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u -#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 -#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u -#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14 -#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u -#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15 -#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u -#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16 -#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u -#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17 -#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u -#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18 -#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u -#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22 -#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u -#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 -#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u -#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28 -#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK) -#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u -#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30 +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS0_MASK 0x1u +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS0_SHIFT 0 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0_MASK 0x6u +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0_SHIFT 1 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_WEIM_ADDRS0_MASK) +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS1_MASK 0x8u +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS1_SHIFT 3 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS1_MASK 0x30u +#define IOMUXC_GPR_GPR1_WEIM_ADDRS1_SHIFT 4 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_WEIM_ADDRS1_MASK) +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS2_MASK 0x40u +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS2_SHIFT 6 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS2_MASK 0x180u +#define IOMUXC_GPR_GPR1_WEIM_ADDRS2_SHIFT 7 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_WEIM_ADDRS2_MASK) +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS3_MASK 0x200u +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS3_SHIFT 9 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS3_MASK 0xC00u +#define IOMUXC_GPR_GPR1_WEIM_ADDRS3_SHIFT 10 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_WEIM_ADDRS3_MASK) +#define IOMUXC_GPR_GPR1_IRQ_MASK 0x1000u +#define IOMUXC_GPR_GPR1_IRQ_SHIFT 12 +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_SEL_MASK 0x2000u +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_SEL_SHIFT 13 +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_SEL_MASK 0x4000u +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_SEL_SHIFT 14 +#define IOMUXC_GPR_GPR1_PAD_ADD_DS_MASK 0x10000u +#define IOMUXC_GPR_GPR1_PAD_ADD_DS_SHIFT 16 +#define IOMUXC_GPR_GPR1_ENET1_CLK_DIR_MASK 0x20000u +#define IOMUXC_GPR_GPR1_ENET1_CLK_DIR_SHIFT 17 +#define IOMUXC_GPR_GPR1_ENET2_CLK_DIR_MASK 0x40000u +#define IOMUXC_GPR_GPR1_ENET2_CLK_DIR_SHIFT 18 +#define IOMUXC_GPR_GPR1_EXC_ERR_RESP_EN_MASK 0x400000u +#define IOMUXC_GPR_GPR1_EXC_ERR_RESP_EN_SHIFT 22 +#define IOMUXC_GPR_GPR1_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u +#define IOMUXC_GPR_GPR1_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 +#define IOMUXC_GPR_GPR1_DBG_ACK_MASK 0x30000000u +#define IOMUXC_GPR_GPR1_DBG_ACK_SHIFT 28 +#define IOMUXC_GPR_GPR1_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_DBG_ACK_MASK) +#define IOMUXC_GPR_GPR1_ENABLE_OCRAM_EPDC_MASK 0x40000000u +#define IOMUXC_GPR_GPR1_ENABLE_OCRAM_EPDC_SHIFT 30 /* GPR2 Bit Fields */ -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0 -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1 -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2 -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u -#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3 -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4 -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5 -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6 -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u -#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7 -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8 -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9 -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10 -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u -#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11 -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12 -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13 -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14 -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u -#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15 -#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u -#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16 -#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK) -#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u -#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24 -#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u -#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25 -#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u -#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26 -#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27 -#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28 -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29 -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30 -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u -#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31 +#define IOMUXC_GPR_GPR2_MEM_PXP_LOWPOWER_MASK 0x1u +#define IOMUXC_GPR_GPR2_MEM_PXP_LOWPOWER_SHIFT 0 +#define IOMUXC_GPR_GPR2_MEM_PXP_SD_MASK 0x2u +#define IOMUXC_GPR_GPR2_MEM_PXP_SD_SHIFT 1 +#define IOMUXC_GPR_GPR2_MEM_PXP_DS_MASK 0x4u +#define IOMUXC_GPR_GPR2_MEM_PXP_DS_SHIFT 2 +#define IOMUXC_GPR_GPR2_MEM_PXP_LS_MASK 0x8u +#define IOMUXC_GPR_GPR2_MEM_PXP_LS_SHIFT 3 +#define IOMUXC_GPR_GPR2_MEM_LCDIF_LOWPOWER_MASK 0x10u +#define IOMUXC_GPR_GPR2_MEM_LCDIF_LOWPOWER_SHIFT 4 +#define IOMUXC_GPR_GPR2_MEM_LCDIF_SD_MASK 0x20u +#define IOMUXC_GPR_GPR2_MEM_LCDIF_SD_SHIFT 5 +#define IOMUXC_GPR_GPR2_MEM_LCDIF_DS_MASK 0x40u +#define IOMUXC_GPR_GPR2_MEM_LCDIF_DS_SHIFT 6 +#define IOMUXC_GPR_GPR2_MEM_LCDIF_LS_MASK 0x80u +#define IOMUXC_GPR_GPR2_MEM_LCDIF_LS_SHIFT 7 +#define IOMUXC_GPR_GPR2_MEM_EPDC_LOWPOWER_MASK 0x100u +#define IOMUXC_GPR_GPR2_MEM_EPDC_LOWPOWER_SHIFT 8 +#define IOMUXC_GPR_GPR2_MEM_EPDC_SD_MASK 0x200u +#define IOMUXC_GPR_GPR2_MEM_EPDC_SD_SHIFT 9 +#define IOMUXC_GPR_GPR2_MEM_EPDC_DS_MASK 0x400u +#define IOMUXC_GPR_GPR2_MEM_EPDC_DS_SHIFT 10 +#define IOMUXC_GPR_GPR2_MEM_EPDC_LS_MASK 0x800u +#define IOMUXC_GPR_GPR2_MEM_EPDC_LS_SHIFT 11 +#define IOMUXC_GPR_GPR2_MEM_CPU_LOWPOWER_MASK 0x1000u +#define IOMUXC_GPR_GPR2_MEM_CPU_LOWPOWER_SHIFT 12 +#define IOMUXC_GPR_GPR2_MEM_CPU_SD_MASK 0x2000u +#define IOMUXC_GPR_GPR2_MEM_CPU_SD_SHIFT 13 +#define IOMUXC_GPR_GPR2_MEM_CPU_DS_MASK 0x4000u +#define IOMUXC_GPR_GPR2_MEM_CPU_DS_SHIFT 14 +#define IOMUXC_GPR_GPR2_MEM_CPU_LS_MASK 0x8000u +#define IOMUXC_GPR_GPR2_MEM_CPU_LS_SHIFT 15 +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK 0xFF0000u +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT 16 +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK 0x1000000u +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT 24 +#define IOMUXC_GPR_GPR2_MQS_EN_MASK 0x2000000u +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT 25 +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK 0x4000000u +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT 26 +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK 0x8000000u +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT 27 +#define IOMUXC_GPR_GPR2_DRAM_RESET_MASK 0x10000000u +#define IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT 28 +#define IOMUXC_GPR_GPR2_DRAM_CKE0_MASK 0x20000000u +#define IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT 29 +#define IOMUXC_GPR_GPR2_DRAM_CKE1_MASK 0x40000000u +#define IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT 30 +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK 0x80000000u +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT 31 /* GPR3 Bit Fields */ -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14 -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u -#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15 -#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16 -#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17 -#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18 -#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19 -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20 -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21 -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22 -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23 -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24 -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25 -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26 -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27 -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28 -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29 -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30 -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u -#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31 +#define IOMUXC_GPR_GPR3_RDATA_WAIT_EN_MASK 0x1u +#define IOMUXC_GPR_GPR3_RDATA_WAIT_EN_SHIFT 0 +#define IOMUXC_GPR_GPR3_RADDR_PIPE_EN_MASK 0x2u +#define IOMUXC_GPR_GPR3_RADDR_PIPE_EN_SHIFT 1 +#define IOMUXC_GPR_GPR3_WDATA_PIPE_EN_MASK 0x4u +#define IOMUXC_GPR_GPR3_WDATA_PIPE_EN_SHIFT 2 +#define IOMUXC_GPR_GPR3_WADDR_PIPE_EN_MASK 0x8u +#define IOMUXC_GPR_GPR3_WADDR_PIPE_EN_SHIFT 3 +#define IOMUXC_GPR_GPR3_S_RDATA_WAIT_EN_MASK 0x10u +#define IOMUXC_GPR_GPR3_S_RDATA_WAIT_EN_SHIFT 4 +#define IOMUXC_GPR_GPR3_S_RADDR_PIPE_EN_MASK 0x20u +#define IOMUXC_GPR_GPR3_S_RADDR_PIPE_EN_SHIFT 5 +#define IOMUXC_GPR_GPR3_S_WDATA_PIPE_EN_MASK 0x40u +#define IOMUXC_GPR_GPR3_S_WDATA_PIPE_EN_SHIFT 6 +#define IOMUXC_GPR_GPR3_S_WADDR_PIPE_EN_MASK 0x80u +#define IOMUXC_GPR_GPR3_S_WADDR_PIPE_EN_SHIFT 7 +#define IOMUXC_GPR_GPR3_E_RDATA_WAIT_EN_MASK 0x100u +#define IOMUXC_GPR_GPR3_E_RDATA_WAIT_EN_SHIFT 8 +#define IOMUXC_GPR_GPR3_E_RADDR_PIPE_EN_MASK 0x200u +#define IOMUXC_GPR_GPR3_E_RADDR_PIPE_EN_SHIFT 9 +#define IOMUXC_GPR_GPR3_E_WDATA_PIPE_EN_MASK 0x400u +#define IOMUXC_GPR_GPR3_E_WDATA_PIPE_EN_SHIFT 10 +#define IOMUXC_GPR_GPR3_E_WADDR_PIPE_EN_MASK 0x800u +#define IOMUXC_GPR_GPR3_E_WADDR_PIPE_EN_SHIFT 11 +#define IOMUXC_GPR_GPR3_P_RDATA_WAIT_EN_MASK 0x1000u +#define IOMUXC_GPR_GPR3_P_RDATA_WAIT_EN_SHIFT 12 +#define IOMUXC_GPR_GPR3_P_RADDR_PIPE_EN_MASK 0x2000u +#define IOMUXC_GPR_GPR3_P_RADDR_PIPE_EN_SHIFT 13 +#define IOMUXC_GPR_GPR3_P_WDATA_PIPE_EN_MASK 0x4000u +#define IOMUXC_GPR_GPR3_P_WDATA_PIPE_EN_SHIFT 14 +#define IOMUXC_GPR_GPR3_P_WADDR_PIPE_EN_MASK 0x8000u +#define IOMUXC_GPR_GPR3_P_WADDR_PIPE_EN_SHIFT 15 +#define IOMUXC_GPR_GPR3_RDATA_WAIT_EN_PDG_MASK 0x10000u +#define IOMUXC_GPR_GPR3_RDATA_WAIT_EN_PDG_SHIFT 16 +#define IOMUXC_GPR_GPR3_RADDR_PIPE_EN_PDG_MASK 0x20000u +#define IOMUXC_GPR_GPR3_RADDR_PIPE_EN_PDG_SHIFT 17 +#define IOMUXC_GPR_GPR3_WDATA_PIPE_EN_PDG_MASK 0x40000u +#define IOMUXC_GPR_GPR3_WDATA_PIPE_EN_PDG_SHIFT 18 +#define IOMUXC_GPR_GPR3_WADDR_PIPE_EN_PNDG_MASK 0x80000u +#define IOMUXC_GPR_GPR3_WADDR_PIPE_EN_PNDG_SHIFT 19 +#define IOMUXC_GPR_GPR3_S_RDATA_WAIT_EN_PNDG_MASK 0x100000u +#define IOMUXC_GPR_GPR3_S_RDATA_WAIT_EN_PNDG_SHIFT 20 +#define IOMUXC_GPR_GPR3_S_RADDR_PIPE_EN_PNDG_MASK 0x200000u +#define IOMUXC_GPR_GPR3_S_RADDR_PIPE_EN_PNDG_SHIFT 21 +#define IOMUXC_GPR_GPR3_S_WDATA_PIPE_EN_PNDG_MASK 0x400000u +#define IOMUXC_GPR_GPR3_S_WDATA_PIPE_EN_PNDG_SHIFT 22 +#define IOMUXC_GPR_GPR3_S_WADDR_PIPE_EN_PNDG_MASK 0x800000u +#define IOMUXC_GPR_GPR3_S_WADDR_PIPE_EN_PNDG_SHIFT 23 +#define IOMUXC_GPR_GPR3_E_RDATA_WAIT_EN_PNDG_MASK 0x1000000u +#define IOMUXC_GPR_GPR3_E_RDATA_WAIT_EN_PNDG_SHIFT 24 +#define IOMUXC_GPR_GPR3_E_RADDR_PIPE_EN_PNDG_MASK 0x2000000u +#define IOMUXC_GPR_GPR3_E_RADDR_PIPE_EN_PNDG_SHIFT 25 +#define IOMUXC_GPR_GPR3_E_WDATA_PIPE_EN_PNDG_MASK 0x4000000u +#define IOMUXC_GPR_GPR3_E_WDATA_PIPE_EN_PNDG_SHIFT 26 +#define IOMUXC_GPR_GPR3_E_WADDR_PIPE_EN_PNDG_MASK 0x8000000u +#define IOMUXC_GPR_GPR3_E_WADDR_PIPE_EN_PNDG_SHIFT 27 +#define IOMUXC_GPR_GPR3_P_RDATA_WAIT_EN_PNDG_MASK 0x10000000u +#define IOMUXC_GPR_GPR3_P_RDATA_WAIT_EN_PNDG_SHIFT 28 +#define IOMUXC_GPR_GPR3_P_RADDR_PIPE_EN_PNDG_MASK 0x20000000u +#define IOMUXC_GPR_GPR3_P_RADDR_PIPE_EN_PNDG_SHIFT 29 +#define IOMUXC_GPR_GPR3_P_WDATA_PIPE_EN_PNDG_MASK 0x40000000u +#define IOMUXC_GPR_GPR3_P_WDATA_PIPE_EN_PNDG_SHIFT 30 +#define IOMUXC_GPR_GPR3_P_WADDR_PIPE_EN_PNDG_MASK 0x80000000u +#define IOMUXC_GPR_GPR3_P_WADDR_PIPE_EN_PNDG_SHIFT 31 /* GPR4 Bit Fields */ -#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u -#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0 -#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u -#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1 -#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u -#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2 -#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u -#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3 -#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u -#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4 -#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u -#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5 -#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u -#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6 -#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u -#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7 -#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u -#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16 -#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u -#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17 -#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u -#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18 -#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u -#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19 -#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u -#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20 -#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u -#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21 -#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u -#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22 -#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u -#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23 -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25 -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK) -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27 -#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK) +#define IOMUXC_GPR_GPR4_SDMA_IPG_STOP_MASK 0x1u +#define IOMUXC_GPR_GPR4_SDMA_IPG_STOP_SHIFT 0 +#define IOMUXC_GPR_GPR4_CAN1_IPG_STOP_MASK 0x2u +#define IOMUXC_GPR_GPR4_CAN1_IPG_STOP_SHIFT 1 +#define IOMUXC_GPR_GPR4_CAN2_IPG_STOP_MASK 0x4u +#define IOMUXC_GPR_GPR4_CAN2_IPG_STOP_SHIFT 2 +#define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_MASK 0x8u +#define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_SHIFT 3 +#define IOMUXC_GPR_GPR4_ENET2_IPG_STOP_MASK 0x10u +#define IOMUXC_GPR_GPR4_ENET2_IPG_STOP_SHIFT 4 +#define IOMUXC_GPR_GPR4_SAI1_IPG_STOP_MASK 0x20u +#define IOMUXC_GPR_GPR4_SAI1_IPG_STOP_SHIFT 5 +#define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_MASK 0x40u +#define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_SHIFT 6 +#define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_MASK 0x80u +#define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_SHIFT 7 +#define IOMUXC_GPR_GPR4_SDMA_IPG_STOP_ACK_MASK 0x10000u +#define IOMUXC_GPR_GPR4_SDMA_IPG_STOP_ACK_SHIFT 16 +#define IOMUXC_GPR_GPR4_CAN1_IPG_STOP_ACK_MASK 0x20000u +#define IOMUXC_GPR_GPR4_CAN1_IPG_STOP_ACK_SHIFT 17 +#define IOMUXC_GPR_GPR4_CAN2_IPG_STOP_ACK_MASK 0x40000u +#define IOMUXC_GPR_GPR4_CAN2_IPG_STOP_ACK_SHIFT 18 +#define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_MASK 0x80000u +#define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_SHIFT 19 +#define IOMUXC_GPR_GPR4_ENET2_IPG_STOP_ACK_MASK 0x100000u +#define IOMUXC_GPR_GPR4_ENET2_IPG_STOP_ACK_SHIFT 20 +#define IOMUXC_GPR_GPR4_SAI1_IPG_STOP_ACK_MASK 0x200000u +#define IOMUXC_GPR_GPR4_SAI1_IPG_STOP_ACK_SHIFT 21 +#define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_MASK 0x400000u +#define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_SHIFT 22 +#define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_MASK 0x800000u +#define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_SHIFT 23 +#define IOMUXC_GPR_GPR4_CPU_STANDBYWFI_MASK 0x6000000u +#define IOMUXC_GPR_GPR4_CPU_STANDBYWFI_SHIFT 25 +#define IOMUXC_GPR_GPR4_CPU_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_CPU_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_CPU_STANDBYWFI_MASK) +#define IOMUXC_GPR_GPR4_CPU_STANDBYWFE_MASK 0x18000000u +#define IOMUXC_GPR_GPR4_CPU_STANDBYWFE_SHIFT 27 +#define IOMUXC_GPR_GPR4_CPU_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_CPU_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_CPU_STANDBYWFE_MASK) /* GPR5 Bit Fields */ -#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u -#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4 -#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u -#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5 -#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u -#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6 -#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u -#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7 -#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u -#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12 -#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u -#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19 -#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u -#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20 -#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u -#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21 -#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u -#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22 -#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u -#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24 -#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u -#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25 -#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u -#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26 -#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u -#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27 -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28 -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29 -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30 -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u -#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31 +#define IOMUXC_GPR_GPR5_CSI_MUX_CONTROL_MASK 0x10u +#define IOMUXC_GPR_GPR5_CSI_MUX_CONTROL_SHIFT 4 +#define IOMUXC_GPR_GPR5_LVDS_MUX_CONTROL_MASK 0x20u +#define IOMUXC_GPR_GPR5_LVDS_MUX_CONTROL_SHIFT 5 +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK 0x40u +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT 6 +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK 0x80u +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT 7 +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_MASK 0x1000u +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_SHIFT 12 +#define IOMUXC_GPR_GPR5_PCIE_BTNRST_MASK 0x80000u +#define IOMUXC_GPR_GPR5_PCIE_BTNRST_SHIFT 19 +#define IOMUXC_GPR_GPR5_WDOG3_MASK_MASK 0x100000u +#define IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT 20 +#define IOMUXC_GPR_GPR5_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u +#define IOMUXC_GPR_GPR5_LCDIF_CSI_VSYNC_SEL_SHIFT 21 +#define IOMUXC_GPR_GPR5_WDOG4_MASK_MASK 0x400000u +#define IOMUXC_GPR_GPR5_WDOG4_MASK_SHIFT 22 +#define IOMUXC_GPR_GPR5_GPT4_CAPIN1_SEL_MASK 0x1000000u +#define IOMUXC_GPR_GPR5_GPT4_CAPIN1_SEL_SHIFT 24 +#define IOMUXC_GPR_GPR5_GPT4_CAPIN2_SEL_MASK 0x2000000u +#define IOMUXC_GPR_GPR5_GPT4_CAPIN2_SEL_SHIFT 25 +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK 0x4000000u +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT 26 +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK 0x8000000u +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT 27 +#define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT1_MASK 0x10000000u +#define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT1_SHIFT 28 +#define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT2_MASK 0x20000000u +#define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT2_SHIFT 29 +#define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT3_MASK 0x40000000u +#define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT3_SHIFT 30 +#define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT4_MASK 0x80000000u +#define IOMUXC_GPR_GPR5_REF_1M_CLK_GPT4_SHIFT 31 /* GPR6 Bit Fields */ -#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u -#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0 -#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u -#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1 -#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u -#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2 -#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u -#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3 +#define IOMUXC_GPR_GPR6_ARCACHE_PXP6_MASK 0x1u +#define IOMUXC_GPR_GPR6_ARCACHE_PXP6_SHIFT 0 +#define IOMUXC_GPR_GPR6_AWCACHE_PXP6_MASK 0x2u +#define IOMUXC_GPR_GPR6_AWCACHE_PXP6_SHIFT 1 +#define IOMUXC_GPR_GPR6_ARCACHE_PXP6_EN_MASK 0x4u +#define IOMUXC_GPR_GPR6_ARCACHE_PXP6_EN_SHIFT 2 +#define IOMUXC_GPR_GPR6_AWCACHE_PXP6_EN_MASK 0x8u +#define IOMUXC_GPR_GPR6_AWCACHE_PXP6_EN_SHIFT 3 /* GPR7 Bit Fields */ -#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u -#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0 -#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u -#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1 -#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u -#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2 -#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u -#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3 -#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u -#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4 -#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK) -#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u -#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6 -#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u -#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7 -#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u -#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8 -#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u -#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9 -#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u -#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10 -#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK) -#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u -#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12 -#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u -#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13 +#define IOMUXC_GPR_GPR7_CHD1_EN_PWRUPLOAD_MASK 0x8u +#define IOMUXC_GPR_GPR7_CHD1_EN_PWRUPLOAD_SHIFT 3 +#define IOMUXC_GPR_GPR7_CHD1_TEST_MASK 0x30u +#define IOMUXC_GPR_GPR7_CHD1_TEST_SHIFT 4 +#define IOMUXC_GPR_GPR7_CHD1_TEST(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_CHD1_TEST_SHIFT))&IOMUXC_GPR_GPR7_CHD1_TEST_MASK) +#define IOMUXC_GPR_GPR7_CHD2_EN_PWRUPLOAD_LDO_USB_1p0_MASK 0x200u +#define IOMUXC_GPR_GPR7_CHD2_EN_PWRUPLOAD_LDO_USB_1p0_SHIFT 9 +#define IOMUXC_GPR_GPR7_CHD2_TEST_MASK 0xC00u +#define IOMUXC_GPR_GPR7_CHD2_TEST_SHIFT 10 +#define IOMUXC_GPR_GPR7_CHD2_TEST(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_CHD2_TEST_SHIFT))&IOMUXC_GPR_GPR7_CHD2_TEST_MASK) /* GPR8 Bit Fields */ -#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u -#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3 -#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK) -#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u -#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8 +#define IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP_MASK 0xF8u +#define IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP_SHIFT 3 +#define IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP_SHIFT))&IOMUXC_GPR_GPR8_DDR_PHY_CTRL_WAKE_UP_MASK) +#define IOMUXC_GPR_GPR8_DDR_PHY_DFI_INIT_START_MASK 0x100u +#define IOMUXC_GPR_GPR8_DDR_PHY_DFI_INIT_START_SHIFT 8 /* GPR9 Bit Fields */ -#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u -#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0 -#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu -#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1 -#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK) +#define IOMUXC_GPR_GPR9_TZASC1_MUX_CONTROL_MASK 0x1u +#define IOMUXC_GPR_GPR9_TZASC1_MUX_CONTROL_SHIFT 0 +#define IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD_MASK 0x3Eu +#define IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD_SHIFT 1 +#define IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD_SHIFT))&IOMUXC_GPR_GPR9_DDR_PHY_CTRL_PD_MASK) /* GPR10 Bit Fields */ -#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u -#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0 -#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u -#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1 -#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u -#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2 -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3 -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4 -#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_EN_MASK 0x4u +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_EN_SHIFT 2 +#define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_EN_MASK 0x8u +#define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_EN_SHIFT 3 +#define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR_MASK 0x3F0u +#define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR_SHIFT 4 +#define IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR10_OCRAM_EPDC_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR10_GPR10_LOCK_MASK 0xFFFFFC00u +#define IOMUXC_GPR_GPR10_GPR10_LOCK_SHIFT 10 +#define IOMUXC_GPR_GPR10_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR10_LOCK_SHIFT))&IOMUXC_GPR_GPR10_GPR10_LOCK_MASK) /* GPR11 Bit Fields */ -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK) -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11 -#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) +#define IOMUXC_GPR_GPR11_OCRAM_TZ_EN_MASK 0x1u +#define IOMUXC_GPR_GPR11_OCRAM_TZ_EN_SHIFT 0 +#define IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR_MASK 0x3Eu +#define IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR_SHIFT 1 +#define IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR11_OCRAM_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_EN_MASK 0x40u +#define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_EN_SHIFT 6 +#define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR_MASK 0x380u +#define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR_SHIFT 7 +#define IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR11_OCRAM_PXP_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR11_OCRAM_S_TZ_EN_MASK 0x400u +#define IOMUXC_GPR_GPR11_OCRAM_S_TZ_EN_SHIFT 10 +#define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_MASK 0x3800u +#define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_SHIFT 11 +#define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR11_GPR11_LOCK_MASK 0xFFFFC000u +#define IOMUXC_GPR_GPR11_GPR11_LOCK_SHIFT 14 +#define IOMUXC_GPR_GPR11_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR11_LOCK_SHIFT))&IOMUXC_GPR_GPR11_GPR11_LOCK_MASK) /* GPR12 Bit Fields */ -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3 -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4 -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u -#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5 -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK) -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK) -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 -#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK) +#define IOMUXC_GPR_GPR12_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u +#define IOMUXC_GPR_GPR12_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 +#define IOMUXC_GPR_GPR12_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u +#define IOMUXC_GPR_GPR12_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 +#define IOMUXC_GPR_GPR12_PCIE_PHY_SSC_EN_MASK 0x8u +#define IOMUXC_GPR_GPR12_PCIE_PHY_SSC_EN_SHIFT 3 +#define IOMUXC_GPR_GPR12_PCIE_PHY_CMN_REG_RST_MASK 0x10u +#define IOMUXC_GPR_GPR12_PCIE_PHY_CMN_REG_RST_SHIFT 4 +#define IOMUXC_GPR_GPR12_PCIE_PHY_REFCLK_SEL_MASK 0x20u +#define IOMUXC_GPR_GPR12_PCIE_PHY_REFCLK_SEL_SHIFT 5 +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_PCIE_CTRL_DEVICE_TYPE_MASK) +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK) +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 +#define IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_PCIE_CTRL_DIAG_CTRL_BUS_MASK) /* GPR13 Bit Fields */ -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12 -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u -#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14 -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u -#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK) -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK) -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u -#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK 0x1u +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT 0 +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK 0x2u +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT 1 +#define IOMUXC_GPR_GPR13_ARCACHE_PXP_MASK 0x4u +#define IOMUXC_GPR_GPR13_ARCACHE_PXP_SHIFT 2 +#define IOMUXC_GPR_GPR13_AWCACHE_PXP_MASK 0x8u +#define IOMUXC_GPR_GPR13_AWCACHE_PXP_SHIFT 3 +#define IOMUXC_GPR_GPR13_ARCACHE_PCIE_MASK 0x10u +#define IOMUXC_GPR_GPR13_ARCACHE_PCIE_SHIFT 4 +#define IOMUXC_GPR_GPR13_AWCACHE_PCIE_MASK 0x20u +#define IOMUXC_GPR_GPR13_AWCACHE_PCIE_SHIFT 5 +#define IOMUXC_GPR_GPR13_ARCACHE_LCDIF_MASK 0x40u +#define IOMUXC_GPR_GPR13_ARCACHE_LCDIF_SHIFT 6 +#define IOMUXC_GPR_GPR13_ARCACHE_EPDC_MASK 0x80u +#define IOMUXC_GPR_GPR13_ARCACHE_EPDC_SHIFT 7 +#define IOMUXC_GPR_GPR13_ARCACHE_PXP_EN_MASK 0x100u +#define IOMUXC_GPR_GPR13_ARCACHE_PXP_EN_SHIFT 8 +#define IOMUXC_GPR_GPR13_AWCACHE_PXP_EN_MASK 0x200u +#define IOMUXC_GPR_GPR13_AWCACHE_PXP_EN_SHIFT 9 +#define IOMUXC_GPR_GPR13_ARCACHE_PCIE_EN_MASK 0x400u +#define IOMUXC_GPR_GPR13_ARCACHE_PCIE_EN_SHIFT 10 +#define IOMUXC_GPR_GPR13_AWCACHE_PCIE_EN_MASK 0x800u +#define IOMUXC_GPR_GPR13_AWCACHE_PCIE_EN_SHIFT 11 +#define IOMUXC_GPR_GPR13_ARCACHE_LCDIF_EN_MASK 0x1000u +#define IOMUXC_GPR_GPR13_ARCACHE_LCDIF_EN_SHIFT 12 +#define IOMUXC_GPR_GPR13_ARCACHE_EPDC_EN_MASK 0x2000u +#define IOMUXC_GPR_GPR13_ARCACHE_EPDC_EN_SHIFT 13 +#define IOMUXC_GPR_GPR13_AWCACHE_EPDC_MASK 0x4000u +#define IOMUXC_GPR_GPR13_AWCACHE_EPDC_SHIFT 14 +#define IOMUXC_GPR_GPR13_AWCACHE_EPDC_EN_MASK 0x8000u +#define IOMUXC_GPR_GPR13_AWCACHE_EPDC_EN_SHIFT 15 +#define IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u +#define IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 +#define IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_PCIE_PHY_AFC_CODE_OUT_CH0_MASK) +#define IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND_MASK 0xF000000u +#define IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND_SHIFT 24 +#define IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_PCIE_PHY_VCO_BAND_MASK) +#define IOMUXC_GPR_GPR13_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u +#define IOMUXC_GPR_GPR13_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 +#define IOMUXC_GPR_GPR13_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u +#define IOMUXC_GPR_GPR13_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 +#define IOMUXC_GPR_GPR13_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u +#define IOMUXC_GPR_GPR13_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 +#define IOMUXC_GPR_GPR13_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u +#define IOMUXC_GPR_GPR13_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 /* GPR14 Bit Fields */ -#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u -#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0 -#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u -#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1 +#define IOMUXC_GPR_GPR14_SIM1_SIMV2_EMV_SEL_MASK 0x1u +#define IOMUXC_GPR_GPR14_SIM1_SIMV2_EMV_SEL_SHIFT 0 +#define IOMUXC_GPR_GPR14_SIM2_SIMV2_EMV_SEL_MASK 0x2u +#define IOMUXC_GPR_GPR14_SIM2_SIMV2_EMV_SEL_SHIFT 1 /* GPR15 Bit Fields */ -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0 -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1 -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2 -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK) -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16 -#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK) +#define IOMUXC_GPR_GPR15_LVDS_I_VBLK_FLAG_MASK 0x1u +#define IOMUXC_GPR_GPR15_LVDS_I_VBLK_FLAG_SHIFT 0 +#define IOMUXC_GPR_GPR15_LVDS_I_AUTO_SEL_MASK 0x2u +#define IOMUXC_GPR_GPR15_LVDS_I_AUTO_SEL_SHIFT 1 +#define IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu +#define IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET_SHIFT 2 +#define IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_LVDS_I_DESKEW_CNT_SET_MASK) +#define IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u +#define IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET_SHIFT 16 +#define IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_LVDS_I_LOCK_PPM_SET_MASK) /* GPR16 Bit Fields */ -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK) -#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2 -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6 -#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK) -#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u -#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10 -#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u -#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11 -#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12 -#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13 -#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK) -#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16 -#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17 -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19 -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK) -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21 -#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22 -#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u -#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23 +#define IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR_MASK 0x3u +#define IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR_SHIFT 0 +#define IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_LVDS_SKEW_REG_CUR_MASK) +#define IOMUXC_GPR_GPR16_LVDS_SEL_DATABF_MASK 0x4u +#define IOMUXC_GPR_GPR16_LVDS_SEL_DATABF_SHIFT 2 +#define IOMUXC_GPR_GPR16_LVDS_CNTB_TDLY_MASK 0x8u +#define IOMUXC_GPR_GPR16_LVDS_CNTB_TDLY_SHIFT 3 +#define IOMUXC_GPR_GPR16_LVDS_SKEW_EN_H_MASK 0x10u +#define IOMUXC_GPR_GPR16_LVDS_SKEW_EN_H_SHIFT 4 +#define IOMUXC_GPR_GPR16_LVDS_SKEWINI_MASK 0x20u +#define IOMUXC_GPR_GPR16_LVDS_SKEWINI_SHIFT 5 +#define IOMUXC_GPR_GPR16_LVDS_SK_BIAS_MASK 0x3C0u +#define IOMUXC_GPR_GPR16_LVDS_SK_BIAS_SHIFT 6 +#define IOMUXC_GPR_GPR16_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_LVDS_SK_BIAS_MASK) +#define IOMUXC_GPR_GPR16_LVDS_AUTO_DSK_SEL_MASK 0x400u +#define IOMUXC_GPR_GPR16_LVDS_AUTO_DSK_SEL_SHIFT 10 +#define IOMUXC_GPR_GPR16_LVDS_LOCK_CNT_MASK 0x800u +#define IOMUXC_GPR_GPR16_LVDS_LOCK_CNT_SHIFT 11 +#define IOMUXC_GPR_GPR16_LVDS_OUTCON_MASK 0x1000u +#define IOMUXC_GPR_GPR16_LVDS_OUTCON_SHIFT 12 +#define IOMUXC_GPR_GPR16_LVDS_FC_CODE_MASK 0xE000u +#define IOMUXC_GPR_GPR16_LVDS_FC_CODE_SHIFT 13 +#define IOMUXC_GPR_GPR16_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_LVDS_FC_CODE_MASK) +#define IOMUXC_GPR_GPR16_LVDS_SRC_TRH_MASK 0x10000u +#define IOMUXC_GPR_GPR16_LVDS_SRC_TRH_SHIFT 16 +#define IOMUXC_GPR_GPR16_LVDS_VOD_HIGH_S_MASK 0x20000u +#define IOMUXC_GPR_GPR16_LVDS_VOD_HIGH_S_SHIFT 17 +#define IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT_MASK 0x180000u +#define IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT_SHIFT 19 +#define IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_LVDS_CNNCT_CNT_MASK) +#define IOMUXC_GPR_GPR16_LVDS_CNNCT_MODE_SEL_MASK 0x200000u +#define IOMUXC_GPR_GPR16_LVDS_CNNCT_MODE_SEL_SHIFT 21 +#define IOMUXC_GPR_GPR16_LVDS_FLT_CNT_MASK 0x400000u +#define IOMUXC_GPR_GPR16_LVDS_FLT_CNT_SHIFT 22 +#define IOMUXC_GPR_GPR16_LVDS_VOD_ONLY_CNT_MASK 0x800000u +#define IOMUXC_GPR_GPR16_LVDS_VOD_ONLY_CNT_SHIFT 23 /* GPR17 Bit Fields */ -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0 -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK) -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8 -#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK) +#define IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H_MASK 0xFFu +#define IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H_SHIFT 0 +#define IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_LVDS_CNT_PEN_H_MASK) +#define IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H_MASK 0xFF00u +#define IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H_SHIFT 8 +#define IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_LVDS_CNT_VOD_H_MASK) /* GPR18 Bit Fields */ -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK) -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26 -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27 -#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28 -#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u -#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL_MASK 0x7u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL_SHIFT 0 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_CH_SEL_MASK) +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV_MASK 0x18u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV_SHIFT 3 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_DATA_INV_MASK) +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV_MASK 0x60u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV_SHIFT 5 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_CLK_INV_MASK) +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_SKEW_CTRL_MASK) +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN_SHIFT 16 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_USER_PATTERN_MASK) +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL_SHIFT 24 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_LVDS_I_BIST_PAT_SEL_MASK) +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_EN_MASK 0x4000000u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_EN_SHIFT 26 +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_RESETB_MASK 0x8000000u +#define IOMUXC_GPR_GPR18_LVDS_I_BIST_RESETB_SHIFT 27 +#define IOMUXC_GPR_GPR18_LVDS_DLYS_BST_MASK 0x10000000u +#define IOMUXC_GPR_GPR18_LVDS_DLYS_BST_SHIFT 28 +#define IOMUXC_GPR_GPR18_LVDS_SKINI_BST_MASK 0x20000000u +#define IOMUXC_GPR_GPR18_LVDS_SKINI_BST_SHIFT 29 /* GPR19 Bit Fields */ -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0 -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8 -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK) -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u -#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16 -#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u -#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17 +#define IOMUXC_GPR_GPR19_LVDS_O_BIST_STATUS_MASK 0x1u +#define IOMUXC_GPR_GPR19_LVDS_O_BIST_STATUS_SHIFT 0 +#define IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u +#define IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT_SHIFT 8 +#define IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_LVDS_O_BIST_ERR_COUNT_MASK) +#define IOMUXC_GPR_GPR19_LVDS_O_BIST_SYNC_MASK 0x10000u +#define IOMUXC_GPR_GPR19_LVDS_O_BIST_SYNC_SHIFT 16 +#define IOMUXC_GPR_GPR19_LVDS_MON_FOR_CNNCT_MASK 0x20000u +#define IOMUXC_GPR_GPR19_LVDS_MON_FOR_CNNCT_SHIFT 17 /* GPR20 Bit Fields */ -#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu -#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0 -#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK) -#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u -#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8 -#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK) -#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u -#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16 -#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK) -#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u -#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24 -#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u -#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25 -#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u -#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27 -#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK) +#define IOMUXC_GPR_GPR20_LVDS_P_MASK 0x3Fu +#define IOMUXC_GPR_GPR20_LVDS_P_SHIFT 0 +#define IOMUXC_GPR_GPR20_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_LVDS_P_MASK) +#define IOMUXC_GPR_GPR20_LVDS_M_MASK 0x3F00u +#define IOMUXC_GPR_GPR20_LVDS_M_SHIFT 8 +#define IOMUXC_GPR_GPR20_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_LVDS_M_MASK) +#define IOMUXC_GPR_GPR20_LVDS_S_MASK 0x30000u +#define IOMUXC_GPR_GPR20_LVDS_S_SHIFT 16 +#define IOMUXC_GPR_GPR20_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_LVDS_S_MASK) +#define IOMUXC_GPR_GPR20_LVDS_VSEL_MASK 0x1000000u +#define IOMUXC_GPR_GPR20_LVDS_VSEL_SHIFT 24 +#define IOMUXC_GPR_GPR20_LVDS_CK_POL_SEL_MASK 0x2000000u +#define IOMUXC_GPR_GPR20_LVDS_CK_POL_SEL_SHIFT 25 +#define IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u +#define IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY_SHIFT 27 +#define IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_LVDS_I_TX2801X_DUMMY_MASK) /* GPR21 Bit Fields */ -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK) -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15 -#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK) +#define IOMUXC_GPR_GPR21_LVDS_SKC0_MASK 0x7u +#define IOMUXC_GPR_GPR21_LVDS_SKC0_SHIFT 0 +#define IOMUXC_GPR_GPR21_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC0_MASK) +#define IOMUXC_GPR_GPR21_LVDS_SKC1_MASK 0x38u +#define IOMUXC_GPR_GPR21_LVDS_SKC1_SHIFT 3 +#define IOMUXC_GPR_GPR21_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC1_MASK) +#define IOMUXC_GPR_GPR21_LVDS_SKC2_MASK 0x1C0u +#define IOMUXC_GPR_GPR21_LVDS_SKC2_SHIFT 6 +#define IOMUXC_GPR_GPR21_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC2_MASK) +#define IOMUXC_GPR_GPR21_LVDS_SKCCK_MASK 0xE00u +#define IOMUXC_GPR_GPR21_LVDS_SKCCK_SHIFT 9 +#define IOMUXC_GPR_GPR21_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKCCK_MASK) +#define IOMUXC_GPR_GPR21_LVDS_SKC3_MASK 0x7000u +#define IOMUXC_GPR_GPR21_LVDS_SKC3_SHIFT 12 +#define IOMUXC_GPR_GPR21_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC3_MASK) +#define IOMUXC_GPR_GPR21_LVDS_SKC4_MASK 0x38000u +#define IOMUXC_GPR_GPR21_LVDS_SKC4_SHIFT 15 +#define IOMUXC_GPR_GPR21_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_LVDS_SKC4_MASK) #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19 /* GPR22 Bit Fields */ -#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u -#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16 -#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK) -#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u -#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24 -#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u -#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25 -#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u -#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26 -#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u -#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27 -#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u -#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28 -#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u -#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29 -#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u -#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31 +#define IOMUXC_GPR_GPR22_DDRC_MRR_DATA_MASK 0xFF0000u +#define IOMUXC_GPR_GPR22_DDRC_MRR_DATA_SHIFT 16 +#define IOMUXC_GPR_GPR22_DDRC_MRR_DATA(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_DDRC_MRR_DATA_SHIFT))&IOMUXC_GPR_GPR22_DDRC_MRR_DATA_MASK) +#define IOMUXC_GPR_GPR22_DDRC_MRR_VALID_MASK 0x1000000u +#define IOMUXC_GPR_GPR22_DDRC_MRR_VALID_SHIFT 24 +#define IOMUXC_GPR_GPR22_DFI_INIT_COMPLETE_MASK 0x2000000u +#define IOMUXC_GPR_GPR22_DFI_INIT_COMPLETE_SHIFT 25 +#define IOMUXC_GPR_GPR22_CHD2_DVDD_STABLE_MASK 0x4000000u +#define IOMUXC_GPR_GPR22_CHD2_DVDD_STABLE_SHIFT 26 +#define IOMUXC_GPR_GPR22_CHD2_ISO_ENA_1_MASK 0x8000000u +#define IOMUXC_GPR_GPR22_CHD2_ISO_ENA_1_SHIFT 27 +#define IOMUXC_GPR_GPR22_CHD1_DVDD_STABLE_MASK 0x10000000u +#define IOMUXC_GPR_GPR22_CHD1_DVDD_STABLE_SHIFT 28 +#define IOMUXC_GPR_GPR22_CHD1_ISO_ENA_1_MASK 0x20000000u +#define IOMUXC_GPR_GPR22_CHD1_ISO_ENA_1_SHIFT 29 +#define IOMUXC_GPR_GPR22_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u +#define IOMUXC_GPR_GPR22_PCIE_PHY_PLL_LOCKED_SHIFT 31 /*! * @} */ /* end of group IOMUXC_GPR_Register_Masks */ - /* IOMUXC_GPR - Peripheral instance base addresses */ /** Peripheral IOMUXC_GPR base address */ #define IOMUXC_GPR_BASE (0x30340000u) /** Peripheral IOMUXC_GPR base pointer */ #define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) #define IOMUXC_GPR_BASE_PTR (IOMUXC_GPR) -/** Array initializer of IOMUXC_GPR peripheral base adresses */ +/** Array initializer of IOMUXC_GPR peripheral base addresses */ #define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } /** Array initializer of IOMUXC_GPR peripheral base pointers */ #define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } - +/** Interrupt vectors for the IOMUXC_GPR peripheral type */ +#define IOMUXC_GPR_IRQS { GPR_IRQn } /* ---------------------------------------------------------------------------- -- IOMUXC_GPR - Register accessor macros ---------------------------------------------------------------------------- */ @@ -77591,7 +27209,6 @@ typedef struct { #define IOMUXC_GPR_GPR20 IOMUXC_GPR_GPR20_REG(IOMUXC_GPR_BASE_PTR) #define IOMUXC_GPR_GPR21 IOMUXC_GPR_GPR21_REG(IOMUXC_GPR_BASE_PTR) #define IOMUXC_GPR_GPR22 IOMUXC_GPR_GPR22_REG(IOMUXC_GPR_BASE_PTR) - /*! * @} */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ @@ -77601,7 +27218,6 @@ typedef struct { * @} */ /* end of group IOMUXC_GPR_Peripheral */ - /* ---------------------------------------------------------------------------- -- IOMUXC_LPSR Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -77634,7 +27250,6 @@ typedef struct { __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO06; /**< SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register, offset: 0x48 */ __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO07; /**< SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register, offset: 0x4C */ } IOMUXC_LPSR_Type, *IOMUXC_LPSR_MemMapPtr; - /* ---------------------------------------------------------------------------- -- IOMUXC_LPSR - Register accessor macros ---------------------------------------------------------------------------- */ @@ -77670,8 +27285,6 @@ typedef struct { /*! * @} */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- IOMUXC_LPSR Register Masks ---------------------------------------------------------------------------- */ @@ -77890,18 +27503,16 @@ typedef struct { * @} */ /* end of group IOMUXC_LPSR_Register_Masks */ - /* IOMUXC_LPSR - Peripheral instance base addresses */ /** Peripheral IOMUXC_LPSR base address */ #define IOMUXC_LPSR_BASE (0x302C0000u) /** Peripheral IOMUXC_LPSR base pointer */ #define IOMUXC_LPSR ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE) #define IOMUXC_LPSR_BASE_PTR (IOMUXC_LPSR) -/** Array initializer of IOMUXC_LPSR peripheral base adresses */ +/** Array initializer of IOMUXC_LPSR peripheral base addresses */ #define IOMUXC_LPSR_BASE_ADDRS { IOMUXC_LPSR_BASE } /** Array initializer of IOMUXC_LPSR peripheral base pointers */ #define IOMUXC_LPSR_BASE_PTRS { IOMUXC_LPSR } - /* ---------------------------------------------------------------------------- -- IOMUXC_LPSR - Register accessor macros ---------------------------------------------------------------------------- */ @@ -77934,7 +27545,6 @@ typedef struct { #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(IOMUXC_LPSR_BASE_PTR) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_REG(IOMUXC_LPSR_BASE_PTR) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(IOMUXC_LPSR_BASE_PTR) - /*! * @} */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */ @@ -77944,6 +27554,362 @@ typedef struct { * @} */ /* end of group IOMUXC_LPSR_Peripheral */ +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_GPR_Peripheral_Access_Layer IOMUXC_LPSR_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_LPSR_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t IOMUXC_LPSR_GPR0; /**< IOMUXC_LPSR General Purpose Register 0, offset: 0x0 */ + __IO uint32_t IOMUXC_LPSR_GPR1; /**< IOMUXC_LPSR General Purpose Register 1, offset: 0x4 */ + __IO uint32_t IOMUXC_LPSR_GPR2; /**< IOMUXC_LPSR General Purpose Register 2, offset: 0x8 */ + __IO uint32_t IOMUXC_LPSR_GPR3; /**< IOMUXC_LPSR General Purpose Register 3, offset: 0xC */ + __IO uint32_t IOMUXC_LPSR_GPR4; /**< IOMUXC_LPSR General Purpose Register 4, offset: 0x10 */ + __IO uint32_t IOMUXC_LPSR_GPR5; /**< IOMUXC_LPSR General Purpose Register 5, offset: 0x14 */ + __IO uint32_t IOMUXC_LPSR_GPR6; /**< IOMUXC_LPSR General Purpose Register 6, offset: 0x18 */ + __IO uint32_t IOMUXC_LPSR_GPR7; /**< IOMUXC_LPSR General Purpose Register 7, offset: 0x1C */ + __IO uint32_t IOMUXC_LPSR_GPR8; /**< IOMUXC_LPSR General Purpose Register 8, offset: 0x20 */ + __IO uint32_t IOMUXC_LPSR_GPR9; /**< IOMUXC_LPSR General Purpose Register 9, offset: 0x24 */ + __IO uint32_t IOMUXC_LPSR_GPR10; /**< IOMUXC_LPSR General Purpose Register 10, offset: 0x28 */ + __IO uint32_t IOMUXC_LPSR_GPR11; /**< IOMUXC_LPSR General Purpose Register 11, offset: 0x2C */ + __IO uint32_t IOMUXC_LPSR_GPR12; /**< IOMUXC_LPSR General Purpose Register 12, offset: 0x30 */ + __IO uint32_t IOMUXC_LPSR_GPR13; /**< IOMUXC_LPSR General Purpose Register 13, offset: 0x34 */ + __IO uint32_t IOMUXC_LPSR_GPR14; /**< IOMUXC_LPSR General Purpose Register 14, offset: 0x38 */ + __IO uint32_t IOMUXC_LPSR_GPR15; /**< IOMUXC_LPSR General Purpose Register 15, offset: 0x3C */ + __IO uint32_t IOMUXC_LPSR_GPR16; /**< IOMUXC_LPSR General Purpose Register 16, offset: 0x40 */ + __IO uint32_t IOMUXC_LPSR_GPR17; /**< IOMUXC_LPSR General Purpose Register 17, offset: 0x44 */ + __IO uint32_t IOMUXC_LPSR_GPR18; /**< IOMUXC_LPSR General Purpose Register 18, offset: 0x48 */ + __IO uint32_t IOMUXC_LPSR_GPR19; /**< IOMUXC_LPSR General Purpose Register 19, offset: 0x4C */ + __IO uint32_t IOMUXC_LPSR_GPR20; /**< IOMUXC_LPSR General Purpose Register 20, offset: 0x50 */ + __IO uint32_t IOMUXC_LPSR_GPR21; /**< IOMUXC_LPSR General Purpose Register 21, offset: 0x54 */ + __IO uint32_t IOMUXC_LPSR_GPR22; /**< IOMUXC_LPSR General Purpose Register 22, offset: 0x58 */ +} IOMUXC_LPSR_GPR_Type, *IOMUXC_LPSR_GPR_MemMapPtr; +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR_GPR - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_GPR_Register_Accessor_Macros IOMUXC_LPSR_GPR - Register accessor macros + * @{ + */ + + +/* IOMUXC_LPSR_GPR - Register accessors */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_REG(base) ((base)->IOMUXC_LPSR_GPR0) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_REG(base) ((base)->IOMUXC_LPSR_GPR1) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_REG(base) ((base)->IOMUXC_LPSR_GPR2) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_REG(base) ((base)->IOMUXC_LPSR_GPR3) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_REG(base) ((base)->IOMUXC_LPSR_GPR4) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_REG(base) ((base)->IOMUXC_LPSR_GPR5) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_REG(base) ((base)->IOMUXC_LPSR_GPR6) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_REG(base) ((base)->IOMUXC_LPSR_GPR7) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_REG(base) ((base)->IOMUXC_LPSR_GPR8) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_REG(base) ((base)->IOMUXC_LPSR_GPR9) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_REG(base) ((base)->IOMUXC_LPSR_GPR10) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_REG(base) ((base)->IOMUXC_LPSR_GPR11) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_REG(base) ((base)->IOMUXC_LPSR_GPR12) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_REG(base) ((base)->IOMUXC_LPSR_GPR13) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_REG(base) ((base)->IOMUXC_LPSR_GPR14) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_REG(base) ((base)->IOMUXC_LPSR_GPR15) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_REG(base) ((base)->IOMUXC_LPSR_GPR16) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_REG(base) ((base)->IOMUXC_LPSR_GPR17) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_REG(base) ((base)->IOMUXC_LPSR_GPR18) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_REG(base) ((base)->IOMUXC_LPSR_GPR19) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_REG(base) ((base)->IOMUXC_LPSR_GPR20) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_REG(base) ((base)->IOMUXC_LPSR_GPR21) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_REG(base) ((base)->IOMUXC_LPSR_GPR22) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_GPR_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_GPR_Register_Masks IOMUXC_LPSR_GPR Register Masks + * @{ + */ + +/* IOMUXC_LPSR_GPR0 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_MASK) +/* IOMUXC_LPSR_GPR1 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_GP_MASK) +/* IOMUXC_LPSR_GPR2 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_GP_MASK) +/* IOMUXC_LPSR_GPR3 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP_MASK 0xFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_GP_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO_MASK 0xFFFF0000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO_SHIFT 16 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_RO_MASK) +/* IOMUXC_LPSR_GPR4 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP_MASK 0xFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_GP_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO_MASK 0xFFFF0000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO_SHIFT 16 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_RO_MASK) +/* IOMUXC_LPSR_GPR5 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_GP_MASK) +/* IOMUXC_LPSR_GPR6 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_GP_MASK) +/* IOMUXC_LPSR_GPR7 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_GP_MASK) +/* IOMUXC_LPSR_GPR8 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_GP_MASK) +/* IOMUXC_LPSR_GPR9 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_STICKY_MASK) +/* IOMUXC_LPSR_GPR10 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK_MASK 0xFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_LOCK_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY_MASK 0xFFFF0000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY_SHIFT 16 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_STICKY_MASK) +/* IOMUXC_LPSR_GPR11 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK_MASK 0xFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_LOCK_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY_MASK 0xFFFF0000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY_SHIFT 16 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_STICKY_MASK) +/* IOMUXC_LPSR_GPR12 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_GP_MASK) +/* IOMUXC_LPSR_GPR13 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP_MASK 0xFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_GP_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO_MASK 0xFFFF0000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO_SHIFT 16 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_RO_MASK) +/* IOMUXC_LPSR_GPR14 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_GP_MASK) +/* IOMUXC_LPSR_GPR15 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_GP_MASK) +/* IOMUXC_LPSR_GPR16 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_GP_MASK) +/* IOMUXC_LPSR_GPR17 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_GP_MASK) +/* IOMUXC_LPSR_GPR18 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_GP_MASK) +/* IOMUXC_LPSR_GPR19 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_GP_MASK) +/* IOMUXC_LPSR_GPR20 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE_MASK 0x3u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_DSE_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_SRE_MASK 0x4u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_SRE_SHIFT 2 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_HYS_MASK 0x8u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_HYS_SHIFT 3 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PE_MASK 0x10u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PE_SHIFT 4 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS_MASK 0x60u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS_SHIFT 5 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_PS_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_MUX_CTL_MASK 0x80u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO08_MUX_CTL_SHIFT 7 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE_MASK 0x300u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE_SHIFT 8 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_DSE_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_SRE_MASK 0x400u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_SRE_SHIFT 10 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_HYS_MASK 0x800u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_HYS_SHIFT 11 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PE_MASK 0x1000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PE_SHIFT 12 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS_MASK 0x6000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS_SHIFT 13 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_PS_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_MUX_CTL_MASK 0x8000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO09_MUX_CTL_SHIFT 15 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE_MASK 0x30000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE_SHIFT 16 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_DSE_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_SRE_MASK 0x40000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_SRE_SHIFT 18 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_HYS_MASK 0x80000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_HYS_SHIFT 19 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PE_MASK 0x100000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PE_SHIFT 20 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS_MASK 0x600000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS_SHIFT 21 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_PS_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_MUX_CTL_MASK 0x800000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO10_MUX_CTL_SHIFT 23 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE_MASK 0x3000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE_SHIFT 24 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_DSE_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_SRE_MASK 0x4000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_SRE_SHIFT 26 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_HYS_MASK 0x8000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_HYS_SHIFT 27 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PE_MASK 0x10000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PE_SHIFT 28 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS_MASK 0x60000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS_SHIFT 29 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_PS_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_MUX_CTL_MASK 0x80000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_GPIO1_IO11_MUX_CTL_SHIFT 31 +/* IOMUXC_LPSR_GPR21 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE_MASK 0x3u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_DSE_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_SRE_MASK 0x4u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_SRE_SHIFT 2 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_HYS_MASK 0x8u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_HYS_SHIFT 3 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PE_MASK 0x10u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PE_SHIFT 4 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS_MASK 0x60u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS_SHIFT 5 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_PS_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_MUX_CTL_MASK 0x80u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO12_MUX_CTL_SHIFT 7 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE_MASK 0x300u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE_SHIFT 8 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_DSE_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_SRE_MASK 0x400u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_SRE_SHIFT 10 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_HYS_MASK 0x800u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_HYS_SHIFT 11 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PE_MASK 0x1000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PE_SHIFT 12 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS_MASK 0x6000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS_SHIFT 13 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_PS_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_MUX_CTL_MASK 0x8000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO13_MUX_CTL_SHIFT 15 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE_MASK 0x30000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE_SHIFT 16 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_DSE_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_SRE_MASK 0x40000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_SRE_SHIFT 18 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_HYS_MASK 0x80000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_HYS_SHIFT 19 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PE_MASK 0x100000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PE_SHIFT 20 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS_MASK 0x600000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS_SHIFT 21 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_PS_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_MUX_CTL_MASK 0x800000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO14_MUX_CTL_SHIFT 23 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE_MASK 0x3000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE_SHIFT 24 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_DSE_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_SRE_MASK 0x4000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_SRE_SHIFT 26 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_HYS_MASK 0x8000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_HYS_SHIFT 27 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PE_MASK 0x10000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PE_SHIFT 28 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS_MASK 0x60000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS_SHIFT 29 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_PS_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_MUX_CTL_MASK 0x80000000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_GPIO1_IO15_MUX_CTL_SHIFT 31 +/* IOMUXC_LPSR_GPR22 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP_MASK 0xFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_GP_MASK) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO_MASK 0xFFFF0000u +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO_SHIFT 16 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO_SHIFT))&IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_RO_MASK) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_GPR_Register_Masks */ + +/* IOMUXC_LPSR_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_LPSR_GPR base address */ +#define IOMUXC_LPSR_GPR_BASE (0x30270000u) +/** Peripheral IOMUXC_LPSR_GPR base pointer */ +#define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) +#define IOMUXC_LPSR_GPR_BASE_PTR (IOMUXC_LPSR_GPR) +/** Array initializer of IOMUXC_LPSR_GPR peripheral base addresses */ +#define IOMUXC_LPSR_GPR_BASE_ADDRS { IOMUXC_LPSR_GPR_BASE } +/** Array initializer of IOMUXC_LPSR_GPR peripheral base pointers */ +#define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR } +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR_GPR - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_GPR_Register_Accessor_Macros IOMUXC_LPSR_GPR - Register accessor macros + * @{ + */ + + +/* IOMUXC_LPSR_GPR - Register instance definitions */ +/* IOMUXC_LPSR_GPR */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_REG(IOMUXC_LPSR_GPR_BASE_PTR) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22 IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_REG(IOMUXC_LPSR_GPR_BASE_PTR) +/*! + * @} + */ /* end of group IOMUXC_LPSR_GPR_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group IOMUXC_LPSR_GPR_Peripheral */ /* ---------------------------------------------------------------------------- -- KPP Peripheral Access Layer @@ -77961,7 +27927,6 @@ typedef struct { __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ } KPP_Type, *KPP_MemMapPtr; - /* ---------------------------------------------------------------------------- -- KPP - Register accessor macros ---------------------------------------------------------------------------- */ @@ -77981,8 +27946,6 @@ typedef struct { /*! * @} */ /* end of group KPP_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- KPP Register Masks ---------------------------------------------------------------------------- */ @@ -78031,18 +27994,18 @@ typedef struct { * @} */ /* end of group KPP_Register_Masks */ - /* KPP - Peripheral instance base addresses */ /** Peripheral KPP base address */ #define KPP_BASE (0x30320000u) /** Peripheral KPP base pointer */ #define KPP ((KPP_Type *)KPP_BASE) #define KPP_BASE_PTR (KPP) -/** Array initializer of KPP peripheral base adresses */ +/** Array initializer of KPP peripheral base addresses */ #define KPP_BASE_ADDRS { KPP_BASE } /** Array initializer of KPP peripheral base pointers */ #define KPP_BASE_PTRS { KPP } - +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } /* ---------------------------------------------------------------------------- -- KPP - Register accessor macros ---------------------------------------------------------------------------- */ @@ -78059,7 +28022,6 @@ typedef struct { #define KPP_KPSR KPP_KPSR_REG(KPP_BASE_PTR) #define KPP_KDDR KPP_KDDR_REG(KPP_BASE_PTR) #define KPP_KPDR KPP_KPDR_REG(KPP_BASE_PTR) - /*! * @} */ /* end of group KPP_Register_Accessor_Macros */ @@ -78069,7 +28031,6 @@ typedef struct { * @} */ /* end of group KPP_Peripheral */ - /* ---------------------------------------------------------------------------- -- LCDIF Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -78143,7 +28104,7 @@ typedef struct { uint8_t RESERVED_21[12]; __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ uint8_t RESERVED_22[12]; - __IO uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ uint8_t RESERVED_23[12]; __I uint32_t VERSION; /**< LCD Interface Version Register, offset: 0x1C0 */ uint8_t RESERVED_24[12]; @@ -78167,13 +28128,12 @@ typedef struct { uint8_t RESERVED_33[12]; __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ uint8_t RESERVED_34[12]; - __I uint32_t DEBUG3; /**< eLCDIF Interface Debug3 Register, offset: 0x270 */ + __IO uint32_t DEBUG3; /**< eLCDIF Interface Debug3 Register, offset: 0x270 */ uint8_t RESERVED_35[12]; - __I uint32_t DEBUG4; /**< LCD Interface Debug4, offset: 0x280 */ + __IO uint32_t DEBUG4; /**< LCD Interface Debug4 , offset: 0x280 */ uint8_t RESERVED_36[12]; - __I uint32_t DEBUG5; /**< LCD Interface Debug5, offset: 0x290 */ + __IO uint32_t DEBUG5; /**< LCD Interface Debug5 , offset: 0x290 */ } LCDIF_Type, *LCDIF_MemMapPtr; - /* ---------------------------------------------------------------------------- -- LCDIF - Register accessor macros ---------------------------------------------------------------------------- */ @@ -78243,8 +28203,6 @@ typedef struct { /*! * @} */ /* end of group LCDIF_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- LCDIF Register Masks ---------------------------------------------------------------------------- */ @@ -79363,7 +29321,6 @@ typedef struct { * @} */ /* end of group LCDIF_Register_Masks */ - /* LCDIF - Peripheral instance base addresses */ /** Peripheral LCDIF1 base address */ #define LCDIF1_BASE (0x30730000u) @@ -79375,11 +29332,10 @@ typedef struct { /** Peripheral LCDIF2 base pointer */ #define LCDIF2 ((LCDIF_Type *)LCDIF2_BASE) #define LCDIF2_BASE_PTR (LCDIF2) -/** Array initializer of LCDIF peripheral base adresses */ +/** Array initializer of LCDIF peripheral base addresses */ #define LCDIF_BASE_ADDRS { LCDIF1_BASE, LCDIF2_BASE } /** Array initializer of LCDIF peripheral base pointers */ #define LCDIF_BASE_PTRS { LCDIF1, LCDIF2 } - /* ---------------------------------------------------------------------------- -- LCDIF - Register accessor macros ---------------------------------------------------------------------------- */ @@ -79501,7 +29457,6 @@ typedef struct { #define LCDIF2_DEBUG3 LCDIF_DEBUG3_REG(LCDIF2_BASE_PTR) #define LCDIF2_DEBUG4 LCDIF_DEBUG4_REG(LCDIF2_BASE_PTR) #define LCDIF2_DEBUG5 LCDIF_DEBUG5_REG(LCDIF2_BASE_PTR) - /*! * @} */ /* end of group LCDIF_Register_Accessor_Macros */ @@ -79511,7 +29466,6 @@ typedef struct { * @} */ /* end of group LCDIF_Peripheral */ - /* ---------------------------------------------------------------------------- -- LMEM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -79533,7 +29487,6 @@ typedef struct { __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */ __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */ } LMEM_Type, *LMEM_MemMapPtr; - /* ---------------------------------------------------------------------------- -- LMEM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -79557,8 +29510,6 @@ typedef struct { /*! * @} */ /* end of group LMEM_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- LMEM Register Masks ---------------------------------------------------------------------------- */ @@ -79673,18 +29624,16 @@ typedef struct { * @} */ /* end of group LMEM_Register_Masks */ - /* LMEM - Peripheral instance base addresses */ /** Peripheral LMEM base address */ #define LMEM_BASE (0xE0082000u) /** Peripheral LMEM base pointer */ #define LMEM ((LMEM_Type *)LMEM_BASE) #define LMEM_BASE_PTR (LMEM) -/** Array initializer of LMEM peripheral base adresses */ +/** Array initializer of LMEM peripheral base addresses */ #define LMEM_BASE_ADDRS { LMEM_BASE } /** Array initializer of LMEM peripheral base pointers */ #define LMEM_BASE_PTRS { LMEM } - /* ---------------------------------------------------------------------------- -- LMEM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -79705,7 +29654,6 @@ typedef struct { #define LMEM_PSCLCR LMEM_PSCLCR_REG(LMEM_BASE_PTR) #define LMEM_PSCSAR LMEM_PSCSAR_REG(LMEM_BASE_PTR) #define LMEM_PSCCVR LMEM_PSCCVR_REG(LMEM_BASE_PTR) - /*! * @} */ /* end of group LMEM_Register_Accessor_Macros */ @@ -79715,7 +29663,6 @@ typedef struct { * @} */ /* end of group LMEM_Peripheral */ - /* ---------------------------------------------------------------------------- -- MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -79735,7 +29682,6 @@ typedef struct { __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ } MCM_Type, *MCM_MemMapPtr; - /* ---------------------------------------------------------------------------- -- MCM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -79756,8 +29702,6 @@ typedef struct { /*! * @} */ /* end of group MCM_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ @@ -79803,18 +29747,16 @@ typedef struct { * @} */ /* end of group MCM_Register_Masks */ - /* MCM - Peripheral instance base addresses */ /** Peripheral MCM base address */ #define MCM_BASE (0xE0000000u) /** Peripheral MCM base pointer */ #define MCM ((MCM_Type *)MCM_BASE) #define MCM_BASE_PTR (MCM) -/** Array initializer of MCM peripheral base adresses */ +/** Array initializer of MCM peripheral base addresses */ #define MCM_BASE_ADDRS { MCM_BASE } /** Array initializer of MCM peripheral base pointers */ #define MCM_BASE_PTRS { MCM } - /* ---------------------------------------------------------------------------- -- MCM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -79832,7 +29774,6 @@ typedef struct { #define MCM_FADR MCM_FADR_REG(MCM_BASE_PTR) #define MCM_FATR MCM_FATR_REG(MCM_BASE_PTR) #define MCM_FDR MCM_FDR_REG(MCM_BASE_PTR) - /*! * @} */ /* end of group MCM_Register_Accessor_Macros */ @@ -79842,6 +29783,462 @@ typedef struct { * @} */ /* end of group MCM_Peripheral */ +/* ---------------------------------------------------------------------------- + -- MIPI_CSI2 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_CSI2_Peripheral_Access_Layer MIPI_CSI2 Peripheral Access Layer + * @{ + */ + +/** MIPI_CSI2 - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t CSIS_CMN_CTRL; /**< CSIS Common Control, offset: 0x4 */ + __IO uint32_t CSIS_CLK_CTRL; /**< CSIS Clock gate Control, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CSIS_INT_MSK; /**< CSIS Interrupt Mask, offset: 0x10 */ + __IO uint32_t CSIS_INT_SRC; /**< CSIS Interrupt Source, offset: 0x14 */ + uint8_t RESERVED_2[8]; + __IO uint32_t DPHY_STATUS; /**< D-PHY Status, offset: 0x20 */ + __IO uint32_t DPHY_CMN_CTRL; /**< D-PHY Common Control, offset: 0x24 */ + uint8_t RESERVED_3[8]; + __IO uint32_t DPHY_BCTRL_L; /**< D-PHY Master and Slave Control register low, offset: 0x30 */ + __IO uint32_t DPHY_BCTRL_H; /**< D-PHY Master and Slave Control register high, offset: 0x34 */ + __IO uint32_t DPHY_SCTRL_L; /**< D-PHY Slave Control register low, offset: 0x38 */ + __IO uint32_t DPHY_SCTRL_H; /**< D-PHY Slave Control register high, offset: 0x3C */ + __IO uint32_t ISP_CONFIG_CH0; /**< ISP Configuration register of CH0, offset: 0x40 */ + __IO uint32_t ISP_RESOL_CH0; /**< ISP Image Resolution register of CH0, offset: 0x44 */ + __IO uint32_t ISP_SYNC_CH0; /**< ISP SYNC register of CH0, offset: 0x48 */ + uint8_t RESERVED_4[52]; + __I uint32_t SDW_CONFIG_CH0; /**< Shadow Configuration register of CH0, offset: 0x80 */ + __I uint32_t SDW_RESOL_CH0; /**< Shadow Resolution register of CH0, offset: 0x84 */ + __IO uint32_t SDW_SYNC_CH0; /**< Shadow SYNC register of CH0, offset: 0x88 */ + uint8_t RESERVED_5[52]; + __IO uint32_t DBG_CTRL; /**< Debug Control register, offset: 0xC0 */ + __IO uint32_t DBG_INTR_MSK; /**< Debug Interrupt Mask, offset: 0xC4 */ + __IO uint32_t DBG_INTR_SRC; /**< Debug Interrupt Mask, offset: 0xC8 */ + uint8_t RESERVED_6[7988]; + __IO uint32_t NON_IMG_DATA; /**< Non Image Data, offset: 0x2000 */ +} MIPI_CSI2_Type, *MIPI_CSI2_MemMapPtr; +/* ---------------------------------------------------------------------------- + -- MIPI_CSI2 - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_CSI2_Register_Accessor_Macros MIPI_CSI2 - Register accessor macros + * @{ + */ + + +/* MIPI_CSI2 - Register accessors */ +#define MIPI_CSI2_CSIS_CMN_CTRL_REG(base) ((base)->CSIS_CMN_CTRL) +#define MIPI_CSI2_CSIS_CLK_CTRL_REG(base) ((base)->CSIS_CLK_CTRL) +#define MIPI_CSI2_CSIS_INT_MSK_REG(base) ((base)->CSIS_INT_MSK) +#define MIPI_CSI2_CSIS_INT_SRC_REG(base) ((base)->CSIS_INT_SRC) +#define MIPI_CSI2_DPHY_STATUS_REG(base) ((base)->DPHY_STATUS) +#define MIPI_CSI2_DPHY_CMN_CTRL_REG(base) ((base)->DPHY_CMN_CTRL) +#define MIPI_CSI2_DPHY_BCTRL_L_REG(base) ((base)->DPHY_BCTRL_L) +#define MIPI_CSI2_DPHY_BCTRL_H_REG(base) ((base)->DPHY_BCTRL_H) +#define MIPI_CSI2_DPHY_SCTRL_L_REG(base) ((base)->DPHY_SCTRL_L) +#define MIPI_CSI2_DPHY_SCTRL_H_REG(base) ((base)->DPHY_SCTRL_H) +#define MIPI_CSI2_ISP_CONFIG_CH0_REG(base) ((base)->ISP_CONFIG_CH0) +#define MIPI_CSI2_ISP_RESOL_CH0_REG(base) ((base)->ISP_RESOL_CH0) +#define MIPI_CSI2_ISP_SYNC_CH0_REG(base) ((base)->ISP_SYNC_CH0) +#define MIPI_CSI2_SDW_CONFIG_CH0_REG(base) ((base)->SDW_CONFIG_CH0) +#define MIPI_CSI2_SDW_RESOL_CH0_REG(base) ((base)->SDW_RESOL_CH0) +#define MIPI_CSI2_SDW_SYNC_CH0_REG(base) ((base)->SDW_SYNC_CH0) +#define MIPI_CSI2_DBG_CTRL_REG(base) ((base)->DBG_CTRL) +#define MIPI_CSI2_DBG_INTR_MSK_REG(base) ((base)->DBG_INTR_MSK) +#define MIPI_CSI2_DBG_INTR_SRC_REG(base) ((base)->DBG_INTR_SRC) +#define MIPI_CSI2_NON_IMG_DATA_REG(base) ((base)->NON_IMG_DATA) + +/*! + * @} + */ /* end of group MIPI_CSI2_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MIPI_CSI2 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_CSI2_Register_Masks MIPI_CSI2 Register Masks + * @{ + */ + +/* CSIS_CMN_CTRL Bit Fields */ +#define MIPI_CSI2_CSIS_CMN_CTRL_CSI_EN_MASK 0x1u +#define MIPI_CSI2_CSIS_CMN_CTRL_CSI_EN_SHIFT 0 +#define MIPI_CSI2_CSIS_CMN_CTRL_SW_REST_MASK 0x2u +#define MIPI_CSI2_CSIS_CMN_CTRL_SW_REST_SHIFT 1 +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_MASK 0x4u +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_SHIFT 2 +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_MASK 0xF8u +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_SHIFT 3 +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_MASK) +#define MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER_MASK 0x300u +#define MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER_SHIFT 8 +#define MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_LANE_NUMBER_MASK) +#define MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK 0xC00u +#define MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE_SHIFT 10 +#define MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK) +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD2_MASK 0xF000u +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD2_SHIFT 12 +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_RSVD2_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_RSVD2_MASK) +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_MASK 0xF0000u +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_SHIFT 16 +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_MASK) +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD1_MASK 0xFFF00000u +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD1_SHIFT 20 +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CMN_CTRL_RSVD1_SHIFT))&MIPI_CSI2_CSIS_CMN_CTRL_RSVD1_MASK) +/* CSIS_CLK_CTRL Bit Fields */ +#define MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC_MASK 0xFu +#define MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC_SHIFT 0 +#define MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC_SHIFT))&MIPI_CSI2_CSIS_CLK_CTRL_WCLK_SRC_MASK) +#define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN_MASK 0xF0u +#define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN_SHIFT 4 +#define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN_SHIFT))&MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_EN_MASK) +#define MIPI_CSI2_CSIS_CLK_CTRL_RSVD4_MASK 0xFF00u +#define MIPI_CSI2_CSIS_CLK_CTRL_RSVD4_SHIFT 8 +#define MIPI_CSI2_CSIS_CLK_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CLK_CTRL_RSVD4_SHIFT))&MIPI_CSI2_CSIS_CLK_CTRL_RSVD4_MASK) +#define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL_MASK 0xFFFF0000u +#define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL_SHIFT 16 +#define MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL_SHIFT))&MIPI_CSI2_CSIS_CLK_CTRL_CLKGATE_TRAIL_MASK) +/* CSIS_INT_MSK Bit Fields */ +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_id_MASK 0x1u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_id_SHIFT 0 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_CRC_MASK 0x2u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_CRC_SHIFT 1 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_ECC_MASK 0x4u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_ECC_SHIFT 2 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_WRONG_CFG_MASK 0x8u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_WRONG_CFG_SHIFT 3 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER_MASK 0xF0u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER_SHIFT 4 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_OVER_MASK) +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE_MASK 0xF00u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE_SHIFT 8 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FE_MASK) +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS_MASK 0xF000u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS_SHIFT 12 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_LOST_FS_MASK) +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS_MASK 0xF0000u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS_SHIFT 16 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_ERR_SOT_HS_MASK) +#define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND_MASK 0xF00000u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND_SHIFT 20 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMEEND_MASK) +#define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART_MASK 0xF000000u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART_SHIFT 24 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART_SHIFT))&MIPI_CSI2_CSIS_INT_MSK_MSK_FRAMESTART_MASK) +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ODDAFTER_MASK 0x10000000u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ODDAFTER_SHIFT 28 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ODDBEFORE_MASK 0x20000000u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_ODDBEFORE_SHIFT 29 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_EVENAFTER_MASK 0x40000000u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_EVENAFTER_SHIFT 30 +#define MIPI_CSI2_CSIS_INT_MSK_MSK_EVENBEFORE_MASK 0x80000000u +#define MIPI_CSI2_CSIS_INT_MSK_MSK_EVENBEFORE_SHIFT 31 +/* CSIS_INT_SRC Bit Fields */ +#define MIPI_CSI2_CSIS_INT_SRC_ERR_ID_MASK 0x1u +#define MIPI_CSI2_CSIS_INT_SRC_ERR_ID_SHIFT 0 +#define MIPI_CSI2_CSIS_INT_SRC_ERR_CRC_MASK 0x2u +#define MIPI_CSI2_CSIS_INT_SRC_ERR_CRC_SHIFT 1 +#define MIPI_CSI2_CSIS_INT_SRC_ERR_ECC_MASK 0x4u +#define MIPI_CSI2_CSIS_INT_SRC_ERR_ECC_SHIFT 2 +#define MIPI_CSI2_CSIS_INT_SRC_ERR_WRONG_CFG_MASK 0x8u +#define MIPI_CSI2_CSIS_INT_SRC_ERR_WRONG_CFG_SHIFT 3 +#define MIPI_CSI2_CSIS_INT_SRC_ERR_OVER_MASK 0xF0u +#define MIPI_CSI2_CSIS_INT_SRC_ERR_OVER_SHIFT 4 +#define MIPI_CSI2_CSIS_INT_SRC_ERR_OVER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_ERR_OVER_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_ERR_OVER_MASK) +#define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE_MASK 0xF00u +#define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE_SHIFT 8 +#define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FE_MASK) +#define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS_MASK 0xF000u +#define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS_SHIFT 12 +#define MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_ERR_LOST_FS_MASK) +#define MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS_MASK 0xF0000u +#define MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS_SHIFT 16 +#define MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_ERR_SOT_HS_MASK) +#define MIPI_CSI2_CSIS_INT_SRC_FRAMEEND_MASK 0xF00000u +#define MIPI_CSI2_CSIS_INT_SRC_FRAMEEND_SHIFT 20 +#define MIPI_CSI2_CSIS_INT_SRC_FRAMEEND(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_FRAMEEND_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_FRAMEEND_MASK) +#define MIPI_CSI2_CSIS_INT_SRC_FRAMESTART_MASK 0xF000000u +#define MIPI_CSI2_CSIS_INT_SRC_FRAMESTART_SHIFT 24 +#define MIPI_CSI2_CSIS_INT_SRC_FRAMESTART(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_CSIS_INT_SRC_FRAMESTART_SHIFT))&MIPI_CSI2_CSIS_INT_SRC_FRAMESTART_MASK) +#define MIPI_CSI2_CSIS_INT_SRC_ODDAFTER_MASK 0x10000000u +#define MIPI_CSI2_CSIS_INT_SRC_ODDAFTER_SHIFT 28 +#define MIPI_CSI2_CSIS_INT_SRC_ODDBEFORE_MASK 0x20000000u +#define MIPI_CSI2_CSIS_INT_SRC_ODDBEFORE_SHIFT 29 +#define MIPI_CSI2_CSIS_INT_SRC_EVENAFTER_MASK 0x40000000u +#define MIPI_CSI2_CSIS_INT_SRC_EVENAFTER_SHIFT 30 +#define MIPI_CSI2_CSIS_INT_SRC_EVENBEFORE_MASK 0x80000000u +#define MIPI_CSI2_CSIS_INT_SRC_EVENBEFORE_SHIFT 31 +/* DPHY_STATUS Bit Fields */ +#define MIPI_CSI2_DPHY_STATUS_STOPSTATECLK_MASK 0x1u +#define MIPI_CSI2_DPHY_STATUS_STOPSTATECLK_SHIFT 0 +#define MIPI_CSI2_DPHY_STATUS_ULPSCLK_MASK 0x2u +#define MIPI_CSI2_DPHY_STATUS_ULPSCLK_SHIFT 1 +#define MIPI_CSI2_DPHY_STATUS_RSVD6_MASK 0xCu +#define MIPI_CSI2_DPHY_STATUS_RSVD6_SHIFT 2 +#define MIPI_CSI2_DPHY_STATUS_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_STATUS_RSVD6_SHIFT))&MIPI_CSI2_DPHY_STATUS_RSVD6_MASK) +#define MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT_MASK 0xF0u +#define MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT_SHIFT 4 +#define MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT_SHIFT))&MIPI_CSI2_DPHY_STATUS_STOPSTATEDAT_MASK) +#define MIPI_CSI2_DPHY_STATUS_ULPSDAT_MASK 0xF00u +#define MIPI_CSI2_DPHY_STATUS_ULPSDAT_SHIFT 8 +#define MIPI_CSI2_DPHY_STATUS_ULPSDAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_STATUS_ULPSDAT_SHIFT))&MIPI_CSI2_DPHY_STATUS_ULPSDAT_MASK) +#define MIPI_CSI2_DPHY_STATUS_RSVD5_MASK 0xFFFFF000u +#define MIPI_CSI2_DPHY_STATUS_RSVD5_SHIFT 12 +#define MIPI_CSI2_DPHY_STATUS_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_STATUS_RSVD5_SHIFT))&MIPI_CSI2_DPHY_STATUS_RSVD5_MASK) +/* DPHY_CMN_CTRL Bit Fields */ +#define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_CLK_MASK 0x1u +#define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_CLK_SHIFT 0 +#define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT_MASK 0x1Eu +#define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT_SHIFT 1 +#define MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT_SHIFT))&MIPI_CSI2_DPHY_CMN_CTRL_ENABLE_DAT_MASK) +#define MIPI_CSI2_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT_MASK 0x20u +#define MIPI_CSI2_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT_SHIFT 5 +#define MIPI_CSI2_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK_MASK 0x40u +#define MIPI_CSI2_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK_SHIFT 6 +#define MIPI_CSI2_DPHY_CMN_CTRL_RSVD7_MASK 0x3FFF80u +#define MIPI_CSI2_DPHY_CMN_CTRL_RSVD7_SHIFT 7 +#define MIPI_CSI2_DPHY_CMN_CTRL_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_CMN_CTRL_RSVD7_SHIFT))&MIPI_CSI2_DPHY_CMN_CTRL_RSVD7_MASK) +#define MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL_MASK 0xC00000u +#define MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL_SHIFT 22 +#define MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL_SHIFT))&MIPI_CSI2_DPHY_CMN_CTRL_S_CLKSETTLECTL_MASK) +#define MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE_MASK 0xFF000000u +#define MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE_SHIFT 24 +#define MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE_SHIFT))&MIPI_CSI2_DPHY_CMN_CTRL_HSSETTLE_MASK) +/* DPHY_BCTRL_L Bit Fields */ +#define MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL_MASK 0xFFFFFFFFu +#define MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL_SHIFT 0 +#define MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL_SHIFT))&MIPI_CSI2_DPHY_BCTRL_L_B_DPHYCTRL_MASK) +/* DPHY_BCTRL_H Bit Fields */ +#define MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL_MASK 0xFFFFFFFFu +#define MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL_SHIFT 0 +#define MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL_SHIFT))&MIPI_CSI2_DPHY_BCTRL_H_B_DPHYCTRL_MASK) +/* DPHY_SCTRL_L Bit Fields */ +#define MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL_MASK 0xFFFFFFFFu +#define MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL_SHIFT 0 +#define MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL_SHIFT))&MIPI_CSI2_DPHY_SCTRL_L_S_DPHYCTRL_MASK) +/* DPHY_SCTRL_H Bit Fields */ +#define MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL_MASK 0xFFFFFFFFu +#define MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL_SHIFT 0 +#define MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL_SHIFT))&MIPI_CSI2_DPHY_SCTRL_H_S_DPHYCTRL_MASK) +/* ISP_CONFIG_CH0 Bit Fields */ +#define MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_MASK 0x3u +#define MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT 0 +#define MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT))&MIPI_CSI2_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_MASK) +#define MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT_MASK 0xFCu +#define MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT_SHIFT 2 +#define MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT_SHIFT))&MIPI_CSI2_ISP_CONFIG_CH0_DATAFORMAT_MASK) +#define MIPI_CSI2_ISP_CONFIG_CH0_DECOMP_EN_MASK 0x100u +#define MIPI_CSI2_ISP_CONFIG_CH0_DECOMP_EN_SHIFT 8 +#define MIPI_CSI2_ISP_CONFIG_CH0_DECOMP_PREDICT_MASK 0x200u +#define MIPI_CSI2_ISP_CONFIG_CH0_DECOMP_PREDICT_SHIFT 9 +#define MIPI_CSI2_ISP_CONFIG_CH0_RGB_SWAP_MASK 0x400u +#define MIPI_CSI2_ISP_CONFIG_CH0_RGB_SWAP_SHIFT 10 +#define MIPI_CSI2_ISP_CONFIG_CH0_PARALLEL_MASK 0x800u +#define MIPI_CSI2_ISP_CONFIG_CH0_PARALLEL_SHIFT 11 +#define MIPI_CSI2_ISP_CONFIG_CH0_DOUBLE_CMPNT_MASK 0x1000u +#define MIPI_CSI2_ISP_CONFIG_CH0_DOUBLE_CMPNT_SHIFT 12 +#define MIPI_CSI2_ISP_CONFIG_CH0_RSVD8_MASK 0xFFE000u +#define MIPI_CSI2_ISP_CONFIG_CH0_RSVD8_SHIFT 13 +#define MIPI_CSI2_ISP_CONFIG_CH0_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_CONFIG_CH0_RSVD8_SHIFT))&MIPI_CSI2_ISP_CONFIG_CH0_RSVD8_MASK) +#define MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP_MASK 0xFF000000u +#define MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP_SHIFT 24 +#define MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP_SHIFT))&MIPI_CSI2_ISP_CONFIG_CH0_MEM_FULL_GAP_MASK) +/* ISP_RESOL_CH0 Bit Fields */ +#define MIPI_CSI2_ISP_RESOL_CH0_HRESOL_MASK 0xFFFFu +#define MIPI_CSI2_ISP_RESOL_CH0_HRESOL_SHIFT 0 +#define MIPI_CSI2_ISP_RESOL_CH0_HRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_RESOL_CH0_HRESOL_SHIFT))&MIPI_CSI2_ISP_RESOL_CH0_HRESOL_MASK) +#define MIPI_CSI2_ISP_RESOL_CH0_VRESOL_MASK 0xFFFF0000u +#define MIPI_CSI2_ISP_RESOL_CH0_VRESOL_SHIFT 16 +#define MIPI_CSI2_ISP_RESOL_CH0_VRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_RESOL_CH0_VRESOL_SHIFT))&MIPI_CSI2_ISP_RESOL_CH0_VRESOL_MASK) +/* ISP_SYNC_CH0 Bit Fields */ +#define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV_MASK 0xFFFu +#define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV_SHIFT 0 +#define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV_SHIFT))&MIPI_CSI2_ISP_SYNC_CH0_VSYNC_EINTV_MASK) +#define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV_MASK 0x3F000u +#define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV_SHIFT 12 +#define MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV_SHIFT))&MIPI_CSI2_ISP_SYNC_CH0_VSYNC_SINTV_MASK) +#define MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV_MASK 0xFC0000u +#define MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV_SHIFT 18 +#define MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV_SHIFT))&MIPI_CSI2_ISP_SYNC_CH0_HSYNC_LINTV_MASK) +#define MIPI_CSI2_ISP_SYNC_CH0_RSVD9_MASK 0xFF000000u +#define MIPI_CSI2_ISP_SYNC_CH0_RSVD9_SHIFT 24 +#define MIPI_CSI2_ISP_SYNC_CH0_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_ISP_SYNC_CH0_RSVD9_SHIFT))&MIPI_CSI2_ISP_SYNC_CH0_RSVD9_MASK) +/* SDW_CONFIG_CH0 Bit Fields */ +#define MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_MASK 0x3u +#define MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT 0 +#define MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT))&MIPI_CSI2_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_MASK) +#define MIPI_CSI2_SDW_CONFIG_CH0_DataFormat_MASK 0xFCu +#define MIPI_CSI2_SDW_CONFIG_CH0_DataFormat_SHIFT 2 +#define MIPI_CSI2_SDW_CONFIG_CH0_DataFormat(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_CONFIG_CH0_DataFormat_SHIFT))&MIPI_CSI2_SDW_CONFIG_CH0_DataFormat_MASK) +#define MIPI_CSI2_SDW_CONFIG_CH0_DECOMP_EN_SDW_MASK 0x100u +#define MIPI_CSI2_SDW_CONFIG_CH0_DECOMP_EN_SDW_SHIFT 8 +#define MIPI_CSI2_SDW_CONFIG_CH0_DECOMP_PREDICT_SDW_MASK 0x200u +#define MIPI_CSI2_SDW_CONFIG_CH0_DECOMP_PREDICT_SDW_SHIFT 9 +#define MIPI_CSI2_SDW_CONFIG_CH0_RGB_SWAP_SDW_MASK 0x400u +#define MIPI_CSI2_SDW_CONFIG_CH0_RGB_SWAP_SDW_SHIFT 10 +#define MIPI_CSI2_SDW_CONFIG_CH0_PARALLEL_SDW_MASK 0x800u +#define MIPI_CSI2_SDW_CONFIG_CH0_PARALLEL_SDW_SHIFT 11 +#define MIPI_CSI2_SDW_CONFIG_CH0_DOUBLE_CMPNT_SDW_MASK 0x1000u +#define MIPI_CSI2_SDW_CONFIG_CH0_DOUBLE_CMPNT_SDW_SHIFT 12 +#define MIPI_CSI2_SDW_CONFIG_CH0_RSVD10_MASK 0xFFE000u +#define MIPI_CSI2_SDW_CONFIG_CH0_RSVD10_SHIFT 13 +#define MIPI_CSI2_SDW_CONFIG_CH0_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_CONFIG_CH0_RSVD10_SHIFT))&MIPI_CSI2_SDW_CONFIG_CH0_RSVD10_MASK) +#define MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_MASK 0xFF000000u +#define MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_SHIFT 24 +#define MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_SHIFT))&MIPI_CSI2_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_MASK) +/* SDW_RESOL_CH0 Bit Fields */ +#define MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW_MASK 0xFFFFu +#define MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW_SHIFT 0 +#define MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW_SHIFT))&MIPI_CSI2_SDW_RESOL_CH0_HRESOL_SDW_MASK) +#define MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW_MASK 0xFFFF0000u +#define MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW_SHIFT 16 +#define MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW_SHIFT))&MIPI_CSI2_SDW_RESOL_CH0_VRESOL_SDW_MASK) +/* SDW_SYNC_CH0 Bit Fields */ +#define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW_MASK 0xFFFu +#define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW_SHIFT 0 +#define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW_SHIFT))&MIPI_CSI2_SDW_SYNC_CH0_VSYNC_EINTV_SDW_MASK) +#define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW_MASK 0x3F000u +#define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW_SHIFT 12 +#define MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW_SHIFT))&MIPI_CSI2_SDW_SYNC_CH0_VSYNC_SINTV_SDW_MASK) +#define MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW_MASK 0xFC0000u +#define MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW_SHIFT 18 +#define MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW_SHIFT))&MIPI_CSI2_SDW_SYNC_CH0_HSYNC_LINTV_SDW_MASK) +#define MIPI_CSI2_SDW_SYNC_CH0_RSVD11_MASK 0xFF000000u +#define MIPI_CSI2_SDW_SYNC_CH0_RSVD11_SHIFT 24 +#define MIPI_CSI2_SDW_SYNC_CH0_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_SDW_SYNC_CH0_RSVD11_SHIFT))&MIPI_CSI2_SDW_SYNC_CH0_RSVD11_MASK) +/* DBG_CTRL Bit Fields */ +#define MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT_MASK 0xFu +#define MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT_SHIFT 0 +#define MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT_SHIFT))&MIPI_CSI2_DBG_CTRL_DBG_CH_OUTPUT_MASK) +#define MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME_MASK 0xF0u +#define MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME_SHIFT 4 +#define MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME_SHIFT))&MIPI_CSI2_DBG_CTRL_DBG_BLK_EXC_FRAME_MASK) +#define MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_MASK 0xF00u +#define MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_SHIFT 8 +#define MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_SHIFT))&MIPI_CSI2_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_MASK) +#define MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE_MASK 0xF000u +#define MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE_SHIFT 12 +#define MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE_SHIFT))&MIPI_CSI2_DBG_CTRL_DBG_FORCE_UPDATE_MASK) +#define MIPI_CSI2_DBG_CTRL_RSVD12_MASK 0xFFFF0000u +#define MIPI_CSI2_DBG_CTRL_RSVD12_SHIFT 16 +#define MIPI_CSI2_DBG_CTRL_RSVD12(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_CTRL_RSVD12_SHIFT))&MIPI_CSI2_DBG_CTRL_RSVD12_MASK) +/* DBG_INTR_MSK Bit Fields */ +#define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE_MASK 0xFu +#define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE_SHIFT 0 +#define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_RISE_MASK) +#define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL_MASK 0xF0u +#define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL_SHIFT 4 +#define MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_CAM_VSYNC_FALL_MASK) +#define MIPI_CSI2_DBG_INTR_MSK_EARLY_FS_MASK 0xF00u +#define MIPI_CSI2_DBG_INTR_MSK_EARLY_FS_SHIFT 8 +#define MIPI_CSI2_DBG_INTR_MSK_EARLY_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_EARLY_FS_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_EARLY_FS_MASK) +#define MIPI_CSI2_DBG_INTR_MSK_EARLY_FE_MASK 0xF000u +#define MIPI_CSI2_DBG_INTR_MSK_EARLY_FE_SHIFT 12 +#define MIPI_CSI2_DBG_INTR_MSK_EARLY_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_EARLY_FE_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_EARLY_FE_MASK) +#define MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME_MASK 0xF0000u +#define MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME_SHIFT 16 +#define MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_TRUNCATED_FRAME_MASK) +#define MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE_MASK 0xF00000u +#define MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE_SHIFT 20 +#define MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_ERR_FRAME_SIZE_MASK) +#define MIPI_CSI2_DBG_INTR_MSK_DT_IGNORE_MASK 0x1000000u +#define MIPI_CSI2_DBG_INTR_MSK_DT_IGNORE_SHIFT 24 +#define MIPI_CSI2_DBG_INTR_MSK_DT_NOT_SUPPORT_MASK 0x2000000u +#define MIPI_CSI2_DBG_INTR_MSK_DT_NOT_SUPPORT_SHIFT 25 +#define MIPI_CSI2_DBG_INTR_MSK_RSVD13_MASK 0xFC000000u +#define MIPI_CSI2_DBG_INTR_MSK_RSVD13_SHIFT 26 +#define MIPI_CSI2_DBG_INTR_MSK_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_MSK_RSVD13_SHIFT))&MIPI_CSI2_DBG_INTR_MSK_RSVD13_MASK) +/* DBG_INTR_SRC Bit Fields */ +#define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE_MASK 0xFu +#define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE_SHIFT 0 +#define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_RISE_MASK) +#define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL_MASK 0xF0u +#define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL_SHIFT 4 +#define MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_CAM_VSYNC_FALL_MASK) +#define MIPI_CSI2_DBG_INTR_SRC_EARLY_FS_MASK 0xF00u +#define MIPI_CSI2_DBG_INTR_SRC_EARLY_FS_SHIFT 8 +#define MIPI_CSI2_DBG_INTR_SRC_EARLY_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_EARLY_FS_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_EARLY_FS_MASK) +#define MIPI_CSI2_DBG_INTR_SRC_EARLY_FE_MASK 0xF000u +#define MIPI_CSI2_DBG_INTR_SRC_EARLY_FE_SHIFT 12 +#define MIPI_CSI2_DBG_INTR_SRC_EARLY_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_EARLY_FE_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_EARLY_FE_MASK) +#define MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME_MASK 0xF0000u +#define MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME_SHIFT 16 +#define MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_TRUNCATED_FRAME_MASK) +#define MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE_MASK 0xF00000u +#define MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE_SHIFT 20 +#define MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_ERR_FRAME_SIZE_MASK) +#define MIPI_CSI2_DBG_INTR_SRC_DT_IGNORE_MASK 0x1000000u +#define MIPI_CSI2_DBG_INTR_SRC_DT_IGNORE_SHIFT 24 +#define MIPI_CSI2_DBG_INTR_SRC_DT_NOT_SUPPURT_MASK 0x2000000u +#define MIPI_CSI2_DBG_INTR_SRC_DT_NOT_SUPPURT_SHIFT 25 +#define MIPI_CSI2_DBG_INTR_SRC_RSVD14_MASK 0xFC000000u +#define MIPI_CSI2_DBG_INTR_SRC_RSVD14_SHIFT 26 +#define MIPI_CSI2_DBG_INTR_SRC_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_DBG_INTR_SRC_RSVD14_SHIFT))&MIPI_CSI2_DBG_INTR_SRC_RSVD14_MASK) +/* NON_IMG_DATA Bit Fields */ +#define MIPI_CSI2_NON_IMG_DATA_NONIMGDATA_MASK 0xFFFFFFFFu +#define MIPI_CSI2_NON_IMG_DATA_NONIMGDATA_SHIFT 0 +#define MIPI_CSI2_NON_IMG_DATA_NONIMGDATA(x) (((uint32_t)(((uint32_t)(x))<<MIPI_CSI2_NON_IMG_DATA_NONIMGDATA_SHIFT))&MIPI_CSI2_NON_IMG_DATA_NONIMGDATA_MASK) + +/*! + * @} + */ /* end of group MIPI_CSI2_Register_Masks */ + +/* MIPI_CSI2 - Peripheral instance base addresses */ +/** Peripheral MIPI_CSI2 base address */ +#define MIPI_CSI2_BASE (0x30750000u) +/** Peripheral MIPI_CSI2 base pointer */ +#define MIPI_CSI2 ((MIPI_CSI2_Type *)MIPI_CSI2_BASE) +#define MIPI_CSI2_BASE_PTR (MIPI_CSI2) +/** Array initializer of MIPI_CSI2 peripheral base addresses */ +#define MIPI_CSI2_BASE_ADDRS { MIPI_CSI2_BASE } +/** Array initializer of MIPI_CSI2 peripheral base pointers */ +#define MIPI_CSI2_BASE_PTRS { MIPI_CSI2 } +/* ---------------------------------------------------------------------------- + -- MIPI_CSI2 - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_CSI2_Register_Accessor_Macros MIPI_CSI2 - Register accessor macros + * @{ + */ + + +/* MIPI_CSI2 - Register instance definitions */ +/* MIPI_CSI2 */ +#define MIPI_CSI2_CSIS_CMN_CTRL MIPI_CSI2_CSIS_CMN_CTRL_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_CSIS_CLK_CTRL MIPI_CSI2_CSIS_CLK_CTRL_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_CSIS_INT_MSK MIPI_CSI2_CSIS_INT_MSK_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_CSIS_INT_SRC MIPI_CSI2_CSIS_INT_SRC_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DPHY_STATUS MIPI_CSI2_DPHY_STATUS_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DPHY_CMN_CTRL MIPI_CSI2_DPHY_CMN_CTRL_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DPHY_BCTRL_L MIPI_CSI2_DPHY_BCTRL_L_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DPHY_BCTRL_H MIPI_CSI2_DPHY_BCTRL_H_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DPHY_SCTRL_L MIPI_CSI2_DPHY_SCTRL_L_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DPHY_SCTRL_H MIPI_CSI2_DPHY_SCTRL_H_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_ISP_CONFIG_CH0 MIPI_CSI2_ISP_CONFIG_CH0_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_ISP_RESOL_CH0 MIPI_CSI2_ISP_RESOL_CH0_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_ISP_SYNC_CH0 MIPI_CSI2_ISP_SYNC_CH0_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_SDW_CONFIG_CH0 MIPI_CSI2_SDW_CONFIG_CH0_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_SDW_RESOL_CH0 MIPI_CSI2_SDW_RESOL_CH0_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_SDW_SYNC_CH0 MIPI_CSI2_SDW_SYNC_CH0_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DBG_CTRL MIPI_CSI2_DBG_CTRL_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DBG_INTR_MSK MIPI_CSI2_DBG_INTR_MSK_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_DBG_INTR_SRC MIPI_CSI2_DBG_INTR_SRC_REG(MIPI_CSI2_BASE_PTR) +#define MIPI_CSI2_NON_IMG_DATA MIPI_CSI2_NON_IMG_DATA_REG(MIPI_CSI2_BASE_PTR) +/*! + * @} + */ /* end of group MIPI_CSI2_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group MIPI_CSI2_Peripheral */ /* ---------------------------------------------------------------------------- -- MIPI_DSI Peripheral Access Layer @@ -79883,23 +30280,14 @@ typedef struct { __IO uint32_t PLLCTRL1; /**< PLL Control Register 1, offset: 0x98 */ __IO uint32_t PLLCTRL2; /**< PLL control register 2, offset: 0x9C */ __IO uint32_t PLLTMR; /**< PLL Timer Register, offset: 0xA0 */ - union { /* offset: 0xA4 */ - struct { /* offset: 0xA4 */ - __IO uint32_t PHYCTRL_B1; /**< D-PHY Master and Slave Analog Block Control Register 1, offset: 0xA4 */ - __IO uint32_t PHYCTRL_B2; /**< D-PHY Master and Slave Analog Block Control Register 2, offset: 0xA8 */ - } PHYCTRL_B; - struct { /* offset: 0xA4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t PHYCTRL_M1; /**< D-PHY Master Analog Block Control Register 1, offset: 0xA8 */ - __IO uint32_t PHYCTRL_M2; /**< D-PHY Master Analog Block Control Register 1, offset: 0xAC */ - } PHYCTRL_M; - }; - uint8_t RESERVED_2[4]; + __IO uint32_t PHYCTRL_B1; /**< D-PHY Master and Slave Analog Block Control Register 1, offset: 0xA4 */ + __IO uint32_t PHYCTRL_B2; /**< D-PHY Master and Slave Analog Block Control Register 2, offset: 0xA8 */ + __IO uint32_t PHYCTRL_M1; /**< D-PHY Master Analog Block Control Register 1, offset: 0xAC */ + __IO uint32_t PHYCTRL_M2; /**< D-PHY Master Analog Block Control Register 1, offset: 0xB0 */ __IO uint32_t PHYTIMING; /**< D-PHY Timing register, offset: 0xB4 */ __IO uint32_t PHYTIMING1; /**< , offset: 0xB8 */ __IO uint32_t PHYTIMING2; /**< D-PHY Timing Register 2, offset: 0xBC */ } MIPI_DSI_Type, *MIPI_DSI_MemMapPtr; - /* ---------------------------------------------------------------------------- -- MIPI_DSI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -79938,10 +30326,10 @@ typedef struct { #define MIPI_DSI_PLLCTRL1_REG(base) ((base)->PLLCTRL1) #define MIPI_DSI_PLLCTRL2_REG(base) ((base)->PLLCTRL2) #define MIPI_DSI_PLLTMR_REG(base) ((base)->PLLTMR) -#define MIPI_DSI_PHYCTRL_B1_REG(base) ((base)->PHYCTRL_B.PHYCTRL_B1) -#define MIPI_DSI_PHYCTRL_B2_REG(base) ((base)->PHYCTRL_B.PHYCTRL_B2) -#define MIPI_DSI_PHYCTRL_M1_REG(base) ((base)->PHYCTRL_M.PHYCTRL_M1) -#define MIPI_DSI_PHYCTRL_M2_REG(base) ((base)->PHYCTRL_M.PHYCTRL_M2) +#define MIPI_DSI_PHYCTRL_B1_REG(base) ((base)->PHYCTRL_B1) +#define MIPI_DSI_PHYCTRL_B2_REG(base) ((base)->PHYCTRL_B2) +#define MIPI_DSI_PHYCTRL_M1_REG(base) ((base)->PHYCTRL_M1) +#define MIPI_DSI_PHYCTRL_M2_REG(base) ((base)->PHYCTRL_M2) #define MIPI_DSI_PHYTIMING_REG(base) ((base)->PHYTIMING) #define MIPI_DSI_PHYTIMING1_REG(base) ((base)->PHYTIMING1) #define MIPI_DSI_PHYTIMING2_REG(base) ((base)->PHYTIMING2) @@ -79949,8 +30337,6 @@ typedef struct { /*! * @} */ /* end of group MIPI_DSI_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- MIPI_DSI Register Masks ---------------------------------------------------------------------------- */ @@ -80401,18 +30787,18 @@ typedef struct { * @} */ /* end of group MIPI_DSI_Register_Masks */ - /* MIPI_DSI - Peripheral instance base addresses */ /** Peripheral MIPI_DSI base address */ #define MIPI_DSI_BASE (0x30760000u) /** Peripheral MIPI_DSI base pointer */ #define MIPI_DSI ((MIPI_DSI_Type *)MIPI_DSI_BASE) #define MIPI_DSI_BASE_PTR (MIPI_DSI) -/** Array initializer of MIPI_DSI peripheral base adresses */ +/** Array initializer of MIPI_DSI peripheral base addresses */ #define MIPI_DSI_BASE_ADDRS { MIPI_DSI_BASE } /** Array initializer of MIPI_DSI peripheral base pointers */ #define MIPI_DSI_BASE_PTRS { MIPI_DSI } - +/** Interrupt vectors for the MIPI_DSI peripheral type */ +#define MIPI_DSI_IRQS { MIPI_DSI_IRQn } /* ---------------------------------------------------------------------------- -- MIPI_DSI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -80459,7 +30845,6 @@ typedef struct { #define MIPI_DSI_PHYTIMING MIPI_DSI_PHYTIMING_REG(MIPI_DSI_BASE_PTR) #define MIPI_DSI_PHYTIMING1 MIPI_DSI_PHYTIMING1_REG(MIPI_DSI_BASE_PTR) #define MIPI_DSI_PHYTIMING2 MIPI_DSI_PHYTIMING2_REG(MIPI_DSI_BASE_PTR) - /*! * @} */ /* end of group MIPI_DSI_Register_Accessor_Macros */ @@ -80469,481 +30854,22 @@ typedef struct { * @} */ /* end of group MIPI_DSI_Peripheral */ - -/* ---------------------------------------------------------------------------- - -- MIPI_HSI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MIPI_HSI_Peripheral_Access_Layer MIPI_HSI Peripheral Access Layer - * @{ - */ - -/** MIPI_HSI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4]; - __IO uint32_t CSIS_CMN_CTRL; /**< CSIS Common Control, offset: 0x4 */ - __IO uint32_t CSIS_CLK_CTRL; /**< CSIS Clock gate Control, offset: 0x8 */ - uint8_t RESERVED_1[4]; - __IO uint32_t CSIS_INT_MSK; /**< CSIS Interrupt Mask, offset: 0x10 */ - __IO uint32_t CSIS_INT_SRC; /**< CSIS Interrupt Source, offset: 0x14 */ - uint8_t RESERVED_2[8]; - __IO uint32_t DPHY_STATUS; /**< D-PHY Status, offset: 0x20 */ - __IO uint32_t DPHY_CMN_CTRL; /**< D-PHY Common Control, offset: 0x24 */ - uint8_t RESERVED_3[8]; - __IO uint32_t DPHY_BCTRL_L; /**< D-PHY Master and Slave Control register low, offset: 0x30 */ - __IO uint32_t DPHY_BCTRL_H; /**< D-PHY Master and Slave Control register high, offset: 0x34 */ - __IO uint32_t DPHY_SCTRL_L; /**< D-PHY Slave Control register low, offset: 0x38 */ - __IO uint32_t DPHY_SCTRL_H; /**< D-PHY Slave Control register high, offset: 0x3C */ - __IO uint32_t ISP_CONFIG_CH0; /**< ISP Configuration register of CH0, offset: 0x40 */ - __IO uint32_t ISP_RESOL_CH0; /**< ISP Image Resolution register of CH0, offset: 0x44 */ - __IO uint32_t ISP_SYNC_CH0; /**< ISP SYNC register of CH0, offset: 0x48 */ - uint8_t RESERVED_4[52]; - __IO uint32_t SDW_CONFIG_CH0; /**< Shadow Configuration register of CH0, offset: 0x80 */ - __IO uint32_t SDW_RESOL_CH0; /**< Shadow Resolution register of CH0, offset: 0x84 */ - __IO uint32_t SDW_SYNC_CH0; /**< Shadow SYNC register of CH0, offset: 0x88 */ - uint8_t RESERVED_5[52]; - __IO uint32_t DBG_CTRL; /**< Debug Control register, offset: 0xC0 */ - __IO uint32_t DBG_INTR_MSK; /**< Debug Interrupt Mask, offset: 0xC4 */ - __IO uint32_t DBG_INTR_SRC; /**< Debug Interrupt Mask, offset: 0xC8 */ - uint8_t RESERVED_6[7988]; - __IO uint32_t NON_IMG_DATA; /**< Non Image Data, offset: 0x2000 */ -} MIPI_HSI_Type, *MIPI_HSI_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- MIPI_HSI - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MIPI_HSI_Register_Accessor_Macros MIPI_HSI - Register accessor macros - * @{ - */ - - -/* MIPI_HSI - Register accessors */ -#define MIPI_HSI_CSIS_CMN_CTRL_REG(base) ((base)->CSIS_CMN_CTRL) -#define MIPI_HSI_CSIS_CLK_CTRL_REG(base) ((base)->CSIS_CLK_CTRL) -#define MIPI_HSI_CSIS_INT_MSK_REG(base) ((base)->CSIS_INT_MSK) -#define MIPI_HSI_CSIS_INT_SRC_REG(base) ((base)->CSIS_INT_SRC) -#define MIPI_HSI_DPHY_STATUS_REG(base) ((base)->DPHY_STATUS) -#define MIPI_HSI_DPHY_CMN_CTRL_REG(base) ((base)->DPHY_CMN_CTRL) -#define MIPI_HSI_DPHY_BCTRL_L_REG(base) ((base)->DPHY_BCTRL_L) -#define MIPI_HSI_DPHY_BCTRL_H_REG(base) ((base)->DPHY_BCTRL_H) -#define MIPI_HSI_DPHY_SCTRL_L_REG(base) ((base)->DPHY_SCTRL_L) -#define MIPI_HSI_DPHY_SCTRL_H_REG(base) ((base)->DPHY_SCTRL_H) -#define MIPI_HSI_ISP_CONFIG_CH0_REG(base) ((base)->ISP_CONFIG_CH0) -#define MIPI_HSI_ISP_RESOL_CH0_REG(base) ((base)->ISP_RESOL_CH0) -#define MIPI_HSI_ISP_SYNC_CH0_REG(base) ((base)->ISP_SYNC_CH0) -#define MIPI_HSI_SDW_CONFIG_CH0_REG(base) ((base)->SDW_CONFIG_CH0) -#define MIPI_HSI_SDW_RESOL_CH0_REG(base) ((base)->SDW_RESOL_CH0) -#define MIPI_HSI_SDW_SYNC_CH0_REG(base) ((base)->SDW_SYNC_CH0) -#define MIPI_HSI_DBG_CTRL_REG(base) ((base)->DBG_CTRL) -#define MIPI_HSI_DBG_INTR_MSK_REG(base) ((base)->DBG_INTR_MSK) -#define MIPI_HSI_DBG_INTR_SRC_REG(base) ((base)->DBG_INTR_SRC) -#define MIPI_HSI_NON_IMG_DATA_REG(base) ((base)->NON_IMG_DATA) - -/*! - * @} - */ /* end of group MIPI_HSI_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MIPI_HSI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MIPI_HSI_Register_Masks MIPI_HSI Register Masks - * @{ - */ - -/* CSIS_CMN_CTRL Bit Fields */ -#define MIPI_HSI_CSIS_CMN_CTRL_CSI_EN_MASK 0x1u -#define MIPI_HSI_CSIS_CMN_CTRL_CSI_EN_SHIFT 0 -#define MIPI_HSI_CSIS_CMN_CTRL_SW_REST_MASK 0x2u -#define MIPI_HSI_CSIS_CMN_CTRL_SW_REST_SHIFT 1 -#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_MASK 0x4u -#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_SHIFT 2 -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD3_MASK 0xF8u -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD3_SHIFT 3 -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_RSVD3_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_RSVD3_MASK) -#define MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER_MASK 0x300u -#define MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER_SHIFT 8 -#define MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER_MASK) -#define MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK 0xC00u -#define MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE_SHIFT 10 -#define MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK) -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD2_MASK 0xF000u -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD2_SHIFT 12 -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_RSVD2_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_RSVD2_MASK) -#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_MASK 0xF0000u -#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_SHIFT 16 -#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_MASK) -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD1_MASK 0xFFF00000u -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD1_SHIFT 20 -#define MIPI_HSI_CSIS_CMN_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_RSVD1_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_RSVD1_MASK) -/* CSIS_CLK_CTRL Bit Fields */ -#define MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC_MASK 0xFu -#define MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC_SHIFT 0 -#define MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC_SHIFT))&MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC_MASK) -#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN_MASK 0xF0u -#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN_SHIFT 4 -#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN_SHIFT))&MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN_MASK) -#define MIPI_HSI_CSIS_CLK_CTRL_RSVD4_MASK 0xFF00u -#define MIPI_HSI_CSIS_CLK_CTRL_RSVD4_SHIFT 8 -#define MIPI_HSI_CSIS_CLK_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CLK_CTRL_RSVD4_SHIFT))&MIPI_HSI_CSIS_CLK_CTRL_RSVD4_MASK) -#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL_MASK 0xFFFF0000u -#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL_SHIFT 16 -#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL_SHIFT))&MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL_MASK) -/* CSIS_INT_MSK Bit Fields */ -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_id_MASK 0x1u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_id_SHIFT 0 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_CRC_MASK 0x2u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_CRC_SHIFT 1 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_ECC_MASK 0x4u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_ECC_SHIFT 2 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_WRONG_CFG_MASK 0x8u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_WRONG_CFG_SHIFT 3 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER_MASK 0xF0u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER_SHIFT 4 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER_MASK) -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE_MASK 0xF00u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE_SHIFT 8 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE_MASK) -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS_MASK 0xF000u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS_SHIFT 12 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS_MASK) -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS_MASK 0xF0000u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS_SHIFT 16 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS_MASK) -#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND_MASK 0xF00000u -#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND_SHIFT 20 -#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND_MASK) -#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART_MASK 0xF000000u -#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART_SHIFT 24 -#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART_MASK) -#define MIPI_HSI_CSIS_INT_MSK_MSK_ODDAFTER_MASK 0x10000000u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ODDAFTER_SHIFT 28 -#define MIPI_HSI_CSIS_INT_MSK_MSK_ODDBEFORE_MASK 0x20000000u -#define MIPI_HSI_CSIS_INT_MSK_MSK_ODDBEFORE_SHIFT 29 -#define MIPI_HSI_CSIS_INT_MSK_MSK_EVENAFTER_MASK 0x40000000u -#define MIPI_HSI_CSIS_INT_MSK_MSK_EVENAFTER_SHIFT 30 -#define MIPI_HSI_CSIS_INT_MSK_MSK_EVENBEFORE_MASK 0x80000000u -#define MIPI_HSI_CSIS_INT_MSK_MSK_EVENBEFORE_SHIFT 31 -/* CSIS_INT_SRC Bit Fields */ -#define MIPI_HSI_CSIS_INT_SRC_ERR_ID_MASK 0x1u -#define MIPI_HSI_CSIS_INT_SRC_ERR_ID_SHIFT 0 -#define MIPI_HSI_CSIS_INT_SRC_ERR_CRC_MASK 0x2u -#define MIPI_HSI_CSIS_INT_SRC_ERR_CRC_SHIFT 1 -#define MIPI_HSI_CSIS_INT_SRC_ERR_ECC_MASK 0x4u -#define MIPI_HSI_CSIS_INT_SRC_ERR_ECC_SHIFT 2 -#define MIPI_HSI_CSIS_INT_SRC_ERR_WRONG_CFG_MASK 0x8u -#define MIPI_HSI_CSIS_INT_SRC_ERR_WRONG_CFG_SHIFT 3 -#define MIPI_HSI_CSIS_INT_SRC_ERR_OVER_MASK 0xF0u -#define MIPI_HSI_CSIS_INT_SRC_ERR_OVER_SHIFT 4 -#define MIPI_HSI_CSIS_INT_SRC_ERR_OVER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_ERR_OVER_SHIFT))&MIPI_HSI_CSIS_INT_SRC_ERR_OVER_MASK) -#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE_MASK 0xF00u -#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE_SHIFT 8 -#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE_SHIFT))&MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE_MASK) -#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS_MASK 0xF000u -#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS_SHIFT 12 -#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS_SHIFT))&MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS_MASK) -#define MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS_MASK 0xF0000u -#define MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS_SHIFT 16 -#define MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS_SHIFT))&MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS_MASK) -#define MIPI_HSI_CSIS_INT_SRC_FRAMEEND_MASK 0xF00000u -#define MIPI_HSI_CSIS_INT_SRC_FRAMEEND_SHIFT 20 -#define MIPI_HSI_CSIS_INT_SRC_FRAMEEND(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_FRAMEEND_SHIFT))&MIPI_HSI_CSIS_INT_SRC_FRAMEEND_MASK) -#define MIPI_HSI_CSIS_INT_SRC_FRAMESTART_MASK 0xF000000u -#define MIPI_HSI_CSIS_INT_SRC_FRAMESTART_SHIFT 24 -#define MIPI_HSI_CSIS_INT_SRC_FRAMESTART(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_FRAMESTART_SHIFT))&MIPI_HSI_CSIS_INT_SRC_FRAMESTART_MASK) -#define MIPI_HSI_CSIS_INT_SRC_ODDAFTER_MASK 0x10000000u -#define MIPI_HSI_CSIS_INT_SRC_ODDAFTER_SHIFT 28 -#define MIPI_HSI_CSIS_INT_SRC_ODDBEFORE_MASK 0x20000000u -#define MIPI_HSI_CSIS_INT_SRC_ODDBEFORE_SHIFT 29 -#define MIPI_HSI_CSIS_INT_SRC_EVENAFTER_MASK 0x40000000u -#define MIPI_HSI_CSIS_INT_SRC_EVENAFTER_SHIFT 30 -#define MIPI_HSI_CSIS_INT_SRC_EVENBEFORE_MASK 0x80000000u -#define MIPI_HSI_CSIS_INT_SRC_EVENBEFORE_SHIFT 31 -/* DPHY_STATUS Bit Fields */ -#define MIPI_HSI_DPHY_STATUS_STOPSTATECLK_MASK 0x1u -#define MIPI_HSI_DPHY_STATUS_STOPSTATECLK_SHIFT 0 -#define MIPI_HSI_DPHY_STATUS_ULPSCLK_MASK 0x2u -#define MIPI_HSI_DPHY_STATUS_ULPSCLK_SHIFT 1 -#define MIPI_HSI_DPHY_STATUS_RSVD6_MASK 0xCu -#define MIPI_HSI_DPHY_STATUS_RSVD6_SHIFT 2 -#define MIPI_HSI_DPHY_STATUS_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_STATUS_RSVD6_SHIFT))&MIPI_HSI_DPHY_STATUS_RSVD6_MASK) -#define MIPI_HSI_DPHY_STATUS_STOPSTATEDAT_MASK 0xF0u -#define MIPI_HSI_DPHY_STATUS_STOPSTATEDAT_SHIFT 4 -#define MIPI_HSI_DPHY_STATUS_STOPSTATEDAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_STATUS_STOPSTATEDAT_SHIFT))&MIPI_HSI_DPHY_STATUS_STOPSTATEDAT_MASK) -#define MIPI_HSI_DPHY_STATUS_ULPSDAT_MASK 0xF00u -#define MIPI_HSI_DPHY_STATUS_ULPSDAT_SHIFT 8 -#define MIPI_HSI_DPHY_STATUS_ULPSDAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_STATUS_ULPSDAT_SHIFT))&MIPI_HSI_DPHY_STATUS_ULPSDAT_MASK) -#define MIPI_HSI_DPHY_STATUS_RSVD5_MASK 0xFFFFF000u -#define MIPI_HSI_DPHY_STATUS_RSVD5_SHIFT 12 -#define MIPI_HSI_DPHY_STATUS_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_STATUS_RSVD5_SHIFT))&MIPI_HSI_DPHY_STATUS_RSVD5_MASK) -/* DPHY_CMN_CTRL Bit Fields */ -#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_CLK_MASK 0x1u -#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_CLK_SHIFT 0 -#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT_MASK 0x1Eu -#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT_SHIFT 1 -#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT_SHIFT))&MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT_MASK) -#define MIPI_HSI_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT_MASK 0x20u -#define MIPI_HSI_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT_SHIFT 5 -#define MIPI_HSI_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK_MASK 0x40u -#define MIPI_HSI_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK_SHIFT 6 -#define MIPI_HSI_DPHY_CMN_CTRL_RSVD7_MASK 0x3FFF80u -#define MIPI_HSI_DPHY_CMN_CTRL_RSVD7_SHIFT 7 -#define MIPI_HSI_DPHY_CMN_CTRL_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_CMN_CTRL_RSVD7_SHIFT))&MIPI_HSI_DPHY_CMN_CTRL_RSVD7_MASK) -#define MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL_MASK 0xC00000u -#define MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL_SHIFT 22 -#define MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL_SHIFT))&MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL_MASK) -#define MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE_MASK 0xFF000000u -#define MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE_SHIFT 24 -#define MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE_SHIFT))&MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE_MASK) -/* DPHY_BCTRL_L Bit Fields */ -#define MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL_MASK 0xFFFFFFFFu -#define MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL_SHIFT 0 -#define MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL_SHIFT))&MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL_MASK) -/* DPHY_BCTRL_H Bit Fields */ -#define MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL_MASK 0xFFFFFFFFu -#define MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL_SHIFT 0 -#define MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL_SHIFT))&MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL_MASK) -/* DPHY_SCTRL_L Bit Fields */ -#define MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL_MASK 0xFFFFFFFFu -#define MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL_SHIFT 0 -#define MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL_SHIFT))&MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL_MASK) -/* DPHY_SCTRL_H Bit Fields */ -#define MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL_MASK 0xFFFFFFFFu -#define MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL_SHIFT 0 -#define MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL_SHIFT))&MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL_MASK) -/* ISP_CONFIG_CH0 Bit Fields */ -#define MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_MASK 0x3u -#define MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT 0 -#define MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT))&MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_MASK) -#define MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT_MASK 0xFCu -#define MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT_SHIFT 2 -#define MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT_SHIFT))&MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT_MASK) -#define MIPI_HSI_ISP_CONFIG_CH0_DECOMP_EN_MASK 0x100u -#define MIPI_HSI_ISP_CONFIG_CH0_DECOMP_EN_SHIFT 8 -#define MIPI_HSI_ISP_CONFIG_CH0_DECOMP_PREDICT_MASK 0x200u -#define MIPI_HSI_ISP_CONFIG_CH0_DECOMP_PREDICT_SHIFT 9 -#define MIPI_HSI_ISP_CONFIG_CH0_RGB_SWAP_MASK 0x400u -#define MIPI_HSI_ISP_CONFIG_CH0_RGB_SWAP_SHIFT 10 -#define MIPI_HSI_ISP_CONFIG_CH0_PARALLEL_MASK 0x800u -#define MIPI_HSI_ISP_CONFIG_CH0_PARALLEL_SHIFT 11 -#define MIPI_HSI_ISP_CONFIG_CH0_DOUBLE_CMPNT_MASK 0x1000u -#define MIPI_HSI_ISP_CONFIG_CH0_DOUBLE_CMPNT_SHIFT 12 -#define MIPI_HSI_ISP_CONFIG_CH0_RSVD8_MASK 0xFFE000u -#define MIPI_HSI_ISP_CONFIG_CH0_RSVD8_SHIFT 13 -#define MIPI_HSI_ISP_CONFIG_CH0_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_CONFIG_CH0_RSVD8_SHIFT))&MIPI_HSI_ISP_CONFIG_CH0_RSVD8_MASK) -#define MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP_MASK 0xFF000000u -#define MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP_SHIFT 24 -#define MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP_SHIFT))&MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP_MASK) -/* ISP_RESOL_CH0 Bit Fields */ -#define MIPI_HSI_ISP_RESOL_CH0_HRESOL_MASK 0xFFFFu -#define MIPI_HSI_ISP_RESOL_CH0_HRESOL_SHIFT 0 -#define MIPI_HSI_ISP_RESOL_CH0_HRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_RESOL_CH0_HRESOL_SHIFT))&MIPI_HSI_ISP_RESOL_CH0_HRESOL_MASK) -#define MIPI_HSI_ISP_RESOL_CH0_VRESOL_MASK 0xFFFF0000u -#define MIPI_HSI_ISP_RESOL_CH0_VRESOL_SHIFT 16 -#define MIPI_HSI_ISP_RESOL_CH0_VRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_RESOL_CH0_VRESOL_SHIFT))&MIPI_HSI_ISP_RESOL_CH0_VRESOL_MASK) -/* ISP_SYNC_CH0 Bit Fields */ -#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV_MASK 0xFFFu -#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV_SHIFT 0 -#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV_SHIFT))&MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV_MASK) -#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV_MASK 0x3F000u -#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV_SHIFT 12 -#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV_SHIFT))&MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV_MASK) -#define MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV_MASK 0xFC0000u -#define MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV_SHIFT 18 -#define MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV_SHIFT))&MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV_MASK) -#define MIPI_HSI_ISP_SYNC_CH0_RSVD9_MASK 0xFF000000u -#define MIPI_HSI_ISP_SYNC_CH0_RSVD9_SHIFT 24 -#define MIPI_HSI_ISP_SYNC_CH0_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_SYNC_CH0_RSVD9_SHIFT))&MIPI_HSI_ISP_SYNC_CH0_RSVD9_MASK) -/* SDW_CONFIG_CH0 Bit Fields */ -#define MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_MASK 0x3u -#define MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT 0 -#define MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT))&MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_MASK) -#define MIPI_HSI_SDW_CONFIG_CH0_DataFormat_MASK 0xFCu -#define MIPI_HSI_SDW_CONFIG_CH0_DataFormat_SHIFT 2 -#define MIPI_HSI_SDW_CONFIG_CH0_DataFormat(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_CONFIG_CH0_DataFormat_SHIFT))&MIPI_HSI_SDW_CONFIG_CH0_DataFormat_MASK) -#define MIPI_HSI_SDW_CONFIG_CH0_DECOMP_EN_SDW_MASK 0x100u -#define MIPI_HSI_SDW_CONFIG_CH0_DECOMP_EN_SDW_SHIFT 8 -#define MIPI_HSI_SDW_CONFIG_CH0_DECOMP_PREDICT_SDW_MASK 0x200u -#define MIPI_HSI_SDW_CONFIG_CH0_DECOMP_PREDICT_SDW_SHIFT 9 -#define MIPI_HSI_SDW_CONFIG_CH0_RGB_SWAP_SDW_MASK 0x400u -#define MIPI_HSI_SDW_CONFIG_CH0_RGB_SWAP_SDW_SHIFT 10 -#define MIPI_HSI_SDW_CONFIG_CH0_PARALLEL_SDW_MASK 0x800u -#define MIPI_HSI_SDW_CONFIG_CH0_PARALLEL_SDW_SHIFT 11 -#define MIPI_HSI_SDW_CONFIG_CH0_DOUBLE_CMPNT_SDW_MASK 0x1000u -#define MIPI_HSI_SDW_CONFIG_CH0_DOUBLE_CMPNT_SDW_SHIFT 12 -#define MIPI_HSI_SDW_CONFIG_CH0_RSVD10_MASK 0xFFE000u -#define MIPI_HSI_SDW_CONFIG_CH0_RSVD10_SHIFT 13 -#define MIPI_HSI_SDW_CONFIG_CH0_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_CONFIG_CH0_RSVD10_SHIFT))&MIPI_HSI_SDW_CONFIG_CH0_RSVD10_MASK) -#define MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_MASK 0xFF000000u -#define MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_SHIFT 24 -#define MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_SHIFT))&MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_MASK) -/* SDW_RESOL_CH0 Bit Fields */ -#define MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW_MASK 0xFFFFu -#define MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW_SHIFT 0 -#define MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW_SHIFT))&MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW_MASK) -#define MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW_MASK 0xFFFF0000u -#define MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW_SHIFT 16 -#define MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW_SHIFT))&MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW_MASK) -/* SDW_SYNC_CH0 Bit Fields */ -#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW_MASK 0xFFFu -#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW_SHIFT 0 -#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW_SHIFT))&MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW_MASK) -#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW_MASK 0x3F000u -#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW_SHIFT 12 -#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW_SHIFT))&MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW_MASK) -#define MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW_MASK 0xFC0000u -#define MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW_SHIFT 18 -#define MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW_SHIFT))&MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW_MASK) -#define MIPI_HSI_SDW_SYNC_CH0_RSVD11_MASK 0xFF000000u -#define MIPI_HSI_SDW_SYNC_CH0_RSVD11_SHIFT 24 -#define MIPI_HSI_SDW_SYNC_CH0_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_SYNC_CH0_RSVD11_SHIFT))&MIPI_HSI_SDW_SYNC_CH0_RSVD11_MASK) -/* DBG_CTRL Bit Fields */ -#define MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT_MASK 0xFu -#define MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT_SHIFT 0 -#define MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT_SHIFT))&MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT_MASK) -#define MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME_MASK 0xF0u -#define MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME_SHIFT 4 -#define MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME_SHIFT))&MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME_MASK) -#define MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_MASK 0xF00u -#define MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_SHIFT 8 -#define MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_SHIFT))&MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_MASK) -#define MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE_MASK 0xF000u -#define MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE_SHIFT 12 -#define MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE_SHIFT))&MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE_MASK) -#define MIPI_HSI_DBG_CTRL_RSVD12_MASK 0xFFFF0000u -#define MIPI_HSI_DBG_CTRL_RSVD12_SHIFT 16 -#define MIPI_HSI_DBG_CTRL_RSVD12(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_RSVD12_SHIFT))&MIPI_HSI_DBG_CTRL_RSVD12_MASK) -/* DBG_INTR_MSK Bit Fields */ -#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE_MASK 0xFu -#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE_SHIFT 0 -#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE_SHIFT))&MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE_MASK) -#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL_MASK 0xF0u -#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL_SHIFT 4 -#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL_SHIFT))&MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL_MASK) -#define MIPI_HSI_DBG_INTR_MSK_EARLY_FS_MASK 0xF00u -#define MIPI_HSI_DBG_INTR_MSK_EARLY_FS_SHIFT 8 -#define MIPI_HSI_DBG_INTR_MSK_EARLY_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_EARLY_FS_SHIFT))&MIPI_HSI_DBG_INTR_MSK_EARLY_FS_MASK) -#define MIPI_HSI_DBG_INTR_MSK_EARLY_FE_MASK 0xF000u -#define MIPI_HSI_DBG_INTR_MSK_EARLY_FE_SHIFT 12 -#define MIPI_HSI_DBG_INTR_MSK_EARLY_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_EARLY_FE_SHIFT))&MIPI_HSI_DBG_INTR_MSK_EARLY_FE_MASK) -#define MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME_MASK 0xF0000u -#define MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME_SHIFT 16 -#define MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME_SHIFT))&MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME_MASK) -#define MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE_MASK 0xF00000u -#define MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE_SHIFT 20 -#define MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE_SHIFT))&MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE_MASK) -#define MIPI_HSI_DBG_INTR_MSK_DT_IGNORE_MASK 0x1000000u -#define MIPI_HSI_DBG_INTR_MSK_DT_IGNORE_SHIFT 24 -#define MIPI_HSI_DBG_INTR_MSK_DT_NOT_SUPPORT_MASK 0x2000000u -#define MIPI_HSI_DBG_INTR_MSK_DT_NOT_SUPPORT_SHIFT 25 -#define MIPI_HSI_DBG_INTR_MSK_RSVD13_MASK 0xFC000000u -#define MIPI_HSI_DBG_INTR_MSK_RSVD13_SHIFT 26 -#define MIPI_HSI_DBG_INTR_MSK_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_RSVD13_SHIFT))&MIPI_HSI_DBG_INTR_MSK_RSVD13_MASK) -/* DBG_INTR_SRC Bit Fields */ -#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE_MASK 0xFu -#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE_SHIFT 0 -#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE_SHIFT))&MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE_MASK) -#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL_MASK 0xF0u -#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL_SHIFT 4 -#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL_SHIFT))&MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL_MASK) -#define MIPI_HSI_DBG_INTR_SRC_EARLY_FS_MASK 0xF00u -#define MIPI_HSI_DBG_INTR_SRC_EARLY_FS_SHIFT 8 -#define MIPI_HSI_DBG_INTR_SRC_EARLY_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_EARLY_FS_SHIFT))&MIPI_HSI_DBG_INTR_SRC_EARLY_FS_MASK) -#define MIPI_HSI_DBG_INTR_SRC_EARLY_FE_MASK 0xF000u -#define MIPI_HSI_DBG_INTR_SRC_EARLY_FE_SHIFT 12 -#define MIPI_HSI_DBG_INTR_SRC_EARLY_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_EARLY_FE_SHIFT))&MIPI_HSI_DBG_INTR_SRC_EARLY_FE_MASK) -#define MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME_MASK 0xF0000u -#define MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME_SHIFT 16 -#define MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME_SHIFT))&MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME_MASK) -#define MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE_MASK 0xF00000u -#define MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE_SHIFT 20 -#define MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE_SHIFT))&MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE_MASK) -#define MIPI_HSI_DBG_INTR_SRC_DT_IGNORE_MASK 0x1000000u -#define MIPI_HSI_DBG_INTR_SRC_DT_IGNORE_SHIFT 24 -#define MIPI_HSI_DBG_INTR_SRC_DT_NOT_SUPPURT_MASK 0x2000000u -#define MIPI_HSI_DBG_INTR_SRC_DT_NOT_SUPPURT_SHIFT 25 -#define MIPI_HSI_DBG_INTR_SRC_RSVD14_MASK 0xFC000000u -#define MIPI_HSI_DBG_INTR_SRC_RSVD14_SHIFT 26 -#define MIPI_HSI_DBG_INTR_SRC_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_RSVD14_SHIFT))&MIPI_HSI_DBG_INTR_SRC_RSVD14_MASK) -/* NON_IMG_DATA Bit Fields */ -#define MIPI_HSI_NON_IMG_DATA_NONIMGDATA_MASK 0xFFFFFFFFu -#define MIPI_HSI_NON_IMG_DATA_NONIMGDATA_SHIFT 0 -#define MIPI_HSI_NON_IMG_DATA_NONIMGDATA(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_NON_IMG_DATA_NONIMGDATA_SHIFT))&MIPI_HSI_NON_IMG_DATA_NONIMGDATA_MASK) - -/*! - * @} - */ /* end of group MIPI_HSI_Register_Masks */ - - -/* MIPI_HSI - Peripheral instance base addresses */ -/** Peripheral MIPI_HSI base address */ -#define MIPI_HSI_BASE (0x30750000u) -/** Peripheral MIPI_HSI base pointer */ -#define MIPI_HSI ((MIPI_HSI_Type *)MIPI_HSI_BASE) -#define MIPI_HSI_BASE_PTR (MIPI_HSI) -/** Array initializer of MIPI_HSI peripheral base adresses */ -#define MIPI_HSI_BASE_ADDRS { MIPI_HSI_BASE } -/** Array initializer of MIPI_HSI peripheral base pointers */ -#define MIPI_HSI_BASE_PTRS { MIPI_HSI } - /* ---------------------------------------------------------------------------- - -- MIPI_HSI - Register accessor macros + -- MU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup MIPI_HSI_Register_Accessor_Macros MIPI_HSI - Register accessor macros + * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer * @{ */ - -/* MIPI_HSI - Register instance definitions */ -/* MIPI_HSI */ -#define MIPI_HSI_CSIS_CMN_CTRL MIPI_HSI_CSIS_CMN_CTRL_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_CSIS_CLK_CTRL MIPI_HSI_CSIS_CLK_CTRL_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_CSIS_INT_MSK MIPI_HSI_CSIS_INT_MSK_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_CSIS_INT_SRC MIPI_HSI_CSIS_INT_SRC_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DPHY_STATUS MIPI_HSI_DPHY_STATUS_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DPHY_CMN_CTRL MIPI_HSI_DPHY_CMN_CTRL_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DPHY_BCTRL_L MIPI_HSI_DPHY_BCTRL_L_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DPHY_BCTRL_H MIPI_HSI_DPHY_BCTRL_H_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DPHY_SCTRL_L MIPI_HSI_DPHY_SCTRL_L_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DPHY_SCTRL_H MIPI_HSI_DPHY_SCTRL_H_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_ISP_CONFIG_CH0 MIPI_HSI_ISP_CONFIG_CH0_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_ISP_RESOL_CH0 MIPI_HSI_ISP_RESOL_CH0_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_ISP_SYNC_CH0 MIPI_HSI_ISP_SYNC_CH0_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_SDW_CONFIG_CH0 MIPI_HSI_SDW_CONFIG_CH0_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_SDW_RESOL_CH0 MIPI_HSI_SDW_RESOL_CH0_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_SDW_SYNC_CH0 MIPI_HSI_SDW_SYNC_CH0_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DBG_CTRL MIPI_HSI_DBG_CTRL_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DBG_INTR_MSK MIPI_HSI_DBG_INTR_MSK_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_DBG_INTR_SRC MIPI_HSI_DBG_INTR_SRC_REG(MIPI_HSI_BASE_PTR) -#define MIPI_HSI_NON_IMG_DATA MIPI_HSI_NON_IMG_DATA_REG(MIPI_HSI_BASE_PTR) - -/*! - * @} - */ /* end of group MIPI_HSI_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group MIPI_HSI_Peripheral */ - - -/* ---------------------------------------------------------------------------- - -- MU Peripheral Access Layer - ---------------------------------------------------------------------------- */ +/** MU - Register Layout Typedef */ typedef struct { - __IO uint32_t TR[4]; /**< Processor B Transmit Register 0, offset: 0x0 */ - __I uint32_t RR[4]; /**< Processor B Receive Register 0, offset: 0x10 */ - __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */ - __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */ + __IO uint32_t TR[4]; /**< Processor B Transmit Register 0, array offset: 0x0, array step: 0x4 */ + __I uint32_t RR[4]; /**< Processor B Receive Register 0, array offset: 0x10, array step: 0x4 */ + __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */ + __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */ } MU_Type, *MU_MemMapPtr; - /* ---------------------------------------------------------------------------- -- MU - Register accessor macros ---------------------------------------------------------------------------- */ @@ -80965,8 +30891,6 @@ typedef struct { /*! * @} */ /* end of group MU_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- MU Register Masks ---------------------------------------------------------------------------- */ @@ -80975,87 +30899,72 @@ typedef struct { * @addtogroup MU_Register_Masks MU Register Masks * @{ */ + /* TR Bit Fields */ -#define MU_TR_DATA_MASK 0xFFFFFFFFu -#define MU_TR_DATA_SHIFT 0 -#define MU_TR_DATA_WIDTH 32 -#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x))<<MU_TR_DATA_SHIFT))&MU_TR_DATA_MASK) +#define MU_TR_TR0_MASK 0xFFFFFFFFu +#define MU_TR_TR0_SHIFT 0 +#define MU_TR_TR0(x) (((uint32_t)(((uint32_t)(x))<<MU_TR_TR0_SHIFT))&MU_TR_TR0_MASK) /* RR Bit Fields */ -#define MU_RR_DATA_MASK 0xFFFFFFFFu -#define MU_RR_DATA_SHIFT 0 -#define MU_RR_DATA_WIDTH 32 -#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x))<<MU_RR_DATA_SHIFT))&MU_RR_DATA_MASK) +#define MU_RR_RR0_MASK 0xFFFFFFFFu +#define MU_RR_RR0_SHIFT 0 +#define MU_RR_RR0(x) (((uint32_t)(((uint32_t)(x))<<MU_RR_RR0_SHIFT))&MU_RR_RR0_MASK) /* SR Bit Fields */ #define MU_SR_Fn_MASK 0x7u #define MU_SR_Fn_SHIFT 0 -#define MU_SR_Fn_WIDTH 3 #define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_Fn_SHIFT))&MU_SR_Fn_MASK) #define MU_SR_EP_MASK 0x10u #define MU_SR_EP_SHIFT 4 -#define MU_SR_EP_WIDTH 1 -#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_EP_SHIFT))&MU_SR_EP_MASK) #define MU_SR_PM_MASK 0x60u #define MU_SR_PM_SHIFT 5 -#define MU_SR_PM_WIDTH 2 #define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_PM_SHIFT))&MU_SR_PM_MASK) #define MU_SR_RS_MASK 0x80u #define MU_SR_RS_SHIFT 7 -#define MU_SR_RS_WIDTH 1 -#define MU_SR_RS(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_RS_SHIFT))&MU_SR_RS_MASK) #define MU_SR_FUP_MASK 0x100u #define MU_SR_FUP_SHIFT 8 -#define MU_SR_FUP_WIDTH 1 -#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_FUP_SHIFT))&MU_SR_FUP_MASK) #define MU_SR_TEn_MASK 0xF00000u #define MU_SR_TEn_SHIFT 20 -#define MU_SR_TEn_WIDTH 4 #define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_TEn_SHIFT))&MU_SR_TEn_MASK) #define MU_SR_RFn_MASK 0xF000000u #define MU_SR_RFn_SHIFT 24 -#define MU_SR_RFn_WIDTH 4 #define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_RFn_SHIFT))&MU_SR_RFn_MASK) #define MU_SR_GIPn_MASK 0xF0000000u #define MU_SR_GIPn_SHIFT 28 -#define MU_SR_GIPn_WIDTH 4 #define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_GIPn_SHIFT))&MU_SR_GIPn_MASK) /* CR Bit Fields */ #define MU_CR_Fn_MASK 0x7u #define MU_CR_Fn_SHIFT 0 -#define MU_CR_Fn_WIDTH 3 #define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_Fn_SHIFT))&MU_CR_Fn_MASK) +#define MU_CR_HRM_MASK 0x10u +#define MU_CR_HRM_SHIFT 4 #define MU_CR_GIRn_MASK 0xF0000u #define MU_CR_GIRn_SHIFT 16 -#define MU_CR_GIRn_WIDTH 4 #define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_GIRn_SHIFT))&MU_CR_GIRn_MASK) #define MU_CR_TIEn_MASK 0xF00000u #define MU_CR_TIEn_SHIFT 20 -#define MU_CR_TIEn_WIDTH 4 #define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_TIEn_SHIFT))&MU_CR_TIEn_MASK) #define MU_CR_RIEn_MASK 0xF000000u #define MU_CR_RIEn_SHIFT 24 -#define MU_CR_RIEn_WIDTH 4 #define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_RIEn_SHIFT))&MU_CR_RIEn_MASK) #define MU_CR_GIEn_MASK 0xF0000000u #define MU_CR_GIEn_SHIFT 28 -#define MU_CR_GIEn_WIDTH 4 #define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_GIEn_SHIFT))&MU_CR_GIEn_MASK) /*! * @} */ /* end of group MU_Register_Masks */ - /* MU - Peripheral instance base addresses */ -/** Peripheral MU0_B base address */ -#define MU0_B_BASE (0x30AB0000u) -/** Peripheral MU0_B base pointer */ -#define MU0_B ((MU_Type *)MU0_B_BASE) -#define MU0_B_BASE_PTR (MU0_B) -/** Array initializer of MU peripheral base adresses */ -#define MU_BASE_ADDRS { MU0_B_BASE } +/** Peripheral MUB base address */ +#define MUB_BASE (0x30AB0000u) +/** Peripheral MUB base pointer */ +#define MUB ((MU_Type *)MUB_BASE) +#define MUB_BASE_PTR (MUB) +/** Array initializer of MU peripheral base addresses */ +#define MU_BASE_ADDRS { MUB_BASE } /** Array initializer of MU peripheral base pointers */ -#define MU_BASE_PTRS { MU0_B } - +#define MU_BASE_PTRS { MUB } +/** Interrupt vectors for the MU peripheral type */ +#define MU_IRQS { MU_M4_IRQn } /* ---------------------------------------------------------------------------- -- MU - Register accessor macros ---------------------------------------------------------------------------- */ @@ -81067,18 +30976,20 @@ typedef struct { /* MU - Register instance definitions */ -/* MU0_B */ -#define MU0_B_TR0 MU_TR_REG(MU0_B,0) -#define MU0_B_TR1 MU_TR_REG(MU0_B,1) -#define MU0_B_TR2 MU_TR_REG(MU0_B,2) -#define MU0_B_TR3 MU_TR_REG(MU0_B,3) -#define MU0_B_RR0 MU_RR_REG(MU0_B,0) -#define MU0_B_RR1 MU_RR_REG(MU0_B,1) -#define MU0_B_RR2 MU_RR_REG(MU0_B,2) -#define MU0_B_RR3 MU_RR_REG(MU0_B,3) -#define MU0_B_SR MU_SR_REG(MU0_B) -#define MU0_B_CR MU_CR_REG(MU0_B) - +/* MUB */ +#define MUB_TR0 MU_TR_REG(MUB_BASE_PTR,0) +#define MUB_TR1 MU_TR_REG(MUB_BASE_PTR,1) +#define MUB_TR2 MU_TR_REG(MUB_BASE_PTR,2) +#define MUB_TR3 MU_TR_REG(MUB_BASE_PTR,3) +#define MUB_RR0 MU_RR_REG(MUB_BASE_PTR,0) +#define MUB_RR1 MU_RR_REG(MUB_BASE_PTR,1) +#define MUB_RR2 MU_RR_REG(MUB_BASE_PTR,2) +#define MUB_RR3 MU_RR_REG(MUB_BASE_PTR,3) +#define MUB_SR MU_SR_REG(MUB_BASE_PTR) +#define MUB_CR MU_CR_REG(MUB_BASE_PTR) +/* MU - Register array accessors */ +#define MUB_TR(index) MU_TR_REG(MUB_BASE_PTR,index) +#define MUB_RR(index) MU_RR_REG(MUB_BASE_PTR,index) /*! * @} */ /* end of group MU_Register_Accessor_Macros */ @@ -81088,7 +30999,6 @@ typedef struct { * @} */ /* end of group MU_Peripheral */ - /* ---------------------------------------------------------------------------- -- OCOTP Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -81231,40 +31141,23 @@ typedef struct { __IO uint32_t MAU_KEY6; /**< Shadow Register for OTP Bank11 Word2 (MAU Key), offset: 0x6E0 */ uint8_t RESERVED_60[12]; __IO uint32_t MAU_KEY7; /**< Shadow Register for OTP Bank11 Word3 (MAU Key), offset: 0x6F0 */ - uint8_t RESERVED_61[12]; - __IO uint32_t ROM_PATCH0; /**< Value of OTP Bank12 Word0 (Rom Patch), offset: 0x700 */ - uint8_t RESERVED_62[12]; - __IO uint32_t ROM_PATCH1; /**< Value of OTP Bank12 Word1 (Rom Patch), offset: 0x710 */ - uint8_t RESERVED_63[12]; - __IO uint32_t ROM_PATCH2; /**< Value of OTP Bank12 Word2 (Rom Patch), offset: 0x720 */ - uint8_t RESERVED_64[12]; - __IO uint32_t ROM_PATCH3; /**< Value of OTP Bank12 Word3 (Rom Patch), offset: 0x730 */ - uint8_t RESERVED_65[12]; - __IO uint32_t ROM_PATCH4; /**< Value of OTP Bank13 Word0 (Rom Patch), offset: 0x740 */ - uint8_t RESERVED_66[12]; - __IO uint32_t ROM_PATCH5; /**< Value of OTP Bank13 Word1 (Rom Patch), offset: 0x750 */ - uint8_t RESERVED_67[12]; - __IO uint32_t ROM_PATCH6; /**< Value of OTP Bank13 Word2 (Rom Patch), offset: 0x760 */ - uint8_t RESERVED_68[12]; - __IO uint32_t ROM_PATCH7; /**< Value of OTP Bank13 Word3 (Rom Patch), offset: 0x770 */ - uint8_t RESERVED_69[12]; + uint8_t RESERVED_61[140]; __IO uint32_t GP10; /**< Value of OTP Bank14 Word0, offset: 0x780 */ - uint8_t RESERVED_70[12]; + uint8_t RESERVED_62[12]; __IO uint32_t GP11; /**< Value of OTP Bank14 Word1, offset: 0x790 */ - uint8_t RESERVED_71[12]; + uint8_t RESERVED_63[12]; __IO uint32_t GP20; /**< Value of OTP Bank14 Word2, offset: 0x7A0 */ - uint8_t RESERVED_72[12]; + uint8_t RESERVED_64[12]; __IO uint32_t GP21; /**< Value of OTP Bank14 Word3, offset: 0x7B0 */ - uint8_t RESERVED_73[12]; + uint8_t RESERVED_65[12]; __IO uint32_t CRC_GP10; /**< Value of OTP Bank15 Word0 (CRC Key), offset: 0x7C0 */ - uint8_t RESERVED_74[12]; + uint8_t RESERVED_66[12]; __IO uint32_t CRC_GP11; /**< Value of OTP Bank15 Word1 (CRC Key), offset: 0x7D0 */ - uint8_t RESERVED_75[12]; + uint8_t RESERVED_67[12]; __IO uint32_t CRC_GP20; /**< Value of OTP Bank15 Word2 (CRC Key), offset: 0x7E0 */ - uint8_t RESERVED_76[12]; + uint8_t RESERVED_68[12]; __IO uint32_t CRC_GP21; /**< Value of OTP Bank15 Word3 (CRC Key), offset: 0x7F0 */ } OCOTP_Type, *OCOTP_MemMapPtr; - /* ---------------------------------------------------------------------------- -- OCOTP - Register accessor macros ---------------------------------------------------------------------------- */ @@ -81346,14 +31239,6 @@ typedef struct { #define OCOTP_MAU_KEY5_REG(base) ((base)->MAU_KEY5) #define OCOTP_MAU_KEY6_REG(base) ((base)->MAU_KEY6) #define OCOTP_MAU_KEY7_REG(base) ((base)->MAU_KEY7) -#define OCOTP_ROM_PATCH0_REG(base) ((base)->ROM_PATCH0) -#define OCOTP_ROM_PATCH1_REG(base) ((base)->ROM_PATCH1) -#define OCOTP_ROM_PATCH2_REG(base) ((base)->ROM_PATCH2) -#define OCOTP_ROM_PATCH3_REG(base) ((base)->ROM_PATCH3) -#define OCOTP_ROM_PATCH4_REG(base) ((base)->ROM_PATCH4) -#define OCOTP_ROM_PATCH5_REG(base) ((base)->ROM_PATCH5) -#define OCOTP_ROM_PATCH6_REG(base) ((base)->ROM_PATCH6) -#define OCOTP_ROM_PATCH7_REG(base) ((base)->ROM_PATCH7) #define OCOTP_GP10_REG(base) ((base)->GP10) #define OCOTP_GP11_REG(base) ((base)->GP11) #define OCOTP_GP20_REG(base) ((base)->GP20) @@ -81366,8 +31251,6 @@ typedef struct { /*! * @} */ /* end of group OCOTP_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- OCOTP Register Masks ---------------------------------------------------------------------------- */ @@ -81473,11 +31356,11 @@ typedef struct { #define OCOTP_TIMING_PROG_MASK 0xFFFu #define OCOTP_TIMING_PROG_SHIFT 0 #define OCOTP_TIMING_PROG(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_PROG_SHIFT))&OCOTP_TIMING_PROG_MASK) -#define OCOTP_TIMING_FSOURCE_MASK 0x7F000u +#define OCOTP_TIMING_FSOURCE_MASK 0xFF000u #define OCOTP_TIMING_FSOURCE_SHIFT 12 #define OCOTP_TIMING_FSOURCE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_FSOURCE_SHIFT))&OCOTP_TIMING_FSOURCE_MASK) -#define OCOTP_TIMING_RSRVD0_MASK 0xFFF80000u -#define OCOTP_TIMING_RSRVD0_SHIFT 19 +#define OCOTP_TIMING_RSRVD0_MASK 0xFFF00000u +#define OCOTP_TIMING_RSRVD0_SHIFT 20 #define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_RSRVD0_SHIFT))&OCOTP_TIMING_RSRVD0_MASK) /* DATA0 Bit Fields */ #define OCOTP_DATA0_DATA0_MASK 0xFFFFFFFFu @@ -81823,38 +31706,6 @@ typedef struct { #define OCOTP_MAU_KEY7_BITS_MASK 0xFFFFFFFFu #define OCOTP_MAU_KEY7_BITS_SHIFT 0 #define OCOTP_MAU_KEY7_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY7_BITS_SHIFT))&OCOTP_MAU_KEY7_BITS_MASK) -/* ROM_PATCH0 Bit Fields */ -#define OCOTP_ROM_PATCH0_BITS_MASK 0xFFFFFFFFu -#define OCOTP_ROM_PATCH0_BITS_SHIFT 0 -#define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH0_BITS_SHIFT))&OCOTP_ROM_PATCH0_BITS_MASK) -/* ROM_PATCH1 Bit Fields */ -#define OCOTP_ROM_PATCH1_BITS_MASK 0xFFFFFFFFu -#define OCOTP_ROM_PATCH1_BITS_SHIFT 0 -#define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH1_BITS_SHIFT))&OCOTP_ROM_PATCH1_BITS_MASK) -/* ROM_PATCH2 Bit Fields */ -#define OCOTP_ROM_PATCH2_BITS_MASK 0xFFFFFFFFu -#define OCOTP_ROM_PATCH2_BITS_SHIFT 0 -#define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH2_BITS_SHIFT))&OCOTP_ROM_PATCH2_BITS_MASK) -/* ROM_PATCH3 Bit Fields */ -#define OCOTP_ROM_PATCH3_BITS_MASK 0xFFFFFFFFu -#define OCOTP_ROM_PATCH3_BITS_SHIFT 0 -#define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH3_BITS_SHIFT))&OCOTP_ROM_PATCH3_BITS_MASK) -/* ROM_PATCH4 Bit Fields */ -#define OCOTP_ROM_PATCH4_BITS_MASK 0xFFFFFFFFu -#define OCOTP_ROM_PATCH4_BITS_SHIFT 0 -#define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH4_BITS_SHIFT))&OCOTP_ROM_PATCH4_BITS_MASK) -/* ROM_PATCH5 Bit Fields */ -#define OCOTP_ROM_PATCH5_BITS_MASK 0xFFFFFFFFu -#define OCOTP_ROM_PATCH5_BITS_SHIFT 0 -#define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH5_BITS_SHIFT))&OCOTP_ROM_PATCH5_BITS_MASK) -/* ROM_PATCH6 Bit Fields */ -#define OCOTP_ROM_PATCH6_BITS_MASK 0xFFFFFFFFu -#define OCOTP_ROM_PATCH6_BITS_SHIFT 0 -#define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH6_BITS_SHIFT))&OCOTP_ROM_PATCH6_BITS_MASK) -/* ROM_PATCH7 Bit Fields */ -#define OCOTP_ROM_PATCH7_BITS_MASK 0xFFFFFFFFu -#define OCOTP_ROM_PATCH7_BITS_SHIFT 0 -#define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH7_BITS_SHIFT))&OCOTP_ROM_PATCH7_BITS_MASK) /* GP10 Bit Fields */ #define OCOTP_GP10_BITS_MASK 0xFFFFFFFFu #define OCOTP_GP10_BITS_SHIFT 0 @@ -81892,18 +31743,16 @@ typedef struct { * @} */ /* end of group OCOTP_Register_Masks */ - /* OCOTP - Peripheral instance base addresses */ /** Peripheral OCOTP base address */ #define OCOTP_BASE (0x30350000u) /** Peripheral OCOTP base pointer */ #define OCOTP ((OCOTP_Type *)OCOTP_BASE) #define OCOTP_BASE_PTR (OCOTP) -/** Array initializer of OCOTP peripheral base adresses */ +/** Array initializer of OCOTP peripheral base addresses */ #define OCOTP_BASE_ADDRS { OCOTP_BASE } /** Array initializer of OCOTP peripheral base pointers */ #define OCOTP_BASE_PTRS { OCOTP } - /* ---------------------------------------------------------------------------- -- OCOTP - Register accessor macros ---------------------------------------------------------------------------- */ @@ -81986,14 +31835,6 @@ typedef struct { #define OCOTP_MAU_KEY5 OCOTP_MAU_KEY5_REG(OCOTP_BASE_PTR) #define OCOTP_MAU_KEY6 OCOTP_MAU_KEY6_REG(OCOTP_BASE_PTR) #define OCOTP_MAU_KEY7 OCOTP_MAU_KEY7_REG(OCOTP_BASE_PTR) -#define OCOTP_ROM_PATCH0 OCOTP_ROM_PATCH0_REG(OCOTP_BASE_PTR) -#define OCOTP_ROM_PATCH1 OCOTP_ROM_PATCH1_REG(OCOTP_BASE_PTR) -#define OCOTP_ROM_PATCH2 OCOTP_ROM_PATCH2_REG(OCOTP_BASE_PTR) -#define OCOTP_ROM_PATCH3 OCOTP_ROM_PATCH3_REG(OCOTP_BASE_PTR) -#define OCOTP_ROM_PATCH4 OCOTP_ROM_PATCH4_REG(OCOTP_BASE_PTR) -#define OCOTP_ROM_PATCH5 OCOTP_ROM_PATCH5_REG(OCOTP_BASE_PTR) -#define OCOTP_ROM_PATCH6 OCOTP_ROM_PATCH6_REG(OCOTP_BASE_PTR) -#define OCOTP_ROM_PATCH7 OCOTP_ROM_PATCH7_REG(OCOTP_BASE_PTR) #define OCOTP_GP10 OCOTP_GP10_REG(OCOTP_BASE_PTR) #define OCOTP_GP11 OCOTP_GP11_REG(OCOTP_BASE_PTR) #define OCOTP_GP20 OCOTP_GP20_REG(OCOTP_BASE_PTR) @@ -82002,7 +31843,6 @@ typedef struct { #define OCOTP_CRC_GP11 OCOTP_CRC_GP11_REG(OCOTP_BASE_PTR) #define OCOTP_CRC_GP20 OCOTP_CRC_GP20_REG(OCOTP_BASE_PTR) #define OCOTP_CRC_GP21 OCOTP_CRC_GP21_REG(OCOTP_BASE_PTR) - /*! * @} */ /* end of group OCOTP_Register_Accessor_Macros */ @@ -82012,7 +31852,6 @@ typedef struct { * @} */ /* end of group OCOTP_Peripheral */ - /* ---------------------------------------------------------------------------- -- PCIE_PHY_CMN Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -82025,7 +31864,7 @@ typedef struct { /** PCIE_PHY_CMN - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; - __IO uint32_t REG01; /**< Impedance Calibration Register, offset: 0x4 */ + __IO uint32_t REG01; /**< , offset: 0x4 */ __IO uint32_t REG02; /**< , offset: 0x8 */ uint8_t RESERVED_1[6]; __IO uint32_t REG03; /**< , offset: 0x12 */ @@ -82050,7 +31889,6 @@ typedef struct { uint8_t RESERVED_7[6]; __IO uint32_t REG1A; /**< , offset: 0x80 */ } PCIE_PHY_CMN_Type, *PCIE_PHY_CMN_MemMapPtr; - /* ---------------------------------------------------------------------------- -- PCIE_PHY_CMN - Register accessor macros ---------------------------------------------------------------------------- */ @@ -82083,8 +31921,6 @@ typedef struct { /*! * @} */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- PCIE_PHY_CMN Register Masks ---------------------------------------------------------------------------- */ @@ -82195,18 +32031,16 @@ typedef struct { * @} */ /* end of group PCIE_PHY_CMN_Register_Masks */ - /* PCIE_PHY_CMN - Peripheral instance base addresses */ /** Peripheral PCIE_PHY_CMN base address */ #define PCIE_PHY_CMN_BASE (0x306D0000u) /** Peripheral PCIE_PHY_CMN base pointer */ #define PCIE_PHY_CMN ((PCIE_PHY_CMN_Type *)PCIE_PHY_CMN_BASE) #define PCIE_PHY_CMN_BASE_PTR (PCIE_PHY_CMN) -/** Array initializer of PCIE_PHY_CMN peripheral base adresses */ +/** Array initializer of PCIE_PHY_CMN peripheral base addresses */ #define PCIE_PHY_CMN_BASE_ADDRS { PCIE_PHY_CMN_BASE } /** Array initializer of PCIE_PHY_CMN peripheral base pointers */ #define PCIE_PHY_CMN_BASE_PTRS { PCIE_PHY_CMN } - /* ---------------------------------------------------------------------------- -- PCIE_PHY_CMN - Register accessor macros ---------------------------------------------------------------------------- */ @@ -82236,7 +32070,6 @@ typedef struct { #define PCIE_PHY_CMN_REG18 PCIE_PHY_CMN_REG18_REG(PCIE_PHY_CMN_BASE_PTR) #define PCIE_PHY_CMN_REG19 PCIE_PHY_CMN_REG19_REG(PCIE_PHY_CMN_BASE_PTR) #define PCIE_PHY_CMN_REG1A PCIE_PHY_CMN_REG1A_REG(PCIE_PHY_CMN_BASE_PTR) - /*! * @} */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */ @@ -82246,7 +32079,6 @@ typedef struct { * @} */ /* end of group PCIE_PHY_CMN_Peripheral */ - /* ---------------------------------------------------------------------------- -- PCIE_PHY_TRSV Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -82289,7 +32121,6 @@ typedef struct { uint8_t RESERVED_12[4]; __IO uint32_t REG42; /**< , offset: 0x168 */ } PCIE_PHY_TRSV_Type, *PCIE_PHY_TRSV_MemMapPtr; - /* ---------------------------------------------------------------------------- -- PCIE_PHY_TRSV - Register accessor macros ---------------------------------------------------------------------------- */ @@ -82322,8 +32153,6 @@ typedef struct { /*! * @} */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- PCIE_PHY_TRSV Register Masks ---------------------------------------------------------------------------- */ @@ -82386,6 +32215,7 @@ typedef struct { /* REG31 Bit Fields */ #define PCIE_PHY_TRSV_REG31_PD_TSV_MASK 0x80u #define PCIE_PHY_TRSV_REG31_PD_TSV_SHIFT 7 +/* REG33 Bit Fields */ /* REG36 Bit Fields */ #define PCIE_PHY_TRSV_REG36_SR_LVL_MASK 0x7u #define PCIE_PHY_TRSV_REG36_SR_LVL_SHIFT 0 @@ -82395,6 +32225,7 @@ typedef struct { #define PCIE_PHY_TRSV_REG36_DRVR_CNT_MASK 0x30u #define PCIE_PHY_TRSV_REG36_DRVR_CNT_SHIFT 4 #define PCIE_PHY_TRSV_REG36_DRVR_CNT(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG36_DRVR_CNT_SHIFT))&PCIE_PHY_TRSV_REG36_DRVR_CNT_MASK) +/* REG37 Bit Fields */ /* REG38 Bit Fields */ #define PCIE_PHY_TRSV_REG38_ADD_ALIGN_MASK 0x8u #define PCIE_PHY_TRSV_REG38_ADD_ALIGN_SHIFT 3 @@ -82424,18 +32255,16 @@ typedef struct { * @} */ /* end of group PCIE_PHY_TRSV_Register_Masks */ - /* PCIE_PHY_TRSV - Peripheral instance base addresses */ /** Peripheral PCIE_PHY_TRSV base address */ #define PCIE_PHY_TRSV_BASE (0x306D0000u) /** Peripheral PCIE_PHY_TRSV base pointer */ #define PCIE_PHY_TRSV ((PCIE_PHY_TRSV_Type *)PCIE_PHY_TRSV_BASE) #define PCIE_PHY_TRSV_BASE_PTR (PCIE_PHY_TRSV) -/** Array initializer of PCIE_PHY_TRSV peripheral base adresses */ +/** Array initializer of PCIE_PHY_TRSV peripheral base addresses */ #define PCIE_PHY_TRSV_BASE_ADDRS { PCIE_PHY_TRSV_BASE } /** Array initializer of PCIE_PHY_TRSV peripheral base pointers */ #define PCIE_PHY_TRSV_BASE_PTRS { PCIE_PHY_TRSV } - /* ---------------------------------------------------------------------------- -- PCIE_PHY_TRSV - Register accessor macros ---------------------------------------------------------------------------- */ @@ -82465,7 +32294,6 @@ typedef struct { #define PCIE_PHY_TRSV_REG39 PCIE_PHY_TRSV_REG39_REG(PCIE_PHY_TRSV_BASE_PTR) #define PCIE_PHY_TRSV_REG40 PCIE_PHY_TRSV_REG40_REG(PCIE_PHY_TRSV_BASE_PTR) #define PCIE_PHY_TRSV_REG42 PCIE_PHY_TRSV_REG42_REG(PCIE_PHY_TRSV_BASE_PTR) - /*! * @} */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */ @@ -82475,166 +32303,6 @@ typedef struct { * @} */ /* end of group PCIE_PHY_TRSV_Peripheral */ - -/* ---------------------------------------------------------------------------- - -- PGC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer - * @{ - */ - -/** PGC - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[608]; - __IO uint32_t GPU_CTRL; /**< PGC Control Register, offset: 0x260 */ - __IO uint32_t GPU_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x264 */ - __IO uint32_t GPU_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x268 */ - __I uint32_t GPU_SR; /**< Power Gating Controller Status Register, offset: 0x26C */ - uint8_t RESERVED_1[48]; - __IO uint32_t CPU_CTRL; /**< PGC Control Register, offset: 0x2A0 */ - __IO uint32_t CPU_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x2A4 */ - __IO uint32_t CPU_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x2A8 */ - __I uint32_t CPU_SR; /**< Power Gating Controller Status Register, offset: 0x2AC */ -} PGC_Type, *PGC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- PGC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PGC_Register_Accessor_Macros PGC - Register accessor macros - * @{ - */ - - -/* PGC - Register accessors */ -#define PGC_GPU_CTRL_REG(base) ((base)->GPU_CTRL) -#define PGC_GPU_PUPSCR_REG(base) ((base)->GPU_PUPSCR) -#define PGC_GPU_PDNSCR_REG(base) ((base)->GPU_PDNSCR) -#define PGC_GPU_SR_REG(base) ((base)->GPU_SR) -#define PGC_CPU_CTRL_REG(base) ((base)->CPU_CTRL) -#define PGC_CPU_PUPSCR_REG(base) ((base)->CPU_PUPSCR) -#define PGC_CPU_PDNSCR_REG(base) ((base)->CPU_PDNSCR) -#define PGC_CPU_SR_REG(base) ((base)->CPU_SR) - -/*! - * @} - */ /* end of group PGC_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- PGC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PGC_Register_Masks PGC Register Masks - * @{ - */ - -/* GPU_CTRL Bit Fields */ -#define PGC_GPU_CTRL_PCR_MASK 0x1u -#define PGC_GPU_CTRL_PCR_SHIFT 0 -/* GPU_PUPSCR Bit Fields */ -#define PGC_GPU_PUPSCR_SW_MASK 0x3Fu -#define PGC_GPU_PUPSCR_SW_SHIFT 0 -#define PGC_GPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PUPSCR_SW_SHIFT))&PGC_GPU_PUPSCR_SW_MASK) -#define PGC_GPU_PUPSCR_SW2ISO_MASK 0x3F00u -#define PGC_GPU_PUPSCR_SW2ISO_SHIFT 8 -#define PGC_GPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PUPSCR_SW2ISO_SHIFT))&PGC_GPU_PUPSCR_SW2ISO_MASK) -/* GPU_PDNSCR Bit Fields */ -#define PGC_GPU_PDNSCR_ISO_MASK 0x3Fu -#define PGC_GPU_PDNSCR_ISO_SHIFT 0 -#define PGC_GPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PDNSCR_ISO_SHIFT))&PGC_GPU_PDNSCR_ISO_MASK) -#define PGC_GPU_PDNSCR_ISO2SW_MASK 0x3F00u -#define PGC_GPU_PDNSCR_ISO2SW_SHIFT 8 -#define PGC_GPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PDNSCR_ISO2SW_SHIFT))&PGC_GPU_PDNSCR_ISO2SW_MASK) -/* GPU_SR Bit Fields */ -#define PGC_GPU_SR_PSR_MASK 0x1u -#define PGC_GPU_SR_PSR_SHIFT 0 -/* CPU_CTRL Bit Fields */ -#define PGC_CPU_CTRL_PCR_MASK 0x1u -#define PGC_CPU_CTRL_PCR_SHIFT 0 -/* CPU_PUPSCR Bit Fields */ -#define PGC_CPU_PUPSCR_SW_MASK 0x3Fu -#define PGC_CPU_PUPSCR_SW_SHIFT 0 -#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW_SHIFT))&PGC_CPU_PUPSCR_SW_MASK) -#define PGC_CPU_PUPSCR_SW2ISO_MASK 0x3F00u -#define PGC_CPU_PUPSCR_SW2ISO_SHIFT 8 -#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW2ISO_SHIFT))&PGC_CPU_PUPSCR_SW2ISO_MASK) -/* CPU_PDNSCR Bit Fields */ -#define PGC_CPU_PDNSCR_ISO_MASK 0x3Fu -#define PGC_CPU_PDNSCR_ISO_SHIFT 0 -#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO_SHIFT))&PGC_CPU_PDNSCR_ISO_MASK) -#define PGC_CPU_PDNSCR_ISO2SW_MASK 0x3F00u -#define PGC_CPU_PDNSCR_ISO2SW_SHIFT 8 -#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO2SW_SHIFT))&PGC_CPU_PDNSCR_ISO2SW_MASK) -/* CPU_SR Bit Fields */ -#define PGC_CPU_SR_PSR_MASK 0x1u -#define PGC_CPU_SR_PSR_SHIFT 0 - -/*! - * @} - */ /* end of group PGC_Register_Masks */ - - -/* PGC - Peripheral instance base addresses */ -/** Peripheral PGC_ARM base address */ -#define PGC_ARM_BASE (0x303A0040u) -/** Peripheral PGC_ARM base pointer */ -#define PGC_ARM ((PGC_ARM_Type *)PGC_ARM_BASE) -#define PGC_ARM_BASE_PTR (PGC_ARM) -/** Peripheral PGC_GPU base address */ -#define PGC_GPU_BASE (0x303A0000u) -/** Peripheral PGC_GPU base pointer */ -#define PGC_GPU ((PGC_GPU_Type *)PGC_GPU_BASE) -#define PGC_GPU_BASE_PTR (PGC_GPU) -/** Array initializer of PGC peripheral base adresses */ -#define PGC_BASE_ADDRS { PGC_ARM_BASE, PGC_GPU_BASE } -/** Array initializer of PGC peripheral base pointers */ -#define PGC_BASE_PTRS { PGC_ARM, PGC_GPU } - -/* ---------------------------------------------------------------------------- - -- PGC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PGC_Register_Accessor_Macros PGC - Register accessor macros - * @{ - */ - - -/* PGC - Register instance definitions */ -/* PGC_ARM */ -#define PGC_ARM_GPU_CTRL PGC_GPU_CTRL_REG(PGC_ARM_BASE_PTR) -#define PGC_ARM_GPU_PUPSCR PGC_GPU_PUPSCR_REG(PGC_ARM_BASE_PTR) -#define PGC_ARM_GPU_PDNSCR PGC_GPU_PDNSCR_REG(PGC_ARM_BASE_PTR) -#define PGC_ARM_GPU_SR PGC_GPU_SR_REG(PGC_ARM_BASE_PTR) -#define PGC_ARM_CPU_CTRL PGC_CPU_CTRL_REG(PGC_ARM_BASE_PTR) -#define PGC_ARM_CPU_PUPSCR PGC_CPU_PUPSCR_REG(PGC_ARM_BASE_PTR) -#define PGC_ARM_CPU_PDNSCR PGC_CPU_PDNSCR_REG(PGC_ARM_BASE_PTR) -#define PGC_ARM_CPU_SR PGC_CPU_SR_REG(PGC_ARM_BASE_PTR) -/* PGC_GPU */ -#define PGC_GPU_GPU_CTRL PGC_GPU_CTRL_REG(PGC_GPU_BASE_PTR) -#define PGC_GPU_GPU_PUPSCR PGC_GPU_PUPSCR_REG(PGC_GPU_BASE_PTR) -#define PGC_GPU_GPU_PDNSCR PGC_GPU_PDNSCR_REG(PGC_GPU_BASE_PTR) -#define PGC_GPU_GPU_SR PGC_GPU_SR_REG(PGC_GPU_BASE_PTR) -#define PGC_GPU_CPU_CTRL PGC_CPU_CTRL_REG(PGC_GPU_BASE_PTR) -#define PGC_GPU_CPU_PUPSCR PGC_CPU_PUPSCR_REG(PGC_GPU_BASE_PTR) -#define PGC_GPU_CPU_PDNSCR PGC_CPU_PDNSCR_REG(PGC_GPU_BASE_PTR) -#define PGC_GPU_CPU_SR PGC_CPU_SR_REG(PGC_GPU_BASE_PTR) - -/*! - * @} - */ /* end of group PGC_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group PGC_Peripheral */ - - /* ---------------------------------------------------------------------------- -- PMU Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -82663,11 +32331,7 @@ typedef struct { __IO uint32_t REG_LPSR_1P0_SET; /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x234 */ __IO uint32_t REG_LPSR_1P0_CLR; /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x238 */ __IO uint32_t REG_LPSR_1P0_TOG; /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x23C */ - __IO uint32_t REG_3P0; /**< Anadig 3.0V USB Regulator Control Register, offset: 0x240 */ - __IO uint32_t REG_3P0_SET; /**< Anadig 3.0V USB Regulator Control Register, offset: 0x244 */ - __IO uint32_t REG_3P0_CLR; /**< Anadig 3.0V USB Regulator Control Register, offset: 0x248 */ - __IO uint32_t REG_3P0_TOG; /**< Anadig 3.0V USB Regulator Control Register, offset: 0x24C */ - uint8_t RESERVED_1[32]; + uint8_t RESERVED_1[48]; __IO uint32_t REF; /**< Anadig Reference Analog Control and Status Register, offset: 0x270 */ __IO uint32_t REF_SET; /**< Anadig Reference Analog Control and Status Register, offset: 0x274 */ __IO uint32_t REF_CLR; /**< Anadig Reference Analog Control and Status Register, offset: 0x278 */ @@ -82678,7 +32342,6 @@ typedef struct { __IO uint32_t LOWPWR_CTRL_CLR; /**< Anadig Low Power Control Register, offset: 0x338 */ __IO uint32_t LOWPWR_CTRL_TOG; /**< Anadig Low Power Control Register, offset: 0x33C */ } PMU_Type, *PMU_MemMapPtr; - /* ---------------------------------------------------------------------------- -- PMU - Register accessor macros ---------------------------------------------------------------------------- */ @@ -82706,10 +32369,6 @@ typedef struct { #define PMU_REG_LPSR_1P0_SET_REG(base) ((base)->REG_LPSR_1P0_SET) #define PMU_REG_LPSR_1P0_CLR_REG(base) ((base)->REG_LPSR_1P0_CLR) #define PMU_REG_LPSR_1P0_TOG_REG(base) ((base)->REG_LPSR_1P0_TOG) -#define PMU_REG_3P0_REG(base) ((base)->REG_3P0) -#define PMU_REG_3P0_SET_REG(base) ((base)->REG_3P0_SET) -#define PMU_REG_3P0_CLR_REG(base) ((base)->REG_3P0_CLR) -#define PMU_REG_3P0_TOG_REG(base) ((base)->REG_3P0_TOG) #define PMU_REF_REG(base) ((base)->REF) #define PMU_REF_SET_REG(base) ((base)->REF_SET) #define PMU_REF_CLR_REG(base) ((base)->REF_CLR) @@ -82722,8 +32381,6 @@ typedef struct { /*! * @} */ /* end of group PMU_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- PMU Register Masks ---------------------------------------------------------------------------- */ @@ -83293,126 +32950,6 @@ typedef struct { #define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u #define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24 #define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK) -/* REG_3P0 Bit Fields */ -#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u -#define PMU_REG_3P0_ENABLE_BO_SHIFT 1 -#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_3P0_RSVD0_MASK 0x8u -#define PMU_REG_3P0_RSVD0_SHIFT 3 -#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u -#define PMU_REG_3P0_BO_OFFSET_SHIFT 4 -#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK) -#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u -#define PMU_REG_3P0_VBUS_SEL_SHIFT 7 -#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_RSVD1_MASK 0xE000u -#define PMU_REG_3P0_RSVD1_SHIFT 13 -#define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK) -#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u -#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 -#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u -#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 -#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u -#define PMU_REG_3P0_REG_TEST_SHIFT 18 -#define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK) -#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u -#define PMU_REG_3P0_RSVD2_SHIFT 22 -#define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK) -/* REG_3P0_SET Bit Fields */ -#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u -#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1 -#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u -#define PMU_REG_3P0_SET_RSVD0_SHIFT 3 -#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u -#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4 -#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK) -#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u -#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7 -#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u -#define PMU_REG_3P0_SET_RSVD1_SHIFT 13 -#define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK) -#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u -#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16 -#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u -#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17 -#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u -#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18 -#define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK) -#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u -#define PMU_REG_3P0_SET_RSVD2_SHIFT 22 -#define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK) -/* REG_3P0_CLR Bit Fields */ -#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u -#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1 -#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u -#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3 -#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u -#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4 -#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK) -#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u -#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7 -#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u -#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13 -#define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK) -#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u -#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16 -#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u -#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17 -#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u -#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18 -#define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK) -#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u -#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22 -#define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK) -/* REG_3P0_TOG Bit Fields */ -#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u -#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0 -#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u -#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1 -#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u -#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2 -#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u -#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3 -#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u -#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4 -#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK) -#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u -#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7 -#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u -#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8 -#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) -#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u -#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13 -#define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK) -#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u -#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16 -#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u -#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17 -#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u -#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18 -#define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK) -#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u -#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22 -#define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK) /* REF Bit Fields */ #define PMU_REF_REFTOP_PWD_MASK 0x1u #define PMU_REF_REFTOP_PWD_SHIFT 0 @@ -83630,18 +33167,16 @@ typedef struct { * @} */ /* end of group PMU_Register_Masks */ - /* PMU - Peripheral instance base addresses */ /** Peripheral PMU base address */ #define PMU_BASE (0x30360000u) /** Peripheral PMU base pointer */ #define PMU ((PMU_Type *)PMU_BASE) #define PMU_BASE_PTR (PMU) -/** Array initializer of PMU peripheral base adresses */ +/** Array initializer of PMU peripheral base addresses */ #define PMU_BASE_ADDRS { PMU_BASE } /** Array initializer of PMU peripheral base pointers */ #define PMU_BASE_PTRS { PMU } - /* ---------------------------------------------------------------------------- -- PMU - Register accessor macros ---------------------------------------------------------------------------- */ @@ -83670,10 +33205,6 @@ typedef struct { #define PMU_REG_LPSR_1P0_SET PMU_REG_LPSR_1P0_SET_REG(PMU_BASE_PTR) #define PMU_REG_LPSR_1P0_CLR PMU_REG_LPSR_1P0_CLR_REG(PMU_BASE_PTR) #define PMU_REG_LPSR_1P0_TOG PMU_REG_LPSR_1P0_TOG_REG(PMU_BASE_PTR) -#define PMU_REG_3P0 PMU_REG_3P0_REG(PMU_BASE_PTR) -#define PMU_REG_3P0_SET PMU_REG_3P0_SET_REG(PMU_BASE_PTR) -#define PMU_REG_3P0_CLR PMU_REG_3P0_CLR_REG(PMU_BASE_PTR) -#define PMU_REG_3P0_TOG PMU_REG_3P0_TOG_REG(PMU_BASE_PTR) #define PMU_REF PMU_REF_REG(PMU_BASE_PTR) #define PMU_REF_SET PMU_REF_SET_REG(PMU_BASE_PTR) #define PMU_REF_CLR PMU_REF_CLR_REG(PMU_BASE_PTR) @@ -83682,7 +33213,6 @@ typedef struct { #define PMU_LOWPWR_CTRL_SET PMU_LOWPWR_CTRL_SET_REG(PMU_BASE_PTR) #define PMU_LOWPWR_CTRL_CLR PMU_LOWPWR_CTRL_CLR_REG(PMU_BASE_PTR) #define PMU_LOWPWR_CTRL_TOG PMU_LOWPWR_CTRL_TOG_REG(PMU_BASE_PTR) - /*! * @} */ /* end of group PMU_Register_Accessor_Macros */ @@ -83692,7 +33222,6 @@ typedef struct { * @} */ /* end of group PMU_Peripheral */ - /* ---------------------------------------------------------------------------- -- PWM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -83711,7 +33240,6 @@ typedef struct { __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ } PWM_Type, *PWM_MemMapPtr; - /* ---------------------------------------------------------------------------- -- PWM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -83733,8 +33261,6 @@ typedef struct { /*! * @} */ /* end of group PWM_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- PWM Register Masks ---------------------------------------------------------------------------- */ @@ -83812,7 +33338,6 @@ typedef struct { * @} */ /* end of group PWM_Register_Masks */ - /* PWM - Peripheral instance base addresses */ /** Peripheral PWM1 base address */ #define PWM1_BASE (0x30660000u) @@ -83834,11 +33359,12 @@ typedef struct { /** Peripheral PWM4 base pointer */ #define PWM4 ((PWM_Type *)PWM4_BASE) #define PWM4_BASE_PTR (PWM4) -/** Array initializer of PWM peripheral base adresses */ +/** Array initializer of PWM peripheral base addresses */ #define PWM_BASE_ADDRS { PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } /** Array initializer of PWM peripheral base pointers */ #define PWM_BASE_PTRS { PWM1, PWM2, PWM3, PWM4 } - +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_IRQS { PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn } /* ---------------------------------------------------------------------------- -- PWM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -83878,7 +33404,6 @@ typedef struct { #define PWM4_PWMSAR PWM_PWMSAR_REG(PWM4_BASE_PTR) #define PWM4_PWMPR PWM_PWMPR_REG(PWM4_BASE_PTR) #define PWM4_PWMCNR PWM_PWMCNR_REG(PWM4_BASE_PTR) - /*! * @} */ /* end of group PWM_Register_Accessor_Macros */ @@ -83888,7 +33413,6 @@ typedef struct { * @} */ /* end of group PWM_Peripheral */ - /* ---------------------------------------------------------------------------- -- PXP Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -83900,87 +33424,87 @@ typedef struct { /** PXP - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t HW_PXP_CTRL; /**< Control Register 0, offset: 0x0 */ uint8_t RESERVED_0[12]; - __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + __IO uint32_t HW_PXP_STAT; /**< Status Register, offset: 0x10 */ uint8_t RESERVED_1[12]; - __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + __IO uint32_t HW_PXP_OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ uint8_t RESERVED_2[12]; - __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + __IO uint32_t HW_PXP_OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ uint8_t RESERVED_3[12]; - __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + __IO uint32_t HW_PXP_OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ uint8_t RESERVED_4[12]; - __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + __IO uint32_t HW_PXP_OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ uint8_t RESERVED_5[12]; - __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + __IO uint32_t HW_PXP_OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ uint8_t RESERVED_6[12]; - __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + __IO uint32_t HW_PXP_OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ uint8_t RESERVED_7[12]; - __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + __IO uint32_t HW_PXP_OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ uint8_t RESERVED_8[12]; - __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + __IO uint32_t HW_PXP_OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ uint8_t RESERVED_9[12]; - __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + __IO uint32_t HW_PXP_OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ uint8_t RESERVED_10[12]; - __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + __IO uint32_t HW_PXP_PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ uint8_t RESERVED_11[12]; - __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + __IO uint32_t HW_PXP_PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ uint8_t RESERVED_12[12]; - __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + __IO uint32_t HW_PXP_PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ uint8_t RESERVED_13[12]; - __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + __IO uint32_t HW_PXP_PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ uint8_t RESERVED_14[12]; - __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + __IO uint32_t HW_PXP_PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ uint8_t RESERVED_15[12]; __IO uint32_t HW_PXP_PS_BACKGROUND_0; /**< PS Background Color, offset: 0x100 */ uint8_t RESERVED_16[12]; - __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + __IO uint32_t HW_PXP_PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ uint8_t RESERVED_17[12]; - __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + __IO uint32_t HW_PXP_PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ uint8_t RESERVED_18[12]; __IO uint32_t HW_PXP_PS_CLRKEYLOW_0; /**< PS Color Key Low, offset: 0x130 */ uint8_t RESERVED_19[12]; __IO uint32_t HW_PXP_PS_CLRKEYHIGH_0; /**< PS Color Key High, offset: 0x140 */ uint8_t RESERVED_20[12]; - __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + __IO uint32_t HW_PXP_AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ uint8_t RESERVED_21[12]; - __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + __IO uint32_t HW_PXP_AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ uint8_t RESERVED_22[12]; - __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + __IO uint32_t HW_PXP_AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ uint8_t RESERVED_23[12]; __IO uint32_t HW_PXP_AS_CLRKEYLOW_0; /**< Overlay Color Key Low, offset: 0x180 */ uint8_t RESERVED_24[12]; __IO uint32_t HW_PXP_AS_CLRKEYHIGH_0; /**< Overlay Color Key High, offset: 0x190 */ uint8_t RESERVED_25[12]; - __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + __IO uint32_t HW_PXP_CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ uint8_t RESERVED_26[12]; - __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + __IO uint32_t HW_PXP_CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ uint8_t RESERVED_27[12]; - __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + __IO uint32_t HW_PXP_CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ uint8_t RESERVED_28[12]; - __IO uint32_t CSC2_CTRL; /**< Color Space Conversion Control Register., offset: 0x1D0 */ + __IO uint32_t HW_PXP_CSC2_CTRL; /**< Color Space Conversion Control Register., offset: 0x1D0 */ uint8_t RESERVED_29[12]; - __IO uint32_t CSC2_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */ + __IO uint32_t HW_PXP_CSC2_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */ uint8_t RESERVED_30[12]; - __IO uint32_t CSC2_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */ + __IO uint32_t HW_PXP_CSC2_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */ uint8_t RESERVED_31[12]; - __IO uint32_t CSC2_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */ + __IO uint32_t HW_PXP_CSC2_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */ uint8_t RESERVED_32[12]; - __IO uint32_t CSC2_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */ + __IO uint32_t HW_PXP_CSC2_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */ uint8_t RESERVED_33[12]; - __IO uint32_t CSC2_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */ + __IO uint32_t HW_PXP_CSC2_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */ uint8_t RESERVED_34[12]; - __IO uint32_t CSC2_COEF5; /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */ + __IO uint32_t HW_PXP_CSC2_COEF5; /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */ uint8_t RESERVED_35[12]; - __IO uint32_t LUT_CTRL; /**< Lookup Table Control Register., offset: 0x240 */ + __IO uint32_t HW_PXP_LUT_CTRL; /**< Lookup Table Control Register., offset: 0x240 */ uint8_t RESERVED_36[12]; - __IO uint32_t LUT_ADDR; /**< Lookup Table Control Register., offset: 0x250 */ + __IO uint32_t HW_PXP_LUT_ADDR; /**< Lookup Table Control Register., offset: 0x250 */ uint8_t RESERVED_37[12]; - __IO uint32_t LUT_DATA; /**< Lookup Table Data Register., offset: 0x260 */ + __IO uint32_t HW_PXP_LUT_DATA; /**< Lookup Table Data Register., offset: 0x260 */ uint8_t RESERVED_38[12]; - __IO uint32_t LUT_EXTMEM; /**< Lookup Table External Memory Address Register., offset: 0x270 */ + __IO uint32_t HW_PXP_LUT_EXTMEM; /**< Lookup Table External Memory Address Register., offset: 0x270 */ uint8_t RESERVED_39[12]; - __IO uint32_t CFA; /**< Color Filter Array Register., offset: 0x280 */ + __IO uint32_t HW_PXP_CFA; /**< Color Filter Array Register., offset: 0x280 */ uint8_t RESERVED_40[12]; __IO uint32_t HW_PXP_ALPHA_A_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x290 */ uint8_t RESERVED_41[12]; @@ -84018,7 +33542,7 @@ typedef struct { uint8_t RESERVED_57[12]; __IO uint32_t HW_PXP_IRQ; /**< PXP Interrupt Register, offset: 0x3A0 */ uint8_t RESERVED_58[92]; - __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + __IO uint32_t HW_PXP_NEXT; /**< Next Frame Pointer, offset: 0x400 */ uint8_t RESERVED_59[76]; __IO uint32_t HW_PXP_INPUT_FETCH_CTRL_CH0; /**< Pre-fetch engine Control Channel 0 Register, offset: 0x450 */ uint8_t RESERVED_60[12]; @@ -84298,21 +33822,21 @@ typedef struct { uint8_t RESERVED_197[12]; __IO uint32_t HW_PXP_HIST_B_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AF0 */ uint8_t RESERVED_198[12]; - __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x2B00 */ + __IO uint32_t HW_PXP_HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x2B00 */ uint8_t RESERVED_199[12]; - __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x2B10 */ + __IO uint32_t HW_PXP_HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x2B10 */ uint8_t RESERVED_200[12]; - __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */ + __IO uint32_t HW_PXP_HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */ uint8_t RESERVED_201[12]; - __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */ + __IO uint32_t HW_PXP_HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */ uint8_t RESERVED_202[12]; - __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */ + __IO uint32_t HW_PXP_HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */ uint8_t RESERVED_203[12]; - __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */ + __IO uint32_t HW_PXP_HIST16_PARAM1; /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */ uint8_t RESERVED_204[12]; - __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */ + __IO uint32_t HW_PXP_HIST16_PARAM2; /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */ uint8_t RESERVED_205[12]; - __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */ + __IO uint32_t HW_PXP_HIST16_PARAM3; /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */ uint8_t RESERVED_206[12]; __IO uint32_t HW_PXP_HIST32_PARAM0; /**< 32-level Histogram Parameter 0 Register., offset: 0x2B80 */ uint8_t RESERVED_207[12]; @@ -84372,7 +33896,6 @@ typedef struct { uint8_t RESERVED_234[12]; __IO uint32_t HW_PXP_HANDSHAKE_CPU_STORE; /**< , offset: 0x2D40 */ } PXP_Type, *PXP_MemMapPtr; - /* ---------------------------------------------------------------------------- -- PXP - Register accessor macros ---------------------------------------------------------------------------- */ @@ -84384,47 +33907,47 @@ typedef struct { /* PXP - Register accessors */ -#define PXP_CTRL_REG(base) ((base)->CTRL) -#define PXP_STAT_REG(base) ((base)->STAT) -#define PXP_OUT_CTRL_REG(base) ((base)->OUT_CTRL) -#define PXP_OUT_BUF_REG(base) ((base)->OUT_BUF) -#define PXP_OUT_BUF2_REG(base) ((base)->OUT_BUF2) -#define PXP_OUT_PITCH_REG(base) ((base)->OUT_PITCH) -#define PXP_OUT_LRC_REG(base) ((base)->OUT_LRC) -#define PXP_OUT_PS_ULC_REG(base) ((base)->OUT_PS_ULC) -#define PXP_OUT_PS_LRC_REG(base) ((base)->OUT_PS_LRC) -#define PXP_OUT_AS_ULC_REG(base) ((base)->OUT_AS_ULC) -#define PXP_OUT_AS_LRC_REG(base) ((base)->OUT_AS_LRC) -#define PXP_PS_CTRL_REG(base) ((base)->PS_CTRL) -#define PXP_PS_BUF_REG(base) ((base)->PS_BUF) -#define PXP_PS_UBUF_REG(base) ((base)->PS_UBUF) -#define PXP_PS_VBUF_REG(base) ((base)->PS_VBUF) -#define PXP_PS_PITCH_REG(base) ((base)->PS_PITCH) +#define PXP_HW_PXP_CTRL_REG(base) ((base)->HW_PXP_CTRL) +#define PXP_HW_PXP_STAT_REG(base) ((base)->HW_PXP_STAT) +#define PXP_HW_PXP_OUT_CTRL_REG(base) ((base)->HW_PXP_OUT_CTRL) +#define PXP_HW_PXP_OUT_BUF_REG(base) ((base)->HW_PXP_OUT_BUF) +#define PXP_HW_PXP_OUT_BUF2_REG(base) ((base)->HW_PXP_OUT_BUF2) +#define PXP_HW_PXP_OUT_PITCH_REG(base) ((base)->HW_PXP_OUT_PITCH) +#define PXP_HW_PXP_OUT_LRC_REG(base) ((base)->HW_PXP_OUT_LRC) +#define PXP_HW_PXP_OUT_PS_ULC_REG(base) ((base)->HW_PXP_OUT_PS_ULC) +#define PXP_HW_PXP_OUT_PS_LRC_REG(base) ((base)->HW_PXP_OUT_PS_LRC) +#define PXP_HW_PXP_OUT_AS_ULC_REG(base) ((base)->HW_PXP_OUT_AS_ULC) +#define PXP_HW_PXP_OUT_AS_LRC_REG(base) ((base)->HW_PXP_OUT_AS_LRC) +#define PXP_HW_PXP_PS_CTRL_REG(base) ((base)->HW_PXP_PS_CTRL) +#define PXP_HW_PXP_PS_BUF_REG(base) ((base)->HW_PXP_PS_BUF) +#define PXP_HW_PXP_PS_UBUF_REG(base) ((base)->HW_PXP_PS_UBUF) +#define PXP_HW_PXP_PS_VBUF_REG(base) ((base)->HW_PXP_PS_VBUF) +#define PXP_HW_PXP_PS_PITCH_REG(base) ((base)->HW_PXP_PS_PITCH) #define PXP_HW_PXP_PS_BACKGROUND_0_REG(base) ((base)->HW_PXP_PS_BACKGROUND_0) -#define PXP_PS_SCALE_REG(base) ((base)->PS_SCALE) -#define PXP_PS_OFFSET_REG(base) ((base)->PS_OFFSET) +#define PXP_HW_PXP_PS_SCALE_REG(base) ((base)->HW_PXP_PS_SCALE) +#define PXP_HW_PXP_PS_OFFSET_REG(base) ((base)->HW_PXP_PS_OFFSET) #define PXP_HW_PXP_PS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_0) #define PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_0) -#define PXP_AS_CTRL_REG(base) ((base)->AS_CTRL) -#define PXP_AS_BUF_REG(base) ((base)->AS_BUF) -#define PXP_AS_PITCH_REG(base) ((base)->AS_PITCH) +#define PXP_HW_PXP_AS_CTRL_REG(base) ((base)->HW_PXP_AS_CTRL) +#define PXP_HW_PXP_AS_BUF_REG(base) ((base)->HW_PXP_AS_BUF) +#define PXP_HW_PXP_AS_PITCH_REG(base) ((base)->HW_PXP_AS_PITCH) #define PXP_HW_PXP_AS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_0) #define PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_0) -#define PXP_CSC1_COEF0_REG(base) ((base)->CSC1_COEF0) -#define PXP_CSC1_COEF1_REG(base) ((base)->CSC1_COEF1) -#define PXP_CSC1_COEF2_REG(base) ((base)->CSC1_COEF2) -#define PXP_CSC2_CTRL_REG(base) ((base)->CSC2_CTRL) -#define PXP_CSC2_COEF0_REG(base) ((base)->CSC2_COEF0) -#define PXP_CSC2_COEF1_REG(base) ((base)->CSC2_COEF1) -#define PXP_CSC2_COEF2_REG(base) ((base)->CSC2_COEF2) -#define PXP_CSC2_COEF3_REG(base) ((base)->CSC2_COEF3) -#define PXP_CSC2_COEF4_REG(base) ((base)->CSC2_COEF4) -#define PXP_CSC2_COEF5_REG(base) ((base)->CSC2_COEF5) -#define PXP_LUT_CTRL_REG(base) ((base)->LUT_CTRL) -#define PXP_LUT_ADDR_REG(base) ((base)->LUT_ADDR) -#define PXP_LUT_DATA_REG(base) ((base)->LUT_DATA) -#define PXP_LUT_EXTMEM_REG(base) ((base)->LUT_EXTMEM) -#define PXP_CFA_REG(base) ((base)->CFA) +#define PXP_HW_PXP_CSC1_COEF0_REG(base) ((base)->HW_PXP_CSC1_COEF0) +#define PXP_HW_PXP_CSC1_COEF1_REG(base) ((base)->HW_PXP_CSC1_COEF1) +#define PXP_HW_PXP_CSC1_COEF2_REG(base) ((base)->HW_PXP_CSC1_COEF2) +#define PXP_HW_PXP_CSC2_CTRL_REG(base) ((base)->HW_PXP_CSC2_CTRL) +#define PXP_HW_PXP_CSC2_COEF0_REG(base) ((base)->HW_PXP_CSC2_COEF0) +#define PXP_HW_PXP_CSC2_COEF1_REG(base) ((base)->HW_PXP_CSC2_COEF1) +#define PXP_HW_PXP_CSC2_COEF2_REG(base) ((base)->HW_PXP_CSC2_COEF2) +#define PXP_HW_PXP_CSC2_COEF3_REG(base) ((base)->HW_PXP_CSC2_COEF3) +#define PXP_HW_PXP_CSC2_COEF4_REG(base) ((base)->HW_PXP_CSC2_COEF4) +#define PXP_HW_PXP_CSC2_COEF5_REG(base) ((base)->HW_PXP_CSC2_COEF5) +#define PXP_HW_PXP_LUT_CTRL_REG(base) ((base)->HW_PXP_LUT_CTRL) +#define PXP_HW_PXP_LUT_ADDR_REG(base) ((base)->HW_PXP_LUT_ADDR) +#define PXP_HW_PXP_LUT_DATA_REG(base) ((base)->HW_PXP_LUT_DATA) +#define PXP_HW_PXP_LUT_EXTMEM_REG(base) ((base)->HW_PXP_LUT_EXTMEM) +#define PXP_HW_PXP_CFA_REG(base) ((base)->HW_PXP_CFA) #define PXP_HW_PXP_ALPHA_A_CTRL_REG(base) ((base)->HW_PXP_ALPHA_A_CTRL) #define PXP_HW_PXP_ALPHA_B_CTRL_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL) #define PXP_HW_PXP_ALPHA_B_CTRL_1_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL_1) @@ -84443,7 +33966,7 @@ typedef struct { #define PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(base) ((base)->HW_PXP_INIT_MEM_DATA_HIGH) #define PXP_HW_PXP_IRQ_MASK_REG(base) ((base)->HW_PXP_IRQ_MASK) #define PXP_HW_PXP_IRQ_REG(base) ((base)->HW_PXP_IRQ) -#define PXP_NEXT_REG(base) ((base)->NEXT) +#define PXP_HW_PXP_NEXT_REG(base) ((base)->HW_PXP_NEXT) #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH0) #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH1) #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH0) @@ -84583,14 +34106,14 @@ typedef struct { #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_Y) #define PXP_HW_PXP_HIST_B_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT0) #define PXP_HW_PXP_HIST_B_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT1) -#define PXP_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) -#define PXP_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) -#define PXP_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) -#define PXP_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) -#define PXP_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) -#define PXP_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) -#define PXP_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) -#define PXP_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) +#define PXP_HW_PXP_HIST2_PARAM_REG(base) ((base)->HW_PXP_HIST2_PARAM) +#define PXP_HW_PXP_HIST4_PARAM_REG(base) ((base)->HW_PXP_HIST4_PARAM) +#define PXP_HW_PXP_HIST8_PARAM0_REG(base) ((base)->HW_PXP_HIST8_PARAM0) +#define PXP_HW_PXP_HIST8_PARAM1_REG(base) ((base)->HW_PXP_HIST8_PARAM1) +#define PXP_HW_PXP_HIST16_PARAM0_REG(base) ((base)->HW_PXP_HIST16_PARAM0) +#define PXP_HW_PXP_HIST16_PARAM1_REG(base) ((base)->HW_PXP_HIST16_PARAM1) +#define PXP_HW_PXP_HIST16_PARAM2_REG(base) ((base)->HW_PXP_HIST16_PARAM2) +#define PXP_HW_PXP_HIST16_PARAM3_REG(base) ((base)->HW_PXP_HIST16_PARAM3) #define PXP_HW_PXP_HIST32_PARAM0_REG(base) ((base)->HW_PXP_HIST32_PARAM0) #define PXP_HW_PXP_HIST32_PARAM1_REG(base) ((base)->HW_PXP_HIST32_PARAM1) #define PXP_HW_PXP_HIST32_PARAM2_REG(base) ((base)->HW_PXP_HIST32_PARAM2) @@ -84624,8 +34147,6 @@ typedef struct { /*! * @} */ /* end of group PXP_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- PXP Register Masks ---------------------------------------------------------------------------- */ @@ -84635,231 +34156,231 @@ typedef struct { * @{ */ -/* CTRL Bit Fields */ -#define PXP_CTRL_ENABLE_MASK 0x1u -#define PXP_CTRL_ENABLE_SHIFT 0 -#define PXP_CTRL_IRQ_ENABLE_MASK 0x2u -#define PXP_CTRL_IRQ_ENABLE_SHIFT 1 -#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u -#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 -#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u -#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 -#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK 0x10u -#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT 4 -#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK 0x20u -#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT 5 -#define PXP_CTRL_RSVD0_MASK 0xC0u -#define PXP_CTRL_RSVD0_SHIFT 6 -#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_RSVD0_SHIFT))&PXP_CTRL_RSVD0_MASK) -#define PXP_CTRL_ROTATE0_MASK 0x300u -#define PXP_CTRL_ROTATE0_SHIFT 8 -#define PXP_CTRL_ROTATE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_ROTATE0_SHIFT))&PXP_CTRL_ROTATE0_MASK) -#define PXP_CTRL_HFLIP0_MASK 0x400u -#define PXP_CTRL_HFLIP0_SHIFT 10 -#define PXP_CTRL_VFLIP0_MASK 0x800u -#define PXP_CTRL_VFLIP0_SHIFT 11 -#define PXP_CTRL_ROTATE1_MASK 0x3000u -#define PXP_CTRL_ROTATE1_SHIFT 12 -#define PXP_CTRL_ROTATE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_ROTATE1_SHIFT))&PXP_CTRL_ROTATE1_MASK) -#define PXP_CTRL_HFLIP1_MASK 0x4000u -#define PXP_CTRL_HFLIP1_SHIFT 14 -#define PXP_CTRL_VFLIP1_MASK 0x8000u -#define PXP_CTRL_VFLIP1_SHIFT 15 -#define PXP_CTRL_ENABLE_PS_AS_OUT_MASK 0x10000u -#define PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT 16 -#define PXP_CTRL_ENABLE_DITHER_MASK 0x20000u -#define PXP_CTRL_ENABLE_DITHER_SHIFT 17 -#define PXP_CTRL_ENABLE_WFE_A_MASK 0x40000u -#define PXP_CTRL_ENABLE_WFE_A_SHIFT 18 -#define PXP_CTRL_ENABLE_WFE_B_MASK 0x80000u -#define PXP_CTRL_ENABLE_WFE_B_SHIFT 19 -#define PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK 0x100000u -#define PXP_CTRL_ENABLE_INPUT_FETCH_STORE_SHIFT 20 -#define PXP_CTRL_ENABLE_ALPHA_B_MASK 0x200000u -#define PXP_CTRL_ENABLE_ALPHA_B_SHIFT 21 -#define PXP_CTRL_RSVD1_MASK 0x400000u -#define PXP_CTRL_RSVD1_SHIFT 22 -#define PXP_CTRL_BLOCK_SIZE_MASK 0x800000u -#define PXP_CTRL_BLOCK_SIZE_SHIFT 23 -#define PXP_CTRL_ENABLE_CSC2_MASK 0x1000000u -#define PXP_CTRL_ENABLE_CSC2_SHIFT 24 -#define PXP_CTRL_ENABLE_LUT_MASK 0x2000000u -#define PXP_CTRL_ENABLE_LUT_SHIFT 25 -#define PXP_CTRL_ENABLE_ROTATE0_MASK 0x4000000u -#define PXP_CTRL_ENABLE_ROTATE0_SHIFT 26 -#define PXP_CTRL_ENABLE_ROTATE1_MASK 0x8000000u -#define PXP_CTRL_ENABLE_ROTATE1_SHIFT 27 -#define PXP_CTRL_EN_REPEAT_MASK 0x10000000u -#define PXP_CTRL_EN_REPEAT_SHIFT 28 -#define PXP_CTRL_RSVD4_MASK 0x20000000u -#define PXP_CTRL_RSVD4_SHIFT 29 -#define PXP_CTRL_CLKGATE_MASK 0x40000000u -#define PXP_CTRL_CLKGATE_SHIFT 30 -#define PXP_CTRL_SFTRST_MASK 0x80000000u -#define PXP_CTRL_SFTRST_SHIFT 31 -/* STAT Bit Fields */ -#define PXP_STAT_IRQ0_MASK 0x1u -#define PXP_STAT_IRQ0_SHIFT 0 -#define PXP_STAT_AXI_WRITE_ERROR_0_MASK 0x2u -#define PXP_STAT_AXI_WRITE_ERROR_0_SHIFT 1 -#define PXP_STAT_AXI_READ_ERROR_0_MASK 0x4u -#define PXP_STAT_AXI_READ_ERROR_0_SHIFT 2 -#define PXP_STAT_NEXT_IRQ_MASK 0x8u -#define PXP_STAT_NEXT_IRQ_SHIFT 3 -#define PXP_STAT_AXI_ERROR_ID_0_MASK 0xF0u -#define PXP_STAT_AXI_ERROR_ID_0_SHIFT 4 -#define PXP_STAT_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_AXI_ERROR_ID_0_SHIFT))&PXP_STAT_AXI_ERROR_ID_0_MASK) -#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK 0x100u -#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT 8 -#define PXP_STAT_AXI_WRITE_ERROR_1_MASK 0x200u -#define PXP_STAT_AXI_WRITE_ERROR_1_SHIFT 9 -#define PXP_STAT_AXI_READ_ERROR_1_MASK 0x400u -#define PXP_STAT_AXI_READ_ERROR_1_SHIFT 10 -#define PXP_STAT_RSVD2_MASK 0x800u -#define PXP_STAT_RSVD2_SHIFT 11 -#define PXP_STAT_AXI_ERROR_ID_1_MASK 0xF000u -#define PXP_STAT_AXI_ERROR_ID_1_SHIFT 12 -#define PXP_STAT_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_AXI_ERROR_ID_1_SHIFT))&PXP_STAT_AXI_ERROR_ID_1_MASK) -#define PXP_STAT_BLOCKY_MASK 0xFF0000u -#define PXP_STAT_BLOCKY_SHIFT 16 -#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_BLOCKY_SHIFT))&PXP_STAT_BLOCKY_MASK) -#define PXP_STAT_BLOCKX_MASK 0xFF000000u -#define PXP_STAT_BLOCKX_SHIFT 24 -#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_BLOCKX_SHIFT))&PXP_STAT_BLOCKX_MASK) -/* OUT_CTRL Bit Fields */ -#define PXP_OUT_CTRL_FORMAT_MASK 0x1Fu -#define PXP_OUT_CTRL_FORMAT_SHIFT 0 -#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_FORMAT_SHIFT))&PXP_OUT_CTRL_FORMAT_MASK) -#define PXP_OUT_CTRL_RSVD0_MASK 0xE0u -#define PXP_OUT_CTRL_RSVD0_SHIFT 5 -#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_RSVD0_SHIFT))&PXP_OUT_CTRL_RSVD0_MASK) -#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK 0x300u -#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT 8 -#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT))&PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_RSVD1_MASK 0x7FFC00u -#define PXP_OUT_CTRL_RSVD1_SHIFT 10 -#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_RSVD1_SHIFT))&PXP_OUT_CTRL_RSVD1_MASK) -#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK 0x800000u -#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT 23 -#define PXP_OUT_CTRL_ALPHA_MASK 0xFF000000u -#define PXP_OUT_CTRL_ALPHA_SHIFT 24 -#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_ALPHA_SHIFT))&PXP_OUT_CTRL_ALPHA_MASK) -/* OUT_BUF Bit Fields */ -#define PXP_OUT_BUF_ADDR_MASK 0xFFFFFFFFu -#define PXP_OUT_BUF_ADDR_SHIFT 0 -#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_BUF_ADDR_SHIFT))&PXP_OUT_BUF_ADDR_MASK) -/* OUT_BUF2 Bit Fields */ -#define PXP_OUT_BUF2_ADDR_MASK 0xFFFFFFFFu -#define PXP_OUT_BUF2_ADDR_SHIFT 0 -#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_BUF2_ADDR_SHIFT))&PXP_OUT_BUF2_ADDR_MASK) -/* OUT_PITCH Bit Fields */ -#define PXP_OUT_PITCH_PITCH_MASK 0xFFFFu -#define PXP_OUT_PITCH_PITCH_SHIFT 0 -#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PITCH_PITCH_SHIFT))&PXP_OUT_PITCH_PITCH_MASK) -#define PXP_OUT_PITCH_RSVD_MASK 0xFFFF0000u -#define PXP_OUT_PITCH_RSVD_SHIFT 16 -#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PITCH_RSVD_SHIFT))&PXP_OUT_PITCH_RSVD_MASK) -/* OUT_LRC Bit Fields */ -#define PXP_OUT_LRC_Y_MASK 0x3FFFu -#define PXP_OUT_LRC_Y_SHIFT 0 -#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_Y_SHIFT))&PXP_OUT_LRC_Y_MASK) -#define PXP_OUT_LRC_RSVD0_MASK 0xC000u -#define PXP_OUT_LRC_RSVD0_SHIFT 14 -#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_RSVD0_SHIFT))&PXP_OUT_LRC_RSVD0_MASK) -#define PXP_OUT_LRC_X_MASK 0x3FFF0000u -#define PXP_OUT_LRC_X_SHIFT 16 -#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_X_SHIFT))&PXP_OUT_LRC_X_MASK) -#define PXP_OUT_LRC_RSVD1_MASK 0xC0000000u -#define PXP_OUT_LRC_RSVD1_SHIFT 30 -#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_RSVD1_SHIFT))&PXP_OUT_LRC_RSVD1_MASK) -/* OUT_PS_ULC Bit Fields */ -#define PXP_OUT_PS_ULC_Y_MASK 0x3FFFu -#define PXP_OUT_PS_ULC_Y_SHIFT 0 -#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_Y_SHIFT))&PXP_OUT_PS_ULC_Y_MASK) -#define PXP_OUT_PS_ULC_RSVD0_MASK 0xC000u -#define PXP_OUT_PS_ULC_RSVD0_SHIFT 14 -#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_RSVD0_SHIFT))&PXP_OUT_PS_ULC_RSVD0_MASK) -#define PXP_OUT_PS_ULC_X_MASK 0x3FFF0000u -#define PXP_OUT_PS_ULC_X_SHIFT 16 -#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_X_SHIFT))&PXP_OUT_PS_ULC_X_MASK) -#define PXP_OUT_PS_ULC_RSVD1_MASK 0xC0000000u -#define PXP_OUT_PS_ULC_RSVD1_SHIFT 30 -#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_RSVD1_SHIFT))&PXP_OUT_PS_ULC_RSVD1_MASK) -/* OUT_PS_LRC Bit Fields */ -#define PXP_OUT_PS_LRC_Y_MASK 0x3FFFu -#define PXP_OUT_PS_LRC_Y_SHIFT 0 -#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_Y_SHIFT))&PXP_OUT_PS_LRC_Y_MASK) -#define PXP_OUT_PS_LRC_RSVD0_MASK 0xC000u -#define PXP_OUT_PS_LRC_RSVD0_SHIFT 14 -#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_RSVD0_SHIFT))&PXP_OUT_PS_LRC_RSVD0_MASK) -#define PXP_OUT_PS_LRC_X_MASK 0x3FFF0000u -#define PXP_OUT_PS_LRC_X_SHIFT 16 -#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_X_SHIFT))&PXP_OUT_PS_LRC_X_MASK) -#define PXP_OUT_PS_LRC_RSVD1_MASK 0xC0000000u -#define PXP_OUT_PS_LRC_RSVD1_SHIFT 30 -#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_RSVD1_SHIFT))&PXP_OUT_PS_LRC_RSVD1_MASK) -/* OUT_AS_ULC Bit Fields */ -#define PXP_OUT_AS_ULC_Y_MASK 0x3FFFu -#define PXP_OUT_AS_ULC_Y_SHIFT 0 -#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_Y_SHIFT))&PXP_OUT_AS_ULC_Y_MASK) -#define PXP_OUT_AS_ULC_RSVD0_MASK 0xC000u -#define PXP_OUT_AS_ULC_RSVD0_SHIFT 14 -#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_RSVD0_SHIFT))&PXP_OUT_AS_ULC_RSVD0_MASK) -#define PXP_OUT_AS_ULC_X_MASK 0x3FFF0000u -#define PXP_OUT_AS_ULC_X_SHIFT 16 -#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_X_SHIFT))&PXP_OUT_AS_ULC_X_MASK) -#define PXP_OUT_AS_ULC_RSVD1_MASK 0xC0000000u -#define PXP_OUT_AS_ULC_RSVD1_SHIFT 30 -#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_RSVD1_SHIFT))&PXP_OUT_AS_ULC_RSVD1_MASK) -/* OUT_AS_LRC Bit Fields */ -#define PXP_OUT_AS_LRC_Y_MASK 0x3FFFu -#define PXP_OUT_AS_LRC_Y_SHIFT 0 -#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_Y_SHIFT))&PXP_OUT_AS_LRC_Y_MASK) -#define PXP_OUT_AS_LRC_RSVD0_MASK 0xC000u -#define PXP_OUT_AS_LRC_RSVD0_SHIFT 14 -#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_RSVD0_SHIFT))&PXP_OUT_AS_LRC_RSVD0_MASK) -#define PXP_OUT_AS_LRC_X_MASK 0x3FFF0000u -#define PXP_OUT_AS_LRC_X_SHIFT 16 -#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_X_SHIFT))&PXP_OUT_AS_LRC_X_MASK) -#define PXP_OUT_AS_LRC_RSVD1_MASK 0xC0000000u -#define PXP_OUT_AS_LRC_RSVD1_SHIFT 30 -#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_RSVD1_SHIFT))&PXP_OUT_AS_LRC_RSVD1_MASK) -/* PS_CTRL Bit Fields */ -#define PXP_PS_CTRL_FORMAT_MASK 0x3Fu -#define PXP_PS_CTRL_FORMAT_SHIFT 0 -#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_FORMAT_SHIFT))&PXP_PS_CTRL_FORMAT_MASK) -#define PXP_PS_CTRL_WB_SWAP_MASK 0x40u -#define PXP_PS_CTRL_WB_SWAP_SHIFT 6 -#define PXP_PS_CTRL_RSVD0_MASK 0x80u -#define PXP_PS_CTRL_RSVD0_SHIFT 7 -#define PXP_PS_CTRL_DECY_MASK 0x300u -#define PXP_PS_CTRL_DECY_SHIFT 8 -#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_DECY_SHIFT))&PXP_PS_CTRL_DECY_MASK) -#define PXP_PS_CTRL_DECX_MASK 0xC00u -#define PXP_PS_CTRL_DECX_SHIFT 10 -#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_DECX_SHIFT))&PXP_PS_CTRL_DECX_MASK) -#define PXP_PS_CTRL_RSVD1_MASK 0xFFFFF000u -#define PXP_PS_CTRL_RSVD1_SHIFT 12 -#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_RSVD1_SHIFT))&PXP_PS_CTRL_RSVD1_MASK) -/* PS_BUF Bit Fields */ -#define PXP_PS_BUF_ADDR_MASK 0xFFFFFFFFu -#define PXP_PS_BUF_ADDR_SHIFT 0 -#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_BUF_ADDR_SHIFT))&PXP_PS_BUF_ADDR_MASK) -/* PS_UBUF Bit Fields */ -#define PXP_PS_UBUF_ADDR_MASK 0xFFFFFFFFu -#define PXP_PS_UBUF_ADDR_SHIFT 0 -#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_UBUF_ADDR_SHIFT))&PXP_PS_UBUF_ADDR_MASK) -/* PS_VBUF Bit Fields */ -#define PXP_PS_VBUF_ADDR_MASK 0xFFFFFFFFu -#define PXP_PS_VBUF_ADDR_SHIFT 0 -#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_VBUF_ADDR_SHIFT))&PXP_PS_VBUF_ADDR_MASK) -/* PS_PITCH Bit Fields */ -#define PXP_PS_PITCH_PITCH_MASK 0xFFFFu -#define PXP_PS_PITCH_PITCH_SHIFT 0 -#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_PITCH_PITCH_SHIFT))&PXP_PS_PITCH_PITCH_MASK) -#define PXP_PS_PITCH_RSVD_MASK 0xFFFF0000u -#define PXP_PS_PITCH_RSVD_SHIFT 16 -#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_PITCH_RSVD_SHIFT))&PXP_PS_PITCH_RSVD_MASK) +/* HW_PXP_CTRL Bit Fields */ +#define PXP_HW_PXP_CTRL_ENABLE_MASK 0x1u +#define PXP_HW_PXP_CTRL_ENABLE_SHIFT 0 +#define PXP_HW_PXP_CTRL_IRQ_ENABLE_MASK 0x2u +#define PXP_HW_PXP_CTRL_IRQ_ENABLE_SHIFT 1 +#define PXP_HW_PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u +#define PXP_HW_PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 +#define PXP_HW_PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u +#define PXP_HW_PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 +#define PXP_HW_PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK 0x10u +#define PXP_HW_PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT 4 +#define PXP_HW_PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK 0x20u +#define PXP_HW_PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT 5 +#define PXP_HW_PXP_CTRL_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_CTRL_RSVD0_SHIFT 6 +#define PXP_HW_PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_CTRL_ROTATE0_MASK 0x300u +#define PXP_HW_PXP_CTRL_ROTATE0_SHIFT 8 +#define PXP_HW_PXP_CTRL_ROTATE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL_ROTATE0_SHIFT))&PXP_HW_PXP_CTRL_ROTATE0_MASK) +#define PXP_HW_PXP_CTRL_HFLIP0_MASK 0x400u +#define PXP_HW_PXP_CTRL_HFLIP0_SHIFT 10 +#define PXP_HW_PXP_CTRL_VFLIP0_MASK 0x800u +#define PXP_HW_PXP_CTRL_VFLIP0_SHIFT 11 +#define PXP_HW_PXP_CTRL_ROTATE1_MASK 0x3000u +#define PXP_HW_PXP_CTRL_ROTATE1_SHIFT 12 +#define PXP_HW_PXP_CTRL_ROTATE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL_ROTATE1_SHIFT))&PXP_HW_PXP_CTRL_ROTATE1_MASK) +#define PXP_HW_PXP_CTRL_HFLIP1_MASK 0x4000u +#define PXP_HW_PXP_CTRL_HFLIP1_SHIFT 14 +#define PXP_HW_PXP_CTRL_VFLIP1_MASK 0x8000u +#define PXP_HW_PXP_CTRL_VFLIP1_SHIFT 15 +#define PXP_HW_PXP_CTRL_ENABLE_PS_AS_OUT_MASK 0x10000u +#define PXP_HW_PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT 16 +#define PXP_HW_PXP_CTRL_ENABLE_DITHER_MASK 0x20000u +#define PXP_HW_PXP_CTRL_ENABLE_DITHER_SHIFT 17 +#define PXP_HW_PXP_CTRL_ENABLE_WFE_A_MASK 0x40000u +#define PXP_HW_PXP_CTRL_ENABLE_WFE_A_SHIFT 18 +#define PXP_HW_PXP_CTRL_ENABLE_WFE_B_MASK 0x80000u +#define PXP_HW_PXP_CTRL_ENABLE_WFE_B_SHIFT 19 +#define PXP_HW_PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK 0x100000u +#define PXP_HW_PXP_CTRL_ENABLE_INPUT_FETCH_STORE_SHIFT 20 +#define PXP_HW_PXP_CTRL_ENABLE_ALPHA_B_MASK 0x200000u +#define PXP_HW_PXP_CTRL_ENABLE_ALPHA_B_SHIFT 21 +#define PXP_HW_PXP_CTRL_RSVD1_MASK 0x400000u +#define PXP_HW_PXP_CTRL_RSVD1_SHIFT 22 +#define PXP_HW_PXP_CTRL_BLOCK_SIZE_MASK 0x800000u +#define PXP_HW_PXP_CTRL_BLOCK_SIZE_SHIFT 23 +#define PXP_HW_PXP_CTRL_ENABLE_CSC2_MASK 0x1000000u +#define PXP_HW_PXP_CTRL_ENABLE_CSC2_SHIFT 24 +#define PXP_HW_PXP_CTRL_ENABLE_LUT_MASK 0x2000000u +#define PXP_HW_PXP_CTRL_ENABLE_LUT_SHIFT 25 +#define PXP_HW_PXP_CTRL_ENABLE_ROTATE0_MASK 0x4000000u +#define PXP_HW_PXP_CTRL_ENABLE_ROTATE0_SHIFT 26 +#define PXP_HW_PXP_CTRL_ENABLE_ROTATE1_MASK 0x8000000u +#define PXP_HW_PXP_CTRL_ENABLE_ROTATE1_SHIFT 27 +#define PXP_HW_PXP_CTRL_EN_REPEAT_MASK 0x10000000u +#define PXP_HW_PXP_CTRL_EN_REPEAT_SHIFT 28 +#define PXP_HW_PXP_CTRL_RSVD4_MASK 0x20000000u +#define PXP_HW_PXP_CTRL_RSVD4_SHIFT 29 +#define PXP_HW_PXP_CTRL_CLKGATE_MASK 0x40000000u +#define PXP_HW_PXP_CTRL_CLKGATE_SHIFT 30 +#define PXP_HW_PXP_CTRL_SFTRST_MASK 0x80000000u +#define PXP_HW_PXP_CTRL_SFTRST_SHIFT 31 +/* HW_PXP_STAT Bit Fields */ +#define PXP_HW_PXP_STAT_IRQ0_MASK 0x1u +#define PXP_HW_PXP_STAT_IRQ0_SHIFT 0 +#define PXP_HW_PXP_STAT_AXI_WRITE_ERROR_0_MASK 0x2u +#define PXP_HW_PXP_STAT_AXI_WRITE_ERROR_0_SHIFT 1 +#define PXP_HW_PXP_STAT_AXI_READ_ERROR_0_MASK 0x4u +#define PXP_HW_PXP_STAT_AXI_READ_ERROR_0_SHIFT 2 +#define PXP_HW_PXP_STAT_NEXT_IRQ_MASK 0x8u +#define PXP_HW_PXP_STAT_NEXT_IRQ_SHIFT 3 +#define PXP_HW_PXP_STAT_AXI_ERROR_ID_0_MASK 0xF0u +#define PXP_HW_PXP_STAT_AXI_ERROR_ID_0_SHIFT 4 +#define PXP_HW_PXP_STAT_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_STAT_AXI_ERROR_ID_0_SHIFT))&PXP_HW_PXP_STAT_AXI_ERROR_ID_0_MASK) +#define PXP_HW_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK 0x100u +#define PXP_HW_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT 8 +#define PXP_HW_PXP_STAT_AXI_WRITE_ERROR_1_MASK 0x200u +#define PXP_HW_PXP_STAT_AXI_WRITE_ERROR_1_SHIFT 9 +#define PXP_HW_PXP_STAT_AXI_READ_ERROR_1_MASK 0x400u +#define PXP_HW_PXP_STAT_AXI_READ_ERROR_1_SHIFT 10 +#define PXP_HW_PXP_STAT_RSVD2_MASK 0x800u +#define PXP_HW_PXP_STAT_RSVD2_SHIFT 11 +#define PXP_HW_PXP_STAT_AXI_ERROR_ID_1_MASK 0xF000u +#define PXP_HW_PXP_STAT_AXI_ERROR_ID_1_SHIFT 12 +#define PXP_HW_PXP_STAT_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_STAT_AXI_ERROR_ID_1_SHIFT))&PXP_HW_PXP_STAT_AXI_ERROR_ID_1_MASK) +#define PXP_HW_PXP_STAT_BLOCKY_MASK 0xFF0000u +#define PXP_HW_PXP_STAT_BLOCKY_SHIFT 16 +#define PXP_HW_PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_STAT_BLOCKY_SHIFT))&PXP_HW_PXP_STAT_BLOCKY_MASK) +#define PXP_HW_PXP_STAT_BLOCKX_MASK 0xFF000000u +#define PXP_HW_PXP_STAT_BLOCKX_SHIFT 24 +#define PXP_HW_PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_STAT_BLOCKX_SHIFT))&PXP_HW_PXP_STAT_BLOCKX_MASK) +/* HW_PXP_OUT_CTRL Bit Fields */ +#define PXP_HW_PXP_OUT_CTRL_FORMAT_MASK 0x1Fu +#define PXP_HW_PXP_OUT_CTRL_FORMAT_SHIFT 0 +#define PXP_HW_PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_FORMAT_SHIFT))&PXP_HW_PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_HW_PXP_OUT_CTRL_RSVD0_MASK 0xE0u +#define PXP_HW_PXP_OUT_CTRL_RSVD0_SHIFT 5 +#define PXP_HW_PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_OUT_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK 0x300u +#define PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT 8 +#define PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT))&PXP_HW_PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_HW_PXP_OUT_CTRL_RSVD1_MASK 0x7FFC00u +#define PXP_HW_PXP_OUT_CTRL_RSVD1_SHIFT 10 +#define PXP_HW_PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_OUT_CTRL_RSVD1_MASK) +#define PXP_HW_PXP_OUT_CTRL_ALPHA_OUTPUT_MASK 0x800000u +#define PXP_HW_PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT 23 +#define PXP_HW_PXP_OUT_CTRL_ALPHA_MASK 0xFF000000u +#define PXP_HW_PXP_OUT_CTRL_ALPHA_SHIFT 24 +#define PXP_HW_PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_CTRL_ALPHA_SHIFT))&PXP_HW_PXP_OUT_CTRL_ALPHA_MASK) +/* HW_PXP_OUT_BUF Bit Fields */ +#define PXP_HW_PXP_OUT_BUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_OUT_BUF_ADDR_SHIFT 0 +#define PXP_HW_PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_BUF_ADDR_SHIFT))&PXP_HW_PXP_OUT_BUF_ADDR_MASK) +/* HW_PXP_OUT_BUF2 Bit Fields */ +#define PXP_HW_PXP_OUT_BUF2_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_OUT_BUF2_ADDR_SHIFT 0 +#define PXP_HW_PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_BUF2_ADDR_SHIFT))&PXP_HW_PXP_OUT_BUF2_ADDR_MASK) +/* HW_PXP_OUT_PITCH Bit Fields */ +#define PXP_HW_PXP_OUT_PITCH_PITCH_MASK 0xFFFFu +#define PXP_HW_PXP_OUT_PITCH_PITCH_SHIFT 0 +#define PXP_HW_PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PITCH_PITCH_SHIFT))&PXP_HW_PXP_OUT_PITCH_PITCH_MASK) +#define PXP_HW_PXP_OUT_PITCH_RSVD_MASK 0xFFFF0000u +#define PXP_HW_PXP_OUT_PITCH_RSVD_SHIFT 16 +#define PXP_HW_PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PITCH_RSVD_SHIFT))&PXP_HW_PXP_OUT_PITCH_RSVD_MASK) +/* HW_PXP_OUT_LRC Bit Fields */ +#define PXP_HW_PXP_OUT_LRC_Y_MASK 0x3FFFu +#define PXP_HW_PXP_OUT_LRC_Y_SHIFT 0 +#define PXP_HW_PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_LRC_Y_SHIFT))&PXP_HW_PXP_OUT_LRC_Y_MASK) +#define PXP_HW_PXP_OUT_LRC_RSVD0_MASK 0xC000u +#define PXP_HW_PXP_OUT_LRC_RSVD0_SHIFT 14 +#define PXP_HW_PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_LRC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_LRC_RSVD0_MASK) +#define PXP_HW_PXP_OUT_LRC_X_MASK 0x3FFF0000u +#define PXP_HW_PXP_OUT_LRC_X_SHIFT 16 +#define PXP_HW_PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_LRC_X_SHIFT))&PXP_HW_PXP_OUT_LRC_X_MASK) +#define PXP_HW_PXP_OUT_LRC_RSVD1_MASK 0xC0000000u +#define PXP_HW_PXP_OUT_LRC_RSVD1_SHIFT 30 +#define PXP_HW_PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_LRC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_LRC_RSVD1_MASK) +/* HW_PXP_OUT_PS_ULC Bit Fields */ +#define PXP_HW_PXP_OUT_PS_ULC_Y_MASK 0x3FFFu +#define PXP_HW_PXP_OUT_PS_ULC_Y_SHIFT 0 +#define PXP_HW_PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_ULC_Y_SHIFT))&PXP_HW_PXP_OUT_PS_ULC_Y_MASK) +#define PXP_HW_PXP_OUT_PS_ULC_RSVD0_MASK 0xC000u +#define PXP_HW_PXP_OUT_PS_ULC_RSVD0_SHIFT 14 +#define PXP_HW_PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_ULC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_PS_ULC_RSVD0_MASK) +#define PXP_HW_PXP_OUT_PS_ULC_X_MASK 0x3FFF0000u +#define PXP_HW_PXP_OUT_PS_ULC_X_SHIFT 16 +#define PXP_HW_PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_ULC_X_SHIFT))&PXP_HW_PXP_OUT_PS_ULC_X_MASK) +#define PXP_HW_PXP_OUT_PS_ULC_RSVD1_MASK 0xC0000000u +#define PXP_HW_PXP_OUT_PS_ULC_RSVD1_SHIFT 30 +#define PXP_HW_PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_ULC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_PS_ULC_RSVD1_MASK) +/* HW_PXP_OUT_PS_LRC Bit Fields */ +#define PXP_HW_PXP_OUT_PS_LRC_Y_MASK 0x3FFFu +#define PXP_HW_PXP_OUT_PS_LRC_Y_SHIFT 0 +#define PXP_HW_PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_LRC_Y_SHIFT))&PXP_HW_PXP_OUT_PS_LRC_Y_MASK) +#define PXP_HW_PXP_OUT_PS_LRC_RSVD0_MASK 0xC000u +#define PXP_HW_PXP_OUT_PS_LRC_RSVD0_SHIFT 14 +#define PXP_HW_PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_LRC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_PS_LRC_RSVD0_MASK) +#define PXP_HW_PXP_OUT_PS_LRC_X_MASK 0x3FFF0000u +#define PXP_HW_PXP_OUT_PS_LRC_X_SHIFT 16 +#define PXP_HW_PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_LRC_X_SHIFT))&PXP_HW_PXP_OUT_PS_LRC_X_MASK) +#define PXP_HW_PXP_OUT_PS_LRC_RSVD1_MASK 0xC0000000u +#define PXP_HW_PXP_OUT_PS_LRC_RSVD1_SHIFT 30 +#define PXP_HW_PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_PS_LRC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_PS_LRC_RSVD1_MASK) +/* HW_PXP_OUT_AS_ULC Bit Fields */ +#define PXP_HW_PXP_OUT_AS_ULC_Y_MASK 0x3FFFu +#define PXP_HW_PXP_OUT_AS_ULC_Y_SHIFT 0 +#define PXP_HW_PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_ULC_Y_SHIFT))&PXP_HW_PXP_OUT_AS_ULC_Y_MASK) +#define PXP_HW_PXP_OUT_AS_ULC_RSVD0_MASK 0xC000u +#define PXP_HW_PXP_OUT_AS_ULC_RSVD0_SHIFT 14 +#define PXP_HW_PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_ULC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_AS_ULC_RSVD0_MASK) +#define PXP_HW_PXP_OUT_AS_ULC_X_MASK 0x3FFF0000u +#define PXP_HW_PXP_OUT_AS_ULC_X_SHIFT 16 +#define PXP_HW_PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_ULC_X_SHIFT))&PXP_HW_PXP_OUT_AS_ULC_X_MASK) +#define PXP_HW_PXP_OUT_AS_ULC_RSVD1_MASK 0xC0000000u +#define PXP_HW_PXP_OUT_AS_ULC_RSVD1_SHIFT 30 +#define PXP_HW_PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_ULC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_AS_ULC_RSVD1_MASK) +/* HW_PXP_OUT_AS_LRC Bit Fields */ +#define PXP_HW_PXP_OUT_AS_LRC_Y_MASK 0x3FFFu +#define PXP_HW_PXP_OUT_AS_LRC_Y_SHIFT 0 +#define PXP_HW_PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_LRC_Y_SHIFT))&PXP_HW_PXP_OUT_AS_LRC_Y_MASK) +#define PXP_HW_PXP_OUT_AS_LRC_RSVD0_MASK 0xC000u +#define PXP_HW_PXP_OUT_AS_LRC_RSVD0_SHIFT 14 +#define PXP_HW_PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_LRC_RSVD0_SHIFT))&PXP_HW_PXP_OUT_AS_LRC_RSVD0_MASK) +#define PXP_HW_PXP_OUT_AS_LRC_X_MASK 0x3FFF0000u +#define PXP_HW_PXP_OUT_AS_LRC_X_SHIFT 16 +#define PXP_HW_PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_LRC_X_SHIFT))&PXP_HW_PXP_OUT_AS_LRC_X_MASK) +#define PXP_HW_PXP_OUT_AS_LRC_RSVD1_MASK 0xC0000000u +#define PXP_HW_PXP_OUT_AS_LRC_RSVD1_SHIFT 30 +#define PXP_HW_PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_OUT_AS_LRC_RSVD1_SHIFT))&PXP_HW_PXP_OUT_AS_LRC_RSVD1_MASK) +/* HW_PXP_PS_CTRL Bit Fields */ +#define PXP_HW_PXP_PS_CTRL_FORMAT_MASK 0x3Fu +#define PXP_HW_PXP_PS_CTRL_FORMAT_SHIFT 0 +#define PXP_HW_PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CTRL_FORMAT_SHIFT))&PXP_HW_PXP_PS_CTRL_FORMAT_MASK) +#define PXP_HW_PXP_PS_CTRL_WB_SWAP_MASK 0x40u +#define PXP_HW_PXP_PS_CTRL_WB_SWAP_SHIFT 6 +#define PXP_HW_PXP_PS_CTRL_RSVD0_MASK 0x80u +#define PXP_HW_PXP_PS_CTRL_RSVD0_SHIFT 7 +#define PXP_HW_PXP_PS_CTRL_DECY_MASK 0x300u +#define PXP_HW_PXP_PS_CTRL_DECY_SHIFT 8 +#define PXP_HW_PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CTRL_DECY_SHIFT))&PXP_HW_PXP_PS_CTRL_DECY_MASK) +#define PXP_HW_PXP_PS_CTRL_DECX_MASK 0xC00u +#define PXP_HW_PXP_PS_CTRL_DECX_SHIFT 10 +#define PXP_HW_PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CTRL_DECX_SHIFT))&PXP_HW_PXP_PS_CTRL_DECX_MASK) +#define PXP_HW_PXP_PS_CTRL_RSVD1_MASK 0xFFFFF000u +#define PXP_HW_PXP_PS_CTRL_RSVD1_SHIFT 12 +#define PXP_HW_PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_PS_CTRL_RSVD1_MASK) +/* HW_PXP_PS_BUF Bit Fields */ +#define PXP_HW_PXP_PS_BUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_PS_BUF_ADDR_SHIFT 0 +#define PXP_HW_PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BUF_ADDR_SHIFT))&PXP_HW_PXP_PS_BUF_ADDR_MASK) +/* HW_PXP_PS_UBUF Bit Fields */ +#define PXP_HW_PXP_PS_UBUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_PS_UBUF_ADDR_SHIFT 0 +#define PXP_HW_PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_UBUF_ADDR_SHIFT))&PXP_HW_PXP_PS_UBUF_ADDR_MASK) +/* HW_PXP_PS_VBUF Bit Fields */ +#define PXP_HW_PXP_PS_VBUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_PS_VBUF_ADDR_SHIFT 0 +#define PXP_HW_PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_VBUF_ADDR_SHIFT))&PXP_HW_PXP_PS_VBUF_ADDR_MASK) +/* HW_PXP_PS_PITCH Bit Fields */ +#define PXP_HW_PXP_PS_PITCH_PITCH_MASK 0xFFFFu +#define PXP_HW_PXP_PS_PITCH_PITCH_SHIFT 0 +#define PXP_HW_PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_PITCH_PITCH_SHIFT))&PXP_HW_PXP_PS_PITCH_PITCH_MASK) +#define PXP_HW_PXP_PS_PITCH_RSVD_MASK 0xFFFF0000u +#define PXP_HW_PXP_PS_PITCH_RSVD_SHIFT 16 +#define PXP_HW_PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_PITCH_RSVD_SHIFT))&PXP_HW_PXP_PS_PITCH_RSVD_MASK) /* HW_PXP_PS_BACKGROUND_0 Bit Fields */ #define PXP_HW_PXP_PS_BACKGROUND_0_COLOR_MASK 0xFFFFFFu #define PXP_HW_PXP_PS_BACKGROUND_0_COLOR_SHIFT 0 @@ -84867,30 +34388,30 @@ typedef struct { #define PXP_HW_PXP_PS_BACKGROUND_0_RSVD_MASK 0xFF000000u #define PXP_HW_PXP_PS_BACKGROUND_0_RSVD_SHIFT 24 #define PXP_HW_PXP_PS_BACKGROUND_0_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_0_RSVD_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_0_RSVD_MASK) -/* PS_SCALE Bit Fields */ -#define PXP_PS_SCALE_XSCALE_MASK 0x7FFFu -#define PXP_PS_SCALE_XSCALE_SHIFT 0 -#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_SCALE_XSCALE_SHIFT))&PXP_PS_SCALE_XSCALE_MASK) -#define PXP_PS_SCALE_RSVD1_MASK 0x8000u -#define PXP_PS_SCALE_RSVD1_SHIFT 15 -#define PXP_PS_SCALE_YSCALE_MASK 0x7FFF0000u -#define PXP_PS_SCALE_YSCALE_SHIFT 16 -#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_SCALE_YSCALE_SHIFT))&PXP_PS_SCALE_YSCALE_MASK) -#define PXP_PS_SCALE_RSVD2_MASK 0x80000000u -#define PXP_PS_SCALE_RSVD2_SHIFT 31 -/* PS_OFFSET Bit Fields */ -#define PXP_PS_OFFSET_XOFFSET_MASK 0xFFFu -#define PXP_PS_OFFSET_XOFFSET_SHIFT 0 -#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_XOFFSET_SHIFT))&PXP_PS_OFFSET_XOFFSET_MASK) -#define PXP_PS_OFFSET_RSVD1_MASK 0xF000u -#define PXP_PS_OFFSET_RSVD1_SHIFT 12 -#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_RSVD1_SHIFT))&PXP_PS_OFFSET_RSVD1_MASK) -#define PXP_PS_OFFSET_YOFFSET_MASK 0xFFF0000u -#define PXP_PS_OFFSET_YOFFSET_SHIFT 16 -#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_YOFFSET_SHIFT))&PXP_PS_OFFSET_YOFFSET_MASK) -#define PXP_PS_OFFSET_RSVD2_MASK 0xF0000000u -#define PXP_PS_OFFSET_RSVD2_SHIFT 28 -#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_RSVD2_SHIFT))&PXP_PS_OFFSET_RSVD2_MASK) +/* HW_PXP_PS_SCALE Bit Fields */ +#define PXP_HW_PXP_PS_SCALE_XSCALE_MASK 0x7FFFu +#define PXP_HW_PXP_PS_SCALE_XSCALE_SHIFT 0 +#define PXP_HW_PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_SCALE_XSCALE_SHIFT))&PXP_HW_PXP_PS_SCALE_XSCALE_MASK) +#define PXP_HW_PXP_PS_SCALE_RSVD1_MASK 0x8000u +#define PXP_HW_PXP_PS_SCALE_RSVD1_SHIFT 15 +#define PXP_HW_PXP_PS_SCALE_YSCALE_MASK 0x7FFF0000u +#define PXP_HW_PXP_PS_SCALE_YSCALE_SHIFT 16 +#define PXP_HW_PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_SCALE_YSCALE_SHIFT))&PXP_HW_PXP_PS_SCALE_YSCALE_MASK) +#define PXP_HW_PXP_PS_SCALE_RSVD2_MASK 0x80000000u +#define PXP_HW_PXP_PS_SCALE_RSVD2_SHIFT 31 +/* HW_PXP_PS_OFFSET Bit Fields */ +#define PXP_HW_PXP_PS_OFFSET_XOFFSET_MASK 0xFFFu +#define PXP_HW_PXP_PS_OFFSET_XOFFSET_SHIFT 0 +#define PXP_HW_PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_OFFSET_XOFFSET_SHIFT))&PXP_HW_PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_HW_PXP_PS_OFFSET_RSVD1_MASK 0xF000u +#define PXP_HW_PXP_PS_OFFSET_RSVD1_SHIFT 12 +#define PXP_HW_PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_OFFSET_RSVD1_SHIFT))&PXP_HW_PXP_PS_OFFSET_RSVD1_MASK) +#define PXP_HW_PXP_PS_OFFSET_YOFFSET_MASK 0xFFF0000u +#define PXP_HW_PXP_PS_OFFSET_YOFFSET_SHIFT 16 +#define PXP_HW_PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_OFFSET_YOFFSET_SHIFT))&PXP_HW_PXP_PS_OFFSET_YOFFSET_MASK) +#define PXP_HW_PXP_PS_OFFSET_RSVD2_MASK 0xF0000000u +#define PXP_HW_PXP_PS_OFFSET_RSVD2_SHIFT 28 +#define PXP_HW_PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_OFFSET_RSVD2_SHIFT))&PXP_HW_PXP_PS_OFFSET_RSVD2_MASK) /* HW_PXP_PS_CLRKEYLOW_0 Bit Fields */ #define PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_MASK 0xFFFFFFu #define PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT 0 @@ -84905,41 +34426,41 @@ typedef struct { #define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_MASK 0xFF000000u #define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_SHIFT 24 #define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_MASK) -/* AS_CTRL Bit Fields */ -#define PXP_AS_CTRL_RSVD0_MASK 0x1u -#define PXP_AS_CTRL_RSVD0_SHIFT 0 -#define PXP_AS_CTRL_ALPHA_CTRL_MASK 0x6u -#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT 1 -#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ALPHA_CTRL_SHIFT))&PXP_AS_CTRL_ALPHA_CTRL_MASK) -#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK 0x8u -#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT 3 -#define PXP_AS_CTRL_FORMAT_MASK 0xF0u -#define PXP_AS_CTRL_FORMAT_SHIFT 4 -#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_FORMAT_SHIFT))&PXP_AS_CTRL_FORMAT_MASK) -#define PXP_AS_CTRL_ALPHA_MASK 0xFF00u -#define PXP_AS_CTRL_ALPHA_SHIFT 8 -#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ALPHA_SHIFT))&PXP_AS_CTRL_ALPHA_MASK) -#define PXP_AS_CTRL_ROP_MASK 0xF0000u -#define PXP_AS_CTRL_ROP_SHIFT 16 -#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ROP_SHIFT))&PXP_AS_CTRL_ROP_MASK) -#define PXP_AS_CTRL_ALPHA0_INVERT_MASK 0x100000u -#define PXP_AS_CTRL_ALPHA0_INVERT_SHIFT 20 -#define PXP_AS_CTRL_ALPHA1_INVERT_MASK 0x200000u -#define PXP_AS_CTRL_ALPHA1_INVERT_SHIFT 21 -#define PXP_AS_CTRL_RSVD1_MASK 0xFFC00000u -#define PXP_AS_CTRL_RSVD1_SHIFT 22 -#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_RSVD1_SHIFT))&PXP_AS_CTRL_RSVD1_MASK) -/* AS_BUF Bit Fields */ -#define PXP_AS_BUF_ADDR_MASK 0xFFFFFFFFu -#define PXP_AS_BUF_ADDR_SHIFT 0 -#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_BUF_ADDR_SHIFT))&PXP_AS_BUF_ADDR_MASK) -/* AS_PITCH Bit Fields */ -#define PXP_AS_PITCH_PITCH_MASK 0xFFFFu -#define PXP_AS_PITCH_PITCH_SHIFT 0 -#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_PITCH_PITCH_SHIFT))&PXP_AS_PITCH_PITCH_MASK) -#define PXP_AS_PITCH_RSVD_MASK 0xFFFF0000u -#define PXP_AS_PITCH_RSVD_SHIFT 16 -#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_PITCH_RSVD_SHIFT))&PXP_AS_PITCH_RSVD_MASK) +/* HW_PXP_AS_CTRL Bit Fields */ +#define PXP_HW_PXP_AS_CTRL_RSVD0_MASK 0x1u +#define PXP_HW_PXP_AS_CTRL_RSVD0_SHIFT 0 +#define PXP_HW_PXP_AS_CTRL_ALPHA_CTRL_MASK 0x6u +#define PXP_HW_PXP_AS_CTRL_ALPHA_CTRL_SHIFT 1 +#define PXP_HW_PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_ALPHA_CTRL_SHIFT))&PXP_HW_PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_HW_PXP_AS_CTRL_ENABLE_COLORKEY_MASK 0x8u +#define PXP_HW_PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT 3 +#define PXP_HW_PXP_AS_CTRL_FORMAT_MASK 0xF0u +#define PXP_HW_PXP_AS_CTRL_FORMAT_SHIFT 4 +#define PXP_HW_PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_FORMAT_SHIFT))&PXP_HW_PXP_AS_CTRL_FORMAT_MASK) +#define PXP_HW_PXP_AS_CTRL_ALPHA_MASK 0xFF00u +#define PXP_HW_PXP_AS_CTRL_ALPHA_SHIFT 8 +#define PXP_HW_PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_ALPHA_SHIFT))&PXP_HW_PXP_AS_CTRL_ALPHA_MASK) +#define PXP_HW_PXP_AS_CTRL_ROP_MASK 0xF0000u +#define PXP_HW_PXP_AS_CTRL_ROP_SHIFT 16 +#define PXP_HW_PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_ROP_SHIFT))&PXP_HW_PXP_AS_CTRL_ROP_MASK) +#define PXP_HW_PXP_AS_CTRL_ALPHA0_INVERT_MASK 0x100000u +#define PXP_HW_PXP_AS_CTRL_ALPHA0_INVERT_SHIFT 20 +#define PXP_HW_PXP_AS_CTRL_ALPHA1_INVERT_MASK 0x200000u +#define PXP_HW_PXP_AS_CTRL_ALPHA1_INVERT_SHIFT 21 +#define PXP_HW_PXP_AS_CTRL_RSVD1_MASK 0xFFC00000u +#define PXP_HW_PXP_AS_CTRL_RSVD1_SHIFT 22 +#define PXP_HW_PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_AS_CTRL_RSVD1_MASK) +/* HW_PXP_AS_BUF Bit Fields */ +#define PXP_HW_PXP_AS_BUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_AS_BUF_ADDR_SHIFT 0 +#define PXP_HW_PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_BUF_ADDR_SHIFT))&PXP_HW_PXP_AS_BUF_ADDR_MASK) +/* HW_PXP_AS_PITCH Bit Fields */ +#define PXP_HW_PXP_AS_PITCH_PITCH_MASK 0xFFFFu +#define PXP_HW_PXP_AS_PITCH_PITCH_SHIFT 0 +#define PXP_HW_PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_PITCH_PITCH_SHIFT))&PXP_HW_PXP_AS_PITCH_PITCH_MASK) +#define PXP_HW_PXP_AS_PITCH_RSVD_MASK 0xFFFF0000u +#define PXP_HW_PXP_AS_PITCH_RSVD_SHIFT 16 +#define PXP_HW_PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_PITCH_RSVD_SHIFT))&PXP_HW_PXP_AS_PITCH_RSVD_MASK) /* HW_PXP_AS_CLRKEYLOW_0 Bit Fields */ #define PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_MASK 0xFFFFFFu #define PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT 0 @@ -84954,188 +34475,188 @@ typedef struct { #define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_MASK 0xFF000000u #define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_SHIFT 24 #define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_MASK) -/* CSC1_COEF0 Bit Fields */ -#define PXP_CSC1_COEF0_Y_OFFSET_MASK 0x1FFu -#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT 0 -#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_Y_OFFSET_SHIFT))&PXP_CSC1_COEF0_Y_OFFSET_MASK) -#define PXP_CSC1_COEF0_UV_OFFSET_MASK 0x3FE00u -#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT 9 -#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_UV_OFFSET_SHIFT))&PXP_CSC1_COEF0_UV_OFFSET_MASK) -#define PXP_CSC1_COEF0_C0_MASK 0x1FFC0000u -#define PXP_CSC1_COEF0_C0_SHIFT 18 -#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_C0_SHIFT))&PXP_CSC1_COEF0_C0_MASK) -#define PXP_CSC1_COEF0_RSVD1_MASK 0x20000000u -#define PXP_CSC1_COEF0_RSVD1_SHIFT 29 -#define PXP_CSC1_COEF0_BYPASS_MASK 0x40000000u -#define PXP_CSC1_COEF0_BYPASS_SHIFT 30 -#define PXP_CSC1_COEF0_YCBCR_MODE_MASK 0x80000000u -#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT 31 -/* CSC1_COEF1 Bit Fields */ -#define PXP_CSC1_COEF1_C4_MASK 0x7FFu -#define PXP_CSC1_COEF1_C4_SHIFT 0 -#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_C4_SHIFT))&PXP_CSC1_COEF1_C4_MASK) -#define PXP_CSC1_COEF1_RSVD0_MASK 0xF800u -#define PXP_CSC1_COEF1_RSVD0_SHIFT 11 -#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_RSVD0_SHIFT))&PXP_CSC1_COEF1_RSVD0_MASK) -#define PXP_CSC1_COEF1_C1_MASK 0x7FF0000u -#define PXP_CSC1_COEF1_C1_SHIFT 16 -#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_C1_SHIFT))&PXP_CSC1_COEF1_C1_MASK) -#define PXP_CSC1_COEF1_RSVD1_MASK 0xF8000000u -#define PXP_CSC1_COEF1_RSVD1_SHIFT 27 -#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_RSVD1_SHIFT))&PXP_CSC1_COEF1_RSVD1_MASK) -/* CSC1_COEF2 Bit Fields */ -#define PXP_CSC1_COEF2_C3_MASK 0x7FFu -#define PXP_CSC1_COEF2_C3_SHIFT 0 -#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_C3_SHIFT))&PXP_CSC1_COEF2_C3_MASK) -#define PXP_CSC1_COEF2_RSVD0_MASK 0xF800u -#define PXP_CSC1_COEF2_RSVD0_SHIFT 11 -#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_RSVD0_SHIFT))&PXP_CSC1_COEF2_RSVD0_MASK) -#define PXP_CSC1_COEF2_C2_MASK 0x7FF0000u -#define PXP_CSC1_COEF2_C2_SHIFT 16 -#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_C2_SHIFT))&PXP_CSC1_COEF2_C2_MASK) -#define PXP_CSC1_COEF2_RSVD1_MASK 0xF8000000u -#define PXP_CSC1_COEF2_RSVD1_SHIFT 27 -#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_RSVD1_SHIFT))&PXP_CSC1_COEF2_RSVD1_MASK) -/* CSC2_CTRL Bit Fields */ -#define PXP_CSC2_CTRL_BYPASS_MASK 0x1u -#define PXP_CSC2_CTRL_BYPASS_SHIFT 0 -#define PXP_CSC2_CTRL_CSC_MODE_MASK 0x6u -#define PXP_CSC2_CTRL_CSC_MODE_SHIFT 1 -#define PXP_CSC2_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_CTRL_CSC_MODE_SHIFT))&PXP_CSC2_CTRL_CSC_MODE_MASK) -#define PXP_CSC2_CTRL_RSVD_MASK 0xFFFFFFF8u -#define PXP_CSC2_CTRL_RSVD_SHIFT 3 -#define PXP_CSC2_CTRL_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_CTRL_RSVD_SHIFT))&PXP_CSC2_CTRL_RSVD_MASK) -/* CSC2_COEF0 Bit Fields */ -#define PXP_CSC2_COEF0_A1_MASK 0x7FFu -#define PXP_CSC2_COEF0_A1_SHIFT 0 -#define PXP_CSC2_COEF0_A1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_A1_SHIFT))&PXP_CSC2_COEF0_A1_MASK) -#define PXP_CSC2_COEF0_RSVD0_MASK 0xF800u -#define PXP_CSC2_COEF0_RSVD0_SHIFT 11 -#define PXP_CSC2_COEF0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_RSVD0_SHIFT))&PXP_CSC2_COEF0_RSVD0_MASK) -#define PXP_CSC2_COEF0_A2_MASK 0x7FF0000u -#define PXP_CSC2_COEF0_A2_SHIFT 16 -#define PXP_CSC2_COEF0_A2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_A2_SHIFT))&PXP_CSC2_COEF0_A2_MASK) -#define PXP_CSC2_COEF0_RSVD1_MASK 0xF8000000u -#define PXP_CSC2_COEF0_RSVD1_SHIFT 27 -#define PXP_CSC2_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_RSVD1_SHIFT))&PXP_CSC2_COEF0_RSVD1_MASK) -/* CSC2_COEF1 Bit Fields */ -#define PXP_CSC2_COEF1_A3_MASK 0x7FFu -#define PXP_CSC2_COEF1_A3_SHIFT 0 -#define PXP_CSC2_COEF1_A3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_A3_SHIFT))&PXP_CSC2_COEF1_A3_MASK) -#define PXP_CSC2_COEF1_RSVD0_MASK 0xF800u -#define PXP_CSC2_COEF1_RSVD0_SHIFT 11 -#define PXP_CSC2_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_RSVD0_SHIFT))&PXP_CSC2_COEF1_RSVD0_MASK) -#define PXP_CSC2_COEF1_B1_MASK 0x7FF0000u -#define PXP_CSC2_COEF1_B1_SHIFT 16 -#define PXP_CSC2_COEF1_B1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_B1_SHIFT))&PXP_CSC2_COEF1_B1_MASK) -#define PXP_CSC2_COEF1_RSVD1_MASK 0xF8000000u -#define PXP_CSC2_COEF1_RSVD1_SHIFT 27 -#define PXP_CSC2_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_RSVD1_SHIFT))&PXP_CSC2_COEF1_RSVD1_MASK) -/* CSC2_COEF2 Bit Fields */ -#define PXP_CSC2_COEF2_B2_MASK 0x7FFu -#define PXP_CSC2_COEF2_B2_SHIFT 0 -#define PXP_CSC2_COEF2_B2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_B2_SHIFT))&PXP_CSC2_COEF2_B2_MASK) -#define PXP_CSC2_COEF2_RSVD0_MASK 0xF800u -#define PXP_CSC2_COEF2_RSVD0_SHIFT 11 -#define PXP_CSC2_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_RSVD0_SHIFT))&PXP_CSC2_COEF2_RSVD0_MASK) -#define PXP_CSC2_COEF2_B3_MASK 0x7FF0000u -#define PXP_CSC2_COEF2_B3_SHIFT 16 -#define PXP_CSC2_COEF2_B3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_B3_SHIFT))&PXP_CSC2_COEF2_B3_MASK) -#define PXP_CSC2_COEF2_RSVD1_MASK 0xF8000000u -#define PXP_CSC2_COEF2_RSVD1_SHIFT 27 -#define PXP_CSC2_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_RSVD1_SHIFT))&PXP_CSC2_COEF2_RSVD1_MASK) -/* CSC2_COEF3 Bit Fields */ -#define PXP_CSC2_COEF3_C1_MASK 0x7FFu -#define PXP_CSC2_COEF3_C1_SHIFT 0 -#define PXP_CSC2_COEF3_C1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_C1_SHIFT))&PXP_CSC2_COEF3_C1_MASK) -#define PXP_CSC2_COEF3_RSVD0_MASK 0xF800u -#define PXP_CSC2_COEF3_RSVD0_SHIFT 11 -#define PXP_CSC2_COEF3_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_RSVD0_SHIFT))&PXP_CSC2_COEF3_RSVD0_MASK) -#define PXP_CSC2_COEF3_C2_MASK 0x7FF0000u -#define PXP_CSC2_COEF3_C2_SHIFT 16 -#define PXP_CSC2_COEF3_C2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_C2_SHIFT))&PXP_CSC2_COEF3_C2_MASK) -#define PXP_CSC2_COEF3_RSVD1_MASK 0xF8000000u -#define PXP_CSC2_COEF3_RSVD1_SHIFT 27 -#define PXP_CSC2_COEF3_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_RSVD1_SHIFT))&PXP_CSC2_COEF3_RSVD1_MASK) -/* CSC2_COEF4 Bit Fields */ -#define PXP_CSC2_COEF4_C3_MASK 0x7FFu -#define PXP_CSC2_COEF4_C3_SHIFT 0 -#define PXP_CSC2_COEF4_C3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_C3_SHIFT))&PXP_CSC2_COEF4_C3_MASK) -#define PXP_CSC2_COEF4_RSVD0_MASK 0xF800u -#define PXP_CSC2_COEF4_RSVD0_SHIFT 11 -#define PXP_CSC2_COEF4_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_RSVD0_SHIFT))&PXP_CSC2_COEF4_RSVD0_MASK) -#define PXP_CSC2_COEF4_D1_MASK 0x1FF0000u -#define PXP_CSC2_COEF4_D1_SHIFT 16 -#define PXP_CSC2_COEF4_D1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_D1_SHIFT))&PXP_CSC2_COEF4_D1_MASK) -#define PXP_CSC2_COEF4_RSVD1_MASK 0xFE000000u -#define PXP_CSC2_COEF4_RSVD1_SHIFT 25 -#define PXP_CSC2_COEF4_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_RSVD1_SHIFT))&PXP_CSC2_COEF4_RSVD1_MASK) -/* CSC2_COEF5 Bit Fields */ -#define PXP_CSC2_COEF5_D2_MASK 0x1FFu -#define PXP_CSC2_COEF5_D2_SHIFT 0 -#define PXP_CSC2_COEF5_D2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_D2_SHIFT))&PXP_CSC2_COEF5_D2_MASK) -#define PXP_CSC2_COEF5_RSVD0_MASK 0xFE00u -#define PXP_CSC2_COEF5_RSVD0_SHIFT 9 -#define PXP_CSC2_COEF5_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_RSVD0_SHIFT))&PXP_CSC2_COEF5_RSVD0_MASK) -#define PXP_CSC2_COEF5_D3_MASK 0x1FF0000u -#define PXP_CSC2_COEF5_D3_SHIFT 16 -#define PXP_CSC2_COEF5_D3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_D3_SHIFT))&PXP_CSC2_COEF5_D3_MASK) -#define PXP_CSC2_COEF5_RSVD1_MASK 0xFE000000u -#define PXP_CSC2_COEF5_RSVD1_SHIFT 25 -#define PXP_CSC2_COEF5_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_RSVD1_SHIFT))&PXP_CSC2_COEF5_RSVD1_MASK) -/* LUT_CTRL Bit Fields */ -#define PXP_LUT_CTRL_DMA_START_MASK 0x1u -#define PXP_LUT_CTRL_DMA_START_SHIFT 0 -#define PXP_LUT_CTRL_RSVD0_MASK 0xFEu -#define PXP_LUT_CTRL_RSVD0_SHIFT 1 -#define PXP_LUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD0_SHIFT))&PXP_LUT_CTRL_RSVD0_MASK) -#define PXP_LUT_CTRL_INVALID_MASK 0x100u -#define PXP_LUT_CTRL_INVALID_SHIFT 8 -#define PXP_LUT_CTRL_LRU_UPD_MASK 0x200u -#define PXP_LUT_CTRL_LRU_UPD_SHIFT 9 -#define PXP_LUT_CTRL_SEL_8KB_MASK 0x400u -#define PXP_LUT_CTRL_SEL_8KB_SHIFT 10 -#define PXP_LUT_CTRL_RSVD1_MASK 0xF800u -#define PXP_LUT_CTRL_RSVD1_SHIFT 11 -#define PXP_LUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD1_SHIFT))&PXP_LUT_CTRL_RSVD1_MASK) -#define PXP_LUT_CTRL_OUT_MODE_MASK 0x30000u -#define PXP_LUT_CTRL_OUT_MODE_SHIFT 16 -#define PXP_LUT_CTRL_OUT_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_OUT_MODE_SHIFT))&PXP_LUT_CTRL_OUT_MODE_MASK) -#define PXP_LUT_CTRL_RSVD2_MASK 0xFC0000u -#define PXP_LUT_CTRL_RSVD2_SHIFT 18 -#define PXP_LUT_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD2_SHIFT))&PXP_LUT_CTRL_RSVD2_MASK) -#define PXP_LUT_CTRL_LOOKUP_MODE_MASK 0x3000000u -#define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT 24 -#define PXP_LUT_CTRL_LOOKUP_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_LOOKUP_MODE_SHIFT))&PXP_LUT_CTRL_LOOKUP_MODE_MASK) -#define PXP_LUT_CTRL_RSVD3_MASK 0x7C000000u -#define PXP_LUT_CTRL_RSVD3_SHIFT 26 -#define PXP_LUT_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD3_SHIFT))&PXP_LUT_CTRL_RSVD3_MASK) -#define PXP_LUT_CTRL_BYPASS_MASK 0x80000000u -#define PXP_LUT_CTRL_BYPASS_SHIFT 31 -/* LUT_ADDR Bit Fields */ -#define PXP_LUT_ADDR_ADDR_MASK 0x3FFFu -#define PXP_LUT_ADDR_ADDR_SHIFT 0 -#define PXP_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_ADDR_SHIFT))&PXP_LUT_ADDR_ADDR_MASK) -#define PXP_LUT_ADDR_RSVD1_MASK 0xC000u -#define PXP_LUT_ADDR_RSVD1_SHIFT 14 -#define PXP_LUT_ADDR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_RSVD1_SHIFT))&PXP_LUT_ADDR_RSVD1_MASK) -#define PXP_LUT_ADDR_NUM_BYTES_MASK 0x7FFF0000u -#define PXP_LUT_ADDR_NUM_BYTES_SHIFT 16 -#define PXP_LUT_ADDR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_NUM_BYTES_SHIFT))&PXP_LUT_ADDR_NUM_BYTES_MASK) -#define PXP_LUT_ADDR_RSVD2_MASK 0x80000000u -#define PXP_LUT_ADDR_RSVD2_SHIFT 31 -/* LUT_DATA Bit Fields */ -#define PXP_LUT_DATA_DATA_MASK 0xFFFFFFFFu -#define PXP_LUT_DATA_DATA_SHIFT 0 -#define PXP_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_DATA_DATA_SHIFT))&PXP_LUT_DATA_DATA_MASK) -/* LUT_EXTMEM Bit Fields */ -#define PXP_LUT_EXTMEM_ADDR_MASK 0xFFFFFFFFu -#define PXP_LUT_EXTMEM_ADDR_SHIFT 0 -#define PXP_LUT_EXTMEM_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_EXTMEM_ADDR_SHIFT))&PXP_LUT_EXTMEM_ADDR_MASK) -/* CFA Bit Fields */ -#define PXP_CFA_DATA_MASK 0xFFFFFFFFu -#define PXP_CFA_DATA_SHIFT 0 -#define PXP_CFA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_CFA_DATA_SHIFT))&PXP_CFA_DATA_MASK) +/* HW_PXP_CSC1_COEF0 Bit Fields */ +#define PXP_HW_PXP_CSC1_COEF0_Y_OFFSET_MASK 0x1FFu +#define PXP_HW_PXP_CSC1_COEF0_Y_OFFSET_SHIFT 0 +#define PXP_HW_PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF0_Y_OFFSET_SHIFT))&PXP_HW_PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_HW_PXP_CSC1_COEF0_UV_OFFSET_MASK 0x3FE00u +#define PXP_HW_PXP_CSC1_COEF0_UV_OFFSET_SHIFT 9 +#define PXP_HW_PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF0_UV_OFFSET_SHIFT))&PXP_HW_PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_HW_PXP_CSC1_COEF0_C0_MASK 0x1FFC0000u +#define PXP_HW_PXP_CSC1_COEF0_C0_SHIFT 18 +#define PXP_HW_PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF0_C0_SHIFT))&PXP_HW_PXP_CSC1_COEF0_C0_MASK) +#define PXP_HW_PXP_CSC1_COEF0_RSVD1_MASK 0x20000000u +#define PXP_HW_PXP_CSC1_COEF0_RSVD1_SHIFT 29 +#define PXP_HW_PXP_CSC1_COEF0_BYPASS_MASK 0x40000000u +#define PXP_HW_PXP_CSC1_COEF0_BYPASS_SHIFT 30 +#define PXP_HW_PXP_CSC1_COEF0_YCBCR_MODE_MASK 0x80000000u +#define PXP_HW_PXP_CSC1_COEF0_YCBCR_MODE_SHIFT 31 +/* HW_PXP_CSC1_COEF1 Bit Fields */ +#define PXP_HW_PXP_CSC1_COEF1_C4_MASK 0x7FFu +#define PXP_HW_PXP_CSC1_COEF1_C4_SHIFT 0 +#define PXP_HW_PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF1_C4_SHIFT))&PXP_HW_PXP_CSC1_COEF1_C4_MASK) +#define PXP_HW_PXP_CSC1_COEF1_RSVD0_MASK 0xF800u +#define PXP_HW_PXP_CSC1_COEF1_RSVD0_SHIFT 11 +#define PXP_HW_PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF1_RSVD0_SHIFT))&PXP_HW_PXP_CSC1_COEF1_RSVD0_MASK) +#define PXP_HW_PXP_CSC1_COEF1_C1_MASK 0x7FF0000u +#define PXP_HW_PXP_CSC1_COEF1_C1_SHIFT 16 +#define PXP_HW_PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF1_C1_SHIFT))&PXP_HW_PXP_CSC1_COEF1_C1_MASK) +#define PXP_HW_PXP_CSC1_COEF1_RSVD1_MASK 0xF8000000u +#define PXP_HW_PXP_CSC1_COEF1_RSVD1_SHIFT 27 +#define PXP_HW_PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF1_RSVD1_SHIFT))&PXP_HW_PXP_CSC1_COEF1_RSVD1_MASK) +/* HW_PXP_CSC1_COEF2 Bit Fields */ +#define PXP_HW_PXP_CSC1_COEF2_C3_MASK 0x7FFu +#define PXP_HW_PXP_CSC1_COEF2_C3_SHIFT 0 +#define PXP_HW_PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF2_C3_SHIFT))&PXP_HW_PXP_CSC1_COEF2_C3_MASK) +#define PXP_HW_PXP_CSC1_COEF2_RSVD0_MASK 0xF800u +#define PXP_HW_PXP_CSC1_COEF2_RSVD0_SHIFT 11 +#define PXP_HW_PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF2_RSVD0_SHIFT))&PXP_HW_PXP_CSC1_COEF2_RSVD0_MASK) +#define PXP_HW_PXP_CSC1_COEF2_C2_MASK 0x7FF0000u +#define PXP_HW_PXP_CSC1_COEF2_C2_SHIFT 16 +#define PXP_HW_PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF2_C2_SHIFT))&PXP_HW_PXP_CSC1_COEF2_C2_MASK) +#define PXP_HW_PXP_CSC1_COEF2_RSVD1_MASK 0xF8000000u +#define PXP_HW_PXP_CSC1_COEF2_RSVD1_SHIFT 27 +#define PXP_HW_PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC1_COEF2_RSVD1_SHIFT))&PXP_HW_PXP_CSC1_COEF2_RSVD1_MASK) +/* HW_PXP_CSC2_CTRL Bit Fields */ +#define PXP_HW_PXP_CSC2_CTRL_BYPASS_MASK 0x1u +#define PXP_HW_PXP_CSC2_CTRL_BYPASS_SHIFT 0 +#define PXP_HW_PXP_CSC2_CTRL_CSC_MODE_MASK 0x6u +#define PXP_HW_PXP_CSC2_CTRL_CSC_MODE_SHIFT 1 +#define PXP_HW_PXP_CSC2_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_CTRL_CSC_MODE_SHIFT))&PXP_HW_PXP_CSC2_CTRL_CSC_MODE_MASK) +#define PXP_HW_PXP_CSC2_CTRL_RSVD_MASK 0xFFFFFFF8u +#define PXP_HW_PXP_CSC2_CTRL_RSVD_SHIFT 3 +#define PXP_HW_PXP_CSC2_CTRL_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_CTRL_RSVD_SHIFT))&PXP_HW_PXP_CSC2_CTRL_RSVD_MASK) +/* HW_PXP_CSC2_COEF0 Bit Fields */ +#define PXP_HW_PXP_CSC2_COEF0_A1_MASK 0x7FFu +#define PXP_HW_PXP_CSC2_COEF0_A1_SHIFT 0 +#define PXP_HW_PXP_CSC2_COEF0_A1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF0_A1_SHIFT))&PXP_HW_PXP_CSC2_COEF0_A1_MASK) +#define PXP_HW_PXP_CSC2_COEF0_RSVD0_MASK 0xF800u +#define PXP_HW_PXP_CSC2_COEF0_RSVD0_SHIFT 11 +#define PXP_HW_PXP_CSC2_COEF0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF0_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF0_RSVD0_MASK) +#define PXP_HW_PXP_CSC2_COEF0_A2_MASK 0x7FF0000u +#define PXP_HW_PXP_CSC2_COEF0_A2_SHIFT 16 +#define PXP_HW_PXP_CSC2_COEF0_A2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF0_A2_SHIFT))&PXP_HW_PXP_CSC2_COEF0_A2_MASK) +#define PXP_HW_PXP_CSC2_COEF0_RSVD1_MASK 0xF8000000u +#define PXP_HW_PXP_CSC2_COEF0_RSVD1_SHIFT 27 +#define PXP_HW_PXP_CSC2_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF0_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF0_RSVD1_MASK) +/* HW_PXP_CSC2_COEF1 Bit Fields */ +#define PXP_HW_PXP_CSC2_COEF1_A3_MASK 0x7FFu +#define PXP_HW_PXP_CSC2_COEF1_A3_SHIFT 0 +#define PXP_HW_PXP_CSC2_COEF1_A3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF1_A3_SHIFT))&PXP_HW_PXP_CSC2_COEF1_A3_MASK) +#define PXP_HW_PXP_CSC2_COEF1_RSVD0_MASK 0xF800u +#define PXP_HW_PXP_CSC2_COEF1_RSVD0_SHIFT 11 +#define PXP_HW_PXP_CSC2_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF1_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF1_RSVD0_MASK) +#define PXP_HW_PXP_CSC2_COEF1_B1_MASK 0x7FF0000u +#define PXP_HW_PXP_CSC2_COEF1_B1_SHIFT 16 +#define PXP_HW_PXP_CSC2_COEF1_B1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF1_B1_SHIFT))&PXP_HW_PXP_CSC2_COEF1_B1_MASK) +#define PXP_HW_PXP_CSC2_COEF1_RSVD1_MASK 0xF8000000u +#define PXP_HW_PXP_CSC2_COEF1_RSVD1_SHIFT 27 +#define PXP_HW_PXP_CSC2_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF1_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF1_RSVD1_MASK) +/* HW_PXP_CSC2_COEF2 Bit Fields */ +#define PXP_HW_PXP_CSC2_COEF2_B2_MASK 0x7FFu +#define PXP_HW_PXP_CSC2_COEF2_B2_SHIFT 0 +#define PXP_HW_PXP_CSC2_COEF2_B2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF2_B2_SHIFT))&PXP_HW_PXP_CSC2_COEF2_B2_MASK) +#define PXP_HW_PXP_CSC2_COEF2_RSVD0_MASK 0xF800u +#define PXP_HW_PXP_CSC2_COEF2_RSVD0_SHIFT 11 +#define PXP_HW_PXP_CSC2_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF2_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF2_RSVD0_MASK) +#define PXP_HW_PXP_CSC2_COEF2_B3_MASK 0x7FF0000u +#define PXP_HW_PXP_CSC2_COEF2_B3_SHIFT 16 +#define PXP_HW_PXP_CSC2_COEF2_B3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF2_B3_SHIFT))&PXP_HW_PXP_CSC2_COEF2_B3_MASK) +#define PXP_HW_PXP_CSC2_COEF2_RSVD1_MASK 0xF8000000u +#define PXP_HW_PXP_CSC2_COEF2_RSVD1_SHIFT 27 +#define PXP_HW_PXP_CSC2_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF2_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF2_RSVD1_MASK) +/* HW_PXP_CSC2_COEF3 Bit Fields */ +#define PXP_HW_PXP_CSC2_COEF3_C1_MASK 0x7FFu +#define PXP_HW_PXP_CSC2_COEF3_C1_SHIFT 0 +#define PXP_HW_PXP_CSC2_COEF3_C1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF3_C1_SHIFT))&PXP_HW_PXP_CSC2_COEF3_C1_MASK) +#define PXP_HW_PXP_CSC2_COEF3_RSVD0_MASK 0xF800u +#define PXP_HW_PXP_CSC2_COEF3_RSVD0_SHIFT 11 +#define PXP_HW_PXP_CSC2_COEF3_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF3_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF3_RSVD0_MASK) +#define PXP_HW_PXP_CSC2_COEF3_C2_MASK 0x7FF0000u +#define PXP_HW_PXP_CSC2_COEF3_C2_SHIFT 16 +#define PXP_HW_PXP_CSC2_COEF3_C2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF3_C2_SHIFT))&PXP_HW_PXP_CSC2_COEF3_C2_MASK) +#define PXP_HW_PXP_CSC2_COEF3_RSVD1_MASK 0xF8000000u +#define PXP_HW_PXP_CSC2_COEF3_RSVD1_SHIFT 27 +#define PXP_HW_PXP_CSC2_COEF3_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF3_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF3_RSVD1_MASK) +/* HW_PXP_CSC2_COEF4 Bit Fields */ +#define PXP_HW_PXP_CSC2_COEF4_C3_MASK 0x7FFu +#define PXP_HW_PXP_CSC2_COEF4_C3_SHIFT 0 +#define PXP_HW_PXP_CSC2_COEF4_C3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF4_C3_SHIFT))&PXP_HW_PXP_CSC2_COEF4_C3_MASK) +#define PXP_HW_PXP_CSC2_COEF4_RSVD0_MASK 0xF800u +#define PXP_HW_PXP_CSC2_COEF4_RSVD0_SHIFT 11 +#define PXP_HW_PXP_CSC2_COEF4_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF4_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF4_RSVD0_MASK) +#define PXP_HW_PXP_CSC2_COEF4_D1_MASK 0x1FF0000u +#define PXP_HW_PXP_CSC2_COEF4_D1_SHIFT 16 +#define PXP_HW_PXP_CSC2_COEF4_D1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF4_D1_SHIFT))&PXP_HW_PXP_CSC2_COEF4_D1_MASK) +#define PXP_HW_PXP_CSC2_COEF4_RSVD1_MASK 0xFE000000u +#define PXP_HW_PXP_CSC2_COEF4_RSVD1_SHIFT 25 +#define PXP_HW_PXP_CSC2_COEF4_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF4_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF4_RSVD1_MASK) +/* HW_PXP_CSC2_COEF5 Bit Fields */ +#define PXP_HW_PXP_CSC2_COEF5_D2_MASK 0x1FFu +#define PXP_HW_PXP_CSC2_COEF5_D2_SHIFT 0 +#define PXP_HW_PXP_CSC2_COEF5_D2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF5_D2_SHIFT))&PXP_HW_PXP_CSC2_COEF5_D2_MASK) +#define PXP_HW_PXP_CSC2_COEF5_RSVD0_MASK 0xFE00u +#define PXP_HW_PXP_CSC2_COEF5_RSVD0_SHIFT 9 +#define PXP_HW_PXP_CSC2_COEF5_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF5_RSVD0_SHIFT))&PXP_HW_PXP_CSC2_COEF5_RSVD0_MASK) +#define PXP_HW_PXP_CSC2_COEF5_D3_MASK 0x1FF0000u +#define PXP_HW_PXP_CSC2_COEF5_D3_SHIFT 16 +#define PXP_HW_PXP_CSC2_COEF5_D3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF5_D3_SHIFT))&PXP_HW_PXP_CSC2_COEF5_D3_MASK) +#define PXP_HW_PXP_CSC2_COEF5_RSVD1_MASK 0xFE000000u +#define PXP_HW_PXP_CSC2_COEF5_RSVD1_SHIFT 25 +#define PXP_HW_PXP_CSC2_COEF5_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CSC2_COEF5_RSVD1_SHIFT))&PXP_HW_PXP_CSC2_COEF5_RSVD1_MASK) +/* HW_PXP_LUT_CTRL Bit Fields */ +#define PXP_HW_PXP_LUT_CTRL_DMA_START_MASK 0x1u +#define PXP_HW_PXP_LUT_CTRL_DMA_START_SHIFT 0 +#define PXP_HW_PXP_LUT_CTRL_RSVD0_MASK 0xFEu +#define PXP_HW_PXP_LUT_CTRL_RSVD0_SHIFT 1 +#define PXP_HW_PXP_LUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_LUT_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_LUT_CTRL_INVALID_MASK 0x100u +#define PXP_HW_PXP_LUT_CTRL_INVALID_SHIFT 8 +#define PXP_HW_PXP_LUT_CTRL_LRU_UPD_MASK 0x200u +#define PXP_HW_PXP_LUT_CTRL_LRU_UPD_SHIFT 9 +#define PXP_HW_PXP_LUT_CTRL_SEL_8KB_MASK 0x400u +#define PXP_HW_PXP_LUT_CTRL_SEL_8KB_SHIFT 10 +#define PXP_HW_PXP_LUT_CTRL_RSVD1_MASK 0xF800u +#define PXP_HW_PXP_LUT_CTRL_RSVD1_SHIFT 11 +#define PXP_HW_PXP_LUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_LUT_CTRL_RSVD1_MASK) +#define PXP_HW_PXP_LUT_CTRL_OUT_MODE_MASK 0x30000u +#define PXP_HW_PXP_LUT_CTRL_OUT_MODE_SHIFT 16 +#define PXP_HW_PXP_LUT_CTRL_OUT_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_OUT_MODE_SHIFT))&PXP_HW_PXP_LUT_CTRL_OUT_MODE_MASK) +#define PXP_HW_PXP_LUT_CTRL_RSVD2_MASK 0xFC0000u +#define PXP_HW_PXP_LUT_CTRL_RSVD2_SHIFT 18 +#define PXP_HW_PXP_LUT_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_RSVD2_SHIFT))&PXP_HW_PXP_LUT_CTRL_RSVD2_MASK) +#define PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE_MASK 0x3000000u +#define PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE_SHIFT 24 +#define PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE_SHIFT))&PXP_HW_PXP_LUT_CTRL_LOOKUP_MODE_MASK) +#define PXP_HW_PXP_LUT_CTRL_RSVD3_MASK 0x7C000000u +#define PXP_HW_PXP_LUT_CTRL_RSVD3_SHIFT 26 +#define PXP_HW_PXP_LUT_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_CTRL_RSVD3_SHIFT))&PXP_HW_PXP_LUT_CTRL_RSVD3_MASK) +#define PXP_HW_PXP_LUT_CTRL_BYPASS_MASK 0x80000000u +#define PXP_HW_PXP_LUT_CTRL_BYPASS_SHIFT 31 +/* HW_PXP_LUT_ADDR Bit Fields */ +#define PXP_HW_PXP_LUT_ADDR_ADDR_MASK 0x3FFFu +#define PXP_HW_PXP_LUT_ADDR_ADDR_SHIFT 0 +#define PXP_HW_PXP_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_ADDR_ADDR_SHIFT))&PXP_HW_PXP_LUT_ADDR_ADDR_MASK) +#define PXP_HW_PXP_LUT_ADDR_RSVD1_MASK 0xC000u +#define PXP_HW_PXP_LUT_ADDR_RSVD1_SHIFT 14 +#define PXP_HW_PXP_LUT_ADDR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_ADDR_RSVD1_SHIFT))&PXP_HW_PXP_LUT_ADDR_RSVD1_MASK) +#define PXP_HW_PXP_LUT_ADDR_NUM_BYTES_MASK 0x7FFF0000u +#define PXP_HW_PXP_LUT_ADDR_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_LUT_ADDR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_ADDR_NUM_BYTES_SHIFT))&PXP_HW_PXP_LUT_ADDR_NUM_BYTES_MASK) +#define PXP_HW_PXP_LUT_ADDR_RSVD2_MASK 0x80000000u +#define PXP_HW_PXP_LUT_ADDR_RSVD2_SHIFT 31 +/* HW_PXP_LUT_DATA Bit Fields */ +#define PXP_HW_PXP_LUT_DATA_DATA_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_LUT_DATA_DATA_SHIFT 0 +#define PXP_HW_PXP_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_DATA_DATA_SHIFT))&PXP_HW_PXP_LUT_DATA_DATA_MASK) +/* HW_PXP_LUT_EXTMEM Bit Fields */ +#define PXP_HW_PXP_LUT_EXTMEM_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_LUT_EXTMEM_ADDR_SHIFT 0 +#define PXP_HW_PXP_LUT_EXTMEM_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_LUT_EXTMEM_ADDR_SHIFT))&PXP_HW_PXP_LUT_EXTMEM_ADDR_MASK) +/* HW_PXP_CFA Bit Fields */ +#define PXP_HW_PXP_CFA_DATA_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_CFA_DATA_SHIFT 0 +#define PXP_HW_PXP_CFA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CFA_DATA_SHIFT))&PXP_HW_PXP_CFA_DATA_MASK) /* HW_PXP_ALPHA_A_CTRL Bit Fields */ #define PXP_HW_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK 0x1u #define PXP_HW_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT 0 @@ -85499,14 +35020,14 @@ typedef struct { #define PXP_HW_PXP_IRQ_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_IRQ_RSVD1_SHIFT))&PXP_HW_PXP_IRQ_RSVD1_MASK) #define PXP_HW_PXP_IRQ_COMPRESS_DONE_IRQ_MASK 0x80000000u #define PXP_HW_PXP_IRQ_COMPRESS_DONE_IRQ_SHIFT 31 -/* NEXT Bit Fields */ -#define PXP_NEXT_ENABLED_MASK 0x1u -#define PXP_NEXT_ENABLED_SHIFT 0 -#define PXP_NEXT_RSVD_MASK 0x2u -#define PXP_NEXT_RSVD_SHIFT 1 -#define PXP_NEXT_POINTER_MASK 0xFFFFFFFCu -#define PXP_NEXT_POINTER_SHIFT 2 -#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x))<<PXP_NEXT_POINTER_SHIFT))&PXP_NEXT_POINTER_MASK) +/* HW_PXP_NEXT Bit Fields */ +#define PXP_HW_PXP_NEXT_ENABLED_MASK 0x1u +#define PXP_HW_PXP_NEXT_ENABLED_SHIFT 0 +#define PXP_HW_PXP_NEXT_RSVD_MASK 0x2u +#define PXP_HW_PXP_NEXT_RSVD_SHIFT 1 +#define PXP_HW_PXP_NEXT_POINTER_MASK 0xFFFFFFFCu +#define PXP_HW_PXP_NEXT_POINTER_SHIFT 2 +#define PXP_HW_PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_NEXT_POINTER_SHIFT))&PXP_HW_PXP_NEXT_POINTER_MASK) /* HW_PXP_INPUT_FETCH_CTRL_CH0 Bit Fields */ #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK 0x1u #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_CH_EN_SHIFT 0 @@ -87103,197 +36624,197 @@ typedef struct { #define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_MASK 0xFFFFFFFFu #define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_SHIFT 0 #define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_SHIFT))&PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_MASK) -/* HIST2_PARAM Bit Fields */ -#define PXP_HIST2_PARAM_VALUE0_MASK 0x3Fu -#define PXP_HIST2_PARAM_VALUE0_SHIFT 0 -#define PXP_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_VALUE0_SHIFT))&PXP_HIST2_PARAM_VALUE0_MASK) -#define PXP_HIST2_PARAM_RSVD0_MASK 0xC0u -#define PXP_HIST2_PARAM_RSVD0_SHIFT 6 -#define PXP_HIST2_PARAM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD0_SHIFT))&PXP_HIST2_PARAM_RSVD0_MASK) -#define PXP_HIST2_PARAM_VALUE1_MASK 0x3F00u -#define PXP_HIST2_PARAM_VALUE1_SHIFT 8 -#define PXP_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_VALUE1_SHIFT))&PXP_HIST2_PARAM_VALUE1_MASK) -#define PXP_HIST2_PARAM_RSVD1_MASK 0xC000u -#define PXP_HIST2_PARAM_RSVD1_SHIFT 14 -#define PXP_HIST2_PARAM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD1_SHIFT))&PXP_HIST2_PARAM_RSVD1_MASK) -#define PXP_HIST2_PARAM_RSVD_MASK 0xFFFF0000u -#define PXP_HIST2_PARAM_RSVD_SHIFT 16 -#define PXP_HIST2_PARAM_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD_SHIFT))&PXP_HIST2_PARAM_RSVD_MASK) -/* HIST4_PARAM Bit Fields */ -#define PXP_HIST4_PARAM_VALUE0_MASK 0x3Fu -#define PXP_HIST4_PARAM_VALUE0_SHIFT 0 -#define PXP_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE0_SHIFT))&PXP_HIST4_PARAM_VALUE0_MASK) -#define PXP_HIST4_PARAM_RSVD0_MASK 0xC0u -#define PXP_HIST4_PARAM_RSVD0_SHIFT 6 -#define PXP_HIST4_PARAM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD0_SHIFT))&PXP_HIST4_PARAM_RSVD0_MASK) -#define PXP_HIST4_PARAM_VALUE1_MASK 0x3F00u -#define PXP_HIST4_PARAM_VALUE1_SHIFT 8 -#define PXP_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE1_SHIFT))&PXP_HIST4_PARAM_VALUE1_MASK) -#define PXP_HIST4_PARAM_RSVD1_MASK 0xC000u -#define PXP_HIST4_PARAM_RSVD1_SHIFT 14 -#define PXP_HIST4_PARAM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD1_SHIFT))&PXP_HIST4_PARAM_RSVD1_MASK) -#define PXP_HIST4_PARAM_VALUE2_MASK 0x3F0000u -#define PXP_HIST4_PARAM_VALUE2_SHIFT 16 -#define PXP_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE2_SHIFT))&PXP_HIST4_PARAM_VALUE2_MASK) -#define PXP_HIST4_PARAM_RSVD2_MASK 0xC00000u -#define PXP_HIST4_PARAM_RSVD2_SHIFT 22 -#define PXP_HIST4_PARAM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD2_SHIFT))&PXP_HIST4_PARAM_RSVD2_MASK) -#define PXP_HIST4_PARAM_VALUE3_MASK 0x3F000000u -#define PXP_HIST4_PARAM_VALUE3_SHIFT 24 -#define PXP_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE3_SHIFT))&PXP_HIST4_PARAM_VALUE3_MASK) -#define PXP_HIST4_PARAM_RSVD3_MASK 0xC0000000u -#define PXP_HIST4_PARAM_RSVD3_SHIFT 30 -#define PXP_HIST4_PARAM_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD3_SHIFT))&PXP_HIST4_PARAM_RSVD3_MASK) -/* HIST8_PARAM0 Bit Fields */ -#define PXP_HIST8_PARAM0_VALUE0_MASK 0x3Fu -#define PXP_HIST8_PARAM0_VALUE0_SHIFT 0 -#define PXP_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE0_SHIFT))&PXP_HIST8_PARAM0_VALUE0_MASK) -#define PXP_HIST8_PARAM0_RSVD0_MASK 0xC0u -#define PXP_HIST8_PARAM0_RSVD0_SHIFT 6 -#define PXP_HIST8_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD0_SHIFT))&PXP_HIST8_PARAM0_RSVD0_MASK) -#define PXP_HIST8_PARAM0_VALUE1_MASK 0x3F00u -#define PXP_HIST8_PARAM0_VALUE1_SHIFT 8 -#define PXP_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE1_SHIFT))&PXP_HIST8_PARAM0_VALUE1_MASK) -#define PXP_HIST8_PARAM0_RSVD1_MASK 0xC000u -#define PXP_HIST8_PARAM0_RSVD1_SHIFT 14 -#define PXP_HIST8_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD1_SHIFT))&PXP_HIST8_PARAM0_RSVD1_MASK) -#define PXP_HIST8_PARAM0_VALUE2_MASK 0x3F0000u -#define PXP_HIST8_PARAM0_VALUE2_SHIFT 16 -#define PXP_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE2_SHIFT))&PXP_HIST8_PARAM0_VALUE2_MASK) -#define PXP_HIST8_PARAM0_RSVD2_MASK 0xC00000u -#define PXP_HIST8_PARAM0_RSVD2_SHIFT 22 -#define PXP_HIST8_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD2_SHIFT))&PXP_HIST8_PARAM0_RSVD2_MASK) -#define PXP_HIST8_PARAM0_VALUE3_MASK 0x3F000000u -#define PXP_HIST8_PARAM0_VALUE3_SHIFT 24 -#define PXP_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE3_SHIFT))&PXP_HIST8_PARAM0_VALUE3_MASK) -#define PXP_HIST8_PARAM0_RSVD3_MASK 0xC0000000u -#define PXP_HIST8_PARAM0_RSVD3_SHIFT 30 -#define PXP_HIST8_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD3_SHIFT))&PXP_HIST8_PARAM0_RSVD3_MASK) -/* HIST8_PARAM1 Bit Fields */ -#define PXP_HIST8_PARAM1_VALUE4_MASK 0x3Fu -#define PXP_HIST8_PARAM1_VALUE4_SHIFT 0 -#define PXP_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE4_SHIFT))&PXP_HIST8_PARAM1_VALUE4_MASK) -#define PXP_HIST8_PARAM1_RSVD4_MASK 0xC0u -#define PXP_HIST8_PARAM1_RSVD4_SHIFT 6 -#define PXP_HIST8_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD4_SHIFT))&PXP_HIST8_PARAM1_RSVD4_MASK) -#define PXP_HIST8_PARAM1_VALUE5_MASK 0x3F00u -#define PXP_HIST8_PARAM1_VALUE5_SHIFT 8 -#define PXP_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE5_SHIFT))&PXP_HIST8_PARAM1_VALUE5_MASK) -#define PXP_HIST8_PARAM1_RSVD5_MASK 0xC000u -#define PXP_HIST8_PARAM1_RSVD5_SHIFT 14 -#define PXP_HIST8_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD5_SHIFT))&PXP_HIST8_PARAM1_RSVD5_MASK) -#define PXP_HIST8_PARAM1_VALUE6_MASK 0x3F0000u -#define PXP_HIST8_PARAM1_VALUE6_SHIFT 16 -#define PXP_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE6_SHIFT))&PXP_HIST8_PARAM1_VALUE6_MASK) -#define PXP_HIST8_PARAM1_RSVD6_MASK 0xC00000u -#define PXP_HIST8_PARAM1_RSVD6_SHIFT 22 -#define PXP_HIST8_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD6_SHIFT))&PXP_HIST8_PARAM1_RSVD6_MASK) -#define PXP_HIST8_PARAM1_VALUE7_MASK 0x3F000000u -#define PXP_HIST8_PARAM1_VALUE7_SHIFT 24 -#define PXP_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE7_SHIFT))&PXP_HIST8_PARAM1_VALUE7_MASK) -#define PXP_HIST8_PARAM1_RSVD7_MASK 0xC0000000u -#define PXP_HIST8_PARAM1_RSVD7_SHIFT 30 -#define PXP_HIST8_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD7_SHIFT))&PXP_HIST8_PARAM1_RSVD7_MASK) -/* HIST16_PARAM0 Bit Fields */ -#define PXP_HIST16_PARAM0_VALUE0_MASK 0x3Fu -#define PXP_HIST16_PARAM0_VALUE0_SHIFT 0 -#define PXP_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE0_SHIFT))&PXP_HIST16_PARAM0_VALUE0_MASK) -#define PXP_HIST16_PARAM0_RSVD0_MASK 0xC0u -#define PXP_HIST16_PARAM0_RSVD0_SHIFT 6 -#define PXP_HIST16_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD0_SHIFT))&PXP_HIST16_PARAM0_RSVD0_MASK) -#define PXP_HIST16_PARAM0_VALUE1_MASK 0x3F00u -#define PXP_HIST16_PARAM0_VALUE1_SHIFT 8 -#define PXP_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE1_SHIFT))&PXP_HIST16_PARAM0_VALUE1_MASK) -#define PXP_HIST16_PARAM0_RSVD1_MASK 0xC000u -#define PXP_HIST16_PARAM0_RSVD1_SHIFT 14 -#define PXP_HIST16_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD1_SHIFT))&PXP_HIST16_PARAM0_RSVD1_MASK) -#define PXP_HIST16_PARAM0_VALUE2_MASK 0x3F0000u -#define PXP_HIST16_PARAM0_VALUE2_SHIFT 16 -#define PXP_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE2_SHIFT))&PXP_HIST16_PARAM0_VALUE2_MASK) -#define PXP_HIST16_PARAM0_RSVD2_MASK 0xC00000u -#define PXP_HIST16_PARAM0_RSVD2_SHIFT 22 -#define PXP_HIST16_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD2_SHIFT))&PXP_HIST16_PARAM0_RSVD2_MASK) -#define PXP_HIST16_PARAM0_VALUE3_MASK 0x3F000000u -#define PXP_HIST16_PARAM0_VALUE3_SHIFT 24 -#define PXP_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE3_SHIFT))&PXP_HIST16_PARAM0_VALUE3_MASK) -#define PXP_HIST16_PARAM0_RSVD3_MASK 0xC0000000u -#define PXP_HIST16_PARAM0_RSVD3_SHIFT 30 -#define PXP_HIST16_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD3_SHIFT))&PXP_HIST16_PARAM0_RSVD3_MASK) -/* HIST16_PARAM1 Bit Fields */ -#define PXP_HIST16_PARAM1_VALUE4_MASK 0x3Fu -#define PXP_HIST16_PARAM1_VALUE4_SHIFT 0 -#define PXP_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE4_SHIFT))&PXP_HIST16_PARAM1_VALUE4_MASK) -#define PXP_HIST16_PARAM1_RSVD4_MASK 0xC0u -#define PXP_HIST16_PARAM1_RSVD4_SHIFT 6 -#define PXP_HIST16_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD4_SHIFT))&PXP_HIST16_PARAM1_RSVD4_MASK) -#define PXP_HIST16_PARAM1_VALUE5_MASK 0x3F00u -#define PXP_HIST16_PARAM1_VALUE5_SHIFT 8 -#define PXP_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE5_SHIFT))&PXP_HIST16_PARAM1_VALUE5_MASK) -#define PXP_HIST16_PARAM1_RSVD5_MASK 0xC000u -#define PXP_HIST16_PARAM1_RSVD5_SHIFT 14 -#define PXP_HIST16_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD5_SHIFT))&PXP_HIST16_PARAM1_RSVD5_MASK) -#define PXP_HIST16_PARAM1_VALUE6_MASK 0x3F0000u -#define PXP_HIST16_PARAM1_VALUE6_SHIFT 16 -#define PXP_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE6_SHIFT))&PXP_HIST16_PARAM1_VALUE6_MASK) -#define PXP_HIST16_PARAM1_RSVD6_MASK 0xC00000u -#define PXP_HIST16_PARAM1_RSVD6_SHIFT 22 -#define PXP_HIST16_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD6_SHIFT))&PXP_HIST16_PARAM1_RSVD6_MASK) -#define PXP_HIST16_PARAM1_VALUE7_MASK 0x3F000000u -#define PXP_HIST16_PARAM1_VALUE7_SHIFT 24 -#define PXP_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE7_SHIFT))&PXP_HIST16_PARAM1_VALUE7_MASK) -#define PXP_HIST16_PARAM1_RSVD7_MASK 0xC0000000u -#define PXP_HIST16_PARAM1_RSVD7_SHIFT 30 -#define PXP_HIST16_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD7_SHIFT))&PXP_HIST16_PARAM1_RSVD7_MASK) -/* HIST16_PARAM2 Bit Fields */ -#define PXP_HIST16_PARAM2_VALUE8_MASK 0x3Fu -#define PXP_HIST16_PARAM2_VALUE8_SHIFT 0 -#define PXP_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE8_SHIFT))&PXP_HIST16_PARAM2_VALUE8_MASK) -#define PXP_HIST16_PARAM2_RSVD8_MASK 0xC0u -#define PXP_HIST16_PARAM2_RSVD8_SHIFT 6 -#define PXP_HIST16_PARAM2_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD8_SHIFT))&PXP_HIST16_PARAM2_RSVD8_MASK) -#define PXP_HIST16_PARAM2_VALUE9_MASK 0x3F00u -#define PXP_HIST16_PARAM2_VALUE9_SHIFT 8 -#define PXP_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE9_SHIFT))&PXP_HIST16_PARAM2_VALUE9_MASK) -#define PXP_HIST16_PARAM2_RSVD9_MASK 0xC000u -#define PXP_HIST16_PARAM2_RSVD9_SHIFT 14 -#define PXP_HIST16_PARAM2_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD9_SHIFT))&PXP_HIST16_PARAM2_RSVD9_MASK) -#define PXP_HIST16_PARAM2_VALUE10_MASK 0x3F0000u -#define PXP_HIST16_PARAM2_VALUE10_SHIFT 16 -#define PXP_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE10_SHIFT))&PXP_HIST16_PARAM2_VALUE10_MASK) -#define PXP_HIST16_PARAM2_RSVD10_MASK 0xC00000u -#define PXP_HIST16_PARAM2_RSVD10_SHIFT 22 -#define PXP_HIST16_PARAM2_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD10_SHIFT))&PXP_HIST16_PARAM2_RSVD10_MASK) -#define PXP_HIST16_PARAM2_VALUE11_MASK 0x3F000000u -#define PXP_HIST16_PARAM2_VALUE11_SHIFT 24 -#define PXP_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE11_SHIFT))&PXP_HIST16_PARAM2_VALUE11_MASK) -#define PXP_HIST16_PARAM2_RSVD11_MASK 0xC0000000u -#define PXP_HIST16_PARAM2_RSVD11_SHIFT 30 -#define PXP_HIST16_PARAM2_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD11_SHIFT))&PXP_HIST16_PARAM2_RSVD11_MASK) -/* HIST16_PARAM3 Bit Fields */ -#define PXP_HIST16_PARAM3_VALUE12_MASK 0x3Fu -#define PXP_HIST16_PARAM3_VALUE12_SHIFT 0 -#define PXP_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE12_SHIFT))&PXP_HIST16_PARAM3_VALUE12_MASK) -#define PXP_HIST16_PARAM3_RSVD12_MASK 0xC0u -#define PXP_HIST16_PARAM3_RSVD12_SHIFT 6 -#define PXP_HIST16_PARAM3_RSVD12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD12_SHIFT))&PXP_HIST16_PARAM3_RSVD12_MASK) -#define PXP_HIST16_PARAM3_VALUE13_MASK 0x3F00u -#define PXP_HIST16_PARAM3_VALUE13_SHIFT 8 -#define PXP_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE13_SHIFT))&PXP_HIST16_PARAM3_VALUE13_MASK) -#define PXP_HIST16_PARAM3_RSVD13_MASK 0xC000u -#define PXP_HIST16_PARAM3_RSVD13_SHIFT 14 -#define PXP_HIST16_PARAM3_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD13_SHIFT))&PXP_HIST16_PARAM3_RSVD13_MASK) -#define PXP_HIST16_PARAM3_VALUE14_MASK 0x3F0000u -#define PXP_HIST16_PARAM3_VALUE14_SHIFT 16 -#define PXP_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE14_SHIFT))&PXP_HIST16_PARAM3_VALUE14_MASK) -#define PXP_HIST16_PARAM3_RSVD14_MASK 0xC00000u -#define PXP_HIST16_PARAM3_RSVD14_SHIFT 22 -#define PXP_HIST16_PARAM3_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD14_SHIFT))&PXP_HIST16_PARAM3_RSVD14_MASK) -#define PXP_HIST16_PARAM3_VALUE15_MASK 0x3F000000u -#define PXP_HIST16_PARAM3_VALUE15_SHIFT 24 -#define PXP_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE15_SHIFT))&PXP_HIST16_PARAM3_VALUE15_MASK) -#define PXP_HIST16_PARAM3_RSVD15_MASK 0xC0000000u -#define PXP_HIST16_PARAM3_RSVD15_SHIFT 30 -#define PXP_HIST16_PARAM3_RSVD15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD15_SHIFT))&PXP_HIST16_PARAM3_RSVD15_MASK) +/* HW_PXP_HIST2_PARAM Bit Fields */ +#define PXP_HW_PXP_HIST2_PARAM_VALUE0_MASK 0x3Fu +#define PXP_HW_PXP_HIST2_PARAM_VALUE0_SHIFT 0 +#define PXP_HW_PXP_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_VALUE0_SHIFT))&PXP_HW_PXP_HIST2_PARAM_VALUE0_MASK) +#define PXP_HW_PXP_HIST2_PARAM_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_HIST2_PARAM_RSVD0_SHIFT 6 +#define PXP_HW_PXP_HIST2_PARAM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_RSVD0_SHIFT))&PXP_HW_PXP_HIST2_PARAM_RSVD0_MASK) +#define PXP_HW_PXP_HIST2_PARAM_VALUE1_MASK 0x3F00u +#define PXP_HW_PXP_HIST2_PARAM_VALUE1_SHIFT 8 +#define PXP_HW_PXP_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_VALUE1_SHIFT))&PXP_HW_PXP_HIST2_PARAM_VALUE1_MASK) +#define PXP_HW_PXP_HIST2_PARAM_RSVD1_MASK 0xC000u +#define PXP_HW_PXP_HIST2_PARAM_RSVD1_SHIFT 14 +#define PXP_HW_PXP_HIST2_PARAM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_RSVD1_SHIFT))&PXP_HW_PXP_HIST2_PARAM_RSVD1_MASK) +#define PXP_HW_PXP_HIST2_PARAM_RSVD_MASK 0xFFFF0000u +#define PXP_HW_PXP_HIST2_PARAM_RSVD_SHIFT 16 +#define PXP_HW_PXP_HIST2_PARAM_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST2_PARAM_RSVD_SHIFT))&PXP_HW_PXP_HIST2_PARAM_RSVD_MASK) +/* HW_PXP_HIST4_PARAM Bit Fields */ +#define PXP_HW_PXP_HIST4_PARAM_VALUE0_MASK 0x3Fu +#define PXP_HW_PXP_HIST4_PARAM_VALUE0_SHIFT 0 +#define PXP_HW_PXP_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_VALUE0_SHIFT))&PXP_HW_PXP_HIST4_PARAM_VALUE0_MASK) +#define PXP_HW_PXP_HIST4_PARAM_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_HIST4_PARAM_RSVD0_SHIFT 6 +#define PXP_HW_PXP_HIST4_PARAM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_RSVD0_SHIFT))&PXP_HW_PXP_HIST4_PARAM_RSVD0_MASK) +#define PXP_HW_PXP_HIST4_PARAM_VALUE1_MASK 0x3F00u +#define PXP_HW_PXP_HIST4_PARAM_VALUE1_SHIFT 8 +#define PXP_HW_PXP_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_VALUE1_SHIFT))&PXP_HW_PXP_HIST4_PARAM_VALUE1_MASK) +#define PXP_HW_PXP_HIST4_PARAM_RSVD1_MASK 0xC000u +#define PXP_HW_PXP_HIST4_PARAM_RSVD1_SHIFT 14 +#define PXP_HW_PXP_HIST4_PARAM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_RSVD1_SHIFT))&PXP_HW_PXP_HIST4_PARAM_RSVD1_MASK) +#define PXP_HW_PXP_HIST4_PARAM_VALUE2_MASK 0x3F0000u +#define PXP_HW_PXP_HIST4_PARAM_VALUE2_SHIFT 16 +#define PXP_HW_PXP_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_VALUE2_SHIFT))&PXP_HW_PXP_HIST4_PARAM_VALUE2_MASK) +#define PXP_HW_PXP_HIST4_PARAM_RSVD2_MASK 0xC00000u +#define PXP_HW_PXP_HIST4_PARAM_RSVD2_SHIFT 22 +#define PXP_HW_PXP_HIST4_PARAM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_RSVD2_SHIFT))&PXP_HW_PXP_HIST4_PARAM_RSVD2_MASK) +#define PXP_HW_PXP_HIST4_PARAM_VALUE3_MASK 0x3F000000u +#define PXP_HW_PXP_HIST4_PARAM_VALUE3_SHIFT 24 +#define PXP_HW_PXP_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_VALUE3_SHIFT))&PXP_HW_PXP_HIST4_PARAM_VALUE3_MASK) +#define PXP_HW_PXP_HIST4_PARAM_RSVD3_MASK 0xC0000000u +#define PXP_HW_PXP_HIST4_PARAM_RSVD3_SHIFT 30 +#define PXP_HW_PXP_HIST4_PARAM_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST4_PARAM_RSVD3_SHIFT))&PXP_HW_PXP_HIST4_PARAM_RSVD3_MASK) +/* HW_PXP_HIST8_PARAM0 Bit Fields */ +#define PXP_HW_PXP_HIST8_PARAM0_VALUE0_MASK 0x3Fu +#define PXP_HW_PXP_HIST8_PARAM0_VALUE0_SHIFT 0 +#define PXP_HW_PXP_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_VALUE0_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_VALUE0_MASK) +#define PXP_HW_PXP_HIST8_PARAM0_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_HIST8_PARAM0_RSVD0_SHIFT 6 +#define PXP_HW_PXP_HIST8_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_RSVD0_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_RSVD0_MASK) +#define PXP_HW_PXP_HIST8_PARAM0_VALUE1_MASK 0x3F00u +#define PXP_HW_PXP_HIST8_PARAM0_VALUE1_SHIFT 8 +#define PXP_HW_PXP_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_VALUE1_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_VALUE1_MASK) +#define PXP_HW_PXP_HIST8_PARAM0_RSVD1_MASK 0xC000u +#define PXP_HW_PXP_HIST8_PARAM0_RSVD1_SHIFT 14 +#define PXP_HW_PXP_HIST8_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_RSVD1_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_RSVD1_MASK) +#define PXP_HW_PXP_HIST8_PARAM0_VALUE2_MASK 0x3F0000u +#define PXP_HW_PXP_HIST8_PARAM0_VALUE2_SHIFT 16 +#define PXP_HW_PXP_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_VALUE2_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_VALUE2_MASK) +#define PXP_HW_PXP_HIST8_PARAM0_RSVD2_MASK 0xC00000u +#define PXP_HW_PXP_HIST8_PARAM0_RSVD2_SHIFT 22 +#define PXP_HW_PXP_HIST8_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_RSVD2_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_RSVD2_MASK) +#define PXP_HW_PXP_HIST8_PARAM0_VALUE3_MASK 0x3F000000u +#define PXP_HW_PXP_HIST8_PARAM0_VALUE3_SHIFT 24 +#define PXP_HW_PXP_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_VALUE3_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_VALUE3_MASK) +#define PXP_HW_PXP_HIST8_PARAM0_RSVD3_MASK 0xC0000000u +#define PXP_HW_PXP_HIST8_PARAM0_RSVD3_SHIFT 30 +#define PXP_HW_PXP_HIST8_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM0_RSVD3_SHIFT))&PXP_HW_PXP_HIST8_PARAM0_RSVD3_MASK) +/* HW_PXP_HIST8_PARAM1 Bit Fields */ +#define PXP_HW_PXP_HIST8_PARAM1_VALUE4_MASK 0x3Fu +#define PXP_HW_PXP_HIST8_PARAM1_VALUE4_SHIFT 0 +#define PXP_HW_PXP_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_VALUE4_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_VALUE4_MASK) +#define PXP_HW_PXP_HIST8_PARAM1_RSVD4_MASK 0xC0u +#define PXP_HW_PXP_HIST8_PARAM1_RSVD4_SHIFT 6 +#define PXP_HW_PXP_HIST8_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_RSVD4_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_RSVD4_MASK) +#define PXP_HW_PXP_HIST8_PARAM1_VALUE5_MASK 0x3F00u +#define PXP_HW_PXP_HIST8_PARAM1_VALUE5_SHIFT 8 +#define PXP_HW_PXP_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_VALUE5_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_VALUE5_MASK) +#define PXP_HW_PXP_HIST8_PARAM1_RSVD5_MASK 0xC000u +#define PXP_HW_PXP_HIST8_PARAM1_RSVD5_SHIFT 14 +#define PXP_HW_PXP_HIST8_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_RSVD5_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_RSVD5_MASK) +#define PXP_HW_PXP_HIST8_PARAM1_VALUE6_MASK 0x3F0000u +#define PXP_HW_PXP_HIST8_PARAM1_VALUE6_SHIFT 16 +#define PXP_HW_PXP_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_VALUE6_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_VALUE6_MASK) +#define PXP_HW_PXP_HIST8_PARAM1_RSVD6_MASK 0xC00000u +#define PXP_HW_PXP_HIST8_PARAM1_RSVD6_SHIFT 22 +#define PXP_HW_PXP_HIST8_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_RSVD6_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_RSVD6_MASK) +#define PXP_HW_PXP_HIST8_PARAM1_VALUE7_MASK 0x3F000000u +#define PXP_HW_PXP_HIST8_PARAM1_VALUE7_SHIFT 24 +#define PXP_HW_PXP_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_VALUE7_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_VALUE7_MASK) +#define PXP_HW_PXP_HIST8_PARAM1_RSVD7_MASK 0xC0000000u +#define PXP_HW_PXP_HIST8_PARAM1_RSVD7_SHIFT 30 +#define PXP_HW_PXP_HIST8_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST8_PARAM1_RSVD7_SHIFT))&PXP_HW_PXP_HIST8_PARAM1_RSVD7_MASK) +/* HW_PXP_HIST16_PARAM0 Bit Fields */ +#define PXP_HW_PXP_HIST16_PARAM0_VALUE0_MASK 0x3Fu +#define PXP_HW_PXP_HIST16_PARAM0_VALUE0_SHIFT 0 +#define PXP_HW_PXP_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_VALUE0_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_VALUE0_MASK) +#define PXP_HW_PXP_HIST16_PARAM0_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_HIST16_PARAM0_RSVD0_SHIFT 6 +#define PXP_HW_PXP_HIST16_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_RSVD0_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_RSVD0_MASK) +#define PXP_HW_PXP_HIST16_PARAM0_VALUE1_MASK 0x3F00u +#define PXP_HW_PXP_HIST16_PARAM0_VALUE1_SHIFT 8 +#define PXP_HW_PXP_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_VALUE1_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_VALUE1_MASK) +#define PXP_HW_PXP_HIST16_PARAM0_RSVD1_MASK 0xC000u +#define PXP_HW_PXP_HIST16_PARAM0_RSVD1_SHIFT 14 +#define PXP_HW_PXP_HIST16_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_RSVD1_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_RSVD1_MASK) +#define PXP_HW_PXP_HIST16_PARAM0_VALUE2_MASK 0x3F0000u +#define PXP_HW_PXP_HIST16_PARAM0_VALUE2_SHIFT 16 +#define PXP_HW_PXP_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_VALUE2_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_VALUE2_MASK) +#define PXP_HW_PXP_HIST16_PARAM0_RSVD2_MASK 0xC00000u +#define PXP_HW_PXP_HIST16_PARAM0_RSVD2_SHIFT 22 +#define PXP_HW_PXP_HIST16_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_RSVD2_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_RSVD2_MASK) +#define PXP_HW_PXP_HIST16_PARAM0_VALUE3_MASK 0x3F000000u +#define PXP_HW_PXP_HIST16_PARAM0_VALUE3_SHIFT 24 +#define PXP_HW_PXP_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_VALUE3_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_VALUE3_MASK) +#define PXP_HW_PXP_HIST16_PARAM0_RSVD3_MASK 0xC0000000u +#define PXP_HW_PXP_HIST16_PARAM0_RSVD3_SHIFT 30 +#define PXP_HW_PXP_HIST16_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM0_RSVD3_SHIFT))&PXP_HW_PXP_HIST16_PARAM0_RSVD3_MASK) +/* HW_PXP_HIST16_PARAM1 Bit Fields */ +#define PXP_HW_PXP_HIST16_PARAM1_VALUE4_MASK 0x3Fu +#define PXP_HW_PXP_HIST16_PARAM1_VALUE4_SHIFT 0 +#define PXP_HW_PXP_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_VALUE4_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_VALUE4_MASK) +#define PXP_HW_PXP_HIST16_PARAM1_RSVD4_MASK 0xC0u +#define PXP_HW_PXP_HIST16_PARAM1_RSVD4_SHIFT 6 +#define PXP_HW_PXP_HIST16_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_RSVD4_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_RSVD4_MASK) +#define PXP_HW_PXP_HIST16_PARAM1_VALUE5_MASK 0x3F00u +#define PXP_HW_PXP_HIST16_PARAM1_VALUE5_SHIFT 8 +#define PXP_HW_PXP_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_VALUE5_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_VALUE5_MASK) +#define PXP_HW_PXP_HIST16_PARAM1_RSVD5_MASK 0xC000u +#define PXP_HW_PXP_HIST16_PARAM1_RSVD5_SHIFT 14 +#define PXP_HW_PXP_HIST16_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_RSVD5_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_RSVD5_MASK) +#define PXP_HW_PXP_HIST16_PARAM1_VALUE6_MASK 0x3F0000u +#define PXP_HW_PXP_HIST16_PARAM1_VALUE6_SHIFT 16 +#define PXP_HW_PXP_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_VALUE6_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_VALUE6_MASK) +#define PXP_HW_PXP_HIST16_PARAM1_RSVD6_MASK 0xC00000u +#define PXP_HW_PXP_HIST16_PARAM1_RSVD6_SHIFT 22 +#define PXP_HW_PXP_HIST16_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_RSVD6_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_RSVD6_MASK) +#define PXP_HW_PXP_HIST16_PARAM1_VALUE7_MASK 0x3F000000u +#define PXP_HW_PXP_HIST16_PARAM1_VALUE7_SHIFT 24 +#define PXP_HW_PXP_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_VALUE7_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_VALUE7_MASK) +#define PXP_HW_PXP_HIST16_PARAM1_RSVD7_MASK 0xC0000000u +#define PXP_HW_PXP_HIST16_PARAM1_RSVD7_SHIFT 30 +#define PXP_HW_PXP_HIST16_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM1_RSVD7_SHIFT))&PXP_HW_PXP_HIST16_PARAM1_RSVD7_MASK) +/* HW_PXP_HIST16_PARAM2 Bit Fields */ +#define PXP_HW_PXP_HIST16_PARAM2_VALUE8_MASK 0x3Fu +#define PXP_HW_PXP_HIST16_PARAM2_VALUE8_SHIFT 0 +#define PXP_HW_PXP_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_VALUE8_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_VALUE8_MASK) +#define PXP_HW_PXP_HIST16_PARAM2_RSVD8_MASK 0xC0u +#define PXP_HW_PXP_HIST16_PARAM2_RSVD8_SHIFT 6 +#define PXP_HW_PXP_HIST16_PARAM2_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_RSVD8_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_RSVD8_MASK) +#define PXP_HW_PXP_HIST16_PARAM2_VALUE9_MASK 0x3F00u +#define PXP_HW_PXP_HIST16_PARAM2_VALUE9_SHIFT 8 +#define PXP_HW_PXP_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_VALUE9_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_VALUE9_MASK) +#define PXP_HW_PXP_HIST16_PARAM2_RSVD9_MASK 0xC000u +#define PXP_HW_PXP_HIST16_PARAM2_RSVD9_SHIFT 14 +#define PXP_HW_PXP_HIST16_PARAM2_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_RSVD9_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_RSVD9_MASK) +#define PXP_HW_PXP_HIST16_PARAM2_VALUE10_MASK 0x3F0000u +#define PXP_HW_PXP_HIST16_PARAM2_VALUE10_SHIFT 16 +#define PXP_HW_PXP_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_VALUE10_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_VALUE10_MASK) +#define PXP_HW_PXP_HIST16_PARAM2_RSVD10_MASK 0xC00000u +#define PXP_HW_PXP_HIST16_PARAM2_RSVD10_SHIFT 22 +#define PXP_HW_PXP_HIST16_PARAM2_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_RSVD10_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_RSVD10_MASK) +#define PXP_HW_PXP_HIST16_PARAM2_VALUE11_MASK 0x3F000000u +#define PXP_HW_PXP_HIST16_PARAM2_VALUE11_SHIFT 24 +#define PXP_HW_PXP_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_VALUE11_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_VALUE11_MASK) +#define PXP_HW_PXP_HIST16_PARAM2_RSVD11_MASK 0xC0000000u +#define PXP_HW_PXP_HIST16_PARAM2_RSVD11_SHIFT 30 +#define PXP_HW_PXP_HIST16_PARAM2_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM2_RSVD11_SHIFT))&PXP_HW_PXP_HIST16_PARAM2_RSVD11_MASK) +/* HW_PXP_HIST16_PARAM3 Bit Fields */ +#define PXP_HW_PXP_HIST16_PARAM3_VALUE12_MASK 0x3Fu +#define PXP_HW_PXP_HIST16_PARAM3_VALUE12_SHIFT 0 +#define PXP_HW_PXP_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_VALUE12_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_VALUE12_MASK) +#define PXP_HW_PXP_HIST16_PARAM3_RSVD12_MASK 0xC0u +#define PXP_HW_PXP_HIST16_PARAM3_RSVD12_SHIFT 6 +#define PXP_HW_PXP_HIST16_PARAM3_RSVD12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_RSVD12_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_RSVD12_MASK) +#define PXP_HW_PXP_HIST16_PARAM3_VALUE13_MASK 0x3F00u +#define PXP_HW_PXP_HIST16_PARAM3_VALUE13_SHIFT 8 +#define PXP_HW_PXP_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_VALUE13_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_VALUE13_MASK) +#define PXP_HW_PXP_HIST16_PARAM3_RSVD13_MASK 0xC000u +#define PXP_HW_PXP_HIST16_PARAM3_RSVD13_SHIFT 14 +#define PXP_HW_PXP_HIST16_PARAM3_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_RSVD13_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_RSVD13_MASK) +#define PXP_HW_PXP_HIST16_PARAM3_VALUE14_MASK 0x3F0000u +#define PXP_HW_PXP_HIST16_PARAM3_VALUE14_SHIFT 16 +#define PXP_HW_PXP_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_VALUE14_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_VALUE14_MASK) +#define PXP_HW_PXP_HIST16_PARAM3_RSVD14_MASK 0xC00000u +#define PXP_HW_PXP_HIST16_PARAM3_RSVD14_SHIFT 22 +#define PXP_HW_PXP_HIST16_PARAM3_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_RSVD14_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_RSVD14_MASK) +#define PXP_HW_PXP_HIST16_PARAM3_VALUE15_MASK 0x3F000000u +#define PXP_HW_PXP_HIST16_PARAM3_VALUE15_SHIFT 24 +#define PXP_HW_PXP_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_VALUE15_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_VALUE15_MASK) +#define PXP_HW_PXP_HIST16_PARAM3_RSVD15_MASK 0xC0000000u +#define PXP_HW_PXP_HIST16_PARAM3_RSVD15_SHIFT 30 +#define PXP_HW_PXP_HIST16_PARAM3_RSVD15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST16_PARAM3_RSVD15_SHIFT))&PXP_HW_PXP_HIST16_PARAM3_RSVD15_MASK) /* HW_PXP_HIST32_PARAM0 Bit Fields */ #define PXP_HW_PXP_HIST32_PARAM0_VALUE0_MASK 0x3Fu #define PXP_HW_PXP_HIST32_PARAM0_VALUE0_SHIFT 0 @@ -87810,18 +37331,16 @@ typedef struct { * @} */ /* end of group PXP_Register_Masks */ - /* PXP - Peripheral instance base addresses */ /** Peripheral PXP base address */ #define PXP_BASE (0x30700000u) /** Peripheral PXP base pointer */ #define PXP ((PXP_Type *)PXP_BASE) #define PXP_BASE_PTR (PXP) -/** Array initializer of PXP peripheral base adresses */ +/** Array initializer of PXP peripheral base addresses */ #define PXP_BASE_ADDRS { PXP_BASE } /** Array initializer of PXP peripheral base pointers */ #define PXP_BASE_PTRS { PXP } - /* ---------------------------------------------------------------------------- -- PXP - Register accessor macros ---------------------------------------------------------------------------- */ @@ -87834,47 +37353,47 @@ typedef struct { /* PXP - Register instance definitions */ /* PXP */ -#define PXP_HW_PXP_CTRL PXP_CTRL_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_STAT PXP_STAT_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_CTRL PXP_OUT_CTRL_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_BUF PXP_OUT_BUF_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_BUF2 PXP_OUT_BUF2_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_PITCH PXP_OUT_PITCH_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_LRC PXP_OUT_LRC_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_PS_ULC PXP_OUT_PS_ULC_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_PS_LRC PXP_OUT_PS_LRC_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_AS_ULC PXP_OUT_AS_ULC_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_OUT_AS_LRC PXP_OUT_AS_LRC_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_PS_CTRL PXP_PS_CTRL_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_PS_BUF PXP_PS_BUF_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_PS_UBUF PXP_PS_UBUF_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_PS_VBUF PXP_PS_VBUF_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_PS_PITCH PXP_PS_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CTRL PXP_HW_PXP_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_STAT PXP_HW_PXP_STAT_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_CTRL PXP_HW_PXP_OUT_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_BUF PXP_HW_PXP_OUT_BUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_BUF2 PXP_HW_PXP_OUT_BUF2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_PITCH PXP_HW_PXP_OUT_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_LRC PXP_HW_PXP_OUT_LRC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_PS_ULC PXP_HW_PXP_OUT_PS_ULC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_PS_LRC PXP_HW_PXP_OUT_PS_LRC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_AS_ULC PXP_HW_PXP_OUT_AS_ULC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_AS_LRC PXP_HW_PXP_OUT_AS_LRC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_CTRL PXP_HW_PXP_PS_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_BUF PXP_HW_PXP_PS_BUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_UBUF PXP_HW_PXP_PS_UBUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_VBUF PXP_HW_PXP_PS_VBUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_PITCH PXP_HW_PXP_PS_PITCH_REG(PXP_BASE_PTR) #define PXP_HW_PXP_PS_BACKGROUND_0 PXP_HW_PXP_PS_BACKGROUND_0_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_PS_SCALE PXP_PS_SCALE_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_PS_OFFSET PXP_PS_OFFSET_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_SCALE PXP_HW_PXP_PS_SCALE_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_OFFSET PXP_HW_PXP_PS_OFFSET_REG(PXP_BASE_PTR) #define PXP_HW_PXP_PS_CLRKEYLOW_0 PXP_HW_PXP_PS_CLRKEYLOW_0_REG(PXP_BASE_PTR) #define PXP_HW_PXP_PS_CLRKEYHIGH_0 PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_AS_CTRL PXP_AS_CTRL_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_AS_BUF PXP_AS_BUF_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_AS_PITCH PXP_AS_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_CTRL PXP_HW_PXP_AS_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_BUF PXP_HW_PXP_AS_BUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_PITCH PXP_HW_PXP_AS_PITCH_REG(PXP_BASE_PTR) #define PXP_HW_PXP_AS_CLRKEYLOW_0 PXP_HW_PXP_AS_CLRKEYLOW_0_REG(PXP_BASE_PTR) #define PXP_HW_PXP_AS_CLRKEYHIGH_0 PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC1_COEF0 PXP_CSC1_COEF0_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC1_COEF1 PXP_CSC1_COEF1_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC1_COEF2 PXP_CSC1_COEF2_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC2_CTRL PXP_CSC2_CTRL_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC2_COEF0 PXP_CSC2_COEF0_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC2_COEF1 PXP_CSC2_COEF1_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC2_COEF2 PXP_CSC2_COEF2_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC2_COEF3 PXP_CSC2_COEF3_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC2_COEF4 PXP_CSC2_COEF4_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CSC2_COEF5 PXP_CSC2_COEF5_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_LUT_CTRL PXP_LUT_CTRL_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_LUT_ADDR PXP_LUT_ADDR_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_LUT_DATA PXP_LUT_DATA_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_LUT_EXTMEM PXP_LUT_EXTMEM_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_CFA PXP_CFA_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC1_COEF0 PXP_HW_PXP_CSC1_COEF0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC1_COEF1 PXP_HW_PXP_CSC1_COEF1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC1_COEF2 PXP_HW_PXP_CSC1_COEF2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_CTRL PXP_HW_PXP_CSC2_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF0 PXP_HW_PXP_CSC2_COEF0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF1 PXP_HW_PXP_CSC2_COEF1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF2 PXP_HW_PXP_CSC2_COEF2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF3 PXP_HW_PXP_CSC2_COEF3_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF4 PXP_HW_PXP_CSC2_COEF4_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF5 PXP_HW_PXP_CSC2_COEF5_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_LUT_CTRL PXP_HW_PXP_LUT_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_LUT_ADDR PXP_HW_PXP_LUT_ADDR_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_LUT_DATA PXP_HW_PXP_LUT_DATA_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_LUT_EXTMEM PXP_HW_PXP_LUT_EXTMEM_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CFA PXP_HW_PXP_CFA_REG(PXP_BASE_PTR) #define PXP_HW_PXP_ALPHA_A_CTRL PXP_HW_PXP_ALPHA_A_CTRL_REG(PXP_BASE_PTR) #define PXP_HW_PXP_ALPHA_B_CTRL PXP_HW_PXP_ALPHA_B_CTRL_REG(PXP_BASE_PTR) #define PXP_HW_PXP_ALPHA_B_CTRL_1 PXP_HW_PXP_ALPHA_B_CTRL_1_REG(PXP_BASE_PTR) @@ -87893,7 +37412,7 @@ typedef struct { #define PXP_HW_PXP_INIT_MEM_DATA_HIGH PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(PXP_BASE_PTR) #define PXP_HW_PXP_IRQ_MASK PXP_HW_PXP_IRQ_MASK_REG(PXP_BASE_PTR) #define PXP_HW_PXP_IRQ PXP_HW_PXP_IRQ_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_NEXT PXP_NEXT_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_NEXT PXP_HW_PXP_NEXT_REG(PXP_BASE_PTR) #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0 PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(PXP_BASE_PTR) #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1 PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(PXP_BASE_PTR) #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0 PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(PXP_BASE_PTR) @@ -88033,14 +37552,14 @@ typedef struct { #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(PXP_BASE_PTR) #define PXP_HW_PXP_HIST_B_RAW_STAT0 PXP_HW_PXP_HIST_B_RAW_STAT0_REG(PXP_BASE_PTR) #define PXP_HW_PXP_HIST_B_RAW_STAT1 PXP_HW_PXP_HIST_B_RAW_STAT1_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_HIST2_PARAM PXP_HIST2_PARAM_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_HIST4_PARAM PXP_HIST4_PARAM_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_HIST8_PARAM0 PXP_HIST8_PARAM0_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_HIST8_PARAM1 PXP_HIST8_PARAM1_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_HIST16_PARAM0 PXP_HIST16_PARAM0_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_HIST16_PARAM1 PXP_HIST16_PARAM1_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_HIST16_PARAM2 PXP_HIST16_PARAM2_REG(PXP_BASE_PTR) -#define PXP_HW_PXP_HIST16_PARAM3 PXP_HIST16_PARAM3_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST2_PARAM PXP_HW_PXP_HIST2_PARAM_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST4_PARAM PXP_HW_PXP_HIST4_PARAM_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST8_PARAM0 PXP_HW_PXP_HIST8_PARAM0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST8_PARAM1 PXP_HW_PXP_HIST8_PARAM1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST16_PARAM0 PXP_HW_PXP_HIST16_PARAM0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST16_PARAM1 PXP_HW_PXP_HIST16_PARAM1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST16_PARAM2 PXP_HW_PXP_HIST16_PARAM2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST16_PARAM3 PXP_HW_PXP_HIST16_PARAM3_REG(PXP_BASE_PTR) #define PXP_HW_PXP_HIST32_PARAM0 PXP_HW_PXP_HIST32_PARAM0_REG(PXP_BASE_PTR) #define PXP_HW_PXP_HIST32_PARAM1 PXP_HW_PXP_HIST32_PARAM1_REG(PXP_BASE_PTR) #define PXP_HW_PXP_HIST32_PARAM2 PXP_HW_PXP_HIST32_PARAM2_REG(PXP_BASE_PTR) @@ -88070,7 +37589,6 @@ typedef struct { #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1 PXP_HW_PXP_HANDSHAKE_DONE_MUX1_REG(PXP_BASE_PTR) #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH PXP_HW_PXP_HANDSHAKE_CPU_FETCH_REG(PXP_BASE_PTR) #define PXP_HW_PXP_HANDSHAKE_CPU_STORE PXP_HW_PXP_HANDSHAKE_CPU_STORE_REG(PXP_BASE_PTR) - /*! * @} */ /* end of group PXP_Register_Accessor_Macros */ @@ -88080,7 +37598,6 @@ typedef struct { * @} */ /* end of group PXP_Peripheral */ - /* ---------------------------------------------------------------------------- -- QuadSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -88133,7 +37650,6 @@ typedef struct { uint8_t RESERVED_9[8]; __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ } QuadSPI_Type, *QuadSPI_MemMapPtr; - /* ---------------------------------------------------------------------------- -- QuadSPI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -88179,8 +37695,6 @@ typedef struct { /*! * @} */ /* end of group QuadSPI_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- QuadSPI Register Masks ---------------------------------------------------------------------------- */ @@ -88208,9 +37722,12 @@ typedef struct { #define QuadSPI_MCR_CLR_TXF_SHIFT 11 #define QuadSPI_MCR_MDIS_MASK 0x4000u #define QuadSPI_MCR_MDIS_SHIFT 14 -#define QuadSPI_MCR_SCLKCFG_MASK 0xFF000000u -#define QuadSPI_MCR_SCLKCFG_SHIFT 24 -#define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_SCLKCFG_SHIFT))&QuadSPI_MCR_SCLKCFG_MASK) +#define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_MASK 0x1000000u +#define QuadSPI_MCR_DQS_LOOPBACK_FROM_PAD_SHIFT 24 +#define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK 0x2000000u +#define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT 25 +#define QuadSPI_MCR_DQS_PHASE_EN_MASK 0x4000000u +#define QuadSPI_MCR_DQS_PHASE_EN_SHIFT 26 /* IPCR Bit Fields */ #define QuadSPI_IPCR_IDATSZ_MASK 0xFFFFu #define QuadSPI_IPCR_IDATSZ_SHIFT 0 @@ -88227,6 +37744,9 @@ typedef struct { #define QuadSPI_FLSHCR_TCSH_MASK 0xF00u #define QuadSPI_FLSHCR_TCSH_SHIFT 8 #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSH_SHIFT))&QuadSPI_FLSHCR_TCSH_MASK) +#define QuadSPI_FLSHCR_TDH_MASK 0x30000u +#define QuadSPI_FLSHCR_TDH_SHIFT 16 +#define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TDH_SHIFT))&QuadSPI_FLSHCR_TDH_MASK) /* BUF0CR Bit Fields */ #define QuadSPI_BUF0CR_MSTRID_MASK 0xFu #define QuadSPI_BUF0CR_MSTRID_SHIFT 0 @@ -88282,16 +37802,9 @@ typedef struct { #define QuadSPI_SFAR_SFADR_SHIFT 0 #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFAR_SFADR_SHIFT))&QuadSPI_SFAR_SFADR_MASK) /* SMPR Bit Fields */ -#define QuadSPI_SMPR_HSENA_MASK 0x1u -#define QuadSPI_SMPR_HSENA_SHIFT 0 -#define QuadSPI_SMPR_HSPHS_MASK 0x2u -#define QuadSPI_SMPR_HSPHS_SHIFT 1 -#define QuadSPI_SMPR_HSDLY_MASK 0x4u -#define QuadSPI_SMPR_HSDLY_SHIFT 2 -#define QuadSPI_SMPR_FSPHS_MASK 0x20u -#define QuadSPI_SMPR_FSPHS_SHIFT 5 -#define QuadSPI_SMPR_FSDLY_MASK 0x40u -#define QuadSPI_SMPR_FSDLY_SHIFT 6 +#define QuadSPI_SMPR_SDRSMP_MASK 0x60u +#define QuadSPI_SMPR_SDRSMP_SHIFT 5 +#define QuadSPI_SMPR_SDRSMP(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_SDRSMP_SHIFT))&QuadSPI_SMPR_SDRSMP_MASK) #define QuadSPI_SMPR_DDRSMP_MASK 0x70000u #define QuadSPI_SMPR_DDRSMP_SHIFT 16 #define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_DDRSMP_SHIFT))&QuadSPI_SMPR_DDRSMP_MASK) @@ -88309,7 +37822,7 @@ typedef struct { #define QuadSPI_RBCT_RXBRD_MASK 0x100u #define QuadSPI_RBCT_RXBRD_SHIFT 8 /* TBSR Bit Fields */ -#define QuadSPI_TBSR_TRBFL_MASK 0x3F00u +#define QuadSPI_TBSR_TRBFL_MASK 0x1F00u #define QuadSPI_TBSR_TRBFL_SHIFT 8 #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRBFL_SHIFT))&QuadSPI_TBSR_TRBFL_MASK) #define QuadSPI_TBSR_TRCTR_MASK 0xFFFF0000u @@ -88326,6 +37839,8 @@ typedef struct { #define QuadSPI_SR_IP_ACC_SHIFT 1 #define QuadSPI_SR_AHB_ACC_MASK 0x4u #define QuadSPI_SR_AHB_ACC_SHIFT 2 +#define QuadSPI_SR_RESERVED_MASK 0x8u +#define QuadSPI_SR_RESERVED_SHIFT 3 #define QuadSPI_SR_AHBGNT_MASK 0x20u #define QuadSPI_SR_AHBGNT_SHIFT 5 #define QuadSPI_SR_AHBTRN_MASK 0x40u @@ -88413,6 +37928,9 @@ typedef struct { #define QuadSPI_RSER_TBUIE_SHIFT 26 #define QuadSPI_RSER_TBFIE_MASK 0x8000000u #define QuadSPI_RSER_TBFIE_SHIFT 27 +#define QuadSPI_RSER_RESERVED_MASK 0x30000000u +#define QuadSPI_RSER_RESERVED_SHIFT 28 +#define QuadSPI_RSER_RESERVED(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_RESERVED_SHIFT))&QuadSPI_RSER_RESERVED_MASK) #define QuadSPI_RSER_DLPFIE_MASK 0x80000000u #define QuadSPI_RSER_DLPFIE_SHIFT 31 /* SPNDST Bit Fields */ @@ -88482,7 +38000,6 @@ typedef struct { * @} */ /* end of group QuadSPI_Register_Masks */ - /* QuadSPI - Peripheral instance base addresses */ /** Peripheral QuadSPI1 base address */ #define QuadSPI1_BASE (0x30BB0000u) @@ -88494,11 +38011,10 @@ typedef struct { /** Peripheral QuadSPI2 base pointer */ #define QuadSPI2 ((QuadSPI_Type *)QuadSPI2_BASE) #define QuadSPI2_BASE_PTR (QuadSPI2) -/** Array initializer of QuadSPI peripheral base adresses */ +/** Array initializer of QuadSPI peripheral base addresses */ #define QuadSPI_BASE_ADDRS { QuadSPI1_BASE, QuadSPI2_BASE } /** Array initializer of QuadSPI peripheral base pointers */ #define QuadSPI_BASE_PTRS { QuadSPI1, QuadSPI2 } - /* ---------------------------------------------------------------------------- -- QuadSPI - Register accessor macros ---------------------------------------------------------------------------- */ @@ -88760,13 +38276,11 @@ typedef struct { #define QuadSPI2_LUT61 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,61) #define QuadSPI2_LUT62 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,62) #define QuadSPI2_LUT63 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,63) - /* QuadSPI - Register array accessors */ #define QuadSPI1_RBDR(index) QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,index) #define QuadSPI2_RBDR(index) QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,index) #define QuadSPI1_LUT(index) QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,index) #define QuadSPI2_LUT(index) QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,index) - /*! * @} */ /* end of group QuadSPI_Register_Accessor_Macros */ @@ -88776,7 +38290,6 @@ typedef struct { * @} */ /* end of group QuadSPI_Peripheral */ - /* ---------------------------------------------------------------------------- -- RDC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -88803,9 +38316,8 @@ typedef struct { __IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */ __IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */ __IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */ - } MR[52]; + } MR[52]; } RDC_Type, *RDC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- RDC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -88831,8 +38343,6 @@ typedef struct { /*! * @} */ /* end of group RDC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- RDC Register Masks ---------------------------------------------------------------------------- */ @@ -88937,18 +38447,18 @@ typedef struct { * @} */ /* end of group RDC_Register_Masks */ - /* RDC - Peripheral instance base addresses */ /** Peripheral RDC base address */ #define RDC_BASE (0x303D0000u) /** Peripheral RDC base pointer */ #define RDC ((RDC_Type *)RDC_BASE) #define RDC_BASE_PTR (RDC) -/** Array initializer of RDC peripheral base adresses */ +/** Array initializer of RDC peripheral base addresses */ #define RDC_BASE_ADDRS { RDC_BASE } /** Array initializer of RDC peripheral base pointers */ #define RDC_BASE_PTRS { RDC } - +/** Interrupt vectors for the RDC peripheral type */ +#define RDC_IRQS { RDC_IRQn } /* ---------------------------------------------------------------------------- -- RDC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -89318,7 +38828,6 @@ typedef struct { #define RDC_MREA51 RDC_MREA_REG(RDC_BASE_PTR,51) #define RDC_MRC51 RDC_MRC_REG(RDC_BASE_PTR,51) #define RDC_MRVS51 RDC_MRVS_REG(RDC_BASE_PTR,51) - /* RDC - Register array accessors */ #define RDC_MDA(index) RDC_MDA_REG(RDC_BASE_PTR,index) #define RDC_PDAP(index) RDC_PDAP_REG(RDC_BASE_PTR,index) @@ -89326,86 +38835,6 @@ typedef struct { #define RDC_MREA(index) RDC_MREA_REG(RDC_BASE_PTR,index) #define RDC_MRC(index) RDC_MRC_REG(RDC_BASE_PTR,index) #define RDC_MRVS(index) RDC_MRVS_REG(RDC_BASE_PTR,index) - -/* MANUAL: RDC ID definition */ -#define RDC_MDA_M4_CORE_ID (1) - -#define RDC_PDAP_GPIO1_ID (0) -#define RDC_PDAP_GPIO2_ID (1) -#define RDC_PDAP_GPIO3_ID (2) -#define RDC_PDAP_GPIO4_ID (3) -#define RDC_PDAP_GPIO5_ID (4) -#define RDC_PDAP_GPIO6_ID (5) -#define RDC_PDAP_GPIO7_ID (6) -#define RDC_PDAP_WDOG3_ID (10) -#define RDC_PDAP_GPT3_ID (15) -#define RDC_PDAP_GPT4_ID (16) -#define RDC_PDAP_ADC1_ID (33) -#define RDC_PDAP_ADC2_ID (34) -#define RDC_PDAP_CAN1_ID (64) -#define RDC_PDAP_CAN2_ID (65) -#define RDC_PDAP_ECSPI1_ID (98) -#define RDC_PDAP_ECSPI2_ID (99) -#define RDC_PDAP_UART2_ID (105) - -/** - * @brief Memory region map register indices - * - * RDC MRxx register indices for memories/ports - */ -#define RDC_MR_MMDC_0_ID (0) -#define RDC_MR_MMDC_1_ID (1) -#define RDC_MR_MMDC_2_ID (2) -#define RDC_MR_MMDC_3_ID (3) -#define RDC_MR_MMDC_4_ID (4) -#define RDC_MR_MMDC_5_ID (5) -#define RDC_MR_MMDC_6_ID (6) -#define RDC_MR_MMDC_7_ID (7) -#define RDC_MR_QSPI_0_ID (8) -#define RDC_MR_QSPI_1_ID (9) -#define RDC_MR_QSPI_2_ID (10) -#define RDC_MR_QSPI_3_ID (11) -#define RDC_MR_QSPI_4_ID (12) -#define RDC_MR_QSPI_5_ID (13) -#define RDC_MR_QSPI_6_ID (14) -#define RDC_MR_QSPI_7_ID (15) -#define RDC_MR_WEIM_0_ID (16) -#define RDC_MR_WEIM_1_ID (17) -#define RDC_MR_WEIM_2_ID (18) -#define RDC_MR_WEIM_3_ID (19) -#define RDC_MR_WEIM_4_ID (20) -#define RDC_MR_WEIM_5_ID (21) -#define RDC_MR_WEIM_6_ID (22) -#define RDC_MR_WEIM_7_ID (23) -#define RDC_MR_PCIe_0_ID (24) -#define RDC_MR_PCIe_1_ID (25) -#define RDC_MR_PCIe_2_ID (26) -#define RDC_MR_PCIe_3_ID (27) -#define RDC_MR_PCIe_4_ID (28) -#define RDC_MR_PCIe_5_ID (29) -#define RDC_MR_PCIe_6_ID (30) -#define RDC_MR_PCIe_7_ID (31) -#define RDC_MR_OCRAM_0_ID (32) -#define RDC_MR_OCRAM_1_ID (33) -#define RDC_MR_OCRAM_2_ID (34) -#define RDC_MR_OCRAM_3_ID (35) -#define RDC_MR_OCRAM_4_ID (36) -#define RDC_MR_OCRAM_S_0_ID (37) -#define RDC_MR_OCRAM_S_1_ID (38) -#define RDC_MR_OCRAM_S_2_ID (39) -#define RDC_MR_OCRAM_S_3_ID (40) -#define RDC_MR_OCRAM_S_4_ID (41) -#define RDC_MR_OCRAM_EPDC_0_ID (42) -#define RDC_MR_OCRAM_EPDC_1_ID (43) -#define RDC_MR_OCRAM_EPDC_2_ID (44) -#define RDC_MR_OCRAM_EPDC_3_ID (45) -#define RDC_MR_OCRAM_EPDC_4_ID (46) -#define RDC_MR_OCRAM_PXP_0_ID (47) -#define RDC_MR_OCRAM_PXP_1_ID (48) -#define RDC_MR_OCRAM_PXP_2_ID (49) -#define RDC_MR_OCRAM_PXP_3_ID (50) -#define RDC_MR_OCRAM_PXP_4_ID (51) - /*! * @} */ /* end of group RDC_Register_Accessor_Macros */ @@ -89415,7 +38844,6 @@ typedef struct { * @} */ /* end of group RDC_Peripheral */ - /* ---------------------------------------------------------------------------- -- RDC_SEMAPHORE Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -89427,13 +38855,12 @@ typedef struct { /** RDC_SEMAPHORE - Register Layout Typedef */ typedef struct { - __IO uint8_t GATE[64]; /**< Gate Register, array offset: 0x0, array step: 0x1 */ + __IO uint8_t GATE[64]; /**< Gate Register, array offset: 0x0, array step: 0x1 */ union { /* offset: 0x40 */ - __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ - __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ + __IO uint16_t RSTGT_W; /**< Reset Gate Write,offset: 0x40 */ + __IO uint16_t RSTGT_R; /**< Reset Gate Read,offset: 0x40 */ }; } RDC_SEMAPHORE_Type, *RDC_SEMAPHORE_MemMapPtr; - /* ---------------------------------------------------------------------------- -- RDC_SEMAPHORE - Register accessor macros ---------------------------------------------------------------------------- */ @@ -89446,14 +38873,12 @@ typedef struct { /* RDC_SEMAPHORE - Register accessors */ #define RDC_SEMAPHORE_GATE_REG(base,index) ((base)->GATE[index]) -#define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) #define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) +#define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) /*! * @} */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- RDC_SEMAPHORE Register Masks ---------------------------------------------------------------------------- */ @@ -89470,6 +38895,13 @@ typedef struct { #define RDC_SEMAPHORE_GATE_LDOM_MASK 0x60u #define RDC_SEMAPHORE_GATE_LDOM_SHIFT 5 #define RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_LDOM_SHIFT))&RDC_SEMAPHORE_GATE_LDOM_MASK) +/* RSTGT_W Bit Fields */ +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK 0xFFu +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT 0 +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK 0xFF00u +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT 8 +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) /* RSTGT_R Bit Fields */ #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK 0xFu #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT 0 @@ -89480,19 +38912,11 @@ typedef struct { #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK 0xFF00u #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT 8 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK) -/* RSTGT_W Bit Fields */ -#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK 0xFFu -#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT 0 -#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) -#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK 0xFF00u -#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT 8 -#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) /*! * @} */ /* end of group RDC_SEMAPHORE_Register_Masks */ - /* RDC_SEMAPHORE - Peripheral instance base addresses */ /** Peripheral RDC_SEMAPHORE1 base address */ #define RDC_SEMAPHORE1_BASE (0x303B0000u) @@ -89504,11 +38928,10 @@ typedef struct { /** Peripheral RDC_SEMAPHORE2 base pointer */ #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE) #define RDC_SEMAPHORE2_BASE_PTR (RDC_SEMAPHORE2) -/** Array initializer of RDC_SEMAPHORE peripheral base adresses */ +/** Array initializer of RDC_SEMAPHORE peripheral base addresses */ #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE } /** Array initializer of RDC_SEMAPHORE peripheral base pointers */ #define RDC_SEMAPHORE_BASE_PTRS { RDC_SEMAPHORE1, RDC_SEMAPHORE2 } - /* ---------------------------------------------------------------------------- -- RDC_SEMAPHORE - Register accessor macros ---------------------------------------------------------------------------- */ @@ -89585,8 +39008,8 @@ typedef struct { #define RDC_SEMAPHORE1_GATE61 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,61) #define RDC_SEMAPHORE1_GATE62 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,62) #define RDC_SEMAPHORE1_GATE63 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,63) -#define RDC_SEMAPHORE1_RSTGT_R RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE1_BASE_PTR) #define RDC_SEMAPHORE1_RSTGT_W RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE1_BASE_PTR) +#define RDC_SEMAPHORE1_RSTGT_R RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE1_BASE_PTR) /* RDC_SEMAPHORE2 */ #define RDC_SEMAPHORE2_GATE0 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,0) #define RDC_SEMAPHORE2_GATE1 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,1) @@ -89652,13 +39075,11 @@ typedef struct { #define RDC_SEMAPHORE2_GATE61 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,61) #define RDC_SEMAPHORE2_GATE62 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,62) #define RDC_SEMAPHORE2_GATE63 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,63) -#define RDC_SEMAPHORE2_RSTGT_R RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE2_BASE_PTR) #define RDC_SEMAPHORE2_RSTGT_W RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE2_BASE_PTR) - +#define RDC_SEMAPHORE2_RSTGT_R RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE2_BASE_PTR) /* RDC_SEMAPHORE - Register array accessors */ #define RDC_SEMAPHORE1_GATE(index) RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,index) #define RDC_SEMAPHORE2_GATE(index) RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,index) - /*! * @} */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ @@ -89668,7 +39089,6 @@ typedef struct { * @} */ /* end of group RDC_SEMAPHORE_Peripheral */ - /* ---------------------------------------------------------------------------- -- ROMC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -89689,7 +39109,6 @@ typedef struct { uint8_t RESERVED_1[200]; __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ } ROMC_Type, *ROMC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- ROMC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -89711,8 +39130,6 @@ typedef struct { /*! * @} */ /* end of group ROMC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- ROMC Register Masks ---------------------------------------------------------------------------- */ @@ -89732,6 +39149,7 @@ typedef struct { #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHCNTL_DATAFIX_SHIFT))&ROMC_ROMPATCHCNTL_DATAFIX_MASK) #define ROMC_ROMPATCHCNTL_DIS_MASK 0x20000000u #define ROMC_ROMPATCHCNTL_DIS_SHIFT 29 +/* ROMPATCHENH Bit Fields */ /* ROMPATCHENL Bit Fields */ #define ROMC_ROMPATCHENL_ENABLE_MASK 0xFFFFu #define ROMC_ROMPATCHENL_ENABLE_SHIFT 0 @@ -89753,18 +39171,16 @@ typedef struct { * @} */ /* end of group ROMC_Register_Masks */ - /* ROMC - Peripheral instance base addresses */ /** Peripheral ROMC base address */ #define ROMC_BASE (0x30310000u) /** Peripheral ROMC base pointer */ #define ROMC ((ROMC_Type *)ROMC_BASE) #define ROMC_BASE_PTR (ROMC) -/** Array initializer of ROMC peripheral base adresses */ +/** Array initializer of ROMC peripheral base addresses */ #define ROMC_BASE_ADDRS { ROMC_BASE } /** Array initializer of ROMC peripheral base pointers */ #define ROMC_BASE_PTRS { ROMC } - /* ---------------------------------------------------------------------------- -- ROMC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -89805,11 +39221,9 @@ typedef struct { #define ROMC_ROMPATCH14A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,14) #define ROMC_ROMPATCH15A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,15) #define ROMC_ROMPATCHSR ROMC_ROMPATCHSR_REG(ROMC_BASE_PTR) - /* ROMC - Register array accessors */ #define ROMC_ROMPATCHD(index) ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,index) #define ROMC_ROMPATCHA(index) ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,index) - /*! * @} */ /* end of group ROMC_Register_Accessor_Macros */ @@ -89819,7 +39233,6 @@ typedef struct { * @} */ /* end of group ROMC_Peripheral */ - /* ---------------------------------------------------------------------------- -- SDMAARM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -89865,7 +39278,6 @@ typedef struct { uint8_t RESERVED_4[128]; __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ } SDMAARM_Type, *SDMAARM_MemMapPtr; - /* ---------------------------------------------------------------------------- -- SDMAARM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -89909,8 +39321,6 @@ typedef struct { /*! * @} */ /* end of group SDMAARM_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- SDMAARM Register Masks ---------------------------------------------------------------------------- */ @@ -90102,18 +39512,18 @@ typedef struct { * @} */ /* end of group SDMAARM_Register_Masks */ - /* SDMAARM - Peripheral instance base addresses */ /** Peripheral SDMAARM base address */ #define SDMAARM_BASE (0x30BD0000u) /** Peripheral SDMAARM base pointer */ #define SDMAARM ((SDMAARM_Type *)SDMAARM_BASE) #define SDMAARM_BASE_PTR (SDMAARM) -/** Array initializer of SDMAARM peripheral base adresses */ +/** Array initializer of SDMAARM peripheral base addresses */ #define SDMAARM_BASE_ADDRS { SDMAARM_BASE } /** Array initializer of SDMAARM peripheral base pointers */ #define SDMAARM_BASE_PTRS { SDMAARM } - +/** Interrupt vectors for the SDMAARM peripheral type */ +#define SDMAARM_IRQS { SDMA_IRQn } /* ---------------------------------------------------------------------------- -- SDMAARM - Register accessor macros ---------------------------------------------------------------------------- */ @@ -90232,11 +39642,9 @@ typedef struct { #define SDMAARM_CHNENBL45 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,45) #define SDMAARM_CHNENBL46 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,46) #define SDMAARM_CHNENBL47 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,47) - /* SDMAARM - Register array accessors */ #define SDMAARM_SDMA_CHNPRI(index) SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,index) #define SDMAARM_CHNENBL(index) SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,index) - /*! * @} */ /* end of group SDMAARM_Register_Accessor_Macros */ @@ -90246,462 +39654,6 @@ typedef struct { * @} */ /* end of group SDMAARM_Peripheral */ - -/* ---------------------------------------------------------------------------- - -- SDMABP Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDMABP_Peripheral_Access_Layer SDMABP Peripheral Access Layer - * @{ - */ - -/** SDMABP - Register Layout Typedef */ -typedef struct { - __IO uint32_t DC0PTR; /**< Channel 0 Pointer, offset: 0x0 */ - __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ - __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ - __I uint32_t DSTART; /**< Channel Start, offset: 0xC */ - uint8_t RESERVED_0[24]; - __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ - __IO uint32_t INTRMASK; /**< Channel DSP Interrupt Mask, offset: 0x2C */ - uint8_t RESERVED_1[4]; - __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ -} SDMABP_Type, *SDMABP_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- SDMABP - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDMABP_Register_Accessor_Macros SDMABP - Register accessor macros - * @{ - */ - - -/* SDMABP - Register accessors */ -#define SDMABP_DC0PTR_REG(base) ((base)->DC0PTR) -#define SDMABP_INTR_REG(base) ((base)->INTR) -#define SDMABP_STOP_STAT_REG(base) ((base)->STOP_STAT) -#define SDMABP_DSTART_REG(base) ((base)->DSTART) -#define SDMABP_EVTERR_REG(base) ((base)->EVTERR) -#define SDMABP_INTRMASK_REG(base) ((base)->INTRMASK) -#define SDMABP_EVTERRDBG_REG(base) ((base)->EVTERRDBG) - -/*! - * @} - */ /* end of group SDMABP_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDMABP Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDMABP_Register_Masks SDMABP Register Masks - * @{ - */ - -/* DC0PTR Bit Fields */ -#define SDMABP_DC0PTR_DC0PTR_MASK 0xFFFFFFFFu -#define SDMABP_DC0PTR_DC0PTR_SHIFT 0 -#define SDMABP_DC0PTR_DC0PTR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_DC0PTR_DC0PTR_SHIFT))&SDMABP_DC0PTR_DC0PTR_MASK) -/* INTR Bit Fields */ -#define SDMABP_INTR_DI_MASK 0xFFFFFFFFu -#define SDMABP_INTR_DI_SHIFT 0 -#define SDMABP_INTR_DI(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_INTR_DI_SHIFT))&SDMABP_INTR_DI_MASK) -/* STOP_STAT Bit Fields */ -#define SDMABP_STOP_STAT_DE_MASK 0xFFFFFFFFu -#define SDMABP_STOP_STAT_DE_SHIFT 0 -#define SDMABP_STOP_STAT_DE(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_STOP_STAT_DE_SHIFT))&SDMABP_STOP_STAT_DE_MASK) -/* DSTART Bit Fields */ -#define SDMABP_DSTART_DSTART_DE_MASK 0xFFFFFFFFu -#define SDMABP_DSTART_DSTART_DE_SHIFT 0 -#define SDMABP_DSTART_DSTART_DE(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_DSTART_DSTART_DE_SHIFT))&SDMABP_DSTART_DSTART_DE_MASK) -/* EVTERR Bit Fields */ -#define SDMABP_EVTERR_CHNERR_MASK 0xFFFFFFFFu -#define SDMABP_EVTERR_CHNERR_SHIFT 0 -#define SDMABP_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_EVTERR_CHNERR_SHIFT))&SDMABP_EVTERR_CHNERR_MASK) -/* INTRMASK Bit Fields */ -#define SDMABP_INTRMASK_DIMASK_MASK 0xFFFFFFFFu -#define SDMABP_INTRMASK_DIMASK_SHIFT 0 -#define SDMABP_INTRMASK_DIMASK(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_INTRMASK_DIMASK_SHIFT))&SDMABP_INTRMASK_DIMASK_MASK) -/* EVTERRDBG Bit Fields */ -#define SDMABP_EVTERRDBG_CHNERR_MASK 0xFFFFFFFFu -#define SDMABP_EVTERRDBG_CHNERR_SHIFT 0 -#define SDMABP_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_EVTERRDBG_CHNERR_SHIFT))&SDMABP_EVTERRDBG_CHNERR_MASK) - -/*! - * @} - */ /* end of group SDMABP_Register_Masks */ - - -/* SDMABP - Peripheral instance base addresses */ -/** Peripheral SDMABP base address */ -#define SDMABP_BASE (0x30BD0000u) -/** Peripheral SDMABP base pointer */ -#define SDMABP ((SDMABP_Type *)SDMABP_BASE) -#define SDMABP_BASE_PTR (SDMABP) -/** Array initializer of SDMABP peripheral base adresses */ -#define SDMABP_BASE_ADDRS { SDMABP_BASE } -/** Array initializer of SDMABP peripheral base pointers */ -#define SDMABP_BASE_PTRS { SDMABP } - -/* ---------------------------------------------------------------------------- - -- SDMABP - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDMABP_Register_Accessor_Macros SDMABP - Register accessor macros - * @{ - */ - - -/* SDMABP - Register instance definitions */ -/* SDMABP */ -#define SDMABP_DC0PTR SDMABP_DC0PTR_REG(SDMABP_BASE_PTR) -#define SDMABP_INTR SDMABP_INTR_REG(SDMABP_BASE_PTR) -#define SDMABP_STOP_STAT SDMABP_STOP_STAT_REG(SDMABP_BASE_PTR) -#define SDMABP_DSTART SDMABP_DSTART_REG(SDMABP_BASE_PTR) -#define SDMABP_EVTERR SDMABP_EVTERR_REG(SDMABP_BASE_PTR) -#define SDMABP_INTRMASK SDMABP_INTRMASK_REG(SDMABP_BASE_PTR) -#define SDMABP_EVTERRDBG SDMABP_EVTERRDBG_REG(SDMABP_BASE_PTR) - -/*! - * @} - */ /* end of group SDMABP_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group SDMABP_Peripheral */ - - -/* ---------------------------------------------------------------------------- - -- SDMACORE Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDMACORE_Peripheral_Access_Layer SDMACORE Peripheral Access Layer - * @{ - */ - -/** SDMACORE - Register Layout Typedef */ -typedef struct { - union { /* offset: 0x0 */ - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[6]; - __I uint32_t CCPRI; /**< Current Channel Priority, offset: 0x6 */ - } CCPRI; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[2]; - __I uint32_t CCPTR; /**< Current Channel Pointer, offset: 0x2 */ - } CCPTR; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[3]; - __I uint32_t CCR; /**< Current Channel Register, offset: 0x3 */ - } CCR; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[11]; - __IO uint32_t EAA; /**< OnCE Event Address Register A, offset: 0xB */ - } EAA; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t EAB; /**< OnCE Event Cell Address Register B, offset: 0xC */ - } EAB; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[13]; - __IO uint32_t EAM; /**< OnCE Event Cell Address Mask, offset: 0xD */ - } EAM; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[9]; - __IO uint32_t ECOUNT; /**< OnCE Event Cell Counter, offset: 0x9 */ - } ECOUNT; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[10]; - __IO uint32_t ECTL; /**< OnCE Event Cell Control Register, offset: 0xA */ - } ECTL; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[14]; - __IO uint32_t ED; /**< OnCE Event Cell Data Register, offset: 0xE */ - } ED; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[15]; - __IO uint32_t EDM; /**< OnCE Event Cell Data Mask, offset: 0xF */ - } EDM; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[5]; - __I uint32_t EVENTS; /**< External DMA Requests Mirror, offset: 0x5 */ - } EVENTS; - __I uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer, offset: 0x0 */ - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[7]; - __I uint32_t NCPRI; /**< Next Channel Priority, offset: 0x7 */ - } NCPRI; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[4]; - __I uint32_t NCR; /**< Highest Pending Channel Register, offset: 0x4 */ - } NCR; - }; - uint8_t RESERVED_0[5]; - union { /* offset: 0x18 */ - struct { /* offset: 0x18 */ - uint8_t RESERVED_0[5]; - __I uint32_t ENDIANNESS; /**< ENDIAN Status Register, offset: 0x1D */ - } ENDIANNESS; - struct { /* offset: 0x18 */ - uint8_t RESERVED_0[7]; - __I uint32_t EVENTS2; /**< External DMA Requests Mirror #2, offset: 0x1F */ - } EVENTS2; - struct { /* offset: 0x18 */ - uint8_t RESERVED_0[4]; - __I uint32_t MCHN0ADDR; /**< Channel 0 Boot Address, offset: 0x1C */ - } MCHN0ADDR; - struct { /* offset: 0x18 */ - uint8_t RESERVED_0[2]; - __I uint32_t OSTAT; /**< OnCE Status, offset: 0x1A */ - } OSTAT; - __IO uint32_t RTB; /**< OnCE Real-Time Buffer, offset: 0x18 */ - struct { /* offset: 0x18 */ - uint8_t RESERVED_0[6]; - __I uint32_t SDMA_LOCK; /**< Lock Status Register, offset: 0x1E */ - } SDMA_LOCK; - struct { /* offset: 0x18 */ - uint8_t RESERVED_0[1]; - __IO uint32_t TB; /**< OnCE Trace Buffer, offset: 0x19 */ - } TB; - }; -} SDMACORE_Type, *SDMACORE_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- SDMACORE - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDMACORE_Register_Accessor_Macros SDMACORE - Register accessor macros - * @{ - */ - - -/* SDMACORE - Register accessors */ -#define SDMACORE_CCPRI_REG(base) ((base)->CCPRI.CCPRI) -#define SDMACORE_CCPTR_REG(base) ((base)->CCPTR.CCPTR) -#define SDMACORE_CCR_REG(base) ((base)->CCR.CCR) -#define SDMACORE_EAA_REG(base) ((base)->EAA.EAA) -#define SDMACORE_EAB_REG(base) ((base)->EAB.EAB) -#define SDMACORE_EAM_REG(base) ((base)->EAM.EAM) -#define SDMACORE_ECOUNT_REG(base) ((base)->ECOUNT.ECOUNT) -#define SDMACORE_ECTL_REG(base) ((base)->ECTL.ECTL) -#define SDMACORE_ED_REG(base) ((base)->ED.ED) -#define SDMACORE_EDM_REG(base) ((base)->EDM.EDM) -#define SDMACORE_EVENTS_REG(base) ((base)->EVENTS.EVENTS) -#define SDMACORE_MC0PTR_REG(base) ((base)->MC0PTR) -#define SDMACORE_NCPRI_REG(base) ((base)->NCPRI.NCPRI) -#define SDMACORE_NCR_REG(base) ((base)->NCR.NCR) -#define SDMACORE_ENDIANNESS_REG(base) ((base)->ENDIANNESS.ENDIANNESS) -#define SDMACORE_EVENTS2_REG(base) ((base)->EVENTS2.EVENTS2) -#define SDMACORE_MCHN0ADDR_REG(base) ((base)->MCHN0ADDR.MCHN0ADDR) -#define SDMACORE_OSTAT_REG(base) ((base)->OSTAT.OSTAT) -#define SDMACORE_RTB_REG(base) ((base)->RTB) -#define SDMACORE_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK.SDMA_LOCK) -#define SDMACORE_TB_REG(base) ((base)->TB.TB) - -/*! - * @} - */ /* end of group SDMACORE_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDMACORE Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDMACORE_Register_Masks SDMACORE Register Masks - * @{ - */ - -/* CCPRI Bit Fields */ -#define SDMACORE_CCPRI_CCPRI_MASK 0x7u -#define SDMACORE_CCPRI_CCPRI_SHIFT 0 -#define SDMACORE_CCPRI_CCPRI(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCPRI_CCPRI_SHIFT))&SDMACORE_CCPRI_CCPRI_MASK) -/* CCPTR Bit Fields */ -#define SDMACORE_CCPTR_CCPTR_MASK 0xFFFFu -#define SDMACORE_CCPTR_CCPTR_SHIFT 0 -#define SDMACORE_CCPTR_CCPTR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCPTR_CCPTR_SHIFT))&SDMACORE_CCPTR_CCPTR_MASK) -/* CCR Bit Fields */ -#define SDMACORE_CCR_CCR_MASK 0x1Fu -#define SDMACORE_CCR_CCR_SHIFT 0 -#define SDMACORE_CCR_CCR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCR_CCR_SHIFT))&SDMACORE_CCR_CCR_MASK) -/* EAA Bit Fields */ -#define SDMACORE_EAA_EAA_MASK 0xFFFFu -#define SDMACORE_EAA_EAA_SHIFT 0 -#define SDMACORE_EAA_EAA(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAA_EAA_SHIFT))&SDMACORE_EAA_EAA_MASK) -/* EAB Bit Fields */ -#define SDMACORE_EAB_EAB_MASK 0xFFFFu -#define SDMACORE_EAB_EAB_SHIFT 0 -#define SDMACORE_EAB_EAB(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAB_EAB_SHIFT))&SDMACORE_EAB_EAB_MASK) -/* EAM Bit Fields */ -#define SDMACORE_EAM_EAM_MASK 0xFFFFu -#define SDMACORE_EAM_EAM_SHIFT 0 -#define SDMACORE_EAM_EAM(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAM_EAM_SHIFT))&SDMACORE_EAM_EAM_MASK) -/* ECOUNT Bit Fields */ -#define SDMACORE_ECOUNT_ECOUNT_MASK 0xFFFFu -#define SDMACORE_ECOUNT_ECOUNT_SHIFT 0 -#define SDMACORE_ECOUNT_ECOUNT(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECOUNT_ECOUNT_SHIFT))&SDMACORE_ECOUNT_ECOUNT_MASK) -/* ECTL Bit Fields */ -#define SDMACORE_ECTL_ATS_MASK 0x3u -#define SDMACORE_ECTL_ATS_SHIFT 0 -#define SDMACORE_ECTL_ATS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ATS_SHIFT))&SDMACORE_ECTL_ATS_MASK) -#define SDMACORE_ECTL_AATC_MASK 0xCu -#define SDMACORE_ECTL_AATC_SHIFT 2 -#define SDMACORE_ECTL_AATC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_AATC_SHIFT))&SDMACORE_ECTL_AATC_MASK) -#define SDMACORE_ECTL_ABTC_MASK 0x30u -#define SDMACORE_ECTL_ABTC_SHIFT 4 -#define SDMACORE_ECTL_ABTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ABTC_SHIFT))&SDMACORE_ECTL_ABTC_MASK) -#define SDMACORE_ECTL_ATC_MASK 0xC0u -#define SDMACORE_ECTL_ATC_SHIFT 6 -#define SDMACORE_ECTL_ATC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ATC_SHIFT))&SDMACORE_ECTL_ATC_MASK) -#define SDMACORE_ECTL_DTC_MASK 0x300u -#define SDMACORE_ECTL_DTC_SHIFT 8 -#define SDMACORE_ECTL_DTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_DTC_SHIFT))&SDMACORE_ECTL_DTC_MASK) -#define SDMACORE_ECTL_ECTC_MASK 0xC00u -#define SDMACORE_ECTL_ECTC_SHIFT 10 -#define SDMACORE_ECTL_ECTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ECTC_SHIFT))&SDMACORE_ECTL_ECTC_MASK) -#define SDMACORE_ECTL_CNT_MASK 0x1000u -#define SDMACORE_ECTL_CNT_SHIFT 12 -#define SDMACORE_ECTL_EN_MASK 0x2000u -#define SDMACORE_ECTL_EN_SHIFT 13 -/* ED Bit Fields */ -#define SDMACORE_ED_ED_MASK 0xFFFFFFFFu -#define SDMACORE_ED_ED_SHIFT 0 -#define SDMACORE_ED_ED(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ED_ED_SHIFT))&SDMACORE_ED_ED_MASK) -/* EDM Bit Fields */ -#define SDMACORE_EDM_EDM_MASK 0xFFFFFFFFu -#define SDMACORE_EDM_EDM_SHIFT 0 -#define SDMACORE_EDM_EDM(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EDM_EDM_SHIFT))&SDMACORE_EDM_EDM_MASK) -/* EVENTS Bit Fields */ -#define SDMACORE_EVENTS_EVENTS_MASK 0xFFFFFFFFu -#define SDMACORE_EVENTS_EVENTS_SHIFT 0 -#define SDMACORE_EVENTS_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EVENTS_EVENTS_SHIFT))&SDMACORE_EVENTS_EVENTS_MASK) -/* MC0PTR Bit Fields */ -#define SDMACORE_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu -#define SDMACORE_MC0PTR_MC0PTR_SHIFT 0 -#define SDMACORE_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_MC0PTR_MC0PTR_SHIFT))&SDMACORE_MC0PTR_MC0PTR_MASK) -/* NCPRI Bit Fields */ -#define SDMACORE_NCPRI_NCPRI_MASK 0x7u -#define SDMACORE_NCPRI_NCPRI_SHIFT 0 -#define SDMACORE_NCPRI_NCPRI(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_NCPRI_NCPRI_SHIFT))&SDMACORE_NCPRI_NCPRI_MASK) -/* NCR Bit Fields */ -#define SDMACORE_NCR_NCR_MASK 0x1Fu -#define SDMACORE_NCR_NCR_SHIFT 0 -#define SDMACORE_NCR_NCR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_NCR_NCR_SHIFT))&SDMACORE_NCR_NCR_MASK) -/* ENDIANNESS Bit Fields */ -#define SDMACORE_ENDIANNESS_APEND_MASK 0x1u -#define SDMACORE_ENDIANNESS_APEND_SHIFT 0 -/* EVENTS2 Bit Fields */ -#define SDMACORE_EVENTS2_EVENTS_MASK 0xFFFFu -#define SDMACORE_EVENTS2_EVENTS_SHIFT 0 -#define SDMACORE_EVENTS2_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EVENTS2_EVENTS_SHIFT))&SDMACORE_EVENTS2_EVENTS_MASK) -/* MCHN0ADDR Bit Fields */ -#define SDMACORE_MCHN0ADDR_CHN0ADDR_MASK 0x3FFFu -#define SDMACORE_MCHN0ADDR_CHN0ADDR_SHIFT 0 -#define SDMACORE_MCHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_MCHN0ADDR_CHN0ADDR_SHIFT))&SDMACORE_MCHN0ADDR_CHN0ADDR_MASK) -#define SDMACORE_MCHN0ADDR_SMSZ_MASK 0x4000u -#define SDMACORE_MCHN0ADDR_SMSZ_SHIFT 14 -/* OSTAT Bit Fields */ -#define SDMACORE_OSTAT_ECDR_MASK 0x7u -#define SDMACORE_OSTAT_ECDR_SHIFT 0 -#define SDMACORE_OSTAT_ECDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_OSTAT_ECDR_SHIFT))&SDMACORE_OSTAT_ECDR_MASK) -#define SDMACORE_OSTAT_MST_MASK 0x80u -#define SDMACORE_OSTAT_MST_SHIFT 7 -#define SDMACORE_OSTAT_SWB_MASK 0x100u -#define SDMACORE_OSTAT_SWB_SHIFT 8 -#define SDMACORE_OSTAT_ODR_MASK 0x200u -#define SDMACORE_OSTAT_ODR_SHIFT 9 -#define SDMACORE_OSTAT_EDR_MASK 0x400u -#define SDMACORE_OSTAT_EDR_SHIFT 10 -#define SDMACORE_OSTAT_RCV_MASK 0x800u -#define SDMACORE_OSTAT_RCV_SHIFT 11 -#define SDMACORE_OSTAT_PST_MASK 0xF000u -#define SDMACORE_OSTAT_PST_SHIFT 12 -#define SDMACORE_OSTAT_PST(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_OSTAT_PST_SHIFT))&SDMACORE_OSTAT_PST_MASK) -/* RTB Bit Fields */ -#define SDMACORE_RTB_RTB_MASK 0xFFFFFFFFu -#define SDMACORE_RTB_RTB_SHIFT 0 -#define SDMACORE_RTB_RTB(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_RTB_RTB_SHIFT))&SDMACORE_RTB_RTB_MASK) -/* SDMA_LOCK Bit Fields */ -#define SDMACORE_SDMA_LOCK_LOCK_MASK 0x1u -#define SDMACORE_SDMA_LOCK_LOCK_SHIFT 0 -/* TB Bit Fields */ -#define SDMACORE_TB_CHFADDR_MASK 0x3FFFu -#define SDMACORE_TB_CHFADDR_SHIFT 0 -#define SDMACORE_TB_CHFADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_TB_CHFADDR_SHIFT))&SDMACORE_TB_CHFADDR_MASK) -#define SDMACORE_TB_TADDR_MASK 0xFFFC000u -#define SDMACORE_TB_TADDR_SHIFT 14 -#define SDMACORE_TB_TADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_TB_TADDR_SHIFT))&SDMACORE_TB_TADDR_MASK) -#define SDMACORE_TB_TBF_MASK 0x10000000u -#define SDMACORE_TB_TBF_SHIFT 28 - -/*! - * @} - */ /* end of group SDMACORE_Register_Masks */ - - -/* SDMACORE - Peripheral instance base addresses */ -/** Peripheral SDMACORE base address */ -#define SDMACORE_BASE (0x30BD0000u) -/** Peripheral SDMACORE base pointer */ -#define SDMACORE ((SDMACORE_Type *)SDMACORE_BASE) -#define SDMACORE_BASE_PTR (SDMACORE) -/** Array initializer of SDMACORE peripheral base adresses */ -#define SDMACORE_BASE_ADDRS { SDMACORE_BASE } -/** Array initializer of SDMACORE peripheral base pointers */ -#define SDMACORE_BASE_PTRS { SDMACORE } - -/* ---------------------------------------------------------------------------- - -- SDMACORE - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDMACORE_Register_Accessor_Macros SDMACORE - Register accessor macros - * @{ - */ - - -/* SDMACORE - Register instance definitions */ -/* SDMACORE */ -#define SDMACORE_MC0PTR SDMACORE_MC0PTR_REG(SDMACORE_BASE_PTR) -#define SDMACORE_CCPTR SDMACORE_CCPTR_REG(SDMACORE_BASE_PTR) -#define SDMACORE_CCR SDMACORE_CCR_REG(SDMACORE_BASE_PTR) -#define SDMACORE_NCR SDMACORE_NCR_REG(SDMACORE_BASE_PTR) -#define SDMACORE_EVENTS SDMACORE_EVENTS_REG(SDMACORE_BASE_PTR) -#define SDMACORE_CCPRI SDMACORE_CCPRI_REG(SDMACORE_BASE_PTR) -#define SDMACORE_NCPRI SDMACORE_NCPRI_REG(SDMACORE_BASE_PTR) -#define SDMACORE_ECOUNT SDMACORE_ECOUNT_REG(SDMACORE_BASE_PTR) -#define SDMACORE_ECTL SDMACORE_ECTL_REG(SDMACORE_BASE_PTR) -#define SDMACORE_EAA SDMACORE_EAA_REG(SDMACORE_BASE_PTR) -#define SDMACORE_EAB SDMACORE_EAB_REG(SDMACORE_BASE_PTR) -#define SDMACORE_EAM SDMACORE_EAM_REG(SDMACORE_BASE_PTR) -#define SDMACORE_ED SDMACORE_ED_REG(SDMACORE_BASE_PTR) -#define SDMACORE_EDM SDMACORE_EDM_REG(SDMACORE_BASE_PTR) -#define SDMACORE_RTB SDMACORE_RTB_REG(SDMACORE_BASE_PTR) -#define SDMACORE_TB SDMACORE_TB_REG(SDMACORE_BASE_PTR) -#define SDMACORE_OSTAT SDMACORE_OSTAT_REG(SDMACORE_BASE_PTR) -#define SDMACORE_MCHN0ADDR SDMACORE_MCHN0ADDR_REG(SDMACORE_BASE_PTR) -#define SDMACORE_ENDIANNESS SDMACORE_ENDIANNESS_REG(SDMACORE_BASE_PTR) -#define SDMACORE_SDMA_LOCK SDMACORE_SDMA_LOCK_REG(SDMACORE_BASE_PTR) -#define SDMACORE_EVENTS2 SDMACORE_EVENTS2_REG(SDMACORE_BASE_PTR) - -/*! - * @} - */ /* end of group SDMACORE_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group SDMACORE_Peripheral */ - - /* ---------------------------------------------------------------------------- -- SEMA4 Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -90711,39 +39663,39 @@ typedef struct { * @{ */ +/** SEMA4 - Register Layout Typedef */ typedef struct { - __IO uint8_t GATE00; /**< Semaphores GATE 0 Register, offset: 0x0 */ - __IO uint8_t GATE01; /**< Semaphores GATE 1 Register, offset: 0x1 */ - __IO uint8_t GATE02; /**< Semaphores GATE 2 Register, offset: 0x2 */ - __IO uint8_t GATE03; /**< Semaphores GATE 3 Register, offset: 0x3 */ - __IO uint8_t GATE04; /**< Semaphores GATE 4 Register, offset: 0x4 */ - __IO uint8_t GATE05; /**< Semaphores GATE 5 Register, offset: 0x5 */ - __IO uint8_t GATE06; /**< Semaphores GATE 6 Register, offset: 0x6 */ - __IO uint8_t GATE07; /**< Semaphores GATE 7 Register, offset: 0x7 */ - __IO uint8_t GATE08; /**< Semaphores GATE 8 Register, offset: 0x8 */ - __IO uint8_t GATE09; /**< Semaphores GATE 9 Register, offset: 0x9 */ - __IO uint8_t GATE10; /**< Semaphores GATE 10 Register, offset: 0xA */ - __IO uint8_t GATE11; /**< Semaphores GATE 11 Register, offset: 0xB */ - __IO uint8_t GATE12; /**< Semaphores GATE 12 Register, offset: 0xC */ - __IO uint8_t GATE13; /**< Semaphores GATE 13 Register, offset: 0xD */ - __IO uint8_t GATE14; /**< Semaphores GATE 14 Register, offset: 0xE */ - __IO uint8_t GATE15; /**< Semaphores GATE 15 Register, offset: 0xF */ - uint8_t RESERVED_0[48]; + __IO uint8_t GATE00; /**< Semaphores Gate 3 Register, offset: 0x0 */ + __IO uint8_t GATE01; /**< Semaphores Gate 2 Register, offset: 0x1 */ + __IO uint8_t GATE02; /**< Semaphores Gate 1 Register, offset: 0x2 */ + __IO uint8_t GATE03; /**< Semaphores Gate 0 Register, offset: 0x3 */ + __IO uint8_t GATE04; /**< Semaphores Gate 7 Register, offset: 0x4 */ + __IO uint8_t GATE05; /**< Semaphores Gate 6 Register, offset: 0x5 */ + __IO uint8_t GATE06; /**< Semaphores Gate 5 Register, offset: 0x6 */ + __IO uint8_t GATE07; /**< Semaphores Gate 4 Register, offset: 0x7 */ + __IO uint8_t GATE08; /**< Semaphores Gate 11 Register, offset: 0x8 */ + __IO uint8_t GATE09; /**< Semaphores Gate 10 Register, offset: 0x9 */ + __IO uint8_t GATE10; /**< Semaphores Gate 9 Register, offset: 0xA */ + __IO uint8_t GATE11; /**< Semaphores Gate 8 Register, offset: 0xB */ + __IO uint8_t GATE12; /**< Semaphores Gate 15 Register, offset: 0xC */ + __IO uint8_t GATE13; /**< Semaphores Gate 14 Register, offset: 0xD */ + __IO uint8_t GATE14; /**< Semaphores Gate 13 Register, offset: 0xE */ + __IO uint8_t GATE15; /**< Semaphores Gate 12 Register, offset: 0xF */ + uint8_t RESERVED_0[48]; struct { /* offset: 0x40, array step: 0x8 */ - __IO uint16_t INE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ - uint8_t RESERVED_0[6]; + __IO uint16_t INE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ + uint8_t RESERVED_0[6]; } CPnINE[2]; - uint8_t RESERVED_1[48]; + uint8_t RESERVED_1[48]; struct { /* offset: 0x80, array step: 0x8 */ - __IO uint16_t NTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */ - uint8_t RESERVED_0[6]; + __I uint16_t NTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */ + uint8_t RESERVED_0[6]; } CPnNTF[2]; - uint8_t RESERVED_2[112]; - __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */ - uint8_t RESERVED_3[2]; - __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */ + uint8_t RESERVED_2[112]; + __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */ + uint8_t RESERVED_3[2]; + __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */ } SEMA4_Type, *SEMA4_MemMapPtr; - /* ---------------------------------------------------------------------------- -- SEMA4 - Register accessor macros ---------------------------------------------------------------------------- */ @@ -90755,32 +39707,30 @@ typedef struct { /* SEMA4 - Register accessors */ -#define SEMA4_GATE03_REG(base) ((base)->Gate03) -#define SEMA4_GATE02_REG(base) ((base)->Gate02) -#define SEMA4_GATE01_REG(base) ((base)->Gate01) -#define SEMA4_GATE00_REG(base) ((base)->Gate00) -#define SEMA4_GATE07_REG(base) ((base)->Gate07) -#define SEMA4_GATE06_REG(base) ((base)->Gate06) -#define SEMA4_GATE05_REG(base) ((base)->Gate05) -#define SEMA4_GATE04_REG(base) ((base)->Gate04) -#define SEMA4_GATE11_REG(base) ((base)->Gate11) -#define SEMA4_GATE10_REG(base) ((base)->Gate10) -#define SEMA4_GATE09_REG(base) ((base)->Gate09) -#define SEMA4_GATE08_REG(base) ((base)->Gate08) -#define SEMA4_GATE15_REG(base) ((base)->Gate15) -#define SEMA4_GATE14_REG(base) ((base)->Gate14) -#define SEMA4_GATE13_REG(base) ((base)->Gate13) -#define SEMA4_GATE12_REG(base) ((base)->Gate12) -#define SEMA4_CPINE_REG(base,index) ((base)->CPINE[index].CPINE) -#define SEMA4_CPNTF_REG(base,index) ((base)->CPNTF[index].CPNTF) +#define SEMA4_GATE00_REG(base) ((base)->GATE00) +#define SEMA4_GATE01_REG(base) ((base)->GATE01) +#define SEMA4_GATE02_REG(base) ((base)->GATE02) +#define SEMA4_GATE03_REG(base) ((base)->GATE03) +#define SEMA4_GATE04_REG(base) ((base)->GATE04) +#define SEMA4_GATE05_REG(base) ((base)->GATE05) +#define SEMA4_GATE06_REG(base) ((base)->GATE06) +#define SEMA4_GATE07_REG(base) ((base)->GATE07) +#define SEMA4_GATE08_REG(base) ((base)->GATE08) +#define SEMA4_GATE09_REG(base) ((base)->GATE09) +#define SEMA4_GATE10_REG(base) ((base)->GATE10) +#define SEMA4_GATE11_REG(base) ((base)->GATE11) +#define SEMA4_GATE12_REG(base) ((base)->GATE12) +#define SEMA4_GATE13_REG(base) ((base)->GATE13) +#define SEMA4_GATE14_REG(base) ((base)->GATE14) +#define SEMA4_GATE15_REG(base) ((base)->GATE15) +#define SEMA4_CPINE_REG(base,index) ((base)->CPnINE[index].INE) +#define SEMA4_CPNTF_REG(base,index) ((base)->CPnNTF[index].NTF) #define SEMA4_RSTGT_REG(base) ((base)->RSTGT) #define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) /*! * @} */ /* end of group SEMA4_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- SEMA4 Register Masks ---------------------------------------------------------------------------- */ @@ -90790,70 +39740,70 @@ typedef struct { * @{ */ -/* Gate03 Bit Fields */ -#define SEMA4_GATE03_GTFSM_MASK 0x3u -#define SEMA4_GATE03_GTFSM_SHIFT 0 -#define SEMA4_GATE03_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE03_GTFSM_SHIFT))&SEMA4_GATE03_GTFSM_MASK) -/* Gate02 Bit Fields */ -#define SEMA4_GATE02_GTFSM_MASK 0x3u -#define SEMA4_GATE02_GTFSM_SHIFT 0 -#define SEMA4_GATE02_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE02_GTFSM_SHIFT))&SEMA4_GATE02_GTFSM_MASK) -/* Gate01 Bit Fields */ -#define SEMA4_GATE01_GTFSM_MASK 0x3u -#define SEMA4_GATE01_GTFSM_SHIFT 0 -#define SEMA4_GATE01_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE01_GTFSM_SHIFT))&SEMA4_GATE01_GTFSM_MASK) -/* Gate00 Bit Fields */ +/* GATE00 Bit Fields */ #define SEMA4_GATE00_GTFSM_MASK 0x3u #define SEMA4_GATE00_GTFSM_SHIFT 0 #define SEMA4_GATE00_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE00_GTFSM_SHIFT))&SEMA4_GATE00_GTFSM_MASK) -/* Gate07 Bit Fields */ -#define SEMA4_GATE07_GTFSM_MASK 0x3u -#define SEMA4_GATE07_GTFSM_SHIFT 0 -#define SEMA4_GATE07_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE07_GTFSM_SHIFT))&SEMA4_GATE07_GTFSM_MASK) -/* Gate06 Bit Fields */ -#define SEMA4_GATE06_GTFSM_MASK 0x3u -#define SEMA4_GATE06_GTFSM_SHIFT 0 -#define SEMA4_GATE06_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE06_GTFSM_SHIFT))&SEMA4_GATE06_GTFSM_MASK) -/* Gate05 Bit Fields */ -#define SEMA4_GATE05_GTFSM_MASK 0x3u -#define SEMA4_GATE05_GTFSM_SHIFT 0 -#define SEMA4_GATE05_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE05_GTFSM_SHIFT))&SEMA4_GATE05_GTFSM_MASK) -/* Gate04 Bit Fields */ +/* GATE01 Bit Fields */ +#define SEMA4_GATE01_GTFSM_MASK 0x3u +#define SEMA4_GATE01_GTFSM_SHIFT 0 +#define SEMA4_GATE01_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE01_GTFSM_SHIFT))&SEMA4_GATE01_GTFSM_MASK) +/* GATE02 Bit Fields */ +#define SEMA4_GATE02_GTFSM_MASK 0x3u +#define SEMA4_GATE02_GTFSM_SHIFT 0 +#define SEMA4_GATE02_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE02_GTFSM_SHIFT))&SEMA4_GATE02_GTFSM_MASK) +/* GATE03 Bit Fields */ +#define SEMA4_GATE03_GTFSM_MASK 0x3u +#define SEMA4_GATE03_GTFSM_SHIFT 0 +#define SEMA4_GATE03_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE03_GTFSM_SHIFT))&SEMA4_GATE03_GTFSM_MASK) +/* GATE04 Bit Fields */ #define SEMA4_GATE04_GTFSM_MASK 0x3u #define SEMA4_GATE04_GTFSM_SHIFT 0 #define SEMA4_GATE04_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE04_GTFSM_SHIFT))&SEMA4_GATE04_GTFSM_MASK) -/* Gate11 Bit Fields */ -#define SEMA4_GATE11_GTFSM_MASK 0x3u -#define SEMA4_GATE11_GTFSM_SHIFT 0 -#define SEMA4_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE11_GTFSM_SHIFT))&SEMA4_GATE11_GTFSM_MASK) -/* Gate10 Bit Fields */ -#define SEMA4_GATE10_GTFSM_MASK 0x3u -#define SEMA4_GATE10_GTFSM_SHIFT 0 -#define SEMA4_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE10_GTFSM_SHIFT))&SEMA4_GATE10_GTFSM_MASK) -/* Gate09 Bit Fields */ -#define SEMA4_GATE09_GTFSM_MASK 0x3u -#define SEMA4_GATE09_GTFSM_SHIFT 0 -#define SEMA4_GATE09_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE09_GTFSM_SHIFT))&SEMA4_GATE09_GTFSM_MASK) -/* Gate08 Bit Fields */ +/* GATE05 Bit Fields */ +#define SEMA4_GATE05_GTFSM_MASK 0x3u +#define SEMA4_GATE05_GTFSM_SHIFT 0 +#define SEMA4_GATE05_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE05_GTFSM_SHIFT))&SEMA4_GATE05_GTFSM_MASK) +/* GATE06 Bit Fields */ +#define SEMA4_GATE06_GTFSM_MASK 0x3u +#define SEMA4_GATE06_GTFSM_SHIFT 0 +#define SEMA4_GATE06_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE06_GTFSM_SHIFT))&SEMA4_GATE06_GTFSM_MASK) +/* GATE07 Bit Fields */ +#define SEMA4_GATE07_GTFSM_MASK 0x3u +#define SEMA4_GATE07_GTFSM_SHIFT 0 +#define SEMA4_GATE07_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE07_GTFSM_SHIFT))&SEMA4_GATE07_GTFSM_MASK) +/* GATE08 Bit Fields */ #define SEMA4_GATE08_GTFSM_MASK 0x3u #define SEMA4_GATE08_GTFSM_SHIFT 0 #define SEMA4_GATE08_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE08_GTFSM_SHIFT))&SEMA4_GATE08_GTFSM_MASK) -/* Gate15 Bit Fields */ -#define SEMA4_GATE15_GTFSM_MASK 0x3u -#define SEMA4_GATE15_GTFSM_SHIFT 0 -#define SEMA4_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE15_GTFSM_SHIFT))&SEMA4_GATE15_GTFSM_MASK) -/* Gate14 Bit Fields */ -#define SEMA4_GATE14_GTFSM_MASK 0x3u -#define SEMA4_GATE14_GTFSM_SHIFT 0 -#define SEMA4_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE14_GTFSM_SHIFT))&SEMA4_GATE14_GTFSM_MASK) -/* Gate13 Bit Fields */ -#define SEMA4_GATE13_GTFSM_MASK 0x3u -#define SEMA4_GATE13_GTFSM_SHIFT 0 -#define SEMA4_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE13_GTFSM_SHIFT))&SEMA4_GATE13_GTFSM_MASK) -/* Gate12 Bit Fields */ +/* GATE09 Bit Fields */ +#define SEMA4_GATE09_GTFSM_MASK 0x3u +#define SEMA4_GATE09_GTFSM_SHIFT 0 +#define SEMA4_GATE09_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE09_GTFSM_SHIFT))&SEMA4_GATE09_GTFSM_MASK) +/* GATE10 Bit Fields */ +#define SEMA4_GATE10_GTFSM_MASK 0x3u +#define SEMA4_GATE10_GTFSM_SHIFT 0 +#define SEMA4_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE10_GTFSM_SHIFT))&SEMA4_GATE10_GTFSM_MASK) +/* GATE11 Bit Fields */ +#define SEMA4_GATE11_GTFSM_MASK 0x3u +#define SEMA4_GATE11_GTFSM_SHIFT 0 +#define SEMA4_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE11_GTFSM_SHIFT))&SEMA4_GATE11_GTFSM_MASK) +/* GATE12 Bit Fields */ #define SEMA4_GATE12_GTFSM_MASK 0x3u #define SEMA4_GATE12_GTFSM_SHIFT 0 #define SEMA4_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE12_GTFSM_SHIFT))&SEMA4_GATE12_GTFSM_MASK) +/* GATE13 Bit Fields */ +#define SEMA4_GATE13_GTFSM_MASK 0x3u +#define SEMA4_GATE13_GTFSM_SHIFT 0 +#define SEMA4_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE13_GTFSM_SHIFT))&SEMA4_GATE13_GTFSM_MASK) +/* GATE14 Bit Fields */ +#define SEMA4_GATE14_GTFSM_MASK 0x3u +#define SEMA4_GATE14_GTFSM_SHIFT 0 +#define SEMA4_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE14_GTFSM_SHIFT))&SEMA4_GATE14_GTFSM_MASK) +/* GATE15 Bit Fields */ +#define SEMA4_GATE15_GTFSM_MASK 0x3u +#define SEMA4_GATE15_GTFSM_SHIFT 0 +#define SEMA4_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE15_GTFSM_SHIFT))&SEMA4_GATE15_GTFSM_MASK) /* CPINE Bit Fields */ #define SEMA4_CPINE_INE7_MASK 0x1u #define SEMA4_CPINE_INE7_SHIFT 0 @@ -90939,18 +39889,18 @@ typedef struct { * @} */ /* end of group SEMA4_Register_Masks */ - /* SEMA4 - Peripheral instance base addresses */ /** Peripheral SEMA4 base address */ #define SEMA4_BASE (0x30AC0000u) /** Peripheral SEMA4 base pointer */ #define SEMA4 ((SEMA4_Type *)SEMA4_BASE) #define SEMA4_BASE_PTR (SEMA4) -/** Array initializer of SEMA4 peripheral base adresses */ +/** Array initializer of SEMA4 peripheral base addresses */ #define SEMA4_BASE_ADDRS { SEMA4_BASE } /** Array initializer of SEMA4 peripheral base pointers */ #define SEMA4_BASE_PTRS { SEMA4 } - +/** Interrupt vectors for the SEMA4 peripheral type */ +#define SEMA4_IRQS { SEMA4_HS_M4_IRQn } /* ---------------------------------------------------------------------------- -- SEMA4 - Register accessor macros ---------------------------------------------------------------------------- */ @@ -90963,33 +39913,31 @@ typedef struct { /* SEMA4 - Register instance definitions */ /* SEMA4 */ -#define SEMA4_GATE03 SEMA4_GATE03_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE02 SEMA4_GATE02_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE01 SEMA4_GATE01_REG(SEMA4_BASE_PTR) #define SEMA4_GATE00 SEMA4_GATE00_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE07 SEMA4_GATE07_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE06 SEMA4_GATE06_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE05 SEMA4_GATE05_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE01 SEMA4_GATE01_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE02 SEMA4_GATE02_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE03 SEMA4_GATE03_REG(SEMA4_BASE_PTR) #define SEMA4_GATE04 SEMA4_GATE04_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE11 SEMA4_GATE11_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE10 SEMA4_GATE10_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE09 SEMA4_GATE09_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE05 SEMA4_GATE05_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE06 SEMA4_GATE06_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE07 SEMA4_GATE07_REG(SEMA4_BASE_PTR) #define SEMA4_GATE08 SEMA4_GATE08_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE15 SEMA4_GATE15_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE14 SEMA4_GATE14_REG(SEMA4_BASE_PTR) -#define SEMA4_GATE13 SEMA4_GATE13_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE09 SEMA4_GATE09_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE10 SEMA4_GATE10_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE11 SEMA4_GATE11_REG(SEMA4_BASE_PTR) #define SEMA4_GATE12 SEMA4_GATE12_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE13 SEMA4_GATE13_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE14 SEMA4_GATE14_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE15 SEMA4_GATE15_REG(SEMA4_BASE_PTR) #define SEMA4_CP0INE SEMA4_CPINE_REG(SEMA4_BASE_PTR,0) #define SEMA4_CP1INE SEMA4_CPINE_REG(SEMA4_BASE_PTR,1) #define SEMA4_CP0NTF SEMA4_CPNTF_REG(SEMA4_BASE_PTR,0) #define SEMA4_CP1NTF SEMA4_CPNTF_REG(SEMA4_BASE_PTR,1) #define SEMA4_RSTGT SEMA4_RSTGT_REG(SEMA4_BASE_PTR) #define SEMA4_RSTNTF SEMA4_RSTNTF_REG(SEMA4_BASE_PTR) - /* SEMA4 - Register array accessors */ #define SEMA4_CPINE(index) SEMA4_CPINE_REG(SEMA4_BASE_PTR,index) #define SEMA4_CPNTF(index) SEMA4_CPNTF_REG(SEMA4_BASE_PTR,index) - /*! * @} */ /* end of group SEMA4_Register_Accessor_Macros */ @@ -90999,7 +39947,6 @@ typedef struct { * @} */ /* end of group SEMA4_Peripheral */ - /* ---------------------------------------------------------------------------- -- SJC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -91012,34 +39959,33 @@ typedef struct { /** SJC - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[4]; - __IO uint32_t DCR; /**< Debug Control Register, offset: 0x4 */ - } DCR; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[7]; - __IO uint32_t GPCCR; /**< General Purpose Clocks Control Register, offset: 0x7 */ - } GPCCR; - struct { /* offset: 0x0 */ - uint8_t RESERVED_0[3]; - __I uint32_t GPSSR; /**< General Purpose Secured Status Register, offset: 0x3 */ - } GPSSR; - __I uint32_t GPUSR1; /**< General Purpose Unsecured Status Register 1, offset: 0x0 */ - struct { /* offset: 0x0 */ + __I uint32_t GPUSR1; /**< General Purpose Unsecured Status Register 1,offset: 0x0 */ + struct { /* offset: 0x1 */ uint8_t RESERVED_0[1]; - __I uint32_t GPUSR2; /**< General Purpose Unsecured Status Register 2, offset: 0x1 */ + __I uint32_t GPUSR2; /**< General Purpose Unsecured Status Register 2,offset: 0x1 */ } GPUSR2; - struct { /* offset: 0x0 */ + struct { /* offset: 0x2 */ uint8_t RESERVED_0[2]; - __I uint32_t GPUSR3; /**< General Purpose Unsecured Status Register 3, offset: 0x2 */ + __I uint32_t GPUSR3; /**< General Purpose Unsecured Status Register 3,offset: 0x2 */ } GPUSR3; - struct { /* offset: 0x0 */ + struct { /* offset: 0x3 */ + uint8_t RESERVED_0[3]; + __I uint32_t GPSSR; /**< General Purpose Secured Status Register,offset: 0x3 */ + } GPSSR; + struct { /* offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< Debug Control Register,offset: 0x4 */ + } DCR; + struct { /* offset: 0x5 */ uint8_t RESERVED_0[5]; - __I uint32_t SSR; /**< Security Status Register, offset: 0x5 */ + __I uint32_t SSR; /**< Security Status Register,offset: 0x5 */ } SSR; + struct { /* offset: 0x7 */ + uint8_t RESERVED_0[7]; + __IO uint32_t GPCCR; /**< General Purpose Clocks Control Register,offset: 0x7 */ + } GPCCR; }; } SJC_Type, *SJC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- SJC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -91051,19 +39997,17 @@ typedef struct { /* SJC - Register accessors */ -#define SJC_DCR_REG(base) ((base)->DCR.DCR) -#define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) -#define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) #define SJC_GPUSR1_REG(base) ((base)->GPUSR1) #define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) #define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) +#define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) +#define SJC_DCR_REG(base) ((base)->DCR.DCR) #define SJC_SSR_REG(base) ((base)->SSR.SSR) +#define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) /*! * @} */ /* end of group SJC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- SJC Register Masks ---------------------------------------------------------------------------- */ @@ -91073,26 +40017,6 @@ typedef struct { * @{ */ -/* DCR Bit Fields */ -#define SJC_DCR_DE_TO_ARM_MASK 0x1u -#define SJC_DCR_DE_TO_ARM_SHIFT 0 -#define SJC_DCR_DE_TO_SDMA_MASK 0x2u -#define SJC_DCR_DE_TO_SDMA_SHIFT 1 -#define SJC_DCR_DEBUG_OBS_MASK 0x8u -#define SJC_DCR_DEBUG_OBS_SHIFT 3 -#define SJC_DCR_DIRECT_SDMA_REQ_EN_MASK 0x20u -#define SJC_DCR_DIRECT_SDMA_REQ_EN_SHIFT 5 -#define SJC_DCR_DIRECT_ARM_REQ_EN_MASK 0x40u -#define SJC_DCR_DIRECT_ARM_REQ_EN_SHIFT 6 -/* GPCCR Bit Fields */ -#define SJC_GPCCR_SCLKR_MASK 0x1u -#define SJC_GPCCR_SCLKR_SHIFT 0 -#define SJC_GPCCR_ACLKOFFDIS_MASK 0x2u -#define SJC_GPCCR_ACLKOFFDIS_SHIFT 1 -/* GPSSR Bit Fields */ -#define SJC_GPSSR_GPSSR_MASK 0xFFFFFFFFu -#define SJC_GPSSR_GPSSR_SHIFT 0 -#define SJC_GPSSR_GPSSR(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPSSR_GPSSR_SHIFT))&SJC_GPSSR_GPSSR_MASK) /* GPUSR1 Bit Fields */ #define SJC_GPUSR1_A_DBG_MASK 0x1u #define SJC_GPUSR1_A_DBG_SHIFT 0 @@ -91120,6 +40044,21 @@ typedef struct { #define SJC_GPUSR3_IPG_STOP_SHIFT 1 #define SJC_GPUSR3_SYS_WAIT_MASK 0x4u #define SJC_GPUSR3_SYS_WAIT_SHIFT 2 +/* GPSSR Bit Fields */ +#define SJC_GPSSR_GPSSR_MASK 0xFFFFFFFFu +#define SJC_GPSSR_GPSSR_SHIFT 0 +#define SJC_GPSSR_GPSSR(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPSSR_GPSSR_SHIFT))&SJC_GPSSR_GPSSR_MASK) +/* DCR Bit Fields */ +#define SJC_DCR_DE_TO_ARM_MASK 0x1u +#define SJC_DCR_DE_TO_ARM_SHIFT 0 +#define SJC_DCR_DE_TO_SDMA_MASK 0x2u +#define SJC_DCR_DE_TO_SDMA_SHIFT 1 +#define SJC_DCR_DEBUG_OBS_MASK 0x8u +#define SJC_DCR_DEBUG_OBS_SHIFT 3 +#define SJC_DCR_DIRECT_SDMA_REQ_EN_MASK 0x20u +#define SJC_DCR_DIRECT_SDMA_REQ_EN_SHIFT 5 +#define SJC_DCR_DIRECT_ARM_REQ_EN_MASK 0x40u +#define SJC_DCR_DIRECT_ARM_REQ_EN_SHIFT 6 /* SSR Bit Fields */ #define SJC_SSR_KTF_MASK 0x1u #define SJC_SSR_KTF_SHIFT 0 @@ -91143,23 +40082,26 @@ typedef struct { #define SJC_SSR_RSSTAT(x) (((uint32_t)(((uint32_t)(x))<<SJC_SSR_RSSTAT_SHIFT))&SJC_SSR_RSSTAT_MASK) #define SJC_SSR_BOOTIND_MASK 0x4000u #define SJC_SSR_BOOTIND_SHIFT 14 +/* GPCCR Bit Fields */ +#define SJC_GPCCR_SCLKR_MASK 0x1u +#define SJC_GPCCR_SCLKR_SHIFT 0 +#define SJC_GPCCR_ACLKOFFDIS_MASK 0x2u +#define SJC_GPCCR_ACLKOFFDIS_SHIFT 1 /*! * @} */ /* end of group SJC_Register_Masks */ - /* SJC - Peripheral instance base addresses */ /** Peripheral SJC base address */ -#define SJC_BASE (0u) +#define SJC_BASE (0x0u) /** Peripheral SJC base pointer */ #define SJC ((SJC_Type *)SJC_BASE) #define SJC_BASE_PTR (SJC) -/** Array initializer of SJC peripheral base adresses */ +/** Array initializer of SJC peripheral base addresses */ #define SJC_BASE_ADDRS { SJC_BASE } /** Array initializer of SJC peripheral base pointers */ #define SJC_BASE_PTRS { SJC } - /* ---------------------------------------------------------------------------- -- SJC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -91179,7 +40121,6 @@ typedef struct { #define SJC_DCR SJC_DCR_REG(SJC_BASE_PTR) #define SJC_SSR SJC_SSR_REG(SJC_BASE_PTR) #define SJC_GPCCR SJC_GPCCR_REG(SJC_BASE_PTR) - /*! * @} */ /* end of group SJC_Register_Accessor_Macros */ @@ -91189,7 +40130,6 @@ typedef struct { * @} */ /* end of group SJC_Peripheral */ - /* ---------------------------------------------------------------------------- -- SNVS Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -91201,30 +40141,29 @@ typedef struct { /** SNVS - Register Layout Typedef */ typedef struct { - __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ - __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ - __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + __IO uint32_t HPLR; /**< , offset: 0x0 */ + __IO uint32_t HPCOMR; /**< , offset: 0x4 */ + __IO uint32_t HPCR; /**< , offset: 0x8 */ uint8_t RESERVED_0[8]; - __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + __IO uint32_t HPSR; /**< , offset: 0x14 */ uint8_t RESERVED_1[12]; - __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ - __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ - __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ - __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ - __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ - __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + __IO uint32_t HPRTCMR; /**< , offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< , offset: 0x28 */ + __IO uint32_t HPTAMR; /**< , offset: 0x2C */ + __IO uint32_t HPTALR; /**< , offset: 0x30 */ + __IO uint32_t LPLR; /**< , offset: 0x34 */ + __IO uint32_t LPCR; /**< , offset: 0x38 */ uint8_t RESERVED_2[16]; - __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + __IO uint32_t LPSR; /**< , offset: 0x4C */ uint8_t RESERVED_3[12]; - __IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ - __IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + __IO uint32_t LPSMCMR; /**< , offset: 0x5C */ + __IO uint32_t LPSMCLR; /**< , offset: 0x60 */ uint8_t RESERVED_4[4]; - __IO uint32_t LPGPR; /**< SNVS_LP General Purpose Register, offset: 0x68 */ + __IO uint32_t LPGPR; /**< , offset: 0x68 */ uint8_t RESERVED_5[2956]; - __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ - __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ + __I uint32_t HPVIDR1; /**< , offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< , offset: 0xBFC */ } SNVS_Type, *SNVS_MemMapPtr; - /* ---------------------------------------------------------------------------- -- SNVS - Register accessor macros ---------------------------------------------------------------------------- */ @@ -91256,8 +40195,6 @@ typedef struct { /*! * @} */ /* end of group SNVS_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- SNVS Register Masks ---------------------------------------------------------------------------- */ @@ -91397,18 +40334,18 @@ typedef struct { * @} */ /* end of group SNVS_Register_Masks */ - /* SNVS - Peripheral instance base addresses */ /** Peripheral SNVS base address */ -#define SNVS_BASE (0x3037C000u) +#define SNVS_BASE (0x30370000u) /** Peripheral SNVS base pointer */ #define SNVS ((SNVS_Type *)SNVS_BASE) #define SNVS_BASE_PTR (SNVS) -/** Array initializer of SNVS peripheral base adresses */ +/** Array initializer of SNVS peripheral base addresses */ #define SNVS_BASE_ADDRS { SNVS_BASE } /** Array initializer of SNVS peripheral base pointers */ #define SNVS_BASE_PTRS { SNVS } - +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_IRQn } /* ---------------------------------------------------------------------------- -- SNVS - Register accessor macros ---------------------------------------------------------------------------- */ @@ -91437,7 +40374,6 @@ typedef struct { #define SNVS_LPGPR SNVS_LPGPR_REG(SNVS_BASE_PTR) #define SNVS_HPVIDR1 SNVS_HPVIDR1_REG(SNVS_BASE_PTR) #define SNVS_HPVIDR2 SNVS_HPVIDR2_REG(SNVS_BASE_PTR) - /*! * @} */ /* end of group SNVS_Register_Accessor_Macros */ @@ -91447,7 +40383,6 @@ typedef struct { * @} */ /* end of group SNVS_Peripheral */ - /* ---------------------------------------------------------------------------- -- SPBA Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -91461,7 +40396,6 @@ typedef struct { typedef struct { __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ } SPBA_Type, *SPBA_MemMapPtr; - /* ---------------------------------------------------------------------------- -- SPBA - Register accessor macros ---------------------------------------------------------------------------- */ @@ -91478,8 +40412,6 @@ typedef struct { /*! * @} */ /* end of group SPBA_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- SPBA Register Masks ---------------------------------------------------------------------------- */ @@ -91507,18 +40439,16 @@ typedef struct { * @} */ /* end of group SPBA_Register_Masks */ - /* SPBA - Peripheral instance base addresses */ /** Peripheral SPBA base address */ #define SPBA_BASE (0x308F0000u) /** Peripheral SPBA base pointer */ #define SPBA ((SPBA_Type *)SPBA_BASE) #define SPBA_BASE_PTR (SPBA) -/** Array initializer of SPBA peripheral base adresses */ +/** Array initializer of SPBA peripheral base addresses */ #define SPBA_BASE_ADDRS { SPBA_BASE } /** Array initializer of SPBA peripheral base pointers */ #define SPBA_BASE_PTRS { SPBA } - /* ---------------------------------------------------------------------------- -- SPBA - Register accessor macros ---------------------------------------------------------------------------- */ @@ -91563,10 +40493,8 @@ typedef struct { #define SPBA_PRR29 SPBA_PRR_REG(SPBA_BASE_PTR,29) #define SPBA_PRR30 SPBA_PRR_REG(SPBA_BASE_PTR,30) #define SPBA_PRR31 SPBA_PRR_REG(SPBA_BASE_PTR,31) - /* SPBA - Register array accessors */ #define SPBA_PRR(index) SPBA_PRR_REG(SPBA_BASE_PTR,index) - /*! * @} */ /* end of group SPBA_Register_Accessor_Macros */ @@ -91576,7 +40504,6 @@ typedef struct { * @} */ /* end of group SPBA_Peripheral */ - /* ---------------------------------------------------------------------------- -- SRC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -91620,7 +40547,6 @@ typedef struct { uint8_t RESERVED_4[3940]; __IO uint32_t DDRC_RCR; /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */ } SRC_Type, *SRC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- SRC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -91662,8 +40588,6 @@ typedef struct { /*! * @} */ /* end of group SRC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- SRC Register Masks ---------------------------------------------------------------------------- */ @@ -91977,6 +40901,12 @@ typedef struct { #define SRC_GPR4_PERSISTENT_ARG1_MASK 0xFFFFFFFFu #define SRC_GPR4_PERSISTENT_ARG1_SHIFT 0 #define SRC_GPR4_PERSISTENT_ARG1(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR4_PERSISTENT_ARG1_SHIFT))&SRC_GPR4_PERSISTENT_ARG1_MASK) +/* GPR5 Bit Fields */ +/* GPR6 Bit Fields */ +/* GPR7 Bit Fields */ +/* GPR8 Bit Fields */ +/* GPR9 Bit Fields */ +/* GPR10 Bit Fields */ /* DDRC_RCR Bit Fields */ #define SRC_DDRC_RCR_DDRC_PRST_MASK 0x1u #define SRC_DDRC_RCR_DDRC_PRST_SHIFT 0 @@ -91999,18 +40929,18 @@ typedef struct { * @} */ /* end of group SRC_Register_Masks */ - /* SRC - Peripheral instance base addresses */ /** Peripheral SRC base address */ #define SRC_BASE (0x30390000u) /** Peripheral SRC base pointer */ #define SRC ((SRC_Type *)SRC_BASE) #define SRC_BASE_PTR (SRC) -/** Array initializer of SRC peripheral base adresses */ +/** Array initializer of SRC peripheral base addresses */ #define SRC_BASE_ADDRS { SRC_BASE } /** Array initializer of SRC peripheral base pointers */ #define SRC_BASE_PTRS { SRC } - +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } /* ---------------------------------------------------------------------------- -- SRC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -92049,7 +40979,6 @@ typedef struct { #define SRC_GPR9 SRC_GPR9_REG(SRC_BASE_PTR) #define SRC_GPR10 SRC_GPR10_REG(SRC_BASE_PTR) #define SRC_DDRC_RCR SRC_DDRC_RCR_REG(SRC_BASE_PTR) - /*! * @} */ /* end of group SRC_Register_Accessor_Macros */ @@ -92059,7 +40988,6 @@ typedef struct { * @} */ /* end of group SRC_Peripheral */ - /* ---------------------------------------------------------------------------- -- TEMPMON Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -92085,7 +41013,6 @@ typedef struct { __IO uint32_t HW_ANADIG_TEMPSENSE_TRIM_CLR; /**< Anadig Tempsensor Trim Control Register, offset: 0x328 */ __IO uint32_t HW_ANADIG_TEMPSENSE_TRIM_TOG; /**< Anadig Tempsensor Trim Control Register, offset: 0x32C */ } TEMPMON_Type, *TEMPMON_MemMapPtr; - /* ---------------------------------------------------------------------------- -- TEMPMON - Register accessor macros ---------------------------------------------------------------------------- */ @@ -92113,8 +41040,6 @@ typedef struct { /*! * @} */ /* end of group TEMPMON_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- TEMPMON Register Masks ---------------------------------------------------------------------------- */ @@ -92341,18 +41266,16 @@ typedef struct { * @} */ /* end of group TEMPMON_Register_Masks */ - /* TEMPMON - Peripheral instance base addresses */ /** Peripheral TEMPMON base address */ #define TEMPMON_BASE (0x30360000u) /** Peripheral TEMPMON base pointer */ #define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) #define TEMPMON_BASE_PTR (TEMPMON) -/** Array initializer of TEMPMON peripheral base adresses */ +/** Array initializer of TEMPMON peripheral base addresses */ #define TEMPMON_BASE_ADDRS { TEMPMON_BASE } /** Array initializer of TEMPMON peripheral base pointers */ #define TEMPMON_BASE_PTRS { TEMPMON } - /* ---------------------------------------------------------------------------- -- TEMPMON - Register accessor macros ---------------------------------------------------------------------------- */ @@ -92377,7 +41300,6 @@ typedef struct { #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_REG(TEMPMON_BASE_PTR) #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_REG(TEMPMON_BASE_PTR) #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_REG(TEMPMON_BASE_PTR) - /*! * @} */ /* end of group TEMPMON_Register_Accessor_Macros */ @@ -92387,7 +41309,6 @@ typedef struct { * @} */ /* end of group TEMPMON_Peripheral */ - /* ---------------------------------------------------------------------------- -- UART Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -92419,7 +41340,6 @@ typedef struct { __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ } UART_Type, *UART_MemMapPtr; - /* ---------------------------------------------------------------------------- -- UART - Register accessor macros ---------------------------------------------------------------------------- */ @@ -92452,8 +41372,6 @@ typedef struct { /*! * @} */ /* end of group UART_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- UART Register Masks ---------------------------------------------------------------------------- */ @@ -92737,7 +41655,6 @@ typedef struct { * @} */ /* end of group UART_Register_Masks */ - /* UART - Peripheral instance base addresses */ /** Peripheral UART1 base address */ #define UART1_BASE (0x30860000u) @@ -92774,12 +41691,12 @@ typedef struct { /** Peripheral UART7 base pointer */ #define UART7 ((UART_Type *)UART7_BASE) #define UART7_BASE_PTR (UART7) -/** Array initializer of UART peripheral base adresses */ +/** Array initializer of UART peripheral base addresses */ #define UART_BASE_ADDRS { UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE, UART7_BASE } /** Array initializer of UART peripheral base pointers */ #define UART_BASE_PTRS { UART1, UART2, UART3, UART4, UART5, UART6, UART7 } /** Interrupt vectors for the UART peripheral type */ -#define UART_IRQS { UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn } +#define UART_IRQS { UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn, UART7_IRQn } /* ---------------------------------------------------------------------------- -- UART - Register accessor macros ---------------------------------------------------------------------------- */ @@ -92899,7 +41816,24 @@ typedef struct { #define UART6_ONEMS UART_ONEMS_REG(UART6_BASE_PTR) #define UART6_UTS UART_UTS_REG(UART6_BASE_PTR) #define UART6_UMCR UART_UMCR_REG(UART6_BASE_PTR) - +/* UART7 */ +#define UART7_URXD UART_URXD_REG(UART7_BASE_PTR) +#define UART7_UTXD UART_UTXD_REG(UART7_BASE_PTR) +#define UART7_UCR1 UART_UCR1_REG(UART7_BASE_PTR) +#define UART7_UCR2 UART_UCR2_REG(UART7_BASE_PTR) +#define UART7_UCR3 UART_UCR3_REG(UART7_BASE_PTR) +#define UART7_UCR4 UART_UCR4_REG(UART7_BASE_PTR) +#define UART7_UFCR UART_UFCR_REG(UART7_BASE_PTR) +#define UART7_USR1 UART_USR1_REG(UART7_BASE_PTR) +#define UART7_USR2 UART_USR2_REG(UART7_BASE_PTR) +#define UART7_UESC UART_UESC_REG(UART7_BASE_PTR) +#define UART7_UTIM UART_UTIM_REG(UART7_BASE_PTR) +#define UART7_UBIR UART_UBIR_REG(UART7_BASE_PTR) +#define UART7_UBMR UART_UBMR_REG(UART7_BASE_PTR) +#define UART7_UBRC UART_UBRC_REG(UART7_BASE_PTR) +#define UART7_ONEMS UART_ONEMS_REG(UART7_BASE_PTR) +#define UART7_UTS UART_UTS_REG(UART7_BASE_PTR) +#define UART7_UMCR UART_UMCR_REG(UART7_BASE_PTR) /*! * @} */ /* end of group UART_Register_Accessor_Macros */ @@ -92909,7 +41843,6 @@ typedef struct { * @} */ /* end of group UART_Peripheral */ - /* ---------------------------------------------------------------------------- -- USB Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -92934,7 +41867,7 @@ typedef struct { __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ uint8_t RESERVED_1[108]; - __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ uint8_t RESERVED_2[1]; __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ @@ -92950,12 +41883,16 @@ typedef struct { __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ uint8_t RESERVED_6[4]; union { /* offset: 0x154 */ - __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ - __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ - }; - union { /* offset: 0x158 */ - __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ - __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address,offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address,offset: 0x154 */ + struct { /* offset: 0x158 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address,offset: 0x158 */ + } ASYNCLISTADDR; + struct { /* offset: 0x158 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address,offset: 0x158 */ + } ENDPTLISTADDR; }; uint8_t RESERVED_7[4]; __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ @@ -92982,7 +41919,6 @@ typedef struct { __IO uint32_t ENDPTCTRL6; /**< Endpoint Control 6, offset: 0x1D8 */ __IO uint32_t ENDPTCTRL7; /**< Endpoint Control 7, offset: 0x1DC */ } USB_Type, *USB_MemMapPtr; - /* ---------------------------------------------------------------------------- -- USB - Register accessor macros ---------------------------------------------------------------------------- */ @@ -93015,10 +41951,10 @@ typedef struct { #define USB_USBSTS_REG(base) ((base)->USBSTS) #define USB_USBINTR_REG(base) ((base)->USBINTR) #define USB_FRINDEX_REG(base) ((base)->FRINDEX) -#define USB_DEVICEADDR_REG(base) ((base)->DEVICEADDR) #define USB_PERIODICLISTBASE_REG(base) ((base)->PERIODICLISTBASE) -#define USB_ASYNCLISTADDR_REG(base) ((base)->ASYNCLISTADDR) -#define USB_ENDPTLISTADDR_REG(base) ((base)->ENDPTLISTADDR) +#define USB_DEVICEADDR_REG(base) ((base)->DEVICEADDR) +#define USB_ASYNCLISTADDR_REG(base) ((base)->ASYNCLISTADDR.ASYNCLISTADDR) +#define USB_ENDPTLISTADDR_REG(base) ((base)->ENDPTLISTADDR.ENDPTLISTADDR) #define USB_BURSTSIZE_REG(base) ((base)->BURSTSIZE) #define USB_TXFILLTUNING_REG(base) ((base)->TXFILLTUNING) #define USB_ENDPTNAK_REG(base) ((base)->ENDPTNAK) @@ -93044,8 +41980,6 @@ typedef struct { /*! * @} */ /* end of group USB_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ @@ -93284,16 +42218,16 @@ typedef struct { #define USB_FRINDEX_FRINDEX_MASK 0x3FFFu #define USB_FRINDEX_FRINDEX_SHIFT 0 #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x))<<USB_FRINDEX_FRINDEX_SHIFT))&USB_FRINDEX_FRINDEX_MASK) +/* PERIODICLISTBASE Bit Fields */ +#define USB_PERIODICLISTBASE_BASEADR_MASK 0xFFFFF000u +#define USB_PERIODICLISTBASE_BASEADR_SHIFT 12 +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x))<<USB_PERIODICLISTBASE_BASEADR_SHIFT))&USB_PERIODICLISTBASE_BASEADR_MASK) /* DEVICEADDR Bit Fields */ #define USB_DEVICEADDR_USBADRA_MASK 0x1000000u #define USB_DEVICEADDR_USBADRA_SHIFT 24 #define USB_DEVICEADDR_USBADR_MASK 0xFE000000u #define USB_DEVICEADDR_USBADR_SHIFT 25 #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x))<<USB_DEVICEADDR_USBADR_SHIFT))&USB_DEVICEADDR_USBADR_MASK) -/* PERIODICLISTBASE Bit Fields */ -#define USB_PERIODICLISTBASE_BASEADR_MASK 0xFFFFF000u -#define USB_PERIODICLISTBASE_BASEADR_SHIFT 12 -#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x))<<USB_PERIODICLISTBASE_BASEADR_SHIFT))&USB_PERIODICLISTBASE_BASEADR_MASK) /* ASYNCLISTADDR Bit Fields */ #define USB_ASYNCLISTADDR_ASYBASE_MASK 0xFFFFFFE0u #define USB_ASYNCLISTADDR_ASYBASE_SHIFT 5 @@ -93413,8 +42347,8 @@ typedef struct { #define USB_OTGSC_BSV_SHIFT 11 #define USB_OTGSC_BSE_MASK 0x1000u #define USB_OTGSC_BSE_SHIFT 12 -#define USB_OTGSC_TOGGLE_1MS_MASK 0x2000u -#define USB_OTGSC_TOGGLE_1MS_SHIFT 13 +#define USB_OTGSC_TOG_1MS_MASK 0x2000u +#define USB_OTGSC_TOG_1MS_SHIFT 13 #define USB_OTGSC_DPS_MASK 0x4000u #define USB_OTGSC_DPS_SHIFT 14 #define USB_OTGSC_IDIS_MASK 0x10000u @@ -93427,8 +42361,8 @@ typedef struct { #define USB_OTGSC_BSVIS_SHIFT 19 #define USB_OTGSC_BSEIS_MASK 0x100000u #define USB_OTGSC_BSEIS_SHIFT 20 -#define USB_OTGSC_RW2CLEAR_1MS_MASK 0x200000u -#define USB_OTGSC_RW2CLEAR_1MS_SHIFT 21 +#define USB_OTGSC_STATUS_1MS_MASK 0x200000u +#define USB_OTGSC_STATUS_1MS_SHIFT 21 #define USB_OTGSC_DPIS_MASK 0x400000u #define USB_OTGSC_DPIS_SHIFT 22 #define USB_OTGSC_IDIE_MASK 0x1000000u @@ -93441,8 +42375,8 @@ typedef struct { #define USB_OTGSC_BSVIE_SHIFT 27 #define USB_OTGSC_BSEIE_MASK 0x10000000u #define USB_OTGSC_BSEIE_SHIFT 28 -#define USB_OTGSC_INT_EN_1MS_MASK 0x20000000u -#define USB_OTGSC_INT_EN_1MS_SHIFT 29 +#define USB_OTGSC_EN_1MS_MASK 0x20000000u +#define USB_OTGSC_EN_1MS_SHIFT 29 #define USB_OTGSC_DPIE_MASK 0x40000000u #define USB_OTGSC_DPIE_SHIFT 30 /* USBMODE Bit Fields */ @@ -93696,7 +42630,6 @@ typedef struct { * @} */ /* end of group USB_Register_Masks */ - /* USB - Peripheral instance base addresses */ /** Peripheral USB1 base address */ #define USB1_BASE (0x30B10000u) @@ -93713,11 +42646,10 @@ typedef struct { /** Peripheral USB3 base pointer */ #define USB3 ((USB_Type *)USB3_BASE) #define USB3_BASE_PTR (USB3) -/** Array initializer of USB peripheral base adresses */ +/** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS { USB1_BASE, USB2_BASE, USB3_BASE } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS { USB1, USB2, USB3 } - /* ---------------------------------------------------------------------------- -- USB - Register accessor macros ---------------------------------------------------------------------------- */ @@ -93751,8 +42683,8 @@ typedef struct { #define USB1_USBSTS USB_USBSTS_REG(USB1_BASE_PTR) #define USB1_USBINTR USB_USBINTR_REG(USB1_BASE_PTR) #define USB1_FRINDEX USB_FRINDEX_REG(USB1_BASE_PTR) -#define USB1_DEVICEADDR USB_DEVICEADDR_REG(USB1_BASE_PTR) #define USB1_PERIODICLISTBASE USB_PERIODICLISTBASE_REG(USB1_BASE_PTR) +#define USB1_DEVICEADDR USB_DEVICEADDR_REG(USB1_BASE_PTR) #define USB1_ASYNCLISTADDR USB_ASYNCLISTADDR_REG(USB1_BASE_PTR) #define USB1_ENDPTLISTADDR USB_ENDPTLISTADDR_REG(USB1_BASE_PTR) #define USB1_BURSTSIZE USB_BURSTSIZE_REG(USB1_BASE_PTR) @@ -93798,8 +42730,8 @@ typedef struct { #define USB2_USBSTS USB_USBSTS_REG(USB2_BASE_PTR) #define USB2_USBINTR USB_USBINTR_REG(USB2_BASE_PTR) #define USB2_FRINDEX USB_FRINDEX_REG(USB2_BASE_PTR) -#define USB2_DEVICEADDR USB_DEVICEADDR_REG(USB2_BASE_PTR) #define USB2_PERIODICLISTBASE USB_PERIODICLISTBASE_REG(USB2_BASE_PTR) +#define USB2_DEVICEADDR USB_DEVICEADDR_REG(USB2_BASE_PTR) #define USB2_ASYNCLISTADDR USB_ASYNCLISTADDR_REG(USB2_BASE_PTR) #define USB2_ENDPTLISTADDR USB_ENDPTLISTADDR_REG(USB2_BASE_PTR) #define USB2_BURSTSIZE USB_BURSTSIZE_REG(USB2_BASE_PTR) @@ -93845,8 +42777,8 @@ typedef struct { #define USB3_USBSTS USB_USBSTS_REG(USB3_BASE_PTR) #define USB3_USBINTR USB_USBINTR_REG(USB3_BASE_PTR) #define USB3_FRINDEX USB_FRINDEX_REG(USB3_BASE_PTR) -#define USB3_DEVICEADDR USB_DEVICEADDR_REG(USB3_BASE_PTR) #define USB3_PERIODICLISTBASE USB_PERIODICLISTBASE_REG(USB3_BASE_PTR) +#define USB3_DEVICEADDR USB_DEVICEADDR_REG(USB3_BASE_PTR) #define USB3_ASYNCLISTADDR USB_ASYNCLISTADDR_REG(USB3_BASE_PTR) #define USB3_ENDPTLISTADDR USB_ENDPTLISTADDR_REG(USB3_BASE_PTR) #define USB3_BURSTSIZE USB_BURSTSIZE_REG(USB3_BASE_PTR) @@ -93870,7 +42802,6 @@ typedef struct { #define USB3_ENDPTCTRL5 USB_ENDPTCTRL5_REG(USB3_BASE_PTR) #define USB3_ENDPTCTRL6 USB_ENDPTCTRL6_REG(USB3_BASE_PTR) #define USB3_ENDPTCTRL7 USB_ENDPTCTRL7_REG(USB3_BASE_PTR) - /*! * @} */ /* end of group USB_Register_Accessor_Macros */ @@ -93880,7 +42811,6 @@ typedef struct { * @} */ /* end of group USB_Peripheral */ - /* ---------------------------------------------------------------------------- -- USBNC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -93893,18 +42823,31 @@ typedef struct { /** USBNC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[512]; - __IO uint32_t USB_x_CTRL1; /**< , offset: 0x200 */ - __IO uint32_t USB_x_CTRL2; /**< , offset: 0x204 */ - uint8_t RESERVED_1[44]; - __IO uint32_t USB_x_PHY_CTL2; /**< , offset: 0x234 */ + __IO uint32_t OTG1_CTRL1; /**< , offset: 0x200 */ + __IO uint32_t OTG1_CTRL2; /**< , offset: 0x204 */ + uint8_t RESERVED_1[40]; + __IO uint32_t OTG1_PHY_CFG1; /**< , offset: 0x230 */ + __IO uint32_t OTG1_PHY_CFG2; /**< , offset: 0x234 */ uint8_t RESERVED_2[4]; - __IO uint32_t USB_x_PHY_STS; /**< , offset: 0x23C */ + __I uint32_t OTG1_PHY_STATUS; /**< , offset: 0x23C */ uint8_t RESERVED_3[16]; - __IO uint32_t ADP_CFG1; /**< , offset: 0x250 */ - __IO uint32_t ADP_CFG2; /**< , offset: 0x254 */ - __I uint32_t ADP_STATUS; /**< , offset: 0x258 */ + __IO uint32_t ADP_CFG1; /**< , offset: 0x250 */ + __IO uint32_t ADP_CFG2; /**< , offset: 0x254 */ + __I uint32_t ADP_STATUS; /**< , offset: 0x258 */ + uint8_t RESERVED_4[65444]; + __IO uint32_t OTG2_CTRL1; /**< , offset: 0x10200 */ + __IO uint32_t OTG2_CTRL2; /**< , offset: 0x10204 */ + uint8_t RESERVED_5[40]; + __IO uint32_t OTG2_PHY_CFG1; /**< , offset: 0x10230 */ + __IO uint32_t OTG2_PHY_CFG2; /**< , offset: 0x10234 */ + uint8_t RESERVED_6[4]; + __I uint32_t OTG2_PHY_STATUS; /**< , offset: 0x1023C */ + uint8_t RESERVED_7[65472]; + __IO uint32_t HSIC_CTRL1; /**< , offset: 0x20200 */ + __IO uint32_t HSIC_CTRL2; /**< , offset: 0x20204 */ + uint8_t RESERVED_8[56]; + __IO uint32_t UH_HSICPHY_CFG1; /**< , offset: 0x20240 */ } USBNC_Type, *USBNC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- USBNC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -93916,19 +42859,26 @@ typedef struct { /* USBNC - Register accessors */ -#define USBNC_USB_x_CTRL1_REG(base) ((base)->USB_x_CTRL1) -#define USBNC_USB_x_CTRL2_REG(base) ((base)->USB_x_CTRL2) -#define USBNC_USB_x_PHY_CTL2_REG(base) ((base)->USB_x_PHY_CTL2) -#define USBNC_USB_x_PHY_STS_REG(base) ((base)->USB_x_PHY_STS) +#define USBNC_OTG1_CTRL1_REG(base) ((base)->OTG1_CTRL1) +#define USBNC_OTG1_CTRL2_REG(base) ((base)->OTG1_CTRL2) +#define USBNC_OTG1_PHY_CFG1_REG(base) ((base)->OTG1_PHY_CFG1) +#define USBNC_OTG1_PHY_CFG2_REG(base) ((base)->OTG1_PHY_CFG2) +#define USBNC_OTG1_PHY_STATUS_REG(base) ((base)->OTG1_PHY_STATUS) #define USBNC_ADP_CFG1_REG(base) ((base)->ADP_CFG1) #define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) #define USBNC_ADP_STATUS_REG(base) ((base)->ADP_STATUS) +#define USBNC_OTG2_CTRL1_REG(base) ((base)->OTG2_CTRL1) +#define USBNC_OTG2_CTRL2_REG(base) ((base)->OTG2_CTRL2) +#define USBNC_OTG2_PHY_CFG1_REG(base) ((base)->OTG2_PHY_CFG1) +#define USBNC_OTG2_PHY_CFG2_REG(base) ((base)->OTG2_PHY_CFG2) +#define USBNC_OTG2_PHY_STATUS_REG(base) ((base)->OTG2_PHY_STATUS) +#define USBNC_HSIC_CTRL1_REG(base) ((base)->HSIC_CTRL1) +#define USBNC_HSIC_CTRL2_REG(base) ((base)->HSIC_CTRL2) +#define USBNC_UH_HSICPHY_CFG1_REG(base) ((base)->UH_HSICPHY_CFG1) /*! * @} */ /* end of group USBNC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- USBNC Register Masks ---------------------------------------------------------------------------- */ @@ -93938,60 +42888,137 @@ typedef struct { * @{ */ -/* USB_x_CTRL1 Bit Fields */ -#define USBNC_USB_x_CTRL1_OVER_CUR_DIS_MASK 0x80u -#define USBNC_USB_x_CTRL1_OVER_CUR_DIS_SHIFT 7 -#define USBNC_USB_x_CTRL1_OVER_CUR_POL_MASK 0x100u -#define USBNC_USB_x_CTRL1_OVER_CUR_POL_SHIFT 8 -#define USBNC_USB_x_CTRL1_PWR_POL_MASK 0x200u -#define USBNC_USB_x_CTRL1_PWR_POL_SHIFT 9 -#define USBNC_USB_x_CTRL1_WIE_MASK 0x400u -#define USBNC_USB_x_CTRL1_WIE_SHIFT 10 -#define USBNC_USB_x_CTRL1_WKUP_SW_EN_MASK 0x4000u -#define USBNC_USB_x_CTRL1_WKUP_SW_EN_SHIFT 14 -#define USBNC_USB_x_CTRL1_WKUP_SW_MASK 0x8000u -#define USBNC_USB_x_CTRL1_WKUP_SW_SHIFT 15 -#define USBNC_USB_x_CTRL1_WKUP_ID_EN_MASK 0x10000u -#define USBNC_USB_x_CTRL1_WKUP_ID_EN_SHIFT 16 -#define USBNC_USB_x_CTRL1_WKUP_VBUS_EN_MASK 0x20000u -#define USBNC_USB_x_CTRL1_WKUP_VBUS_EN_SHIFT 17 -#define USBNC_USB_x_CTRL1_WKUP_DPDM_EN_MASK 0x20000000u -#define USBNC_USB_x_CTRL1_WKUP_DPDM_EN_SHIFT 29 -#define USBNC_USB_x_CTRL1_WIR_MASK 0x80000000u -#define USBNC_USB_x_CTRL1_WIR_SHIFT 31 -/* USB_x_CTRL2 Bit Fields */ -#define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_MASK 0x3u -#define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_SHIFT 0 -#define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x))<<USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_SHIFT))&USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_MASK) -#define USBNC_USB_x_CTRL2_AUTURESUME_EN_MASK 0x4u -#define USBNC_USB_x_CTRL2_AUTURESUME_EN_SHIFT 2 -#define USBNC_USB_x_CTRL2_LOWSPEED_EN_MASK 0x8u -#define USBNC_USB_x_CTRL2_LOWSPEED_EN_SHIFT 3 -#define USBNC_USB_x_CTRL2_DIG_ID_SEL_MASK 0x100000u -#define USBNC_USB_x_CTRL2_DIG_ID_SEL_SHIFT 20 -#define USBNC_USB_x_CTRL2_UTMI_CLK_VLD_MASK 0x80000000u -#define USBNC_USB_x_CTRL2_UTMI_CLK_VLD_SHIFT 31 -/* USB_x_PHY_CTL2 Bit Fields */ -#define USBNC_USB_x_PHY_CTL2_CHRGSEL0_MASK 0x1u -#define USBNC_USB_x_PHY_CTL2_CHRGSEL0_SHIFT 0 -#define USBNC_USB_x_PHY_CTL2_VDATDETENB0_MASK 0x2u -#define USBNC_USB_x_PHY_CTL2_VDATDETENB0_SHIFT 1 -#define USBNC_USB_x_PHY_CTL2_VDATSRCENB0_MASK 0x4u -#define USBNC_USB_x_PHY_CTL2_VDATSRCENB0_SHIFT 2 -#define USBNC_USB_x_PHY_CTL2_DCDENB0_MASK 0x8u -#define USBNC_USB_x_PHY_CTL2_DCDENB0_SHIFT 3 -/* USB_x_PHY_STS Bit Fields */ -#define USBNC_USB_x_PHY_STS_LINE_STATE_MASK 0x3u -#define USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT 0 -#define USBNC_USB_x_PHY_STS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x))<<USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT))&USBNC_USB_x_PHY_STS_LINE_STATE_MASK) -#define USBNC_USB_x_PHY_STS_SESS_VLD_MASK 0x4u -#define USBNC_USB_x_PHY_STS_SESS_VLD_SHIFT 2 -#define USBNC_USB_x_PHY_STS_VBUS_VLD_MASK 0x8u -#define USBNC_USB_x_PHY_STS_VBUS_VLD_SHIFT 3 -#define USBNC_USB_x_PHY_STS_ID_DIG_MASK 0x10u -#define USBNC_USB_x_PHY_STS_ID_DIG_SHIFT 4 -#define USBNC_USB_x_PHY_STS_USB_OTG1_CHD_B_MASK 0x20000000u -#define USBNC_USB_x_PHY_STS_USB_OTG1_CHD_B_SHIFT 29 +/* OTG1_CTRL1 Bit Fields */ +#define USBNC_OTG1_CTRL1_OVER_CUR_DIS_MASK 0x80u +#define USBNC_OTG1_CTRL1_OVER_CUR_DIS_SHIFT 7 +#define USBNC_OTG1_CTRL1_OVER_CUR_POL_MASK 0x100u +#define USBNC_OTG1_CTRL1_OVER_CUR_POL_SHIFT 8 +#define USBNC_OTG1_CTRL1_PWR_POL_MASK 0x200u +#define USBNC_OTG1_CTRL1_PWR_POL_SHIFT 9 +#define USBNC_OTG1_CTRL1_WIE_MASK 0x400u +#define USBNC_OTG1_CTRL1_WIE_SHIFT 10 +#define USBNC_OTG1_CTRL1_WKUP_SW_EN_MASK 0x4000u +#define USBNC_OTG1_CTRL1_WKUP_SW_EN_SHIFT 14 +#define USBNC_OTG1_CTRL1_WKUP_SW_MASK 0x8000u +#define USBNC_OTG1_CTRL1_WKUP_SW_SHIFT 15 +#define USBNC_OTG1_CTRL1_WKUP_ID_EN_MASK 0x10000u +#define USBNC_OTG1_CTRL1_WKUP_ID_EN_SHIFT 16 +#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_MASK 0x20000u +#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_SHIFT 17 +#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_MASK 0x20000000u +#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_SHIFT 29 +#define USBNC_OTG1_CTRL1_WIR_MASK 0x80000000u +#define USBNC_OTG1_CTRL1_WIR_SHIFT 31 +/* OTG1_CTRL2 Bit Fields */ +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK 0x3u +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT 0 +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT))&USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK) +#define USBNC_OTG1_CTRL2_AUTURESUME_EN_MASK 0x4u +#define USBNC_OTG1_CTRL2_AUTURESUME_EN_SHIFT 2 +#define USBNC_OTG1_CTRL2_LOWSPEED_EN_MASK 0x8u +#define USBNC_OTG1_CTRL2_LOWSPEED_EN_SHIFT 3 +#define USBNC_OTG1_CTRL2_DIG_ID_SEL_MASK 0x100000u +#define USBNC_OTG1_CTRL2_DIG_ID_SEL_SHIFT 20 +#define USBNC_OTG1_CTRL2_UTMI_CLK_VLD_MASK 0x80000000u +#define USBNC_OTG1_CTRL2_UTMI_CLK_VLD_SHIFT 31 +/* OTG1_PHY_CFG1 Bit Fields */ +#define USBNC_OTG1_PHY_CFG1_COMMONONN_MASK 0x1u +#define USBNC_OTG1_PHY_CFG1_COMMONONN_SHIFT 0 +#define USBNC_OTG1_PHY_CFG1_FSEL_MASK 0xEu +#define USBNC_OTG1_PHY_CFG1_FSEL_SHIFT 1 +#define USBNC_OTG1_PHY_CFG1_FSEL(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_FSEL_SHIFT))&USBNC_OTG1_PHY_CFG1_FSEL_MASK) +#define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_MASK 0x70u +#define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_SHIFT 4 +#define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_SQRXTUNE0_MASK 0x380u +#define USBNC_OTG1_PHY_CFG1_SQRXTUNE0_SHIFT 7 +#define USBNC_OTG1_PHY_CFG1_SQRXTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_SQRXTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_SQRXTUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_OTGTUNE0_MASK 0x1C00u +#define USBNC_OTG1_PHY_CFG1_OTGTUNE0_SHIFT 10 +#define USBNC_OTG1_PHY_CFG1_OTGTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_OTGTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_OTGTUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_MASK 0x6000u +#define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_SHIFT 13 +#define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_MASK 0xF0000u +#define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_SHIFT 16 +#define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_MASK 0xF00000u +#define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_SHIFT 20 +#define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_TXRISETUNE0_MASK 0x3000000u +#define USBNC_OTG1_PHY_CFG1_TXRISETUNE0_SHIFT 24 +#define USBNC_OTG1_PHY_CFG1_TXRISETUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXRISETUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXRISETUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_TXRESTUNE0_MASK 0xC000000u +#define USBNC_OTG1_PHY_CFG1_TXRESTUNE0_SHIFT 26 +#define USBNC_OTG1_PHY_CFG1_TXRESTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXRESTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXRESTUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_MASK 0x30000000u +#define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT 28 +#define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT))&USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_MASK) +#define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_MASK 0x40000000u +#define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT 30 +#define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_MASK 0x80000000u +#define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_SHIFT 31 +/* OTG1_PHY_CFG2 Bit Fields */ +#define USBNC_OTG1_PHY_CFG2_CHRGSEL_MASK 0x1u +#define USBNC_OTG1_PHY_CFG2_CHRGSEL_SHIFT 0 +#define USBNC_OTG1_PHY_CFG2_VDATDETENB0_MASK 0x2u +#define USBNC_OTG1_PHY_CFG2_VDATDETENB0_SHIFT 1 +#define USBNC_OTG1_PHY_CFG2_VDATSRCENB0_MASK 0x4u +#define USBNC_OTG1_PHY_CFG2_VDATSRCENB0_SHIFT 2 +#define USBNC_OTG1_PHY_CFG2_DCDENB_MASK 0x8u +#define USBNC_OTG1_PHY_CFG2_DCDENB_SHIFT 3 +#define USBNC_OTG1_PHY_CFG2_ACAENB0_MASK 0x10u +#define USBNC_OTG1_PHY_CFG2_ACAENB0_SHIFT 4 +#define USBNC_OTG1_PHY_CFG2_SLEEPM0_MASK 0x20u +#define USBNC_OTG1_PHY_CFG2_SLEEPM0_SHIFT 5 +#define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_MASK 0x40u +#define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_SHIFT 6 +#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_MASK 0x100u +#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_SHIFT 8 +#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_MASK 0x200u +#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_SHIFT 9 +#define USBNC_OTG1_PHY_CFG2_OTGDISABLE0_MASK 0x400u +#define USBNC_OTG1_PHY_CFG2_OTGDISABLE0_SHIFT 10 +#define USBNC_OTG1_PHY_CFG2_ADPCHRG0_MASK 0x800u +#define USBNC_OTG1_PHY_CFG2_ADPCHRG0_SHIFT 11 +#define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_MASK 0x1000u +#define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_SHIFT 12 +#define USBNC_OTG1_PHY_CFG2_ADPPRBENB0_MASK 0x2000u +#define USBNC_OTG1_PHY_CFG2_ADPPRBENB0_SHIFT 13 +#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_MASK 0x4000u +#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT 14 +#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_MASK 0x8000u +#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_SHIFT 15 +#define USBNC_OTG1_PHY_CFG2_DRVVBUS0_MASK 0x10000u +#define USBNC_OTG1_PHY_CFG2_DRVVBUS0_SHIFT 16 +/* OTG1_PHY_STATUS Bit Fields */ +#define USBNC_OTG1_PHY_STATUS_LINE_STATE_MASK 0x3u +#define USBNC_OTG1_PHY_STATUS_LINE_STATE_SHIFT 0 +#define USBNC_OTG1_PHY_STATUS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG1_PHY_STATUS_LINE_STATE_SHIFT))&USBNC_OTG1_PHY_STATUS_LINE_STATE_MASK) +#define USBNC_OTG1_PHY_STATUS_SESS_VLD_MASK 0x4u +#define USBNC_OTG1_PHY_STATUS_SESS_VLD_SHIFT 2 +#define USBNC_OTG1_PHY_STATUS_VBUS_VLD_MASK 0x8u +#define USBNC_OTG1_PHY_STATUS_VBUS_VLD_SHIFT 3 +#define USBNC_OTG1_PHY_STATUS_ID_DIG_MASK 0x10u +#define USBNC_OTG1_PHY_STATUS_ID_DIG_SHIFT 4 +#define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_MASK 0x20u +#define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_SHIFT 5 +#define USBNC_OTG1_PHY_STATUS_RIDC0_MASK 0x1000000u +#define USBNC_OTG1_PHY_STATUS_RIDC0_SHIFT 24 +#define USBNC_OTG1_PHY_STATUS_RIDB0_MASK 0x2000000u +#define USBNC_OTG1_PHY_STATUS_RIDB0_SHIFT 25 +#define USBNC_OTG1_PHY_STATUS_RIDA0_MASK 0x4000000u +#define USBNC_OTG1_PHY_STATUS_RIDA0_SHIFT 26 +#define USBNC_OTG1_PHY_STATUS_RIDGND0_MASK 0x8000000u +#define USBNC_OTG1_PHY_STATUS_RIDGND0_SHIFT 27 +#define USBNC_OTG1_PHY_STATUS_RIDFLOAT0_MASK 0x10000000u +#define USBNC_OTG1_PHY_STATUS_RIDFLOAT0_SHIFT 28 +#define USBNC_OTG1_PHY_STATUS_CHRGDET_MASK 0x20000000u +#define USBNC_OTG1_PHY_STATUS_CHRGDET_SHIFT 29 +#define USBNC_OTG1_PHY_STATUS_ADPPRB0_MASK 0x40000000u +#define USBNC_OTG1_PHY_STATUS_ADPPRB0_SHIFT 30 +#define USBNC_OTG1_PHY_STATUS_ADPSNS0_MASK 0x80000000u +#define USBNC_OTG1_PHY_STATUS_ADPSNS0_SHIFT 31 /* ADP_CFG1 Bit Fields */ #define USBNC_ADP_CFG1_ADP_WAIT_MASK 0x3FFFFu #define USBNC_ADP_CFG1_ADP_WAIT_SHIFT 0 @@ -94027,33 +43054,215 @@ typedef struct { #define USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT 26 #define USBNC_ADP_STATUS_ADP_PRB_INT_MASK 0x8000000u #define USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT 27 +/* OTG2_CTRL1 Bit Fields */ +#define USBNC_OTG2_CTRL1_OVER_CUR_DIS_MASK 0x80u +#define USBNC_OTG2_CTRL1_OVER_CUR_DIS_SHIFT 7 +#define USBNC_OTG2_CTRL1_OVER_CUR_POL_MASK 0x100u +#define USBNC_OTG2_CTRL1_OVER_CUR_POL_SHIFT 8 +#define USBNC_OTG2_CTRL1_PWR_POL_MASK 0x200u +#define USBNC_OTG2_CTRL1_PWR_POL_SHIFT 9 +#define USBNC_OTG2_CTRL1_WIE_MASK 0x400u +#define USBNC_OTG2_CTRL1_WIE_SHIFT 10 +#define USBNC_OTG2_CTRL1_WKUP_SW_EN_MASK 0x4000u +#define USBNC_OTG2_CTRL1_WKUP_SW_EN_SHIFT 14 +#define USBNC_OTG2_CTRL1_WKUP_SW_MASK 0x8000u +#define USBNC_OTG2_CTRL1_WKUP_SW_SHIFT 15 +#define USBNC_OTG2_CTRL1_WKUP_ID_EN_MASK 0x10000u +#define USBNC_OTG2_CTRL1_WKUP_ID_EN_SHIFT 16 +#define USBNC_OTG2_CTRL1_WKUP_VBUS_EN_MASK 0x20000u +#define USBNC_OTG2_CTRL1_WKUP_VBUS_EN_SHIFT 17 +#define USBNC_OTG2_CTRL1_WKUP_DPDM_EN_MASK 0x20000000u +#define USBNC_OTG2_CTRL1_WKUP_DPDM_EN_SHIFT 29 +#define USBNC_OTG2_CTRL1_WIR_MASK 0x80000000u +#define USBNC_OTG2_CTRL1_WIR_SHIFT 31 +/* OTG2_CTRL2 Bit Fields */ +#define USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL_MASK 0x3u +#define USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL_SHIFT 0 +#define USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL_SHIFT))&USBNC_OTG2_CTRL2_VBUS_SOURCE_SEL_MASK) +#define USBNC_OTG2_CTRL2_AUTURESUME_EN_MASK 0x4u +#define USBNC_OTG2_CTRL2_AUTURESUME_EN_SHIFT 2 +#define USBNC_OTG2_CTRL2_LOWSPEED_EN_MASK 0x8u +#define USBNC_OTG2_CTRL2_LOWSPEED_EN_SHIFT 3 +#define USBNC_OTG2_CTRL2_DIG_ID_SEL_MASK 0x100000u +#define USBNC_OTG2_CTRL2_DIG_ID_SEL_SHIFT 20 +#define USBNC_OTG2_CTRL2_UTMI_CLK_VLD_MASK 0x80000000u +#define USBNC_OTG2_CTRL2_UTMI_CLK_VLD_SHIFT 31 +/* OTG2_PHY_CFG1 Bit Fields */ +#define USBNC_OTG2_PHY_CFG1_COMMONONN_MASK 0x1u +#define USBNC_OTG2_PHY_CFG1_COMMONONN_SHIFT 0 +#define USBNC_OTG2_PHY_CFG1_FSEL_MASK 0xEu +#define USBNC_OTG2_PHY_CFG1_FSEL_SHIFT 1 +#define USBNC_OTG2_PHY_CFG1_FSEL(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_FSEL_SHIFT))&USBNC_OTG2_PHY_CFG1_FSEL_MASK) +#define USBNC_OTG2_PHY_CFG1_COMPDISTUNE0_MASK 0x70u +#define USBNC_OTG2_PHY_CFG1_COMPDISTUNE0_SHIFT 4 +#define USBNC_OTG2_PHY_CFG1_COMPDISTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_COMPDISTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_COMPDISTUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_SQRXTUNE0_MASK 0x380u +#define USBNC_OTG2_PHY_CFG1_SQRXTUNE0_SHIFT 7 +#define USBNC_OTG2_PHY_CFG1_SQRXTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_SQRXTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_SQRXTUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_OTGTUNE0_MASK 0x1C00u +#define USBNC_OTG2_PHY_CFG1_OTGTUNE0_SHIFT 10 +#define USBNC_OTG2_PHY_CFG1_OTGTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_OTGTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_OTGTUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0_MASK 0x6000u +#define USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0_SHIFT 13 +#define USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXHSXVTUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0_MASK 0xF0000u +#define USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0_SHIFT 16 +#define USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXFSLSTUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_TXVREFTUNE0_MASK 0xF00000u +#define USBNC_OTG2_PHY_CFG1_TXVREFTUNE0_SHIFT 20 +#define USBNC_OTG2_PHY_CFG1_TXVREFTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXVREFTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXVREFTUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_TXRISETUNE0_MASK 0x3000000u +#define USBNC_OTG2_PHY_CFG1_TXRISETUNE0_SHIFT 24 +#define USBNC_OTG2_PHY_CFG1_TXRISETUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXRISETUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXRISETUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_TXRESTUNE0_MASK 0xC000000u +#define USBNC_OTG2_PHY_CFG1_TXRESTUNE0_SHIFT 26 +#define USBNC_OTG2_PHY_CFG1_TXRESTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXRESTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXRESTUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0_MASK 0x30000000u +#define USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT 28 +#define USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT))&USBNC_OTG2_PHY_CFG1_TXPREEMPAMPTUNE0_MASK) +#define USBNC_OTG2_PHY_CFG1_TXPREEMPPULSETUNE0_MASK 0x40000000u +#define USBNC_OTG2_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT 30 +#define USBNC_OTG2_PHY_CFG1_CHRGDET_Megamix_MASK 0x80000000u +#define USBNC_OTG2_PHY_CFG1_CHRGDET_Megamix_SHIFT 31 +/* OTG2_PHY_CFG2 Bit Fields */ +#define USBNC_OTG2_PHY_CFG2_CHRGSEL_MASK 0x1u +#define USBNC_OTG2_PHY_CFG2_CHRGSEL_SHIFT 0 +#define USBNC_OTG2_PHY_CFG2_VDATDETENB0_MASK 0x2u +#define USBNC_OTG2_PHY_CFG2_VDATDETENB0_SHIFT 1 +#define USBNC_OTG2_PHY_CFG2_VDATSRCENB0_MASK 0x4u +#define USBNC_OTG2_PHY_CFG2_VDATSRCENB0_SHIFT 2 +#define USBNC_OTG2_PHY_CFG2_DCDENB_MASK 0x8u +#define USBNC_OTG2_PHY_CFG2_DCDENB_SHIFT 3 +#define USBNC_OTG2_PHY_CFG2_ACAENB0_MASK 0x10u +#define USBNC_OTG2_PHY_CFG2_ACAENB0_SHIFT 4 +#define USBNC_OTG2_PHY_CFG2_SLEEPM0_MASK 0x20u +#define USBNC_OTG2_PHY_CFG2_SLEEPM0_SHIFT 5 +#define USBNC_OTG2_PHY_CFG2_LOOPBACKENB0_MASK 0x40u +#define USBNC_OTG2_PHY_CFG2_LOOPBACKENB0_SHIFT 6 +#define USBNC_OTG2_PHY_CFG2_TXBITSTUFFEN0_MASK 0x100u +#define USBNC_OTG2_PHY_CFG2_TXBITSTUFFEN0_SHIFT 8 +#define USBNC_OTG2_PHY_CFG2_TXBITSTUFFENH0_MASK 0x200u +#define USBNC_OTG2_PHY_CFG2_TXBITSTUFFENH0_SHIFT 9 +#define USBNC_OTG2_PHY_CFG2_OTGDISABLE0_MASK 0x400u +#define USBNC_OTG2_PHY_CFG2_OTGDISABLE0_SHIFT 10 +#define USBNC_OTG2_PHY_CFG2_ADPCHRG0_MASK 0x800u +#define USBNC_OTG2_PHY_CFG2_ADPCHRG0_SHIFT 11 +#define USBNC_OTG2_PHY_CFG2_ADPDISCHRG0_MASK 0x1000u +#define USBNC_OTG2_PHY_CFG2_ADPDISCHRG0_SHIFT 12 +#define USBNC_OTG2_PHY_CFG2_ADPPRBENB0_MASK 0x2000u +#define USBNC_OTG2_PHY_CFG2_ADPPRBENB0_SHIFT 13 +#define USBNC_OTG2_PHY_CFG2_VBUSVLDEXTSEL0_MASK 0x4000u +#define USBNC_OTG2_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT 14 +#define USBNC_OTG2_PHY_CFG2_VBUSVLDEXT_MASK 0x8000u +#define USBNC_OTG2_PHY_CFG2_VBUSVLDEXT_SHIFT 15 +#define USBNC_OTG2_PHY_CFG2_DRVVBUS0_MASK 0x10000u +#define USBNC_OTG2_PHY_CFG2_DRVVBUS0_SHIFT 16 +/* OTG2_PHY_STATUS Bit Fields */ +#define USBNC_OTG2_PHY_STATUS_LINE_STATE_MASK 0x3u +#define USBNC_OTG2_PHY_STATUS_LINE_STATE_SHIFT 0 +#define USBNC_OTG2_PHY_STATUS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x))<<USBNC_OTG2_PHY_STATUS_LINE_STATE_SHIFT))&USBNC_OTG2_PHY_STATUS_LINE_STATE_MASK) +#define USBNC_OTG2_PHY_STATUS_SESS_VLD_MASK 0x4u +#define USBNC_OTG2_PHY_STATUS_SESS_VLD_SHIFT 2 +#define USBNC_OTG2_PHY_STATUS_VBUS_VLD_MASK 0x8u +#define USBNC_OTG2_PHY_STATUS_VBUS_VLD_SHIFT 3 +#define USBNC_OTG2_PHY_STATUS_ID_DIG_MASK 0x10u +#define USBNC_OTG2_PHY_STATUS_ID_DIG_SHIFT 4 +#define USBNC_OTG2_PHY_STATUS_HOST_DISCONNECT_MASK 0x20u +#define USBNC_OTG2_PHY_STATUS_HOST_DISCONNECT_SHIFT 5 +#define USBNC_OTG2_PHY_STATUS_RIDC0_MASK 0x1000000u +#define USBNC_OTG2_PHY_STATUS_RIDC0_SHIFT 24 +#define USBNC_OTG2_PHY_STATUS_RIDB0_MASK 0x2000000u +#define USBNC_OTG2_PHY_STATUS_RIDB0_SHIFT 25 +#define USBNC_OTG2_PHY_STATUS_RIDA0_MASK 0x4000000u +#define USBNC_OTG2_PHY_STATUS_RIDA0_SHIFT 26 +#define USBNC_OTG2_PHY_STATUS_RIDGND0_MASK 0x8000000u +#define USBNC_OTG2_PHY_STATUS_RIDGND0_SHIFT 27 +#define USBNC_OTG2_PHY_STATUS_RIDFLOAT0_MASK 0x10000000u +#define USBNC_OTG2_PHY_STATUS_RIDFLOAT0_SHIFT 28 +#define USBNC_OTG2_PHY_STATUS_CHRGDET_MASK 0x20000000u +#define USBNC_OTG2_PHY_STATUS_CHRGDET_SHIFT 29 +#define USBNC_OTG2_PHY_STATUS_ADPPRB0_MASK 0x40000000u +#define USBNC_OTG2_PHY_STATUS_ADPPRB0_SHIFT 30 +#define USBNC_OTG2_PHY_STATUS_ADPSNS0_MASK 0x80000000u +#define USBNC_OTG2_PHY_STATUS_ADPSNS0_SHIFT 31 +/* HSIC_CTRL1 Bit Fields */ +#define USBNC_HSIC_CTRL1_OVER_CUR_DIS_MASK 0x80u +#define USBNC_HSIC_CTRL1_OVER_CUR_DIS_SHIFT 7 +#define USBNC_HSIC_CTRL1_OVER_CUR_POL_MASK 0x100u +#define USBNC_HSIC_CTRL1_OVER_CUR_POL_SHIFT 8 +#define USBNC_HSIC_CTRL1_PWR_POL_MASK 0x200u +#define USBNC_HSIC_CTRL1_PWR_POL_SHIFT 9 +#define USBNC_HSIC_CTRL1_WIE_MASK 0x400u +#define USBNC_HSIC_CTRL1_WIE_SHIFT 10 +#define USBNC_HSIC_CTRL1_WKUP_SW_EN_MASK 0x4000u +#define USBNC_HSIC_CTRL1_WKUP_SW_EN_SHIFT 14 +#define USBNC_HSIC_CTRL1_WKUP_SW_MASK 0x8000u +#define USBNC_HSIC_CTRL1_WKUP_SW_SHIFT 15 +#define USBNC_HSIC_CTRL1_WKUP_ID_EN_MASK 0x10000u +#define USBNC_HSIC_CTRL1_WKUP_ID_EN_SHIFT 16 +#define USBNC_HSIC_CTRL1_WKUP_VBUS_EN_MASK 0x20000u +#define USBNC_HSIC_CTRL1_WKUP_VBUS_EN_SHIFT 17 +#define USBNC_HSIC_CTRL1_WKUP_DPDM_EN_MASK 0x20000000u +#define USBNC_HSIC_CTRL1_WKUP_DPDM_EN_SHIFT 29 +#define USBNC_HSIC_CTRL1_WIR_MASK 0x80000000u +#define USBNC_HSIC_CTRL1_WIR_SHIFT 31 +/* HSIC_CTRL2 Bit Fields */ +#define USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL_MASK 0x3u +#define USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL_SHIFT 0 +#define USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x))<<USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL_SHIFT))&USBNC_HSIC_CTRL2_VBUS_SOURCE_SEL_MASK) +#define USBNC_HSIC_CTRL2_AUTURESUME_EN_MASK 0x4u +#define USBNC_HSIC_CTRL2_AUTURESUME_EN_SHIFT 2 +#define USBNC_HSIC_CTRL2_LOWSPEED_EN_MASK 0x8u +#define USBNC_HSIC_CTRL2_LOWSPEED_EN_SHIFT 3 +#define USBNC_HSIC_CTRL2_DIG_ID_SEL_MASK 0x100000u +#define USBNC_HSIC_CTRL2_DIG_ID_SEL_SHIFT 20 +#define USBNC_HSIC_CTRL2_UTMI_CLK_VLD_MASK 0x80000000u +#define USBNC_HSIC_CTRL2_UTMI_CLK_VLD_SHIFT 31 +/* UH_HSICPHY_CFG1 Bit Fields */ +#define USBNC_UH_HSICPHY_CFG1_COMMONONN_MASK 0x1u +#define USBNC_UH_HSICPHY_CFG1_COMMONONN_SHIFT 0 +#define USBNC_UH_HSICPHY_CFG1_LOOPBACKENB_MASK 0x2u +#define USBNC_UH_HSICPHY_CFG1_LOOPBACKENB_SHIFT 1 +#define USBNC_UH_HSICPHY_CFG1_DPPULLDOWN_MASK 0x4u +#define USBNC_UH_HSICPHY_CFG1_DPPULLDOWN_SHIFT 2 +#define USBNC_UH_HSICPHY_CFG1_DMPULLDOWN_MASK 0x8u +#define USBNC_UH_HSICPHY_CFG1_DMPULLDOWN_SHIFT 3 +#define USBNC_UH_HSICPHY_CFG1_SLEEPM_MASK 0x10u +#define USBNC_UH_HSICPHY_CFG1_SLEEPM_SHIFT 4 +#define USBNC_UH_HSICPHY_CFG1_TXBITSTUFFEN_MASK 0x20u +#define USBNC_UH_HSICPHY_CFG1_TXBITSTUFFEN_SHIFT 5 +#define USBNC_UH_HSICPHY_CFG1_TXBITSTUFFENH_MASK 0x40u +#define USBNC_UH_HSICPHY_CFG1_TXBITSTUFFENH_SHIFT 6 +#define USBNC_UH_HSICPHY_CFG1_TXRPUTUNE_MASK 0x300u +#define USBNC_UH_HSICPHY_CFG1_TXRPUTUNE_SHIFT 8 +#define USBNC_UH_HSICPHY_CFG1_TXRPUTUNE(x) (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_TXRPUTUNE_SHIFT))&USBNC_UH_HSICPHY_CFG1_TXRPUTUNE_MASK) +#define USBNC_UH_HSICPHY_CFG1_TXRPDTUNE_MASK 0xC00u +#define USBNC_UH_HSICPHY_CFG1_TXRPDTUNE_SHIFT 10 +#define USBNC_UH_HSICPHY_CFG1_TXRPDTUNE(x) (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_TXRPDTUNE_SHIFT))&USBNC_UH_HSICPHY_CFG1_TXRPDTUNE_MASK) +#define USBNC_UH_HSICPHY_CFG1_TXSRTUNE_MASK 0xF000u +#define USBNC_UH_HSICPHY_CFG1_TXSRTUNE_SHIFT 12 +#define USBNC_UH_HSICPHY_CFG1_TXSRTUNE(x) (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_TXSRTUNE_SHIFT))&USBNC_UH_HSICPHY_CFG1_TXSRTUNE_MASK) +#define USBNC_UH_HSICPHY_CFG1_REFCLKDIV_MASK 0x7F0000u +#define USBNC_UH_HSICPHY_CFG1_REFCLKDIV_SHIFT 16 +#define USBNC_UH_HSICPHY_CFG1_REFCLKDIV(x) (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_REFCLKDIV_SHIFT))&USBNC_UH_HSICPHY_CFG1_REFCLKDIV_MASK) +#define USBNC_UH_HSICPHY_CFG1_REFCLKSEL_MASK 0x3000000u +#define USBNC_UH_HSICPHY_CFG1_REFCLKSEL_SHIFT 24 +#define USBNC_UH_HSICPHY_CFG1_REFCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<USBNC_UH_HSICPHY_CFG1_REFCLKSEL_SHIFT))&USBNC_UH_HSICPHY_CFG1_REFCLKSEL_MASK) /*! * @} */ /* end of group USBNC_Register_Masks */ - /* USBNC - Peripheral instance base addresses */ -/** Peripheral USBNC1 base address */ -#define USBNC1_BASE (0x30B10000u) -/** Peripheral USBNC1 base pointer */ -#define USBNC1 ((USBNC_Type *)USBNC1_BASE) -#define USBNC1_BASE_PTR (USBNC1) -/** Peripheral USBNC2 base address */ -#define USBNC2_BASE (0x30B20000u) -/** Peripheral USBNC2 base pointer */ -#define USBNC2 ((USBNC_Type *)USBNC2_BASE) -#define USBNC2_BASE_PTR (USBNC2) -/** Peripheral USBNC3 base address */ -#define USBNC3_BASE (0x30B30000u) -/** Peripheral USBNC3 base pointer */ -#define USBNC3 ((USBNC_Type *)USBNC3_BASE) -#define USBNC3_BASE_PTR (USBNC3) -/** Array initializer of USBNC peripheral base adresses */ -#define USBNC_BASE_ADDRS { USBNC1_BASE, USBNC2_BASE, USBNC3_BASE } +/** Peripheral USBNC base address */ +#define USBNC_BASE (0x30B10000u) +/** Peripheral USBNC base pointer */ +#define USBNC ((USBNC_Type *)USBNC_BASE) +#define USBNC_BASE_PTR (USBNC) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { USBNC_BASE } /** Array initializer of USBNC peripheral base pointers */ -#define USBNC_BASE_PTRS { USBNC1, USBNC2, USBNC3 } - +#define USBNC_BASE_PTRS { USBNC } /* ---------------------------------------------------------------------------- -- USBNC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -94065,31 +43274,23 @@ typedef struct { /* USBNC - Register instance definitions */ -/* USBNC1 */ -#define USBNC1_USB_x_CTRL1 USBNC_USB_x_CTRL1_REG(USBNC1_BASE_PTR) -#define USBNC1_USB_x_CTRL2 USBNC_USB_x_CTRL2_REG(USBNC1_BASE_PTR) -#define USBNC1_USB_x_PHY_CTL2 USBNC_USB_x_PHY_CTL2_REG(USBNC1_BASE_PTR) -#define USBNC1_USB_x_PHY_STS USBNC_USB_x_PHY_STS_REG(USBNC1_BASE_PTR) -#define USBNC1_ADP_CFG1 USBNC_ADP_CFG1_REG(USBNC1_BASE_PTR) -#define USBNC1_ADP_CFG2 USBNC_ADP_CFG2_REG(USBNC1_BASE_PTR) -#define USBNC1_ADP_STATUS USBNC_ADP_STATUS_REG(USBNC1_BASE_PTR) -/* USBNC2 */ -#define USBNC2_USB_x_CTRL1 USBNC_USB_x_CTRL1_REG(USBNC2_BASE_PTR) -#define USBNC2_USB_x_CTRL2 USBNC_USB_x_CTRL2_REG(USBNC2_BASE_PTR) -#define USBNC2_USB_x_PHY_CTL2 USBNC_USB_x_PHY_CTL2_REG(USBNC2_BASE_PTR) -#define USBNC2_USB_x_PHY_STS USBNC_USB_x_PHY_STS_REG(USBNC2_BASE_PTR) -#define USBNC2_ADP_CFG1 USBNC_ADP_CFG1_REG(USBNC2_BASE_PTR) -#define USBNC2_ADP_CFG2 USBNC_ADP_CFG2_REG(USBNC2_BASE_PTR) -#define USBNC2_ADP_STATUS USBNC_ADP_STATUS_REG(USBNC2_BASE_PTR) -/* USBNC3 */ -#define USBNC3_USB_x_CTRL1 USBNC_USB_x_CTRL1_REG(USBNC3_BASE_PTR) -#define USBNC3_USB_x_CTRL2 USBNC_USB_x_CTRL2_REG(USBNC3_BASE_PTR) -#define USBNC3_USB_x_PHY_CTL2 USBNC_USB_x_PHY_CTL2_REG(USBNC3_BASE_PTR) -#define USBNC3_USB_x_PHY_STS USBNC_USB_x_PHY_STS_REG(USBNC3_BASE_PTR) -#define USBNC3_ADP_CFG1 USBNC_ADP_CFG1_REG(USBNC3_BASE_PTR) -#define USBNC3_ADP_CFG2 USBNC_ADP_CFG2_REG(USBNC3_BASE_PTR) -#define USBNC3_ADP_STATUS USBNC_ADP_STATUS_REG(USBNC3_BASE_PTR) - +/* USBNC */ +#define USBNC_OTG1_CTRL1 USBNC_OTG1_CTRL1_REG(USBNC_BASE_PTR) +#define USBNC_OTG1_CTRL2 USBNC_OTG1_CTRL2_REG(USBNC_BASE_PTR) +#define USBNC_OTG1_PHY_CFG1 USBNC_OTG1_PHY_CFG1_REG(USBNC_BASE_PTR) +#define USBNC_OTG1_PHY_CFG2 USBNC_OTG1_PHY_CFG2_REG(USBNC_BASE_PTR) +#define USBNC_OTG1_PHY_STATUS USBNC_OTG1_PHY_STATUS_REG(USBNC_BASE_PTR) +#define USBNC_ADP_CFG1 USBNC_ADP_CFG1_REG(USBNC_BASE_PTR) +#define USBNC_ADP_CFG2 USBNC_ADP_CFG2_REG(USBNC_BASE_PTR) +#define USBNC_ADP_STATUS USBNC_ADP_STATUS_REG(USBNC_BASE_PTR) +#define USBNC_OTG2_CTRL1 USBNC_OTG2_CTRL1_REG(USBNC_BASE_PTR) +#define USBNC_OTG2_CTRL2 USBNC_OTG2_CTRL2_REG(USBNC_BASE_PTR) +#define USBNC_OTG2_PHY_CFG1 USBNC_OTG2_PHY_CFG1_REG(USBNC_BASE_PTR) +#define USBNC_OTG2_PHY_CFG2 USBNC_OTG2_PHY_CFG2_REG(USBNC_BASE_PTR) +#define USBNC_OTG2_PHY_STATUS USBNC_OTG2_PHY_STATUS_REG(USBNC_BASE_PTR) +#define USBNC_HSIC_CTRL1 USBNC_HSIC_CTRL1_REG(USBNC_BASE_PTR) +#define USBNC_HSIC_CTRL2 USBNC_HSIC_CTRL2_REG(USBNC_BASE_PTR) +#define USBNC_UH_HSICPHY_CFG1 USBNC_UH_HSICPHY_CFG1_REG(USBNC_BASE_PTR) /*! * @} */ /* end of group USBNC_Register_Accessor_Macros */ @@ -94099,1369 +43300,6 @@ typedef struct { * @} */ /* end of group USBNC_Peripheral */ - -/* ---------------------------------------------------------------------------- - -- USBPHY Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer - * @{ - */ - -/** USBPHY - Register Layout Typedef */ -typedef struct { - __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ - __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ - __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ - __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ - __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ - __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ - __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ - __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ - __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ - __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ - __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ - __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ - __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ - __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ - __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ - __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t DEBUG; /**< USB PHY Debug Register, offset: 0x50 */ - __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ - __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ - __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ - __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ - uint8_t RESERVED_1[12]; - __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ - __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ - __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ - __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ - __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ -} USBPHY_Type, *USBPHY_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- USBPHY - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Accessor_Macros USBPHY - Register accessor macros - * @{ - */ - - -/* USBPHY - Register accessors */ -#define USBPHY_PWD_REG(base) ((base)->PWD) -#define USBPHY_PWD_SET_REG(base) ((base)->PWD_SET) -#define USBPHY_PWD_CLR_REG(base) ((base)->PWD_CLR) -#define USBPHY_PWD_TOG_REG(base) ((base)->PWD_TOG) -#define USBPHY_TX_REG(base) ((base)->TX) -#define USBPHY_TX_SET_REG(base) ((base)->TX_SET) -#define USBPHY_TX_CLR_REG(base) ((base)->TX_CLR) -#define USBPHY_TX_TOG_REG(base) ((base)->TX_TOG) -#define USBPHY_RX_REG(base) ((base)->RX) -#define USBPHY_RX_SET_REG(base) ((base)->RX_SET) -#define USBPHY_RX_CLR_REG(base) ((base)->RX_CLR) -#define USBPHY_RX_TOG_REG(base) ((base)->RX_TOG) -#define USBPHY_CTRL_REG(base) ((base)->CTRL) -#define USBPHY_CTRL_SET_REG(base) ((base)->CTRL_SET) -#define USBPHY_CTRL_CLR_REG(base) ((base)->CTRL_CLR) -#define USBPHY_CTRL_TOG_REG(base) ((base)->CTRL_TOG) -#define USBPHY_STATUS_REG(base) ((base)->STATUS) -#define USBPHY_DEBUG_REG(base) ((base)->DEBUG) -#define USBPHY_DEBUG_SET_REG(base) ((base)->DEBUG_SET) -#define USBPHY_DEBUG_CLR_REG(base) ((base)->DEBUG_CLR) -#define USBPHY_DEBUG_TOG_REG(base) ((base)->DEBUG_TOG) -#define USBPHY_DEBUG0_STATUS_REG(base) ((base)->DEBUG0_STATUS) -#define USBPHY_DEBUG1_REG(base) ((base)->DEBUG1) -#define USBPHY_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) -#define USBPHY_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) -#define USBPHY_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) -#define USBPHY_VERSION_REG(base) ((base)->VERSION) - -/*! - * @} - */ /* end of group USBPHY_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USBPHY Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Masks USBPHY Register Masks - * @{ - */ - -/* PWD Bit Fields */ -#define USBPHY_PWD_RSVD0_MASK 0x3FFu -#define USBPHY_PWD_RSVD0_SHIFT 0 -#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD0_SHIFT))&USBPHY_PWD_RSVD0_MASK) -#define USBPHY_PWD_TXPWDFS_MASK 0x400u -#define USBPHY_PWD_TXPWDFS_SHIFT 10 -#define USBPHY_PWD_TXPWDIBIAS_MASK 0x800u -#define USBPHY_PWD_TXPWDIBIAS_SHIFT 11 -#define USBPHY_PWD_TXPWDV2I_MASK 0x1000u -#define USBPHY_PWD_TXPWDV2I_SHIFT 12 -#define USBPHY_PWD_RSVD1_MASK 0x1E000u -#define USBPHY_PWD_RSVD1_SHIFT 13 -#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD1_SHIFT))&USBPHY_PWD_RSVD1_MASK) -#define USBPHY_PWD_RXPWDENV_MASK 0x20000u -#define USBPHY_PWD_RXPWDENV_SHIFT 17 -#define USBPHY_PWD_RXPWD1PT1_MASK 0x40000u -#define USBPHY_PWD_RXPWD1PT1_SHIFT 18 -#define USBPHY_PWD_RXPWDDIFF_MASK 0x80000u -#define USBPHY_PWD_RXPWDDIFF_SHIFT 19 -#define USBPHY_PWD_RXPWDRX_MASK 0x100000u -#define USBPHY_PWD_RXPWDRX_SHIFT 20 -#define USBPHY_PWD_RSVD2_MASK 0xFFE00000u -#define USBPHY_PWD_RSVD2_SHIFT 21 -#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD2_SHIFT))&USBPHY_PWD_RSVD2_MASK) -/* PWD_SET Bit Fields */ -#define USBPHY_PWD_SET_RSVD0_MASK 0x3FFu -#define USBPHY_PWD_SET_RSVD0_SHIFT 0 -#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD0_SHIFT))&USBPHY_PWD_SET_RSVD0_MASK) -#define USBPHY_PWD_SET_TXPWDFS_MASK 0x400u -#define USBPHY_PWD_SET_TXPWDFS_SHIFT 10 -#define USBPHY_PWD_SET_TXPWDIBIAS_MASK 0x800u -#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT 11 -#define USBPHY_PWD_SET_TXPWDV2I_MASK 0x1000u -#define USBPHY_PWD_SET_TXPWDV2I_SHIFT 12 -#define USBPHY_PWD_SET_RSVD1_MASK 0x1E000u -#define USBPHY_PWD_SET_RSVD1_SHIFT 13 -#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD1_SHIFT))&USBPHY_PWD_SET_RSVD1_MASK) -#define USBPHY_PWD_SET_RXPWDENV_MASK 0x20000u -#define USBPHY_PWD_SET_RXPWDENV_SHIFT 17 -#define USBPHY_PWD_SET_RXPWD1PT1_MASK 0x40000u -#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT 18 -#define USBPHY_PWD_SET_RXPWDDIFF_MASK 0x80000u -#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT 19 -#define USBPHY_PWD_SET_RXPWDRX_MASK 0x100000u -#define USBPHY_PWD_SET_RXPWDRX_SHIFT 20 -#define USBPHY_PWD_SET_RSVD2_MASK 0xFFE00000u -#define USBPHY_PWD_SET_RSVD2_SHIFT 21 -#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD2_SHIFT))&USBPHY_PWD_SET_RSVD2_MASK) -/* PWD_CLR Bit Fields */ -#define USBPHY_PWD_CLR_RSVD0_MASK 0x3FFu -#define USBPHY_PWD_CLR_RSVD0_SHIFT 0 -#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD0_SHIFT))&USBPHY_PWD_CLR_RSVD0_MASK) -#define USBPHY_PWD_CLR_TXPWDFS_MASK 0x400u -#define USBPHY_PWD_CLR_TXPWDFS_SHIFT 10 -#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK 0x800u -#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT 11 -#define USBPHY_PWD_CLR_TXPWDV2I_MASK 0x1000u -#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT 12 -#define USBPHY_PWD_CLR_RSVD1_MASK 0x1E000u -#define USBPHY_PWD_CLR_RSVD1_SHIFT 13 -#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD1_SHIFT))&USBPHY_PWD_CLR_RSVD1_MASK) -#define USBPHY_PWD_CLR_RXPWDENV_MASK 0x20000u -#define USBPHY_PWD_CLR_RXPWDENV_SHIFT 17 -#define USBPHY_PWD_CLR_RXPWD1PT1_MASK 0x40000u -#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT 18 -#define USBPHY_PWD_CLR_RXPWDDIFF_MASK 0x80000u -#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT 19 -#define USBPHY_PWD_CLR_RXPWDRX_MASK 0x100000u -#define USBPHY_PWD_CLR_RXPWDRX_SHIFT 20 -#define USBPHY_PWD_CLR_RSVD2_MASK 0xFFE00000u -#define USBPHY_PWD_CLR_RSVD2_SHIFT 21 -#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD2_SHIFT))&USBPHY_PWD_CLR_RSVD2_MASK) -/* PWD_TOG Bit Fields */ -#define USBPHY_PWD_TOG_RSVD0_MASK 0x3FFu -#define USBPHY_PWD_TOG_RSVD0_SHIFT 0 -#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD0_SHIFT))&USBPHY_PWD_TOG_RSVD0_MASK) -#define USBPHY_PWD_TOG_TXPWDFS_MASK 0x400u -#define USBPHY_PWD_TOG_TXPWDFS_SHIFT 10 -#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK 0x800u -#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT 11 -#define USBPHY_PWD_TOG_TXPWDV2I_MASK 0x1000u -#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT 12 -#define USBPHY_PWD_TOG_RSVD1_MASK 0x1E000u -#define USBPHY_PWD_TOG_RSVD1_SHIFT 13 -#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD1_SHIFT))&USBPHY_PWD_TOG_RSVD1_MASK) -#define USBPHY_PWD_TOG_RXPWDENV_MASK 0x20000u -#define USBPHY_PWD_TOG_RXPWDENV_SHIFT 17 -#define USBPHY_PWD_TOG_RXPWD1PT1_MASK 0x40000u -#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT 18 -#define USBPHY_PWD_TOG_RXPWDDIFF_MASK 0x80000u -#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT 19 -#define USBPHY_PWD_TOG_RXPWDRX_MASK 0x100000u -#define USBPHY_PWD_TOG_RXPWDRX_SHIFT 20 -#define USBPHY_PWD_TOG_RSVD2_MASK 0xFFE00000u -#define USBPHY_PWD_TOG_RSVD2_SHIFT 21 -#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD2_SHIFT))&USBPHY_PWD_TOG_RSVD2_MASK) -/* TX Bit Fields */ -#define USBPHY_TX_D_CAL_MASK 0xFu -#define USBPHY_TX_D_CAL_SHIFT 0 -#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_D_CAL_SHIFT))&USBPHY_TX_D_CAL_MASK) -#define USBPHY_TX_RSVD0_MASK 0xF0u -#define USBPHY_TX_RSVD0_SHIFT 4 -#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD0_SHIFT))&USBPHY_TX_RSVD0_MASK) -#define USBPHY_TX_TXCAL45DN_MASK 0xF00u -#define USBPHY_TX_TXCAL45DN_SHIFT 8 -#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DN_SHIFT))&USBPHY_TX_TXCAL45DN_MASK) -#define USBPHY_TX_RSVD1_MASK 0xF000u -#define USBPHY_TX_RSVD1_SHIFT 12 -#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD1_SHIFT))&USBPHY_TX_RSVD1_MASK) -#define USBPHY_TX_TXCAL45DP_MASK 0xF0000u -#define USBPHY_TX_TXCAL45DP_SHIFT 16 -#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DP_SHIFT))&USBPHY_TX_TXCAL45DP_MASK) -#define USBPHY_TX_RSVD2_MASK 0x3F00000u -#define USBPHY_TX_RSVD2_SHIFT 20 -#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD2_SHIFT))&USBPHY_TX_RSVD2_MASK) -#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK 0x1C000000u -#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT 26 -#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) -#define USBPHY_TX_RSVD5_MASK 0xE0000000u -#define USBPHY_TX_RSVD5_SHIFT 29 -#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD5_SHIFT))&USBPHY_TX_RSVD5_MASK) -/* TX_SET Bit Fields */ -#define USBPHY_TX_SET_D_CAL_MASK 0xFu -#define USBPHY_TX_SET_D_CAL_SHIFT 0 -#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_D_CAL_SHIFT))&USBPHY_TX_SET_D_CAL_MASK) -#define USBPHY_TX_SET_RSVD0_MASK 0xF0u -#define USBPHY_TX_SET_RSVD0_SHIFT 4 -#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD0_SHIFT))&USBPHY_TX_SET_RSVD0_MASK) -#define USBPHY_TX_SET_TXCAL45DN_MASK 0xF00u -#define USBPHY_TX_SET_TXCAL45DN_SHIFT 8 -#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_TXCAL45DN_SHIFT))&USBPHY_TX_SET_TXCAL45DN_MASK) -#define USBPHY_TX_SET_RSVD1_MASK 0xF000u -#define USBPHY_TX_SET_RSVD1_SHIFT 12 -#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD1_SHIFT))&USBPHY_TX_SET_RSVD1_MASK) -#define USBPHY_TX_SET_TXCAL45DP_MASK 0xF0000u -#define USBPHY_TX_SET_TXCAL45DP_SHIFT 16 -#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_TXCAL45DP_SHIFT))&USBPHY_TX_SET_TXCAL45DP_MASK) -#define USBPHY_TX_SET_RSVD2_MASK 0x3F00000u -#define USBPHY_TX_SET_RSVD2_SHIFT 20 -#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD2_SHIFT))&USBPHY_TX_SET_RSVD2_MASK) -#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK 0x1C000000u -#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT 26 -#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) -#define USBPHY_TX_SET_RSVD5_MASK 0xE0000000u -#define USBPHY_TX_SET_RSVD5_SHIFT 29 -#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD5_SHIFT))&USBPHY_TX_SET_RSVD5_MASK) -/* TX_CLR Bit Fields */ -#define USBPHY_TX_CLR_D_CAL_MASK 0xFu -#define USBPHY_TX_CLR_D_CAL_SHIFT 0 -#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_D_CAL_SHIFT))&USBPHY_TX_CLR_D_CAL_MASK) -#define USBPHY_TX_CLR_RSVD0_MASK 0xF0u -#define USBPHY_TX_CLR_RSVD0_SHIFT 4 -#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD0_SHIFT))&USBPHY_TX_CLR_RSVD0_MASK) -#define USBPHY_TX_CLR_TXCAL45DN_MASK 0xF00u -#define USBPHY_TX_CLR_TXCAL45DN_SHIFT 8 -#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_TXCAL45DN_SHIFT))&USBPHY_TX_CLR_TXCAL45DN_MASK) -#define USBPHY_TX_CLR_RSVD1_MASK 0xF000u -#define USBPHY_TX_CLR_RSVD1_SHIFT 12 -#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD1_SHIFT))&USBPHY_TX_CLR_RSVD1_MASK) -#define USBPHY_TX_CLR_TXCAL45DP_MASK 0xF0000u -#define USBPHY_TX_CLR_TXCAL45DP_SHIFT 16 -#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_TXCAL45DP_SHIFT))&USBPHY_TX_CLR_TXCAL45DP_MASK) -#define USBPHY_TX_CLR_RSVD2_MASK 0x3F00000u -#define USBPHY_TX_CLR_RSVD2_SHIFT 20 -#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD2_SHIFT))&USBPHY_TX_CLR_RSVD2_MASK) -#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK 0x1C000000u -#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT 26 -#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) -#define USBPHY_TX_CLR_RSVD5_MASK 0xE0000000u -#define USBPHY_TX_CLR_RSVD5_SHIFT 29 -#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD5_SHIFT))&USBPHY_TX_CLR_RSVD5_MASK) -/* TX_TOG Bit Fields */ -#define USBPHY_TX_TOG_D_CAL_MASK 0xFu -#define USBPHY_TX_TOG_D_CAL_SHIFT 0 -#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_D_CAL_SHIFT))&USBPHY_TX_TOG_D_CAL_MASK) -#define USBPHY_TX_TOG_RSVD0_MASK 0xF0u -#define USBPHY_TX_TOG_RSVD0_SHIFT 4 -#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD0_SHIFT))&USBPHY_TX_TOG_RSVD0_MASK) -#define USBPHY_TX_TOG_TXCAL45DN_MASK 0xF00u -#define USBPHY_TX_TOG_TXCAL45DN_SHIFT 8 -#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_TXCAL45DN_SHIFT))&USBPHY_TX_TOG_TXCAL45DN_MASK) -#define USBPHY_TX_TOG_RSVD1_MASK 0xF000u -#define USBPHY_TX_TOG_RSVD1_SHIFT 12 -#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD1_SHIFT))&USBPHY_TX_TOG_RSVD1_MASK) -#define USBPHY_TX_TOG_TXCAL45DP_MASK 0xF0000u -#define USBPHY_TX_TOG_TXCAL45DP_SHIFT 16 -#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_TXCAL45DP_SHIFT))&USBPHY_TX_TOG_TXCAL45DP_MASK) -#define USBPHY_TX_TOG_RSVD2_MASK 0x3F00000u -#define USBPHY_TX_TOG_RSVD2_SHIFT 20 -#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD2_SHIFT))&USBPHY_TX_TOG_RSVD2_MASK) -#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK 0x1C000000u -#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT 26 -#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) -#define USBPHY_TX_TOG_RSVD5_MASK 0xE0000000u -#define USBPHY_TX_TOG_RSVD5_SHIFT 29 -#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD5_SHIFT))&USBPHY_TX_TOG_RSVD5_MASK) -/* RX Bit Fields */ -#define USBPHY_RX_ENVADJ_MASK 0x7u -#define USBPHY_RX_ENVADJ_SHIFT 0 -#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_ENVADJ_SHIFT))&USBPHY_RX_ENVADJ_MASK) -#define USBPHY_RX_RSVD0_MASK 0x8u -#define USBPHY_RX_RSVD0_SHIFT 3 -#define USBPHY_RX_DISCONADJ_MASK 0x70u -#define USBPHY_RX_DISCONADJ_SHIFT 4 -#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_DISCONADJ_SHIFT))&USBPHY_RX_DISCONADJ_MASK) -#define USBPHY_RX_RSVD1_MASK 0x3FFF80u -#define USBPHY_RX_RSVD1_SHIFT 7 -#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD1_SHIFT))&USBPHY_RX_RSVD1_MASK) -#define USBPHY_RX_RXDBYPASS_MASK 0x400000u -#define USBPHY_RX_RXDBYPASS_SHIFT 22 -#define USBPHY_RX_RSVD2_MASK 0xFF800000u -#define USBPHY_RX_RSVD2_SHIFT 23 -#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD2_SHIFT))&USBPHY_RX_RSVD2_MASK) -/* RX_SET Bit Fields */ -#define USBPHY_RX_SET_ENVADJ_MASK 0x7u -#define USBPHY_RX_SET_ENVADJ_SHIFT 0 -#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_ENVADJ_SHIFT))&USBPHY_RX_SET_ENVADJ_MASK) -#define USBPHY_RX_SET_RSVD0_MASK 0x8u -#define USBPHY_RX_SET_RSVD0_SHIFT 3 -#define USBPHY_RX_SET_DISCONADJ_MASK 0x70u -#define USBPHY_RX_SET_DISCONADJ_SHIFT 4 -#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_DISCONADJ_SHIFT))&USBPHY_RX_SET_DISCONADJ_MASK) -#define USBPHY_RX_SET_RSVD1_MASK 0x3FFF80u -#define USBPHY_RX_SET_RSVD1_SHIFT 7 -#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD1_SHIFT))&USBPHY_RX_SET_RSVD1_MASK) -#define USBPHY_RX_SET_RXDBYPASS_MASK 0x400000u -#define USBPHY_RX_SET_RXDBYPASS_SHIFT 22 -#define USBPHY_RX_SET_RSVD2_MASK 0xFF800000u -#define USBPHY_RX_SET_RSVD2_SHIFT 23 -#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD2_SHIFT))&USBPHY_RX_SET_RSVD2_MASK) -/* RX_CLR Bit Fields */ -#define USBPHY_RX_CLR_ENVADJ_MASK 0x7u -#define USBPHY_RX_CLR_ENVADJ_SHIFT 0 -#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_ENVADJ_SHIFT))&USBPHY_RX_CLR_ENVADJ_MASK) -#define USBPHY_RX_CLR_RSVD0_MASK 0x8u -#define USBPHY_RX_CLR_RSVD0_SHIFT 3 -#define USBPHY_RX_CLR_DISCONADJ_MASK 0x70u -#define USBPHY_RX_CLR_DISCONADJ_SHIFT 4 -#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_DISCONADJ_SHIFT))&USBPHY_RX_CLR_DISCONADJ_MASK) -#define USBPHY_RX_CLR_RSVD1_MASK 0x3FFF80u -#define USBPHY_RX_CLR_RSVD1_SHIFT 7 -#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD1_SHIFT))&USBPHY_RX_CLR_RSVD1_MASK) -#define USBPHY_RX_CLR_RXDBYPASS_MASK 0x400000u -#define USBPHY_RX_CLR_RXDBYPASS_SHIFT 22 -#define USBPHY_RX_CLR_RSVD2_MASK 0xFF800000u -#define USBPHY_RX_CLR_RSVD2_SHIFT 23 -#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD2_SHIFT))&USBPHY_RX_CLR_RSVD2_MASK) -/* RX_TOG Bit Fields */ -#define USBPHY_RX_TOG_ENVADJ_MASK 0x7u -#define USBPHY_RX_TOG_ENVADJ_SHIFT 0 -#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_ENVADJ_SHIFT))&USBPHY_RX_TOG_ENVADJ_MASK) -#define USBPHY_RX_TOG_RSVD0_MASK 0x8u -#define USBPHY_RX_TOG_RSVD0_SHIFT 3 -#define USBPHY_RX_TOG_DISCONADJ_MASK 0x70u -#define USBPHY_RX_TOG_DISCONADJ_SHIFT 4 -#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_DISCONADJ_SHIFT))&USBPHY_RX_TOG_DISCONADJ_MASK) -#define USBPHY_RX_TOG_RSVD1_MASK 0x3FFF80u -#define USBPHY_RX_TOG_RSVD1_SHIFT 7 -#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD1_SHIFT))&USBPHY_RX_TOG_RSVD1_MASK) -#define USBPHY_RX_TOG_RXDBYPASS_MASK 0x400000u -#define USBPHY_RX_TOG_RXDBYPASS_SHIFT 22 -#define USBPHY_RX_TOG_RSVD2_MASK 0xFF800000u -#define USBPHY_RX_TOG_RSVD2_SHIFT 23 -#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD2_SHIFT))&USBPHY_RX_TOG_RSVD2_MASK) -/* CTRL Bit Fields */ -#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK 0x1u -#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT 0 -#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK 0x2u -#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT 1 -#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK 0x4u -#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT 2 -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK 0x8u -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT 3 -#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK 0x10u -#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT 4 -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK 0x20u -#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT 5 -#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK 0x40u -#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT 6 -#define USBPHY_CTRL_ENOTGIDDETECT_MASK 0x80u -#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT 7 -#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK 0x100u -#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT 8 -#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK 0x200u -#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT 9 -#define USBPHY_CTRL_RESUME_IRQ_MASK 0x400u -#define USBPHY_CTRL_RESUME_IRQ_SHIFT 10 -#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK 0x800u -#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT 11 -#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK 0x1000u -#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT 12 -#define USBPHY_CTRL_DATA_ON_LRADC_MASK 0x2000u -#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT 13 -#define USBPHY_CTRL_ENUTMILEVEL2_MASK 0x4000u -#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT 14 -#define USBPHY_CTRL_ENUTMILEVEL3_MASK 0x8000u -#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT 15 -#define USBPHY_CTRL_ENIRQWAKEUP_MASK 0x10000u -#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT 16 -#define USBPHY_CTRL_WAKEUP_IRQ_MASK 0x20000u -#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT 17 -#define USBPHY_CTRL_RSVD0_MASK 0x40000u -#define USBPHY_CTRL_RSVD0_SHIFT 18 -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK 0x80000u -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT 19 -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK 0x100000u -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT 20 -#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK 0x200000u -#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT 21 -#define USBPHY_CTRL_ENIDCHG_WKUP_MASK 0x400000u -#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT 22 -#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK 0x800000u -#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT 23 -#define USBPHY_CTRL_FSDLL_RST_EN_MASK 0x1000000u -#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT 24 -#define USBPHY_CTRL_RSVD1_MASK 0x6000000u -#define USBPHY_CTRL_RSVD1_SHIFT 25 -#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_RSVD1_SHIFT))&USBPHY_CTRL_RSVD1_MASK) -#define USBPHY_CTRL_OTG_ID_VALUE_MASK 0x8000000u -#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT 27 -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK 0x10000000u -#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT 28 -#define USBPHY_CTRL_UTMI_SUSPENDM_MASK 0x20000000u -#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT 29 -#define USBPHY_CTRL_CLKGATE_MASK 0x40000000u -#define USBPHY_CTRL_CLKGATE_SHIFT 30 -#define USBPHY_CTRL_SFTRST_MASK 0x80000000u -#define USBPHY_CTRL_SFTRST_SHIFT 31 -/* CTRL_SET Bit Fields */ -#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK 0x1u -#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT 0 -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK 0x2u -#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT 1 -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK 0x4u -#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT 2 -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK 0x8u -#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT 3 -#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK 0x10u -#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT 4 -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK 0x20u -#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT 5 -#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK 0x40u -#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT 6 -#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK 0x80u -#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT 7 -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK 0x100u -#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT 8 -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK 0x200u -#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT 9 -#define USBPHY_CTRL_SET_RESUME_IRQ_MASK 0x400u -#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT 10 -#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK 0x800u -#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT 11 -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK 0x1000u -#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT 12 -#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK 0x2000u -#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT 13 -#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK 0x4000u -#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT 14 -#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK 0x8000u -#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT 15 -#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK 0x10000u -#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT 16 -#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK 0x20000u -#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT 17 -#define USBPHY_CTRL_SET_RSVD0_MASK 0x40000u -#define USBPHY_CTRL_SET_RSVD0_SHIFT 18 -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK 0x80000u -#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT 19 -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK 0x100000u -#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT 20 -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK 0x200000u -#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT 21 -#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK 0x400000u -#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT 22 -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK 0x800000u -#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT 23 -#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK 0x1000000u -#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT 24 -#define USBPHY_CTRL_SET_RSVD1_MASK 0x6000000u -#define USBPHY_CTRL_SET_RSVD1_SHIFT 25 -#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_SET_RSVD1_SHIFT))&USBPHY_CTRL_SET_RSVD1_MASK) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK 0x8000000u -#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT 27 -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK 0x10000000u -#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT 28 -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK 0x20000000u -#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT 29 -#define USBPHY_CTRL_SET_CLKGATE_MASK 0x40000000u -#define USBPHY_CTRL_SET_CLKGATE_SHIFT 30 -#define USBPHY_CTRL_SET_SFTRST_MASK 0x80000000u -#define USBPHY_CTRL_SET_SFTRST_SHIFT 31 -/* CTRL_CLR Bit Fields */ -#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK 0x1u -#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT 0 -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK 0x2u -#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT 1 -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK 0x4u -#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT 2 -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK 0x8u -#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT 3 -#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK 0x10u -#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT 4 -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK 0x20u -#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT 5 -#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK 0x40u -#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT 6 -#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK 0x80u -#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT 7 -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK 0x100u -#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT 8 -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK 0x200u -#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT 9 -#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK 0x400u -#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT 10 -#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK 0x800u -#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT 11 -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK 0x1000u -#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT 12 -#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK 0x2000u -#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT 13 -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK 0x4000u -#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT 14 -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK 0x8000u -#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT 15 -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK 0x10000u -#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT 16 -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK 0x20000u -#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT 17 -#define USBPHY_CTRL_CLR_RSVD0_MASK 0x40000u -#define USBPHY_CTRL_CLR_RSVD0_SHIFT 18 -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK 0x80000u -#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT 19 -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK 0x100000u -#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT 20 -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK 0x200000u -#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT 21 -#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK 0x400000u -#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT 22 -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK 0x800000u -#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT 23 -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK 0x1000000u -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT 24 -#define USBPHY_CTRL_CLR_RSVD1_MASK 0x6000000u -#define USBPHY_CTRL_CLR_RSVD1_SHIFT 25 -#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_CLR_RSVD1_SHIFT))&USBPHY_CTRL_CLR_RSVD1_MASK) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK 0x8000000u -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT 27 -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK 0x10000000u -#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT 28 -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK 0x20000000u -#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT 29 -#define USBPHY_CTRL_CLR_CLKGATE_MASK 0x40000000u -#define USBPHY_CTRL_CLR_CLKGATE_SHIFT 30 -#define USBPHY_CTRL_CLR_SFTRST_MASK 0x80000000u -#define USBPHY_CTRL_CLR_SFTRST_SHIFT 31 -/* CTRL_TOG Bit Fields */ -#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK 0x1u -#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT 0 -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK 0x2u -#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT 1 -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK 0x4u -#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT 2 -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK 0x8u -#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT 3 -#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK 0x10u -#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT 4 -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK 0x20u -#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT 5 -#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK 0x40u -#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT 6 -#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK 0x80u -#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT 7 -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK 0x100u -#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT 8 -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK 0x200u -#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT 9 -#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK 0x400u -#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT 10 -#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK 0x800u -#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT 11 -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK 0x1000u -#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT 12 -#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK 0x2000u -#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT 13 -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK 0x4000u -#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT 14 -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK 0x8000u -#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT 15 -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK 0x10000u -#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT 16 -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK 0x20000u -#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT 17 -#define USBPHY_CTRL_TOG_RSVD0_MASK 0x40000u -#define USBPHY_CTRL_TOG_RSVD0_SHIFT 18 -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK 0x80000u -#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT 19 -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK 0x100000u -#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT 20 -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK 0x200000u -#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT 21 -#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK 0x400000u -#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT 22 -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK 0x800000u -#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT 23 -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK 0x1000000u -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT 24 -#define USBPHY_CTRL_TOG_RSVD1_MASK 0x6000000u -#define USBPHY_CTRL_TOG_RSVD1_SHIFT 25 -#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_TOG_RSVD1_SHIFT))&USBPHY_CTRL_TOG_RSVD1_MASK) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK 0x8000000u -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT 27 -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK 0x10000000u -#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT 28 -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK 0x20000000u -#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT 29 -#define USBPHY_CTRL_TOG_CLKGATE_MASK 0x40000000u -#define USBPHY_CTRL_TOG_CLKGATE_SHIFT 30 -#define USBPHY_CTRL_TOG_SFTRST_MASK 0x80000000u -#define USBPHY_CTRL_TOG_SFTRST_SHIFT 31 -/* STATUS Bit Fields */ -#define USBPHY_STATUS_RSVD0_MASK 0x7u -#define USBPHY_STATUS_RSVD0_SHIFT 0 -#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD0_SHIFT))&USBPHY_STATUS_RSVD0_MASK) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK 0x8u -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT 3 -#define USBPHY_STATUS_RSVD1_MASK 0x30u -#define USBPHY_STATUS_RSVD1_SHIFT 4 -#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD1_SHIFT))&USBPHY_STATUS_RSVD1_MASK) -#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK 0x40u -#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT 6 -#define USBPHY_STATUS_RSVD2_MASK 0x80u -#define USBPHY_STATUS_RSVD2_SHIFT 7 -#define USBPHY_STATUS_OTGID_STATUS_MASK 0x100u -#define USBPHY_STATUS_OTGID_STATUS_SHIFT 8 -#define USBPHY_STATUS_RSVD3_MASK 0x200u -#define USBPHY_STATUS_RSVD3_SHIFT 9 -#define USBPHY_STATUS_RESUME_STATUS_MASK 0x400u -#define USBPHY_STATUS_RESUME_STATUS_SHIFT 10 -#define USBPHY_STATUS_RSVD4_MASK 0xFFFFF800u -#define USBPHY_STATUS_RSVD4_SHIFT 11 -#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD4_SHIFT))&USBPHY_STATUS_RSVD4_MASK) -/* DEBUG Bit Fields */ -#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK 0x1u -#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT 0 -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK 0x2u -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT 1 -#define USBPHY_DEBUG_HSTPULLDOWN_MASK 0xCu -#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT 2 -#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK 0x30u -#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT 4 -#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG_RSVD0_MASK 0xC0u -#define USBPHY_DEBUG_RSVD0_SHIFT 6 -#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD0_SHIFT))&USBPHY_DEBUG_RSVD0_MASK) -#define USBPHY_DEBUG_TX2RXCOUNT_MASK 0xF00u -#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT 8 -#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK 0x1000u -#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT 12 -#define USBPHY_DEBUG_RSVD1_MASK 0xE000u -#define USBPHY_DEBUG_RSVD1_SHIFT 13 -#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD1_SHIFT))&USBPHY_DEBUG_RSVD1_MASK) -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK 0x1F0000u -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT 16 -#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG_RSVD2_MASK 0xE00000u -#define USBPHY_DEBUG_RSVD2_SHIFT 21 -#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD2_SHIFT))&USBPHY_DEBUG_RSVD2_MASK) -#define USBPHY_DEBUG_ENSQUELCHRESET_MASK 0x1000000u -#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT 24 -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK 0x1E000000u -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT 25 -#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK 0x20000000u -#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT 29 -#define USBPHY_DEBUG_CLKGATE_MASK 0x40000000u -#define USBPHY_DEBUG_CLKGATE_SHIFT 30 -#define USBPHY_DEBUG_RSVD3_MASK 0x80000000u -#define USBPHY_DEBUG_RSVD3_SHIFT 31 -/* DEBUG_SET Bit Fields */ -#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK 0x1u -#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT 0 -#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK 0x2u -#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT 1 -#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK 0xCu -#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT 2 -#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK 0x30u -#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT 4 -#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG_SET_RSVD0_MASK 0xC0u -#define USBPHY_DEBUG_SET_RSVD0_SHIFT 6 -#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD0_SHIFT))&USBPHY_DEBUG_SET_RSVD0_MASK) -#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK 0xF00u -#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT 8 -#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK 0x1000u -#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT 12 -#define USBPHY_DEBUG_SET_RSVD1_MASK 0xE000u -#define USBPHY_DEBUG_SET_RSVD1_SHIFT 13 -#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD1_SHIFT))&USBPHY_DEBUG_SET_RSVD1_MASK) -#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK 0x1F0000u -#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT 16 -#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG_SET_RSVD2_MASK 0xE00000u -#define USBPHY_DEBUG_SET_RSVD2_SHIFT 21 -#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD2_SHIFT))&USBPHY_DEBUG_SET_RSVD2_MASK) -#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK 0x1000000u -#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT 24 -#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK 0x1E000000u -#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT 25 -#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK 0x20000000u -#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT 29 -#define USBPHY_DEBUG_SET_CLKGATE_MASK 0x40000000u -#define USBPHY_DEBUG_SET_CLKGATE_SHIFT 30 -#define USBPHY_DEBUG_SET_RSVD3_MASK 0x80000000u -#define USBPHY_DEBUG_SET_RSVD3_SHIFT 31 -/* DEBUG_CLR Bit Fields */ -#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK 0x1u -#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT 0 -#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK 0x2u -#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT 1 -#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK 0xCu -#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT 2 -#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK 0x30u -#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT 4 -#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG_CLR_RSVD0_MASK 0xC0u -#define USBPHY_DEBUG_CLR_RSVD0_SHIFT 6 -#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD0_SHIFT))&USBPHY_DEBUG_CLR_RSVD0_MASK) -#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK 0xF00u -#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT 8 -#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK 0x1000u -#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT 12 -#define USBPHY_DEBUG_CLR_RSVD1_MASK 0xE000u -#define USBPHY_DEBUG_CLR_RSVD1_SHIFT 13 -#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD1_SHIFT))&USBPHY_DEBUG_CLR_RSVD1_MASK) -#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK 0x1F0000u -#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT 16 -#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG_CLR_RSVD2_MASK 0xE00000u -#define USBPHY_DEBUG_CLR_RSVD2_SHIFT 21 -#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD2_SHIFT))&USBPHY_DEBUG_CLR_RSVD2_MASK) -#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK 0x1000000u -#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT 24 -#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK 0x1E000000u -#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT 25 -#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK 0x20000000u -#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT 29 -#define USBPHY_DEBUG_CLR_CLKGATE_MASK 0x40000000u -#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT 30 -#define USBPHY_DEBUG_CLR_RSVD3_MASK 0x80000000u -#define USBPHY_DEBUG_CLR_RSVD3_SHIFT 31 -/* DEBUG_TOG Bit Fields */ -#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK 0x1u -#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT 0 -#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK 0x2u -#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT 1 -#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK 0xCu -#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT 2 -#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK 0x30u -#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT 4 -#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG_TOG_RSVD0_MASK 0xC0u -#define USBPHY_DEBUG_TOG_RSVD0_SHIFT 6 -#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD0_SHIFT))&USBPHY_DEBUG_TOG_RSVD0_MASK) -#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK 0xF00u -#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT 8 -#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK 0x1000u -#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT 12 -#define USBPHY_DEBUG_TOG_RSVD1_MASK 0xE000u -#define USBPHY_DEBUG_TOG_RSVD1_SHIFT 13 -#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD1_SHIFT))&USBPHY_DEBUG_TOG_RSVD1_MASK) -#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK 0x1F0000u -#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT 16 -#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG_TOG_RSVD2_MASK 0xE00000u -#define USBPHY_DEBUG_TOG_RSVD2_SHIFT 21 -#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD2_SHIFT))&USBPHY_DEBUG_TOG_RSVD2_MASK) -#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK 0x1000000u -#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT 24 -#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK 0x1E000000u -#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT 25 -#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK 0x20000000u -#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT 29 -#define USBPHY_DEBUG_TOG_CLKGATE_MASK 0x40000000u -#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT 30 -#define USBPHY_DEBUG_TOG_RSVD3_MASK 0x80000000u -#define USBPHY_DEBUG_TOG_RSVD3_SHIFT 31 -/* DEBUG0_STATUS Bit Fields */ -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK 0xFFFFu -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT 0 -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK 0x3FF0000u -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT 16 -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK 0xFC000000u -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT 26 -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) -/* DEBUG1 Bit Fields */ -#define USBPHY_DEBUG1_RSVD0_MASK 0x1FFFu -#define USBPHY_DEBUG1_RSVD0_SHIFT 0 -#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD0_SHIFT))&USBPHY_DEBUG1_RSVD0_MASK) -#define USBPHY_DEBUG1_ENTAILADJVD_MASK 0x6000u -#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT 13 -#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_RSVD1_MASK 0xFFFF8000u -#define USBPHY_DEBUG1_RSVD1_SHIFT 15 -#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD1_SHIFT))&USBPHY_DEBUG1_RSVD1_MASK) -/* DEBUG1_SET Bit Fields */ -#define USBPHY_DEBUG1_SET_RSVD0_MASK 0x1FFFu -#define USBPHY_DEBUG1_SET_RSVD0_SHIFT 0 -#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD0_SHIFT))&USBPHY_DEBUG1_SET_RSVD0_MASK) -#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK 0x6000u -#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT 13 -#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_SET_RSVD1_MASK 0xFFFF8000u -#define USBPHY_DEBUG1_SET_RSVD1_SHIFT 15 -#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD1_SHIFT))&USBPHY_DEBUG1_SET_RSVD1_MASK) -/* DEBUG1_CLR Bit Fields */ -#define USBPHY_DEBUG1_CLR_RSVD0_MASK 0x1FFFu -#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT 0 -#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD0_SHIFT))&USBPHY_DEBUG1_CLR_RSVD0_MASK) -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK 0x6000u -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT 13 -#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_CLR_RSVD1_MASK 0xFFFF8000u -#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT 15 -#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD1_SHIFT))&USBPHY_DEBUG1_CLR_RSVD1_MASK) -/* DEBUG1_TOG Bit Fields */ -#define USBPHY_DEBUG1_TOG_RSVD0_MASK 0x1FFFu -#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT 0 -#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD0_SHIFT))&USBPHY_DEBUG1_TOG_RSVD0_MASK) -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK 0x6000u -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT 13 -#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_TOG_RSVD1_MASK 0xFFFF8000u -#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT 15 -#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD1_SHIFT))&USBPHY_DEBUG1_TOG_RSVD1_MASK) -/* VERSION Bit Fields */ -#define USBPHY_VERSION_STEP_MASK 0xFFFFu -#define USBPHY_VERSION_STEP_SHIFT 0 -#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_STEP_SHIFT))&USBPHY_VERSION_STEP_MASK) -#define USBPHY_VERSION_MINOR_MASK 0xFF0000u -#define USBPHY_VERSION_MINOR_SHIFT 16 -#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MINOR_SHIFT))&USBPHY_VERSION_MINOR_MASK) -#define USBPHY_VERSION_MAJOR_MASK 0xFF000000u -#define USBPHY_VERSION_MAJOR_SHIFT 24 -#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MAJOR_SHIFT))&USBPHY_VERSION_MAJOR_MASK) - -/*! - * @} - */ /* end of group USBPHY_Register_Masks */ - - -/* USBPHY - Peripheral instance base addresses */ -/** Peripheral USBPHY1 base address */ -#define USBPHY1_BASE (0x30361000u) -/** Peripheral USBPHY1 base pointer */ -#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) -#define USBPHY1_BASE_PTR (USBPHY1) -/** Peripheral USBPHY2 base address */ -#define USBPHY2_BASE (0x30362000u) -/** Peripheral USBPHY2 base pointer */ -#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) -#define USBPHY2_BASE_PTR (USBPHY2) -/** Array initializer of USBPHY peripheral base adresses */ -#define USBPHY_BASE_ADDRS { USBPHY1_BASE, USBPHY2_BASE } -/** Array initializer of USBPHY peripheral base pointers */ -#define USBPHY_BASE_PTRS { USBPHY1, USBPHY2 } - -/* ---------------------------------------------------------------------------- - -- USBPHY - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USBPHY_Register_Accessor_Macros USBPHY - Register accessor macros - * @{ - */ - - -/* USBPHY - Register instance definitions */ -/* USBPHY1 */ -#define USBPHY1_PWD USBPHY_PWD_REG(USBPHY1_BASE_PTR) -#define USBPHY1_PWD_SET USBPHY_PWD_SET_REG(USBPHY1_BASE_PTR) -#define USBPHY1_PWD_CLR USBPHY_PWD_CLR_REG(USBPHY1_BASE_PTR) -#define USBPHY1_PWD_TOG USBPHY_PWD_TOG_REG(USBPHY1_BASE_PTR) -#define USBPHY1_TX USBPHY_TX_REG(USBPHY1_BASE_PTR) -#define USBPHY1_TX_SET USBPHY_TX_SET_REG(USBPHY1_BASE_PTR) -#define USBPHY1_TX_CLR USBPHY_TX_CLR_REG(USBPHY1_BASE_PTR) -#define USBPHY1_TX_TOG USBPHY_TX_TOG_REG(USBPHY1_BASE_PTR) -#define USBPHY1_RX USBPHY_RX_REG(USBPHY1_BASE_PTR) -#define USBPHY1_RX_SET USBPHY_RX_SET_REG(USBPHY1_BASE_PTR) -#define USBPHY1_RX_CLR USBPHY_RX_CLR_REG(USBPHY1_BASE_PTR) -#define USBPHY1_RX_TOG USBPHY_RX_TOG_REG(USBPHY1_BASE_PTR) -#define USBPHY1_CTRL USBPHY_CTRL_REG(USBPHY1_BASE_PTR) -#define USBPHY1_CTRL_SET USBPHY_CTRL_SET_REG(USBPHY1_BASE_PTR) -#define USBPHY1_CTRL_CLR USBPHY_CTRL_CLR_REG(USBPHY1_BASE_PTR) -#define USBPHY1_CTRL_TOG USBPHY_CTRL_TOG_REG(USBPHY1_BASE_PTR) -#define USBPHY1_STATUS USBPHY_STATUS_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG USBPHY_DEBUG_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG_SET USBPHY_DEBUG_SET_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG_CLR USBPHY_DEBUG_CLR_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG_TOG USBPHY_DEBUG_TOG_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG0_STATUS USBPHY_DEBUG0_STATUS_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG1 USBPHY_DEBUG1_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG1_SET USBPHY_DEBUG1_SET_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG1_CLR USBPHY_DEBUG1_CLR_REG(USBPHY1_BASE_PTR) -#define USBPHY1_DEBUG1_TOG USBPHY_DEBUG1_TOG_REG(USBPHY1_BASE_PTR) -#define USBPHY1_VERSION USBPHY_VERSION_REG(USBPHY1_BASE_PTR) -/* USBPHY2 */ -#define USBPHY2_PWD USBPHY_PWD_REG(USBPHY2_BASE_PTR) -#define USBPHY2_PWD_SET USBPHY_PWD_SET_REG(USBPHY2_BASE_PTR) -#define USBPHY2_PWD_CLR USBPHY_PWD_CLR_REG(USBPHY2_BASE_PTR) -#define USBPHY2_PWD_TOG USBPHY_PWD_TOG_REG(USBPHY2_BASE_PTR) -#define USBPHY2_TX USBPHY_TX_REG(USBPHY2_BASE_PTR) -#define USBPHY2_TX_SET USBPHY_TX_SET_REG(USBPHY2_BASE_PTR) -#define USBPHY2_TX_CLR USBPHY_TX_CLR_REG(USBPHY2_BASE_PTR) -#define USBPHY2_TX_TOG USBPHY_TX_TOG_REG(USBPHY2_BASE_PTR) -#define USBPHY2_RX USBPHY_RX_REG(USBPHY2_BASE_PTR) -#define USBPHY2_RX_SET USBPHY_RX_SET_REG(USBPHY2_BASE_PTR) -#define USBPHY2_RX_CLR USBPHY_RX_CLR_REG(USBPHY2_BASE_PTR) -#define USBPHY2_RX_TOG USBPHY_RX_TOG_REG(USBPHY2_BASE_PTR) -#define USBPHY2_CTRL USBPHY_CTRL_REG(USBPHY2_BASE_PTR) -#define USBPHY2_CTRL_SET USBPHY_CTRL_SET_REG(USBPHY2_BASE_PTR) -#define USBPHY2_CTRL_CLR USBPHY_CTRL_CLR_REG(USBPHY2_BASE_PTR) -#define USBPHY2_CTRL_TOG USBPHY_CTRL_TOG_REG(USBPHY2_BASE_PTR) -#define USBPHY2_STATUS USBPHY_STATUS_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG USBPHY_DEBUG_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG_SET USBPHY_DEBUG_SET_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG_CLR USBPHY_DEBUG_CLR_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG_TOG USBPHY_DEBUG_TOG_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG0_STATUS USBPHY_DEBUG0_STATUS_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG1 USBPHY_DEBUG1_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG1_SET USBPHY_DEBUG1_SET_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG1_CLR USBPHY_DEBUG1_CLR_REG(USBPHY2_BASE_PTR) -#define USBPHY2_DEBUG1_TOG USBPHY_DEBUG1_TOG_REG(USBPHY2_BASE_PTR) -#define USBPHY2_VERSION USBPHY_VERSION_REG(USBPHY2_BASE_PTR) - -/*! - * @} - */ /* end of group USBPHY_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group USBPHY_Peripheral */ - - -/* ---------------------------------------------------------------------------- - -- USB_ANALOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer - * @{ - */ - -/** USB_ANALOG - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[416]; - __IO uint32_t USB1_VBUS_DETECT; /**< USB VBUS Detect Register, offset: 0x1A0 */ - __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB VBUS Detect Register, offset: 0x1A4 */ - __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB VBUS Detect Register, offset: 0x1A8 */ - __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB VBUS Detect Register, offset: 0x1AC */ - __IO uint32_t USB1_CHRG_DETECT; /**< USB Charger Detect Register, offset: 0x1B0 */ - __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB Charger Detect Register, offset: 0x1B4 */ - __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB Charger Detect Register, offset: 0x1B8 */ - __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB Charger Detect Register, offset: 0x1BC */ - __I uint32_t USB1_VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, offset: 0x1C0 */ - uint8_t RESERVED_1[12]; - __I uint32_t USB1_CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, offset: 0x1D0 */ - uint8_t RESERVED_2[28]; - __IO uint32_t USB1_MISC; /**< USB Misc Register, offset: 0x1F0 */ - __IO uint32_t USB1_MISC_SET; /**< USB Misc Register, offset: 0x1F4 */ - __IO uint32_t USB1_MISC_CLR; /**< USB Misc Register, offset: 0x1F8 */ - __IO uint32_t USB1_MISC_TOG; /**< USB Misc Register, offset: 0x1FC */ - __IO uint32_t USB2_VBUS_DETECT; /**< USB VBUS Detect Register, offset: 0x200 */ - __IO uint32_t USB2_VBUS_DETECT_SET; /**< USB VBUS Detect Register, offset: 0x204 */ - __IO uint32_t USB2_VBUS_DETECT_CLR; /**< USB VBUS Detect Register, offset: 0x208 */ - __IO uint32_t USB2_VBUS_DETECT_TOG; /**< USB VBUS Detect Register, offset: 0x20C */ - __IO uint32_t USB2_CHRG_DETECT; /**< USB Charger Detect Register, offset: 0x210 */ - __IO uint32_t USB2_CHRG_DETECT_SET; /**< USB Charger Detect Register, offset: 0x214 */ - __IO uint32_t USB2_CHRG_DETECT_CLR; /**< USB Charger Detect Register, offset: 0x218 */ - __IO uint32_t USB2_CHRG_DETECT_TOG; /**< USB Charger Detect Register, offset: 0x21C */ - __I uint32_t USB2_VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, offset: 0x220 */ - uint8_t RESERVED_3[12]; - __I uint32_t USB2_CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, offset: 0x230 */ - uint8_t RESERVED_4[28]; - __IO uint32_t USB2_MISC; /**< USB Misc Register, offset: 0x250 */ - __IO uint32_t USB2_MISC_SET; /**< USB Misc Register, offset: 0x254 */ - __IO uint32_t USB2_MISC_CLR; /**< USB Misc Register, offset: 0x258 */ - __IO uint32_t USB2_MISC_TOG; /**< USB Misc Register, offset: 0x25C */ - __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ -} USB_ANALOG_Type, *USB_ANALOG_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- USB_ANALOG - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_ANALOG_Register_Accessor_Macros USB_ANALOG - Register accessor macros - * @{ - */ - - -/* USB_ANALOG - Register accessors */ -#define USB_ANALOG_USB1_VBUS_DETECT_REG(base) ((base)->USB1_VBUS_DETECT) -#define USB_ANALOG_USB1_VBUS_DETECT_SET_REG(base) ((base)->USB1_VBUS_DETECT_SET) -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(base) ((base)->USB1_VBUS_DETECT_CLR) -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(base) ((base)->USB1_VBUS_DETECT_TOG) -#define USB_ANALOG_USB1_CHRG_DETECT_REG(base) ((base)->USB1_CHRG_DETECT) -#define USB_ANALOG_USB1_CHRG_DETECT_SET_REG(base) ((base)->USB1_CHRG_DETECT_SET) -#define USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(base) ((base)->USB1_CHRG_DETECT_CLR) -#define USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(base) ((base)->USB1_CHRG_DETECT_TOG) -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(base) ((base)->USB1_VBUS_DETECT_STAT) -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(base) ((base)->USB1_CHRG_DETECT_STAT) -#define USB_ANALOG_USB1_MISC_REG(base) ((base)->USB1_MISC) -#define USB_ANALOG_USB1_MISC_SET_REG(base) ((base)->USB1_MISC_SET) -#define USB_ANALOG_USB1_MISC_CLR_REG(base) ((base)->USB1_MISC_CLR) -#define USB_ANALOG_USB1_MISC_TOG_REG(base) ((base)->USB1_MISC_TOG) -#define USB_ANALOG_USB2_VBUS_DETECT_REG(base) ((base)->USB2_VBUS_DETECT) -#define USB_ANALOG_USB2_VBUS_DETECT_SET_REG(base) ((base)->USB2_VBUS_DETECT_SET) -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(base) ((base)->USB2_VBUS_DETECT_CLR) -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(base) ((base)->USB2_VBUS_DETECT_TOG) -#define USB_ANALOG_USB2_CHRG_DETECT_REG(base) ((base)->USB2_CHRG_DETECT) -#define USB_ANALOG_USB2_CHRG_DETECT_SET_REG(base) ((base)->USB2_CHRG_DETECT_SET) -#define USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(base) ((base)->USB2_CHRG_DETECT_CLR) -#define USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(base) ((base)->USB2_CHRG_DETECT_TOG) -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(base) ((base)->USB2_VBUS_DETECT_STAT) -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(base) ((base)->USB2_CHRG_DETECT_STAT) -#define USB_ANALOG_USB2_MISC_REG(base) ((base)->USB2_MISC) -#define USB_ANALOG_USB2_MISC_SET_REG(base) ((base)->USB2_MISC_SET) -#define USB_ANALOG_USB2_MISC_CLR_REG(base) ((base)->USB2_MISC_CLR) -#define USB_ANALOG_USB2_MISC_TOG_REG(base) ((base)->USB2_MISC_TOG) -#define USB_ANALOG_DIGPROG_REG(base) ((base)->DIGPROG) - -/*! - * @} - */ /* end of group USB_ANALOG_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- USB_ANALOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks - * @{ - */ - -/* USB1_VBUS_DETECT Bit Fields */ -#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u -#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 -#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u -#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20 -#define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u -#define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26 -#define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u -#define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_SHIFT 27 -/* USB1_VBUS_DETECT_SET Bit Fields */ -#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK 0x7u -#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT 0 -#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK 0x100000u -#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT 20 -#define USB_ANALOG_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK 0x4000000u -#define USB_ANALOG_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT 26 -#define USB_ANALOG_USB1_VBUS_DETECT_SET_CHARGE_VBUS_MASK 0x8000000u -#define USB_ANALOG_USB1_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT 27 -/* USB1_VBUS_DETECT_CLR Bit Fields */ -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK 0x7u -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT 0 -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK 0x100000u -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT 20 -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK 0x4000000u -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT 26 -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_CHARGE_VBUS_MASK 0x8000000u -#define USB_ANALOG_USB1_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT 27 -/* USB1_VBUS_DETECT_TOG Bit Fields */ -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK 0x7u -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT 0 -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK 0x100000u -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT 20 -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK 0x4000000u -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT 26 -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_CHARGE_VBUS_MASK 0x8000000u -#define USB_ANALOG_USB1_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT 27 -/* USB1_CHRG_DETECT Bit Fields */ -#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u -#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT 18 -#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u -#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT 19 -#define USB_ANALOG_USB1_CHRG_DETECT_EN_B_MASK 0x100000u -#define USB_ANALOG_USB1_CHRG_DETECT_EN_B_SHIFT 20 -/* USB1_CHRG_DETECT_SET Bit Fields */ -#define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK 0x40000u -#define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT 18 -#define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK 0x80000u -#define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT 19 -#define USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B_MASK 0x100000u -#define USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B_SHIFT 20 -/* USB1_CHRG_DETECT_CLR Bit Fields */ -#define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK 0x40000u -#define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT 18 -#define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK 0x80000u -#define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT 19 -#define USB_ANALOG_USB1_CHRG_DETECT_CLR_EN_B_MASK 0x100000u -#define USB_ANALOG_USB1_CHRG_DETECT_CLR_EN_B_SHIFT 20 -/* USB1_CHRG_DETECT_TOG Bit Fields */ -#define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK 0x40000u -#define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT 18 -#define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK 0x80000u -#define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT 19 -#define USB_ANALOG_USB1_CHRG_DETECT_TOG_EN_B_MASK 0x100000u -#define USB_ANALOG_USB1_CHRG_DETECT_TOG_EN_B_SHIFT 20 -/* USB1_VBUS_DETECT_STAT Bit Fields */ -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND_MASK 0x1u -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND_SHIFT 0 -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID_MASK 0x2u -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID_SHIFT 1 -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID_MASK 0x4u -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID_SHIFT 2 -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID_MASK 0x8u -#define USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID_SHIFT 3 -/* USB1_CHRG_DETECT_STAT Bit Fields */ -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT_MASK 0x1u -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT 0 -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED_MASK 0x2u -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT 1 -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE_MASK 0x4u -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE_SHIFT 2 -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE_MASK 0x8u -#define USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE_SHIFT 3 -/* USB1_MISC Bit Fields */ -#define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_MASK 0x1u -#define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_SHIFT 0 -#define USB_ANALOG_USB1_MISC_EN_DEGLITCH_MASK 0x2u -#define USB_ANALOG_USB1_MISC_EN_DEGLITCH_SHIFT 1 -#define USB_ANALOG_USB1_MISC_EN_CLK_UTMI_MASK 0x40000000u -#define USB_ANALOG_USB1_MISC_EN_CLK_UTMI_SHIFT 30 -/* USB1_MISC_SET Bit Fields */ -#define USB_ANALOG_USB1_MISC_SET_HS_USE_EXTERNAL_R_MASK 0x1u -#define USB_ANALOG_USB1_MISC_SET_HS_USE_EXTERNAL_R_SHIFT 0 -#define USB_ANALOG_USB1_MISC_SET_EN_DEGLITCH_MASK 0x2u -#define USB_ANALOG_USB1_MISC_SET_EN_DEGLITCH_SHIFT 1 -#define USB_ANALOG_USB1_MISC_SET_EN_CLK_UTMI_MASK 0x40000000u -#define USB_ANALOG_USB1_MISC_SET_EN_CLK_UTMI_SHIFT 30 -/* USB1_MISC_CLR Bit Fields */ -#define USB_ANALOG_USB1_MISC_CLR_HS_USE_EXTERNAL_R_MASK 0x1u -#define USB_ANALOG_USB1_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT 0 -#define USB_ANALOG_USB1_MISC_CLR_EN_DEGLITCH_MASK 0x2u -#define USB_ANALOG_USB1_MISC_CLR_EN_DEGLITCH_SHIFT 1 -#define USB_ANALOG_USB1_MISC_CLR_EN_CLK_UTMI_MASK 0x40000000u -#define USB_ANALOG_USB1_MISC_CLR_EN_CLK_UTMI_SHIFT 30 -/* USB1_MISC_TOG Bit Fields */ -#define USB_ANALOG_USB1_MISC_TOG_HS_USE_EXTERNAL_R_MASK 0x1u -#define USB_ANALOG_USB1_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT 0 -#define USB_ANALOG_USB1_MISC_TOG_EN_DEGLITCH_MASK 0x2u -#define USB_ANALOG_USB1_MISC_TOG_EN_DEGLITCH_SHIFT 1 -#define USB_ANALOG_USB1_MISC_TOG_EN_CLK_UTMI_MASK 0x40000000u -#define USB_ANALOG_USB1_MISC_TOG_EN_CLK_UTMI_SHIFT 30 -/* USB2_VBUS_DETECT Bit Fields */ -#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u -#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 -#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u -#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20 -#define USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u -#define USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26 -#define USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u -#define USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS_SHIFT 27 -/* USB2_VBUS_DETECT_SET Bit Fields */ -#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK 0x7u -#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT 0 -#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK 0x100000u -#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT 20 -#define USB_ANALOG_USB2_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK 0x4000000u -#define USB_ANALOG_USB2_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT 26 -#define USB_ANALOG_USB2_VBUS_DETECT_SET_CHARGE_VBUS_MASK 0x8000000u -#define USB_ANALOG_USB2_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT 27 -/* USB2_VBUS_DETECT_CLR Bit Fields */ -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK 0x7u -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT 0 -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK 0x100000u -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT 20 -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK 0x4000000u -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT 26 -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_CHARGE_VBUS_MASK 0x8000000u -#define USB_ANALOG_USB2_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT 27 -/* USB2_VBUS_DETECT_TOG Bit Fields */ -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK 0x7u -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT 0 -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK 0x100000u -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT 20 -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK 0x4000000u -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT 26 -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_CHARGE_VBUS_MASK 0x8000000u -#define USB_ANALOG_USB2_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT 27 -/* USB2_CHRG_DETECT Bit Fields */ -#define USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u -#define USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT_SHIFT 18 -#define USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u -#define USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B_SHIFT 19 -#define USB_ANALOG_USB2_CHRG_DETECT_EN_B_MASK 0x100000u -#define USB_ANALOG_USB2_CHRG_DETECT_EN_B_SHIFT 20 -/* USB2_CHRG_DETECT_SET Bit Fields */ -#define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CONTACT_MASK 0x40000u -#define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CONTACT_SHIFT 18 -#define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B_MASK 0x80000u -#define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT 19 -#define USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B_MASK 0x100000u -#define USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B_SHIFT 20 -/* USB2_CHRG_DETECT_CLR Bit Fields */ -#define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CONTACT_MASK 0x40000u -#define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT 18 -#define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CHRG_B_MASK 0x80000u -#define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT 19 -#define USB_ANALOG_USB2_CHRG_DETECT_CLR_EN_B_MASK 0x100000u -#define USB_ANALOG_USB2_CHRG_DETECT_CLR_EN_B_SHIFT 20 -/* USB2_CHRG_DETECT_TOG Bit Fields */ -#define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CONTACT_MASK 0x40000u -#define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT 18 -#define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CHRG_B_MASK 0x80000u -#define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT 19 -#define USB_ANALOG_USB2_CHRG_DETECT_TOG_EN_B_MASK 0x100000u -#define USB_ANALOG_USB2_CHRG_DETECT_TOG_EN_B_SHIFT 20 -/* USB2_VBUS_DETECT_STAT Bit Fields */ -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND_MASK 0x1u -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND_SHIFT 0 -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID_MASK 0x2u -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID_SHIFT 1 -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID_MASK 0x4u -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID_SHIFT 2 -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID_MASK 0x8u -#define USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID_SHIFT 3 -/* USB2_CHRG_DETECT_STAT Bit Fields */ -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT_MASK 0x1u -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT 0 -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED_MASK 0x2u -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT 1 -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE_MASK 0x4u -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE_SHIFT 2 -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE_MASK 0x8u -#define USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE_SHIFT 3 -/* USB2_MISC Bit Fields */ -#define USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R_MASK 0x1u -#define USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R_SHIFT 0 -#define USB_ANALOG_USB2_MISC_EN_DEGLITCH_MASK 0x2u -#define USB_ANALOG_USB2_MISC_EN_DEGLITCH_SHIFT 1 -#define USB_ANALOG_USB2_MISC_EN_CLK_UTMI_MASK 0x40000000u -#define USB_ANALOG_USB2_MISC_EN_CLK_UTMI_SHIFT 30 -/* USB2_MISC_SET Bit Fields */ -#define USB_ANALOG_USB2_MISC_SET_HS_USE_EXTERNAL_R_MASK 0x1u -#define USB_ANALOG_USB2_MISC_SET_HS_USE_EXTERNAL_R_SHIFT 0 -#define USB_ANALOG_USB2_MISC_SET_EN_DEGLITCH_MASK 0x2u -#define USB_ANALOG_USB2_MISC_SET_EN_DEGLITCH_SHIFT 1 -#define USB_ANALOG_USB2_MISC_SET_EN_CLK_UTMI_MASK 0x40000000u -#define USB_ANALOG_USB2_MISC_SET_EN_CLK_UTMI_SHIFT 30 -/* USB2_MISC_CLR Bit Fields */ -#define USB_ANALOG_USB2_MISC_CLR_HS_USE_EXTERNAL_R_MASK 0x1u -#define USB_ANALOG_USB2_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT 0 -#define USB_ANALOG_USB2_MISC_CLR_EN_DEGLITCH_MASK 0x2u -#define USB_ANALOG_USB2_MISC_CLR_EN_DEGLITCH_SHIFT 1 -#define USB_ANALOG_USB2_MISC_CLR_EN_CLK_UTMI_MASK 0x40000000u -#define USB_ANALOG_USB2_MISC_CLR_EN_CLK_UTMI_SHIFT 30 -/* USB2_MISC_TOG Bit Fields */ -#define USB_ANALOG_USB2_MISC_TOG_HS_USE_EXTERNAL_R_MASK 0x1u -#define USB_ANALOG_USB2_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT 0 -#define USB_ANALOG_USB2_MISC_TOG_EN_DEGLITCH_MASK 0x2u -#define USB_ANALOG_USB2_MISC_TOG_EN_DEGLITCH_SHIFT 1 -#define USB_ANALOG_USB2_MISC_TOG_EN_CLK_UTMI_MASK 0x40000000u -#define USB_ANALOG_USB2_MISC_TOG_EN_CLK_UTMI_SHIFT 30 -/* DIGPROG Bit Fields */ -#define USB_ANALOG_DIGPROG_MINOR_MASK 0xFFu -#define USB_ANALOG_DIGPROG_MINOR_SHIFT 0 -#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MINOR_SHIFT))&USB_ANALOG_DIGPROG_MINOR_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK 0xFF00u -#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT 8 -#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT))&USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK 0xFF0000u -#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT 16 -#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT))&USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) - -/*! - * @} - */ /* end of group USB_ANALOG_Register_Masks */ - - -/* USB_ANALOG - Peripheral instance base addresses */ -/** Peripheral USB_ANALOG base address */ -#define USB_ANALOG_BASE (0x30360000u) -/** Peripheral USB_ANALOG base pointer */ -#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) -#define USB_ANALOG_BASE_PTR (USB_ANALOG) -/** Array initializer of USB_ANALOG peripheral base adresses */ -#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } -/** Array initializer of USB_ANALOG peripheral base pointers */ -#define USB_ANALOG_BASE_PTRS { USB_ANALOG } - -/* ---------------------------------------------------------------------------- - -- USB_ANALOG - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_ANALOG_Register_Accessor_Macros USB_ANALOG - Register accessor macros - * @{ - */ - - -/* USB_ANALOG - Register instance definitions */ -/* USB_ANALOG */ -#define USB_ANALOG_USB1_VBUS_DETECT USB_ANALOG_USB1_VBUS_DETECT_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_VBUS_DETECT_SET USB_ANALOG_USB1_VBUS_DETECT_SET_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_VBUS_DETECT_CLR USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_VBUS_DETECT_TOG USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_CHRG_DETECT USB_ANALOG_USB1_CHRG_DETECT_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_CHRG_DETECT_SET USB_ANALOG_USB1_CHRG_DETECT_SET_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_CHRG_DETECT_CLR USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_CHRG_DETECT_TOG USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_VBUS_DETECT_STAT USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_CHRG_DETECT_STAT USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_MISC USB_ANALOG_USB1_MISC_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_MISC_SET USB_ANALOG_USB1_MISC_SET_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_MISC_CLR USB_ANALOG_USB1_MISC_CLR_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB1_MISC_TOG USB_ANALOG_USB1_MISC_TOG_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_VBUS_DETECT USB_ANALOG_USB2_VBUS_DETECT_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_VBUS_DETECT_SET USB_ANALOG_USB2_VBUS_DETECT_SET_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_VBUS_DETECT_CLR USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_VBUS_DETECT_TOG USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_CHRG_DETECT USB_ANALOG_USB2_CHRG_DETECT_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_CHRG_DETECT_SET USB_ANALOG_USB2_CHRG_DETECT_SET_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_CHRG_DETECT_CLR USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_CHRG_DETECT_TOG USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_VBUS_DETECT_STAT USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_CHRG_DETECT_STAT USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_MISC USB_ANALOG_USB2_MISC_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_MISC_SET USB_ANALOG_USB2_MISC_SET_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_MISC_CLR USB_ANALOG_USB2_MISC_CLR_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_USB2_MISC_TOG USB_ANALOG_USB2_MISC_TOG_REG(USB_ANALOG_BASE_PTR) -#define USB_ANALOG_DIGPROG USB_ANALOG_DIGPROG_REG(USB_ANALOG_BASE_PTR) - -/*! - * @} - */ /* end of group USB_ANALOG_Register_Accessor_Macros */ - - -/*! - * @} - */ /* end of group USB_ANALOG_Peripheral */ - - /* ---------------------------------------------------------------------------- -- WDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -95479,7 +43317,6 @@ typedef struct { __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ } WDOG_Type, *WDOG_MemMapPtr; - /* ---------------------------------------------------------------------------- -- WDOG - Register accessor macros ---------------------------------------------------------------------------- */ @@ -95500,8 +43337,6 @@ typedef struct { /*! * @} */ /* end of group WDOG_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ @@ -95558,7 +43393,6 @@ typedef struct { * @} */ /* end of group WDOG_Register_Masks */ - /* WDOG - Peripheral instance base addresses */ /** Peripheral WDOG1 base address */ #define WDOG1_BASE (0x30280000u) @@ -95580,11 +43414,12 @@ typedef struct { /** Peripheral WDOG4 base pointer */ #define WDOG4 ((WDOG_Type *)WDOG4_BASE) #define WDOG4_BASE_PTR (WDOG4) -/** Array initializer of WDOG peripheral base adresses */ +/** Array initializer of WDOG peripheral base addresses */ #define WDOG_BASE_ADDRS { WDOG1_BASE, WDOG2_BASE, WDOG3_BASE, WDOG4_BASE } /** Array initializer of WDOG peripheral base pointers */ #define WDOG_BASE_PTRS { WDOG1, WDOG2, WDOG3, WDOG4 } - +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn, WDOG4_IRQn } /* ---------------------------------------------------------------------------- -- WDOG - Register accessor macros ---------------------------------------------------------------------------- */ @@ -95620,7 +43455,6 @@ typedef struct { #define WDOG4_WRSR WDOG_WRSR_REG(WDOG4_BASE_PTR) #define WDOG4_WICR WDOG_WICR_REG(WDOG4_BASE_PTR) #define WDOG4_WMCR WDOG_WMCR_REG(WDOG4_BASE_PTR) - /*! * @} */ /* end of group WDOG_Register_Accessor_Macros */ @@ -95630,7 +43464,6 @@ typedef struct { * @} */ /* end of group WDOG_Peripheral */ - /* ---------------------------------------------------------------------------- -- XTALOSC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -95664,7 +43497,6 @@ typedef struct { __IO uint32_t OSC_32K_CLR; /**< 32K Oscillator Control Register, offset: 0x58 */ __IO uint32_t OSC_32K_TOG; /**< 32K Oscillator Control Register, offset: 0x5C */ } XTALOSC_Type, *XTALOSC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- XTALOSC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -95700,8 +43532,6 @@ typedef struct { /*! * @} */ /* end of group XTALOSC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- XTALOSC Register Masks ---------------------------------------------------------------------------- */ @@ -95736,13 +43566,9 @@ typedef struct { #define XTALOSC_CTRL_24M_OSC_SEL_SHIFT 12 #define XTALOSC_CTRL_24M_RC_OSC_EN_MASK 0x2000u #define XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT 13 -#define XTALOSC_CTRL_24M_RSVD0_MASK 0x4000u -#define XTALOSC_CTRL_24M_RSVD0_SHIFT 14 #define XTALOSC_CTRL_24M_XTAL_MISC_MASK 0x7FFF8000u #define XTALOSC_CTRL_24M_XTAL_MISC_SHIFT 15 #define XTALOSC_CTRL_24M_XTAL_MISC(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_XTAL_MISC_MASK) -#define XTALOSC_CTRL_24M_RSVD1_MASK 0x80000000u -#define XTALOSC_CTRL_24M_RSVD1_SHIFT 31 /* CTRL_24M_SET Bit Fields */ #define XTALOSC_CTRL_24M_SET_XTAL_24M_PWD_MASK 0x1u #define XTALOSC_CTRL_24M_SET_XTAL_24M_PWD_SHIFT 0 @@ -95768,13 +43594,9 @@ typedef struct { #define XTALOSC_CTRL_24M_SET_OSC_SEL_SHIFT 12 #define XTALOSC_CTRL_24M_SET_RC_OSC_EN_MASK 0x2000u #define XTALOSC_CTRL_24M_SET_RC_OSC_EN_SHIFT 13 -#define XTALOSC_CTRL_24M_SET_RSVD0_MASK 0x4000u -#define XTALOSC_CTRL_24M_SET_RSVD0_SHIFT 14 #define XTALOSC_CTRL_24M_SET_XTAL_MISC_MASK 0x7FFF8000u #define XTALOSC_CTRL_24M_SET_XTAL_MISC_SHIFT 15 #define XTALOSC_CTRL_24M_SET_XTAL_MISC(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_SET_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_SET_XTAL_MISC_MASK) -#define XTALOSC_CTRL_24M_SET_RSVD1_MASK 0x80000000u -#define XTALOSC_CTRL_24M_SET_RSVD1_SHIFT 31 /* CTRL_24M_CLR Bit Fields */ #define XTALOSC_CTRL_24M_CLR_XTAL_24M_PWD_MASK 0x1u #define XTALOSC_CTRL_24M_CLR_XTAL_24M_PWD_SHIFT 0 @@ -95800,13 +43622,9 @@ typedef struct { #define XTALOSC_CTRL_24M_CLR_OSC_SEL_SHIFT 12 #define XTALOSC_CTRL_24M_CLR_RC_OSC_EN_MASK 0x2000u #define XTALOSC_CTRL_24M_CLR_RC_OSC_EN_SHIFT 13 -#define XTALOSC_CTRL_24M_CLR_RSVD0_MASK 0x4000u -#define XTALOSC_CTRL_24M_CLR_RSVD0_SHIFT 14 #define XTALOSC_CTRL_24M_CLR_XTAL_MISC_MASK 0x7FFF8000u #define XTALOSC_CTRL_24M_CLR_XTAL_MISC_SHIFT 15 #define XTALOSC_CTRL_24M_CLR_XTAL_MISC(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLR_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_CLR_XTAL_MISC_MASK) -#define XTALOSC_CTRL_24M_CLR_RSVD1_MASK 0x80000000u -#define XTALOSC_CTRL_24M_CLR_RSVD1_SHIFT 31 /* CTRL_24M_TOG Bit Fields */ #define XTALOSC_CTRL_24M_TOG_XTAL_24M_PWD_MASK 0x1u #define XTALOSC_CTRL_24M_TOG_XTAL_24M_PWD_SHIFT 0 @@ -95832,13 +43650,9 @@ typedef struct { #define XTALOSC_CTRL_24M_TOG_OSC_SEL_SHIFT 12 #define XTALOSC_CTRL_24M_TOG_RC_OSC_EN_MASK 0x2000u #define XTALOSC_CTRL_24M_TOG_RC_OSC_EN_SHIFT 13 -#define XTALOSC_CTRL_24M_TOG_RSVD0_MASK 0x4000u -#define XTALOSC_CTRL_24M_TOG_RSVD0_SHIFT 14 #define XTALOSC_CTRL_24M_TOG_XTAL_MISC_MASK 0x7FFF8000u #define XTALOSC_CTRL_24M_TOG_XTAL_MISC_SHIFT 15 #define XTALOSC_CTRL_24M_TOG_XTAL_MISC(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_TOG_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_TOG_XTAL_MISC_MASK) -#define XTALOSC_CTRL_24M_TOG_RSVD1_MASK 0x80000000u -#define XTALOSC_CTRL_24M_TOG_RSVD1_SHIFT 31 /* RCOSC_CONFIG0 Bit Fields */ #define XTALOSC_RCOSC_CONFIG0_TUNE_START_MASK 0x1u #define XTALOSC_RCOSC_CONFIG0_TUNE_START_SHIFT 0 @@ -95857,9 +43671,6 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG0_HYST_MINUS_MASK 0xF0000u #define XTALOSC_RCOSC_CONFIG0_HYST_MINUS_SHIFT 16 #define XTALOSC_RCOSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_HYST_MINUS_MASK) -#define XTALOSC_RCOSC_CONFIG0_RSVD0_MASK 0xF00000u -#define XTALOSC_RCOSC_CONFIG0_RSVD0_SHIFT 20 -#define XTALOSC_RCOSC_CONFIG0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG0_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_MASK 0xFF000000u #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 #define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_MASK) @@ -95881,9 +43692,6 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_MASK 0xF0000u #define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_SHIFT 16 #define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_MASK) -#define XTALOSC_RCOSC_CONFIG0_SET_RSVD0_MASK 0xF00000u -#define XTALOSC_RCOSC_CONFIG0_SET_RSVD0_SHIFT 20 -#define XTALOSC_RCOSC_CONFIG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK 0xFF000000u #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT 24 #define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) @@ -95905,9 +43713,6 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_MASK 0xF0000u #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_SHIFT 16 #define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_MASK) -#define XTALOSC_RCOSC_CONFIG0_CLR_RSVD0_MASK 0xF00000u -#define XTALOSC_RCOSC_CONFIG0_CLR_RSVD0_SHIFT 20 -#define XTALOSC_RCOSC_CONFIG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK 0xFF000000u #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT 24 #define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) @@ -95929,9 +43734,6 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_MASK 0xF0000u #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_SHIFT 16 #define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_MASK) -#define XTALOSC_RCOSC_CONFIG0_TOG_RSVD0_MASK 0xF00000u -#define XTALOSC_RCOSC_CONFIG0_TOG_RSVD0_SHIFT 20 -#define XTALOSC_RCOSC_CONFIG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK 0xFF000000u #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT 24 #define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) @@ -95939,9 +43741,6 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_MASK 0xFFFu #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_MASK) -#define XTALOSC_RCOSC_CONFIG1_RSVD0_MASK 0xFF000u -#define XTALOSC_RCOSC_CONFIG1_RSVD0_SHIFT 12 -#define XTALOSC_RCOSC_CONFIG1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG1_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_MASK 0xFFF00000u #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 #define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_MASK) @@ -95949,9 +43748,6 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_MASK 0xFFFu #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT 0 #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_MASK) -#define XTALOSC_RCOSC_CONFIG1_SET_RSVD0_MASK 0xFF000u -#define XTALOSC_RCOSC_CONFIG1_SET_RSVD0_SHIFT 12 -#define XTALOSC_RCOSC_CONFIG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_SET_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG1_SET_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_MASK 0xFFF00000u #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT 20 #define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_MASK) @@ -95959,9 +43755,6 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_MASK 0xFFFu #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT 0 #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) -#define XTALOSC_RCOSC_CONFIG1_CLR_RSVD0_MASK 0xFF000u -#define XTALOSC_RCOSC_CONFIG1_CLR_RSVD0_SHIFT 12 -#define XTALOSC_RCOSC_CONFIG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_CLR_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG1_CLR_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_MASK 0xFFF00000u #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT 20 #define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) @@ -95969,9 +43762,6 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_MASK 0xFFFu #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT 0 #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) -#define XTALOSC_RCOSC_CONFIG1_TOG_RSVD0_MASK 0xFF000u -#define XTALOSC_RCOSC_CONFIG1_TOG_RSVD0_SHIFT 12 -#define XTALOSC_RCOSC_CONFIG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_TOG_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG1_TOG_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_MASK 0xFFF00000u #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT 20 #define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) @@ -95979,107 +43769,69 @@ typedef struct { #define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_MASK 0xFFFu #define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 #define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_MASK) -#define XTALOSC_RCOSC_CONFIG2_RSVD0_MASK 0xF000u -#define XTALOSC_RCOSC_CONFIG2_RSVD0_SHIFT 12 -#define XTALOSC_RCOSC_CONFIG2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG2_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG2_ENABLE_1M_MASK 0x10000u #define XTALOSC_RCOSC_CONFIG2_ENABLE_1M_SHIFT 16 #define XTALOSC_RCOSC_CONFIG2_MUX_1M_MASK 0x20000u #define XTALOSC_RCOSC_CONFIG2_MUX_1M_SHIFT 17 -#define XTALOSC_RCOSC_CONFIG2_RSVD1_MASK 0x7FFC0000u -#define XTALOSC_RCOSC_CONFIG2_RSVD1_SHIFT 18 -#define XTALOSC_RCOSC_CONFIG2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_RSVD1_SHIFT))&XTALOSC_RCOSC_CONFIG2_RSVD1_MASK) #define XTALOSC_RCOSC_CONFIG2_CLK_1M_ERR_FL_MASK 0x80000000u #define XTALOSC_RCOSC_CONFIG2_CLK_1M_ERR_FL_SHIFT 31 /* RCOSC_CONFIG2_SET Bit Fields */ #define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_MASK 0xFFFu #define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT 0 #define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_MASK) -#define XTALOSC_RCOSC_CONFIG2_SET_RSVD0_MASK 0xF000u -#define XTALOSC_RCOSC_CONFIG2_SET_RSVD0_SHIFT 12 -#define XTALOSC_RCOSC_CONFIG2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_SET_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG2_SET_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG2_SET_ENABLE_1M_MASK 0x10000u #define XTALOSC_RCOSC_CONFIG2_SET_ENABLE_1M_SHIFT 16 #define XTALOSC_RCOSC_CONFIG2_SET_MUX_1M_MASK 0x20000u #define XTALOSC_RCOSC_CONFIG2_SET_MUX_1M_SHIFT 17 -#define XTALOSC_RCOSC_CONFIG2_SET_RSVD1_MASK 0x7FFC0000u -#define XTALOSC_RCOSC_CONFIG2_SET_RSVD1_SHIFT 18 -#define XTALOSC_RCOSC_CONFIG2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_SET_RSVD1_SHIFT))&XTALOSC_RCOSC_CONFIG2_SET_RSVD1_MASK) #define XTALOSC_RCOSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK 0x80000000u #define XTALOSC_RCOSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT 31 /* RCOSC_CONFIG2_CLR Bit Fields */ #define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_MASK 0xFFFu #define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT 0 #define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) -#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD0_MASK 0xF000u -#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD0_SHIFT 12 -#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_CLR_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG2_CLR_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG2_CLR_ENABLE_1M_MASK 0x10000u #define XTALOSC_RCOSC_CONFIG2_CLR_ENABLE_1M_SHIFT 16 #define XTALOSC_RCOSC_CONFIG2_CLR_MUX_1M_MASK 0x20000u #define XTALOSC_RCOSC_CONFIG2_CLR_MUX_1M_SHIFT 17 -#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD1_MASK 0x7FFC0000u -#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD1_SHIFT 18 -#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_CLR_RSVD1_SHIFT))&XTALOSC_RCOSC_CONFIG2_CLR_RSVD1_MASK) #define XTALOSC_RCOSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK 0x80000000u #define XTALOSC_RCOSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT 31 /* RCOSC_CONFIG2_TOG Bit Fields */ #define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_MASK 0xFFFu #define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT 0 #define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) -#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD0_MASK 0xF000u -#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD0_SHIFT 12 -#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_TOG_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG2_TOG_RSVD0_MASK) #define XTALOSC_RCOSC_CONFIG2_TOG_ENABLE_1M_MASK 0x10000u #define XTALOSC_RCOSC_CONFIG2_TOG_ENABLE_1M_SHIFT 16 #define XTALOSC_RCOSC_CONFIG2_TOG_MUX_1M_MASK 0x20000u #define XTALOSC_RCOSC_CONFIG2_TOG_MUX_1M_SHIFT 17 -#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD1_MASK 0x7FFC0000u -#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD1_SHIFT 18 -#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_TOG_RSVD1_SHIFT))&XTALOSC_RCOSC_CONFIG2_TOG_RSVD1_MASK) #define XTALOSC_RCOSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK 0x80000000u #define XTALOSC_RCOSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT 31 /* OSC_32K Bit Fields */ #define XTALOSC_OSC_32K_RTC_XTAL_SOURCE_MASK 0x1u #define XTALOSC_OSC_32K_RTC_XTAL_SOURCE_SHIFT 0 -#define XTALOSC_OSC_32K_RSVD0_MASK 0xFFFFFFFEu -#define XTALOSC_OSC_32K_RSVD0_SHIFT 1 -#define XTALOSC_OSC_32K_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_OSC_32K_RSVD0_SHIFT))&XTALOSC_OSC_32K_RSVD0_MASK) /* OSC_32K_SET Bit Fields */ #define XTALOSC_OSC_32K_SET_RTC_XTAL_SOURCE_MASK 0x1u #define XTALOSC_OSC_32K_SET_RTC_XTAL_SOURCE_SHIFT 0 -#define XTALOSC_OSC_32K_SET_RSVD0_MASK 0xFFFFFFFEu -#define XTALOSC_OSC_32K_SET_RSVD0_SHIFT 1 -#define XTALOSC_OSC_32K_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_OSC_32K_SET_RSVD0_SHIFT))&XTALOSC_OSC_32K_SET_RSVD0_MASK) /* OSC_32K_CLR Bit Fields */ #define XTALOSC_OSC_32K_CLR_RTC_XTAL_SOURCE_MASK 0x1u #define XTALOSC_OSC_32K_CLR_RTC_XTAL_SOURCE_SHIFT 0 -#define XTALOSC_OSC_32K_CLR_RSVD0_MASK 0xFFFFFFFEu -#define XTALOSC_OSC_32K_CLR_RSVD0_SHIFT 1 -#define XTALOSC_OSC_32K_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_OSC_32K_CLR_RSVD0_SHIFT))&XTALOSC_OSC_32K_CLR_RSVD0_MASK) /* OSC_32K_TOG Bit Fields */ #define XTALOSC_OSC_32K_TOG_RTC_XTAL_SOURCE_MASK 0x1u #define XTALOSC_OSC_32K_TOG_RTC_XTAL_SOURCE_SHIFT 0 -#define XTALOSC_OSC_32K_TOG_RSVD0_MASK 0xFFFFFFFEu -#define XTALOSC_OSC_32K_TOG_RSVD0_SHIFT 1 -#define XTALOSC_OSC_32K_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_OSC_32K_TOG_RSVD0_SHIFT))&XTALOSC_OSC_32K_TOG_RSVD0_MASK) /*! * @} */ /* end of group XTALOSC_Register_Masks */ - /* XTALOSC - Peripheral instance base addresses */ /** Peripheral XTALOSC base address */ #define XTALOSC_BASE (0x30360000u) /** Peripheral XTALOSC base pointer */ #define XTALOSC ((XTALOSC_Type *)XTALOSC_BASE) #define XTALOSC_BASE_PTR (XTALOSC) -/** Array initializer of XTALOSC peripheral base adresses */ +/** Array initializer of XTALOSC peripheral base addresses */ #define XTALOSC_BASE_ADDRS { XTALOSC_BASE } /** Array initializer of XTALOSC peripheral base pointers */ #define XTALOSC_BASE_PTRS { XTALOSC } - /* ---------------------------------------------------------------------------- -- XTALOSC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -96112,7 +43864,6 @@ typedef struct { #define XTALOSC_OSC_32K_SET XTALOSC_OSC_32K_SET_REG(XTALOSC_BASE_PTR) #define XTALOSC_OSC_32K_CLR XTALOSC_OSC_32K_CLR_REG(XTALOSC_BASE_PTR) #define XTALOSC_OSC_32K_TOG XTALOSC_OSC_32K_TOG_REG(XTALOSC_BASE_PTR) - /*! * @} */ /* end of group XTALOSC_Register_Accessor_Macros */ @@ -96122,7 +43873,6 @@ typedef struct { * @} */ /* end of group XTALOSC_Peripheral */ - /* ---------------------------------------------------------------------------- -- uSDHC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -96170,7 +43920,6 @@ typedef struct { __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ } uSDHC_Type, *uSDHC_MemMapPtr; - /* ---------------------------------------------------------------------------- -- uSDHC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -96217,8 +43966,6 @@ typedef struct { /*! * @} */ /* end of group uSDHC_Register_Accessor_Macros */ - - /* ---------------------------------------------------------------------------- -- uSDHC Register Masks ---------------------------------------------------------------------------- */ @@ -96833,7 +44580,6 @@ typedef struct { * @} */ /* end of group uSDHC_Register_Masks */ - /* uSDHC - Peripheral instance base addresses */ /** Peripheral uSDHC1 base address */ #define uSDHC1_BASE (0x30B40000u) @@ -96850,11 +44596,12 @@ typedef struct { /** Peripheral uSDHC3 base pointer */ #define uSDHC3 ((uSDHC_Type *)uSDHC3_BASE) #define uSDHC3_BASE_PTR (uSDHC3) -/** Array initializer of uSDHC peripheral base adresses */ +/** Array initializer of uSDHC peripheral base addresses */ #define uSDHC_BASE_ADDRS { uSDHC1_BASE, uSDHC2_BASE, uSDHC3_BASE } /** Array initializer of uSDHC peripheral base pointers */ #define uSDHC_BASE_PTRS { uSDHC1, uSDHC2, uSDHC3 } - +/** Interrupt vectors for the uSDHC peripheral type */ +#define uSDHC_IRQS { uSDHC1_IRQn, uSDHC2_IRQn, uSDHC3_IRQn } /* ---------------------------------------------------------------------------- -- uSDHC - Register accessor macros ---------------------------------------------------------------------------- */ @@ -96962,7 +44709,6 @@ typedef struct { #define uSDHC3_MMC_BOOT uSDHC_MMC_BOOT_REG(uSDHC3_BASE_PTR) #define uSDHC3_VEND_SPEC2 uSDHC_VEND_SPEC2_REG(uSDHC3_BASE_PTR) #define uSDHC3_TUNING_CTRL uSDHC_TUNING_CTRL_REG(uSDHC3_BASE_PTR) - /*! * @} */ /* end of group uSDHC_Register_Accessor_Macros */ @@ -96972,9 +44718,6 @@ typedef struct { * @} */ /* end of group uSDHC_Peripheral */ - - - /* ** End of section using anonymous unions */ @@ -97010,13 +44753,13 @@ typedef struct { */ /* end of group Backward_Compatibility_Symbols */ -#else /* #if !defined(MCU_iMX7D) */ +#else /* #if !defined(MCU_MCIMX7D) */ /* There is already included the same memory map. Check if it is compatible (has the same major version) */ #if (MCU_MEM_MAP_VERSION != 0x0100u) #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) #warning There are included two not compatible versions of memory maps. Please check possible differences. #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ -#endif /* #if !defined(MCU_iMX7D) */ +#endif /* #if !defined(MCU_MCIMX7D) */ -/* iMX7D.h, eof. */ +/* MCIMX7D_M4.h, eof. */ diff --git a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIA.scf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIA.scf deleted file mode 100755 index a94eafb..0000000 --- a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIA.scf +++ /dev/null @@ -1,36 +0,0 @@ -#! armcc -E --cpu Cortex-M4 - -#define m_text_start 0x60000000 -#define m_text_size 0x7FF0 - -#define m_data_start 0x20000000 -#define m_data_size 0x7FF0 - -#define HEAP_SIZE 0x200 -#define STACK_SIZE 0x400 -#define MY_ALIGN(address, alignment) ((address + (alignment-1)) AND ~(alignment-1)) - - -LR_m_text m_text_start m_text_size -{ - ER_m_text m_text_start m_text_size { - * (RESET,+FIRST) - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start { ; RW data - .ANY (+RW ) - } - ZI_m_data +0 { ; ZI data - .ANY (+ZI ) - } - - ARM_LIB_HEAP (m_data_start+m_data_size-HEAP_SIZE-STACK_SIZE) EMPTY HEAP_SIZE - { ; Heap region growing up - } - ARM_LIB_STACK (m_data_start+m_data_size) EMPTY -STACK_SIZE - { ; Stack region growing down - } - -} diff --git a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIB.scf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIB.scf deleted file mode 100755 index b7857af..0000000 --- a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIB.scf +++ /dev/null @@ -1,36 +0,0 @@ -#! armcc -E --cpu Cortex-M4 - -#define m_text_start 0x68000000 -#define m_text_size 0x7FF0 - -#define m_data_start 0x20000000 -#define m_data_size 0x7FF0 - -#define HEAP_SIZE 0x200 -#define STACK_SIZE 0x400 -#define MY_ALIGN(address, alignment) ((address + (alignment-1)) AND ~(alignment-1)) - - -LR_m_text m_text_start m_text_size -{ - ER_m_text m_text_start m_text_size { - * (RESET,+FIRST) - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start { ; RW data - .ANY (+RW ) - } - ZI_m_data +0 { ; ZI data - .ANY (+ZI ) - } - - ARM_LIB_HEAP (m_data_start+m_data_size-HEAP_SIZE-STACK_SIZE) EMPTY HEAP_SIZE - { ; Heap region growing up - } - ARM_LIB_STACK (m_data_start+m_data_size) EMPTY -STACK_SIZE - { ; Stack region growing down - } - -} diff --git a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_tcm.icf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_ddr.scf index 04d9c21..2e98852 100644 --- a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_tcm.icf +++ b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_ddr.scf @@ -1,3 +1,4 @@ +#! armcc -E /* ** ################################################################### ** Processors: MCIMX7D7DVK10SA @@ -5,12 +6,12 @@ ** MCIMX7D3DVK10SA ** MCIMX7D3EVM10SA ** -** Compiler: IAR ANSI C/C++ Compiler for ARM +** Compiler: ARM C/C++ Compiler ** Reference manual: IMX7DRM, Rev.A, February 2015 -** Version: rev. 1.0, 2015-05-19 +** Version: rev. 1.0, 2015-07-08 ** ** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM +** Linker file for the ARM C/C++ Compiler ** ** Copyright (c) 2015 Freescale Semiconductor, Inc. ** All rights reserved. @@ -46,48 +47,44 @@ ** ################################################################### */ -define symbol m_interrupts_start = 0x1FFF8000; -define symbol m_interrupts_end = 0x1FFF823F; +#define m_interrupts_start 0x9ff00000 +#define m_interrupts_size 0x00000240 -define symbol m_text_start = 0x1FFF8240; -define symbol m_text_end = 0x1FFFFFFF; +#define m_text_start 0x9ff00240 +#define m_text_size 0x00007DC0 -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x20007FFF; +#define m_data_start 0x20000000 +#define m_data_size 0x8000 /* Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define exported symbol __VECTOR_TABLE = m_interrupts_start; +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite, section .textrw }; -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP m_data_start+m_data_size-Heap_Size-Stack_Size EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} +LR_m_interrupts m_interrupts_start m_interrupts_size { + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } +} diff --git a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIA.icf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_ocram.scf index f2294ec..85ad735 100644 --- a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIA.icf +++ b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_ocram.scf @@ -1,93 +1,90 @@ -/*
-** ###################################################################
-** Processors: MCIMX7D7DVK10SA
-** MCIMX7D7DVM10SA
-** MCIMX7D3DVK10SA
-** MCIMX7D3EVM10SA
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMX7DRM, Rev.A, February 2015
-** Version: rev. 1.0, 2015-05-19
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright (c) 2015 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** ###################################################################
-*/
-
-define symbol m_interrupts_start = 0x60000000;
-define symbol m_interrupts_end = 0x6000023F;
-
-define symbol m_text_start = 0x60000240;
-define symbol m_text_end = 0x60007FFF;
-
-define symbol m_data_start = 0x20000000;
-define symbol m_data_end = 0x20007FFF;
-
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
-define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { readwrite };
-define block ZI { zi };
-
-initialize by copy { readwrite, section .textrw };
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-place in TEXT_region { readonly };
-place in DATA_region { block RW };
-place in DATA_region { block ZI };
-place in DATA_region { last block HEAP };
-place in CSTACK_region { block CSTACK };
+#! armcc -E +/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: ARM C/C++ Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-07-08 +** +** Abstract: +** Linker file for the ARM C/C++ Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x20210000 +#define m_interrupts_size 0x00000240 + +#define m_text_start 0x20210240 +#define m_text_size 0x00007DC0 + +#define m_data_start 0x20000000 +#define m_data_size 0x8000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP m_data_start+m_data_size-Heap_Size-Stack_Size EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} + +LR_m_interrupts m_interrupts_start m_interrupts_size { + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } +} diff --git a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIB.icf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_qspia.scf index cc0930e..ec2980f 100644 --- a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIB.icf +++ b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_qspia.scf @@ -1,93 +1,90 @@ -/*
-** ###################################################################
-** Processors: MCIMX7D7DVK10SA
-** MCIMX7D7DVM10SA
-** MCIMX7D3DVK10SA
-** MCIMX7D3EVM10SA
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: IMX7DRM, Rev.A, February 2015
-** Version: rev. 1.0, 2015-05-19
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright (c) 2015 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** ###################################################################
-*/
-
-define symbol m_interrupts_start = 0x68000000;
-define symbol m_interrupts_end = 0x6800023F;
-
-define symbol m_text_start = 0x68000240;
-define symbol m_text_end = 0x68007FFF;
-
-define symbol m_data_start = 0x20000000;
-define symbol m_data_end = 0x20007FFF;
-
-
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
-define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { readwrite };
-define block ZI { zi };
-
-initialize by copy { readwrite, section .textrw };
-do not initialize { section .noinit };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-place in TEXT_region { readonly };
-place in DATA_region { block RW };
-place in DATA_region { block ZI };
-place in DATA_region { last block HEAP };
-place in CSTACK_region { block CSTACK };
+#! armcc -E +/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: ARM C/C++ Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-07-08 +** +** Abstract: +** Linker file for the ARM C/C++ Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x60100000 +#define m_interrupts_size 0x00000240 + +#define m_text_start 0x60100240 +#define m_text_size 0x00007DC0 + +#define m_data_start 0x20000000 +#define m_data_size 0x8000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP m_data_start+m_data_size-Heap_Size-Stack_Size EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} + +LR_m_interrupts m_interrupts_start m_interrupts_size { + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } +} diff --git a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_qspib.scf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_qspib.scf new file mode 100644 index 0000000..638567e --- /dev/null +++ b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_qspib.scf @@ -0,0 +1,90 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: ARM C/C++ Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-07-08 +** +** Abstract: +** Linker file for the ARM C/C++ Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x68000000 +#define m_interrupts_size 0x00000240 + +#define m_text_start 0x68000240 +#define m_text_size 0x00007DC0 + +#define m_data_start 0x20000000 +#define m_data_size 0x8000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP m_data_start+m_data_size-Heap_Size-Stack_Size EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} + +LR_m_interrupts m_interrupts_start m_interrupts_size { + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } +} diff --git a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_tcm.scf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_tcm.scf index 95a4dda..d4cd94f 100755..100644 --- a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_tcm.scf +++ b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_tcm.scf @@ -1,36 +1,90 @@ -#! armcc -E --cpu Cortex-M4 +#! armcc -E +/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: ARM C/C++ Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-07-08 +** +** Abstract: +** Linker file for the ARM C/C++ Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ -#define m_text_start 0x1FFF8000 -#define m_text_size 0x7FF0 +#define m_interrupts_start 0x1FFF8000 +#define m_interrupts_size 0x00000240 -#define m_data_start 0x20000000 -#define m_data_size 0x7FF0 +#define m_text_start 0x1FFF8240 +#define m_text_size 0x00007DC0 -#define HEAP_SIZE 0x200 -#define STACK_SIZE 0x400 -#define MY_ALIGN(address, alignment) ((address + (alignment-1)) AND ~(alignment-1)) +#define m_data_start 0x20000000 +#define m_data_size 0x8000 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif -LR_m_text m_text_start m_text_size -{ - ER_m_text m_text_start m_text_size { - * (RESET,+FIRST) +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start m_text_size { ; load address = execution address * (InRoot$$Sections) .ANY (+RO) } - - RW_m_data m_data_start { ; RW data - .ANY (+RW ) - } - ZI_m_data +0 { ; ZI data - .ANY (+ZI ) + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) } - - ARM_LIB_HEAP (m_data_start+m_data_size-HEAP_SIZE-STACK_SIZE) EMPTY HEAP_SIZE - { ; Heap region growing up + ARM_LIB_HEAP m_data_start+m_data_size-Heap_Size-Stack_Size EMPTY Heap_Size { ; Heap region growing up } - ARM_LIB_STACK (m_data_start+m_data_size) EMPTY -STACK_SIZE - { ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down } +} +LR_m_interrupts m_interrupts_start m_interrupts_size { + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } } diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIA.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld index 5b5ec1a..84c0301 100644 --- a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIA.ld +++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld @@ -1,167 +1,222 @@ -/* Entry Point */
-ENTRY(Reset_Handler)
-
-STACK_SIZE = 0x400;
-HEAP_SIZE = 0x200;
-/* Specify the memory areas */
-MEMORY
-{
- m_text (RX) : ORIGIN = 0x60000000, LENGTH = 0x00007FFF
-
- m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007FFF
-
-}
-
-SECTIONS
-{
- .interrupts :
- {
- __VECTOR_TABLE = .;
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } > m_text
-
- __VECTOR_RAM = __VECTOR_TABLE;
- __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
-
-
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
- KEEP (*(.init))
- KEEP (*(.fini))
- . = ALIGN(4);
- } > m_text
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > m_text
-
- .ARM :
- {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } > m_text
-
- .ctors :
- {
- __CTOR_LIST__ = .;
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- from the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- __CTOR_END__ = .;
- } > m_text
-
- .dtors :
- {
- __DTOR_LIST__ = .;
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- __DTOR_END__ = .;
- } > m_text
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } > m_text
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } > m_text
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array*))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } > m_text
-
- __etext = .; /* define a global symbol at end of code */
- __DATA_ROM = .; /* Symbol is used by startup for data initialization */
-
- .data : AT(__DATA_ROM)
- {
- . = ALIGN(4);
- __DATA_RAM = .;
- __data_start__ = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
- KEEP(*(.jcr*))
- . = ALIGN(4);
- __data_end__ = .; /* define a global symbol at data end */
- } > m_data
-
- __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
-
- /* Uninitialized data section */
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
- __START_BSS = .;
- __bss_start__ = .;
- *(.bss)
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- __bss_end__ = .;
- __END_BSS = .;
- } > m_data
-
- .heap :
- {
- . = ALIGN(8);
- __end__ = .;
- PROVIDE(end = .);
- __HeapBase = .;
- . += HEAP_SIZE;
- __HeapLimit = .;
- } > m_data
- .stack :
- {
- . = ALIGN(8);
- . += STACK_SIZE;
- } > m_data
- /* Initializes stack on the end of block */
- __StackTop = ORIGIN(m_data) + LENGTH(m_data);
- __StackLimit = __StackTop - STACK_SIZE;
- PROVIDE(__stack = __StackTop);
- .ARM.attributes 0 : { *(.ARM.attributes) }
-
- ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
- }
+/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: GNU C Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-05-19 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x9ff00000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x9ff00240, LENGTH = 0x00007DC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +__FLASH_START = ORIGIN(m_interrupts); +__FLASH_END = ORIGIN(m_text) + LENGTH(m_text); + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ocram.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ocram.ld index 76988c4..5653095 100644 --- a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ocram.ld +++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ocram.ld @@ -1,30 +1,81 @@ +/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: GNU C Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-05-19 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + /* Entry Point */ ENTRY(Reset_Handler) -STACK_SIZE = 0x400; -HEAP_SIZE = 0x200; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + /* Specify the memory areas */ MEMORY { - m_text (RX) : ORIGIN = 0x00920000, LENGTH = 0x00020000 - - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007FFF + m_interrupts (RX) : ORIGIN = 0x20210000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x20210240, LENGTH = 0x00007DC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000 } +__FLASH_START = ORIGIN(m_interrupts); +__FLASH_END = ORIGIN(m_text) + LENGTH(m_text); + +/* Define output sections */ SECTIONS { + /* The startup code goes first into Flash */ .interrupts : { __VECTOR_TABLE = .; . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); - } > m_text - - __VECTOR_RAM = __VECTOR_TABLE; - __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; - + } > m_interrupts + /* The program code and other data goes into Flash */ .text : { . = ALIGN(4); @@ -126,6 +177,8 @@ SECTIONS } > m_data __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") /* Uninitialized data section */ .bss : @@ -151,16 +204,19 @@ SECTIONS . += HEAP_SIZE; __HeapLimit = .; } > m_data - .stack : + + .stack : { . = ALIGN(8); . += STACK_SIZE; } > m_data - /* Initializes stack on the end of block */ + + /* Initializes stack on the end of block */ __StackTop = ORIGIN(m_data) + LENGTH(m_data); __StackLimit = __StackTop - STACK_SIZE; PROVIDE(__stack = __StackTop); + .ARM.attributes 0 : { *(.ARM.attributes) } ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") - }
\ No newline at end of file +} diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIB.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_qspia.ld index 84dceb5..07c5da5 100644 --- a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIB.ld +++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_qspia.ld @@ -1,167 +1,222 @@ -/* Entry Point */
-ENTRY(Reset_Handler)
-
-STACK_SIZE = 0x400;
-HEAP_SIZE = 0x200;
-/* Specify the memory areas */
-MEMORY
-{
- m_text (RX) : ORIGIN = 0x68000000, LENGTH = 0x00007FFF
-
- m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007FFF
-
-}
-
-SECTIONS
-{
- .interrupts :
- {
- __VECTOR_TABLE = .;
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } > m_text
-
- __VECTOR_RAM = __VECTOR_TABLE;
- __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
-
-
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
- KEEP (*(.init))
- KEEP (*(.fini))
- . = ALIGN(4);
- } > m_text
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > m_text
-
- .ARM :
- {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } > m_text
-
- .ctors :
- {
- __CTOR_LIST__ = .;
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- from the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- __CTOR_END__ = .;
- } > m_text
-
- .dtors :
- {
- __DTOR_LIST__ = .;
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- __DTOR_END__ = .;
- } > m_text
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } > m_text
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } > m_text
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array*))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } > m_text
-
- __etext = .; /* define a global symbol at end of code */
- __DATA_ROM = .; /* Symbol is used by startup for data initialization */
-
- .data : AT(__DATA_ROM)
- {
- . = ALIGN(4);
- __DATA_RAM = .;
- __data_start__ = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
- KEEP(*(.jcr*))
- . = ALIGN(4);
- __data_end__ = .; /* define a global symbol at data end */
- } > m_data
-
- __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
-
- /* Uninitialized data section */
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
- __START_BSS = .;
- __bss_start__ = .;
- *(.bss)
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- __bss_end__ = .;
- __END_BSS = .;
- } > m_data
-
- .heap :
- {
- . = ALIGN(8);
- __end__ = .;
- PROVIDE(end = .);
- __HeapBase = .;
- . += HEAP_SIZE;
- __HeapLimit = .;
- } > m_data
- .stack :
- {
- . = ALIGN(8);
- . += STACK_SIZE;
- } > m_data
- /* Initializes stack on the end of block */
- __StackTop = ORIGIN(m_data) + LENGTH(m_data);
- __StackLimit = __StackTop - STACK_SIZE;
- PROVIDE(__stack = __StackTop);
- .ARM.attributes 0 : { *(.ARM.attributes) }
-
- ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
- }
+/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: GNU C Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-05-19 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x60100000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x60100240, LENGTH = 0x00007DC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +__FLASH_START = ORIGIN(m_interrupts); +__FLASH_END = ORIGIN(m_text) + LENGTH(m_text); + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_qspib.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_qspib.ld new file mode 100644 index 0000000..c3f8bcd --- /dev/null +++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_qspib.ld @@ -0,0 +1,222 @@ +/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: GNU C Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-05-19 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x68000000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x68000240, LENGTH = 0x00007DC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +__FLASH_START = ORIGIN(m_interrupts); +__FLASH_END = ORIGIN(m_text) + LENGTH(m_text); + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into Flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into Flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_tcm.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_tcm.ld index 5fd3435..b296a42 100644 --- a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_tcm.ld +++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_tcm.ld @@ -1,31 +1,78 @@ +/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: GNU C Compiler +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-05-19 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + /* Entry Point */ ENTRY(Reset_Handler) -STACK_SIZE = 0x400; -HEAP_SIZE = 0x200; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + /* Specify the memory areas */ MEMORY { - m_text (RX) : ORIGIN = 0x1FFF8000, LENGTH = 0x00007FFF - - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007FFF - + m_interrupts (RX) : ORIGIN = 0x1FFF8000, LENGTH = 0x00000240 + m_text (RX) : ORIGIN = 0x1FFF8240, LENGTH = 0x00007DC0 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000 } +/* Define output sections */ SECTIONS { + /* The startup code goes first into TCML */ .interrupts : { __VECTOR_TABLE = .; . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); - } > m_text - - __VECTOR_RAM = __VECTOR_TABLE; - __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; - + } > m_interrupts + /* The program code and other data goes into TCML */ .text : { . = ALIGN(4); @@ -127,6 +174,8 @@ SECTIONS } > m_data __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") /* Uninitialized data section */ .bss : @@ -152,16 +201,19 @@ SECTIONS . += HEAP_SIZE; __HeapLimit = .; } > m_data - .stack : + + .stack : { . = ALIGN(8); . += STACK_SIZE; } > m_data - /* Initializes stack on the end of block */ + + /* Initializes stack on the end of block */ __StackTop = ORIGIN(m_data) + LENGTH(m_data); __StackLimit = __StackTop - STACK_SIZE; PROVIDE(__stack = __StackTop); + .ARM.attributes 0 : { *(.ARM.attributes) } ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") - }
\ No newline at end of file +} diff --git a/platform/devices/MCIMX7D/startup/arm/startup_MCIMX7D_M4.s b/platform/devices/MCIMX7D/startup/arm/startup_MCIMX7D_M4.s index c367752..c0bb23e 100644 --- a/platform/devices/MCIMX7D/startup/arm/startup_MCIMX7D_M4.s +++ b/platform/devices/MCIMX7D/startup/arm/startup_MCIMX7D_M4.s @@ -1,10 +1,10 @@ ; * --------------------------------------------------------------------------------------- ; * @file: startup_MCIMX7D_M4.s ; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * IMX7D_M4 -; * @version: 0.1 +; * MCIMX7D_M4 +; * @version: 1.0 ; * @date: 2015-5-27 -; * @build: b54573 +; * @build: b150527 ; * --------------------------------------------------------------------------------------- ; * ; * Copyright (c) 2015 , Freescale Semiconductor, Inc. @@ -51,7 +51,8 @@ EXPORT __Vectors_End EXPORT __Vectors_Size IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ;NMI Handler DCD HardFault_Handler ;Hard Fault Handler @@ -69,142 +70,141 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD SysTick_Handler ;SysTick Handler ;External Interrupts - DCD DefaultISR ;Reserved Interrupt 16 - DCD DefaultISR ;Reserved Interrupt 17 - DCD DefaultISR ;Reserved Interrupt 18 - DCD DefaultISR ;Reserved Interrupt 19 - DCD DefaultISR ;Reserved Interrupt 20 - DCD DefaultISR ;Reserved Interrupt 21 - DCD DefaultISR ;Reserved Interrupt 22 - DCD DefaultISR ;Reserved Interrupt 23 - DCD DefaultISR ;Reserved Interrupt 24 - DCD DefaultISR ;Reserved Interrupt 25 - DCD WDOG3_Handler ;WDOG3 Handler - DCD SEMA4_Handler ;SEMA4_Handler - DCD DefaultISR ;Reserved Interrupt 28 - DCD DefaultISR ;Reserved Interrupt 29 - DCD DefaultISR ;Reserved Interrupt 30 - DCD DefaultISR ;Reserved Interrupt 31 - DCD UART6_Handler ;UART6 Handler - DCD DefaultISR ;Reserved Interrupt 33 - DCD DefaultISR ;Reserved Interrupt 34 - DCD DefaultISR ;Reserved Interrupt 35 - DCD DefaultISR ;Reserved Interrupt 36 - DCD DefaultISR ;Reserved Interrupt 37 - DCD DefaultISR ;Reserved Interrupt 38 - DCD DefaultISR ;Reserved Interrupt 39 - DCD DefaultISR ;Reserved Interrupt 40 - DCD DefaultISR ;Reserved Interrupt 41 - DCD UART1_Handler ;UART1 Handler - DCD UART2_Handler ;UART2 Handler - DCD UART3_Handler ;UART3 Handler - DCD UART4_Handler ;UART4 Handler - DCD UART5_Handler ;UART5 Handler - DCD eCSPI1_Handler ;eCSPI1 Handler - DCD eCSPI2_Handler ;eCSPI2 Handler - DCD eCSPI3_Handler ;eCSPI3 Handler - DCD eCSPI4_Handler ;eCSPI4 Handler - DCD I2C1_Handler ;I2C1 Handler - DCD I2C2_Handler ;I2C2 Handler - DCD I2C3_Handler ;I2C3 Handler - DCD I2C4_Handler ;I2C4 Handler - DCD DefaultISR ;Reserved Interrupt 55 - DCD DefaultISR ;Reserved Interrupt 56 - DCD DefaultISR ;Reserved Interrupt 57 - DCD DefaultISR ;Reserved Interrupt 58 - DCD DefaultISR ;Reserved Interrupt 59 - DCD DefaultISR ;Reserved Interrupt 60 - DCD DefaultISR ;Reserved Interrupt 61 - DCD DefaultISR ;Reserved Interrupt 62 - DCD DefaultISR ;Reserved Interrupt 63 - DCD DefaultISR ;Reserved Interrupt 64 - DCD DefaultISR ;Reserved Interrupt 65 - DCD DefaultISR ;Reserved Interrupt 66 - DCD DefaultISR ;Reserved Interrupt 67 - DCD GPT4_Handler ;GPT4 handler - DCD GPT3_Handler ;GPT3 handler - DCD GPT2_Handler ;GPT2 handler - DCD GPT1_Handler ;GPT1 handler - DCD GPIO1_INT7_Handler ;Active HIGH Interrupt from INT7 from GPIO - DCD GPIO1_INT6_Handler ;Active HIGH Interrupt from INT6 from GPIO - DCD GPIO1_INT5_Handler ;Active HIGH Interrupt from INT5 from GPIO - DCD GPIO1_INT4_Handler ;Active HIGH Interrupt from INT4 from GPIO - DCD GPIO1_INT3_Handler ;Active HIGH Interrupt from INT3 from GPIO - DCD GPIO1_INT2_Handler ;Active HIGH Interrupt from INT2 from GPIO - DCD GPIO1_INT1_Handler ;Active HIGH Interrupt from INT1 from GPIO - DCD GPIO1_INT0_Handler ;Active HIGH Interrupt from INT0 from GPIO - DCD GPIO1_INT15_0_Handler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 - DCD GPIO1_INT31_16_Handler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 - DCD GPIO2_INT15_0_Handler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 - DCD GPIO2_INT31_16_Handler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 - DCD GPIO3_INT15_0_Handler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 - DCD GPIO3_INT31_16_Handler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 - DCD GPIO4_INT15_0_Handler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 - DCD GPIO4_INT31_16_Handler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 - DCD GPIO5_INT15_0_Handler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 - DCD GPIO5_INT31_16_Handler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 - DCD GPIO6_INT15_0_Handler ;Combined interrupt indication for GPIO6 signal 0 throughout 15 - DCD GPIO6_INT31_16_Handler ;Combined interrupt indication for GPIO6 signal 16 throughout 31 - DCD GPIO7_INT15_0_Handler ;Combined interrupt indication for GPIO7 signal 0 throughout 15 - DCD GPIO7_INT31_16_Handler ;Combined interrupt indication for GPIO7 signal 16 throughout 31 - DCD DefaultISR ;Reserved Interrupt 94 - DCD DefaultISR ;Reserved Interrupt 95 - DCD DefaultISR ;Reserved Interrupt 96 - DCD DefaultISR ;Reserved Interrupt 97 - DCD DefaultISR ;Reserved Interrupt 98 - DCD DefaultISR ;Reserved Interrupt 99 - DCD DefaultISR ;Reserved Interrupt 100 - DCD DefaultISR ;Reserved Interrupt 101 - DCD DefaultISR ;Reserved Interrupt 102 - DCD DefaultISR ;Reserved Interrupt 103 - DCD DefaultISR ;Reserved Interrupt 104 - DCD DefaultISR ;Reserved Interrupt 105 - DCD DefaultISR ;Reserved Interrupt 106 - DCD DefaultISR ;Reserved Interrupt 107 - DCD DefaultISR ;Reserved Interrupt 108 - DCD DefaultISR ;Reserved Interrupt 109 - DCD DefaultISR ;Reserved Interrupt 110 - DCD DefaultISR ;Reserved Interrupt 111 - DCD DefaultISR ;Reserved Interrupt 112 - DCD MU_Handler ;MU_Handler - DCD ADC1_Handler ;ADC1 Handler - DCD ADC2_Handler ;ADC2 Handler - DCD DefaultISR ;Reserved Interrupt 116 - DCD DefaultISR ;Reserved Interrupt 117 - DCD DefaultISR ;Reserved Interrupt 118 - DCD DefaultISR ;Reserved Interrupt 119 - DCD DefaultISR ;Reserved Interrupt 120 - DCD DefaultISR ;Reserved Interrupt 121 - DCD DefaultISR ;Reserved Interrupt 122 - DCD DefaultISR ;Reserved Interrupt 123 - DCD DefaultISR ;Reserved Interrupt 124 - DCD DefaultISR ;Reserved Interrupt 125 - DCD FLEXCAN1_Handler ;FLEXCAN1 Handler - DCD FLEXCAN2_Handler ;FLEXCAN2 Handler - DCD DefaultISR ;Reserved Interrupt 128 - DCD DefaultISR ;Reserved Interrupt 129 - DCD DefaultISR ;Reserved Interrupt 130 - DCD DefaultISR ;Reserved Interrupt 131 - DCD DefaultISR ;Reserved Interrupt 132 - DCD DefaultISR ;Reserved Interrupt 133 - DCD DefaultISR ;Reserved Interrupt 134 - DCD DefaultISR ;Reserved Interrupt 135 - DCD DefaultISR ;Reserved Interrupt 136 - DCD DefaultISR ;Reserved Interrupt 137 - DCD DefaultISR ;Reserved Interrupt 138 - DCD DefaultISR ;Reserved Interrupt 139 - DCD DefaultISR ;Reserved Interrupt 140 - DCD DefaultISR ;Reserved Interrupt 141 - DCD UART7_Handler ;UART7 Handler - DCD DefaultISR ;Reserved Interrupt 143 - + DCD GPR_Handler ;GPR Interrupt + DCD DAP_Handler ;DAP Interrupt + DCD SDMA_Handler ;SDMA Interrupt + DCD DBGMON_Handler ;DBGMON Interrupt + DCD SNVS_Handler ;SNVS Interrupt + DCD LCDIF_Handler ;LCDIF Interrupt + DCD SIM2_Handler ;SIM2 Interrupt + DCD CSI_Handler ;CSI Interrupt + DCD PXP1_Handler ;PXP1 Interrupt + DCD Reserved9_Handler ;Reserved interrupt 9 + DCD WDOG3_Handler ;WDOG3 Interrupt + DCD SEMA4_HS_M4_Handler ;SEMA4_HS_M4 Interrupt + DCD APBHDMA_Handler ;APBHDMA Interrupt + DCD EIM_Handler ;EIM Interrupt + DCD BCH_Handler ;BCH Interrupt + DCD GPMI_Handler ;GPMI Interrupt + DCD UART6_Handler ;UART6 Interrupt + DCD FTM1_Handler ;FTM1 Interrupt + DCD FTM2_Handler ;FTM2 Interrupt + DCD SNVS_CONSOLIDATED_Handler ;SNVS_CONSOLIDATED Interrupt + DCD SNVS_SECURITY_Handler ;SNVS_SECURITY Interrupt + DCD CSU_Handler ;CSU Interrupt + DCD uSDHC1_Handler ;uSDHC1 Interrupt + DCD uSDHC2_Handler ;uSDHC2 Interrupt + DCD uSDHC3_Handler ;uSDHC3 Interrupt + DCD MIPI_CSI_Handler ;MIPI_CSI Interrupt + DCD UART1_Handler ;UART1 Interrupt + DCD UART2_Handler ;UART2 Interrupt + DCD UART3_Handler ;UART3 Interrupt + DCD UART4_Handler ;UART4 Interrupt + DCD UART5_Handler ;UART5 Interrupt + DCD eCSPI1_Handler ;eCSPI1 Interrupt + DCD eCSPI2_Handler ;eCSPI2 Interrupt + DCD eCSPI3_Handler ;eCSPI3 Interrupt + DCD eCSPI4_Handler ;eCSPI4 Interrupt + DCD I2C1_Handler ;I2C1 Interrupt + DCD I2C2_Handler ;I2C2 Interrupt + DCD I2C3_Handler ;I2C3 Interrupt + DCD I2C4_Handler ;I2C4 Interrupt + DCD RDC_Handler ;RDC Interrupt + DCD USB_OH3_OTG2_1_Handler ;USB_OH3_OTG2_1 Interrupt + DCD MIPI_DSI_Handler ;MIPI_DSI Interrupt + DCD USB_OH3_OTG2_2_Handler ;USB_OH3_OTG2_2 Interrupt + DCD USB_OH2_OTG_Handler ;USB_OH2_OTG Interrupt + DCD USB_OTG1_Handler ;USB_OTG1 Interrupt + DCD USB_OTG2_Handler ;USB_OTG2 Interrupt + DCD PXP2_Handler ;PXP2 Interrupt + DCD SCTR1_Handler ;SCTR1 Interrupt + DCD SCTR2_Handler ;SCTR2 Interrupt + DCD Analog_TempSensor_Handler ;Analog_TempSensor Interrupt + DCD SAI3_Handler ;SAI3 Interrupt + DCD Analog_brown_out_Handler ;Analog_brown_out Interrupt + DCD GPT4_Handler ;GPT4 Interrupt + DCD GPT3_Handler ;GPT3 Interrupt + DCD GPT2_Handler ;GPT2 Interrupt + DCD GPT1_Handler ;GPT1 Interrupt + DCD GPIO1_INT7_Handler ;GPIO1_INT7 Interrupt + DCD GPIO1_INT6_Handler ;GPIO1_INT6 Interrupt + DCD GPIO1_INT5_Handler ;GPIO1_INT5 Interrupt + DCD GPIO1_INT4_Handler ;GPIO1_INT4 Interrupt + DCD GPIO1_INT3_Handler ;GPIO1_INT3 Interrupt + DCD GPIO1_INT2_Handler ;GPIO1_INT2 Interrupt + DCD GPIO1_INT1_Handler ;GPIO1_INT1 Interrupt + DCD GPIO1_INT0_Handler ;GPIO1_INT0 Interrupt + DCD GPIO1_INT15_0_Handler ;GPIO1_INT15_0 Interrupt + DCD GPIO1_INT31_16_Handler ;GPIO1_INT31_16 Interrupt + DCD GPIO2_INT15_0_Handler ;GPIO2_INT15_0 Interrupt + DCD GPIO2_INT31_16_Handler ;GPIO2_INT31_16 Interrupt + DCD GPIO3_INT15_0_Handler ;GPIO3_INT15_0 Interrupt + DCD GPIO3_INT31_16_Handler ;GPIO3_INT31_16 Interrupt + DCD GPIO4_INT15_0_Handler ;GPIO4_INT15_0 Interrupt + DCD GPIO4_INT31_16_Handler ;GPIO4_INT31_16 Interrupt + DCD GPIO5_INT15_0_Handler ;GPIO5_INT15_0 Interrupt + DCD GPIO5_INT31_16_Handler ;GPIO5_INT31_16 Interrupt + DCD GPIO6_INT15_0_Handler ;GPIO6_INT15_0 Interrupt + DCD GPIO6_INT31_16_Handler ;GPIO6_INT31_16 Interrupt + DCD GPIO7_INT15_0_Handler ;GPIO7_INT15_0 Interrupt + DCD GPIO7_INT31_16_Handler ;GPIO7_INT31_16 Interrupt + DCD WDOG1_Handler ;WDOG1 Interrupt + DCD WDOG2_Handler ;WDOG2 Interrupt + DCD KPP_Handler ;KPP Interrupt + DCD PWM1_Handler ;PWM1 Interrupt + DCD PWM2_Handler ;PWM2 Interrupt + DCD PWM3_Handler ;PWM3 Interrupt + DCD PWM4_Handler ;PWM4 Interrupt + DCD CCM1_Handler ;CCM1 Interrupt + DCD CCM2_Handler ;CCM2 Interrupt + DCD GPC_Handler ;GPC Interrupt + DCD MU_A7_Handler ;MU_A7 Interrupt + DCD SRC_Handler ;SRC Interrupt + DCD SIM1_Handler ;SIM1 Interrupt + DCD RTIC_Handler ;RTIC Interrupt + DCD CPU_Handler ;CPU Interrupt + DCD CPU_CTI_Handler ;CPU_CTI Interrupt + DCD CCM_SRC_GPC_Handler ;CCM_SRC_GPC Interrupt + DCD SAI1_Handler ;SAI1 Interrupt + DCD SAI2_Handler ;SAI2 Interrupt + DCD MU_M4_Handler ;MU_M4 Interrupt + DCD ADC1_Handler ;ADC1 Interrupt + DCD ADC2_Handler ;ADC2 Interrupt + DCD ENET2_MAC0_TRANS1_Handler ;ENET2_MAC0_TRANS1 Interrupt + DCD ENET2_MAC0_TRANS2_Handler ;ENET2_MAC0_TRANS2 Interrupt + DCD ENET2_MAC0_IRQ_Handler ;ENET2_MAC0_IRQ Interrupt + DCD ENET2_1588_TIMER_IRQ_Handler ;ENET2_1588_TIMER_IRQ Interrupt + DCD TPR_Handler ;TPR Interrupt + DCD CAAM_QUEUE_Handler ;CAAM_QUEUE Interrupt + DCD CAAM_ERROR_Handler ;CAAM_ERROR Interrupt + DCD QSPI_Handler ;QSPI Interrupt + DCD TZASC1_Handler ;TZASC1 Interrupt + DCD WDOG4_Handler ;WDOG4 Interrupt + DCD FLEXCAN1_Handler ;FLEXCAN1 Interrupt + DCD FLEXCAN2_Handler ;FLEXCAN2 Interrupt + DCD PERFMON1_Handler ;PERFMON1 Interrupt + DCD PERFMON2_Handler ;PERFMON2 Interrupt + DCD CAAM_WRAPPER1_Handler ;CAAM_WRAPPER1 Interrupt + DCD CAAM_WRAPPER2_Handler ;CAAM_WRAPPER2 Interrupt + DCD SEMA4_HS_A7_Handler ;SEMA4_HS_A7 Interrupt + DCD EPDC_Handler ;EPDC Interrupt + DCD ENET1_MAC0_TRANS1_Handler ;ENET1_MAC0_TRANS1 Interrupt + DCD ENET1_MAC0_TRANS2_Handler ;ENET1_MAC0_TRANS2 Interrupt + DCD ENET1_MAC0_Handler ;ENET1_MAC0 Interrupt + DCD ENET1_1588_TIMER_Handler ;ENET1_1588_TIMER Interrupt + DCD PCIE_CTRL1_Handler ;PCIE_CTRL1 Interrupt + DCD PCIE_CTRL2_Handler ;PCIE_CTRL2 Interrupt + DCD PCIE_CTRL3_Handler ;PCIE_CTRL3 Interrupt + DCD PCIE_CTRL4_Handler ;PCIE_CTRL4 Interrupt + DCD UART7_Handler ;UART7 Interrupt + DCD PCIE_CTRL_REQUEST_Handler ;PCIE_CTRL_REQUEST Interrupt __Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - +__Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY + ; Reset Handler Reset_Handler PROC @@ -267,255 +267,266 @@ SysTick_Handler\ EXPORT SysTick_Handler [WEAK] B . ENDP -WDOG3_Handler\ +Default_Handler\ PROC + EXPORT GPR_Handler [WEAK] + EXPORT DAP_Handler [WEAK] + EXPORT SDMA_Handler [WEAK] + EXPORT DBGMON_Handler [WEAK] + EXPORT SNVS_Handler [WEAK] + EXPORT LCDIF_Handler [WEAK] + EXPORT SIM2_Handler [WEAK] + EXPORT CSI_Handler [WEAK] + EXPORT PXP1_Handler [WEAK] + EXPORT Reserved9_Handler [WEAK] EXPORT WDOG3_Handler [WEAK] - B . - ENDP -SEMA4_Handler\ - PROC - EXPORT SEMA4_Handler [WEAK] - B . - ENDP -UART6_Handler\ - PROC + EXPORT SEMA4_HS_M4_Handler [WEAK] + EXPORT APBHDMA_Handler [WEAK] + EXPORT EIM_Handler [WEAK] + EXPORT BCH_Handler [WEAK] + EXPORT GPMI_Handler [WEAK] EXPORT UART6_Handler [WEAK] - B . - ENDP -UART1_Handler\ - PROC + EXPORT FTM1_Handler [WEAK] + EXPORT FTM2_Handler [WEAK] + EXPORT SNVS_CONSOLIDATED_Handler [WEAK] + EXPORT SNVS_SECURITY_Handler [WEAK] + EXPORT CSU_Handler [WEAK] + EXPORT uSDHC1_Handler [WEAK] + EXPORT uSDHC2_Handler [WEAK] + EXPORT uSDHC3_Handler [WEAK] + EXPORT MIPI_CSI_Handler [WEAK] EXPORT UART1_Handler [WEAK] - B . - ENDP -UART2_Handler\ - PROC EXPORT UART2_Handler [WEAK] - B . - ENDP -UART3_Handler\ - PROC EXPORT UART3_Handler [WEAK] - B . - ENDP -UART4_Handler\ - PROC EXPORT UART4_Handler [WEAK] - B . - ENDP -UART5_Handler\ - PROC EXPORT UART5_Handler [WEAK] - B . - ENDP -eCSPI1_Handler\ - PROC EXPORT eCSPI1_Handler [WEAK] - B . - ENDP -eCSPI2_Handler\ - PROC EXPORT eCSPI2_Handler [WEAK] - B . - ENDP -eCSPI3_Handler\ - PROC EXPORT eCSPI3_Handler [WEAK] - B . - ENDP -eCSPI4_Handler\ - PROC EXPORT eCSPI4_Handler [WEAK] - B . - ENDP -I2C1_Handler\ - PROC EXPORT I2C1_Handler [WEAK] - B . - ENDP -I2C2_Handler\ - PROC EXPORT I2C2_Handler [WEAK] - B . - ENDP -I2C3_Handler\ - PROC EXPORT I2C3_Handler [WEAK] - B . - ENDP -I2C4_Handler\ - PROC EXPORT I2C4_Handler [WEAK] - B . - ENDP -GPT4_Handler\ - PROC + EXPORT RDC_Handler [WEAK] + EXPORT USB_OH3_OTG2_1_Handler [WEAK] + EXPORT MIPI_DSI_Handler [WEAK] + EXPORT USB_OH3_OTG2_2_Handler [WEAK] + EXPORT USB_OH2_OTG_Handler [WEAK] + EXPORT USB_OTG1_Handler [WEAK] + EXPORT USB_OTG2_Handler [WEAK] + EXPORT PXP2_Handler [WEAK] + EXPORT SCTR1_Handler [WEAK] + EXPORT SCTR2_Handler [WEAK] + EXPORT Analog_TempSensor_Handler [WEAK] + EXPORT SAI3_Handler [WEAK] + EXPORT Analog_brown_out_Handler [WEAK] EXPORT GPT4_Handler [WEAK] - B . - ENDP -GPT3_Handler\ - PROC EXPORT GPT3_Handler [WEAK] - B . - ENDP -GPT2_Handler\ - PROC EXPORT GPT2_Handler [WEAK] - B . - ENDP -GPT1_Handler\ - PROC EXPORT GPT1_Handler [WEAK] - B . - ENDP -GPIO1_INT7_Handler\ - PROC EXPORT GPIO1_INT7_Handler [WEAK] - B . - ENDP -GPIO1_INT6_Handler\ - PROC EXPORT GPIO1_INT6_Handler [WEAK] - B . - ENDP -GPIO1_INT5_Handler\ - PROC EXPORT GPIO1_INT5_Handler [WEAK] - B . - ENDP -GPIO1_INT4_Handler\ - PROC EXPORT GPIO1_INT4_Handler [WEAK] - B . - ENDP -GPIO1_INT3_Handler\ - PROC EXPORT GPIO1_INT3_Handler [WEAK] - B . - ENDP -GPIO1_INT2_Handler\ - PROC EXPORT GPIO1_INT2_Handler [WEAK] - B . - ENDP -GPIO1_INT1_Handler\ - PROC EXPORT GPIO1_INT1_Handler [WEAK] - B . - ENDP -GPIO1_INT0_Handler\ - PROC EXPORT GPIO1_INT0_Handler [WEAK] - B . - ENDP -GPIO1_INT15_0_Handler\ - PROC EXPORT GPIO1_INT15_0_Handler [WEAK] - B . - ENDP -GPIO1_INT31_16_Handler\ - PROC EXPORT GPIO1_INT31_16_Handler [WEAK] - B . - ENDP -GPIO2_INT15_0_Handler\ - PROC EXPORT GPIO2_INT15_0_Handler [WEAK] - B . - ENDP -GPIO2_INT31_16_Handler\ - PROC EXPORT GPIO2_INT31_16_Handler [WEAK] - B . - ENDP -GPIO3_INT15_0_Handler\ - PROC EXPORT GPIO3_INT15_0_Handler [WEAK] - B . - ENDP -GPIO3_INT31_16_Handler\ - PROC EXPORT GPIO3_INT31_16_Handler [WEAK] - B . - ENDP -GPIO4_INT15_0_Handler\ - PROC EXPORT GPIO4_INT15_0_Handler [WEAK] - B . - ENDP -GPIO4_INT31_16_Handler\ - PROC EXPORT GPIO4_INT31_16_Handler [WEAK] - B . - ENDP -GPIO5_INT15_0_Handler\ - PROC EXPORT GPIO5_INT15_0_Handler [WEAK] - B . - ENDP -GPIO5_INT31_16_Handler\ - PROC EXPORT GPIO5_INT31_16_Handler [WEAK] - B . - ENDP -GPIO6_INT15_0_Handler\ - PROC EXPORT GPIO6_INT15_0_Handler [WEAK] - B . - ENDP -GPIO6_INT31_16_Handler\ - PROC EXPORT GPIO6_INT31_16_Handler [WEAK] - B . - ENDP -GPIO7_INT15_0_Handler\ - PROC EXPORT GPIO7_INT15_0_Handler [WEAK] - B . - ENDP -GPIO7_INT31_16_Handler\ - PROC EXPORT GPIO7_INT31_16_Handler [WEAK] - B . - ENDP -MU_Handler\ - PROC - EXPORT MU_Handler [WEAK] - B . - ENDP -ADC1_Handler\ - PROC + EXPORT WDOG1_Handler [WEAK] + EXPORT WDOG2_Handler [WEAK] + EXPORT KPP_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT CCM1_Handler [WEAK] + EXPORT CCM2_Handler [WEAK] + EXPORT GPC_Handler [WEAK] + EXPORT MU_A7_Handler [WEAK] + EXPORT SRC_Handler [WEAK] + EXPORT SIM1_Handler [WEAK] + EXPORT RTIC_Handler [WEAK] + EXPORT CPU_Handler [WEAK] + EXPORT CPU_CTI_Handler [WEAK] + EXPORT CCM_SRC_GPC_Handler [WEAK] + EXPORT SAI1_Handler [WEAK] + EXPORT SAI2_Handler [WEAK] + EXPORT MU_M4_Handler [WEAK] EXPORT ADC1_Handler [WEAK] - B . - ENDP -ADC2_Handler\ - PROC EXPORT ADC2_Handler [WEAK] - B . - ENDP -FLEXCAN1_Handler\ - PROC + EXPORT ENET2_MAC0_TRANS1_Handler [WEAK] + EXPORT ENET2_MAC0_TRANS2_Handler [WEAK] + EXPORT ENET2_MAC0_IRQ_Handler [WEAK] + EXPORT ENET2_1588_TIMER_IRQ_Handler[WEAK] + EXPORT TPR_Handler [WEAK] + EXPORT CAAM_QUEUE_Handler [WEAK] + EXPORT CAAM_ERROR_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT TZASC1_Handler [WEAK] + EXPORT WDOG4_Handler [WEAK] EXPORT FLEXCAN1_Handler [WEAK] - B . - ENDP -FLEXCAN2_Handler\ - PROC EXPORT FLEXCAN2_Handler [WEAK] - B . - ENDP -UART7_Handler\ - PROC + EXPORT PERFMON1_Handler [WEAK] + EXPORT PERFMON2_Handler [WEAK] + EXPORT CAAM_WRAPPER1_Handler [WEAK] + EXPORT CAAM_WRAPPER2_Handler [WEAK] + EXPORT SEMA4_HS_A7_Handler [WEAK] + EXPORT EPDC_Handler [WEAK] + EXPORT ENET1_MAC0_TRANS1_Handler [WEAK] + EXPORT ENET1_MAC0_TRANS2_Handler [WEAK] + EXPORT ENET1_MAC0_Handler [WEAK] + EXPORT ENET1_1588_TIMER_Handler [WEAK] + EXPORT PCIE_CTRL1_Handler [WEAK] + EXPORT PCIE_CTRL2_Handler [WEAK] + EXPORT PCIE_CTRL3_Handler [WEAK] + EXPORT PCIE_CTRL4_Handler [WEAK] EXPORT UART7_Handler [WEAK] - B . - ENDP - -Default_Handler\ - PROC - + EXPORT PCIE_CTRL_REQUEST_Handler [WEAK] EXPORT DefaultISR [WEAK] - - +GPR_Handler +DAP_Handler +SDMA_Handler +DBGMON_Handler +SNVS_Handler +LCDIF_Handler +SIM2_Handler +CSI_Handler +PXP1_Handler +Reserved9_Handler +WDOG3_Handler +SEMA4_HS_M4_Handler +APBHDMA_Handler +EIM_Handler +BCH_Handler +GPMI_Handler +UART6_Handler +FTM1_Handler +FTM2_Handler +SNVS_CONSOLIDATED_Handler +SNVS_SECURITY_Handler +CSU_Handler +uSDHC1_Handler +uSDHC2_Handler +uSDHC3_Handler +MIPI_CSI_Handler +UART1_Handler +UART2_Handler +UART3_Handler +UART4_Handler +UART5_Handler +eCSPI1_Handler +eCSPI2_Handler +eCSPI3_Handler +eCSPI4_Handler +I2C1_Handler +I2C2_Handler +I2C3_Handler +I2C4_Handler +RDC_Handler +USB_OH3_OTG2_1_Handler +MIPI_DSI_Handler +USB_OH3_OTG2_2_Handler +USB_OH2_OTG_Handler +USB_OTG1_Handler +USB_OTG2_Handler +PXP2_Handler +SCTR1_Handler +SCTR2_Handler +Analog_TempSensor_Handler +SAI3_Handler +Analog_brown_out_Handler +GPT4_Handler +GPT3_Handler +GPT2_Handler +GPT1_Handler +GPIO1_INT7_Handler +GPIO1_INT6_Handler +GPIO1_INT5_Handler +GPIO1_INT4_Handler +GPIO1_INT3_Handler +GPIO1_INT2_Handler +GPIO1_INT1_Handler +GPIO1_INT0_Handler +GPIO1_INT15_0_Handler +GPIO1_INT31_16_Handler +GPIO2_INT15_0_Handler +GPIO2_INT31_16_Handler +GPIO3_INT15_0_Handler +GPIO3_INT31_16_Handler +GPIO4_INT15_0_Handler +GPIO4_INT31_16_Handler +GPIO5_INT15_0_Handler +GPIO5_INT31_16_Handler +GPIO6_INT15_0_Handler +GPIO6_INT31_16_Handler +GPIO7_INT15_0_Handler +GPIO7_INT31_16_Handler +WDOG1_Handler +WDOG2_Handler +KPP_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +CCM1_Handler +CCM2_Handler +GPC_Handler +MU_A7_Handler +SRC_Handler +SIM1_Handler +RTIC_Handler +CPU_Handler +CPU_CTI_Handler +CCM_SRC_GPC_Handler +SAI1_Handler +SAI2_Handler +MU_M4_Handler +ADC1_Handler +ADC2_Handler +ENET2_MAC0_TRANS1_Handler +ENET2_MAC0_TRANS2_Handler +ENET2_MAC0_IRQ_Handler +ENET2_1588_TIMER_IRQ_Handler +TPR_Handler +CAAM_QUEUE_Handler +CAAM_ERROR_Handler +QSPI_Handler +TZASC1_Handler +WDOG4_Handler +FLEXCAN1_Handler +FLEXCAN2_Handler +PERFMON1_Handler +PERFMON2_Handler +CAAM_WRAPPER1_Handler +CAAM_WRAPPER2_Handler +SEMA4_HS_A7_Handler +EPDC_Handler +ENET1_MAC0_TRANS1_Handler +ENET1_MAC0_TRANS2_Handler +ENET1_MAC0_Handler +ENET1_1588_TIMER_Handler +PCIE_CTRL1_Handler +PCIE_CTRL2_Handler +PCIE_CTRL3_Handler +PCIE_CTRL4_Handler +UART7_Handler +PCIE_CTRL_REQUEST_Handler DefaultISR - B DefaultISR ENDP ALIGN diff --git a/platform/devices/MCIMX7D/startup/gcc/startup_MCIMX7D_M4.S b/platform/devices/MCIMX7D/startup/gcc/startup_MCIMX7D_M4.S index 15965bb..5726a36 100644 --- a/platform/devices/MCIMX7D/startup/gcc/startup_MCIMX7D_M4.S +++ b/platform/devices/MCIMX7D/startup/gcc/startup_MCIMX7D_M4.S @@ -1,10 +1,10 @@ /* ---------------------------------------------------------------------------------------*/ -/* @file: startup_MCIMX7D_M4.s */ +/* @file: startup_MCIMX7D_M4.S */ /* @purpose: CMSIS Cortex-M4 Core Device Startup File */ -/* IMX7D_M4 */ -/* @version: 0.1 */ +/* MCIMX7D_M4 */ +/* @version: 1.0 */ /* @date: 2015-04-06 */ -/* @build: b54573 */ +/* @build: b150406 */ /* ---------------------------------------------------------------------------------------*/ /* */ /* Copyright (c) 2015 , Freescale Semiconductor, Inc. */ @@ -37,16 +37,6 @@ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ /*****************************************************************************/ - - - .word __etext - .word __data_start__ - .word __data_end__ - .word __bss_end__ - - - - .syntax unified .arch armv7-m @@ -72,139 +62,137 @@ __isr_vector: .long SysTick_Handler /* SysTick Handler*/ /* External Interrupts*/ - .long DefaultISR /* 16*/ - .long DefaultISR /* 17*/ - .long DefaultISR /* 18*/ - .long DefaultISR /* 19*/ - .long DefaultISR /* 20*/ - .long DefaultISR /* 21*/ - .long DefaultISR /* 22*/ - .long DefaultISR /* 23*/ - .long DefaultISR /* 24*/ - .long DefaultISR /* 25*/ - .long WDOG3_Handler /* WDOG3 Handler*/ - .long SEMA4_Handler /* SEMA4_Handler*/ - .long DefaultISR /* 28*/ - .long DefaultISR /* 29*/ - .long DefaultISR /* 30*/ - .long DefaultISR /* 31*/ - .long UART6_Handler /* UART6 Handler*/ - .long DefaultISR /* 33*/ - .long DefaultISR /* 34*/ - .long DefaultISR /* 35*/ - .long DefaultISR /* 36*/ - .long DefaultISR /* 37*/ - .long DefaultISR /* 38*/ - .long DefaultISR /* 39*/ - .long DefaultISR /* 40*/ - .long DefaultISR /* 41*/ - .long UART1_Handler /* UART1 Handler*/ - .long UART2_Handler /* UART2 Handler*/ - .long UART3_Handler /* UART3 Handler*/ - .long UART4_Handler /* UART4 Handler*/ - .long UART5_Handler /* UART5 Handler*/ - .long eCSPI1_Handler /* eCSPI1 Handler*/ - .long eCSPI2_Handler /* eCSPI2 Handler*/ - .long eCSPI3_Handler /* eCSPI3 Handler*/ - .long eCSPI4_Handler /* eCSPI4 Handler*/ - .long I2C1_Handler /* I2C1 Handler*/ - .long I2C2_Handler /* I2C2 Handler*/ - .long I2C3_Handler /* I2C3 Handler*/ - .long I2C4_Handler /* I2C4 Handler*/ - .long DefaultISR /* 55*/ - .long DefaultISR /* 56*/ - .long DefaultISR /* 57*/ - .long DefaultISR /* 58*/ - .long DefaultISR /* 59*/ - .long DefaultISR /* 60*/ - .long DefaultISR /* 61*/ - .long DefaultISR /* 62*/ - .long DefaultISR /* 63*/ - .long DefaultISR /* 64*/ - .long DefaultISR /* 65*/ - .long DefaultISR /* 66*/ - .long DefaultISR /* 67*/ - .long GPT4_Handler /* GPT4 handler*/ - .long GPT3_Handler /* GPT3 handler*/ - .long GPT2_Handler /* GPT2 handler*/ - .long GPT1_Handler /* GPT1 handler*/ - .long GPIO1_INT7_Handler /* Active HIGH Interrupt from INT7 from GPIO*/ - .long GPIO1_INT6_Handler /* Active HIGH Interrupt from INT6 from GPIO*/ - .long GPIO1_INT5_Handler /* Active HIGH Interrupt from INT5 from GPIO*/ - .long GPIO1_INT4_Handler /* Active HIGH Interrupt from INT4 from GPIO*/ - .long GPIO1_INT3_Handler /* Active HIGH Interrupt from INT3 from GPIO*/ - .long GPIO1_INT2_Handler /* Active HIGH Interrupt from INT2 from GPIO*/ - .long GPIO1_INT1_Handler /* Active HIGH Interrupt from INT1 from GPIO*/ - .long GPIO1_INT0_Handler /* Active HIGH Interrupt from INT0 from GPIO*/ - .long GPIO1_INT15_0_Handler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ - .long GPIO1_INT31_16_Handler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ - .long GPIO2_INT15_0_Handler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ - .long GPIO2_INT31_16_Handler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ - .long GPIO3_INT15_0_Handler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ - .long GPIO3_INT31_16_Handler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ - .long GPIO4_INT15_0_Handler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ - .long GPIO4_INT31_16_Handler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ - .long GPIO5_INT15_0_Handler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ - .long GPIO5_INT31_16_Handler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ - .long GPIO6_INT15_0_Handler /* Combined interrupt indication for GPIO6 signal 0 throughout 15*/ - .long GPIO6_INT31_16_Handler /* Combined interrupt indication for GPIO6 signal 16 throughout 31*/ - .long GPIO7_INT15_0_Handler /* Combined interrupt indication for GPIO7 signal 0 throughout 15*/ - .long GPIO7_INT31_16_Handler /* Combined interrupt indication for GPIO7 signal 16 throughout 31*/ - .long DefaultISR /* 94*/ - .long DefaultISR /* 95*/ - .long DefaultISR /* 96*/ - .long DefaultISR /* 97*/ - .long DefaultISR /* 98*/ - .long DefaultISR /* 99*/ - .long DefaultISR /* 100*/ - .long DefaultISR /* 101*/ - .long DefaultISR /* 102*/ - .long DefaultISR /* 103*/ - .long DefaultISR /* 104*/ - .long DefaultISR /* 105*/ - .long DefaultISR /* 106*/ - .long DefaultISR /* 107*/ - .long DefaultISR /* 108*/ - .long DefaultISR /* 109*/ - .long DefaultISR /* 110*/ - .long DefaultISR /* 111*/ - .long DefaultISR /* 112*/ - .long MU_Handler /* MU Handler*/ - .long ADC1_Handler /* ADC1 Handler*/ - .long ADC2_Handler /* ADC2 Handler*/ - .long DefaultISR /* 116*/ - .long DefaultISR /* 117*/ - .long DefaultISR /* 118*/ - .long DefaultISR /* 119*/ - .long DefaultISR /* 120*/ - .long DefaultISR /* 121*/ - .long DefaultISR /* 122*/ - .long DefaultISR /* 123*/ - .long DefaultISR /* 124*/ - .long DefaultISR /* 125*/ - .long FLEXCAN1_Handler /* FLEXCAN1 Handler*/ - .long FLEXCAN2_Handler /* FLEXCAN2 Handler*/ - .long DefaultISR /* 128*/ - .long DefaultISR /* 129*/ - .long DefaultISR /* 130*/ - .long DefaultISR /* 131*/ - .long DefaultISR /* 132*/ - .long DefaultISR /* 133*/ - .long DefaultISR /* 134*/ - .long DefaultISR /* 135*/ - .long DefaultISR /* 136*/ - .long DefaultISR /* 137*/ - .long DefaultISR /* 138*/ - .long DefaultISR /* 139*/ - .long DefaultISR /* 140*/ - .long DefaultISR /* 141*/ - .long UART7_Handler /* UART7 Handler*/ - .long DefaultISR /* 143*/ + .long GPR_Handler /* GPR Interrupt*/ + .long DAP_Handler /* DAP Interrupt*/ + .long SDMA_Handler /* SDMA Interrupt*/ + .long DBGMON_Handler /* DBGMON Interrupt*/ + .long SNVS_Handler /* SNVS Interrupt*/ + .long LCDIF_Handler /* LCDIF Interrupt*/ + .long SIM2_Handler /* SIM2 Interrupt*/ + .long CSI_Handler /* CSI Interrupt*/ + .long PXP1_Handler /* PXP1 Interrupt*/ + .long Reserved9_Handler /* Reserved interrupt 9*/ + .long WDOG3_Handler /* WDOG3 Interrupt*/ + .long SEMA4_HS_M4_Handler /* SEMA4_HS_M4 Interrupt*/ + .long APBHDMA_Handler /* APBHDMA Interrupt*/ + .long EIM_Handler /* EIM Interrupt*/ + .long BCH_Handler /* BCH Interrupt*/ + .long GPMI_Handler /* GPMI Interrupt*/ + .long UART6_Handler /* UART6 Interrupt*/ + .long FTM1_Handler /* FTM1 Interrupt*/ + .long FTM2_Handler /* FTM2 Interrupt*/ + .long SNVS_CONSOLIDATED_Handler /* SNVS_CONSOLIDATED Interrupt*/ + .long SNVS_SECURITY_Handler /* SNVS_SECURITY Interrupt*/ + .long CSU_Handler /* CSU Interrupt*/ + .long uSDHC1_Handler /* uSDHC1 Interrupt*/ + .long uSDHC2_Handler /* uSDHC2 Interrupt*/ + .long uSDHC3_Handler /* uSDHC3 Interrupt*/ + .long MIPI_CSI_Handler /* MIPI_CSI Interrupt*/ + .long UART1_Handler /* UART1 Interrupt*/ + .long UART2_Handler /* UART2 Interrupt*/ + .long UART3_Handler /* UART3 Interrupt*/ + .long UART4_Handler /* UART4 Interrupt*/ + .long UART5_Handler /* UART5 Interrupt*/ + .long eCSPI1_Handler /* eCSPI1 Interrupt*/ + .long eCSPI2_Handler /* eCSPI2 Interrupt*/ + .long eCSPI3_Handler /* eCSPI3 Interrupt*/ + .long eCSPI4_Handler /* eCSPI4 Interrupt*/ + .long I2C1_Handler /* I2C1 Interrupt*/ + .long I2C2_Handler /* I2C2 Interrupt*/ + .long I2C3_Handler /* I2C3 Interrupt*/ + .long I2C4_Handler /* I2C4 Interrupt*/ + .long RDC_Handler /* RDC Interrupt*/ + .long USB_OH3_OTG2_1_Handler /* USB_OH3_OTG2_1 Interrupt*/ + .long MIPI_DSI_Handler /* MIPI_DSI Interrupt*/ + .long USB_OH3_OTG2_2_Handler /* USB_OH3_OTG2_2 Interrupt*/ + .long USB_OH2_OTG_Handler /* USB_OH2_OTG Interrupt*/ + .long USB_OTG1_Handler /* USB_OTG1 Interrupt*/ + .long USB_OTG2_Handler /* USB_OTG2 Interrupt*/ + .long PXP2_Handler /* PXP2 Interrupt*/ + .long SCTR1_Handler /* SCTR1 Interrupt*/ + .long SCTR2_Handler /* SCTR2 Interrupt*/ + .long Analog_TempSensor_Handler /* Analog_TempSensor Interrupt*/ + .long SAI3_Handler /* SAI3 Interrupt*/ + .long Analog_brown_out_Handler /* Analog_brown_out Interrupt*/ + .long GPT4_Handler /* GPT4 Interrupt*/ + .long GPT3_Handler /* GPT3 Interrupt*/ + .long GPT2_Handler /* GPT2 Interrupt*/ + .long GPT1_Handler /* GPT1 Interrupt*/ + .long GPIO1_INT7_Handler /* GPIO1_INT7 Interrupt*/ + .long GPIO1_INT6_Handler /* GPIO1_INT6 Interrupt*/ + .long GPIO1_INT5_Handler /* GPIO1_INT5 Interrupt*/ + .long GPIO1_INT4_Handler /* GPIO1_INT4 Interrupt*/ + .long GPIO1_INT3_Handler /* GPIO1_INT3 Interrupt*/ + .long GPIO1_INT2_Handler /* GPIO1_INT2 Interrupt*/ + .long GPIO1_INT1_Handler /* GPIO1_INT1 Interrupt*/ + .long GPIO1_INT0_Handler /* GPIO1_INT0 Interrupt*/ + .long GPIO1_INT15_0_Handler /* GPIO1_INT15_0 Interrupt*/ + .long GPIO1_INT31_16_Handler /* GPIO1_INT31_16 Interrupt*/ + .long GPIO2_INT15_0_Handler /* GPIO2_INT15_0 Interrupt*/ + .long GPIO2_INT31_16_Handler /* GPIO2_INT31_16 Interrupt*/ + .long GPIO3_INT15_0_Handler /* GPIO3_INT15_0 Interrupt*/ + .long GPIO3_INT31_16_Handler /* GPIO3_INT31_16 Interrupt*/ + .long GPIO4_INT15_0_Handler /* GPIO4_INT15_0 Interrupt*/ + .long GPIO4_INT31_16_Handler /* GPIO4_INT31_16 Interrupt*/ + .long GPIO5_INT15_0_Handler /* GPIO5_INT15_0 Interrupt*/ + .long GPIO5_INT31_16_Handler /* GPIO5_INT31_16 Interrupt*/ + .long GPIO6_INT15_0_Handler /* GPIO6_INT15_0 Interrupt*/ + .long GPIO6_INT31_16_Handler /* GPIO6_INT31_16 Interrupt*/ + .long GPIO7_INT15_0_Handler /* GPIO7_INT15_0 Interrupt*/ + .long GPIO7_INT31_16_Handler /* GPIO7_INT31_16 Interrupt*/ + .long WDOG1_Handler /* WDOG1 Interrupt*/ + .long WDOG2_Handler /* WDOG2 Interrupt*/ + .long KPP_Handler /* KPP Interrupt*/ + .long PWM1_Handler /* PWM1 Interrupt*/ + .long PWM2_Handler /* PWM2 Interrupt*/ + .long PWM3_Handler /* PWM3 Interrupt*/ + .long PWM4_Handler /* PWM4 Interrupt*/ + .long CCM1_Handler /* CCM1 Interrupt*/ + .long CCM2_Handler /* CCM2 Interrupt*/ + .long GPC_Handler /* GPC Interrupt*/ + .long MU_A7_Handler /* MU_A7 Interrupt*/ + .long SRC_Handler /* SRC Interrupt*/ + .long SIM1_Handler /* SIM1 Interrupt*/ + .long RTIC_Handler /* RTIC Interrupt*/ + .long CPU_Handler /* CPU Interrupt*/ + .long CPU_CTI_Handler /* CPU_CTI Interrupt*/ + .long CCM_SRC_GPC_Handler /* CCM_SRC_GPC Interrupt*/ + .long SAI1_Handler /* SAI1 Interrupt*/ + .long SAI2_Handler /* SAI2 Interrupt*/ + .long MU_M4_Handler /* MU_M4 Interrupt*/ + .long ADC1_Handler /* ADC1 Interrupt*/ + .long ADC2_Handler /* ADC2 Interrupt*/ + .long ENET2_MAC0_TRANS1_Handler /* ENET2_MAC0_TRANS1 Interrupt*/ + .long ENET2_MAC0_TRANS2_Handler /* ENET2_MAC0_TRANS2 Interrupt*/ + .long ENET2_MAC0_IRQ_Handler /* ENET2_MAC0_IRQ Interrupt*/ + .long ENET2_1588_TIMER_IRQ_Handler /* ENET2_1588_TIMER_IRQ Interrupt*/ + .long TPR_Handler /* TPR Interrupt*/ + .long CAAM_QUEUE_Handler /* CAAM_QUEUE Interrupt*/ + .long CAAM_ERROR_Handler /* CAAM_ERROR Interrupt*/ + .long QSPI_Handler /* QSPI Interrupt*/ + .long TZASC1_Handler /* TZASC1 Interrupt*/ + .long WDOG4_Handler /* WDOG4 Interrupt*/ + .long FLEXCAN1_Handler /* FLEXCAN1 Interrupt*/ + .long FLEXCAN2_Handler /* FLEXCAN2 Interrupt*/ + .long PERFMON1_Handler /* PERFMON1 Interrupt*/ + .long PERFMON2_Handler /* PERFMON2 Interrupt*/ + .long CAAM_WRAPPER1_Handler /* CAAM_WRAPPER1 Interrupt*/ + .long CAAM_WRAPPER2_Handler /* CAAM_WRAPPER2 Interrupt*/ + .long SEMA4_HS_A7_Handler /* SEMA4_HS_A7 Interrupt*/ + .long EPDC_Handler /* EPDC Interrupt*/ + .long ENET1_MAC0_TRANS1_Handler /* ENET1_MAC0_TRANS1 Interrupt*/ + .long ENET1_MAC0_TRANS2_Handler /* ENET1_MAC0_TRANS2 Interrupt*/ + .long ENET1_MAC0_Handler /* ENET1_MAC0 Interrupt*/ + .long ENET1_1588_TIMER_Handler /* ENET1_1588_TIMER Interrupt*/ + .long PCIE_CTRL1_Handler /* PCIE_CTRL1 Interrupt*/ + .long PCIE_CTRL2_Handler /* PCIE_CTRL2 Interrupt*/ + .long PCIE_CTRL3_Handler /* PCIE_CTRL3 Interrupt*/ + .long PCIE_CTRL4_Handler /* PCIE_CTRL4 Interrupt*/ + .long UART7_Handler /* UART7 Interrupt*/ + .long PCIE_CTRL_REQUEST_Handler /* PCIE_CTRL_REQUEST Interrupt*/ .size __isr_vector, . - __isr_vector - - .text .thumb @@ -220,24 +208,57 @@ Reset_Handler: #ifndef __NO_SYSTEM_INIT bl SystemInit #endif - /* data copy */ - ldr r0,=__DATA_ROM - subs r0,r0,#0x1 - ldr r1,=__data_start__ - subs r1,r1,#0x1 - ldr r2,=__data_end__ - subs r3,r2,r1 - b Copy_init_data - Loop_copy_init_data: - adds r1,r1,#0x1 - adds r0,r0,#0x1 - ldrb r4,[r0] - str r4,[r1] +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ - Copy_init_data: - subs r3,r3,#0x1 - cmp r3,#0x0 - bne Loop_copy_init_data + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ cpsie i /* Unmask interrupts */ bl _start @@ -270,9 +291,32 @@ DefaultISR: def_irq_handler DebugMon_Handler def_irq_handler PendSV_Handler def_irq_handler SysTick_Handler + def_irq_handler GPR_Handler + def_irq_handler DAP_Handler + def_irq_handler SDMA_Handler + def_irq_handler DBGMON_Handler + def_irq_handler SNVS_Handler + def_irq_handler LCDIF_Handler + def_irq_handler SIM2_Handler + def_irq_handler CSI_Handler + def_irq_handler PXP1_Handler + def_irq_handler Reserved9_Handler def_irq_handler WDOG3_Handler - def_irq_handler SEMA4_Handler + def_irq_handler SEMA4_HS_M4_Handler + def_irq_handler APBHDMA_Handler + def_irq_handler EIM_Handler + def_irq_handler BCH_Handler + def_irq_handler GPMI_Handler def_irq_handler UART6_Handler + def_irq_handler FTM1_Handler + def_irq_handler FTM2_Handler + def_irq_handler SNVS_CONSOLIDATED_Handler + def_irq_handler SNVS_SECURITY_Handler + def_irq_handler CSU_Handler + def_irq_handler uSDHC1_Handler + def_irq_handler uSDHC2_Handler + def_irq_handler uSDHC3_Handler + def_irq_handler MIPI_CSI_Handler def_irq_handler UART1_Handler def_irq_handler UART2_Handler def_irq_handler UART3_Handler @@ -286,6 +330,19 @@ DefaultISR: def_irq_handler I2C2_Handler def_irq_handler I2C3_Handler def_irq_handler I2C4_Handler + def_irq_handler RDC_Handler + def_irq_handler USB_OH3_OTG2_1_Handler + def_irq_handler MIPI_DSI_Handler + def_irq_handler USB_OH3_OTG2_2_Handler + def_irq_handler USB_OH2_OTG_Handler + def_irq_handler USB_OTG1_Handler + def_irq_handler USB_OTG2_Handler + def_irq_handler PXP2_Handler + def_irq_handler SCTR1_Handler + def_irq_handler SCTR2_Handler + def_irq_handler Analog_TempSensor_Handler + def_irq_handler SAI3_Handler + def_irq_handler Analog_brown_out_Handler def_irq_handler GPT4_Handler def_irq_handler GPT3_Handler def_irq_handler GPT2_Handler @@ -312,10 +369,54 @@ DefaultISR: def_irq_handler GPIO6_INT31_16_Handler def_irq_handler GPIO7_INT15_0_Handler def_irq_handler GPIO7_INT31_16_Handler - def_irq_handler MU_Handler + def_irq_handler WDOG1_Handler + def_irq_handler WDOG2_Handler + def_irq_handler KPP_Handler + def_irq_handler PWM1_Handler + def_irq_handler PWM2_Handler + def_irq_handler PWM3_Handler + def_irq_handler PWM4_Handler + def_irq_handler CCM1_Handler + def_irq_handler CCM2_Handler + def_irq_handler GPC_Handler + def_irq_handler MU_A7_Handler + def_irq_handler SRC_Handler + def_irq_handler SIM1_Handler + def_irq_handler RTIC_Handler + def_irq_handler CPU_Handler + def_irq_handler CPU_CTI_Handler + def_irq_handler CCM_SRC_GPC_Handler + def_irq_handler SAI1_Handler + def_irq_handler SAI2_Handler + def_irq_handler MU_M4_Handler def_irq_handler ADC1_Handler def_irq_handler ADC2_Handler + def_irq_handler ENET2_MAC0_TRANS1_Handler + def_irq_handler ENET2_MAC0_TRANS2_Handler + def_irq_handler ENET2_MAC0_IRQ_Handler + def_irq_handler ENET2_1588_TIMER_IRQ_Handler + def_irq_handler TPR_Handler + def_irq_handler CAAM_QUEUE_Handler + def_irq_handler CAAM_ERROR_Handler + def_irq_handler QSPI_Handler + def_irq_handler TZASC1_Handler + def_irq_handler WDOG4_Handler def_irq_handler FLEXCAN1_Handler def_irq_handler FLEXCAN2_Handler + def_irq_handler PERFMON1_Handler + def_irq_handler PERFMON2_Handler + def_irq_handler CAAM_WRAPPER1_Handler + def_irq_handler CAAM_WRAPPER2_Handler + def_irq_handler SEMA4_HS_A7_Handler + def_irq_handler EPDC_Handler + def_irq_handler ENET1_MAC0_TRANS1_Handler + def_irq_handler ENET1_MAC0_TRANS2_Handler + def_irq_handler ENET1_MAC0_Handler + def_irq_handler ENET1_1588_TIMER_Handler + def_irq_handler PCIE_CTRL1_Handler + def_irq_handler PCIE_CTRL2_Handler + def_irq_handler PCIE_CTRL3_Handler + def_irq_handler PCIE_CTRL4_Handler def_irq_handler UART7_Handler + def_irq_handler PCIE_CTRL_REQUEST_Handler .end diff --git a/platform/devices/MCIMX7D/startup/iar/startup_MCIMX7D_M4.s b/platform/devices/MCIMX7D/startup/iar/startup_MCIMX7D_M4.s deleted file mode 100644 index 385c49c..0000000 --- a/platform/devices/MCIMX7D/startup/iar/startup_MCIMX7D_M4.s +++ /dev/null @@ -1,520 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MCIMX7D_M4.s -; @purpose: CMSIS Cortex-M4 Core Device Startup File -; IMX7D_M4 -; @version: 0.1 -; @date: 2015-04-06 -; @build: b49163 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 2015 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - -;External Interrupts - DCD DefaultISR ;Reserved Interrupt 16 - DCD DefaultISR ;Reserved Interrupt 17 - DCD DefaultISR ;Reserved Interrupt 18 - DCD DefaultISR ;Reserved Interrupt 19 - DCD DefaultISR ;Reserved Interrupt 20 - DCD DefaultISR ;Reserved Interrupt 21 - DCD DefaultISR ;Reserved Interrupt 22 - DCD DefaultISR ;Reserved Interrupt 23 - DCD DefaultISR ;Reserved Interrupt 24 - DCD DefaultISR ;Reserved Interrupt 25 - DCD WDOG3_Handler ;WDOG3 Handler - DCD SEMA4_Handler ;SEMA4 handler - DCD DefaultISR ;Reserved Interrupt 28 - DCD DefaultISR ;Reserved Interrupt 29 - DCD DefaultISR ;Reserved Interrupt 30 - DCD DefaultISR ;Reserved Interrupt 31 - DCD UART6_Handler ;UART6 Handler - DCD DefaultISR ;Reserved Interrupt 33 - DCD DefaultISR ;Reserved Interrupt 34 - DCD DefaultISR ;Reserved Interrupt 35 - DCD DefaultISR ;Reserved Interrupt 36 - DCD DefaultISR ;Reserved Interrupt 37 - DCD DefaultISR ;Reserved Interrupt 38 - DCD DefaultISR ;Reserved Interrupt 39 - DCD DefaultISR ;Reserved Interrupt 40 - DCD DefaultISR ;Reserved Interrupt 41 - DCD UART1_Handler ;UART1 Handler - DCD UART2_Handler ;UART2 Handler - DCD UART3_Handler ;UART3 Handler - DCD UART4_Handler ;UART4 Handler - DCD UART5_Handler ;UART5 Handler - DCD eCSPI1_Handler ;eCSPI1 Handler - DCD eCSPI2_Handler ;eCSPI2 Handler - DCD eCSPI3_Handler ;eCSPI3 Handler - DCD eCSPI4_Handler ;eCSPI4 Handler - DCD I2C1_Handler ;I2C1 Handler - DCD I2C2_Handler ;I2C2 Handler - DCD I2C3_Handler ;I2C3 Handler - DCD I2C4_Handler ;I2C4 Handler - DCD DefaultISR ;Reserved Interrupt 55 - DCD DefaultISR ;Reserved Interrupt 56 - DCD DefaultISR ;Reserved Interrupt 57 - DCD DefaultISR ;Reserved Interrupt 58 - DCD DefaultISR ;Reserved Interrupt 59 - DCD DefaultISR ;Reserved Interrupt 60 - DCD DefaultISR ;Reserved Interrupt 61 - DCD DefaultISR ;Reserved Interrupt 62 - DCD DefaultISR ;Reserved Interrupt 63 - DCD DefaultISR ;Reserved Interrupt 64 - DCD DefaultISR ;Reserved Interrupt 65 - DCD DefaultISR ;Reserved Interrupt 66 - DCD DefaultISR ;Reserved Interrupt 67 - DCD GPT4_Handler ;GPT4 handler - DCD GPT3_Handler ;GPT3 handler - DCD GPT2_Handler ;GPT2 handler - DCD GPT1_Handler ;GPT1 handler - DCD GPIO1_INT7_Handler ;Active HIGH Interrupt from INT7 from GPIO - DCD GPIO1_INT6_Handler ;Active HIGH Interrupt from INT6 from GPIO - DCD GPIO1_INT5_Handler ;Active HIGH Interrupt from INT5 from GPIO - DCD GPIO1_INT4_Handler ;Active HIGH Interrupt from INT4 from GPIO - DCD GPIO1_INT3_Handler ;Active HIGH Interrupt from INT3 from GPIO - DCD GPIO1_INT2_Handler ;Active HIGH Interrupt from INT2 from GPIO - DCD GPIO1_INT1_Handler ;Active HIGH Interrupt from INT1 from GPIO - DCD GPIO1_INT0_Handler ;Active HIGH Interrupt from INT0 from GPIO - DCD GPIO1_INT15_0_Handler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 - DCD GPIO1_INT31_16_Handler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 - DCD GPIO2_INT15_0_Handler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 - DCD GPIO2_INT31_16_Handler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 - DCD GPIO3_INT15_0_Handler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 - DCD GPIO3_INT31_16_Handler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 - DCD GPIO4_INT15_0_Handler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 - DCD GPIO4_INT31_16_Handler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 - DCD GPIO5_INT15_0_Handler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 - DCD GPIO5_INT31_16_Handler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 - DCD GPIO6_INT15_0_Handler ;Combined interrupt indication for GPIO6 signal 0 throughout 15 - DCD GPIO6_INT31_16_Handler ;Combined interrupt indication for GPIO6 signal 16 throughout 31 - DCD GPIO7_INT15_0_Handler ;Combined interrupt indication for GPIO7 signal 0 throughout 15 - DCD GPIO7_INT31_16_Handler ;Combined interrupt indication for GPIO7 signal 16 throughout 31 - DCD DefaultISR ;Reserved Interrupt 94 - DCD DefaultISR ;Reserved Interrupt 95 - DCD DefaultISR ;Reserved Interrupt 96 - DCD DefaultISR ;Reserved Interrupt 97 - DCD DefaultISR ;Reserved Interrupt 98 - DCD DefaultISR ;Reserved Interrupt 99 - DCD DefaultISR ;Reserved Interrupt 100 - DCD DefaultISR ;Reserved Interrupt 101 - DCD DefaultISR ;Reserved Interrupt 102 - DCD DefaultISR ;Reserved Interrupt 103 - DCD DefaultISR ;Reserved Interrupt 104 - DCD DefaultISR ;Reserved Interrupt 105 - DCD DefaultISR ;Reserved Interrupt 106 - DCD DefaultISR ;Reserved Interrupt 107 - DCD DefaultISR ;Reserved Interrupt 108 - DCD DefaultISR ;Reserved Interrupt 109 - DCD DefaultISR ;Reserved Interrupt 110 - DCD DefaultISR ;Reserved Interrupt 111 - DCD DefaultISR ;Reserved Interrupt 112 - DCD MU_Handler ;MU Handler - DCD ADC1_Handler ;ADC1 Handler - DCD ADC2_Handler ;ADC2 Handler - DCD DefaultISR ;Reserved Interrupt 116 - DCD DefaultISR ;Reserved Interrupt 117 - DCD DefaultISR ;Reserved Interrupt 118 - DCD DefaultISR ;Reserved Interrupt 119 - DCD DefaultISR ;Reserved Interrupt 120 - DCD DefaultISR ;Reserved Interrupt 121 - DCD DefaultISR ;Reserved Interrupt 122 - DCD DefaultISR ;Reserved Interrupt 123 - DCD DefaultISR ;Reserved Interrupt 124 - DCD DefaultISR ;Reserved Interrupt 125 - DCD FLEXCAN1_Handler ;FLEXCAN1 Handler - DCD FLEXCAN2_Handler ;FLEXCAN2 Handler - DCD DefaultISR ;Reserved Interrupt 128 - DCD DefaultISR ;Reserved Interrupt 129 - DCD DefaultISR ;Reserved Interrupt 130 - DCD DefaultISR ;Reserved Interrupt 131 - DCD DefaultISR ;Reserved Interrupt 132 - DCD DefaultISR ;Reserved Interrupt 133 - DCD DefaultISR ;Reserved Interrupt 134 - DCD DefaultISR ;Reserved Interrupt 135 - DCD DefaultISR ;Reserved Interrupt 136 - DCD DefaultISR ;Reserved Interrupt 137 - DCD DefaultISR ;Reserved Interrupt 138 - DCD DefaultISR ;Reserved Interrupt 139 - DCD DefaultISR ;Reserved Interrupt 140 - DCD DefaultISR ;Reserved Interrupt 141 - DCD UART7_Handler ;UART7 Handler - DCD DefaultISR ;Reserved Interrupt 143 - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDOG3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG3_Handler - B . - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B . - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B . - - PUBWEAK UART3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART3_Handler - B . - - PUBWEAK UART4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_Handler - B . - - PUBWEAK UART5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_Handler - B . - - PUBWEAK UART6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART6_Handler - B . - - PUBWEAK UART7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART7_Handler - B . - - PUBWEAK eCSPI1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -eCSPI1_Handler - B . - - PUBWEAK eCSPI2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -eCSPI2_Handler - B . - - PUBWEAK eCSPI3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -eCSPI3_Handler - B . - - PUBWEAK eCSPI4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -eCSPI4_Handler - B . - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B . - - PUBWEAK I2C2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_Handler - B . - - PUBWEAK I2C3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_Handler - B . - - PUBWEAK I2C4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C4_Handler - B . - - PUBWEAK GPT4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPT4_Handler - B . - - PUBWEAK GPT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPT3_Handler - B . - - PUBWEAK GPT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPT2_Handler - B . - - PUBWEAK GPT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPT1_Handler - B . - - PUBWEAK GPIO1_INT7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT7_Handler - B . - - PUBWEAK GPIO1_INT6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT6_Handler - B . - - PUBWEAK GPIO1_INT5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT5_Handler - B . - - PUBWEAK GPIO1_INT4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT4_Handler - B . - - PUBWEAK GPIO1_INT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT3_Handler - B . - - PUBWEAK GPIO1_INT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT2_Handler - B . - - PUBWEAK GPIO1_INT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT1_Handler - B . - - PUBWEAK GPIO1_INT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT0_Handler - B . - - PUBWEAK GPIO1_INT15_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT15_0_Handler - B . - - PUBWEAK GPIO1_INT31_16_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO1_INT31_16_Handler - B . - - PUBWEAK GPIO2_INT15_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO2_INT15_0_Handler - B . - - PUBWEAK GPIO2_INT31_16_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO2_INT31_16_Handler - B . - - PUBWEAK GPIO3_INT15_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO3_INT15_0_Handler - B . - - PUBWEAK GPIO3_INT31_16_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO3_INT31_16_Handler - B . - - PUBWEAK GPIO4_INT15_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO4_INT15_0_Handler - B . - - PUBWEAK GPIO4_INT31_16_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO4_INT31_16_Handler - B . - - PUBWEAK GPIO5_INT15_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO5_INT15_0_Handler - B . - - PUBWEAK GPIO5_INT31_16_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO5_INT31_16_Handler - B . - - PUBWEAK GPIO6_INT15_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO6_INT15_0_Handler - B . - - PUBWEAK GPIO6_INT31_16_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO6_INT31_16_Handler - B . - - PUBWEAK GPIO7_INT15_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO7_INT15_0_Handler - B . - - PUBWEAK GPIO7_INT31_16_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO7_INT31_16_Handler - B . - - PUBWEAK MU_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MU_Handler - B . - - PUBWEAK ADC1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC1_Handler - B . - - PUBWEAK ADC2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC2_Handler - B . - - PUBWEAK SEMA4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SEMA4_Handler - B . - - PUBWEAK FLEXCAN1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -FLEXCAN1_Handler - - PUBWEAK FLEXCAN2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -FLEXCAN2_Handler - - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(1) -DefaultISR - B DefaultISR - - END - diff --git a/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.c b/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.c index 550e4ba..dedf6de 100644 --- a/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.c +++ b/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.c @@ -30,6 +30,10 @@ #include <stdbool.h> #include "MCIMX7D_M4.h" +/* ---------------------------------------------------------------------------- + -- Helper macro + ---------------------------------------------------------------------------- */ +#define EXTRACT_BITFIELD(reg, shift, width) ((*(reg) & (((1 << (width)) - 1) << (shift))) >> (shift)) /* ---------------------------------------------------------------------------- -- Vector Table offset @@ -39,35 +43,145 @@ /* ---------------------------------------------------------------------------- -- Core clock ---------------------------------------------------------------------------- */ -uint32_t SystemCoreClock = 240000000; +uint32_t SystemCoreClock = 240000000ul; /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ void SystemInit(void) { - // The Vector table base address is given by linker script. + /* The Vector table base address is given by linker script. */ #if defined(__CC_ARM) - extern uint32_t Image$$ER_m_text$$Base[]; + extern uint32_t Image$$VECTOR_ROM$$Base[]; #else extern uint32_t __VECTOR_TABLE[]; #endif - + /* Enable FPU */ #if ((1 == __FPU_PRESENT) && (1 == __FPU_USED)) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif - /* M4 core root SYS PLL Div2: 240MHz */ + /* Set M4 core clock to SYS_PLL_Div2 @ 240MHz. */ CCM_TARGET_ROOT1 = 0x11000000; - /* initialize cache */ - // Enable I_Cache - // Enable D_Cache + /* Initialize MPU */ + /* Make sure outstanding transfers are done. */ + __DMB(); + /* Disable the MPU. */ + MPU->CTRL = 0; + + /* Select Region 0 to configure. */ + MPU->RNR = 0; + /* Set base address of Region 0 to the base of Default CODE + SRAM memory region(1GB). */ + MPU->RBAR = 0x00000000; + /* Region 0 setting: + * 1) Enable Instruction Access; + * 2) Full Data Access Permission; + * 3) Outer and inner Non-Cacheable; + * 4) Region Not Shared; + * 5) All Sub-Region Enable; + * 6) MPU Protection Region size = 1GB; + * 7) Enable Region 0. + */ + MPU->RASR = 0x0308003B; + + /* Select Region 1 to configure. */ + MPU->RNR = 1; + /* Set base address of Region 1 to the base of Default RAM memory region(2GB). */ + MPU->RBAR = 0x60000000; + /* Region 1 setting: + * 1) Enable Instruction Access; + * 2) Full Data Access Permission; + * 3) Outer and inner Non-Cacheable; + * 4) Region Not Shared; + * 5) All Sub-Region Enable; + * 6) MPU Protection Region size = 2GB; + * 7) Enable Region 1. + */ + MPU->RASR = 0x0308003D; + + /* Select Region 2 to configure. */ + MPU->RNR = 2; + /* Set base address of Region 2 to the base of Cacheable OCRAM region(128KB). */ + MPU->RBAR = 0x20200000; + /* Region 2 setting: + * 1) Enable Instruction Access; + * 2) Full Data Access Permission; + * 3) Write Back, Write Allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enable; + * 6) MPU Protection Region size = 128KB; + * 7) Enable Region 2. + */ + MPU->RASR = 0x030B0021; + + /* Select Region 3 to configure. */ + MPU->RNR = 3; + /* Set base address of Region 3 to the base of Cacheable QSPI Flash region(2MB). */ + MPU->RBAR = 0x60000000; + /* Region 3 setting: + * 1) Enable Instruction Access; + * 2) Full Data Access Permission; + * 3) Write Back, Write Allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enable; + * 6) MPU Protection Region size = 2MB; + * 7) Enable Region 3. + */ + MPU->RASR = 0x030B0029; - /* relocate vector table */ + /* Select Region 4 to configure. */ + MPU->RNR = 4; + /* Set base address of Region 4 to the base of Cacheable DDR RAM region(2MB). */ + MPU->RBAR = 0x80000000; + /* Region 4 setting: + * 1) Enable Instruction Access; + * 2) Full Data Access Permission; + * 3) Write Back, Write Allocate; + * 4) Region Not Shared; + * 5) All Sub-Region Enable; + * 6) MPU Protection Region size = 2MB; + * 7) Enable Region 4. + */ + MPU->RASR = 0x030B0029; + + /* Disable unused regions. */ + MPU->RNR = 5; + MPU->RBAR = 0; + MPU->RASR = 0; + MPU->RNR = 6; + MPU->RBAR = 0; + MPU->RASR = 0; + MPU->RNR = 7; + MPU->RBAR = 0; + MPU->RASR = 0; + + /* Enable Privileged default memory map and the MPU. */ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | + MPU_CTRL_PRIVDEFENA_Msk; + /* Memory barriers to ensure subsequence data & instruction + * transfers using updated MPU settings. + */ + __DSB(); + __ISB(); + + /* Initialize Cache */ + /* Enable System Bus Cache */ + /* set command to invalidate all ways, enable write buffer + and write GO bit to initiate command */ + LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; + LMEM_PSCCR |= LMEM_PSCCR_GO_MASK; + /* wait until the command completes */ + while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK); + /* Enable cache, enable write buffer */ + LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); + __DSB(); + __ISB(); + + /* Relocate vector table */ #if defined(__CC_ARM) - SCB->VTOR = (uint32_t)Image$$ER_m_text$$Base + VECT_TAB_OFFSET; + SCB->VTOR = (uint32_t)Image$$VECTOR_ROM$$Base + VECT_TAB_OFFSET; #else SCB->VTOR = (uint32_t)__VECTOR_TABLE + VECT_TAB_OFFSET; #endif @@ -76,10 +190,204 @@ void SystemInit(void) /* ---------------------------------------------------------------------------- -- SystemCoreClockUpdate() ---------------------------------------------------------------------------- */ - void SystemCoreClockUpdate(void) { - SystemCoreClock = 240000000; + uint8_t coreClockRoot = EXTRACT_BITFIELD(&CCM_TARGET_ROOT1, 24, 3); + uint8_t coreClockPreDiv = EXTRACT_BITFIELD(&CCM_TARGET_ROOT1, 16, 3) + 1; + uint8_t coreClockPostDiv = EXTRACT_BITFIELD(&CCM_TARGET_ROOT1, 0, 6) + 1; + float temp; + + switch (coreClockRoot) + { + /* OSC_24M: */ + case 0: + SystemCoreClock = 24000000ul; + break; + + /* SYS_PLL_DIV2: */ + case 1: + /* Check SYS PLL bypass bit. */ + if (!EXTRACT_BITFIELD(&CCM_ANALOG_PLL_480_REG(CCM_ANALOG), 16, 1)) + { + SystemCoreClock = (1 == EXTRACT_BITFIELD(&CCM_ANALOG_PLL_480_REG(CCM_ANALOG), \ + 0, 1)) ? 264000000ul : 240000000ul; + } + else + { + SystemCoreClock = 24000000ul; + } + break; + + /* ENET_PLL_DIV4: */ + case 2: + /* Check ENET PLL bypass bit. */ + if (!EXTRACT_BITFIELD(&CCM_ANALOG_PLL_ENET_REG(CCM_ANALOG), 16, 1)) + SystemCoreClock = 250000000ul; + else + SystemCoreClock = 24000000ul; + break; + + /* SYS_PLL_PFD2: */ + case 3: + /* Check SYS SYS PLL bypass bit. */ + if (!EXTRACT_BITFIELD(&CCM_ANALOG_PLL_480_REG(CCM_ANALOG), 16, 1)) + { + SystemCoreClock = (1 == EXTRACT_BITFIELD(&CCM_ANALOG_PLL_480_REG(CCM_ANALOG), \ + 0, 1)) ? 528000000ul : 480000000ul; + SystemCoreClock /= EXTRACT_BITFIELD(&CCM_ANALOG_PFD_480A_REG(CCM_ANALOG), 16, 6); + SystemCoreClock *= 18; + } + else + { + SystemCoreClock = 24000000ul; + } + break; + + /* DDR_PLL_DIV2: */ + case 4: + /* Check DDR PLL bypass bit. */ + if (!EXTRACT_BITFIELD(&CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG), 16, 1)) + { + if (1 == EXTRACT_BITFIELD(&CCM_ANALOG_PLL_DDR_SS_REG(CCM_ANALOG), 15, 1)) + { + temp = (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_DDR_SS_REG(CCM_ANALOG), 0, 15) / + (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_DDR_DENOM_REG(CCM_ANALOG), 0, 30) * + (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_DDR_NUM_REG(CCM_ANALOG), 0, 30); + temp += EXTRACT_BITFIELD(&CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG), 0, 7); + SystemCoreClock = (uint32_t)(24000000ul * temp); + } + else + SystemCoreClock = 24000000ul * EXTRACT_BITFIELD(&CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG), 0, 7); + + switch (EXTRACT_BITFIELD(&CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG), 21, 2)) + { + case 0: + SystemCoreClock >>= 2; + break; + case 1: + SystemCoreClock >>= 1; + break; + case 2: + case 3: + break; + } + + SystemCoreClock >>= 1; + } + else + { + SystemCoreClock = 24000000ul; + } + break; + + /* AUDIO_PLL: */ + case 5: + /* Check AUDIO PLL bypass bit. */ + if (!EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG), 16, 1)) + { + if (1 == EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_SS_REG(CCM_ANALOG), 15, 1)) + { + temp = (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_SS_REG(CCM_ANALOG), 0, 15) / + (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_DENOM_REG(CCM_ANALOG), 0, 30) * + (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_NUM_REG(CCM_ANALOG), 0, 30); + temp += EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG), 0, 7); + SystemCoreClock = (uint32_t)(24000000ul * temp); + } + else + SystemCoreClock = 24000000ul * EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG), 0, 7); + + switch (EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG), 19, 2)) + { + case 0x0: + SystemCoreClock >>= 2; + break; + case 0x1: + SystemCoreClock >>= 1; + break; + case 0x2: + case 0x3: + break; + } + + switch (EXTRACT_BITFIELD(&CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG), 22, 2)) + { + case 0x0: + case 0x2: + break; + case 0x1: + SystemCoreClock >>= 1; + break; + case 0x3: + SystemCoreClock >>= 2; + break; + } + } + else + { + SystemCoreClock = 24000000ul; + } + break; + + /* VIDEO_PLL: */ + case 6: + /* Check VIDEO PLL bypass bit. */ + if (!EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG), 16, 1)) + { + if (1 == EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_SS_REG(CCM_ANALOG), 15, 1)) + { + temp = (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_SS_REG(CCM_ANALOG), 0, 15) / + (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_DENOM_REG(CCM_ANALOG), 0, 30) * + (float)EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_NUM_REG(CCM_ANALOG), 0, 30); + temp += EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG), 0, 7); + SystemCoreClock = (uint32_t)(24000000ul * temp); + } + else + SystemCoreClock = 24000000ul * EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG), 0, 7); + + switch (EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG), 19, 2)) + { + case 0x0: + SystemCoreClock >>= 2; + break; + case 0x1: + SystemCoreClock >>= 1; + break; + case 0x2: + case 0x3: + break; + } + + switch (EXTRACT_BITFIELD(&CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG), 22, 2)) + { + case 0x0: + case 0x2: + break; + case 0x1: + SystemCoreClock >>= 1; + break; + case 0x3: + SystemCoreClock >>= 2; + break; + } + } + else + { + SystemCoreClock = 24000000ul; + } + break; + + /* USB_PLL: */ + case 7: + SystemCoreClock = 480000000ul; + break; + + default: + /* Set SystemCoreClock to default clock freq. */ + SystemCoreClock = 240000000ul; + break; + } + + SystemCoreClock = (SystemCoreClock / coreClockPreDiv) / coreClockPostDiv; } /******************************************************************************* diff --git a/platform/devices/device_imx.h b/platform/devices/device_imx.h index fe1b21b..b90fbcc 100644 --- a/platform/devices/device_imx.h +++ b/platform/devices/device_imx.h @@ -48,12 +48,14 @@ * * The CPU macro should be declared in the project or makefile. */ -#if defined(CPU_IMX6SX_M4) +#if defined(CPU_MCIMX6X_M4) /* CMSIS-style register definitions */ - #include "MCIMX6X/include/MCIMX6SX_M4.h" + #include "MCIMX6X/include/MCIMX6X_M4.h" + #define RDC_SEMAPHORE_MASTER_SELF (5) + #define SEMA4_PROCESSOR_SELF (1) -#elif defined(CPU_IMX7D_M4) +#elif defined(CPU_MCIMX7D_M4) /* CMSIS-style register definitions */ #include "MCIMX7D/include/MCIMX7D_M4.h" diff --git a/platform/drivers/inc/adc_imx7d.h b/platform/drivers/inc/adc_imx7d.h index d163c3a..a3d4eba 100644 --- a/platform/drivers/inc/adc_imx7d.h +++ b/platform/drivers/inc/adc_imx7d.h @@ -45,113 +45,98 @@ * Definitions ******************************************************************************/ -/*! - * @brief ADC module initialize structure. - */ +/*! @brief ADC module initialize structure. */ typedef struct _adc_init_config { - uint32_t sampleRate; /*!< The desired ADC sample rate.*/ - bool levelShifterEnable; /*!< The level shifter module configuration(Enable to power on ADC module).*/ + uint32_t sampleRate; /*!< The desired ADC sample rate.*/ + bool levelShifterEnable; /*!< The level shifter module configuration(Enable to power on ADC module).*/ } adc_init_config_t; -/*! - * @brief ADC logic channel initialize structure. - */ +/*! @brief ADC logic channel initialize structure. */ typedef struct _adc_logic_ch_init_config { - uint8_t inputChannel; /*!< The logic channel to be set.*/ - bool coutinuousEnable; /*!< Continuous sample mode enable configuration.*/ - uint32_t convertRate; /*!< The continuous rate when continuous sample enabled.*/ - bool averageEnable; /*!< Hardware average enable configuration.*/ - uint8_t averageNumber; /*!< The average number for hardware average function.*/ + uint32_t convertRate; /*!< The continuous rate when continuous sample enabled.*/ + uint8_t inputChannel; /*!< The logic channel to be set.*/ + uint8_t averageNumber; /*!< The average number for hardware average function.*/ + bool coutinuousEnable; /*!< Continuous sample mode enable configuration.*/ + bool averageEnable; /*!< Hardware average enable configuration.*/ } adc_logic_ch_init_config_t; -/*! - * @brief ADC logic channel selection enumeration. - */ +/*! @brief ADC logic channel selection enumeration. */ enum _adc_logic_ch_selection { - adcLogicChA = 0x0, /*!< ADC Logic Channel A.*/ - adcLogicChB = 0x1, /*!< ADC Logic Channel B.*/ - adcLogicChC = 0x2, /*!< ADC Logic Channel C.*/ - adcLogicChD = 0x3, /*!< ADC Logic Channel D.*/ - adcLogicChSW = 0x4 /*!< ADC Logic Channel Software.*/ + adcLogicChA = 0x0, /*!< ADC Logic Channel A.*/ + adcLogicChB = 0x1, /*!< ADC Logic Channel B.*/ + adcLogicChC = 0x2, /*!< ADC Logic Channel C.*/ + adcLogicChD = 0x3, /*!< ADC Logic Channel D.*/ + adcLogicChSW = 0x4, /*!< ADC Logic Channel Software.*/ }; -/*! - * @brief ADC hardware average number enumeration. - */ +/*! @brief ADC hardware average number enumeration. */ enum _adc_average_number { - adcAvgNum4 = 0x0, /*!< ADC Hardware Average Number is set to 4.*/ - adcAvgNum8 = 0x1, /*!< ADC Hardware Average Number is set to 8.*/ - adcAvgNum16 = 0x2, /*!< ADC Hardware Average Number is set to 16.*/ - adcAvgNum32 = 0x3 /*!< ADC Hardware Average Number is set to 32.*/ + adcAvgNum4 = 0x0, /*!< ADC Hardware Average Number is set to 4.*/ + adcAvgNum8 = 0x1, /*!< ADC Hardware Average Number is set to 8.*/ + adcAvgNum16 = 0x2, /*!< ADC Hardware Average Number is set to 16.*/ + adcAvgNum32 = 0x3, /*!< ADC Hardware Average Number is set to 32.*/ }; -/*! - * @brief ADC build-in comparer work mode configuration enumeration. - */ +/*! @brief ADC build-in comparer work mode configuration enumeration. */ enum _adc_compare_mode { - adcCmpModeDisable = 0x0, /*!< ADC build-in comparator is disabled.*/ - adcCmpModeGreaterThanLow = 0x1, /*!< ADC build-in comparator will be triggered when sample value greater than low threshold.*/ - adcCmpModeLessThanLow = 0x2, /*!< ADC build-in comparator will be triggered when sample value less than low threshold.*/ - adcCmpModeInInterval = 0x3, /*!< ADC build-in comparator will be triggered when sample value in interval between low and high threshold.*/ - adcCmpModeGreaterThanHigh = 0x5, /*!< ADC build-in comparator will be triggered when sample value greater than high threshold.*/ - adcCmpModeLessThanHigh = 0x6, /*!< ADC build-in comparator will be triggered when sample value less than high threshold.*/ - adcCmpModeOutOffInterval = 0x7 /*!< ADC build-in comparator will be triggered when sample value out of interval between low and high threshold.*/ + adcCmpModeDisable = 0x0, /*!< ADC build-in comparator is disabled.*/ + adcCmpModeGreaterThanLow = 0x1, /*!< ADC build-in comparator is triggered when sample value greater than low threshold.*/ + adcCmpModeLessThanLow = 0x2, /*!< ADC build-in comparator is triggered when sample value less than low threshold.*/ + adcCmpModeInInterval = 0x3, /*!< ADC build-in comparator is triggered when sample value in interval between low and high threshold.*/ + adcCmpModeGreaterThanHigh = 0x5, /*!< ADC build-in comparator is triggered when sample value greater than high threshold.*/ + adcCmpModeLessThanHigh = 0x6, /*!< ADC build-in comparator is triggered when sample value less than high threshold.*/ + adcCmpModeOutOffInterval = 0x7, /*!< ADC build-in comparator is triggered when sample value out of interval between low and high threshold.*/ }; -/*! - * @brief This enumeration contains the settings for all of the ADC - * interrupt configurations. - */ +/*! @brief This enumeration contains the settings for all of the ADC interrupt configurations. */ enum _adc_interrupt { - adcIntLastFifoDataRead = ADC_INT_EN_LAST_FIFO_DATA_READ_EN_MASK, - adcIntConvertTimeoutChSw = ADC_INT_EN_SW_CH_COV_TO_INT_EN_MASK, - adcIntConvertTimeoutChD = ADC_INT_EN_CHD_COV_TO_INT_EN_MASK, - adcIntConvertTimeoutChC = ADC_INT_EN_CHC_COV_TO_INT_EN_MASK, - adcIntConvertTimeoutChB = ADC_INT_EN_CHB_COV_TO_INT_EN_MASK, - adcIntConvertTimeoutChA = ADC_INT_EN_CHA_COV_TO_INT_EN_MASK, - adcIntConvertChSw = ADC_INT_EN_SW_CH_COV_INT_EN_MASK, - adcIntConvertChD = ADC_INT_EN_CHD_COV_INT_EN_MASK, - adcIntConvertChC = ADC_INT_EN_CHC_COV_INT_EN_MASK, - adcIntConvertChB = ADC_INT_EN_CHB_COV_INT_EN_MASK, - adcIntConvertChA = ADC_INT_EN_CHA_COV_INT_EN_MASK, - adcIntFifoOverrun = ADC_INT_EN_FIFO_OVERRUN_INT_EN_MASK, - adcIntFifoUnderrun = ADC_INT_EN_FIFO_UNDERRUN_INT_EN_MASK, - adcIntDmaReachWatermark = ADC_INT_EN_DMA_REACH_WM_INT_EN_MASK, - adcIntCmpChD = ADC_INT_EN_CHD_CMP_INT_EN_MASK, - adcIntCmpChC = ADC_INT_EN_CHC_CMP_INT_EN_MASK, - adcIntCmpChB = ADC_INT_EN_CHB_CMP_INT_EN_MASK, - adcIntCmpChA = ADC_INT_EN_CHA_CMP_INT_EN_MASK + adcIntLastFifoDataRead = ADC_INT_EN_LAST_FIFO_DATA_READ_EN_MASK, /*!< Last FIFO Data Read Interrupt Enable.*/ + adcIntConvertTimeoutChSw = ADC_INT_EN_SW_CH_COV_TO_INT_EN_MASK, /*!< Software Channel Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChD = ADC_INT_EN_CHD_COV_TO_INT_EN_MASK, /*!< Channel D Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChC = ADC_INT_EN_CHC_COV_TO_INT_EN_MASK, /*!< Channel C Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChB = ADC_INT_EN_CHB_COV_TO_INT_EN_MASK, /*!< Channel B Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChA = ADC_INT_EN_CHA_COV_TO_INT_EN_MASK, /*!< Channel A Conversion Time Out Interrupt Enable.*/ + adcIntConvertChSw = ADC_INT_EN_SW_CH_COV_INT_EN_MASK, /*!< Software Channel Conversion Interrupt Enable.*/ + adcIntConvertChD = ADC_INT_EN_CHD_COV_INT_EN_MASK, /*!< Channel D Conversion Interrupt Enable.*/ + adcIntConvertChC = ADC_INT_EN_CHC_COV_INT_EN_MASK, /*!< Channel C Conversion Interrupt Enable.*/ + adcIntConvertChB = ADC_INT_EN_CHB_COV_INT_EN_MASK, /*!< Channel B Conversion Interrupt Enable.*/ + adcIntConvertChA = ADC_INT_EN_CHA_COV_INT_EN_MASK, /*!< Channel A Conversion Interrupt Enable.*/ + adcIntFifoOverrun = ADC_INT_EN_FIFO_OVERRUN_INT_EN_MASK, /*!< FIFO overrun Interrupt Enable.*/ + adcIntFifoUnderrun = ADC_INT_EN_FIFO_UNDERRUN_INT_EN_MASK, /*!< FIFO underrun Interrupt Enable.*/ + adcIntDmaReachWatermark = ADC_INT_EN_DMA_REACH_WM_INT_EN_MASK, /*!< DMA Reach Watermark Level Interrupt Enable.*/ + adcIntCmpChD = ADC_INT_EN_CHD_CMP_INT_EN_MASK, /*!< Channel D Compare Interrupt Enable.*/ + adcIntCmpChC = ADC_INT_EN_CHC_CMP_INT_EN_MASK, /*!< Channel C Compare Interrupt Enable.*/ + adcIntCmpChB = ADC_INT_EN_CHB_CMP_INT_EN_MASK, /*!< Channel B Compare Interrupt Enable.*/ + adcIntCmpChA = ADC_INT_EN_CHA_CMP_INT_EN_MASK, /*!< Channel A Compare Interrupt Enable.*/ }; -/*! - * @brief Flag for ADC interrupt/DMA status check or polling status. - */ +/*! @brief Flag for ADC interrupt/DMA status check or polling status. */ enum _adc_status_flag { - adcStatusLastFifoDataRead = ADC_INT_STATUS_LAST_FIFO_DATA_READ_MASK, - adcStatusConvertTimeoutChSw = ADC_INT_STATUS_SW_CH_COV_TO_MASK, - adcStatusConvertTimeoutChD = ADC_INT_STATUS_CHD_COV_TO_MASK, - adcStatusConvertTimeoutChC = ADC_INT_STATUS_CHC_COV_TO_MASK, - adcStatusConvertTimeoutChB = ADC_INT_STATUS_CHB_COV_TO_MASK, - adcStatusConvertTimeoutChA = ADC_INT_STATUS_CHA_COV_TO_MASK, - adcStatusConvertChSw = ADC_INT_STATUS_SW_CH_COV_MASK, - adcStatusConvertChD = ADC_INT_STATUS_CHD_COV_MASK, - adcStatusConvertChC = ADC_INT_STATUS_CHC_COV_MASK, - adcStatusConvertChB = ADC_INT_STATUS_CHB_COV_MASK, - adcStatusConvertChA = ADC_INT_STATUS_CHA_COV_MASK, - adcStatusFifoOverrun = ADC_INT_STATUS_FIFO_OVERRUN_MASK, - adcStatusFifoUnderrun = ADC_INT_STATUS_FIFO_UNDERRUN_MASK, - adcStatusDmaReachWatermark = ADC_INT_STATUS_DMA_REACH_WM_MASK, - adcStatusCmpChD = ADC_INT_STATUS_CHD_CMP_MASK, - adcStatusCmpChC = ADC_INT_STATUS_CHC_CMP_MASK, - adcStatusCmpChB = ADC_INT_STATUS_CHB_CMP_MASK, - adcStatusCmpChA = ADC_INT_STATUS_CHA_CMP_MASK + adcStatusLastFifoDataRead = ADC_INT_STATUS_LAST_FIFO_DATA_READ_MASK, /*!< Last FIFO Data Read status flag.*/ + adcStatusConvertTimeoutChSw = ADC_INT_STATUS_SW_CH_COV_TO_MASK, /*!< Software Channel Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChD = ADC_INT_STATUS_CHD_COV_TO_MASK, /*!< Channel D Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChC = ADC_INT_STATUS_CHC_COV_TO_MASK, /*!< Channel C Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChB = ADC_INT_STATUS_CHB_COV_TO_MASK, /*!< Channel B Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChA = ADC_INT_STATUS_CHA_COV_TO_MASK, /*!< Channel A Conversion Time Out status flag.*/ + adcStatusConvertChSw = ADC_INT_STATUS_SW_CH_COV_MASK, /*!< Software Channel Conversion status flag.*/ + adcStatusConvertChD = ADC_INT_STATUS_CHD_COV_MASK, /*!< Channel D Conversion status flag.*/ + adcStatusConvertChC = ADC_INT_STATUS_CHC_COV_MASK, /*!< Channel C Conversion status flag.*/ + adcStatusConvertChB = ADC_INT_STATUS_CHB_COV_MASK, /*!< Channel B Conversion status flag.*/ + adcStatusConvertChA = ADC_INT_STATUS_CHA_COV_MASK, /*!< Channel A Conversion status flag.*/ + adcStatusFifoOverrun = ADC_INT_STATUS_FIFO_OVERRUN_MASK, /*!< FIFO Overrun status flag.*/ + adcStatusFifoUnderrun = ADC_INT_STATUS_FIFO_UNDERRUN_MASK, /*!< FIFO Underrun status flag.*/ + adcStatusDmaReachWatermark = ADC_INT_STATUS_DMA_REACH_WM_MASK, /*!< DMA Reach Watermark Level status flag.*/ + adcStatusCmpChD = ADC_INT_STATUS_CHD_CMP_MASK, /*!< Channel D Compare status flag.*/ + adcStatusCmpChC = ADC_INT_STATUS_CHC_CMP_MASK, /*!< Channel C Compare status flag.*/ + adcStatusCmpChB = ADC_INT_STATUS_CHB_CMP_MASK, /*!< Channel B Compare status flag.*/ + adcStatusCmpChA = ADC_INT_STATUS_CHA_CMP_MASK, /*!< Channel A Compare status flag.*/ }; /******************************************************************************* @@ -173,7 +158,7 @@ extern "C" { * @param base ADC base pointer. * @param initConfig ADC initialize structure. */ -void ADC_Init(ADC_Type* base, adc_init_config_t* initConfig); +void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig); /*! * @brief This function reset ADC module register content to its default value. @@ -184,7 +169,7 @@ void ADC_Deinit(ADC_Type* base); /*! * @brief This function Enable ADC module build-in Level Shifter. - * For iMX7D, Level Shifter should always be enabled. + * For i.MX 7Dual, Level Shifter should always be enabled. * User can disable Level Shifter to save power. * * @param base ADC base pointer. @@ -224,7 +209,8 @@ void ADC_SetSampleRate(ADC_Type* base, uint32_t sampleRate); * @brief This function is used to stop all digital part power. * * @param base ADC base pointer. - * @param clockDown - true: Clock down. + * @param clockDown Stop all ADC digital part or not. + * - true: Clock down. * - false: Clock running. */ void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown); @@ -233,7 +219,8 @@ void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown); * @brief This function is used to power down ADC analogue core. * Before entering into stop-mode, power down ADC analogue core first. * @param base ADC base pointer. - * @param powerDown - true: Power down the ADC analogue core. + * @param powerDown Power down ADC analogue core or not. + * - true: Power down the ADC analogue core. * - false: Do not power down the ADC analogue core. */ void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown); @@ -249,16 +236,16 @@ void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown); * @brief Initialize ADC Logic channel with initialize structure. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). * @param chInitConfig ADC logic channel initialize structure. */ -void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, adc_logic_ch_init_config_t* chInitConfig); +void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfig); /*! * @brief Reset target ADC logic channel registers to default value. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). */ void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh); @@ -266,7 +253,7 @@ void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh); * @brief Select input channel for target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). * @param inputCh Input channel selection for target logic channel(vary from 0 to 15). */ void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh); @@ -275,7 +262,7 @@ void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh); * @brief Set ADC conversion rate of target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). * @param convertRate ADC conversion rate in Hz. */ void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate); @@ -284,9 +271,10 @@ void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate); * @brief Set work state of hardware average feature of target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). - * @param enable - true: Enable hardware average. - * - faluse: Disable hardware average. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable hardware average + * - true: Enable hardware average of given logic channel. + * - false: Disable hardware average of given logic channel. */ void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable); @@ -294,8 +282,8 @@ void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable); * @brief Set hardware average number of target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). - * @param avgNum hardware average number(should select from _adc_average_number enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param avgNum hardware average number(should select from @ref _adc_average_number enumeration). */ void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum); @@ -310,9 +298,10 @@ void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum); * @brief Set continuous convert work mode of target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). - * @param enable - true: Enable continuous convert. - * - false: Disable continuous convert. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable continuous convertion. + * - true: Enable continuous convertion. + * - false: Disable continuous convertion. */ void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable); @@ -320,15 +309,24 @@ void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable); * @brief Trigger single time convert on target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). */ void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh); /*! + * @brief Stop current convert on target logic channel. + * For logic channel A ~ D, current conversion will stop immediately. + * For Software channel, this function will be waited until current conversion finished. + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +void ADC_StopConvert(ADC_Type* base, uint8_t logicCh); + +/*! * @brief Get 12-bit length right aligned convert result. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). * @return convert result on target logic channel. */ uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh); @@ -344,8 +342,8 @@ uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh); * @brief Set the work mode of ADC module build-in comparer on target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). - * @param cmpMode Comparer work mode selected from _adc_compare_mode enumeration. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param cmpMode Comparer work mode selected from @ref _adc_compare_mode enumeration. */ void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode); @@ -353,7 +351,7 @@ void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode); * @brief Set ADC module build-in comparer high threshold on target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). * @param threshold Comparer threshold in 12-bit unsigned int formate. */ void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold); @@ -362,7 +360,7 @@ void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold); * @brief Set ADC module build-in comparer low threshold on target logic channel. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). * @param threshold Comparer threshold in 12-bit unsigned int formate. */ void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold); @@ -372,9 +370,10 @@ void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold); * This feature can disable continuous conversion when CMP condition matched. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). - * @param enable - true: Enable Auto Disable feature. - * - false: Disable Auto Disable feature. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable Auto Disable feature. + * - true: Enable Auto Disable feature. + * - false: Disable Auto Disable feature. */ void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable); @@ -389,8 +388,10 @@ void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable); * @brief Enables or disables ADC interrupt requests. * * @param base ADC base pointer. - * @param intSource ADC interrupt sources to config. - * @param enable Pass true to enable interrupt, false to disable. + * @param intSource ADC interrupt sources to configuration. + * @param enable Enable/Disable given ADC interrupt. + * - true: Enable given ADC interrupt. + * - false: Disable given ADC interrupt. */ void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable); @@ -398,8 +399,10 @@ void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable); * @brief Enables or disables ADC interrupt flag when interrupt condition met. * * @param base ADC base pointer. - * @param intSignal ADC interrupt signals to config. - * @param intSignal Should be select from _adc_interrupt enumeration. + * @param intSignal ADC interrupt signals to configuration (see @ref _adc_interrupt enumeration). + * @param enable Enable/Disable given ADC interrupt flags. + * - true: Enable given ADC interrupt flags. + * - false: Disable given ADC interrupt flags. */ void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable); @@ -407,7 +410,7 @@ void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable); * @brief Gets the ADC status flag state. * * @param base ADC base pointer. - * @param flags ADC status flag mask defined in _adc_status_flag enumeration. + * @param flags ADC status flag mask defined in @ref _adc_status_flag enumeration. * @return ADC status, each bit represents one status flag */ static inline uint32_t ADC_GetStatusFlag(ADC_Type* base, uint32_t flags) @@ -419,7 +422,7 @@ static inline uint32_t ADC_GetStatusFlag(ADC_Type* base, uint32_t flags) * @brief Clear one or more ADC status flag state. * * @param base ADC base pointer. - * @param flags ADC status flag mask defined in _adc_status_flag enumeration. + * @param flags ADC status flag mask defined in @ref _adc_status_flag enumeration. */ static inline void ADC_ClearStatusFlag(ADC_Type* base, uint32_t flags) { @@ -437,8 +440,9 @@ static inline void ADC_ClearStatusFlag(ADC_Type* base, uint32_t flags) * @brief Set the reset state of ADC internal DMA part. * * @param base ADC base pointer. - * @param active - true :Reset the DMA and DMA FIFO return to its reset value. - * - false :de-active DMA reset. + * @param active Reset DMA & DMA FIFO or not. + * - true: Reset the DMA and DMA FIFO return to its reset value. + * - false: Do not reset DMA and DMA FIFO. */ void ADC_SetDmaReset(ADC_Type* base, bool active); @@ -446,8 +450,9 @@ void ADC_SetDmaReset(ADC_Type* base, bool active); * @brief Set the work mode of ADC DMA part. * * @param base ADC base pointer. - * @param enable - true :Enable DMA, the data in DMA FIFO should move by SDMA. - * - false :Disable DMA, the data in DMA FIFO can only move by CPU. + * @param enable Enable/Disable ADC DMA part. + * - true: Enable DMA, the data in DMA FIFO should move by SDMA. + * - false: Disable DMA, the data in DMA FIFO can only move by CPU. */ void ADC_SetDmaCmd(ADC_Type* base, bool enable); @@ -455,16 +460,17 @@ void ADC_SetDmaCmd(ADC_Type* base, bool enable); * @brief Set the work mode of ADC DMA FIFO part. * * @param base ADC base pointer. - * @param enable - true :Enable DMA FIFO. - * - false :Disable DMA FIFO. + * @param enable Enable/Disable DMA FIFO. + * - true: Enable DMA FIFO. + * - false: Disable DMA FIFO. */ void ADC_SetDmaFifoCmd(ADC_Type* base, bool enable); /*! - * @brief Select the logic channel that will use DMA transfer. + * @brief Select the logic channel that uses the DMA transfer. * * @param base ADC base pointer. - * @param logicCh ADC module logic channel selection(refer to _adc_logic_ch_selection enumeration). + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). */ static inline void ADC_SetDmaCh(ADC_Type* base, uint32_t logicCh) { @@ -504,8 +510,8 @@ static inline uint32_t ADC_GetFifoData(ADC_Type* base) * @brief Get the DMA FIFO full status * * @param base ADC base pointer. - * @return - true: DMA FIFO full - * - false: DMA FIFO not full + * @retval true: DMA FIFO full. + * @retval false: DMA FIFO not full. */ static inline bool ADC_IsFifoFull(ADC_Type* base) { @@ -516,8 +522,8 @@ static inline bool ADC_IsFifoFull(ADC_Type* base) * @brief Get the DMA FIFO empty status * * @param base ADC base pointer. - * @return - true: DMA FIFO empty - * - false: DMA FIFO not empty + * @retval true: DMA FIFO is empty. + * @retval false: DMA FIFO is not empty. */ static inline bool ADC_IsFifoEmpty(ADC_Type* base) { diff --git a/platform/drivers/inc/ccm_analog_imx7d.h b/platform/drivers/inc/ccm_analog_imx7d.h index 675ae1d..0b5f2a1 100644 --- a/platform/drivers/inc/ccm_analog_imx7d.h +++ b/platform/drivers/inc/ccm_analog_imx7d.h @@ -56,108 +56,104 @@ * @brief PLL control names for PLL power/bypass/lock operations. * * These constants define the PLL control names for PLL power/bypass/lock operations.\n - * 0:15 : REG offset to CCM_ANALOG_BASE in bytes\n - * 16:20 : Powerdown bit shift + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Power down bit shift. */ -enum _ccm_analog_pll_control { - ccmAnalogPllArmControl = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT), - ccmAnalogPllDdrControl = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT), - ccmAnalogPll480Control = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_POWERDOWN_SHIFT), - ccmAnalogPllEnetControl = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT), - ccmAnalogPllAudioControl = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT), - ccmAnalogPllVideoControl = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT) +enum _ccm_analog_pll_control +{ + ccmAnalogPllArmControl = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT), /*!< CCM Analog ARM PLL Control.*/ + ccmAnalogPllDdrControl = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT), /*!< CCM Analog DDR PLL Control.*/ + ccmAnalogPll480Control = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_POWERDOWN_SHIFT), /*!< CCM Analog 480M PLL Control.*/ + ccmAnalogPllEnetControl = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT), /*!< CCM Analog Ethernet PLL Control.*/ + ccmAnalogPllAudioControl = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT), /*!< CCM Analog AUDIO PLL Control.*/ + ccmAnalogPllVideoControl = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT), /*!< CCM Analog VIDEO PLL Control.*/ }; /*! * @brief PLL clock names for clock enable/disable settings. * * These constants define the PLL clock names for PLL clock enable/disable operations.\n - * 0:15 : REG offset to CCM_ANALOG_BASE in bytes\n - * 16:20 : Clock enable bit shift + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock enable bit shift. */ -enum _ccm_analog_pll_clock { - ccmAnalogPllArmClock = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT), - - ccmAnalogPllDdrClock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT), - ccmAnalogPllDdrDiv2Clock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT), - - ccmAnalogPll480Clock = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT), - - ccmAnalogPllEnet25MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT), - ccmAnalogPllEnet40MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT), - ccmAnalogPllEnet50MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT), - ccmAnalogPllEnet100MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT), - ccmAnalogPllEnet125MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT), - ccmAnalogPllEnet250MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT), - ccmAnalogPllEnet500MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT), - - ccmAnalogPllAudioClock = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT), - ccmAnalogPllVideoClock = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT) +enum _ccm_analog_pll_clock +{ + ccmAnalogPllArmClock = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT), /*!< CCM Analog ARM PLL Clock.*/ + ccmAnalogPllDdrClock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT), /*!< CCM Analog DDR PLL Clock.*/ + ccmAnalogPllDdrDiv2Clock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT), /*!< CCM Analog DDR PLL divided by 2 Clock.*/ + ccmAnalogPll480Clock = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT), /*!< CCM Analog 480M PLL Clock.*/ + ccmAnalogPllEnet25MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT), /*!< CCM Analog Ethernet 25M PLL Clock.*/ + ccmAnalogPllEnet40MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT), /*!< CCM Analog Ethernet 40M PLL Clock.*/ + ccmAnalogPllEnet50MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT), /*!< CCM Analog Ethernet 50M PLL Clock.*/ + ccmAnalogPllEnet100MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT), /*!< CCM Analog Ethernet 100M PLL Clock.*/ + ccmAnalogPllEnet125MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT), /*!< CCM Analog Ethernet 125M PLL Clock.*/ + ccmAnalogPllEnet250MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT), /*!< CCM Analog Ethernet 250M PLL Clock.*/ + ccmAnalogPllEnet500MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT), /*!< CCM Analog Ethernet 500M PLL Clock.*/ + ccmAnalogPllAudioClock = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT), /*!< CCM Analog AUDIO PLL Clock.*/ + ccmAnalogPllVideoClock = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT), /*!< CCM Analog VIDEO PLL Clock.*/ }; /*! * @brief PFD gate names for clock gate settings, clock source is system PLL(PLL_480) * * These constants define the PFD gate names for PFD clock enable/disable operations.\n - * 0:15 : REG offset to CCM_ANALOG_BASE in bytes\n - * 16:20 : Clock gate bit shift + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock gate bit shift. */ -enum _ccm_analog_pfd_clkgate { - ccmAnalogMainDiv1ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT), - ccmAnalogMainDiv2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT), - ccmAnalogMainDiv4ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT), - - ccmAnalogPfd0Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT), - ccmAnalogPfd1Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT), - ccmAnalogPfd2Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT), - - ccmAnalogPfd0Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT), - ccmAnalogPfd1Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT), - ccmAnalogPfd2Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT), - ccmAnalogPfd3Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT), - - ccmAnalogPfd4Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT), - ccmAnalogPfd5Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT), - ccmAnalogPfd6Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT), - ccmAnalogPfd7Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT) +enum _ccm_analog_pfd_clkgate +{ + ccmAnalogMainDiv1ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV1 Clock Gate.*/ + ccmAnalogMainDiv2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV2 Clock Gate.*/ + ccmAnalogMainDiv4ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV4 Clock Gate.*/ + ccmAnalogPfd0Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD0 DIV2 Clock Gate.*/ + ccmAnalogPfd1Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD1 DIV2 Clock Gate.*/ + ccmAnalogPfd2Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD2 DIV2 Clock Gate.*/ + ccmAnalogPfd0Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD0 DIV1 Clock Gate.*/ + ccmAnalogPfd1Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD1 DIV1 Clock Gate.*/ + ccmAnalogPfd2Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD2 DIV1 Clock Gate.*/ + ccmAnalogPfd3Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD3 DIV1 Clock Gate.*/ + ccmAnalogPfd4Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD4 DIV1 Clock Gate.*/ + ccmAnalogPfd5Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD5 DIV1 Clock Gate.*/ + ccmAnalogPfd6Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD6 DIV1 Clock Gate.*/ + ccmAnalogPfd7Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD7 DIV1 Clock Gate.*/ }; /*! * @brief PFD fraction names for clock fractional divider operations * * These constants define the PFD fraction names for PFD fractional divider operations.\n - * 0:15 : REG offset to CCM_ANALOG_BASE in bytes\n - * 16:20 : Fraction bits shift + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Fraction bits shift. */ -enum _ccm_analog_pfd_frac { - ccmAnalogPfd0Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT), - ccmAnalogPfd1Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT), - ccmAnalogPfd2Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT), - ccmAnalogPfd3Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT), - - ccmAnalogPfd4Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT), - ccmAnalogPfd5Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT), - ccmAnalogPfd6Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT), - ccmAnalogPfd7Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT) +enum _ccm_analog_pfd_frac +{ + ccmAnalogPfd0Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT), /*!< CCM Analog 480A PFD0 fractional divider.*/ + ccmAnalogPfd1Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT), /*!< CCM Analog 480A PFD1 fractional divider.*/ + ccmAnalogPfd2Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT), /*!< CCM Analog 480A PFD2 fractional divider.*/ + ccmAnalogPfd3Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT), /*!< CCM Analog 480A PFD3 fractional divider.*/ + ccmAnalogPfd4Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT), /*!< CCM Analog 480B PFD4 fractional divider.*/ + ccmAnalogPfd5Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT), /*!< CCM Analog 480B PFD5 fractional divider.*/ + ccmAnalogPfd6Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT), /*!< CCM Analog 480B PFD6 fractional divider.*/ + ccmAnalogPfd7Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT), /*!< CCM Analog 480B PFD7 fractional divider.*/ }; /*! * @brief PFD stable names for clock stable query * * These constants define the PFD stable names for clock stable query.\n - * 0:15 : REG offset to CCM_ANALOG_BASE in bytes\n - * 16:20 : Stable bit shift + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Stable bit shift. */ -enum _ccm_analog_pfd_stable { - ccmAnalogPfd0Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT), - ccmAnalogPfd1Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT), - ccmAnalogPfd2Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT), - ccmAnalogPfd3Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT), - - ccmAnalogPfd4Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT), - ccmAnalogPfd5Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT), - ccmAnalogPfd6Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT), - ccmAnalogPfd7Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT) +enum _ccm_analog_pfd_stable +{ + ccmAnalogPfd0Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT), /*!< CCM Analog 480A PFD0 clock stable query.*/ + ccmAnalogPfd1Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT), /*!< CCM Analog 480A PFD1 clock stable query.*/ + ccmAnalogPfd2Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT), /*!< CCM Analog 480A PFD2 clock stable query.*/ + ccmAnalogPfd3Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT), /*!< CCM Analog 480A PFD3 clock stable query.*/ + ccmAnalogPfd4Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT), /*!< CCM Analog 480B PFD4 clock stable query.*/ + ccmAnalogPfd5Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT), /*!< CCM Analog 480B PFD5 clock stable query.*/ + ccmAnalogPfd6Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT), /*!< CCM Analog 480B PFD6 clock stable query.*/ + ccmAnalogPfd7Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT), /*!< CCM Analog 480B PFD7 clock stable query.*/ }; /******************************************************************************* @@ -169,7 +165,7 @@ extern "C" { #endif /*! - * @name CCM Analog PLL Operations + * @name CCM Analog PLL Operatoin Functions * @{ */ @@ -177,7 +173,7 @@ extern "C" { * @brief Power up PLL * * @param base CCM_ANALOG base pointer. - * @param pllControl PLL control name (see _ccm_analog_pll_control enumeration) + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) */ static inline void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl) { @@ -188,7 +184,7 @@ static inline void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllCon * @brief Power down PLL * * @param base CCM_ANALOG base pointer. - * @param pllControl PLL control name (see _ccm_analog_pll_control enumeration) + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) */ static inline void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl) { @@ -199,8 +195,10 @@ static inline void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllC * @brief PLL bypass setting * * @param base CCM_ANALOG base pointer. - * @param pllControl PLL control name (see _ccm_analog_pll_control enumeration) - * @param bypass Bypass the PLL (true: bypass, false: not bypass) + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false: Do not bypass the PLL. */ static inline void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass) { @@ -214,8 +212,10 @@ static inline void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllC * @brief Check if PLL is bypassed * * @param base CCM_ANALOG base pointer. - * @param pllControl PLL control name (see _ccm_analog_pll_control enumeration) - * @return PLL bypass status (true: bypassed, false: not bypassed) + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. */ static inline bool CCM_ANALOG_IsPllBypassed(CCM_ANALOG_Type * base, uint32_t pllControl) { @@ -226,8 +226,10 @@ static inline bool CCM_ANALOG_IsPllBypassed(CCM_ANALOG_Type * base, uint32_t pll * @brief Check if PLL clock is locked * * @param base CCM_ANALOG base pointer. - * @param pllControl PLL control name (see _ccm_analog_pll_control enumeration) - * @return PLL lock status (true: locked, false: not locked) + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL lock status. + * - true: The PLL clock is locked. + * - false: The PLL clock is not locked. */ static inline bool CCM_ANALOG_IsPllLocked(CCM_ANALOG_Type * base, uint32_t pllControl) { @@ -238,7 +240,7 @@ static inline bool CCM_ANALOG_IsPllLocked(CCM_ANALOG_Type * base, uint32_t pllCo * @brief Enable PLL clock * * @param base CCM_ANALOG base pointer. - * @param pllClock PLL clock name (see _ccm_analog_pll_clock enumeration) + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) */ static inline void CCM_ANALOG_EnablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) { @@ -249,7 +251,7 @@ static inline void CCM_ANALOG_EnablePllClock(CCM_ANALOG_Type * base, uint32_t pl * @brief Disable PLL clock * * @param base CCM_ANALOG base pointer. - * @param pllClock PLL clock name (see _ccm_analog_pll_clock enumeration) + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) */ static inline void CCM_ANALOG_DisablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) { @@ -257,6 +259,14 @@ static inline void CCM_ANALOG_DisablePllClock(CCM_ANALOG_Type * base, uint32_t p } /*! + * @brief Get ARM PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return ARM PLL clock frequency in HZ + */ +uint32_t CCM_ANALOG_GetArmPllFreq(CCM_ANALOG_Type * base); + +/*! * @brief Get System PLL (PLL_480) clock frequency * * @param base CCM_ANALOG base pointer. @@ -264,10 +274,42 @@ static inline void CCM_ANALOG_DisablePllClock(CCM_ANALOG_Type * base, uint32_t p */ uint32_t CCM_ANALOG_GetSysPllFreq(CCM_ANALOG_Type * base); +/*! + * @brief Get DDR PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return DDR PLL clock frequency in HZ + */ +uint32_t CCM_ANALOG_GetDdrPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get ENET PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return ENET PLL clock frequency in HZ + */ +uint32_t CCM_ANALOG_GetEnetPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get Audio PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return Audio PLL clock frequency in HZ + */ +uint32_t CCM_ANALOG_GetAudioPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get Video PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return Video PLL clock frequency in HZ + */ +uint32_t CCM_ANALOG_GetVideoPllFreq(CCM_ANALOG_Type * base); + /*@}*/ /*! - * @name CCM Analog PFD Operations + * @name CCM Analog PFD Operatoin Functions * @{ */ @@ -275,7 +317,7 @@ uint32_t CCM_ANALOG_GetSysPllFreq(CCM_ANALOG_Type * base); * @brief Enable PFD clock * * @param base CCM_ANALOG base pointer. - * @param pfdClkGate PFD clock gate (see _ccm_analog_pfd_clkgate enumeration) + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) */ static inline void CCM_ANALOG_EnablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) { @@ -286,7 +328,7 @@ static inline void CCM_ANALOG_EnablePfdClock(CCM_ANALOG_Type * base, uint32_t pf * @brief Disable PFD clock * * @param base CCM_ANALOG base pointer. - * @param pfdClkGate PFD clock gate (see _ccm_analog_pfd_clkgate enumeration) + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) */ static inline void CCM_ANALOG_DisablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) { @@ -297,8 +339,10 @@ static inline void CCM_ANALOG_DisablePfdClock(CCM_ANALOG_Type * base, uint32_t p * @brief Check if PFD clock is stable * * @param base CCM_ANALOG base pointer. - * @param pfdStable PFD stable identifier (see _ccm_analog_pfd_stable enumeration) - * @return PFD clock stable status (true: stable, false: not stable) + * @param pfdStable PFD stable identifier (see @ref _ccm_analog_pfd_stable enumeration) + * @return PFD clock stable status. + * - true: The PFD clock is stable. + * - false: The PFD clock is not stable. */ static inline bool CCM_ANALOG_IsPfdStable(CCM_ANALOG_Type * base, uint32_t pfdStable) { @@ -309,7 +353,7 @@ static inline bool CCM_ANALOG_IsPfdStable(CCM_ANALOG_Type * base, uint32_t pfdSt * @brief Set PFD clock fraction * * @param base CCM_ANALOG base pointer. - * @param pfdFrac PFD clock fraction (see _ccm_analog_pfd_frac enumeration) + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) * @param value PFD clock fraction value */ static inline void CCM_ANALOG_SetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac, uint32_t value) @@ -323,7 +367,7 @@ static inline void CCM_ANALOG_SetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFra * @brief Get PFD clock fraction * * @param base CCM_ANALOG base pointer. - * @param pfdFrac PFD clock fraction (see _ccm_analog_pfd_frac enumeration) + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) * @return PFD clock fraction value */ static inline uint32_t CCM_ANALOG_GetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac) @@ -335,7 +379,7 @@ static inline uint32_t CCM_ANALOG_GetPfdFrac(CCM_ANALOG_Type * base, uint32_t pf * @brief Get PFD clock frequency * * @param base CCM_ANALOG base pointer. - * @param pfdFrac PFD clock fraction (see _ccm_analog_pfd_frac enumeration) + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) * @return PFD clock frequency in HZ */ uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac); diff --git a/platform/drivers/inc/ccm_imx7d.h b/platform/drivers/inc/ccm_imx7d.h index d73db7d..cc4d88f 100644 --- a/platform/drivers/inc/ccm_imx7d.h +++ b/platform/drivers/inc/ccm_imx7d.h @@ -45,310 +45,290 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)root + off))) -#define CCM_REG(root) CCM_REG_OFF(root, 0) -#define CCM_REG_SET(root) CCM_REG_OFF(root, 4) -#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8) +#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)root + off))) +#define CCM_REG(root) CCM_REG_OFF(root, 0) +#define CCM_REG_SET(root) CCM_REG_OFF(root, 4) +#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8) -/*! - * @brief Root control names for root clock setting. - */ -enum _ccm_root_control { - ccmRootM4 = (uint32_t)(&CCM_TARGET_ROOT1), - ccmRootAxi = (uint32_t)(&CCM_TARGET_ROOT16), - ccmRootAhb = (uint32_t)(&CCM_TARGET_ROOT32), - ccmRootIpg = (uint32_t)(&CCM_TARGET_ROOT33), - ccmRootQspi = (uint32_t)(&CCM_TARGET_ROOT85), - ccmRootCan1 = (uint32_t)(&CCM_TARGET_ROOT89), - ccmRootCan2 = (uint32_t)(&CCM_TARGET_ROOT90), - ccmRootI2c1 = (uint32_t)(&CCM_TARGET_ROOT91), - ccmRootI2c2 = (uint32_t)(&CCM_TARGET_ROOT92), - ccmRootI2c3 = (uint32_t)(&CCM_TARGET_ROOT93), - ccmRootI2c4 = (uint32_t)(&CCM_TARGET_ROOT94), - ccmRootUart1 = (uint32_t)(&CCM_TARGET_ROOT95), - ccmRootUart2 = (uint32_t)(&CCM_TARGET_ROOT96), - ccmRootUart3 = (uint32_t)(&CCM_TARGET_ROOT97), - ccmRootUart4 = (uint32_t)(&CCM_TARGET_ROOT98), - ccmRootUart5 = (uint32_t)(&CCM_TARGET_ROOT99), - ccmRootUart6 = (uint32_t)(&CCM_TARGET_ROOT100), - ccmRootUart7 = (uint32_t)(&CCM_TARGET_ROOT101), - ccmRootEcspi1 = (uint32_t)(&CCM_TARGET_ROOT102), - ccmRootEcspi2 = (uint32_t)(&CCM_TARGET_ROOT103), - ccmRootEcspi3 = (uint32_t)(&CCM_TARGET_ROOT104), - ccmRootEcspi4 = (uint32_t)(&CCM_TARGET_ROOT105), - ccmRootFtm1 = (uint32_t)(&CCM_TARGET_ROOT110), - ccmRootFtm2 = (uint32_t)(&CCM_TARGET_ROOT111), - ccmRootGpt1 = (uint32_t)(&CCM_TARGET_ROOT114), - ccmRootGpt2 = (uint32_t)(&CCM_TARGET_ROOT115), - ccmRootGpt3 = (uint32_t)(&CCM_TARGET_ROOT116), - ccmRootGpt4 = (uint32_t)(&CCM_TARGET_ROOT117), - ccmRootWdog = (uint32_t)(&CCM_TARGET_ROOT119) +/*! @brief Root control names for root clock setting. */ +enum _ccm_root_control +{ + ccmRootM4 = (uint32_t)(&CCM_TARGET_ROOT1), /*!< M4 Clock control name.*/ + ccmRootAxi = (uint32_t)(&CCM_TARGET_ROOT16), /*!< AXI Clock control name.*/ + ccmRootAhb = (uint32_t)(&CCM_TARGET_ROOT32), /*!< AHB Clock control name.*/ + ccmRootIpg = (uint32_t)(&CCM_TARGET_ROOT33), /*!< IPG Clock control name.*/ + ccmRootQspi = (uint32_t)(&CCM_TARGET_ROOT85), /*!< QSPI Clock control name.*/ + ccmRootCan1 = (uint32_t)(&CCM_TARGET_ROOT89), /*!< CAN1 Clock control name.*/ + ccmRootCan2 = (uint32_t)(&CCM_TARGET_ROOT90), /*!< CAN2 Clock control name.*/ + ccmRootI2c1 = (uint32_t)(&CCM_TARGET_ROOT91), /*!< I2C1 Clock control name.*/ + ccmRootI2c2 = (uint32_t)(&CCM_TARGET_ROOT92), /*!< I2C2 Clock control name.*/ + ccmRootI2c3 = (uint32_t)(&CCM_TARGET_ROOT93), /*!< I2C3 Clock control name.*/ + ccmRootI2c4 = (uint32_t)(&CCM_TARGET_ROOT94), /*!< I2C4 Clock control name.*/ + ccmRootUart1 = (uint32_t)(&CCM_TARGET_ROOT95), /*!< UART1 Clock control name.*/ + ccmRootUart2 = (uint32_t)(&CCM_TARGET_ROOT96), /*!< UART2 Clock control name.*/ + ccmRootUart3 = (uint32_t)(&CCM_TARGET_ROOT97), /*!< UART3 Clock control name.*/ + ccmRootUart4 = (uint32_t)(&CCM_TARGET_ROOT98), /*!< UART4 Clock control name.*/ + ccmRootUart5 = (uint32_t)(&CCM_TARGET_ROOT99), /*!< UART5 Clock control name.*/ + ccmRootUart6 = (uint32_t)(&CCM_TARGET_ROOT100), /*!< UART6 Clock control name.*/ + ccmRootUart7 = (uint32_t)(&CCM_TARGET_ROOT101), /*!< UART7 Clock control name.*/ + ccmRootEcspi1 = (uint32_t)(&CCM_TARGET_ROOT102), /*!< ECSPI1 Clock control name.*/ + ccmRootEcspi2 = (uint32_t)(&CCM_TARGET_ROOT103), /*!< ECSPI2 Clock control name.*/ + ccmRootEcspi3 = (uint32_t)(&CCM_TARGET_ROOT104), /*!< ECSPI3 Clock control name.*/ + ccmRootEcspi4 = (uint32_t)(&CCM_TARGET_ROOT105), /*!< ECSPI4 Clock control name.*/ + ccmRootFtm1 = (uint32_t)(&CCM_TARGET_ROOT110), /*!< FTM1 Clock control name.*/ + ccmRootFtm2 = (uint32_t)(&CCM_TARGET_ROOT111), /*!< FTM2 Clock control name.*/ + ccmRootGpt1 = (uint32_t)(&CCM_TARGET_ROOT114), /*!< GPT1 Clock control name.*/ + ccmRootGpt2 = (uint32_t)(&CCM_TARGET_ROOT115), /*!< GPT2 Clock control name.*/ + ccmRootGpt3 = (uint32_t)(&CCM_TARGET_ROOT116), /*!< GPT3 Clock control name.*/ + ccmRootGpt4 = (uint32_t)(&CCM_TARGET_ROOT117), /*!< GPT4 Clock control name.*/ + ccmRootWdog = (uint32_t)(&CCM_TARGET_ROOT119), /*!< WDOG Clock control name.*/ }; -/*! - * @brief Clock source enumeration for M4 core. - */ -enum _ccm_rootmux_m4 { - ccmRootmuxM4Osc24m = 0U, - ccmRootmuxM4SysPllDiv2 = 1U, - ccmRootmuxM4EnetPll250m = 2U, - ccmRootmuxM4SysPllPfd2 = 3U, - ccmRootmuxM4DdrPllDiv2 = 4U, - ccmRootmuxM4AudioPll = 5U, - ccmRootmuxM4VideoPll = 6U, - ccmRootmuxM4UsbPll = 7U +/*! @brief Clock source enumeration for ARM Cortex-M4 core. */ +enum _ccm_rootmux_m4 +{ + ccmRootmuxM4Osc24m = 0U, /*!< M4 Clock from OSC 24M.*/ + ccmRootmuxM4SysPllDiv2 = 1U, /*!< M4 Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxM4EnetPll250m = 2U, /*!< M4 Clock from Ethernet PLL 250M.*/ + ccmRootmuxM4SysPllPfd2 = 3U, /*!< M4 Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxM4DdrPllDiv2 = 4U, /*!< M4 Clock from DDR PLL divided by 2.*/ + ccmRootmuxM4AudioPll = 5U, /*!< M4 Clock from AUDIO PLL.*/ + ccmRootmuxM4VideoPll = 6U, /*!< M4 Clock from VIDEO PLL.*/ + ccmRootmuxM4UsbPll = 7U, /*!< M4 Clock from USB PLL.*/ }; -/*! - * @brief Clock source enumeration for AXI bus. - */ -enum _ccm_rootmux_axi { - ccmRootmuxAxiOsc24m = 0U, - ccmRootmuxAxiSysPllPfd1 = 1U, - ccmRootmuxAxiDdrPllDiv2 = 2U, - ccmRootmuxAxiEnetPll250m = 3U, - ccmRootmuxAxiSysPllPfd5 = 4U, - ccmRootmuxAxiAudioPll = 5U, - ccmRootmuxAxiVideoPll = 6U, - ccmRootmuxAxiSysPllPfd7 = 7U +/*! @brief Clock source enumeration for AXI bus. */ +enum _ccm_rootmux_axi +{ + ccmRootmuxAxiOsc24m = 0U, /*!< AXI Clock from OSC 24M.*/ + ccmRootmuxAxiSysPllPfd1 = 1U, /*!< AXI Clock from SYSTEM PLL PFD1.*/ + ccmRootmuxAxiDdrPllDiv2 = 2U, /*!< AXI Clock DDR PLL divided by 2.*/ + ccmRootmuxAxiEnetPll250m = 3U, /*!< AXI Clock Ethernet PLL 250M.*/ + ccmRootmuxAxiSysPllPfd5 = 4U, /*!< AXI Clock SYSTEM PLL PFD5.*/ + ccmRootmuxAxiAudioPll = 5U, /*!< AXI Clock AUDIO PLL.*/ + ccmRootmuxAxiVideoPll = 6U, /*!< AXI Clock VIDEO PLL.*/ + ccmRootmuxAxiSysPllPfd7 = 7U, /*!< AXI Clock SYSTEM PLL PFD7.*/ }; -/*! - * @brief Clock source enumeration for AHB bus. - */ -enum _ccm_rootmux_ahb { - ccmRootmuxAhbOsc24m = 0U, - ccmRootmuxAhbSysPllPfd2 = 1U, - ccmRootmuxAhbDdrPllDiv2 = 2U, - ccmRootmuxAhbSysPllPfd0 = 3U, - ccmRootmuxAhbEnetPll125m = 4U, - ccmRootmuxAhbUsbPll = 5U, - ccmRootmuxAhbAudioPll = 6U, - ccmRootmuxAhbVideoPll = 7U +/*! @brief Clock source enumeration for AHB bus. */ +enum _ccm_rootmux_ahb +{ + ccmRootmuxAhbOsc24m = 0U, /*!< AHB Clock from OSC 24M.*/ + ccmRootmuxAhbSysPllPfd2 = 1U, /*!< AHB Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxAhbDdrPllDiv2 = 2U, /*!< AHB Clock from DDR PLL divided by 2.*/ + ccmRootmuxAhbSysPllPfd0 = 3U, /*!< AHB Clock from SYSTEM PLL PFD0.*/ + ccmRootmuxAhbEnetPll125m = 4U, /*!< AHB Clock from Ethernet PLL 125M.*/ + ccmRootmuxAhbUsbPll = 5U, /*!< AHB Clock from USB PLL.*/ + ccmRootmuxAhbAudioPll = 6U, /*!< AHB Clock from AUDIO PLL.*/ + ccmRootmuxAhbVideoPll = 7U, /*!< AHB Clock from VIDEO PLL.*/ }; -/*! - * @brief Clock source enumeration for IPG bus. - */ -enum _ccm_rootmux_ipg { - ccmRootmuxIpgAHB = 0U +/*! @brief Clock source enumeration for IPG bus. */ +enum _ccm_rootmux_ipg +{ + ccmRootmuxIpgAHB = 0U, /*!< IPG Clock from AHB Clock.*/ }; -/*! - * @brief Clock source enumeration for QSPI peripheral. - */ -enum _ccm_rootmux_qspi { - ccmRootmuxQspiOsc24m = 0U, - ccmRootmuxQspiSysPllPfd4 = 1U, - ccmRootmuxQspiDdrPllDiv2 = 2U, - ccmRootmuxQspiEnetPll500m = 3U, - ccmRootmuxQspiSysPllPfd3 = 4U, - ccmRootmuxQspiSysPllPfd2 = 5U, - ccmRootmuxQspiSysPllPfd6 = 6U, - ccmRootmuxQspiSysPllPfd7 = 7U +/*! @brief Clock source enumeration for QSPI peripheral. */ +enum _ccm_rootmux_qspi +{ + ccmRootmuxQspiOsc24m = 0U, /*!< QSPI Clock from OSC 24M.*/ + ccmRootmuxQspiSysPllPfd4 = 1U, /*!< QSPI Clock from SYSTEM PLL PFD4.*/ + ccmRootmuxQspiDdrPllDiv2 = 2U, /*!< QSPI Clock from DDR PLL divided by 2.*/ + ccmRootmuxQspiEnetPll500m = 3U, /*!< QSPI Clock from Ethernet PLL 500M.*/ + ccmRootmuxQspiSysPllPfd3 = 4U, /*!< QSPI Clock from SYSTEM PLL PFD3.*/ + ccmRootmuxQspiSysPllPfd2 = 5U, /*!< QSPI Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxQspiSysPllPfd6 = 6U, /*!< QSPI Clock from SYSTEM PLL PFD6.*/ + ccmRootmuxQspiSysPllPfd7 = 7U, /*!< QSPI Clock from SYSTEM PLL PFD7.*/ }; -/*! - * @brief Clock source enumeration for CAN peripheral. - */ -enum _ccm_rootmux_can { - ccmRootmuxCanOsc24m = 0U, - ccmRootmuxCanSysPllDiv4 = 1U, - ccmRootmuxCanDdrPllDiv2 = 2U, - ccmRootmuxCanSysPllDiv1 = 3U, - ccmRootmuxCanEnetPll40m = 4U, - ccmRootmuxCanUsbPll = 5U, - ccmRootmuxCanExtClk1 = 6U, - ccmRootmuxCanExtClk34 = 7U +/*! @brief Clock source enumeration for CAN peripheral. */ +enum _ccm_rootmux_can +{ + ccmRootmuxCanOsc24m = 0U, /*!< CAN Clock from OSC 24M.*/ + ccmRootmuxCanSysPllDiv4 = 1U, /*!< CAN Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxCanDdrPllDiv2 = 2U, /*!< CAN Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxCanSysPllDiv1 = 3U, /*!< CAN Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxCanEnetPll40m = 4U, /*!< CAN Clock from Ethernet PLL 40M.*/ + ccmRootmuxCanUsbPll = 5U, /*!< CAN Clock from USB PLL.*/ + ccmRootmuxCanExtClk1 = 6U, /*!< CAN Clock from External Clock1.*/ + ccmRootmuxCanExtClk34 = 7U, /*!< CAN Clock from External Clock34.*/ }; -/*! - * @brief Clock source enumeration for ECSPI peripheral. - */ -enum _ccm_rootmux_ecspi { - ccmRootmuxEcspiOsc24m = 0U, - ccmRootmuxEcspiSysPllDiv2 = 1U, - ccmRootmuxEcspiEnetPll40m = 2U, - ccmRootmuxEcspiSysPllDiv4 = 3U, - ccmRootmuxEcspiSysPllDiv1 = 4U, - ccmRootmuxEcspiSysPllPfd4 = 5U, - ccmRootmuxEcspiEnetPll250m = 6U, - ccmRootmuxEcspiUsbPll = 7U +/*! @brief Clock source enumeration for ECSPI peripheral. */ +enum _ccm_rootmux_ecspi +{ + ccmRootmuxEcspiOsc24m = 0U, /*!< ECSPI Clock from OSC 24M.*/ + ccmRootmuxEcspiSysPllDiv2 = 1U, /*!< ECSPI Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxEcspiEnetPll40m = 2U, /*!< ECSPI Clock from Ethernet PLL 40M.*/ + ccmRootmuxEcspiSysPllDiv4 = 3U, /*!< ECSPI Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxEcspiSysPllDiv1 = 4U, /*!< ECSPI Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxEcspiSysPllPfd4 = 5U, /*!< ECSPI Clock from SYSTEM PLL PFD4.*/ + ccmRootmuxEcspiEnetPll250m = 6U, /*!< ECSPI Clock from Ethernet PLL 250M.*/ + ccmRootmuxEcspiUsbPll = 7U, /*!< ECSPI Clock from USB PLL.*/ }; -/*! - * @brief Clock source enumeration for I2C peripheral. - */ -enum _ccm_rootmux_i2c { - ccmRootmuxI2cOsc24m = 0U, - ccmRootmuxI2cSysPllDiv4 = 1U, - ccmRootmuxI2cEnetPll50m = 2U, - ccmRootmuxI2cDdrPllDiv2 = 3U, - ccmRootmuxI2cAudioPll = 4U, - ccmRootmuxI2cVideoPll = 5U, - ccmRootmuxI2cUsbPll = 6U, - ccmRootmuxI2cSysPllPfd2Div2 = 7U +/*! @brief Clock source enumeration for I2C peripheral. */ +enum _ccm_rootmux_i2c +{ + ccmRootmuxI2cOsc24m = 0U, /*!< I2C Clock from OSC 24M.*/ + ccmRootmuxI2cSysPllDiv4 = 1U, /*!< I2C Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxI2cEnetPll50m = 2U, /*!< I2C Clock from Ethernet PLL 50M.*/ + ccmRootmuxI2cDdrPllDiv2 = 3U, /*!< I2C Clock from DDR PLL divided by .*/ + ccmRootmuxI2cAudioPll = 4U, /*!< I2C Clock from AUDIO PLL.*/ + ccmRootmuxI2cVideoPll = 5U, /*!< I2C Clock from VIDEO PLL.*/ + ccmRootmuxI2cUsbPll = 6U, /*!< I2C Clock from USB PLL.*/ + ccmRootmuxI2cSysPllPfd2Div2 = 7U, /*!< I2C Clock from SYSTEM PLL PFD2 divided by 2.*/ }; -/*! - * @brief Clock source enumeration for UART peripheral. - */ -enum _ccm_rootmux_uart { - ccmRootmuxUartOsc24m = 0U, - ccmRootmuxUartSysPllDiv2 = 1U, - ccmRootmuxUartEnetPll40m = 2U, - ccmRootmuxUartEnetPll100m = 3U, - ccmRootmuxUartSysPllDiv1 = 4U, - ccmRootmuxUartExtClk2 = 5U, - ccmRootmuxUartExtClk34 = 6U, - ccmRootmuxUartUsbPll = 7U +/*! @brief Clock source enumeration for UART peripheral. */ +enum _ccm_rootmux_uart +{ + ccmRootmuxUartOsc24m = 0U, /*!< UART Clock from OSC 24M.*/ + ccmRootmuxUartSysPllDiv2 = 1U, /*!< UART Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxUartEnetPll40m = 2U, /*!< UART Clock from Ethernet PLL 40M.*/ + ccmRootmuxUartEnetPll100m = 3U, /*!< UART Clock from Ethernet PLL 100M.*/ + ccmRootmuxUartSysPllDiv1 = 4U, /*!< UART Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxUartExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/ + ccmRootmuxUartExtClk34 = 6U, /*!< UART Clock from External Clock 34.*/ + ccmRootmuxUartUsbPll = 7U, /*!< UART Clock from USB PLL.*/ }; -/*! - * @brief Clock source enumeration for FlexTimer peripheral. - */ -enum _ccm_rootmux_ftm { - ccmRootmuxFtmOsc24m = 0U, - ccmRootmuxFtmEnetPll100m = 1U, - ccmRootmuxFtmSysPllDiv4 = 2U, - ccmRootmuxFtmEnetPll40m = 3U, - ccmRootmuxFtmAudioPll = 4U, - ccmRootmuxFtmExtClk3 = 5U, - ccmRootmuxFtmRef1m = 6U, - ccmRootmuxFtmVideoPll = 7U +/*! @brief Clock source enumeration for FlexTimer peripheral. */ +enum _ccm_rootmux_ftm +{ + ccmRootmuxFtmOsc24m = 0U, /*!< FTM Clock from OSC 24M.*/ + ccmRootmuxFtmEnetPll100m = 1U, /*!< FTM Clock from Ethernet PLL 100M.*/ + ccmRootmuxFtmSysPllDiv4 = 2U, /*!< FTM Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxFtmEnetPll40m = 3U, /*!< FTM Clock from Ethernet PLL 40M.*/ + ccmRootmuxFtmAudioPll = 4U, /*!< FTM Clock from AUDIO PLL.*/ + ccmRootmuxFtmExtClk3 = 5U, /*!< FTM Clock from External Clock 3.*/ + ccmRootmuxFtmRef1m = 6U, /*!< FTM Clock from Refernece Clock 1M.*/ + ccmRootmuxFtmVideoPll = 7U, /*!< FTM Clock from VIDEO PLL.*/ }; -/*! - * @brief Clock source enumeration for GPT peripheral. - */ -enum _ccm_rootmux_gpt { - ccmRootmuxGptOsc24m = 0U, - ccmRootmuxGptEnetPll100m = 1U, - ccmRootmuxGptSysPllPfd0 = 2U, - ccmRootmuxGptEnetPll40m = 3U, - ccmRootmuxGptVideoPll = 4U, - ccmRootmuxGptRef1m = 5U, - ccmRootmuxGptAudioPll = 6U, - ccmRootmuxGptExtClk = 7U +/*! @brief Clock source enumeration for GPT peripheral. */ +enum _ccm_rootmux_gpt +{ + ccmRootmuxGptOsc24m = 0U, /*!< GPT Clock from OSC 24M.*/ + ccmRootmuxGptEnetPll100m = 1U, /*!< GPT Clock from Ethernet PLL 100M.*/ + ccmRootmuxGptSysPllPfd0 = 2U, /*!< GPT Clock from SYSTEM PLL PFD0.*/ + ccmRootmuxGptEnetPll40m = 3U, /*!< GPT Clock from Ethernet PLL 40M.*/ + ccmRootmuxGptVideoPll = 4U, /*!< GPT Clock from VIDEO PLL.*/ + ccmRootmuxGptRef1m = 5U, /*!< GPT Clock from Refernece Clock 1M.*/ + ccmRootmuxGptAudioPll = 6U, /*!< GPT Clock from AUDIO PLL.*/ + ccmRootmuxGptExtClk = 7U, /*!< GPT Clock from External Clock.*/ }; -/*! - * @brief Clock source enumeration for WDOG peripheral. - */ -enum _ccm_rootmux_wdog { - ccmRootmuxWdogOsc24m = 0U, - ccmRootmuxWdogSysPllPfd2Div2 = 1U, - ccmRootmuxWdogSysPllDiv4 = 2U, - ccmRootmuxWdogDdrPllDiv2 = 3U, - ccmRootmuxWdogEnetPll125m = 4U, - ccmRootmuxWdogUsbPll = 5U, - ccmRootmuxWdogRef1m = 6U, - ccmRootmuxWdogSysPllPfd1Div2 = 7U +/*! @brief Clock source enumeration for WDOG peripheral. */ +enum _ccm_rootmux_wdog +{ + ccmRootmuxWdogOsc24m = 0U, /*!< WDOG Clock from OSC 24M.*/ + ccmRootmuxWdogSysPllPfd2Div2 = 1U, /*!< WDOG Clock from SYSTEM PLL PFD2 divided by 2.*/ + ccmRootmuxWdogSysPllDiv4 = 2U, /*!< WDOG Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxWdogDdrPllDiv2 = 3U, /*!< WDOG Clock from DDR PLL divided by 2.*/ + ccmRootmuxWdogEnetPll125m = 4U, /*!< WDOG Clock from Ethernet PLL 125M.*/ + ccmRootmuxWdogUsbPll = 5U, /*!< WDOG Clock from USB PLL.*/ + ccmRootmuxWdogRef1m = 6U, /*!< WDOG Clock from Refernece Clock 1M.*/ + ccmRootmuxWdogSysPllPfd1Div2 = 7U, /*!< WDOG Clock from SYSTEM PLL PFD1 divided by 2.*/ }; -/*! - * @brief CCM PLL gate control - */ -enum _ccm_pll_gate { - ccmPllGateCkil = (uint32_t)(&CCM_PLL_CTRL0_REG(CCM_BASE_PTR)), - ccmPllGateArm = (uint32_t)(&CCM_PLL_CTRL1_REG(CCM_BASE_PTR)), - ccmPllGateArmDiv1 = (uint32_t)(&CCM_PLL_CTRL2_REG(CCM_BASE_PTR)), - ccmPllGateDdr = (uint32_t)(&CCM_PLL_CTRL3_REG(CCM_BASE_PTR)), - ccmPllGateDdrDiv1 = (uint32_t)(&CCM_PLL_CTRL4_REG(CCM_BASE_PTR)), - ccmPllGateDdrDiv2 = (uint32_t)(&CCM_PLL_CTRL5_REG(CCM_BASE_PTR)), - ccmPllGateSys = (uint32_t)(&CCM_PLL_CTRL6_REG(CCM_BASE_PTR)), - ccmPllGateSysDiv1 = (uint32_t)(&CCM_PLL_CTRL7_REG(CCM_BASE_PTR)), - ccmPllGateSysDiv2 = (uint32_t)(&CCM_PLL_CTRL8_REG(CCM_BASE_PTR)), - ccmPllGateSysDiv4 = (uint32_t)(&CCM_PLL_CTRL9_REG(CCM_BASE_PTR)), - ccmPllGatePfd0 = (uint32_t)(&CCM_PLL_CTRL10_REG(CCM_BASE_PTR)), - ccmPllGatePfd0Div2 = (uint32_t)(&CCM_PLL_CTRL11_REG(CCM_BASE_PTR)), - ccmPllGatePfd1 = (uint32_t)(&CCM_PLL_CTRL12_REG(CCM_BASE_PTR)), - ccmPllGatePfd1Div2 = (uint32_t)(&CCM_PLL_CTRL13_REG(CCM_BASE_PTR)), - ccmPllGatePfd2 = (uint32_t)(&CCM_PLL_CTRL14_REG(CCM_BASE_PTR)), - ccmPllGatePfd2Div2 = (uint32_t)(&CCM_PLL_CTRL15_REG(CCM_BASE_PTR)), - ccmPllGatePfd3 = (uint32_t)(&CCM_PLL_CTRL16_REG(CCM_BASE_PTR)), - ccmPllGatePfd4 = (uint32_t)(&CCM_PLL_CTRL17_REG(CCM_BASE_PTR)), - ccmPllGatePfd5 = (uint32_t)(&CCM_PLL_CTRL18_REG(CCM_BASE_PTR)), - ccmPllGatePfd6 = (uint32_t)(&CCM_PLL_CTRL19_REG(CCM_BASE_PTR)), - ccmPllGatePfd7 = (uint32_t)(&CCM_PLL_CTRL20_REG(CCM_BASE_PTR)), - ccmPllGateEnet = (uint32_t)(&CCM_PLL_CTRL21_REG(CCM_BASE_PTR)), - ccmPllGateEnet500m = (uint32_t)(&CCM_PLL_CTRL22_REG(CCM_BASE_PTR)), - ccmPllGateEnet250m = (uint32_t)(&CCM_PLL_CTRL23_REG(CCM_BASE_PTR)), - ccmPllGateEnet125m = (uint32_t)(&CCM_PLL_CTRL24_REG(CCM_BASE_PTR)), - ccmPllGateEnet100m = (uint32_t)(&CCM_PLL_CTRL25_REG(CCM_BASE_PTR)), - ccmPllGateEnet50m = (uint32_t)(&CCM_PLL_CTRL26_REG(CCM_BASE_PTR)), - ccmPllGateEnet40m = (uint32_t)(&CCM_PLL_CTRL27_REG(CCM_BASE_PTR)), - ccmPllGateEnet25m = (uint32_t)(&CCM_PLL_CTRL28_REG(CCM_BASE_PTR)), - ccmPllGateAudio = (uint32_t)(&CCM_PLL_CTRL29_REG(CCM_BASE_PTR)), - ccmPllGateAudioDiv1 = (uint32_t)(&CCM_PLL_CTRL30_REG(CCM_BASE_PTR)), - ccmPllGateVideo = (uint32_t)(&CCM_PLL_CTRL31_REG(CCM_BASE_PTR)), - ccmPllGateVideoDiv1 = (uint32_t)(&CCM_PLL_CTRL32_REG(CCM_BASE_PTR)) +/*! @brief CCM PLL gate control. */ +enum _ccm_pll_gate +{ + ccmPllGateCkil = (uint32_t)(&CCM_PLL_CTRL0), /*!< Ckil PLL Gate.*/ + ccmPllGateArm = (uint32_t)(&CCM_PLL_CTRL1), /*!< ARM PLL Gate.*/ + ccmPllGateArmDiv1 = (uint32_t)(&CCM_PLL_CTRL2), /*!< ARM PLL Div1 Gate.*/ + ccmPllGateDdr = (uint32_t)(&CCM_PLL_CTRL3), /*!< DDR PLL Gate.*/ + ccmPllGateDdrDiv1 = (uint32_t)(&CCM_PLL_CTRL4), /*!< DDR PLL Div1 Gate.*/ + ccmPllGateDdrDiv2 = (uint32_t)(&CCM_PLL_CTRL5), /*!< DDR PLL Div2 Gate.*/ + ccmPllGateSys = (uint32_t)(&CCM_PLL_CTRL6), /*!< SYSTEM PLL Gate.*/ + ccmPllGateSysDiv1 = (uint32_t)(&CCM_PLL_CTRL7), /*!< SYSTEM PLL Div1 Gate.*/ + ccmPllGateSysDiv2 = (uint32_t)(&CCM_PLL_CTRL8), /*!< SYSTEM PLL Div2 Gate.*/ + ccmPllGateSysDiv4 = (uint32_t)(&CCM_PLL_CTRL9), /*!< SYSTEM PLL Div4 Gate.*/ + ccmPllGatePfd0 = (uint32_t)(&CCM_PLL_CTRL10), /*!< PFD0 Gate.*/ + ccmPllGatePfd0Div2 = (uint32_t)(&CCM_PLL_CTRL11), /*!< PFD0 Div2 Gate.*/ + ccmPllGatePfd1 = (uint32_t)(&CCM_PLL_CTRL12), /*!< PFD1 Gate.*/ + ccmPllGatePfd1Div2 = (uint32_t)(&CCM_PLL_CTRL13), /*!< PFD1 Div2 Gate.*/ + ccmPllGatePfd2 = (uint32_t)(&CCM_PLL_CTRL14), /*!< PFD2 Gate.*/ + ccmPllGatePfd2Div2 = (uint32_t)(&CCM_PLL_CTRL15), /*!< PDF2 Div2.*/ + ccmPllGatePfd3 = (uint32_t)(&CCM_PLL_CTRL16), /*!< PDF3 Gate.*/ + ccmPllGatePfd4 = (uint32_t)(&CCM_PLL_CTRL17), /*!< PDF4 Gate.*/ + ccmPllGatePfd5 = (uint32_t)(&CCM_PLL_CTRL18), /*!< PDF5 Gate.*/ + ccmPllGatePfd6 = (uint32_t)(&CCM_PLL_CTRL19), /*!< PDF6 Gate.*/ + ccmPllGatePfd7 = (uint32_t)(&CCM_PLL_CTRL20), /*!< PDF7 Gate.*/ + ccmPllGateEnet = (uint32_t)(&CCM_PLL_CTRL21), /*!< Ethernet PLL Gate.*/ + ccmPllGateEnet500m = (uint32_t)(&CCM_PLL_CTRL22), /*!< Ethernet 500M PLL Gate.*/ + ccmPllGateEnet250m = (uint32_t)(&CCM_PLL_CTRL23), /*!< Ethernet 250M PLL Gate.*/ + ccmPllGateEnet125m = (uint32_t)(&CCM_PLL_CTRL24), /*!< Ethernet 125M PLL Gate.*/ + ccmPllGateEnet100m = (uint32_t)(&CCM_PLL_CTRL25), /*!< Ethernet 100M PLL Gate.*/ + ccmPllGateEnet50m = (uint32_t)(&CCM_PLL_CTRL26), /*!< Ethernet 50M PLL Gate.*/ + ccmPllGateEnet40m = (uint32_t)(&CCM_PLL_CTRL27), /*!< Ethernet 40M PLL Gate.*/ + ccmPllGateEnet25m = (uint32_t)(&CCM_PLL_CTRL28), /*!< Ethernet 25M PLL Gate.*/ + ccmPllGateAudio = (uint32_t)(&CCM_PLL_CTRL29), /*!< AUDIO PLL Gate.*/ + ccmPllGateAudioDiv1 = (uint32_t)(&CCM_PLL_CTRL30), /*!< AUDIO PLL Div1 Gate.*/ + ccmPllGateVideo = (uint32_t)(&CCM_PLL_CTRL31), /*!< VIDEO PLL Gate.*/ + ccmPllGateVideoDiv1 = (uint32_t)(&CCM_PLL_CTRL32), /*!< VIDEO PLL Div1 Gate.*/ }; -/*! - * @brief CCM CCGR gate control - */ -enum _ccm_ccgr_gate { - ccmCcgrGateIpmux1 = (uint32_t)(&CCM_CCGR10), - ccmCcgrGateIpmux2 = (uint32_t)(&CCM_CCGR11), - ccmCcgrGateIpmux3 = (uint32_t)(&CCM_CCGR12), - ccmCcgrGateOcram = (uint32_t)(&CCM_CCGR17), - ccmCcgrGateOcramS = (uint32_t)(&CCM_CCGR18), - ccmCcgrGateQspi = (uint32_t)(&CCM_CCGR21), - ccmCcgrGateAdc = (uint32_t)(&CCM_CCGR32), - ccmCcgrGateRdc = (uint32_t)(&CCM_CCGR38), - ccmCcgrGateMu = (uint32_t)(&CCM_CCGR39), - ccmCcgrGateSemaHs = (uint32_t)(&CCM_CCGR40), - ccmCcgrGateSema1 = (uint32_t)(&CCM_CCGR64), - ccmCcgrGateSema2 = (uint32_t)(&CCM_CCGR65), - ccmCcgrGateCan1 = (uint32_t)(&CCM_CCGR116), - ccmCcgrGateCan2 = (uint32_t)(&CCM_CCGR117), - ccmCcgrGateEcspi1 = (uint32_t)(&CCM_CCGR120), - ccmCcgrGateEcspi2 = (uint32_t)(&CCM_CCGR121), - ccmCcgrGateEcspi3 = (uint32_t)(&CCM_CCGR122), - ccmCcgrGateEcspi4 = (uint32_t)(&CCM_CCGR123), - ccmCcgrGateGpt1 = (uint32_t)(&CCM_CCGR124), - ccmCcgrGateGpt2 = (uint32_t)(&CCM_CCGR125), - ccmCcgrGateGpt3 = (uint32_t)(&CCM_CCGR126), - ccmCcgrGateGpt4 = (uint32_t)(&CCM_CCGR127), - ccmCcgrGateI2c1 = (uint32_t)(&CCM_CCGR136), - ccmCcgrGateI2c2 = (uint32_t)(&CCM_CCGR137), - ccmCcgrGateI2c3 = (uint32_t)(&CCM_CCGR138), - ccmCcgrGateI2c4 = (uint32_t)(&CCM_CCGR139), - ccmCcgrGateUart1 = (uint32_t)(&CCM_CCGR148), - ccmCcgrGateUart2 = (uint32_t)(&CCM_CCGR149), - ccmCcgrGateUart3 = (uint32_t)(&CCM_CCGR150), - ccmCcgrGateUart4 = (uint32_t)(&CCM_CCGR151), - ccmCcgrGateUart5 = (uint32_t)(&CCM_CCGR152), - ccmCcgrGateUart6 = (uint32_t)(&CCM_CCGR153), - ccmCcgrGateUart7 = (uint32_t)(&CCM_CCGR154), - ccmCcgrGateWdog1 = (uint32_t)(&CCM_CCGR156), - ccmCcgrGateWdog2 = (uint32_t)(&CCM_CCGR157), - ccmCcgrGateWdog3 = (uint32_t)(&CCM_CCGR158), - ccmCcgrGateWdog4 = (uint32_t)(&CCM_CCGR159), - ccmCcgrGateGpio1 = (uint32_t)(&CCM_CCGR160), - ccmCcgrGateGpio2 = (uint32_t)(&CCM_CCGR161), - ccmCcgrGateGpio3 = (uint32_t)(&CCM_CCGR162), - ccmCcgrGateGpio4 = (uint32_t)(&CCM_CCGR163), - ccmCcgrGateGpio5 = (uint32_t)(&CCM_CCGR164), - ccmCcgrGateGpio6 = (uint32_t)(&CCM_CCGR165), - ccmCcgrGateGpio7 = (uint32_t)(&CCM_CCGR166), - ccmCcgrGateIomux = (uint32_t)(&CCM_CCGR168), - ccmCcgrGateIomuxLpsr = (uint32_t)(&CCM_CCGR169), - ccmCcgrGatePwm1 = (uint32_t)(&CCM_CCGR132), - ccmCcgrGatePwm2 = (uint32_t)(&CCM_CCGR133), - ccmCcgrGatePwm3 = (uint32_t)(&CCM_CCGR134), - ccmCcgrGatePwm4 = (uint32_t)(&CCM_CCGR135) +/*! @brief CCM CCGR gate control. */ +enum _ccm_ccgr_gate +{ + ccmCcgrGateIpmux1 = (uint32_t)(&CCM_CCGR10), /*!< IOMUX1 Clock Gate.*/ + ccmCcgrGateIpmux2 = (uint32_t)(&CCM_CCGR11), /*!< IOMUX2 Clock Gate.*/ + ccmCcgrGateIpmux3 = (uint32_t)(&CCM_CCGR12), /*!< IPMUX3 Clock Gate.*/ + ccmCcgrGateOcram = (uint32_t)(&CCM_CCGR17), /*!< OCRAM Clock Gate.*/ + ccmCcgrGateOcramS = (uint32_t)(&CCM_CCGR18), /*!< OCRAM S Clock Gate.*/ + ccmCcgrGateQspi = (uint32_t)(&CCM_CCGR21), /*!< QSPI Clock Gate.*/ + ccmCcgrGateAdc = (uint32_t)(&CCM_CCGR32), /*!< ADC Clock Gate.*/ + ccmCcgrGateRdc = (uint32_t)(&CCM_CCGR38), /*!< RDC Clock Gate.*/ + ccmCcgrGateMu = (uint32_t)(&CCM_CCGR39), /*!< MU Clock Gate.*/ + ccmCcgrGateSemaHs = (uint32_t)(&CCM_CCGR40), /*!< SEMA HS Clock Gate.*/ + ccmCcgrGateSema1 = (uint32_t)(&CCM_CCGR64), /*!< SEMA1 Clock Gate.*/ + ccmCcgrGateSema2 = (uint32_t)(&CCM_CCGR65), /*!< SEMA2 Clock Gate.*/ + ccmCcgrGateCan1 = (uint32_t)(&CCM_CCGR116), /*!< CAN1 Clock Gate.*/ + ccmCcgrGateCan2 = (uint32_t)(&CCM_CCGR117), /*!< CAN2 Clock Gate.*/ + ccmCcgrGateEcspi1 = (uint32_t)(&CCM_CCGR120), /*!< ECSPI1 Clock Gate.*/ + ccmCcgrGateEcspi2 = (uint32_t)(&CCM_CCGR121), /*!< ECSPI2 Clock Gate.*/ + ccmCcgrGateEcspi3 = (uint32_t)(&CCM_CCGR122), /*!< ECSPI3 Clock Gate.*/ + ccmCcgrGateEcspi4 = (uint32_t)(&CCM_CCGR123), /*!< ECSPI4 Clock Gate.*/ + ccmCcgrGateGpt1 = (uint32_t)(&CCM_CCGR124), /*!< GPT1 Clock Gate.*/ + ccmCcgrGateGpt2 = (uint32_t)(&CCM_CCGR125), /*!< GPT2 Clock Gate.*/ + ccmCcgrGateGpt3 = (uint32_t)(&CCM_CCGR126), /*!< GPT3 Clock Gate.*/ + ccmCcgrGateGpt4 = (uint32_t)(&CCM_CCGR127), /*!< GPT4 Clock Gate.*/ + ccmCcgrGateI2c1 = (uint32_t)(&CCM_CCGR136), /*!< I2C1 Clock Gate.*/ + ccmCcgrGateI2c2 = (uint32_t)(&CCM_CCGR137), /*!< I2C2 Clock Gate.*/ + ccmCcgrGateI2c3 = (uint32_t)(&CCM_CCGR138), /*!< I2C3 Clock Gate.*/ + ccmCcgrGateI2c4 = (uint32_t)(&CCM_CCGR139), /*!< I2C4 Clock Gate.*/ + ccmCcgrGateUart1 = (uint32_t)(&CCM_CCGR148), /*!< UART1 Clock Gate.*/ + ccmCcgrGateUart2 = (uint32_t)(&CCM_CCGR149), /*!< UART2 Clock Gate.*/ + ccmCcgrGateUart3 = (uint32_t)(&CCM_CCGR150), /*!< UART3 Clock Gate.*/ + ccmCcgrGateUart4 = (uint32_t)(&CCM_CCGR151), /*!< UART4 Clock Gate.*/ + ccmCcgrGateUart5 = (uint32_t)(&CCM_CCGR152), /*!< UART5 Clock Gate.*/ + ccmCcgrGateUart6 = (uint32_t)(&CCM_CCGR153), /*!< UART6 Clock Gate.*/ + ccmCcgrGateUart7 = (uint32_t)(&CCM_CCGR154), /*!< UART7 Clock Gate.*/ + ccmCcgrGateWdog1 = (uint32_t)(&CCM_CCGR156), /*!< WDOG1 Clock Gate.*/ + ccmCcgrGateWdog2 = (uint32_t)(&CCM_CCGR157), /*!< WDOG2 Clock Gate.*/ + ccmCcgrGateWdog3 = (uint32_t)(&CCM_CCGR158), /*!< WDOG3 Clock Gate.*/ + ccmCcgrGateWdog4 = (uint32_t)(&CCM_CCGR159), /*!< WDOG4 Clock Gate.*/ + ccmCcgrGateGpio1 = (uint32_t)(&CCM_CCGR160), /*!< GPIO1 Clock Gate.*/ + ccmCcgrGateGpio2 = (uint32_t)(&CCM_CCGR161), /*!< GPIO2 Clock Gate.*/ + ccmCcgrGateGpio3 = (uint32_t)(&CCM_CCGR162), /*!< GPIO3 Clock Gate.*/ + ccmCcgrGateGpio4 = (uint32_t)(&CCM_CCGR163), /*!< GPIO4 Clock Gate.*/ + ccmCcgrGateGpio5 = (uint32_t)(&CCM_CCGR164), /*!< GPIO5 Clock Gate.*/ + ccmCcgrGateGpio6 = (uint32_t)(&CCM_CCGR165), /*!< GPIO6 Clock Gate.*/ + ccmCcgrGateGpio7 = (uint32_t)(&CCM_CCGR166), /*!< GPIO7 Clock Gate.*/ + ccmCcgrGateIomux = (uint32_t)(&CCM_CCGR168), /*!< IOMUX Clock Gate.*/ + ccmCcgrGateIomuxLpsr = (uint32_t)(&CCM_CCGR169), /*!< IOMUX LPSR Clock Gate.*/ }; -/*! - * @brief CCM gate control value - */ -enum _ccm_gate_value { - ccmClockNotNeeded = 0x0U, /*!< Clock always disabled.*/ - ccmClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/ - ccmClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/ - ccmClockNeededAll = 0x3333U /*!< Clock always enabled.*/ +/*! @brief CCM gate control value. */ +enum _ccm_gate_value +{ + ccmClockNotNeeded = 0x0U, /*!< Clock always disabled.*/ + ccmClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/ + ccmClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/ + ccmClockNeededAll = 0x3333U, /*!< Clock always enabled.*/ }; /******************************************************************************* @@ -368,66 +348,68 @@ extern "C" { * @brief Set clock root mux * * @param base CCM base pointer. - * @param ccmRoot Root control (see _ccm_root_control enumeration) - * @param mux Root mux value (see _ccm_rootmux_xxx enumeration) + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param mux Root mux value (see @ref _ccm_rootmux_xxx enumeration) */ static inline void CCM_SetRootMux(CCM_Type * base, uint32_t ccmRoot, uint32_t mux) { - CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & (~CCM_TARGET_ROOT0_MUX_MASK)) | - CCM_TARGET_ROOT0_MUX(mux); + CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & (~CCM_TARGET_ROOT_MUX_MASK)) | + CCM_TARGET_ROOT_MUX(mux); } /*! * @brief Get clock root mux * * @param base CCM base pointer. - * @param ccmRoot Root control (see _ccm_root_control enumeration) - * @return root mux value (see _ccm_rootmux_xxx enumeration) + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @return root mux value (see @ref _ccm_rootmux_xxx enumeration) */ static inline uint32_t CCM_GetRootMux(CCM_Type * base, uint32_t ccmRoot) { - return (CCM_REG(ccmRoot) & CCM_TARGET_ROOT0_MUX_MASK) >> CCM_TARGET_ROOT0_MUX_SHIFT; + return (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; } /*! * @brief Enable clock root * * @param base CCM base pointer. - * @param ccmRoot Root control (see _ccm_root_control enumeration) + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) */ static inline void CCM_EnableRoot(CCM_Type * base, uint32_t ccmRoot) { - CCM_REG_SET(ccmRoot) = CCM_TARGET_ROOT0_SET_ENABLE_MASK; + CCM_REG_SET(ccmRoot) = CCM_TARGET_ROOT_SET_ENABLE_MASK; } /*! * @brief Disable clock root * * @param base CCM base pointer. - * @param ccmRoot Root control (see _ccm_root_control enumeration) + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) */ static inline void CCM_DisableRoot(CCM_Type * base, uint32_t ccmRoot) { - CCM_REG_CLR(ccmRoot) = CCM_TARGET_ROOT0_CLR_ENABLE_MASK; + CCM_REG_CLR(ccmRoot) = CCM_TARGET_ROOT_CLR_ENABLE_MASK; } /*! * @brief Check whether clock root is enabled * * @param base CCM base pointer. - * @param ccmRoot Root control (see _ccm_root_control enumeration) - * @return CCM root enabled or not (true: enabled, false: disabled) + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @return CCM root enabled or not. + * - true: Clock root is enabled. + * - false: Clock root is disabled. */ static inline bool CCM_IsRootEnabled(CCM_Type * base, uint32_t ccmRoot) { - return (bool)(CCM_REG(ccmRoot) & CCM_TARGET_ROOT0_ENABLE_MASK); + return (bool)(CCM_REG(ccmRoot) & CCM_TARGET_ROOT_ENABLE_MASK); } /*! * @brief Set root clock divider * * @param base CCM base pointer. - * @param ccmRoot Root control (see _ccm_root_control enumeration) + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) * @param pre Pre divider value (0-7, divider=n+1) * @param post Post divider value (0-63, divider=n+1) */ @@ -437,7 +419,7 @@ void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t pre, uint32_ * @brief Get root clock divider * * @param base CCM base pointer. - * @param ccmRoot Root control (see _ccm_root_control enumeration) + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) * @param pre Pointer to pre divider value store address * @param post Pointer to post divider value store address */ @@ -447,8 +429,8 @@ void CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t *pre, uint32 * @brief Update clock root in one step, for dynamical clock switching * * @param base CCM base pointer. - * @param ccmRoot Root control (see _ccm_root_control enumeration) - * @param root mux value (see _ccm_rootmux_xxx enumeration) + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param root mux value (see @ref _ccm_rootmux_xxx enumeration) * @param pre Pre divider value (0-7, divider=n+1) * @param post Post divider value (0-63, divider=n+1) */ @@ -465,8 +447,8 @@ void CCM_UpdateRoot(CCM_Type * base, uint32_t ccmRoot, uint32_t mux, uint32_t pr * @brief Set PLL or CCGR gate control * * @param base CCM base pointer. - * @param ccmGate Gate control (see _ccm_pll_gate and _ccm_ccgr_gate enumeration) - * @param control Gate control value (see _ccm_gate_value) + * @param ccmGate Gate control (see @ref _ccm_pll_gate and @ref _ccm_ccgr_gate enumeration) + * @param control Gate control value (see @ref _ccm_gate_value) */ static inline void CCM_ControlGate(CCM_Type * base, uint32_t ccmGate, uint32_t control) { diff --git a/platform/drivers/inc/ecspi.h b/platform/drivers/inc/ecspi.h index 2e11401..151472b 100644 --- a/platform/drivers/inc/ecspi.h +++ b/platform/drivers/inc/ecspi.h @@ -45,129 +45,115 @@ * Definitions ******************************************************************************/ -/*! - * @brief Channel select. - */ -enum _ecspi_channel_select { - ecspiSelectChannel0 = 0U, /*!< Selecte Channel 0. Chip Select 0 (SS0) will be asserted.*/ - ecspiSelectChannel1 = 1U, /*!< Selecte Channel 1. Chip Select 1 (SS1) will be asserted.*/ - ecspiSelectChannel2 = 2U, /*!< Selecte Channel 2. Chip Select 2 (SS2) will be asserted.*/ - ecspiSelectChannel3 = 3U /*!< Selecte Channel 3. Chip Select 3 (SS3) will be asserted.*/ +/*! @brief Channel select. */ +enum _ecspi_channel_select +{ + ecspiSelectChannel0 = 0U, /*!< Select Channel 0. Chip Select 0 (SS0) is asserted.*/ + ecspiSelectChannel1 = 1U, /*!< Select Channel 1. Chip Select 1 (SS1) is asserted.*/ + ecspiSelectChannel2 = 2U, /*!< Select Channel 2. Chip Select 2 (SS2) is asserted.*/ + ecspiSelectChannel3 = 3U, /*!< Select Channel 3. Chip Select 3 (SS3) is asserted.*/ }; -/*! - * @brief Channel mode. - */ -enum _ecspi_master_slave_mode { - ecspiSlaveMode = 0U, /*!< Set Slave Mode.*/ - ecspiMasterMode = 1U /*!< Set Master Mode.*/ +/*! @brief Channel mode. */ +enum _ecspi_master_slave_mode +{ + ecspiSlaveMode = 0U, /*!< Set Slave Mode.*/ + ecspiMasterMode = 1U, /*!< Set Master Mode.*/ }; -/*! - * @brief Clock phase. - */ -enum _ecspi_clock_phase { - ecspiClockPhaseFirstEdge = 0U, /*!< Data is captured on the leading edge of the SCK and - changed on the following edge.*/ - ecspiClockPhaseSecondEdge = 1U /*!< Data is changed on the leading edge of the SCK and - captured on the following edge.*/ +/*! @brief Clock phase. */ +enum _ecspi_clock_phase +{ + ecspiClockPhaseFirstEdge = 0U, /*!< Data is captured on the leading edge of the SCK and + changed on the following edge.*/ + ecspiClockPhaseSecondEdge = 1U, /*!< Data is changed on the leading edge of the SCK and + captured on the following edge.*/ }; -/*! - * @brief Clock polarity. - */ -enum _ecspi_clock_polarity { - ecspiClockPolarityActiveHigh = 0U, /*!< Active-high ECSPI clock (idles low)*/ - ecspiClockPolarityActiveLow = 1U /*!< Active-low ECSPI clock (idles high)*/ +/*! @brief Clock polarity. */ +enum _ecspi_clock_polarity +{ + ecspiClockPolarityActiveHigh = 0U, /*!< Active-high eCSPI clock (idles low).*/ + ecspiClockPolarityActiveLow = 1U, /*!< Active-low eCSPI clock (idles high).*/ }; -/*! - * @brief SS signal polarity. - */ -enum _ecspi_ss_polarity { - ecspiSSPolarityActiveLow = 0U, /*!< Active-low, ECSPI SS signal*/ - ecspiSSPolarityActiveHigh = 1U /*!< Active-high, ECSPI SS signal */ +/*! @brief SS signal polarity. */ +enum _ecspi_ss_polarity +{ + ecspiSSPolarityActiveLow = 0U, /*!< Active-low, eCSPI SS signal.*/ + ecspiSSPolarityActiveHigh = 1U, /*!< Active-high, eCSPI SS signal.*/ }; -/*! - * @brief Inactive state of data line. - */ -enum _ecspi_dataline_inactivestate { - ecspiDataLineStayHigh = 0U, /*!< Data line inactive state stay high */ - ecspiDataLineStayLow = 1U /*!< Data line inactive state stay low */ +/*! @brief Inactive state of data line. */ +enum _ecspi_dataline_inactivestate +{ + ecspiDataLineStayHigh = 0U, /*!< Data line inactive state stay high.*/ + ecspiDataLineStayLow = 1U, /*!< Data line inactive state stay low.*/ }; -/*! - * @brief Inactive state of SCLK. - */ -enum _ecspi_sclk_inactivestate { - ecspiSclkStayLow = 0U, /*!< SCLK inactive state stay low */ - ecspiSclkStayHigh = 1U /*!< SCLK line inactive state stay high */ +/*! @brief Inactive state of SCLK. */ +enum _ecspi_sclk_inactivestate +{ + ecspiSclkStayLow = 0U, /*!< SCLK inactive state stay low.*/ + ecspiSclkStayHigh = 1U, /*!< SCLK line inactive state stay high.*/ }; -/*! - * @brief sample period counter clock source. - */ -enum _ecspi_sampleperiod_clocksource { - ecspiSclk = 0U, /*!< SCLK */ - ecspiLowFreq32K = 1U /*!< Low-Frequency Reference Clock (32.768 KHz) */ +/*! @brief sample period counter clock source. */ +enum _ecspi_sampleperiod_clocksource +{ + ecspiSclk = 0U, /*!< Sample period counter clock from SCLK.*/ + ecspiLowFreq32K = 1U, /*!< Sample period counter clock from from LFRC (32.768 KHz).*/ }; -/*! - * @brief DMA Source definition. - */ -enum _ecspi_dma_source { - ecspiDmaTxfifoEmpty = 7U, /*!< TXFIFO Empty DMA Request*/ - ecspiDmaRxfifoRequest = 23U, /*!< RXFIFO DMA Request */ - ecspiDmaRxfifoTail = 31U, /*!< RXFIFO TAIL DMA Request */ +/*! @brief DMA Source definition. */ +enum _ecspi_dma_source +{ + ecspiDmaTxfifoEmpty = 7U, /*!< TXFIFO Empty DMA Request.*/ + ecspiDmaRxfifoRequest = 23U, /*!< RXFIFO DMA Request.*/ + ecspiDmaRxfifoTail = 31U, /*!< RXFIFO TAIL DMA Request.*/ }; -/*! - * @brief RXFIFO and TXFIFO threshold. - */ -enum _ecspi_fifothreshold { - ecspiTxfifoThreshold = 0U, /*!< Defines the FIFO threshold that triggers a TX DMA/INT request */ - ecspiRxfifoThreshold = 16U /*!< defines the FIFO threshold that triggers a RX DMA/INT request. */ +/*! @brief RXFIFO and TXFIFO threshold. */ +enum _ecspi_fifothreshold +{ + ecspiTxfifoThreshold = 0U, /*!< Defines the FIFO threshold that triggers a TX DMA/INT request.*/ + ecspiRxfifoThreshold = 16U, /*!< defines the FIFO threshold that triggers a RX DMA/INT request.*/ }; -/*! - * @brief Status flag. - */ -enum _ecspi_status_flag { - ecspiFlagTxfifoEmpty = 1U << 0, /*!< TXFIFO Empty Flag */ - ecspiFlagTxfifoDataRequest = 1U << 1, /*!< TXFIFO Data Request Flag */ - ecspiFlagTxfifoFull = 1U << 2, /*!< TXFIFO Full Flag */ - ecspiFlagRxfifoReady = 1U << 3, /*!< RXFIFO Ready Flag */ - ecspiFlagRxfifoDataRequest = 1U << 4, /*!< RXFIFO Data Request Flag */ - ecspiFlagRxfifoFull = 1U << 5, /*!< RXFIFO Full Flag */ - ecspiFlagRxfifoOverflow = 1U << 6, /*!< RXFIFO Overflow Flag */ - ecspiFlagTxfifoTc = 1U << 7 /*!< TXFIFO Transform Completed Flag */ +/*! @brief Status flag. */ +enum _ecspi_status_flag +{ + ecspiFlagTxfifoEmpty = 1U << 0, /*!< TXFIFO Empty Flag.*/ + ecspiFlagTxfifoDataRequest = 1U << 1, /*!< TXFIFO Data Request Flag.*/ + ecspiFlagTxfifoFull = 1U << 2, /*!< TXFIFO Full Flag.*/ + ecspiFlagRxfifoReady = 1U << 3, /*!< RXFIFO Ready Flag.*/ + ecspiFlagRxfifoDataRequest = 1U << 4, /*!< RXFIFO Data Request Flag.*/ + ecspiFlagRxfifoFull = 1U << 5, /*!< RXFIFO Full Flag.*/ + ecspiFlagRxfifoOverflow = 1U << 6, /*!< RXFIFO Overflow Flag.*/ + ecspiFlagTxfifoTc = 1U << 7, /*!< TXFIFO Transform Completed Flag.*/ }; -/*! - * @brief Data Ready Control. - */ -enum _ecspi_data_ready { - ecspiRdyNoCare = 0U, /*!< The SPI_RDY signal is a don't care */ - ecspiRdyFallEdgeTrig = 1U, /*!< Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered) */ - ecspiRdyLowLevelTrig = 2U, /*!< Burst will be triggered by a low level of the SPI_RDY signal (level-triggered) */ - ecspiRdyReserved = 3U, /*!< Reserved */ +/*! @brief Data Ready Control. */ +enum _ecspi_data_ready +{ + ecspiRdyNoCare = 0U, /*!< The SPI_RDY signal is ignored.*/ + ecspiRdyFallEdgeTrig = 1U, /*!< Burst is triggered by the falling edge of the SPI_RDY signal (edge-triggered).*/ + ecspiRdyLowLevelTrig = 2U, /*!< Burst is triggered by a low level of the SPI_RDY signal (level-triggered).*/ + ecspiRdyReserved = 3U, /*!< Reserved.*/ }; -/*! - * @brief Init structure. - */ -typedef struct EcspiInit +/*! @brief Init structure. */ +typedef struct _ecspi_init_config { - uint32_t clockRate; /*!< Specifies ECSPII module clock freq. */ - uint32_t baudRate; /*!< Specifies desired ECSPI baud rate. */ - uint32_t channelSelect; /*!< Specifies the channel select */ - uint32_t mode; /*!< Specifies the mode */ - bool ecspiAutoStart; /*!< Specifies the start mode */ - uint32_t burstLength; /*!< Specifies the length of a burst to be transferred */ - uint32_t clockPhase; /*!< Specifies the clock phase */ - uint32_t clockPolarity; /*!< Specifies the clock polarity */ -} ecspi_init_t; + uint32_t clockRate; /*!< Specifies ECSPII module clock freq.*/ + uint32_t baudRate; /*!< Specifies desired eCSPI baud rate.*/ + uint32_t channelSelect; /*!< Specifies the channel select.*/ + uint32_t mode; /*!< Specifies the mode.*/ + uint32_t burstLength; /*!< Specifies the length of a burst to be transferred.*/ + uint32_t clockPhase; /*!< Specifies the clock phase.*/ + uint32_t clockPolarity; /*!< Specifies the clock polarity.*/ + bool ecspiAutoStart; /*!< Specifies the start mode.*/ +} ecspi_init_config_t; /******************************************************************************* * API @@ -178,49 +164,49 @@ extern "C" { #endif /*! - * @name ECSPI Initialization and Configuration functions + * @name eCSPI Initialization and Configuration functions * @{ */ - /*! - * @brief Initializes the ECSPI module. +/*! + * @brief Initializes the eCSPI module. * - * @param base: ECSPI base pointer. - * @param initStruct: pointer to a ecspi_init_t structure. + * @param base eCSPI base pointer. + * @param initConfig eCSPI initialize structure. */ -void ECSPI_Init(ECSPI_Type* base, ecspi_init_t* initStruct); +void ECSPI_Init(ECSPI_Type* base, const ecspi_init_config_t* initConfig); - /*! - * @brief Enables the specified ECSPI module. +/*! + * @brief Enables the specified eCSPI module. * - * @param base ECSPI base pointer. + * @param base eCSPI base pointer. */ static inline void ECSPI_Enable(ECSPI_Type* base) { - /* Enable the ECSPI */ + /* Enable the eCSPI. */ ECSPI_CONREG_REG(base) |= ECSPI_CONREG_EN_MASK; } - /*! - * @brief Disable the specified ECSPI module. +/*! + * @brief Disable the specified eCSPI module. * - * @param base ECSPI base pointer. + * @param base eCSPI base pointer. */ static inline void ECSPI_Disable(ECSPI_Type* base) { - /* Enable the ECSPI */ + /* Enable the eCSPI. */ ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_EN_MASK; } /*! * @brief Insert the number of wait states to be inserted in data transfers. * - * @param base ECSPI base pointer. + * @param base eCSPI base pointer. * @param number the number of wait states. */ static inline void ECSPI_InsertWaitState(ECSPI_Type* base, uint32_t number) { - /* Configure the number of wait states inserted */ + /* Configure the number of wait states inserted. */ ECSPI_PERIODREG_REG(base) = (ECSPI_PERIODREG_REG(base) & (~ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)) | ECSPI_PERIODREG_SAMPLE_PERIOD(number); } @@ -228,21 +214,21 @@ static inline void ECSPI_InsertWaitState(ECSPI_Type* base, uint32_t number) /*! * @brief Set the clock source for the sample period counter. * - * @param base ECSPI base pointer. - * @param source the clock source (see _ecspi_sampleperiod_clocksource). + * @param base eCSPI base pointer. + * @param source The clock source (see @ref _ecspi_sampleperiod_clocksource enumeration). */ void ECSPI_SetSampClockSource(ECSPI_Type* base, uint32_t source); /*! - * @brief Set the ECSPI clocks inserte between the chip select's active edge - * and the first ECSPI clock edge + * @brief Set the eCSPI clocks insert between the chip select active edge + * and the first eCSPI clock edge. * - * @param base ECSPI base pointer. - * @param delay the number of wait states. + * @param base eCSPI base pointer. + * @param delay The number of wait states. */ static inline void ECSPI_SetDelay(ECSPI_Type* base, uint32_t delay) { - /* Set the number of clocks inserte */ + /* Set the number of clocks insert. */ ECSPI_PERIODREG_REG(base) = (ECSPI_PERIODREG_REG(base) & (~ECSPI_PERIODREG_CSD_CTL_MASK)) | ECSPI_PERIODREG_CSD_CTL(delay); } @@ -250,13 +236,13 @@ static inline void ECSPI_SetDelay(ECSPI_Type* base, uint32_t delay) /*! * @brief Set the inactive state of SCLK. * - * @param base ECSPI base pointer. - * @param channel ECSPI channel select (see _ecspi_channel_select). - * @param state SCLK inactive state (see _ecspi_sclk_inactivestate). + * @param base eCSPI base pointer. + * @param channel eCSPI channel select (see @ref _ecspi_channel_select enumeration). + * @param state SCLK inactive state (see @ref _ecspi_sclk_inactivestate enumeration). */ static inline void ECSPI_SetSCLKInactiveState(ECSPI_Type* base, uint32_t channel, uint32_t state) { - /* Configure the inactive state of SCLK */ + /* Configure the inactive state of SCLK. */ ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SCLK_CTL(1 << channel))) | ECSPI_CONFIGREG_SCLK_CTL((state & 1) << channel); } @@ -264,13 +250,13 @@ static inline void ECSPI_SetSCLKInactiveState(ECSPI_Type* base, uint32_t channel /*! * @brief Set the inactive state of data line. * - * @param base ECSPI base pointer. - * @param channel ECSPI channel select (see _ecspi_channel_select). - * @param state Data line inactive state (see _ecspi_dataline_inactivestate). + * @param base eCSPI base pointer. + * @param channel eCSPI channel select (see @ref _ecspi_channel_select enumeration). + * @param state Data line inactive state (see @ref _ecspi_dataline_inactivestate enumeration). */ static inline void ECSPI_SetDataInactiveState(ECSPI_Type* base, uint32_t channel, uint32_t state) { - /* Set the inactive state of Data Line */ + /* Set the inactive state of Data Line. */ ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_DATA_CTL(1 << channel))) | ECSPI_CONFIGREG_DATA_CTL((state & 1) << channel); } @@ -278,32 +264,32 @@ static inline void ECSPI_SetDataInactiveState(ECSPI_Type* base, uint32_t channel /*! * @brief Trigger a burst. * - * @param base ECSPI base pointer. + * @param base eCSPI base pointer. */ static inline void ECSPI_StartBurst(ECSPI_Type* base) { - /* start a burst */ + /* Start a burst. */ ECSPI_CONREG_REG(base) |= ECSPI_CONREG_XCH_MASK; } /*! * @brief Set the burst length. * - * @param base ECSPI base pointer. - * @param length the value of burst length. + * @param base eCSPI base pointer. + * @param length The value of burst length. */ static inline void ECSPI_SetBurstLength(ECSPI_Type* base, uint32_t length) { - /* Set the burst length according to length */ + /* Set the burst length according to length. */ ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_BURST_LENGTH_MASK)) | ECSPI_CONREG_BURST_LENGTH(length); } /*! - * @brief Set ECSPI SS Wave Form. + * @brief Set eCSPI SS Wave Form. * - * @param base ECSPI base pointer. - * @param channel ECSPI channel selected (see _ecspi_channel_select). + * @param base eCSPI base pointer. + * @param channel eCSPI channel selected (see @ref _ecspi_channel_select enumeration). * @param ssMultiBurst For master mode, set true for multiple burst and false for one burst. * For slave mode, set true to complete burst by SS signal edges and false to complete * burst by number of bits received. @@ -316,11 +302,11 @@ static inline void ECSPI_SetSSMultipleBurst(ECSPI_Type* base, uint32_t channel, } /*! - * @brief Set ECSPI SS Polarity. + * @brief Set eCSPI SS Polarity. * - * @param base ECSPI base pointer. - * @param channel ECSPI channel selected (see _ecspi_channel_select). - * @param polarity set SS signal active logic (see _ecspi_ss_polarity). + * @param base eCSPI base pointer. + * @param channel eCSPI channel selected (see @ref _ecspi_channel_select enumeration). + * @param polarity Set SS signal active logic (see @ref _ecspi_ss_polarity enumeration). */ static inline void ECSPI_SetSSPolarity(ECSPI_Type* base, uint32_t channel, uint32_t polarity) { @@ -332,22 +318,22 @@ static inline void ECSPI_SetSSPolarity(ECSPI_Type* base, uint32_t channel, uint3 /*! * @brief Set the Data Ready Control. * - * @param base ECSPI base pointer. - * @param spidataready ECSPI data ready control (see _ecspi_data_ready). + * @param base eCSPI base pointer. + * @param spidataready eCSPI data ready control (see @ref _ecspi_data_ready enumeration). */ static inline void ECSPI_SetSPIDataReady(ECSPI_Type* base, uint32_t spidataready) { - /* Set the Data Ready Control */ + /* Set the Data Ready Control. */ ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_DRCTL_MASK)) | ECSPI_CONREG_DRCTL(spidataready); } /*! - * @brief Calculated the ECSPI baud rate in bits per second. + * @brief Calculated the eCSPI baud rate in bits per second. * The calculated baud rate must not exceed the desired baud rate. * - * @param base ECSPI base pointer. - * @param sourceClockInHz ECSPI Clock(SCLK) (in Hz). + * @param base eCSPI base pointer. + * @param sourceClockInHz eCSPI Clock(SCLK) (in Hz). * @param bitsPerSec the value of Baud Rate. * @return The calculated baud rate in bits-per-second, the nearest possible * baud rate without exceeding the desired baud rate. @@ -364,47 +350,48 @@ uint32_t ECSPI_SetBaudRate(ECSPI_Type* base, uint32_t sourceClockInHz, uint32_t /*! * @brief Transmits a data to TXFIFO. * - * @param base ECSPI base pointer. + * @param base eCSPI base pointer. * @param data Data to be transmitted. */ static inline void ECSPI_SendData(ECSPI_Type* base, uint32_t data) { - /* Write data to Transmit Data Register */ + /* Write data to Transmit Data Register. */ ECSPI_TXDATA_REG(base) = data; } /*! * @brief Receives a data from RXFIFO. - * @param base ECSPI base pointer. + * + * @param base eCSPI base pointer. * @return The value of received data. */ static inline uint32_t ECSPI_ReceiveData(ECSPI_Type* base) { - /* Read data from Receive Data Register */ + /* Read data from Receive Data Register. */ return ECSPI_RXDATA_REG(base); } /*! * @brief Read the number of words in the RXFIFO. * - * @param base ECSPI base pointer. + * @param base eCSPI base pointer. * @return The number of words in the RXFIFO. */ static inline uint32_t ECSPI_GetRxfifoCounter(ECSPI_Type* base) { - /* Get the number of words in the RXFIFO */ + /* Get the number of words in the RXFIFO. */ return ((ECSPI_TESTREG_REG(base) & ECSPI_TESTREG_RXCNT_MASK) >> ECSPI_TESTREG_RXCNT_SHIFT); } /*! * @brief Read the number of words in the TXFIFO. * - * @param base ECSPI base pointer. + * @param base eCSPI base pointer. * @return The number of words in the TXFIFO. */ static inline uint32_t ECSPI_GetTxfifoCounter(ECSPI_Type* base) { - /* Get the number of words in the RXFIFO */ + /* Get the number of words in the RXFIFO. */ return ((ECSPI_TESTREG_REG(base) & ECSPI_TESTREG_TXCNT_MASK) >> ECSPI_TESTREG_TXCNT_SHIFT); } @@ -418,21 +405,23 @@ static inline uint32_t ECSPI_GetTxfifoCounter(ECSPI_Type* base) /*! * @brief Enable or disable the specified DMA Source. * - * @param base ECSPI base pointer. - * @param source specifies DMA source (see _ecspi_dma_source). - * @param enable True or False. + * @param base eCSPI base pointer. + * @param source specifies DMA source (see @ref _ecspi_dma_source enumeration). + * @param enable Enable/Disable specified DMA Source. + * - true: Enable specified DMA Source. + * - false: Disable specified DMA Source. */ void ECSPPI_SetDMACmd(ECSPI_Type* base, uint32_t source, bool enable); /*! * @brief Set the burst length of a DMA operation. * - * @param base ECSPI base pointer. - * @param length specifies the burst length of a DMA operation. + * @param base eCSPI base pointer. + * @param length Specifies the burst length of a DMA operation. */ static inline void ECSPI_SetDMABurstLength(ECSPI_Type* base, uint32_t length) { - /* Configure the burst length of a DMA operation */ + /* Configure the burst length of a DMA operation. */ ECSPI_DMAREG_REG(base) = (ECSPI_DMAREG_REG(base) & (~ECSPI_DMAREG_RX_DMA_LENGTH_MASK)) | ECSPI_DMAREG_RX_DMA_LENGTH(length); } @@ -440,8 +429,8 @@ static inline void ECSPI_SetDMABurstLength(ECSPI_Type* base, uint32_t length) /*! * @brief Set the RXFIFO or TXFIFO threshold. * - * @param base ECSPI base pointer. - * @param fifo Data transfer fifo (see _ecspi_fifothreshold) + * @param base eCSPI base pointer. + * @param fifo Data transfer FIFO (see @ref _ecspi_fifothreshold enumeration). * @param threshold Threshold value. */ void ECSPI_SetFIFOThreshold(ECSPI_Type* base, uint32_t fifo, uint32_t threshold); @@ -454,36 +443,38 @@ void ECSPI_SetFIFOThreshold(ECSPI_Type* base, uint32_t fifo, uint32_t threshold) */ /*! - * @brief Enable or disable the specified ECSPI interrupts. + * @brief Enable or disable the specified eCSPI interrupts. * - * @param base ECSPI base pointer. - * @param flags ECSPI status flag mask (see _ecspi_status_flag for bit definition). - * @param enable Interrupt enable (true: enable, false: disable). + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). + * @param enable Interrupt enable. + * - true: Enable specified eCSPI interrupts. + * - false: Disable specified eCSPI interrupts. */ void ECSPI_SetIntCmd(ECSPI_Type* base, uint32_t flags, bool enable); /*! - * @brief Checks whether the specified ECSPI flag is set or not. + * @brief Checks whether the specified eCSPI flag is set or not. * - * @param base ECSPI base pointer. - * @param flags ECSPI status flag mask (see _ecspi_status_flag for bit definition). - * @return ECSPI status, each bit represents one status flag. + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). + * @return eCSPI status, each bit represents one status flag. */ static inline uint32_t ECSPI_GetStatusFlag(ECSPI_Type* base, uint32_t flags) { - /* return the vale of ECSPI status */ + /* return the vale of eCSPI status. */ return ECSPI_STATREG_REG(base) & flags; } /*! - * @brief Clear one or more ECSPI status flag. + * @brief Clear one or more eCSPI status flag. * - * @param base ECSPI base pointer. - * @param flags ECSPI status flag mask (see _ecspi_status_flag for bit definition). + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). */ static inline void ECSPI_ClearStatusFlag(ECSPI_Type* base, uint32_t flags) { - /* Write 1 to the status bit */ + /* Write 1 to the status bit. */ ECSPI_STATREG_REG(base) = flags; } diff --git a/platform/drivers/inc/flexcan.h b/platform/drivers/inc/flexcan.h index 8f27315..016952b 100644 --- a/platform/drivers/inc/flexcan.h +++ b/platform/drivers/inc/flexcan.h @@ -36,6 +36,18 @@ #include <assert.h> #include "device_imx.h" +/* Start of section using anonymous unions. */ +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + /*! * @addtogroup flexcan_driver * @{ @@ -45,124 +57,133 @@ * Definitions ******************************************************************************/ -/*! @brief FlexCAN message buffer CODE for Rx buffers */ -enum _flexcan_msgbuf_code_rx { - flexcanRxInactive = 0x0, /*!< MB is not active. */ - flexcanRxFull = 0x2, /*!< MB is full. */ - flexcanRxEmpty = 0x4, /*!< MB is active and empty. */ - flexcanRxOverrun = 0x6, /*!< MB is overwritten into a full buffer. */ - flexcanRxBusy = 0x8, /*!< FlexCAN is updating the contents of the MB. */ - /*! The CPU must not access the MB. */ - flexcanRxRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ - /*! and transmit a Response Frame in return. */ - flexcanRxNotUsed = 0xF /*!< Not used */ +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_msgbuf_code_rx +{ + flexcanRxInactive = 0x0, /*!< MB is not active. */ + flexcanRxFull = 0x2, /*!< MB is full. */ + flexcanRxEmpty = 0x4, /*!< MB is active and empty. */ + flexcanRxOverrun = 0x6, /*!< MB is overwritten into a full buffer. */ + flexcanRxBusy = 0x8, /*!< FlexCAN is updating the contents of the MB. */ + /*! The CPU must not access the MB. */ + flexcanRxRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ + /*! and transmit a Response Frame in return. */ + flexcanRxNotUsed = 0xF, /*!< Not used. */ }; -/*! @brief FlexCAN message buffer CODE FOR Tx buffers */ -enum _flexcan_msgbuf_code_tx { - flexcanTxInactive = 0x8, /*!< MB is not active. */ - flexcanTxAbort = 0x9, /*!< MB is aborted. */ - flexcanTxDataOrRemte = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ - /*!< MB is a TX Remote Request Frame (when MB RTR = 1). */ - flexcanTxTanswer = 0xE, /*!< MB is a TX Response Request Frame from. */ - /*! an incoming Remote Request Frame. */ - flexcanTxNotUsed = 0xF /*!< Not used */ +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_msgbuf_code_tx +{ + flexcanTxInactive = 0x8, /*!< MB is not active. */ + flexcanTxAbort = 0x9, /*!< MB is aborted. */ + flexcanTxDataOrRemte = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ + /*!< MB is a TX Remote Request Frame (when MB RTR = 1). */ + flexcanTxTanswer = 0xE, /*!< MB is a TX Response Request Frame from. */ + /*! an incoming Remote Request Frame. */ + flexcanTxNotUsed = 0xF, /*!< Not used. */ }; -/*! @brief FlexCAN operation modes */ -enum _flexcan_operatining_modes { - flexCanNormalMode = 0x1, /*!< Normal mode or user mode @internal gui name="Normal" */ - flexcanListenOnlyMode = 0x2, /*!< Listen-only mode @internal gui name="Listen-only" */ - flexcanLoopBackMode = 0x4, /*!< Loop-back mode @internal gui name="Loop back" */ +/*! @brief FlexCAN operation modes. */ +enum _flexcan_operatining_modes +{ + flexCanNormalMode = 0x1, /*!< Normal mode or user mode @internal gui name="Normal". */ + flexcanListenOnlyMode = 0x2, /*!< Listen-only mode @internal gui name="Listen-only". */ + flexcanLoopBackMode = 0x4, /*!< Loop-back mode @internal gui name="Loop back". */ }; -/*! @brief FlexCAN RX mask mode.*/ -enum _flexcan_rx_mask_mode { - flexcanRxMaskGlobal = 0x0, /*!< Rx global mask*/ - flexcanRxMaskIndividual = 0x1 /*!< Rx individual mask*/ +/*! @brief FlexCAN RX mask mode. */ +enum _flexcan_rx_mask_mode +{ + flexcanRxMaskGlobal = 0x0, /*!< Rx global mask. */ + flexcanRxMaskIndividual = 0x1, /*!< Rx individual mask. */ }; /*! @brief The ID type used in rx matching process. */ -enum _flexcan_rx_mask_id_type { - flexcanRxMaskIdStd = 0x0, /*!< Standard ID*/ - flexcanRxMaskIdExt = 0x1 /*!< Extended ID*/ +enum _flexcan_rx_mask_id_type +{ + flexcanRxMaskIdStd = 0x0, /*!< Standard ID. */ + flexcanRxMaskIdExt = 0x1, /*!< Extended ID. */ }; -/*! @brief Flexcan error interrupt source enumeration. */ -enum _flexcan_interrutpt { - flexcanIntRxWarning = 0x01, - flexcanIntTxWarning = 0x02, - flexcanIntWakeUp = 0x04, - flexcanIntBusOff = 0x08, - flexcanIntError = 0x10, +/*! @brief FlexCAN error interrupt source enumeration. */ +enum _flexcan_interrutpt +{ + flexcanIntRxWarning = 0x01, /*!< Tx Warning interrupt source. */ + flexcanIntTxWarning = 0x02, /*!< Tx Warning interrupt source. */ + flexcanIntWakeUp = 0x04, /*!< Wake Up interrupt source. */ + flexcanIntBusOff = 0x08, /*!< Bus Off interrupt source. */ + flexcanIntError = 0x10, /*!< Error interrupt source. */ }; -/*! @brief Flexcan error interrupt flags. */ -enum _flexcan_status_flag { - flexcanStatusSynch = CAN_ESR1_SYNCH_MASK, - flexcanStatusTxWarningInt = CAN_ESR1_TWRN_INT_MASK, - flexcanStatusRxWarningInt = CAN_ESR1_RWRN_INT_MASK, - flexcanStatusBit1Err = CAN_ESR1_BIT1_ERR_MASK, - flexcanStatusBit0Err = CAN_ESR1_BIT0_ERR_MASK, - flexcanStatusAckErr = CAN_ESR1_ACK_ERR_MASK, - flexcanStatusCrcErr = CAN_ESR1_CRC_ERR_MASK, - flexcanStatusFrameErr = CAN_ESR1_FRM_ERR_MASK, - flexcanStatusStuffingErr = CAN_ESR1_FRM_ERR_MASK, - flexcanStatusTxWarning = CAN_ESR1_TX_WRN_MASK, - flexcanStatusRxWarning = CAN_ESR1_RX_WRN_MASK, - flexcanStatusIdle = CAN_ESR1_IDLE_MASK, - flexcanStatusTransmitting = CAN_ESR1_TX_MASK, - flexcanStatusFltConf = CAN_ESR1_FLT_CONF_MASK, - flexcanStatusReceiving = CAN_ESR1_RX_MASK, - flexcanStatusBusOff = CAN_ESR1_BOFF_INT_MASK, - flexcanStatusError = CAN_ESR1_ERR_INT_MASK, - flexcanStatusWake = CAN_ESR1_WAK_INT_MASK +/*! @brief FlexCAN error interrupt flags. */ +enum _flexcan_status_flag +{ + flexcanStatusSynch = CAN_ESR1_SYNCH_MASK, /*!< Bus Synchronized flag. */ + flexcanStatusTxWarningInt = CAN_ESR1_TWRN_INT_MASK, /*!< Tx Warning initerrupt flag. */ + flexcanStatusRxWarningInt = CAN_ESR1_RWRN_INT_MASK, /*!< Tx Warning initerrupt flag. */ + flexcanStatusBit1Err = CAN_ESR1_BIT1_ERR_MASK, /*!< Bit0 Error flag. */ + flexcanStatusBit0Err = CAN_ESR1_BIT0_ERR_MASK, /*!< Bit1 Error flag. */ + flexcanStatusAckErr = CAN_ESR1_ACK_ERR_MASK, /*!< Ack Error flag. */ + flexcanStatusCrcErr = CAN_ESR1_CRC_ERR_MASK, /*!< CRC Error flag. */ + flexcanStatusFrameErr = CAN_ESR1_FRM_ERR_MASK, /*!< Frame Error flag. */ + flexcanStatusStuffingErr = CAN_ESR1_STF_ERR_MASK, /*!< Stuffing Error flag. */ + flexcanStatusTxWarning = CAN_ESR1_TX_WRN_MASK, /*!< Tx Warning flag. */ + flexcanStatusRxWarning = CAN_ESR1_RX_WRN_MASK, /*!< Rx Warning flag. */ + flexcanStatusIdle = CAN_ESR1_IDLE_MASK, /*!< FlexCAN Idle flag. */ + flexcanStatusTransmitting = CAN_ESR1_TX_MASK, /*!< Trasmitting flag. */ + flexcanStatusFltConf = CAN_ESR1_FLT_CONF_MASK, /*!< Fault Config flag. */ + flexcanStatusReceiving = CAN_ESR1_RX_MASK, /*!< Receiving flag. */ + flexcanStatusBusOff = CAN_ESR1_BOFF_INT_MASK, /*!< Bus Off interrupt flag. */ + flexcanStatusError = CAN_ESR1_ERR_INT_MASK, /*!< Error interrupt flag. */ + flexcanStatusWake = CAN_ESR1_WAK_INT_MASK, /*!< Wake Up interrupt flag. */ }; /*! @brief The id filter element type selection. */ -enum _flexcan_rx_fifo_id_element_format { - flexcanFxFifoIdElementFormatA = 0x0, /*!< One full ID (standard and extended) per ID Filter Table*/ - /*! element.*/ - flexcanFxFifoIdElementFormatB = 0x1, /*!< Two full standard IDs or two partial 14-bit (standard and*/ - /*! extended) IDs per ID Filter Table element.*/ - flexcanFxFifoIdElementFormatC = 0x2, /*!< Four partial 8-bit Standard IDs per ID Filter Table*/ - /*! element.*/ - flexcanFxFifoIdElementFormatD = 0x3 /*!< All frames rejected.*/ +enum _flexcan_rx_fifo_id_element_format +{ + flexcanRxFifoIdElementFormatA = 0x0, /*!< One full ID (standard and extended) per ID Filter Table element. */ + flexcanRxFifoIdElementFormatB = 0x1, /*!< Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. */ + flexcanRxFifoIdElementFormatC = 0x2, /*!< Four partial 8-bit Standard IDs per ID Filter Table element. */ + flexcanRxFifoIdElementFormatD = 0x3, /*!< All frames rejected. */ }; -/*! @brief FlexCAN Rx FIFO filters number*/ +/*! @brief FlexCAN Rx FIFO filters number. */ enum _flexcan_rx_fifo_filter_id_number { - flexcanRxFifoIdFilterNum8 = 0x0, /*!< 8 Rx FIFO Filters. @internal gui name="8 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum16 = 0x1, /*!< 16 Rx FIFO Filters. @internal gui name="16 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum24 = 0x2, /*!< 24 Rx FIFO Filters. @internal gui name="24 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum32 = 0x3, /*!< 32 Rx FIFO Filters. @internal gui name="32 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum40 = 0x4, /*!< 40 Rx FIFO Filters. @internal gui name="40 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum48 = 0x5, /*!< 48 Rx FIFO Filters. @internal gui name="48 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum56 = 0x6, /*!< 56 Rx FIFO Filters. @internal gui name="56 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum64 = 0x7, /*!< 64 Rx FIFO Filters. @internal gui name="64 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum72 = 0x8, /*!< 72 Rx FIFO Filters. @internal gui name="72 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum80 = 0x9, /*!< 80 Rx FIFO Filters. @internal gui name="80 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum88 = 0xA, /*!< 88 Rx FIFO Filters. @internal gui name="88 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum96 = 0xB, /*!< 96 Rx FIFO Filters. @internal gui name="96 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum104 = 0xC, /*!< 104 Rx FIFO Filters. @internal gui name="104 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum112 = 0xD, /*!< 112 Rx FIFO Filters. @internal gui name="112 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum120 = 0xE, /*!< 120 Rx FIFO Filters. @internal gui name="120 Rx FIFO Filters" */ - flexcanRxFifoIdFilterNum128 = 0xF, /*!< 128 Rx FIFO Filters. @internal gui name="128 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum8 = 0x0, /*!< 8 Rx FIFO Filters. @internal gui name="8 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum16 = 0x1, /*!< 16 Rx FIFO Filters. @internal gui name="16 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum24 = 0x2, /*!< 24 Rx FIFO Filters. @internal gui name="24 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum32 = 0x3, /*!< 32 Rx FIFO Filters. @internal gui name="32 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum40 = 0x4, /*!< 40 Rx FIFO Filters. @internal gui name="40 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum48 = 0x5, /*!< 48 Rx FIFO Filters. @internal gui name="48 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum56 = 0x6, /*!< 56 Rx FIFO Filters. @internal gui name="56 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum64 = 0x7, /*!< 64 Rx FIFO Filters. @internal gui name="64 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum72 = 0x8, /*!< 72 Rx FIFO Filters. @internal gui name="72 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum80 = 0x9, /*!< 80 Rx FIFO Filters. @internal gui name="80 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum88 = 0xA, /*!< 88 Rx FIFO Filters. @internal gui name="88 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum96 = 0xB, /*!< 96 Rx FIFO Filters. @internal gui name="96 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum104 = 0xC, /*!< 104 Rx FIFO Filters. @internal gui name="104 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum112 = 0xD, /*!< 112 Rx FIFO Filters. @internal gui name="112 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum120 = 0xE, /*!< 120 Rx FIFO Filters. @internal gui name="120 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum128 = 0xF, /*!< 128 Rx FIFO Filters. @internal gui name="128 Rx FIFO Filters" */ }; -/*! @brief FlexCAN RX FIFO ID filter table structure*/ -typedef struct FLEXCANIdTable { - bool isRemoteFrame; /*!< Remote frame*/ - bool isExtendedFrame; /*!< Extended frame*/ - uint32_t *idFilter; /*!< Rx FIFO ID filter elements*/ +/*! @brief FlexCAN RX FIFO ID filter table structure. */ +typedef struct FLEXCANIdTable +{ + uint32_t *idFilter; /*!< Rx FIFO ID filter elements. */ + bool isRemoteFrame; /*!< Remote frame. */ + bool isExtendedFrame; /*!< Extended frame. */ } flexcan_id_table_t; -/*! @brief FlexCAN message buffer structure*/ -typedef struct _flexcan_msgbuf { - union { - uint32_t cs; /*!< Code and Status*/ - struct { +/*! @brief FlexCAN message buffer structure. */ +typedef struct _flexcan_msgbuf +{ + union + { + uint32_t cs; /*!< Code and Status. */ + struct + { uint32_t timeStamp : 16; uint32_t dlc : 4; uint32_t rtr : 1; @@ -174,18 +195,22 @@ typedef struct _flexcan_msgbuf { }; }; - union{ - uint32_t id; /*!< Message Buffer ID*/ - struct { + union + { + uint32_t id; /*!< Message Buffer ID. */ + struct + { uint32_t idExt : 18; uint32_t idStd : 11; uint32_t prio : 3; }; }; - union{ - uint32_t word0; /*!< Bytes of the FlexCAN message*/ - struct { + union + { + uint32_t word0; /*!< Bytes of the FlexCAN message. */ + struct + { uint8_t data3; uint8_t data2; uint8_t data1; @@ -193,9 +218,11 @@ typedef struct _flexcan_msgbuf { }; }; - union{ - uint32_t word1; /*!< Bytes of the FlexCAN message*/ - struct { + union + { + uint32_t word1; /*!< Bytes of the FlexCAN message. */ + struct + { uint8_t data7; uint8_t data6; uint8_t data5; @@ -204,20 +231,22 @@ typedef struct _flexcan_msgbuf { }; } flexcan_msgbuf_t; -/*! @brief FlexCAN timing related structures*/ -typedef struct _flexcan_timing { - uint32_t preDiv; /*!< Clock pre divider*/ - uint32_t rJumpwidth; /*!< Resync jump width*/ - uint32_t phaseSeg1; /*!< Phase segment 1*/ - uint32_t phaseSeg2; /*!< Phase segment 1*/ - uint32_t propSeg; /*!< Propagation segment*/ +/*! @brief FlexCAN timing-related structures. */ +typedef struct _flexcan_timing +{ + uint32_t preDiv; /*!< Clock pre divider. */ + uint32_t rJumpwidth; /*!< Resync jump width. */ + uint32_t phaseSeg1; /*!< Phase segment 1. */ + uint32_t phaseSeg2; /*!< Phase segment 2. */ + uint32_t propSeg; /*!< Propagation segment. */ } flexcan_timing_t; -/*! @brief Flexcan module initialize structure. */ -typedef struct _flexcan_init_config { - flexcan_timing_t timing; /*!< Desired Flexcan module timing configuration. */ - uint32_t operatingMode; /*!< Desired Flexcan module operating mode. */ - uint8_t maxMsgBufNum; /*!< The maximal number of available message buffer. */ +/*! @brief FlexCAN module initialize structure. */ +typedef struct _flexcan_init_config +{ + flexcan_timing_t timing; /*!< Desired FlexCAN module timing configuration. */ + uint32_t operatingMode; /*!< Desired FlexCAN module operating mode. */ + uint8_t maxMsgBufNum; /*!< The maximal number of available message buffer. */ } flexcan_init_config_t; /******************************************************************************* @@ -234,29 +263,29 @@ extern "C" { */ /*! - * @brief Initialize Flexcan module with given initialize structure. + * @brief Initialize FlexCAN module with given initialize structure. * * @param base CAN base pointer. - * @param initConfig CAN initialize structure(see flexcan_init_config_t above). + * @param initConfig CAN initialize structure (see @ref flexcan_init_config_t structure). */ -void FLEXCAN_Init(CAN_Type* base, flexcan_init_config_t* initConfig); +void FLEXCAN_Init(CAN_Type* base, const flexcan_init_config_t* initConfig); /*! - * @brief This function reset Flexcan module register content to its default value. + * @brief This function reset FlexCAN module register content to its default value. * * @param base FlexCAN base pointer. */ void FLEXCAN_Deinit(CAN_Type* base); /*! - * @brief This function is used to Enable the Flexcan Module. + * @brief This function is used to Enable the FlexCAN Module. * * @param base FlexCAN base pointer. */ void FLEXCAN_Enable(CAN_Type* base); /*! - * @brief This function is used to Disable the CAN Module. + * @brief This function is used to Disable the FlexCAN Module. * * @param base FlexCAN base pointer. */ @@ -265,33 +294,33 @@ void FLEXCAN_Disable(CAN_Type* base); /*! * @brief Sets the FlexCAN time segments for setting up bit rate. * - * @param base FlexCAN base pointer. - * @param timing FlexCAN time segments, which need to be set for the bit rate. + * @param base FlexCAN base pointer. + * @param timing FlexCAN time segments, which need to be set for the bit rate (See @ref flexcan_timing_t structure). */ -void FLEXCAN_SetTiming(CAN_Type* base, flexcan_timing_t* timing); +void FLEXCAN_SetTiming(CAN_Type* base, const flexcan_timing_t* timing); /*! * @brief Set operation mode. * - * @param base FlexCAN base pointer. - * @param mode Set an operation mode. + * @param base FlexCAN base pointer. + * @param mode Set an operation mode. */ void FLEXCAN_SetOperatingMode(CAN_Type* base, uint8_t mode); /*! * @brief Set the maximum number of Message Buffers. * - * @param base FlexCAN base pointer. - * @param bufNum Maximum number of message buffers + * @param base FlexCAN base pointer. + * @param bufNum Maximum number of message buffers. */ void FLEXCAN_SetMaxMsgBufNum(CAN_Type* base, uint32_t bufNum); /*! - * @brief Get the working status of Flexcan module. + * @brief Get the working status of FlexCAN module. * - * @param base FlexCAN base pointer. - * @return true : FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode - * false : FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + * @param base FlexCAN base pointer. + * @return - true: FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode. + * - false: FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode. */ static inline bool FLEXCAN_IsModuleReady(CAN_Type* base) { @@ -299,63 +328,66 @@ static inline bool FLEXCAN_IsModuleReady(CAN_Type* base) } /*! - * @brief Set the Transmit abort feature enablement. + * @brief Set the Transmit Abort feature enablement. * - * @param base FlexCAN base pointer. - * @param enable - true : Enable Transmit Abort feature. - * - false : Disable Transmit Abort feature. + * @param base FlexCAN base pointer. + * @param enable Enable/Disable Transmit Abort feature. + * - true: Enable Transmit Abort feature. + * - false: Disable Transmit Abort feature. */ void FLEXCAN_SetAbortCmd(CAN_Type* base, bool enable); /*! * @brief Set the local transmit priority enablement. * - * @param base FlexCAN base pointer. - * @param enable - true : transmit MB with highest local priority. - * - false : transmit MB with lowest MB number. + * @param base FlexCAN base pointer. + * @param enable Enable/Disable local transmit periority. + * - true: Transmit MB with highest local priority. + * - false: Transmit MB with lowest MB number. */ void FLEXCAN_SetLocalPrioCmd(CAN_Type* base, bool enable); /*! * @brief Set the Rx matching process priority. * - * @param base FlexCAN base pointer. - * @param priority - true : Matching starts from Mailboxes and continues on Rx FIFO. - * - false : Matching starts from Rx FIFO and continues on Mailboxes. + * @param base FlexCAN base pointer. + * @param priority Set Rx matching process priority. + * - true: Matching starts from Mailboxes and continues on Rx FIFO. + * - false: Matching starts from Rx FIFO and continues on Mailboxes. */ void FLEXCAN_SetMatchPrioCmd(CAN_Type* base, bool priority); /*@}*/ /*! - * @name Flexcan Message buffer control functions + * @name FlexCAN Message buffer control functions * @{ */ /*! * @brief Get message buffer pointer for transition. * - * @param base FlexCAN base pointer. - * @param msgBufIdx message buffer index. - * @return message buffer pointer. + * @param base FlexCAN base pointer. + * @param msgBufIdx message buffer index. + * @return message buffer pointer. */ flexcan_msgbuf_t* FLEXCAN_GetMsgBufPtr(CAN_Type* base, uint8_t msgBufIdx); /*! * @brief Locks the FlexCAN Rx message buffer. * - * @param base FlexCAN base pointer. - * @param msgBuffIdx Index of the message buffer - * @return true : if successful; - * false : failed. + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer + * @return - true: Lock Rx Message Buffer successful. + * - false: Lock Rx Message Buffer failed. */ bool FLEXCAN_LockRxMsgBuf(CAN_Type* base, uint8_t msgBufIdx); /*! * @brief Unlocks the FlexCAN Rx message buffer. * - * @param base FlexCAN base pointer. - * @return current free run timer counter value. + * @param base FlexCAN base pointer. + * @return current free run timer counter value. */ uint16_t FLEXCAN_UnlockAllRxMsgBuf(CAN_Type* base); @@ -369,61 +401,64 @@ uint16_t FLEXCAN_UnlockAllRxMsgBuf(CAN_Type* base); /*! * @brief Enables/Disables the FlexCAN Message Buffer interrupt. * - * @param base FlexCAN base pointer. - * @param msgBuffIdx Index of the message buffer. - * @param enable Choose enable or disable. + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @param enable Enables/Disables interrupt. + * - true: Enable Message Buffer interrupt. + * - disable: Disable Message Buffer interrupt. */ void FLEXCAN_SetMsgBufIntCmd(CAN_Type* base, uint8_t msgBufIdx, bool enable); /*! * @brief Gets the individual FlexCAN MB interrupt flag. * - * @param base FlexCAN base pointer. - * @param msgBuffIdx Index of the message buffer. - * @return the individual Message Buffer interrupt flag (true and false are the flag value). + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @retval true: Message Buffer Interrupt is pending. + * @retval false: There is no Message Buffer Interrupt. */ bool FLEXCAN_GetMsgBufStatusFlag(CAN_Type* base, uint8_t msgBufIdx); /*! * @brief Clears the interrupt flag of the message buffers. * - * @param base FlexCAN base pointer. - * @param msgBuffIdx Index of the message buffer. + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. */ void FLEXCAN_ClearMsgBufStatusFlag(CAN_Type* base, uint32_t msgBufIdx); /*! * @brief Enables error interrupt of the FlexCAN module. * - * @param base FlexCAN base pointer. - * @param errorSrc The interrupt source. - * @param enable Choose enable or disable. + * @param base FlexCAN base pointer. + * @param errorSrc The interrupt source (see @ref _flexcan_interrutpt enumeration). + * @param enable Choose enable or disable. */ void FLEXCAN_SetErrIntCmd(CAN_Type* base, uint32_t errorSrc, bool enable); /*! * @brief Gets the FlexCAN module interrupt flag. * - * @param base FlexCAN base pointer. - * @param errFlags Flexcan error flags. - * @return the individual Message Buffer interrupt flag (0 and 1 are the flag value) + * @param base FlexCAN base pointer. + * @param errFlags FlexCAN error flags (see @ref _flexcan_status_flag enumeration). + * @return The individual Message Buffer interrupt flag (0 and 1 are the flag value) */ uint32_t FLEXCAN_GetErrStatusFlag(CAN_Type* base, uint32_t errFlags); /*! * @brief Clears the interrupt flag of the FlexCAN module. * - * @param base FlexCAN base pointer. - * @param errFlags The value to be written to the interrupt flag1 register. + * @param base FlexCAN base pointer. + * @param errFlags The value to be written to the interrupt flag1 register (see @ref _flexcan_status_flag enumeration). */ void FLEXCAN_ClearErrStatusFlag(CAN_Type* base, uint32_t errFlags); /*! * @brief Get the error counter of FlexCAN module. * - * @param base FlexCAN base pointer. - * @param txError Tx_Err_Counter pointer. - * @param rxError Rx_Err_Counter pointer. + * @param base FlexCAN base pointer. + * @param txError Tx_Err_Counter pointer. + * @param rxError Rx_Err_Counter pointer. */ void FLEXCAN_GetErrCounter(CAN_Type* base, uint8_t* txError, uint8_t* rxError); @@ -437,40 +472,40 @@ void FLEXCAN_GetErrCounter(CAN_Type* base, uint8_t* txError, uint8_t* rxError); /*! * @brief Enables the Rx FIFO. * - * @param base FlexCAN base pointer. - * @param numOfFilters The number of Rx FIFO filters + * @param base FlexCAN base pointer. + * @param numOfFilters The number of Rx FIFO filters */ void FLEXCAN_EnableRxFifo(CAN_Type* base, uint8_t numOfFilters); /*! * @brief Disables the Rx FIFO. * - * @param base FlexCAN base pointer. + * @param base FlexCAN base pointer. */ void FLEXCAN_DisableRxFifo(CAN_Type* base); /*! * @brief Set the number of the Rx FIFO filters. * - * @param base FlexCAN base pointer. - * @param number The number of Rx FIFO filters. + * @param base FlexCAN base pointer. + * @param numOfFilters The number of Rx FIFO filters. */ void FLEXCAN_SetRxFifoFilterNum(CAN_Type* base, uint32_t numOfFilters); /*! * @brief Set the FlexCAN Rx FIFO fields. * - * @param base FlexCAN base pointer. - * @param idFormat The format of the Rx FIFO ID Filter Table Elements - * @param idFilterTable The ID filter table elements which contain RTR bit, IDE bit and RX message ID. + * @param base FlexCAN base pointer. + * @param idFormat The format of the Rx FIFO ID Filter Table Elements + * @param idFilterTable The ID filter table elements which contain RTR bit, IDE bit and RX message ID. */ void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table_t *idFilterTable); /*! * @brief Gets the FlexCAN Rx FIFO data pointer. * - * @param base FlexCAN base pointer. - * @return Rx FIFO data pointer. + * @param base FlexCAN base pointer. + * @return Rx FIFO data pointer. */ flexcan_msgbuf_t* FLEXCAN_GetRxFifoPtr(CAN_Type* base); @@ -478,8 +513,8 @@ flexcan_msgbuf_t* FLEXCAN_GetRxFifoPtr(CAN_Type* base); * @brief Gets the FlexCAN Rx FIFO information. * The return value indicates which Identifier Acceptance Filter * (see Rx FIFO Structure) was hit by the received message. - * @param base FlexCAN base pointer. - * @return Rx FIFO filter number. + * @param base FlexCAN base pointer. + * @return Rx FIFO filter number. */ uint16_t FLEXCAN_GetRxFifoInfo(CAN_Type* base); @@ -493,58 +528,59 @@ uint16_t FLEXCAN_GetRxFifoInfo(CAN_Type* base); /*! * @brief Set the Rx masking mode. * - * @param base FlexCAN base pointer. - * @param mode The FlexCAN Rx mask mode: can be set to global mode and individual mode. + * @param base FlexCAN base pointer. + * @param mode The FlexCAN Rx mask mode (see @ref _flexcan_rx_mask_mode enumeration). */ void FLEXCAN_SetRxMaskMode(CAN_Type* base, uint32_t mode); /*! * @brief Set the remote trasmit request mask enablement. * - * @param base FlexCAN base pointer. - * @param enable - true : Enable RTR matching judgement. - * false : Disable RTR matching judgement. + * @param base FlexCAN base pointer. + * @param enable Enable/Disable remote trasmit request mask. + * - true: Enable RTR matching judgement. + * - false: Disable RTR matching judgement. */ -void FLEXCAN_SetRxMaskRtrCmd(CAN_Type* base, uint32_t enable); +void FLEXCAN_SetRxMaskRtrCmd(CAN_Type* base, bool enable); /*! * @brief Set the FlexCAN RX global mask. * - * @param base FlexCAN base pointer. - * @param mask Rx Global mask. + * @param base FlexCAN base pointer. + * @param mask Rx Global mask. */ void FLEXCAN_SetRxGlobalMask(CAN_Type* base, uint32_t mask); /*! * @brief Set the FlexCAN Rx individual mask for ID filtering in the Rx MBs and the Rx FIFO. * - * @param base FlexCAN base pointer. - * @param msgBufIdx Index of the message buffer. - * @param mask Individual mask + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @param mask Individual mask */ void FLEXCAN_SetRxIndividualMask(CAN_Type* base, uint32_t msgBufIdx, uint32_t mask); /*! * @brief Set the FlexCAN RX Message Buffer BUF14 mask. * - * @param base FlexCAN base pointer. - * @param mask Message Buffer BUF14 mask. + * @param base FlexCAN base pointer. + * @param mask Message Buffer BUF14 mask. */ void FLEXCAN_SetRxMsgBuff14Mask(CAN_Type* base, uint32_t mask); /*! * @brief Set the FlexCAN RX Message Buffer BUF15 mask. * - * @param base FlexCAN base pointer. - * @param mask Message Buffer BUF15 mask. + * @param base FlexCAN base pointer. + * @param mask Message Buffer BUF15 mask. */ void FLEXCAN_SetRxMsgBuff15Mask(CAN_Type* base, uint32_t mask); /*! * @brief Set the FlexCAN RX Fifo global mask. * - * @param base FlexCAN base pointer. - * @param mask Rx Fifo Global mask. + * @param base FlexCAN base pointer. + * @param mask Rx Fifo Global mask. */ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type* base, uint32_t mask); @@ -558,62 +594,67 @@ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type* base, uint32_t mask); /*! * @brief Enable/disable the FlexCAN self wakeup feature. * - * @param base FlexCAN base pointer. - * @param lpfEnable The low pass filter for Rx self wakeup feature enablement. - * @param enable The self wakeup feature enablement. + * @param base FlexCAN base pointer. + * @param lpfEnable The low pass filter for Rx self wakeup feature enablement. + * @param enable The self wakeup feature enablement. */ void FLEXCAN_SetSelfWakeUpCmd(CAN_Type* base, bool lpfEnable, bool enable); /*! - * @brief Enable/disable the FlexCAN self reception feature. + * @brief Enable/Disable the FlexCAN self reception feature. * - * @param base FlexCAN base pointer. - * @param enable - true : enable self reception feature. - * false : disable self reception feature. + * @param base FlexCAN base pointer. + * @param enable Enable/Disable self reception feature. + * - true: Enable self reception feature. + * - false: Disable self reception feature. */ void FLEXCAN_SetSelfReceptionCmd(CAN_Type* base, bool enable); /*! * @brief Enable/disable the enhance FlexCAN Rx vote. * - * @param base FlexCAN base pointer. - * @param enable - true : Three samples are used to determine the value of the received bit. - * false : Just one sample is used to determine the bit value. + * @param base FlexCAN base pointer. + * @param enable Enable/Disable FlexCAN Rx vote mechanism + * - true: Three samples are used to determine the value of the received bit. + * - false: Just one sample is used to determine the bit value. */ void FLEXCAN_SetRxVoteCmd(CAN_Type* base, bool enable); /*! * @brief Enable/disable the Auto Busoff recover feature. * - * @param base FlexCAN base pointer. - * @param enable - true : Enable Auto Bus Off recover feature. - * false : Disable Auto Bus Off recover feature. + * @param base FlexCAN base pointer. + * @param enable Enable/Disable Auto Busoff Recover + * - true: Enable Auto Bus Off recover feature. + * - false: Disable Auto Bus Off recover feature. */ void FLEXCAN_SetAutoBusOffRecoverCmd(CAN_Type* base, bool enable); /*! * @brief Enable/disable the Time Sync feature. * - * @param base FlexCAN base pointer. - * @param enable - true : Enable Time Sync feature. - * false : Disable Time Sync feature. + * @param base FlexCAN base pointer. + * @param enable Enable/Disable the Time Sync + * - true: Enable Time Sync feature. + * - false: Disable Time Sync feature. */ void FLEXCAN_SetTimeSyncCmd(CAN_Type* base, bool enable); /*! * @brief Enable/disable the Auto Remote Response feature. * - * @param base FlexCAN base pointer. - * @param enable - true : Enable Auto Remote Response feature. - * false : Disable Auto Remote Response feature. + * @param base FlexCAN base pointer. + * @param enable Enable/Disable the Auto Remote Response feature + * - true: Enable Auto Remote Response feature. + * - false: Disable Auto Remote Response feature. */ void FLEXCAN_SetAutoRemoteResponseCmd(CAN_Type* base, bool enable); /*! * @brief Enable/disable the Glitch Filter Width when FLEXCAN enters the STOP mode. * - * @param base FlexCAN base pointer. - * @param filterWidth The Glitch Filter Width. + * @param base FlexCAN base pointer. + * @param filterWidth The Glitch Filter Width. */ static inline void FLEXCAN_SetGlitchFilterWidth(CAN_Type* base, uint8_t filterWidth) { @@ -623,10 +664,10 @@ static inline void FLEXCAN_SetGlitchFilterWidth(CAN_Type* base, uint8_t filterWi /*! * @brief Get the lowest inactive message buffer number. * - * @param base FlexCAN base pointer. - * @return bit 22-16 : the lowest number inactive Mailbox. - * bit 14 : indicates whether the number content is valid or not. - * bit 13 : this bit indicates whether there is any inactive Mailbox. + * @param base FlexCAN base pointer. + * @return bit 22-16 : The lowest number inactive Mailbox. + * bit 14 : Indicates whether the number content is valid or not. + * bit 13 : This bit indicates whether there is any inactive Mailbox. */ static inline uint32_t FLEXCAN_GetLowestInactiveMsgBuf(CAN_Type* base) { @@ -636,10 +677,10 @@ static inline uint32_t FLEXCAN_GetLowestInactiveMsgBuf(CAN_Type* base) /*! * @brief Set the Tx Arbitration Start Delay number. * This function is used to optimize the transmit performance. - * For more information about to set this value, please refer to RM. + * For more information about to set this value, see the Chip Reference Manual. * - * @param base FlexCAN base pointer. - * @return tasd The lowest number inactive Mailbox. + * @param base FlexCAN base pointer. + * @param tasd The lowest number inactive Mailbox. */ static inline void FLEXCAN_SetTxArbitrationStartDelay(CAN_Type* base, uint8_t tasd) { @@ -655,6 +696,16 @@ static inline void FLEXCAN_SetTxArbitrationStartDelay(CAN_Type* base, uint8_t ta /*! @}*/ +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + #endif /* __FLEXCAN_H__ */ /******************************************************************************* * EOF diff --git a/platform/drivers/inc/gpio_imx.h b/platform/drivers/inc/gpio_imx.h index 1cf60e7..1af7ceb 100644 --- a/platform/drivers/inc/gpio_imx.h +++ b/platform/drivers/inc/gpio_imx.h @@ -45,34 +45,37 @@ * Definitions ******************************************************************************/ -/*! @brief GPIO direction definition */ -typedef enum _gpio_pin_direction { - gpioDigitalInput = 0U, /*!< Set current pin as digital input*/ - gpioDigitalOutput = 1U /*!< Set current pin as digital output*/ +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + gpioDigitalInput = 0U, /*!< Set current pin as digital input.*/ + gpioDigitalOutput = 1U, /*!< Set current pin as digital output.*/ } gpio_pin_direction_t; -/*! @brief GPIO interrupt mode definition*/ -typedef enum _gpio_interrupt_mode { - gpioIntLowLevel = 0U, /*!< Set current pin interrupt is low-level sensitive.*/ - gpioIntHighLevel = 1U, /*!< Set current pin interrupt is high-level sensitive.*/ - gpioIntRisingEdge = 2U, /*!< Set current pin interrupt is rising-edge sensitive.*/ - gpioIntFallingEdge = 3U, /*!< Set current pin interrupt is falling-edge sensitive.*/ - gpioNoIntmode = 4U /*!< Set current pin general IO functionality. */ +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + gpioIntLowLevel = 0U, /*!< Set current pin interrupt is low-level sensitive.*/ + gpioIntHighLevel = 1U, /*!< Set current pin interrupt is high-level sensitive.*/ + gpioIntRisingEdge = 2U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + gpioIntFallingEdge = 3U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + gpioNoIntmode = 4U, /*!< Set current pin general IO functionality. */ } gpio_interrupt_mode_t; -/*! @brief GPIO pin(bit) value definition */ -typedef enum _gpio_pin_action { - gpioPinClear = 0U, - gpioPinSet = 1U +/*! @brief GPIO pin(bit) value definition. */ +typedef enum _gpio_pin_action +{ + gpioPinClear = 0U, /*!< Clear GPIO Pin.*/ + gpioPinSet = 1U, /*!< Set GPIO Pin.*/ } gpio_pin_action_t; -/*! @brief GPIO Init structure definition */ -typedef struct GpioInit +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_init_config { - uint32_t pin; /*!< Specifies the pin number. */ - gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ - gpio_interrupt_mode_t interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ -} gpio_init_t; + uint32_t pin; /*!< Specifies the pin number. */ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + gpio_interrupt_mode_t interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_init_config_t; /******************************************************************************* * API @@ -89,13 +92,13 @@ extern "C" { /*! * @brief Initializes the GPIO peripheral according to the specified - * parameters in the initStruct. + * parameters in the initConfig. * - * @param base GPIO base pointer (GPIO1, GPIO2, GPIO3, etc.). - * @param initStruct pointer to a gpio_init_t structure that - * contains the configuration information. + * @param base GPIO base pointer. + * @param initConfig pointer to a @ref gpio_init_config_t structure that + * contains the configuration information. */ -void GPIO_Init(GPIO_Type* base, gpio_init_t* initStruct); +void GPIO_Init(GPIO_Type* base, const gpio_init_config_t* initConfig); /*@}*/ @@ -104,18 +107,17 @@ void GPIO_Init(GPIO_Type* base, gpio_init_t* initStruct); * @{ */ - /*! +/*! * @brief Reads the current input value of the pin when pin's direction is configured as input. * - * @param base GPIO base pointer (GPIO1, GPIO2, GPIO3, etc.). + * @param base GPIO base pointer. * @param pin GPIO port pin number. * @return GPIO pin input value. - * - 0: Pin logic level is 0, or is not configured for use by digital function. - * - 1: Pin logic level is 1. */ static inline uint8_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) { assert(pin < 32); + return (uint8_t)((GPIO_DR_REG(base) >> pin) & 1U); } @@ -123,14 +125,10 @@ static inline uint8_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) * @brief Reads the current input value of a specific GPIO port when port's direction are all configured as input. * This function gets all 32-pin input as a 32-bit integer. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.) - * @return GPIO port input data. Each bit represents one pin. For each bit: - * - 0: Pin logic level is 0, or is not configured for use by digital function. - * - 1: Pin logic level is 1. - * - LSB: pin 0 - * - MSB: pin 31 + * @param base GPIO base pointer. + * @return GPIO port input data. */ -static inline uint32_t GPIO_ReadPortInput(GPIO_Type *base) +static inline uint32_t GPIO_ReadPortInput(GPIO_Type* base) { return GPIO_DR_REG(base); } @@ -138,26 +136,23 @@ static inline uint32_t GPIO_ReadPortInput(GPIO_Type *base) /*! * @brief Reads the current pin output. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.) + * @param base GPIO base pointer. * @param pin GPIO port pin number. - * @return current pin output value, 0 - Low logic, 1 - High logic. + * @return Current pin output value. */ static inline uint8_t GPIO_ReadPinOutput(GPIO_Type* base, uint32_t pin) { assert(pin < 32); + return (uint8_t)((GPIO_DR_REG(base) >> pin) & 0x1U); } /*! * @brief Reads out all pin output status of the current port. - * This function operates all 32 port pins. + * This function operates all 32 port pins. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.) - * @return current port output status. Each bit represents one pin. For each bit: - * - 0: corresponding pin is outputting logic level 0 - * - 1: corresponding pin is outputting logic level 1 - * - LSB: pin 0 - * - MSB: pin 31 + * @param base GPIO base pointer. + * @return Current port output status. */ static inline uint32_t GPIO_ReadPortOutput(GPIO_Type* base) { @@ -167,11 +162,9 @@ static inline uint32_t GPIO_ReadPortOutput(GPIO_Type* base) /*! * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.) + * @param base GPIO base pointer. * @param pin GPIO port pin number. - * @param pinVal pin output value, one of the follow. - * -gpioPinClear: logic 0; - * -gpioPinSet: logic 1. + * @param pinVal pin output value (See @ref gpio_pin_action_t structure). */ void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal); @@ -179,12 +172,8 @@ void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal * @brief Sets the output of the GPIO port pins to a specific logic value. * This function operates all 32 port pins. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.) - * @param portVal data to configure the GPIO output. Each bit represents one pin. For each bit: - * - 0: set logic level 0 to pin - * - 1: set logic level 1 to pin - * - LSB: pin 0 - * - MSB: pin 31 + * @param base GPIO base pointer. + * @param portVal data to configure the GPIO output. */ static inline void GPIO_WritePortOutput(GPIO_Type* base, uint32_t portVal) { @@ -201,15 +190,14 @@ static inline void GPIO_WritePortOutput(GPIO_Type* base, uint32_t portVal) /*! * @brief Reads the current GPIO pin pad status. * - * @param base GPIO base pointer (GPIO1, GPIO2, GPIO3, etc.). + * @param base GPIO base pointer. * @param pin GPIO port pin number. * @return GPIO pin pad status value. - * - 0: Pin pad status logic level is 0. - * - 1: Pin pad status logic level is 1. */ static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) { assert(pin < 32); + return (uint8_t)((GPIO_PSR_REG(base) >> pin) & 1U); } @@ -221,26 +209,27 @@ static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) */ /*! - * @brief Disable or enable the specific pin interrupt. + * @brief Enable or Disable the specific pin interrupt. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.). + * @param base GPIO base pointer. * @param pin GPIO pin number. - * @param enable enable or disable interrupt. + * @param enable Enable or disable interrupt. + * - true: Enable GPIO interrupt. + * - false: Disable GPIO interrupt. */ void GPIO_SetPinIntMode(GPIO_Type* base, uint32_t pin, bool enable); /*! * @brief Check individual pin interrupt status. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.) + * @param base GPIO base pointer. * @param pin GPIO port pin number. * @return current pin interrupt status flag. - * - 0: interrupt is not detected. - * - 1: interrupt is detected. */ static inline bool GPIO_IsIntPending(GPIO_Type* base, uint32_t pin) { assert(pin < 32); + return (bool)((GPIO_ISR_REG(base) >> pin) & 1U); } @@ -248,22 +237,23 @@ static inline bool GPIO_IsIntPending(GPIO_Type* base, uint32_t pin) * @brief Clear pin interrupt flag. Status flags are cleared by * writing a 1 to the corresponding bit position. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.) + * @param base GPIO base pointer. * @param pin GPIO port pin number. */ static inline void GPIO_ClearStatusFlag(GPIO_Type* base, uint32_t pin) { assert(pin < 32); - GPIO_ISR_REG(base) |= (1U << pin); + + GPIO_ISR_REG(base) = (1U << pin); } /*! - * @brief Disable or enable the edge select bit to override + * @brief Enable or disable the edge select bit to override * the ICR register's configuration. * - * @param base GPIO base pointer(GPIO1, GPIO2, GPIO3, etc.). + * @param base GPIO base pointer. * @param pin GPIO port pin number. - * @param enable enable or disable. + * @param enable Enable or disable edge select bit. */ void GPIO_SetIntEdgeSelect(GPIO_Type* base, uint32_t pin, bool enable); diff --git a/platform/drivers/inc/gpt.h b/platform/drivers/inc/gpt.h index 14c3b9e..3c95c1b 100644 --- a/platform/drivers/inc/gpt.h +++ b/platform/drivers/inc/gpt.h @@ -45,78 +45,70 @@ * Definitions ******************************************************************************/ -/*! - * @brief Clock source - */ -enum _gpt_clock_source { - gptClockSourceNone = 0U, /*!< No source selected.*/ - gptClockSourcePeriph = 1U, /*!< Use peripheral module clock.*/ - gptClockSourceLowFreq = 4U, /*!< Use 32K clock.*/ - gptClockSourceOsc = 5U /*!< Use 24M OSC clock.*/ +/*! @brief Clock source. */ +enum _gpt_clock_source +{ + gptClockSourceNone = 0U, /*!< No source selected.*/ + gptClockSourcePeriph = 1U, /*!< Use peripheral module clock.*/ + gptClockSourceLowFreq = 4U, /*!< Use 32 K clock.*/ + gptClockSourceOsc = 5U, /*!< Use 24 M OSC clock.*/ }; -/*! - * @brief Input capture channel number - */ -enum _gpt_input_capture_channel { - gptInputCaptureChannel1 = 0U, - gptInputCaptureChannel2 = 1U +/*! @brief Input capture channel number. */ +enum _gpt_input_capture_channel +{ + gptInputCaptureChannel1 = 0U, /*!< Input Capture Channel1.*/ + gptInputCaptureChannel2 = 1U, /*!< Input Capture Channel2.*/ }; -/*! - * @brief Input capture operation mode - */ -enum _gpt_input_operation_mode { - gptInputOperationDisabled = 0U, /*!< Don't capture.*/ - gptInputOperationRiseEdge = 1U, /*!< Capture on rising edge of input pin.*/ - gptInputOperationFallEdge = 2U, /*!< Capture on falling edge of input pin.*/ - gptInputOperationBothEdge = 3U /*!< Capture on both edges of input pin.*/ +/*! @brief Input capture operation mode. */ +enum _gpt_input_operation_mode +{ + gptInputOperationDisabled = 0U, /*!< Don't capture.*/ + gptInputOperationRiseEdge = 1U, /*!< Capture on rising edge of input pin.*/ + gptInputOperationFallEdge = 2U, /*!< Capture on falling edge of input pin.*/ + gptInputOperationBothEdge = 3U, /*!< Capture on both edges of input pin.*/ }; -/*! - * @brief Output compare channel number - */ -enum _gpt_output_compare_channel { - gptOutputCompareChannel1 = 0U, - gptOutputCompareChannel2 = 1U, - gptOutputCompareChannel3 = 2U +/*! @brief Output compare channel number. */ +enum _gpt_output_compare_channel +{ + gptOutputCompareChannel1 = 0U, /*!< Output Compare Channel1.*/ + gptOutputCompareChannel2 = 1U, /*!< Output Compare Channel2.*/ + gptOutputCompareChannel3 = 2U, /*!< Output Compare Channel3.*/ }; -/*! - * @brief Output compare operation mode - */ -enum _gpt_output_operation_mode { - gptOutputOperationDisconnected = 0U, /*!< Don't change output pin.*/ - gptOutputOperationToggle = 1U, /*!< Toggle output pin.*/ - gptOutputOperationClear = 2U, /*!< Set output pin low.*/ - gptOutputOperationSet = 3U, /*!< Set output pin high.*/ - gptOutputOperationActivelow = 4U /*!< Generate a active low pulse on output pin.*/ +/*! @brief Output compare operation mode. */ +enum _gpt_output_operation_mode +{ + gptOutputOperationDisconnected = 0U, /*!< Don't change output pin.*/ + gptOutputOperationToggle = 1U, /*!< Toggle output pin.*/ + gptOutputOperationClear = 2U, /*!< Set output pin low.*/ + gptOutputOperationSet = 3U, /*!< Set output pin high.*/ + gptOutputOperationActivelow = 4U, /*!< Generate a active low pulse on output pin.*/ }; -/*! - * @brief Status flag - */ -enum _gpt_status_flag { - gptStatusFlagOutputCompare1 = 1U << 0, /*!< Output compare channel 1 evevnt.*/ - gptStatusFlagOutputCompare2 = 1U << 1, /*!< Output compare channel 2 evevnt.*/ - gptStatusFlagOutputCompare3 = 1U << 2, /*!< Output compare channel 3 evevnt.*/ - gptStatusFlagInputCapture1 = 1U << 3, /*!< Capture channel 1 evevnt.*/ - gptStatusFlagInputCapture2 = 1U << 4, /*!< Capture channel 2 evevnt.*/ - gptStatusFlagRollOver = 1U << 5 /*!< Counter reaches maximum value and rolled over to 0 evevnt.*/ +/*! @brief Status flag. */ +enum _gpt_status_flag +{ + gptStatusFlagOutputCompare1 = 1U << 0, /*!< Output compare channel 1 event.*/ + gptStatusFlagOutputCompare2 = 1U << 1, /*!< Output compare channel 2 event.*/ + gptStatusFlagOutputCompare3 = 1U << 2, /*!< Output compare channel 3 event.*/ + gptStatusFlagInputCapture1 = 1U << 3, /*!< Capture channel 1 event.*/ + gptStatusFlagInputCapture2 = 1U << 4, /*!< Capture channel 2 event.*/ + gptStatusFlagRollOver = 1U << 5, /*!< Counter reaches maximum value and rolled over to 0 event.*/ }; -/*! - * @brief Structure to configure the running mode. - */ -typedef struct GptModeConfig +/*! @brief Structure to configure the running mode. */ +typedef struct _gpt_init_config { - bool freeRun; /*!< true: FreeRun mode, false: Restart mode */ - bool waitEnable; /*!< GPT enabled in wait mode */ - bool stopEnable; /*!< GPT enabled in stop mode */ - bool dozeEnable; /*!< GPT enabled in doze mode */ - bool dbgEnable; /*!< GPT enabled in debug mode */ - bool enableMode; /*!< true: counter reset to 0 when enabled, false: counter retain its value when enabled */ -} gpt_mode_config_t; + bool freeRun; /*!< true: FreeRun mode, false: Restart mode. */ + bool waitEnable; /*!< GPT enabled in wait mode. */ + bool stopEnable; /*!< GPT enabled in stop mode. */ + bool dozeEnable; /*!< GPT enabled in doze mode. */ + bool dbgEnable; /*!< GPT enabled in debug mode. */ + bool enableMode; /*!< true: counter reset to 0 when enabled, false: counter retain its value when enabled. */ +} gpt_init_config_t; /******************************************************************************* * API @@ -132,117 +124,119 @@ extern "C" { */ /*! - * @brief Initialize GPT to reset state and initialize running mode + * @brief Initialize GPT to reset state and initialize running mode. * * @param base GPT base pointer. - * @param config GPT mode setting configuration. + * @param initConfig GPT mode setting configuration. */ -void GPT_Init(GPT_Type * base, gpt_mode_config_t *config); +void GPT_Init(GPT_Type* base, const gpt_init_config_t* initConfig); /*! - * @brief Software reset of GPT module + * @brief Software reset of GPT module. * * @param base GPT base pointer. */ -static inline void GPT_SoftReset(GPT_Type * base) +static inline void GPT_SoftReset(GPT_Type* base) { base->CR |= GPT_CR_SWR_MASK; - /* Wait reset finished */ - while (base->CR & GPT_CR_SWR_MASK) { } + /* Wait reset finished. */ + while (base->CR & GPT_CR_SWR_MASK) {}; } /*! - * @brief Set clock source of GPT + * @brief Set clock source of GPT. * * @param base GPT base pointer. - * @param source clock source (see _gpt_clock_source) + * @param source Clock source (see @ref _gpt_clock_source enumeration). */ -void GPT_SetClockSource(GPT_Type * base, uint32_t source); +void GPT_SetClockSource(GPT_Type* base, uint32_t source); /*! - * @brief Get clock source of GPT + * @brief Get clock source of GPT. * * @param base GPT base pointer. - * @return clock source (see _gpt_clock_source) + * @return clock source (see @ref _gpt_clock_source enumeration). */ -static inline uint32_t GPT_GetClockSource(GPT_Type * base) +static inline uint32_t GPT_GetClockSource(GPT_Type* base) { return (base->CR & GPT_CR_CLKSRC_MASK) >> GPT_CR_CLKSRC_SHIFT; } /*! - * @brief Set pre scaler of GPT + * @brief Set pre scaler of GPT. * * @param base GPT base pointer. - * @param prescaler pre scaler of GPT (0-4095, divider=prescaler+1) + * @param prescaler Pre-scaler of GPT (0-4095, divider = prescaler + 1). */ -static inline void GPT_SetPrescaler(GPT_Type * base, uint32_t prescaler) +static inline void GPT_SetPrescaler(GPT_Type* base, uint32_t prescaler) { assert(prescaler <= GPT_PR_PRESCALER_MASK); + base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(prescaler); } /*! - * @brief Get pre scaler of GPT + * @brief Get pre scaler of GPT. * * @param base GPT base pointer. - * @return pre scaler of GPT (0-4095) + * @return pre scaler of GPT (0-4095). */ -static inline uint32_t GPT_GetPrescaler(GPT_Type * base) +static inline uint32_t GPT_GetPrescaler(GPT_Type* base) { return (base->PR & GPT_PR_PRESCALER_MASK) >> GPT_PR_PRESCALER_SHIFT; } /*! - * @brief OSC 24M pre scaler before selected by clock source + * @brief OSC 24M pre-scaler before selected by clock source. * * @param base GPT base pointer. - * @param prescaler OSC pre scaler(0-15, divider=prescaler+1) + * @param prescaler OSC pre-scaler(0-15, divider = prescaler + 1). */ -static inline void GPT_SetOscPrescaler(GPT_Type * base, uint32_t prescaler) +static inline void GPT_SetOscPrescaler(GPT_Type* base, uint32_t prescaler) { assert(prescaler <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)); + base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(prescaler); } /*! - * @brief Get pre scaler of GPT + * @brief Get pre-scaler of GPT. * * @param base GPT base pointer. - * @return OSC pre scaler of GPT (0-15) + * @return OSC pre scaler of GPT (0-15). */ -static inline uint32_t GPT_GetOscPrescaler(GPT_Type * base) +static inline uint32_t GPT_GetOscPrescaler(GPT_Type* base) { return (base->PR & GPT_PR_PRESCALER24M_MASK) >> GPT_PR_PRESCALER24M_SHIFT; } /*! - * @brief Enable GPT module + * @brief Enable GPT module. * * @param base GPT base pointer. */ -static inline void GPT_Enable(GPT_Type * base) +static inline void GPT_Enable(GPT_Type* base) { base->CR |= GPT_CR_EN_MASK; } /*! - * @brief Disable GPT module + * @brief Disable GPT module. * * @param base GPT base pointer. */ -static inline void GPT_Disable(GPT_Type * base) +static inline void GPT_Disable(GPT_Type* base) { base->CR &= ~GPT_CR_EN_MASK; } /*! - * @brief Get GPT counter value + * @brief Get GPT counter value. * * @param base GPT base pointer. - * @return GPT counter value + * @return GPT counter value. */ -static inline uint32_t GPT_ReadCounter(GPT_Type * base) +static inline uint32_t GPT_ReadCounter(GPT_Type* base) { return base->CNT; } @@ -255,93 +249,100 @@ static inline uint32_t GPT_ReadCounter(GPT_Type * base) */ /*! - * @brief Set GPT operation mode of input capture channel + * @brief Set GPT operation mode of input capture channel. * * @param base GPT base pointer. - * @param channel GPT capture channel (see _gpt_input_capture_channel). - * @param mode GPT input capture operation mode (see _gpt_input_operation_mode). + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @param mode GPT input capture operation mode (see @ref _gpt_input_operation_mode enumeration). */ -static inline void GPT_SetInputOperationMode(GPT_Type * base, uint32_t channel, uint32_t mode) +static inline void GPT_SetInputOperationMode(GPT_Type* base, uint32_t channel, uint32_t mode) { assert (channel <= gptInputCaptureChannel2); + base->CR = (base->CR & ~(GPT_CR_IM1_MASK << (channel * 2))) | (GPT_CR_IM1(mode) << (channel * 2)); } /*! - * @brief Get GPT operation mode of input capture channel + * @brief Get GPT operation mode of input capture channel. * * @param base GPT base pointer. - * @param channel GPT capture channel (see _gpt_input_capture_channel). - * @return GPT input capture operation mode (see _gpt_input_operation_mode). + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @return GPT input capture operation mode (see @ref _gpt_input_operation_mode enumeration). */ -static inline uint32_t GPT_GetInputOperationMode(GPT_Type * base, uint32_t channel) +static inline uint32_t GPT_GetInputOperationMode(GPT_Type* base, uint32_t channel) { assert (channel <= gptInputCaptureChannel2); + return (base->CR >> (GPT_CR_IM1_SHIFT + channel * 2)) & (GPT_CR_IM1_MASK >> GPT_CR_IM1_SHIFT); } /*! - * @brief Get GPT input capture value of certain channel + * @brief Get GPT input capture value of certain channel. * * @param base GPT base pointer. - * @param channel GPT capture channel (see _gpt_input_capture_channel). - * @return GPT input capture value + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @return GPT input capture value. */ -static inline uint32_t GPT_GetInputCaptureValue(GPT_Type * base, uint32_t channel) +static inline uint32_t GPT_GetInputCaptureValue(GPT_Type* base, uint32_t channel) { assert (channel <= gptInputCaptureChannel2); + return *(&base->ICR1 + channel); } /*! - * @brief Set GPT operation mode of output compare channel + * @brief Set GPT operation mode of output compare channel. * * @param base GPT base pointer. - * @param channel GPT output compare channel (see _gpt_output_compare_channel). - * @param mode GPT output operation mode (see _gpt_output_operation_mode). + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @param mode GPT output operation mode (see @ref _gpt_output_operation_mode enumeration). */ -static inline void GPT_SetOutputOperationMode(GPT_Type * base, uint32_t channel, uint32_t mode) +static inline void GPT_SetOutputOperationMode(GPT_Type* base, uint32_t channel, uint32_t mode) { assert (channel <= gptOutputCompareChannel3); + base->CR = (base->CR & ~(GPT_CR_OM1_MASK << (channel * 3))) | (GPT_CR_OM1(mode) << (channel * 3)); } /*! - * @brief Get GPT operation mode of output compare channel + * @brief Get GPT operation mode of output compare channel. * * @param base GPT base pointer. - * @param channel GPT output compare channel (see _gpt_output_compare_channel). - * @return GPT output operation mode (see _gpt_output_operation_mode). + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @return GPT output operation mode (see @ref _gpt_output_operation_mode enumeration). */ -static inline uint32_t GPT_GetOutputOperationMode(GPT_Type * base, uint32_t channel) +static inline uint32_t GPT_GetOutputOperationMode(GPT_Type* base, uint32_t channel) { assert (channel <= gptOutputCompareChannel3); + return (base->CR >> (GPT_CR_OM1_SHIFT + channel * 3)) & (GPT_CR_OM1_MASK >> GPT_CR_OM1_SHIFT); } /*! - * @brief Set GPT output compare value of output compare channel + * @brief Set GPT output compare value of output compare channel. * * @param base GPT base pointer. - * @param channel GPT output compare channel (see _gpt_output_compare_channel). - * @param value GPT output compare value + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @param value GPT output compare value. */ -static inline void GPT_SetOutputCompareValue(GPT_Type * base, uint32_t channel, uint32_t value) +static inline void GPT_SetOutputCompareValue(GPT_Type* base, uint32_t channel, uint32_t value) { assert (channel <= gptOutputCompareChannel3); + *(&base->OCR1 + channel) = value; } /*! - * @brief Get GPT output compare value of output compare channel + * @brief Get GPT output compare value of output compare channel. * * @param base GPT base pointer. - * @param channel GPT output compare channel (see _gpt_output_compare_channel). - * @return GPT output compare value + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @return GPT output compare value. */ -static inline uint32_t GPT_GetOutputCompareValue(GPT_Type * base, uint32_t channel) +static inline uint32_t GPT_GetOutputCompareValue(GPT_Type* base, uint32_t channel) { assert (channel <= gptOutputCompareChannel3); + return *(&base->OCR1 + channel); } @@ -349,18 +350,19 @@ static inline uint32_t GPT_GetOutputCompareValue(GPT_Type * base, uint32_t chann * @brief Force GPT output action on output compare channel, ignoring comparator. * * @param base GPT base pointer. - * @param channel GPT output compare channel (see _gpt_output_compare_channel). + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). */ -static inline void GPT_ForceOutput(GPT_Type * base, uint32_t channel) +static inline void GPT_ForceOutput(GPT_Type* base, uint32_t channel) { assert (channel <= gptOutputCompareChannel3); + base->CR |= (GPT_CR_FO1_MASK << channel); } /*@}*/ /*! - * @name GPT Interupt and Status Control + * @name GPT Interrupt and Status Control * @{ */ @@ -368,10 +370,10 @@ static inline void GPT_ForceOutput(GPT_Type * base, uint32_t channel) * @brief Get GPT status flag. * * @param base GPT base pointer. - * @param flags GPT status flag mask (see _gpt_status_flag for bit definition). - * @return GPT status, each bit represents one status flag + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). + * @return GPT status, each bit represents one status flag. */ -static inline uint32_t GPT_GetStatusFlag(GPT_Type * base, uint32_t flags) +static inline uint32_t GPT_GetStatusFlag(GPT_Type* base, uint32_t flags) { return base->SR & flags; } @@ -380,21 +382,23 @@ static inline uint32_t GPT_GetStatusFlag(GPT_Type * base, uint32_t flags) * @brief Clear one or more GPT status flag. * * @param base GPT base pointer. - * @param flags GPT status flag mask (see _gpt_status_flag for bit definition). + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). */ -static inline void GPT_ClearStatusFlag(GPT_Type * base, uint32_t flags) +static inline void GPT_ClearStatusFlag(GPT_Type* base, uint32_t flags) { base->SR = flags; } /*! - * @brief Enable or disable GPT interrupts. + * @brief Enable or Disable GPT interrupts. * * @param base GPT base pointer. - * @param flags GPT status flag mask (see _gpt_status_flag for bit definition). - * @param enable Interrupt enable (true: enable, false: disable). + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). + * @param enable Enable/Disable GPT interrupts. + * -true: Enable GPT interrupts. + * -false: Disable GPT interrupts. */ -void GPT_SetIntCmd(GPT_Type * base, uint32_t flags, bool enable); +void GPT_SetIntCmd(GPT_Type* base, uint32_t flags, bool enable); /*@}*/ diff --git a/platform/drivers/inc/i2c_imx.h b/platform/drivers/inc/i2c_imx.h index 3d93112..566c70a 100644 --- a/platform/drivers/inc/i2c_imx.h +++ b/platform/drivers/inc/i2c_imx.h @@ -48,41 +48,35 @@ /*! @brief I2C module initialize structure. */ typedef struct _i2c_init_config { - uint32_t clockRate; /*!< Current I2C module clock freq. */ - uint32_t baudRate; /*!< Desired I2C baud rate. */ - uint8_t slaveAddress; /*!< I2C module's own address when addressed as slave device. */ + uint32_t clockRate; /*!< Current I2C module clock freq. */ + uint32_t baudRate; /*!< Desired I2C baud rate. */ + uint8_t slaveAddress; /*!< I2C module's own address when addressed as slave device. */ } i2c_init_config_t; -/*! - * @brief Flag for I2C interrupt status check or polling status. - */ +/*! @brief Flag for I2C interrupt status check or polling status. */ enum _i2c_status_flag { - i2cStatusTransferComplete = I2C_I2SR_ICF_MASK, - i2cStatusAddressedAsSlave = I2C_I2SR_IAAS_MASK, - i2cStatusBusBusy = I2C_I2SR_IBB_MASK, - i2cStatusArbitrationLost = I2C_I2SR_IAL_MASK, - i2cStatusSlaveReadWrite = I2C_I2SR_SRW_MASK, - i2cStatusInterrupt = I2C_I2SR_IIF_MASK, - i2cStatusReceivedAck = I2C_I2SR_RXAK_MASK + i2cStatusTransferComplete = I2C_I2SR_ICF_MASK, /*!< Data Transfer complete flag. */ + i2cStatusAddressedAsSlave = I2C_I2SR_IAAS_MASK, /*!< Addressed as a slave flag. */ + i2cStatusBusBusy = I2C_I2SR_IBB_MASK, /*!< Bus is busy flag. */ + i2cStatusArbitrationLost = I2C_I2SR_IAL_MASK, /*!< Arbitration is lost flag. */ + i2cStatusSlaveReadWrite = I2C_I2SR_SRW_MASK, /*!< Master reading from slave flag(De-assert if master writing to slave). */ + i2cStatusInterrupt = I2C_I2SR_IIF_MASK, /*!< An interrupt is pending flag. */ + i2cStatusReceivedAck = I2C_I2SR_RXAK_MASK, /*!< No acknowledge detected flag. */ }; -/*! - * @brief I2C Bus role of this module. - */ +/*! @brief I2C Bus role of this module. */ enum _i2c_work_mode { - i2cModeSlave = 0x0, - i2cModeMaster = I2C_I2CR_MSTA_MASK + i2cModeSlave = 0x0, /*!< This module works as I2C Slave. */ + i2cModeMaster = I2C_I2CR_MSTA_MASK, /*!< This module works as I2C Master. */ }; -/*! - * @brief Data transfer direction. - */ +/*! @brief Data transfer direction. */ enum _i2c_direction_mode { - i2cDirectionReceive = 0x0, - i2cDirectionTransmit = I2C_I2CR_MTX_MASK + i2cDirectionReceive = 0x0, /*!< This module works at receive mode. */ + i2cDirectionTransmit = I2C_I2CR_MTX_MASK, /*!< This module works at transmit mode. */ }; /******************************************************************************* @@ -102,9 +96,9 @@ extern "C" { * @brief Initialize I2C module with given initialize structure. * * @param base I2C base pointer. - * @param initConfig I2C initialize structure(see i2c_init_config_t above). + * @param initConfig I2C initialize structure (see @ref i2c_init_config_t). */ -void I2C_Init(I2C_Type* base, i2c_init_config_t* initConfig); +void I2C_Init(I2C_Type* base, const i2c_init_config_t* initConfig); /*! * @brief This function reset I2C module register content to its default value. @@ -151,6 +145,7 @@ void I2C_SetBaudRate(I2C_Type* base, uint32_t clockRate, uint32_t baudRate); static inline void I2C_SetSlaveAddress(I2C_Type* base, uint8_t slaveAddress) { assert(slaveAddress < 0x80); + I2C_IADR_REG(base) = (I2C_IADR_REG(base) & ~I2C_IADR_ADR_MASK) | I2C_IADR_ADR(slaveAddress); } @@ -174,11 +169,12 @@ static inline void I2C_SendRepeatStart(I2C_Type* base) * both I2C Bus Master and Slave can be select. * * @param base I2C base pointer. - * @param mode I2C Bus role to set (see _i2c_work_mode enumeration). + * @param mode I2C Bus role to set (see @ref _i2c_work_mode enumeration). */ static inline void I2C_SetWorkMode(I2C_Type* base, uint32_t mode) { assert((mode == i2cModeMaster) || (mode == i2cModeSlave)); + I2C_I2CR_REG(base) = (I2C_I2CR_REG(base) & ~I2C_I2CR_MSTA_MASK) | mode; } @@ -187,11 +183,12 @@ static inline void I2C_SetWorkMode(I2C_Type* base, uint32_t mode) * both Transmit and Receive can be select. * * @param base I2C base pointer. - * @param direction I2C Bus data transfer direction (see _i2c_direction_mode enumeration). + * @param direction I2C Bus data transfer direction (see @ref _i2c_direction_mode enumeration). */ static inline void I2C_SetDirMode(I2C_Type* base, uint32_t direction) { assert((direction == i2cDirectionReceive) || (direction == i2cDirectionTransmit)); + I2C_I2CR_REG(base) = (I2C_I2CR_REG(base) & ~I2C_I2CR_MTX_MASK) | direction; } @@ -200,8 +197,9 @@ static inline void I2C_SetDirMode(I2C_Type* base, uint32_t direction) * data from other device. * * @param base I2C base pointer. - * @param ack true: An acknowledge signal is sent to the bus at the ninth clock bit - * false: No acknowledge signal response is sent + * @param ack The ACK value answerback to remote I2C device. + * - true: An acknowledge signal is sent to the bus at the ninth clock bit. + * - false: No acknowledge signal response is sent. */ void I2C_SetAckBit(I2C_Type* base, bool ack); @@ -213,7 +211,7 @@ void I2C_SetAckBit(I2C_Type* base, bool ack); /*! * @brief Writes one byte of data to the I2C bus. * - * @param base The I2C peripheral base pointer. + * @param base I2C base pointer. * @param byte The byte of data to transmit. */ static inline void I2C_WriteByte(I2C_Type* base, uint8_t byte) @@ -226,9 +224,9 @@ static inline void I2C_WriteByte(I2C_Type* base, uint8_t byte) * * In a master receive mode, calling this function initiates receiving the next byte of data. * - * @param base The I2C peripheral base pointer + * @param base I2C base pointer. * @return This function returns the last byte received while the I2C module is configured in master - * receive or slave receive mode. + * receive or slave receive mode. */ static inline uint8_t I2C_ReadByte(I2C_Type* base) { @@ -241,10 +239,12 @@ static inline uint8_t I2C_ReadByte(I2C_Type* base) */ /*! - * @brief Enables or disables I2C interrupt requests. + * @brief Enable or disable I2C interrupt requests. * - * @param base The I2C peripheral base pointer - * @param enable Pass true to enable interrupt, false to disable. + * @param base I2C base pointer. + * @param enable Enable/Disbale I2C interrupt. + * - true: Enable I2C interrupt. + * - false: Disable I2C interrupt. */ void I2C_SetIntCmd(I2C_Type* base, bool enable); @@ -252,7 +252,7 @@ void I2C_SetIntCmd(I2C_Type* base, bool enable); * @brief Gets the I2C status flag state. * * @param base I2C base pointer. - * @param flags I2C status flag mask defined in _i2c_status_flag enumeration. + * @param flags I2C status flag mask (see @ref _i2c_status_flag enumeration.) * @return I2C status, each bit represents one status flag */ static inline uint32_t I2C_GetStatusFlag(I2C_Type* base, uint32_t flags) @@ -264,7 +264,7 @@ static inline uint32_t I2C_GetStatusFlag(I2C_Type* base, uint32_t flags) * @brief Clear one or more I2C status flag state. * * @param base I2C base pointer. - * @param flags I2C status flag mask defined in _i2c_status_flag enumeration. + * @param flags I2C status flag mask (see @ref _i2c_status_flag enumeration.) */ static inline void I2C_ClearStatusFlag(I2C_Type* base, uint32_t flags) { diff --git a/platform/drivers/inc/lmem.h b/platform/drivers/inc/lmem.h new file mode 100644 index 0000000..5c77d74 --- /dev/null +++ b/platform/drivers/inc/lmem.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __LMEM_H__ +#define __LMEM_H__ + +#include <stdint.h> +#include <assert.h> +#include "device_imx.h" + +/*! + * @addtogroup lmem_driver + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Processor System Cache control functions + * @{ + */ + +/*! + * @brief This function enable the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_EnableSystemCache(LMEM_Type *base); + +/*! + * @brief This function disable the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_DisableSystemCache(LMEM_Type *base); + +/*! + * @brief This function flush the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_FlushSystemCache(LMEM_Type *base); + +/*! + * @brief This function is called to flush the System Cache by performing cache copy-backs. + * It must determine how many cache lines need to be copied back and then + * perform the copy-backs. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of flush address space. + */ +void LMEM_FlushSystemCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*! + * @brief This function invalidate the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_InvalidateSystemCache(LMEM_Type *base); + +/*! + * @brief This function is responsible for performing an System Cache invalidate. + * It must determine how many cache lines need to be invalidated and then + * perform the invalidation. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of invalidate address space. + */ +void LMEM_InvalidateSystemCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*@}*/ + +/*! + * @name Processor Code Cache control functions + * @{ + */ + +/*! + * @brief This function enable the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_EnableCodeCache(LMEM_Type *base); + +/*! + * @brief This function disable the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_DisableCodeCache(LMEM_Type *base); + +/*! + * @brief This function flush the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_FlushCodeCache(LMEM_Type *base); + +/*! + * @brief This function is called to flush the Code Cache by performing cache copy-backs. + * It must determine how many cache lines need to be copied back and then + * perform the copy-backs. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of flush address space. + */ +void LMEM_FlushCodeCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*! + * @brief This function invalidate the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_InvalidateCodeCache(LMEM_Type *base); + +/*! + * @brief This function is responsible for performing an Code Cache invalidate. + * It must determine how many cache lines need to be invalidated and then + * perform the invalidation. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of invalidate address space. + */ +void LMEM_InvalidateCodeCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __LMEM_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/platform/drivers/inc/mu_imx.h b/platform/drivers/inc/mu_imx.h index 40bacc7..2e16afd 100644 --- a/platform/drivers/inc/mu_imx.h +++ b/platform/drivers/inc/mu_imx.h @@ -66,24 +66,20 @@ /* Mask for MU_CR_GIRN. When read-modify-write to MU_CR, should pay attention to these bits in case of trigger interrupts by mistake.*/ -/*! - * @brief MU status return codes. - */ +/*! @brief MU status return codes. */ typedef enum _mu_status { - kStatus_MU_Success = 0U, /*!< Success. */ - kStatus_MU_TxNotEmpty = 1U, /*!< TX register is not empty. */ - kStatus_MU_RxNotFull = 2U, /*!< RX register is not full. */ - kStatus_MU_FlagPending = 3U, /*!< Previous flags update pending. */ - kStatus_MU_EventPending = 4U, /*!< MU event is pending. */ - kStatus_MU_Initialized = 5U, /*!< MU driver has initialized previously. */ - kStatus_MU_IntPending = 6U, /*!< Previous general interrupt still pending. */ - kStatus_MU_Failed = 7U /*!< Execution failed. */ + kStatus_MU_Success = 0U, /*!< Success. */ + kStatus_MU_TxNotEmpty = 1U, /*!< TX register is not empty. */ + kStatus_MU_RxNotFull = 2U, /*!< RX register is not full. */ + kStatus_MU_FlagPending = 3U, /*!< Previous flags update pending. */ + kStatus_MU_EventPending = 4U, /*!< MU event is pending. */ + kStatus_MU_Initialized = 5U, /*!< MU driver has initialized previously. */ + kStatus_MU_IntPending = 6U, /*!< Previous general interrupt still pending. */ + kStatus_MU_Failed = 7U /*!< Execution failed. */ } mu_status_t; -/*! - * @brief MU message status. - */ +/*! @brief MU message status. */ typedef enum _mu_msg_status { kMuTxEmpty0 = MU_SR_TE0_MASK, /*!< TX0 empty status. */ @@ -119,15 +115,13 @@ typedef enum _mu_msg_status } mu_msg_status_t; -/*! - * @brief Power mode definition. - */ +/*! @brief Power mode definition. */ typedef enum _mu_power_mode { - kMuPowerModeRun = 0x00U, /*!< Run mode. */ - kMuPowerModeWait = 0x01U, /*!< WAIT mode. */ - kMuPowerModeStop = 0x02U, /*!< STOP mode. */ - kMuPowerModeDsm = 0x03U, /*!< DSM mode. */ + kMuPowerModeRun = 0x00U, /*!< Run mode. */ + kMuPowerModeWait = 0x01U, /*!< WAIT mode. */ + kMuPowerModeStop = 0x02U, /*!< STOP mode. */ + kMuPowerModeDsm = 0x03U, /*!< DSM mode. */ } mu_power_mode_t; /******************************************************************************* @@ -144,8 +138,7 @@ extern "C" { */ /*! * @brief Initializes the MU module to reset state. - * - * This function sets the MU module control register to its default reset value. + * This function sets the MU module control register to its default reset value. * * @param base Register base address for the module. */ @@ -190,12 +183,12 @@ void MU_SendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg); /*! * @brief Check TX empty status. * - * This function checks the specific tramsmit register empty status. + * This function checks the specific transmit register empty status. * * @param base Register base address for the module. - * @param index TX register index to check. - * @retval true TX register is empty. - * @retval false TX register is not empty. + * @param index TX register index to check. + * @retval true TX register is empty. + * @retval false TX register is not empty. */ static inline bool MU_IsTxEmpty(MU_Type * base, uint32_t index) { @@ -207,8 +200,8 @@ static inline bool MU_IsTxEmpty(MU_Type * base, uint32_t index) * * This function enables specific TX empty interrupt. * - * @param base Register base address for the module. - * @param index TX interrupt index to enable. + * @param base Register base address for the module. + * @param index TX interrupt index to enable. * * Example: @code @@ -227,7 +220,7 @@ static inline void MU_EnableTxEmptyInt(MU_Type * base, uint32_t index) * * This function disables specific TX empty interrupt. * - * @param base Register base address for the module. + * @param base Register base address for the module. * @param disableMask Bitmap of the interrupts to disable. * * Example: @@ -255,8 +248,8 @@ static inline void MU_DisableTxEmptyInt(MU_Type * base, uint32_t index) * this function returns kStatus_MU_RxNotFull. * * @param base Register base address for the module. - * @param regIdex Rx register index. - * @param msg Message to receive. + * @param regIdex Rx register index. + * @param msg Message to receive. * @retval kStatus_MU_Success Message receive successfully. * @retval kStatus_MU_RxNotFull Message not received because RX is not full. */ @@ -268,8 +261,8 @@ mu_status_t MU_TryReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg); * This function waits until RX register is full and receive the message. * * @param base Register base address for the module. - * @param regIdex Rx register index. - * @param msg Message to receive. + * @param regIdex Rx register index. + * @param msg Message to receive. */ void MU_ReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg); @@ -279,9 +272,9 @@ void MU_ReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg); * This function checks the specific receive register full status. * * @param base Register base address for the module. - * @param index RX register index to check. - * @retval true RX register is full. - * @retval false RX register is not full. + * @param index RX register index to check. + * @retval true RX register is full. + * @retval false RX register is not full. */ static inline bool MU_IsRxFull(MU_Type * base, uint32_t index) { @@ -293,8 +286,8 @@ static inline bool MU_IsRxFull(MU_Type * base, uint32_t index) * * This function enables specific RX full interrupt. * - * @param base Register base address for the module. - * @param index RX interrupt index to enable. + * @param base Register base address for the module. + * @param index RX interrupt index to enable. * * Example: @code @@ -313,7 +306,7 @@ static inline void MU_EnableRxFullInt(MU_Type * base, uint32_t index) * * This function disables specific RX full interrupt. * - * @param base Register base address for the module. + * @param base Register base address for the module. * @param disableMask Bitmap of the interrupts to disable. * * Example: @@ -339,8 +332,8 @@ static inline void MU_DisableRxFullInt(MU_Type * base, uint32_t index) * * This function enables specific general purpose interrupt. * - * @param base Register base address for the module. - * @param index General purpose interrupt index to enable. + * @param base Register base address for the module. + * @param index General purpose interrupt index to enable. * * Example: @code @@ -359,8 +352,8 @@ static inline void MU_EnableGeneralInt(MU_Type * base, uint32_t index) * * This function disables specific general purpose interrupt. * - * @param base Register base address for the module. - * @param index General purpose interrupt index to disable. + * @param base Register base address for the module. + * @param index General purpose interrupt index to disable. * * Example: @code @@ -379,9 +372,9 @@ static inline void MU_DisableGeneralInt(MU_Type * base, uint32_t index) * This function checks the specific general purpose interrupt pending status. * * @param base Register base address for the module. - * @param index Index of the general purpose interrupt flag to check. - * @retval true General purpose interrupt is pending. - * @retval false General purpose interrupt is not pending. + * @param index Index of the general purpose interrupt flag to check. + * @retval true General purpose interrupt is pending. + * @retval false General purpose interrupt is not pending. */ static inline bool MU_IsGeneralIntPending(MU_Type * base, uint32_t index) { @@ -394,7 +387,7 @@ static inline bool MU_IsGeneralIntPending(MU_Type * base, uint32_t index) * This function clears the specific general purpose interrupt pending status. * * @param base Register base address for the module. - * @param index Index of the general purpose interrupt flag to clear. + * @param index Index of the general purpose interrupt flag to clear. */ static inline void MU_ClearGeneralIntPending(MU_Type * base, uint32_t index) { @@ -406,14 +399,14 @@ static inline void MU_ClearGeneralIntPending(MU_Type * base, uint32_t index) * * This function triggers specific general purpose interrupt to other core. * - * To ensure proper operations, please make sure the correspond general purpose - * interrupt triggerd previously has been accepted by the other core. The - * function MU_IsGeneralIntAccepted could be used for this check. If the + * To ensure proper operations, make sure the correspond general purpose + * interrupt triggered previously has been accepted by the other core. The + * function MU_IsGeneralIntAccepted can be used for this check. If the * previous general interrupt has not been accepted by the other core, this - * function does not trigger interrupt acctually and returns error. + * function does not trigger interrupt actually and returns an error. * * @param base Register base address for the module. - * @param index Index of general purpose interrupt to trigger. + * @param index Index of general purpose interrupt to trigger. * @retval kStatus_MU_Success Interrupt has been triggered successfully. * @retval kStatus_MU_IntPending Previous interrupt has not been accepted. */ @@ -426,9 +419,9 @@ mu_status_t MU_TriggerGeneralInt(MU_Type * base, uint32_t index); * been accepted by the other core or not. * * @param base Register base address for the module. - * @param index Index of the general purpose interrupt to check. - * @retval true General purpose interrupt is accepted. - * @retval false General purpose interrupt is not accepted. + * @param index Index of the general purpose interrupt to check. + * @retval true General purpose interrupt is accepted. + * @retval false General purpose interrupt is not accepted. */ static inline bool MU_IsGeneralIntAccepted(MU_Type * base, uint32_t index) { @@ -458,7 +451,7 @@ mu_status_t MU_TrySetFlags(MU_Type * base, uint32_t flags); * @brief Set some bits of the 3-bit flag reflect on the other MU side. * * This functions set some bits of the 3-bit flag. If previous flags update is - * still pending, this function will block and poll to set the flag. + * still pending, this function blocks and polls to set the flag. * * @param base Register base address for the module. */ @@ -467,13 +460,13 @@ void MU_SetFlags(MU_Type * base, uint32_t flags); /*! * @brief Checks whether the previous flag update is pending. * - * After setting flags, the flags update request is pending untill internally + * After setting flags, the flags update request is pending until internally * acknowledged. During the pending period, it is not allowed to set flags again. - * This function is used to check the pending status, it could be used together + * This function is used to check the pending status, it can be used together * with function MU_TrySetFlags. * * @param base Register base address for the module. - * @return True if pending, faulse if not. + * @return True if pending, false if not. */ static inline bool MU_IsFlagPending(MU_Type * base) { @@ -486,7 +479,7 @@ static inline bool MU_IsFlagPending(MU_Type * base) * This functions gets the current value of the 3-bit flag. * * @param base Register base address for the module. - * @return flags Current value of the 3-bit flag. + * @return flags Current value of the 3-bit flag. */ static inline uint32_t MU_GetFlags(MU_Type * base) { @@ -517,12 +510,12 @@ static inline mu_power_mode_t MU_GetOtherCorePowerMode(MU_Type * base) * @brief Get the event pending status. * * This functions gets the event pending status. To ensure events have been - * posted to the other side before entering STOP mode, please verify the + * posted to the other side before entering STOP mode, verify the * event pending status using this function. * * @param base Register base address for the module. - * @retval true Event is pending. - * @retval false Event is not pending. + * @retval true Event is pending. + * @retval false Event is not pending. */ static inline bool MU_IsEventPending(MU_Type * base) { diff --git a/platform/drivers/inc/rdc.h b/platform/drivers/inc/rdc.h index 6259e78..872e39d 100644 --- a/platform/drivers/inc/rdc.h +++ b/platform/drivers/inc/rdc.h @@ -73,7 +73,9 @@ static inline uint32_t RDC_GetSelfDomainID(RDC_Type * base) * @brief Check whether memory region controlled by RDC is accessible after low power recovery * * @param base RDC base pointer. - * @return Memory region power status (true: on and accessible, false: off) + * @return Memory region power status. + * - true: on and accessible. + * - false: off. */ static inline bool RDC_IsMemPowered(RDC_Type * base) { @@ -84,7 +86,9 @@ static inline bool RDC_IsMemPowered(RDC_Type * base) * @brief Check whether there's pending RDC memory region restoration interrupt * * @param base RDC base pointer. - * @return RDC interrupt status (true: interrupt pending, false: no interrupt pending) + * @return RDC interrupt status + * - true: Interrupt pending. + * - false: No interrupt pending. */ static inline bool RDC_IsIntPending(RDC_Type * base) { @@ -105,7 +109,9 @@ static inline void RDC_ClearStatusFlag(RDC_Type * base) * @brief Set RDC interrupt mode * * @param base RDC base pointer - * @param enable RDC interrupt control (true: enable, false: disable) + * @param enable RDC interrupt control. + * - true: enable interrupt. + * - false: disable interrupt. */ static inline void RDC_SetIntCmd(RDC_Type * base, bool enable) { @@ -123,13 +129,14 @@ static inline void RDC_SetIntCmd(RDC_Type * base, bool enable) * @brief Set RDC domain ID for RDC master * * @param base RDC base pointer - * @param mda RDC master assignment (see _rdc_mda in rdc_defs_<device>.h) + * @param mda RDC master assignment (see @ref _rdc_mda in rdc_defs_<device>.h) * @param domainId RDC domain ID (0-3) * @param lock Whether to lock this setting? Once locked, no one can change the domain assignment until reset */ static inline void RDC_SetDomainID(RDC_Type * base, uint32_t mda, uint32_t domainId, bool lock) { assert (domainId <= RDC_MDA_DID_MASK); + base->MDA[mda] = RDC_MDA_DID(domainId) | (lock ? RDC_MDA_LCK_MASK : 0); } @@ -137,7 +144,7 @@ static inline void RDC_SetDomainID(RDC_Type * base, uint32_t mda, uint32_t domai * @brief Get RDC domain ID for RDC master * * @param base RDC base pointer - * @param mda RDC master assignment (see _rdc_mda in rdc_defs_<device>.h) + * @param mda RDC master assignment (see @ref _rdc_mda in rdc_defs_<device>.h) * @return RDC domain ID (0-3) */ static inline uint32_t RDC_GetDomainID(RDC_Type * base, uint32_t mda) @@ -149,7 +156,7 @@ static inline uint32_t RDC_GetDomainID(RDC_Type * base, uint32_t mda) * @brief Set RDC peripheral access permission for RDC domains * * @param base RDC base pointer - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) * @param perm RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) * @param sreq Force acquiring SEMA42 to access this peripheral or not * @param lock Whether to lock this setting or not. Once locked, no one can change the RDC setting until reset @@ -163,7 +170,7 @@ static inline void RDC_SetPdapAccess(RDC_Type * base, uint32_t pdap, uint8_t per * @brief Get RDC peripheral access permission for RDC domains * * @param base RDC base pointer - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) * @return RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) */ static inline uint8_t RDC_GetPdapAccess(RDC_Type * base, uint32_t pdap) @@ -175,8 +182,10 @@ static inline uint8_t RDC_GetPdapAccess(RDC_Type * base, uint32_t pdap) * @brief Check whether RDC semaphore is required to access the peripheral * * @param base RDC base pointer - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) - * @return RDC semaphore required or not (true: required, false: not required) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) + * @return RDC semaphore required or not. + * - true: RDC semaphore is required. + * - false: RDC semaphore is not required. */ static inline bool RDC_IsPdapSemaphoreRequired(RDC_Type * base, uint32_t pdap) { @@ -187,7 +196,7 @@ static inline bool RDC_IsPdapSemaphoreRequired(RDC_Type * base, uint32_t pdap) * @brief Set RDC memory region access permission for RDC domains * * @param base RDC base pointer - * @param mr RDC memory region assignment (see _rdc_mr in rdc_defs_<device>.h) + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_<device>.h) * @param startAddr memory region start address (inclusive) * @param endAddr memory region end address (exclusive) * @param perm RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) @@ -201,7 +210,7 @@ void RDC_SetMrAccess(RDC_Type * base, uint32_t mr, uint32_t startAddr, uint32_t * @brief Get RDC memory region access permission for RDC domains * * @param base RDC base pointer - * @param mr RDC memory region assignment (see _rdc_mr in rdc_defs_<device>.h) + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_<device>.h) * @param startAddr pointer to get memory region start address (inclusive), NULL is allowed. * @param endAddr pointer to get memory region end address (exclusive), NULL is allowed. * @return RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) @@ -214,7 +223,9 @@ uint8_t RDC_GetMrAccess(RDC_Type * base, uint32_t mr, uint32_t *startAddr, uint3 * * @param base RDC base pointer * @param mr RDC memory region assignment (see _rdc_mr in rdc_defs_<device>.h) - * @return Memory region enabled or not (true: enabled, false: not enabled) + * @return Memory region enabled or not. + * - true: Memory region is enabled. + * - false: Memory region is not enabled. */ static inline bool RDC_IsMrEnabled(RDC_Type * base, uint32_t mr) { @@ -225,10 +236,12 @@ static inline bool RDC_IsMrEnabled(RDC_Type * base, uint32_t mr) * @brief Get memory violation status * * @param base RDC base pointer - * @param mr RDC memory region assignment (see _rdc_mr in rdc_defs_<device>.h) + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_<device>.h) * @param violationAddr Pointer to store violation address, NULL allowed * @param violationDomain Pointer to store domain ID causing violation, NULL allowed - * @return Memory violation occured or not (true: violation happened, false: no violation happened) + * @return Memory violation occurred or not. + * - true: violation happened. + * - false: No violation happened. */ bool RDC_GetViolationStatus(RDC_Type * base, uint32_t mr, uint32_t *violationAddr, uint32_t *violationDomain); @@ -236,7 +249,7 @@ bool RDC_GetViolationStatus(RDC_Type * base, uint32_t mr, uint32_t *violationAdd * @brief Clear RDC violation status * * @param base RDC base pointer - * @param mr RDC memory region assignment (see _rdc_mr in rdc_defs_<device>.h) + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_<device>.h) */ static inline void RDC_ClearViolationStatus(RDC_Type * base, uint32_t mr) { diff --git a/platform/drivers/inc/rdc_defs_imx7d.h b/platform/drivers/inc/rdc_defs_imx7d.h index 20bff89..e77990f 100644 --- a/platform/drivers/inc/rdc_defs_imx7d.h +++ b/platform/drivers/inc/rdc_defs_imx7d.h @@ -40,183 +40,180 @@ * Definitions ******************************************************************************/ -/*! - * @brief RDC master assignment - */ -enum _rdc_mda { - rdcMdaA7 = 0U, - rdcMdaM4 = 1U, - rdcMdaPcie = 2U, - rdcMdaCsi = 3U, - rdcMdaEpdc = 4U, - rdcMdaLcdif = 5U, - rdcMdaDisplayPort = 6U, - rdcMdaPxp = 7U, - rdcMdaCoresight = 8U, - rdcMdaDap = 9U, - rdcMdaCaam = 10U, - rdcMdaSdmaPeriph = 11U, - rdcMdaSdmaBurst = 12U, - rdcMdaApbhdma = 13U, - rdcMdaRawnand = 14U, - rdcMdaUsdhc1 = 15U, - rdcMdaUsdhc2 = 16U, - rdcMdaUsdhc3 = 17U, - rdcMdaNc1 = 18U, - rdcMdaUsb = 19U, - rdcMdaNc2 = 20U, - rdcMdaTest = 21U, - rdcMdaEnet1Tx = 22U, - rdcMdaEnet1Rx = 23U, - rdcMdaEnet2Tx = 24U, - rdcMdaEnet2Rx = 25U, - rdcMdaSdmaPort = 26U +/*! @brief RDC master assignment. */ +enum _rdc_mda +{ + rdcMdaA7 = 0U, /*!< A7 RDC Master. */ + rdcMdaM4 = 1U, /*!< M4 RDC Master. */ + rdcMdaPcie = 2U, /*!< PCIE RDC Master. */ + rdcMdaCsi = 3U, /*!< CSI RDC Master. */ + rdcMdaEpdc = 4U, /*!< EPDC RDC Master. */ + rdcMdaLcdif = 5U, /*!< LCDIF RDC Master. */ + rdcMdaDisplayPort = 6U, /*!< DISPLAY PORT RDC Master. */ + rdcMdaPxp = 7U, /*!< PXP RDC Master. */ + rdcMdaCoresight = 8U, /*!< CORESIGHT RDC Master. */ + rdcMdaDap = 9U, /*!< DAP RDC Master. */ + rdcMdaCaam = 10U, /*!< CAAM RDC Master. */ + rdcMdaSdmaPeriph = 11U, /*!< SDMA PERIPHERAL RDC Master. */ + rdcMdaSdmaBurst = 12U, /*!< SDMA BURST RDC Master. */ + rdcMdaApbhdma = 13U, /*!< APBH DMA RDC Master. */ + rdcMdaRawnand = 14U, /*!< RAW NAND RDC Master. */ + rdcMdaUsdhc1 = 15U, /*!< USDHC1 RDC Master. */ + rdcMdaUsdhc2 = 16U, /*!< USDHC2 RDC Master. */ + rdcMdaUsdhc3 = 17U, /*!< USDHC3 RDC Master. */ + rdcMdaNc1 = 18U, /*!< NC1 RDC Master. */ + rdcMdaUsb = 19U, /*!< USB RDC Master. */ + rdcMdaNc2 = 20U, /*!< NC2 RDC Master. */ + rdcMdaTest = 21U, /*!< TEST RDC Master. */ + rdcMdaEnet1Tx = 22U, /*!< Ethernet1 Tx RDC Master. */ + rdcMdaEnet1Rx = 23U, /*!< Ethernet1 Rx RDC Master. */ + rdcMdaEnet2Tx = 24U, /*!< Ethernet2 Tx RDC Master. */ + rdcMdaEnet2Rx = 25U, /*!< Ethernet2 Rx RDC Master. */ + rdcMdaSdmaPort = 26U, /*!< SDMA PORT RDC Master. */ }; -/*! - * @brief RDC peripheral assignment - */ -enum _rdc_pdap { - rdcPdapGpio1 = 0U, - rdcPdapGpio2 = 1U, - rdcPdapGpio3 = 2U, - rdcPdapGpio4 = 3U, - rdcPdapGpio5 = 4U, - rdcPdapGpio6 = 5U, - rdcPdapGpio7 = 6U, - rdcPdapIomuxcLpsrGpr = 7U, - rdcPdapWdog1 = 8U, - rdcPdapWdog2 = 9U, - rdcPdapWdog3 = 10U, - rdcPdapWdog4 = 11U, - rdcPdapIomuxcLpsr = 12U, - rdcPdapGpt1 = 13U, - rdcPdapGpt2 = 14U, - rdcPdapGpt3 = 15U, - rdcPdapGpt4 = 16U, - rdcPdapRomcp = 17U, - rdcPdapKpp = 18U, - rdcPdapIomuxc = 19U, - rdcPdapIomuxcGpr = 20U, - rdcPdapOcotpCtrl = 21U, - rdcPdapAnatopDig = 22U, - rdcPdapSnvs = 23U, - rdcPdapCcm = 24U, - rdcPdapSrc = 25U, - rdcPdapGpc = 26U, - rdcPdapSemaphore1 = 27U, - rdcPdapSemaphore2 = 28U, - rdcPdapRdc = 29U, - rdcPdapCsu = 30U, - rdcPdapReserved1 = 31U, - rdcPdapReserved2 = 32U, - rdcPdapAdc1 = 33U, - rdcPdapAdc2 = 34U, - rdcPdapEcspi4 = 35U, - rdcPdapFlexTimer1 = 36U, - rdcPdapFlexTimer2 = 37U, - rdcPdapPwm1 = 38U, - rdcPdapPwm2 = 39U, - rdcPdapPwm3 = 40U, - rdcPdapPwm4 = 41U, - rdcPdapSystemCounterRead = 42U, - rdcPdapSystemCounterCompare = 43U, - rdcPdapSystemCounterControl = 44U, - rdcPdapPcie = 45U, - rdcPdapReserved3 = 46U, - rdcPdapEpdc = 47U, - rdcPdapPxp = 48U, - rdcPdapCsi = 49U, - rdcPdapReserved4 = 50U, - rdcPdapLcdif = 51U, - rdcPdapReserved5 = 52U, - rdcPdapMipiCsi = 53U, - rdcPdapMipiDsi = 54U, - rdcPdapReserved6 = 55U, - rdcPdapTzasc = 56U, - rdcPdapDdrPhy = 57U, - rdcPdapDdrc = 58U, - rdcPdapReserved7 = 59U, - rdcPdapPerfMon1 = 60U, - rdcPdapPerfMon2 = 61U, - rdcPdapAxi = 62U, - rdcPdapQosc = 63U, - rdcPdapFlexCan1 = 64U, - rdcPdapFlexCan2 = 65U, - rdcPdapI2c1 = 66U, - rdcPdapI2c2 = 67U, - rdcPdapI2c3 = 68U, - rdcPdapI2c4 = 69U, - rdcPdapUart4 = 70U, - rdcPdapUart5 = 71U, - rdcPdapUart6 = 72U, - rdcPdapUart7 = 73U, - rdcPdapMuA = 74U, - rdcPdapMuB = 75U, - rdcPdapSemaphoreHs = 76U, - rdcPdapUsbPl301 = 77U, - rdcPdapReserved8 = 78U, - rdcPdapReserved9 = 79U, - rdcPdapReserved10 = 80U, - rdcPdapUSB1Otg1 = 81U, - rdcPdapUSB2Otg2 = 82U, - rdcPdapUSB3Host = 83U, - rdcPdapUsdhc1 = 84U, - rdcPdapUsdhc2 = 85U, - rdcPdapUsdhc3 = 86U, - rdcPdapReserved11 = 87U, - rdcPdapReserved12 = 88U, - rdcPdapSim1 = 89U, - rdcPdapSim2 = 90U, - rdcPdapQspi = 91U, - rdcPdapWeim = 92U, - rdcPdapSdma = 93U, - rdcPdapEnet1 = 94U, - rdcPdapEnet2 = 95U, - rdcPdapReserved13 = 96U, - rdcPdapReserved14 = 97U, - rdcPdapEcspi1 = 98U, - rdcPdapEcspi2 = 99U, - rdcPdapEcspi3 = 100U, - rdcPdapReserved15 = 101U, - rdcPdapUart1 = 102U, - rdcPdapReserved16 = 103U, - rdcPdapUart3 = 104U, - rdcPdapUart2 = 105U, - rdcPdapSai1 = 106U, - rdcPdapSai2 = 107U, - rdcPdapSai3 = 108U, - rdcPdapReserved17 = 109U, - rdcPdapReserved18 = 110U, - rdcPdapSpba = 111U, - rdcPdapDap = 112U, - rdcPdapReserved19 = 113U, - rdcPdapReserved20 = 114U, - rdcPdapReserved21 = 115U, - rdcPdapCaam = 116U, - rdcPdapReserved22 = 117U +/*! @brief RDC peripheral assignment. */ +enum _rdc_pdap +{ + rdcPdapGpio1 = 0U, /*!< GPIO1 RDC Peripheral. */ + rdcPdapGpio2 = 1U, /*!< GPIO2 RDC Peripheral. */ + rdcPdapGpio3 = 2U, /*!< GPIO3 RDC Peripheral. */ + rdcPdapGpio4 = 3U, /*!< GPIO4 RDC Peripheral. */ + rdcPdapGpio5 = 4U, /*!< GPIO5 RDC Peripheral. */ + rdcPdapGpio6 = 5U, /*!< GPIO6 RDC Peripheral. */ + rdcPdapGpio7 = 6U, /*!< GPIO7 RDC Peripheral. */ + rdcPdapIomuxcLpsrGpr = 7U, /*!< IOMXUC LPSR GPR RDC Peripheral. */ + rdcPdapWdog1 = 8U, /*!< WDOG1 RDC Peripheral. */ + rdcPdapWdog2 = 9U, /*!< WDOG2 RDC Peripheral. */ + rdcPdapWdog3 = 10U, /*!< WDOG3 RDC Peripheral. */ + rdcPdapWdog4 = 11U, /*!< WDOG4 RDC Peripheral. */ + rdcPdapIomuxcLpsr = 12U, /*!< IOMUXC LPSR RDC Peripheral. */ + rdcPdapGpt1 = 13U, /*!< GPT1 RDC Peripheral. */ + rdcPdapGpt2 = 14U, /*!< GPT2 RDC Peripheral. */ + rdcPdapGpt3 = 15U, /*!< GPT3 RDC Peripheral. */ + rdcPdapGpt4 = 16U, /*!< GPT4 RDC Peripheral. */ + rdcPdapRomcp = 17U, /*!< ROMCP RDC Peripheral. */ + rdcPdapKpp = 18U, /*!< KPP RDC Peripheral. */ + rdcPdapIomuxc = 19U, /*!< IOMUXC RDC Peripheral. */ + rdcPdapIomuxcGpr = 20U, /*!< IOMUXC GPR RDC Peripheral. */ + rdcPdapOcotpCtrl = 21U, /*!< OCOTP CTRL RDC Peripheral. */ + rdcPdapAnatopDig = 22U, /*!< ANATOPDIG RDC Peripheral. */ + rdcPdapSnvs = 23U, /*!< SNVS RDC Peripheral. */ + rdcPdapCcm = 24U, /*!< CCM RDC Peripheral. */ + rdcPdapSrc = 25U, /*!< SRC RDC Peripheral. */ + rdcPdapGpc = 26U, /*!< GPC RDC Peripheral. */ + rdcPdapSemaphore1 = 27U, /*!< SEMAPHORE1 RDC Peripheral. */ + rdcPdapSemaphore2 = 28U, /*!< SEMAPHORE2 RDC Peripheral. */ + rdcPdapRdc = 29U, /*!< RDC RDC Peripheral. */ + rdcPdapCsu = 30U, /*!< CSU RDC Peripheral. */ + rdcPdapReserved1 = 31U, /*!< Reserved1 RDC Peripheral. */ + rdcPdapReserved2 = 32U, /*!< Reserved2 RDC Peripheral. */ + rdcPdapAdc1 = 33U, /*!< ADC1 RDC Peripheral. */ + rdcPdapAdc2 = 34U, /*!< ADC2 RDC Peripheral. */ + rdcPdapEcspi4 = 35U, /*!< ECSPI4 RDC Peripheral. */ + rdcPdapFlexTimer1 = 36U, /*!< FTM1 RDC Peripheral. */ + rdcPdapFlexTimer2 = 37U, /*!< FTM2 RDC Peripheral. */ + rdcPdapPwm1 = 38U, /*!< PWM1 RDC Peripheral. */ + rdcPdapPwm2 = 39U, /*!< PWM2 RDC Peripheral. */ + rdcPdapPwm3 = 40U, /*!< PWM3 RDC Peripheral. */ + rdcPdapPwm4 = 41U, /*!< PWM4 RDC Peripheral. */ + rdcPdapSystemCounterRead = 42U, /*!< System Counter Read RDC Peripheral. */ + rdcPdapSystemCounterCompare = 43U, /*!< System Counter Compare RDC Peripheral. */ + rdcPdapSystemCounterControl = 44U, /*!< System Counter Control RDC Peripheral. */ + rdcPdapPcie = 45U, /*!< PCIE RDC Peripheral. */ + rdcPdapReserved3 = 46U, /*!< Reserved3 RDC Peripheral. */ + rdcPdapEpdc = 47U, /*!< EPDC RDC Peripheral. */ + rdcPdapPxp = 48U, /*!< PXP RDC Peripheral. */ + rdcPdapCsi = 49U, /*!< CSI RDC Peripheral. */ + rdcPdapReserved4 = 50U, /*!< Reserved4 RDC Peripheral. */ + rdcPdapLcdif = 51U, /*!< LCDIF RDC Peripheral. */ + rdcPdapReserved5 = 52U, /*!< Reserved5 RDC Peripheral. */ + rdcPdapMipiCsi = 53U, /*!< MIPI CSI RDC Peripheral. */ + rdcPdapMipiDsi = 54U, /*!< MIPI DSI RDC Peripheral. */ + rdcPdapReserved6 = 55U, /*!< Reserved6 RDC Peripheral. */ + rdcPdapTzasc = 56U, /*!< TZASC RDC Peripheral. */ + rdcPdapDdrPhy = 57U, /*!< DDR PHY RDC Peripheral. */ + rdcPdapDdrc = 58U, /*!< DDRC RDC Peripheral. */ + rdcPdapReserved7 = 59U, /*!< Reserved7 RDC Peripheral. */ + rdcPdapPerfMon1 = 60U, /*!< PerfMon1 RDC Peripheral. */ + rdcPdapPerfMon2 = 61U, /*!< PerfMon2 RDC Peripheral. */ + rdcPdapAxi = 62U, /*!< AXI RDC Peripheral. */ + rdcPdapQosc = 63U, /*!< QOSC RDC Peripheral. */ + rdcPdapFlexCan1 = 64U, /*!< FLEXCAN1 RDC Peripheral. */ + rdcPdapFlexCan2 = 65U, /*!< FLEXCAN2 RDC Peripheral. */ + rdcPdapI2c1 = 66U, /*!< I2C1 RDC Peripheral. */ + rdcPdapI2c2 = 67U, /*!< I2C2 RDC Peripheral. */ + rdcPdapI2c3 = 68U, /*!< I2C3 RDC Peripheral. */ + rdcPdapI2c4 = 69U, /*!< I2C4 RDC Peripheral. */ + rdcPdapUart4 = 70U, /*!< UART4 RDC Peripheral. */ + rdcPdapUart5 = 71U, /*!< UART5 RDC Peripheral. */ + rdcPdapUart6 = 72U, /*!< UART6 RDC Peripheral. */ + rdcPdapUart7 = 73U, /*!< UART7 RDC Peripheral. */ + rdcPdapMuA = 74U, /*!< MUA RDC Peripheral. */ + rdcPdapMuB = 75U, /*!< MUB RDC Peripheral. */ + rdcPdapSemaphoreHs = 76U, /*!< SEMAPHORE HS RDC Peripheral. */ + rdcPdapUsbPl301 = 77U, /*!< USB PL301 RDC Peripheral. */ + rdcPdapReserved8 = 78U, /*!< Reserved8 RDC Peripheral. */ + rdcPdapReserved9 = 79U, /*!< Reserved9 RDC Peripheral. */ + rdcPdapReserved10 = 80U, /*!< Reserved10 RDC Peripheral. */ + rdcPdapUSB1Otg1 = 81U, /*!< USB2 OTG1 RDC Peripheral. */ + rdcPdapUSB2Otg2 = 82U, /*!< USB2 OTG2 RDC Peripheral. */ + rdcPdapUSB3Host = 83U, /*!< USB3 HOST RDC Peripheral. */ + rdcPdapUsdhc1 = 84U, /*!< USDHC1 RDC Peripheral. */ + rdcPdapUsdhc2 = 85U, /*!< USDHC2 RDC Peripheral. */ + rdcPdapUsdhc3 = 86U, /*!< USDHC3 RDC Peripheral. */ + rdcPdapReserved11 = 87U, /*!< Reserved11 RDC Peripheral. */ + rdcPdapReserved12 = 88U, /*!< Reserved12 RDC Peripheral. */ + rdcPdapSim1 = 89U, /*!< SIM1 RDC Peripheral. */ + rdcPdapSim2 = 90U, /*!< SIM2 RDC Peripheral. */ + rdcPdapQspi = 91U, /*!< QSPI RDC Peripheral. */ + rdcPdapWeim = 92U, /*!< WEIM RDC Peripheral. */ + rdcPdapSdma = 93U, /*!< SDMA RDC Peripheral. */ + rdcPdapEnet1 = 94U, /*!< Eneternet1 RDC Peripheral. */ + rdcPdapEnet2 = 95U, /*!< Eneternet2 RDC Peripheral. */ + rdcPdapReserved13 = 96U, /*!< Reserved13 RDC Peripheral. */ + rdcPdapReserved14 = 97U, /*!< Reserved14 RDC Peripheral. */ + rdcPdapEcspi1 = 98U, /*!< ECSPI1 RDC Peripheral. */ + rdcPdapEcspi2 = 99U, /*!< ECSPI2 RDC Peripheral. */ + rdcPdapEcspi3 = 100U, /*!< ECSPI3 RDC Peripheral. */ + rdcPdapReserved15 = 101U, /*!< Reserved15 RDC Peripheral. */ + rdcPdapUart1 = 102U, /*!< UART1 RDC Peripheral. */ + rdcPdapReserved16 = 103U, /*!< Reserved16 RDC Peripheral. */ + rdcPdapUart3 = 104U, /*!< UART3 RDC Peripheral. */ + rdcPdapUart2 = 105U, /*!< UART2 RDC Peripheral. */ + rdcPdapSai1 = 106U, /*!< SAI1 RDC Peripheral. */ + rdcPdapSai2 = 107U, /*!< SAI2 RDC Peripheral. */ + rdcPdapSai3 = 108U, /*!< SAI3 RDC Peripheral. */ + rdcPdapReserved17 = 109U, /*!< Reserved17 RDC Peripheral. */ + rdcPdapReserved18 = 110U, /*!< Reserved18 RDC Peripheral. */ + rdcPdapSpba = 111U, /*!< SPBA RDC Peripheral. */ + rdcPdapDap = 112U, /*!< DAP RDC Peripheral. */ + rdcPdapReserved19 = 113U, /*!< Reserved19 RDC Peripheral. */ + rdcPdapReserved20 = 114U, /*!< Reserved20 RDC Peripheral. */ + rdcPdapReserved21 = 115U, /*!< Reserved21 RDC Peripheral. */ + rdcPdapCaam = 116U, /*!< CAAM RDC Peripheral. */ + rdcPdapReserved22 = 117U, /*!< Reserved22 RDC Peripheral. */ }; -/*! - * @brief RDC memory region - */ -enum _rdc_mr { - rdcMrMmdc = 0U, /* alignment 4096 */ - rdcMrMmdcLast = 7U, /* alignment 4096 */ - rdcMrQspi = 8U, /* alignment 4096 */ - rdcMrQspiLast = 15U, /* alignment 4096 */ - rdcMrWeim = 16U, /* alignment 4096 */ - rdcMrWeimLast = 23U, /* alignment 4096 */ - rdcMrPcie = 24U, /* alignment 4096 */ - rdcMrPcieLast = 31U, /* alignment 4096 */ - rdcMrOcram = 32U, /* alignment 128 */ - rdcMrOcramLast = 36U, /* alignment 128 */ - rdcMrOcramS = 37U, /* alignment 128 */ - rdcMrOcramSLast = 41U, /* alignment 128 */ - rdcMrOcramEpdc = 42U, /* alignment 128 */ - rdcMrOcramEpdcLast = 46U, /* alignment 128 */ - rdcMrOcramPxp = 47U, /* alignment 128 */ - rdcMrOcramPxpLast = 51U /* alignment 128 */ +/*! @brief RDC memory region. */ +enum _rdc_mr +{ + rdcMrMmdc = 0U, /*!< alignment 4096 */ + rdcMrMmdcLast = 7U, /*!< alignment 4096 */ + rdcMrQspi = 8U, /*!< alignment 4096 */ + rdcMrQspiLast = 15U, /*!< alignment 4096 */ + rdcMrWeim = 16U, /*!< alignment 4096 */ + rdcMrWeimLast = 23U, /*!< alignment 4096 */ + rdcMrPcie = 24U, /*!< alignment 4096 */ + rdcMrPcieLast = 31U, /*!< alignment 4096 */ + rdcMrOcram = 32U, /*!< alignment 128 */ + rdcMrOcramLast = 36U, /*!< alignment 128 */ + rdcMrOcramS = 37U, /*!< alignment 128 */ + rdcMrOcramSLast = 41U, /*!< alignment 128 */ + rdcMrOcramEpdc = 42U, /*!< alignment 128 */ + rdcMrOcramEpdcLast = 46U, /*!< alignment 128 */ + rdcMrOcramPxp = 47U, /*!< alignment 128 */ + rdcMrOcramPxpLast = 51U, /*!< alignment 128 */ }; #endif /* __RDC_DEFS_IMX7D__ */ diff --git a/platform/drivers/inc/rdc_semaphore.h b/platform/drivers/inc/rdc_semaphore.h index 7e67e6d..ec990b8 100644 --- a/platform/drivers/inc/rdc_semaphore.h +++ b/platform/drivers/inc/rdc_semaphore.h @@ -43,15 +43,13 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#define RDC_SEMAPHORE_MASTER_NONE (0xFF) +#define RDC_SEMAPHORE_MASTER_NONE (0xFF) -/*! - * @brief RDC SEMAPHORE status return codes. - */ +/*! @brief RDC Semaphore status return codes. */ typedef enum _rdc_semaphore_status { - statusRdcSemaphoreSuccess = 0U, /*!< Success. */ - statusRdcSemaphoreBusy = 1U /*!< RDC semaphore has been locked by other processor. */ + statusRdcSemaphoreSuccess = 0U, /*!< Success. */ + statusRdcSemaphoreBusy = 1U, /*!< RDC semaphore has been locked by other processor. */ } rdc_semaphore_status_t; /******************************************************************************* @@ -70,7 +68,7 @@ extern "C" { /*! * @brief Lock RDC semaphore for shared peripheral access * - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) * @retval statusRdcSemaphoreSuccess Lock the semaphore successfully. * @retval statusRdcSemaphoreBusy Semaphore has been locked by other processor. */ @@ -79,21 +77,21 @@ rdc_semaphore_status_t RDC_SEMAPHORE_TryLock(uint32_t pdap); /*! * @brief Lock RDC semaphore for shared peripheral access, polling until success. * - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) */ void RDC_SEMAPHORE_Lock(uint32_t pdap); /*! * @brief Unlock RDC semaphore * - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) */ void RDC_SEMAPHORE_Unlock(uint32_t pdap); /*! * @brief Get domain ID which locks the semaphore * - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) * @return domain ID which locks the RDC semaphore */ uint32_t RDC_SEMAPHORE_GetLockDomainID(uint32_t pdap); @@ -101,7 +99,7 @@ uint32_t RDC_SEMAPHORE_GetLockDomainID(uint32_t pdap); /*! * @brief Get master index which locks the semaphore * - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) * @return master index which locks the RDC semaphore, or RDC_SEMAPHORE_MASTER_NONE * to indicate it is not locked. */ @@ -117,12 +115,12 @@ uint32_t RDC_SEMAPHORE_GetLockMaster(uint32_t pdap); /*! * @brief Reset RDC semaphore to unlocked status * - * @param pdap RDC peripheral assignment (see _rdc_pdap in rdc_defs_<device>.h) + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_<device>.h) */ void RDC_SEMAPHORE_Reset(uint32_t pdap); /*! - * @brief Reset all RDC semaphors to unlocked status for certain RDC_SEMAPHORE instance + * @brief Reset all RDC semaphore to unlocked status for certain RDC_SEMAPHORE instance * * @param base RDC semaphore base pointer. */ diff --git a/platform/drivers/inc/sema4.h b/platform/drivers/inc/sema4.h index 55ed0e0..cd04c14 100644 --- a/platform/drivers/inc/sema4.h +++ b/platform/drivers/inc/sema4.h @@ -43,48 +43,43 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#define SEMA4_PROCESSOR_NONE (0xFF) -#define SEMA4_GATE_STATUS_FLAG(gate) ((uint16_t)(1U << ((gate) ^ 7))) +#define SEMA4_PROCESSOR_NONE (0xFF) +#define SEMA4_GATE_STATUS_FLAG(gate) ((uint16_t)(1U << ((gate) ^ 7))) -/*! - * @brief Status flag - */ -enum _sema4_status_flag { - sema4StatusFlagGate0 = 1U << 7, - sema4StatusFlagGate1 = 1U << 6, - sema4StatusFlagGate2 = 1U << 5, - sema4StatusFlagGate3 = 1U << 4, - sema4StatusFlagGate4 = 1U << 3, - sema4StatusFlagGate5 = 1U << 2, - sema4StatusFlagGate6 = 1U << 1, - sema4StatusFlagGate7 = 1U << 0, - sema4StatusFlagGate8 = 1U << 15, - sema4StatusFlagGate9 = 1U << 14, - sema4StatusFlagGate10 = 1U << 13, - sema4StatusFlagGate11 = 1U << 12, - sema4StatusFlagGate12 = 1U << 11, - sema4StatusFlagGate13 = 1U << 10, - sema4StatusFlagGate14 = 1U << 9, - sema4StatusFlagGate15 = 1U << 8 +/*! @brief Status flag. */ +enum _sema4_status_flag +{ + sema4StatusFlagGate0 = 1U << 7, /*!< Sema4 Gate 0 flag. */ + sema4StatusFlagGate1 = 1U << 6, /*!< Sema4 Gate 1 flag. */ + sema4StatusFlagGate2 = 1U << 5, /*!< Sema4 Gate 2 flag. */ + sema4StatusFlagGate3 = 1U << 4, /*!< Sema4 Gate 3 flag. */ + sema4StatusFlagGate4 = 1U << 3, /*!< Sema4 Gate 4 flag. */ + sema4StatusFlagGate5 = 1U << 2, /*!< Sema4 Gate 5 flag. */ + sema4StatusFlagGate6 = 1U << 1, /*!< Sema4 Gate 6 flag. */ + sema4StatusFlagGate7 = 1U << 0, /*!< Sema4 Gate 7 flag. */ + sema4StatusFlagGate8 = 1U << 15, /*!< Sema4 Gate 8 flag. */ + sema4StatusFlagGate9 = 1U << 14, /*!< Sema4 Gate 9 flag. */ + sema4StatusFlagGate10 = 1U << 13, /*!< Sema4 Gate 10 flag. */ + sema4StatusFlagGate11 = 1U << 12, /*!< Sema4 Gate 11 flag. */ + sema4StatusFlagGate12 = 1U << 11, /*!< Sema4 Gate 12 flag. */ + sema4StatusFlagGate13 = 1U << 10, /*!< Sema4 Gate 13 flag. */ + sema4StatusFlagGate14 = 1U << 9, /*!< Sema4 Gate 14 flag. */ + sema4StatusFlagGate15 = 1U << 8, /*!< Sema4 Gate 15 flag. */ }; -/*! - * @brief SEMA4 reset finite state machine. - */ +/*! @brief SEMA4 reset finite state machine. */ enum _sema4_reset_state { - sema4ResetIdle = 0U, /*!< Idle, waiting for the first data pattern write. */ - sema4ResetMid = 1U, /*!< Waiting for the second data pattern write. */ - sema4ResetFinished = 2U, /*!< Reset completed. Software could not get this state. */ + sema4ResetIdle = 0U, /*!< Idle, waiting for the first data pattern write. */ + sema4ResetMid = 1U, /*!< Waiting for the second data pattern write. */ + sema4ResetFinished = 2U, /*!< Reset completed. Software can't get this state. */ }; -/*! - * @brief SEMA4 status return codes. - */ +/*! @brief SEMA4 status return codes. */ typedef enum _sema4_status { - statusSema4Success = 0U, /*!< Success. */ - statusSema4Busy = 1U /*!< SEMA4 gate has been locked by other processor. */ + statusSema4Success = 0U, /*!< Success. */ + statusSema4Busy = 1U, /*!< SEMA4 gate has been locked by other processor. */ } sema4_status_t; /******************************************************************************* @@ -101,10 +96,10 @@ extern "C" { */ /*! - * @brief Lock SEMA4 gate for exclusive access between multicore + * @brief Lock SEMA4 gate for exclusive access between multicore. * - * @param base SEMA4 base address - * @param gateIndex SEMA4 gate index + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. * @retval statusSema4Success Lock the gate successfully. * @retval statusSema4Busy SEMA4 gate has been locked by other processor. */ @@ -113,24 +108,24 @@ sema4_status_t SEMA4_TryLock(SEMA4_Type *base, uint32_t gateIndex); /*! * @brief Lock SEMA4 gate for exclusive access between multicore, polling until success. * - * @param base SEMA4 base address - * @param gateIndex SEMA4 gate index + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. */ void SEMA4_Lock(SEMA4_Type *base, uint32_t gateIndex); /*! - * @brief Unlock SEMA4 gate + * @brief Unlock SEMA4 gate. * * @param base SEMA4 base pointer. - * @param gateIndex SEMA4 gate index + * @param gateIndex SEMA4 gate index. */ void SEMA4_Unlock(SEMA4_Type *base, uint32_t gateIndex); /*! - * @brief Get processor number which locks the SEMA4 gate + * @brief Get processor number which locks the SEMA4 gate. * * @param base SEMA4 base pointer. - * @param gateIndex SEMA4 gate index + * @param gateIndex SEMA4 gate index. * @return processor number which locks the SEMA4 gate, or SEMA4_PROCESSOR_NONE * to indicate the gate is not locked. */ @@ -144,15 +139,15 @@ uint32_t SEMA4_GetLockProcessor(SEMA4_Type *base, uint32_t gateIndex); */ /*! - * @brief Reset SEMA4 gate to unlocked status + * @brief Reset SEMA4 gate to unlocked status. * * @param base SEMA4 base pointer. - * @param gateIndex SEMA4 gate index + * @param gateIndex SEMA4 gate index. */ void SEMA4_ResetGate(SEMA4_Type *base, uint32_t gateIndex); /*! - * @brief Reset all SEMA4 gates to unlocked status + * @brief Reset all SEMA4 gates to unlocked status. * * @param base SEMA4 base pointer. */ @@ -160,9 +155,8 @@ void SEMA4_ResetAllGates(SEMA4_Type *base); /*! * @brief Get bus master number which performing the gate reset function. - * - * This function gets the bus master number which performing the gate reset - * function. + * This function gets the bus master number which performing the + * gate reset function. * * @param base SEMA4 base pointer. * @return Bus master number. @@ -174,11 +168,11 @@ static inline uint8_t SEMA4_GetGateResetBus(SEMA4_Type *base) /*! * @brief Get sema4 gate reset state. - * - * This function gets current state of the sema4 reset gate finite state machine. + * This function gets current state of the sema4 reset gate finite + * state machine. * * @param base SEMA4 base pointer. - * @return Current state, see _sema4_reset_state. + * @return Current state (see @ref _sema4_reset_state). */ static inline uint8_t SEMA4_GetGateResetState(SEMA4_Type *base) { @@ -186,15 +180,15 @@ static inline uint8_t SEMA4_GetGateResetState(SEMA4_Type *base) } /*! - * @brief Reset SEMA4 IRQ notification + * @brief Reset SEMA4 IRQ notification. * * @param base SEMA4 base pointer. - * @param gateIndex SEMA4 gate index + * @param gateIndex SEMA4 gate index. */ void SEMA4_ResetNotification(SEMA4_Type *base, uint32_t gateIndex); /*! - * @brief Reset all IRQ notifications + * @brief Reset all IRQ notifications. * * @param base SEMA4 base pointer. */ @@ -202,9 +196,8 @@ void SEMA4_ResetAllNotifications(SEMA4_Type *base); /*! * @brief Get bus master number which performing the notification reset function. - * - * This function gets the bus master number which performing the notification reset - * function. + * This function gets the bus master number which performing the notification + * reset function. * * @param base SEMA4 base pointer. * @return Bus master number. @@ -220,7 +213,7 @@ static inline uint8_t SEMA4_GetNotificationResetBus(SEMA4_Type *base) * This function gets current state of the sema4 reset notification finite state machine. * * @param base SEMA4 base pointer. - * @return Current state, see _sema4_reset_state. + * @return Current state (See @ref _sema4_reset_state). */ static inline uint8_t SEMA4_GetNotificationResetState(SEMA4_Type *base) { @@ -230,7 +223,7 @@ static inline uint8_t SEMA4_GetNotificationResetState(SEMA4_Type *base) /*@}*/ /*! - * @name SEMA4 Interupt and Status Control + * @name SEMA4 Interrupt and Status Control * @{ */ @@ -238,7 +231,7 @@ static inline uint8_t SEMA4_GetNotificationResetState(SEMA4_Type *base) * @brief Get SEMA4 notification status. * * @param base SEMA4 base pointer. - * @param flags SEMA4 gate status mask (see _sema4_status_flag) + * @param flags SEMA4 gate status mask (See @ref _sema4_status_flag). * @return SEMA4 notification status bits. If bit value is set, the corresponding * gate's notification is available. */ @@ -251,9 +244,10 @@ static inline uint16_t SEMA4_GetStatusFlag(SEMA4_Type * base, uint16_t flags) * @brief Enable or disable SEMA4 IRQ notification. * * @param base SEMA4 base pointer. - * @param intMask SEMA4 gate status mask (see _sema4_status_flag) - * @param enable Interrupt enable (true: enable, false: disable), only those gates - * whose intMask is set will be affected. + * @param intMask SEMA4 gate status mask (see @ref _sema4_status_flag). + * @param enable Enable/Disable Sema4 interrupt, only those gates whose intMask is set are affected. + * - true: Enable Sema4 interrupt. + * - false: Disable Sema4 interrupt. */ void SEMA4_SetIntCmd(SEMA4_Type * base, uint16_t intMask, bool enable); @@ -261,7 +255,7 @@ void SEMA4_SetIntCmd(SEMA4_Type * base, uint16_t intMask, bool enable); * @brief check whether SEMA4 IRQ notification enabled. * * @param base SEMA4 base pointer. - * @param flags SEMA4 gate status mask (see _sema4_status_flag) + * @param flags SEMA4 gate status mask (see @ref _sema4_status_flag). * @return SEMA4 notification interrupt enable status bits. If bit value is set, * the corresponding gate's notification is enabled */ diff --git a/platform/drivers/inc/uart_imx.h b/platform/drivers/inc/uart_imx.h index eae3f07..bb204ab 100644 --- a/platform/drivers/inc/uart_imx.h +++ b/platform/drivers/inc/uart_imx.h @@ -48,187 +48,162 @@ /*! @brief Uart module initialize structure. */ typedef struct _uart_init_config { - uint32_t clockRate; /*!< Current UART module clock freq. */ - uint32_t baudRate; /*!< Desired UART baud rate. */ - uint32_t wordLength; /*!< Data bits in one frame. */ - uint32_t stopBitNum; /*!< Number of stop bits in one frame. */ - uint32_t parity; /*!< Parity error check mode of this module. */ - uint32_t direction; /*!< Data transfer direction of this module. */ + uint32_t clockRate; /*!< Current UART module clock freq. */ + uint32_t baudRate; /*!< Desired UART baud rate. */ + uint32_t wordLength; /*!< Data bits in one frame. */ + uint32_t stopBitNum; /*!< Number of stop bits in one frame. */ + uint32_t parity; /*!< Parity error check mode of this module. */ + uint32_t direction; /*!< Data transfer direction of this module. */ } uart_init_config_t; -/*! - * @brief UART number of data bits in a character. - */ +/*! @brief UART number of data bits in a character. */ enum _uart_word_length { - uartWordLength7Bits = 0x0, - uartWordLength8Bits = UART_UCR2_WS_MASK, + uartWordLength7Bits = 0x0, /*!< One character has 7 bits. */ + uartWordLength8Bits = UART_UCR2_WS_MASK, /*!< One character has 8 bits. */ }; -/*! - * @brief UART number of stop bits. - */ +/*! @brief UART number of stop bits. */ enum _uart_stop_bit_num { - uartStopBitNumOne = 0x0, - uartStopBitNumTwo = UART_UCR2_STPB_MASK, + uartStopBitNumOne = 0x0, /*!< One bit Stop. */ + uartStopBitNumTwo = UART_UCR2_STPB_MASK, /*!< Two bits Stop. */ }; -/*! - * @brief UART parity mode. - */ +/*! @brief UART parity mode. */ enum _uart_partity_mode { - uartParityDisable = 0x0, - uartParityEven = UART_UCR2_PREN_MASK, - uartParityOdd = UART_UCR2_PREN_MASK | UART_UCR2_PROE_MASK + uartParityDisable = 0x0, /*!< Parity error check disabled. */ + uartParityEven = UART_UCR2_PREN_MASK, /*!< Even error check is selected. */ + uartParityOdd = UART_UCR2_PREN_MASK | UART_UCR2_PROE_MASK, /*!< Odd error check is selected. */ }; -/*! - * @brief Data transfer direction. - */ +/*! @brief Data transfer direction. */ enum _uart_direction_mode { - uartDirectionDisable = 0x0, - uartDirectionTx = UART_UCR2_TXEN_MASK, - uartDirectionRx = UART_UCR2_RXEN_MASK, - uartDirectionTxRx = UART_UCR2_TXEN_MASK | UART_UCR2_RXEN_MASK + uartDirectionDisable = 0x0, /*!< Both Tx and Rx are disabled. */ + uartDirectionTx = UART_UCR2_TXEN_MASK, /*!< Tx is enabled. */ + uartDirectionRx = UART_UCR2_RXEN_MASK, /*!< Rx is enabled. */ + uartDirectionTxRx = UART_UCR2_TXEN_MASK | UART_UCR2_RXEN_MASK, /*!< Both Tx and Rx are enabled. */ }; -/*! - * @brief This enumeration contains the settings for all of the UART - * interrupt configurations. - */ +/*! @brief This enumeration contains the settings for all of the UART interrupt configurations. */ enum _uart_interrupt { - uartIntAutoBaud = 0x0080000F, - uartIntTxReady = 0x0080000D, - uartIntIdle = 0x0080000C, - uartIntRxReady = 0x00800009, - uartIntTxEmpty = 0x00800006, - uartIntRtsDelta = 0x00800005, - uartIntEscape = 0x0084000F, - uartIntRts = 0x00840004, - uartIntAgingTimer = 0x00840003, - uartIntDtr = 0x0088000D, - uartIntParityError = 0x0088000C, - uartIntFrameError = 0x0088000B, - uartIntDcd = 0x00880009, - uartIntRi = 0x00880008, - uartIntRxDs = 0x00880006, - uartInttAirWake = 0x00880005, - uartIntAwake = 0x00880004, - uartIntDtrDelta = 0x00880003, - uartIntAutoBaudCnt = 0x00880000, - uartIntIr = 0x008C0008, - uartIntWake = 0x008C0007, - uartIntTxComplete = 0x008C0003, - uartIntBreakDetect = 0x008C0002, - uartIntRxOverrun = 0x008C0001, - uartIntRxDataReady = 0x008C0000, - uartIntRs485SlaveAddrMatch = 0x00B80003 + uartIntAutoBaud = 0x0080000F, /*!< Automatic baud rate detection Interrupt Enable. */ + uartIntTxReady = 0x0080000D, /*!< transmitter ready Interrupt Enable. */ + uartIntIdle = 0x0080000C, /*!< IDLE Interrupt Enable. */ + uartIntRxReady = 0x00800009, /*!< Receiver Ready Interrupt Enable. */ + uartIntTxEmpty = 0x00800006, /*!< Transmitter Empty Interrupt Enable. */ + uartIntRtsDelta = 0x00800005, /*!< RTS Delta Interrupt Enable. */ + uartIntEscape = 0x0084000F, /*!< Escape Sequence Interrupt Enable. */ + uartIntRts = 0x00840004, /*!< Request to Send Interrupt Enable. */ + uartIntAgingTimer = 0x00840003, /*!< Aging Timer Interrupt Enable. */ + uartIntDtr = 0x0088000D, /*!< Data Terminal Ready Interrupt Enable. */ + uartIntParityError = 0x0088000C, /*!< Parity Error Interrupt Enable. */ + uartIntFrameError = 0x0088000B, /*!< Frame Error Interrupt Enable. */ + uartIntDcd = 0x00880009, /*!< Data Carrier Detect Interrupt Enable. */ + uartIntRi = 0x00880008, /*!< Ring Indicator Interrupt Enable. */ + uartIntRxDs = 0x00880006, /*!< Receive Status Interrupt Enable. */ + uartInttAirWake = 0x00880005, /*!< Asynchronous IR WAKE Interrupt Enable. */ + uartIntAwake = 0x00880004, /*!< Asynchronous WAKE Interrupt Enable. */ + uartIntDtrDelta = 0x00880003, /*!< Data Terminal Ready Delta Interrupt Enable. */ + uartIntAutoBaudCnt = 0x00880000, /*!< Autobaud Counter Interrupt Enable. */ + uartIntIr = 0x008C0008, /*!< Serial Infrared Interrupt Enable. */ + uartIntWake = 0x008C0007, /*!< WAKE Interrupt Enable. */ + uartIntTxComplete = 0x008C0003, /*!< TransmitComplete Interrupt Enable. */ + uartIntBreakDetect = 0x008C0002, /*!< BREAK Condition Detected Interrupt Enable. */ + uartIntRxOverrun = 0x008C0001, /*!< Receiver Overrun Interrupt Enable. */ + uartIntRxDataReady = 0x008C0000, /*!< Receive Data Ready Interrupt Enable. */ + uartIntRs485SlaveAddrMatch = 0x00B80003, /*!< RS-485 Slave Address Detected Interrupt Enable. */ }; -/*! - * @brief Flag for UART interrupt/DMA status check or polling status. - */ +/*! @brief Flag for UART interrupt/DMA status check or polling status. */ enum _uart_status_flag { - uartStatusRxCharReady = 0x0000000F, - uartStatusRxError = 0x0000000E, - uartStatusRxOverrunError = 0x0000000D, - uartStatusRxFrameError = 0x0000000C, - uartStatusRxBreakDetect = 0x0000000B, - uartStatusRxParityError = 0x0000000A, - uartStatusParityError = 0x0094000F, - uartStatusRtsStatus = 0x0094000E, - uartStatusTxReady = 0x0094000D, - uartStatusRtsDelta = 0x0094000C, - uartStatusEscape = 0x0094000B, - uartStatusFrameError = 0x0094000A, - uartStatusRxReady = 0x00940009, - uartStatusAgingTimer = 0x00940008, - uartStatusDtrDelta = 0x00940007, - uartStatusRxDs = 0x00940006, - uartStatustAirWake = 0x00940005, - uartStatusAwake = 0x00940004, - uartStatusRs485SlaveAddrMatch = 0x00940003, - uartStatusAutoBaud = 0x0098000F, - uartStatusTxEmpty = 0x0098000E, - uartStatusDtr = 0x0098000D, - uartStatusIdle = 0x0098000C, - uartStatusAutoBaudCntStop = 0x0098000B, - uartStatusRiDelta = 0x0098000A, - uartStatusRi = 0x00980009, - uartStatusIr = 0x00980008, - uartStatusWake = 0x00980007, - uartStatusDcdDelta = 0x00980006, - uartStatusDcd = 0x00980005, - uartStatusRts = 0x00980004, - uartStatusTxComplete = 0x00980003, - uartStatusBreakDetect = 0x00980002, - uartStatusRxOverrun = 0x00980001, - uartStatusRxDataReady = 0x00980000 + uartStatusRxCharReady = 0x0000000F, /*!< Rx Character Ready Flag. */ + uartStatusRxError = 0x0000000E, /*!< Rx Error Detect Flag. */ + uartStatusRxOverrunError = 0x0000000D, /*!< Rx Overrun Flag. */ + uartStatusRxFrameError = 0x0000000C, /*!< Rx Frame Error Flag. */ + uartStatusRxBreakDetect = 0x0000000B, /*!< Rx Break Detect Flag. */ + uartStatusRxParityError = 0x0000000A, /*!< Rx Parity Error Flag. */ + uartStatusParityError = 0x0094000F, /*!< Parity Error Interrupt Flag. */ + uartStatusRtsStatus = 0x0094000E, /*!< RTS_B Pin Status Flag. */ + uartStatusTxReady = 0x0094000D, /*!< Transmitter Ready Interrupt/DMA Flag. */ + uartStatusRtsDelta = 0x0094000C, /*!< RTS Delta Flag. */ + uartStatusEscape = 0x0094000B, /*!< Escape Sequence Interrupt Flag. */ + uartStatusFrameError = 0x0094000A, /*!< Frame Error Interrupt Flag. */ + uartStatusRxReady = 0x00940009, /*!< Receiver Ready Interrupt/DMA Flag. */ + uartStatusAgingTimer = 0x00940008, /*!< Ageing Timer Interrupt Flag. */ + uartStatusDtrDelta = 0x00940007, /*!< DTR Delta Flag. */ + uartStatusRxDs = 0x00940006, /*!< Receiver IDLE Interrupt Flag. */ + uartStatustAirWake = 0x00940005, /*!< Asynchronous IR WAKE Interrupt Flag. */ + uartStatusAwake = 0x00940004, /*!< Asynchronous WAKE Interrupt Flag. */ + uartStatusRs485SlaveAddrMatch = 0x00940003, /*!< RS-485 Slave Address Detected Interrupt Flag. */ + uartStatusAutoBaud = 0x0098000F, /*!< Automatic Baud Rate Detect Complete Flag. */ + uartStatusTxEmpty = 0x0098000E, /*!< Transmit Buffer FIFO Empty. */ + uartStatusDtr = 0x0098000D, /*!< DTR edge triggered interrupt flag. */ + uartStatusIdle = 0x0098000C, /*!< Idle Condition Flag. */ + uartStatusAutoBaudCntStop = 0x0098000B, /*!< Autobaud Counter Stopped Flag. */ + uartStatusRiDelta = 0x0098000A, /*!< Ring Indicator Delta Flag. */ + uartStatusRi = 0x00980009, /*!< Ring Indicator Input Flag. */ + uartStatusIr = 0x00980008, /*!< Serial Infrared Interrupt Flag. */ + uartStatusWake = 0x00980007, /*!< Wake Flag. */ + uartStatusDcdDelta = 0x00980006, /*!< Data Carrier Detect Delta Flag. */ + uartStatusDcd = 0x00980005, /*!< Data Carrier Detect Input Flag. */ + uartStatusRts = 0x00980004, /*!< RTS Edge Triggered Interrupt Flag. */ + uartStatusTxComplete = 0x00980003, /*!< Transmitter Complete Flag. */ + uartStatusBreakDetect = 0x00980002, /*!< BREAK Condition Detected Flag. */ + uartStatusRxOverrun = 0x00980001, /*!< Overrun Error Flag. */ + uartStatusRxDataReady = 0x00980000, /*!< Receive Data Ready Flag. */ }; -/*! - * @brief The events will generate DMA Request. - */ +/*! @brief The events generate the DMA Request. */ enum _uart_dma { - uartDmaRxReady = 0x00800008, - uartDmaTxReady = 0x00800003, - uartDmaAgingTimer = 0x00800002, - uartDmaIdle = 0x008C0006 + uartDmaRxReady = 0x00800008, /*!< Receive Ready DMA Enable. */ + uartDmaTxReady = 0x00800003, /*!< Transmitter Ready DMA Enable. */ + uartDmaAgingTimer = 0x00800002, /*!< Aging DMA Timer Enable. */ + uartDmaIdle = 0x008C0006, /*!< DMA IDLE Condition Detected Interrupt Enable. */ }; -/*! - * @brief RTS pin interrupt trigger edge. - */ +/*! @brief RTS pin interrupt trigger edge. */ enum _uart_rts_int_trigger_edge { - uartRtsTriggerEdgeRising = UART_UCR2_RTEC(0), - uartRtsTriggerEdgeFalling = UART_UCR2_RTEC(1), - uartRtsTriggerEdgeBoth = UART_UCR2_RTEC(2) + uartRtsTriggerEdgeRising = UART_UCR2_RTEC(0), /*!< RTS pin interrupt triggered on rising edge. */ + uartRtsTriggerEdgeFalling = UART_UCR2_RTEC(1), /*!< RTS pin interrupt triggered on falling edge. */ + uartRtsTriggerEdgeBoth = UART_UCR2_RTEC(2), /*!< RTS pin interrupt triggered on both edge. */ }; -/*! - * @brief UART module modem role selections. - */ +/*! @brief UART module modem role selections. */ enum _uart_modem_mode { - uartModemModeDce = 0, - uartModemModeDte = UART_UFCR_DCEDTE_MASK + uartModemModeDce = 0, /*!< UART module works as DCE. */ + uartModemModeDte = UART_UFCR_DCEDTE_MASK, /*!< UART module works as DTE. */ }; -/*! - * @brief DTR pin interrupt trigger edge. - */ +/*! @brief DTR pin interrupt trigger edge. */ enum _uart_dtr_int_trigger_edge { - uartDtrTriggerEdgeRising = UART_UCR3_DPEC(0), - uartDtrTriggerEdgeFalling = UART_UCR3_DPEC(1), - uartDtrTriggerEdgeBoth = UART_UCR3_DPEC(2) + uartDtrTriggerEdgeRising = UART_UCR3_DPEC(0), /*!< DTR pin interrupt triggered on rising edge. */ + uartDtrTriggerEdgeFalling = UART_UCR3_DPEC(1), /*!< DTR pin interrupt triggered on falling edge. */ + uartDtrTriggerEdgeBoth = UART_UCR3_DPEC(2), /*!< DTR pin interrupt triggered on both edge. */ }; -/*! - * @brief IrDA vote clock selections. - */ +/*! @brief IrDA vote clock selections. */ enum _uart_irda_vote_clock { - uartIrdaVoteClockSampling = 0x0, - uartIrdaVoteClockReference = UART_UCR4_IRSC_MASK + uartIrdaVoteClockSampling = 0x0, /*!< The vote logic uses the sampling clock (16x baud rate) for normal operation. */ + uartIrdaVoteClockReference = UART_UCR4_IRSC_MASK, /*!< The vote logic uses the UART reference clock. */ }; -/*! - * @brief UART module Rx Idle condition selections. - */ +/*! @brief UART module Rx Idle condition selections. */ enum _uart_rx_idle_condition { - uartRxIdleMoreThan4Frames = UART_UCR1_ICD(0), - uartRxIdleMoreThan8Frames = UART_UCR1_ICD(1), - uartRxIdleMoreThan16Frames = UART_UCR1_ICD(2), - uartRxIdleMoreThan32Frames = UART_UCR1_ICD(3), + uartRxIdleMoreThan4Frames = UART_UCR1_ICD(0), /*!< Idle for more than 4 frames. */ + uartRxIdleMoreThan8Frames = UART_UCR1_ICD(1), /*!< Idle for more than 8 frames. */ + uartRxIdleMoreThan16Frames = UART_UCR1_ICD(2), /*!< Idle for more than 16 frames. */ + uartRxIdleMoreThan32Frames = UART_UCR1_ICD(3), /*!< Idle for more than 32 frames. */ }; /******************************************************************************* @@ -248,12 +223,12 @@ extern "C" { * @brief Initialize UART module with given initialize structure. * * @param base UART base pointer. - * @param initConfig UART initialize structure(see uart_init_config_t above). + * @param initConfig UART initialize structure (see @ref uart_init_config_t structure above). */ -void UART_Init(UART_Type* base, uart_init_config_t* initConfig); +void UART_Init(UART_Type* base, const uart_init_config_t* initConfig); /*! - * @brief This function reset Uart module register content to its default value. + * @brief This function reset UART module register content to its default value. * * @param base UART base pointer. */ @@ -292,26 +267,28 @@ void UART_SetBaudRate(UART_Type* base, uint32_t clockRate, uint32_t baudRate); * @brief This function is used to set the transform direction of UART Module. * * @param base UART base pointer. - * @param direction UART transfer direction(see _uart_direction_mode enumeration above). + * @param direction UART transfer direction (see @ref _uart_direction_mode enumeration). */ static inline void UART_SetDirMode(UART_Type* base, uint32_t direction) { assert((direction & uartDirectionTx) || (direction & uartDirectionRx)); + UART_UCR2_REG(base) = (UART_UCR2_REG(base) & ~(UART_UCR2_RXEN_MASK | UART_UCR2_TXEN_MASK)) | direction; } /*! * @brief This function is used to set the number of frames RXD is allowed to * be idle before an idle condition is reported. The available condition - * can be select from _uart_idle_condition enumeration. + * can be select from @ref _uart_idle_condition enumeration. * * @param base UART base pointer. * @param idleCondition The condition that an idle condition is reported - * (see _uart_idle_condition enumeration above). + * (see @ref _uart_idle_condition enumeration). */ static inline void UART_SetRxIdleCondition(UART_Type* base, uint32_t idleCondition) { assert(idleCondition <= uartRxIdleMoreThan32Frames); + UART_UCR1_REG(base) = (UART_UCR1_REG(base) & ~UART_UCR1_ICD_MASK) | idleCondition; } @@ -320,7 +297,7 @@ static inline void UART_SetRxIdleCondition(UART_Type* base, uint32_t idleConditi * of Tx and Rx can be set separately. * * @param base UART base pointer. - * @param direction UART transfer direction(see _uart_direction_mode enumeration above). + * @param direction UART transfer direction (see @ref _uart_direction_mode enumeration). * @param invert Set true to invert the polarity of UART signal. */ void UART_SetInvertCmd(UART_Type* base, uint32_t direction, bool invert); @@ -336,7 +313,9 @@ void UART_SetInvertCmd(UART_Type* base, uint32_t direction, bool invert); * @brief This function is used to set UART enable condition in the DOZE state. * * @param base UART base pointer. - * @param enable Set true to enable UART module in doze mode. + * @param enable Enable/Disable UART module in doze mode. + * - true: Enable UART module in doze mode. + * - false: Disable UART module in doze mode. */ void UART_SetDozeMode(UART_Type* base, bool enable); @@ -344,7 +323,9 @@ void UART_SetDozeMode(UART_Type* base, bool enable); * @brief This function is used to set UART enable condition of the UART low power feature. * * @param base UART base pointer. - * @param enable Set true to enable UART module low power feature. + * @param enable Enable/Disable UART module low power feature. + * - true: Enable UART module low power feature. + * - false: Disable UART module low power feature. */ void UART_SetLowPowerMode(UART_Type* base, bool enable); @@ -360,7 +341,7 @@ void UART_SetLowPowerMode(UART_Type* base, bool enable); * A independent 9 Bits RS-485 send data function is provided. * * @param base UART base pointer. - * @param data Data to be set through Uart module. + * @param data Data to be set through UART module. */ static inline void UART_Putchar(UART_Type* base, uint8_t data) { @@ -389,18 +370,20 @@ static inline uint8_t UART_Getchar(UART_Type* base) /*! * @brief This function is used to set the enable condition of * specific UART interrupt source. The available interrupt - * source can be select from uart_interrupt enumeration. + * source can be select from @ref _uart_interrupt enumeration. * * @param base UART base pointer. * @param intSource Available interrupt source for this module. - * @param enable Set true to enable corresponding interrupt. + * @param enable Enable/Disable corresponding interrupt. + * - true: Enable corresponding interrupt. + * - false: Disable corresponding interrupt. */ void UART_SetIntCmd(UART_Type* base, uint32_t intSource, bool enable); /*! * @brief This function is used to get the current status of specific * UART status flag(including interrupt flag). The available - * status flag can be select from _uart_status_flag enumeration. + * status flag can be select from @ref _uart_status_flag enumeration. * * @param base UART base pointer. * @param flag Status flag to check. @@ -411,7 +394,7 @@ bool UART_GetStatusFlag(UART_Type* base, uint32_t flag); /*! * @brief This function is used to get the current status * of specific UART status flag. The available status - * flag can be select from _uart_status_flag enumeration. + * flag can be select from @ref _uart_status_flag enumeration. * * @param base UART base pointer. * @param flag Status flag to clear. @@ -428,11 +411,13 @@ void UART_ClearStatusFlag(UART_Type* base, uint32_t flag); /*! * @brief This function is used to set the enable condition of * specific UART DMA source. The available DMA source - * can be select from _uart_dma enumeration. + * can be select from @ref _uart_dma enumeration. * * @param base UART base pointer. * @param dmaSource The Event that can generate DMA request. - * @param enable Set true to enable corresponding DMA source. + * @param enable Enable/Disable corresponding DMA source. + * - true: Enable corresponding DMA source. + * - false: Disable corresponding DMA source. */ void UART_SetDmaCmd(UART_Type* base, uint32_t dmaSource, bool enable); @@ -483,14 +468,16 @@ static inline void UART_SetRxFifoWatermark(UART_Type* base, uint8_t watermark) * Hardware flow control. * * @param base UART base pointer. - * @param enable Set true to enable RTS hardware flow control. + * @param enable Enable/Disbale RTS hardware flow control. + * - true: Enable RTS hardware flow control. + * - false: Disbale RTS hardware flow control. */ void UART_SetRtsFlowCtrlCmd(UART_Type* base, bool enable); /*! * @brief This function is used to set the RTS interrupt trigger edge. * The available trigger edge can be select from - * _uart_rts_trigger_edge enumeration. + * @ref _uart_rts_trigger_edge enumeration. * * @param base UART base pointer. * @param triggerEdge Available RTS pin interrupt trigger edge. @@ -507,12 +494,14 @@ static inline void UART_SetRtsIntTriggerEdge(UART_Type* base, uint32_t triggerEd /*! * @brief This function is used to set the enable condition of CTS - * auto control. if CTS control is enabled, the CTS_B pin will - * be controlled by the receiver, otherwise the CTS_B pin will + * auto control. if CTS control is enabled, the CTS_B pin + * is controlled by the receiver, otherwise the CTS_B pin is * controlled by UART_CTSPinCtrl function. * * @param base UART base pointer. - * @param enable Set true to enable CTS auto control. + * @param enable Enable/Disable CTS auto control. + * - true: Enable CTS auto control. + * - false: Disable CTS auto control. */ void UART_SetCtsFlowCtrlCmd(UART_Type* base, bool enable); @@ -523,14 +512,15 @@ void UART_SetCtsFlowCtrlCmd(UART_Type* base, bool enable); * The CTS_B pin is high(inactive) * * @param base UART base pointer. - * @param active Set true: the CTS_B pin active; - * Set false: the CTS_B pin inactive. + * @param active The CTS_B pin state to set. + * - true: the CTS_B pin active; + * - false: the CTS_B pin inactive. */ void UART_SetCtsPinLevel(UART_Type* base, bool active); /*! * @brief This function is used to set the auto CTS_B pin control - * trigger level. The CTS_B pin will be de-asserted when + * trigger level. The CTS_B pin is de-asserted when * Rx FIFO reach CTS trigger level. * * @param base UART base pointer. @@ -547,23 +537,24 @@ static inline void UART_SetCtsTriggerLevel(UART_Type* base, uint8_t triggerLevel * in RS-232 communication. * * @param base UART base pointer. - * @param mode The role(DTE/DCE) of UART module(see _uart_modem_mode enumeration above). + * @param mode The role(DTE/DCE) of UART module (see @ref _uart_modem_mode enumeration). */ void UART_SetModemMode(UART_Type* base, uint32_t mode); /*! * @brief This function is used to set the edge of DTR_B (DCE) or - * DSR_B (DTE) on which an interrupt will be generated. + * DSR_B (DTE) on which an interrupt is generated. * * @param base UART base pointer. - * @param triggerEdge The trigger edge on which an interrupt will be generated. - * (see _uart_dtr_trigger_edge enumeration above) + * @param triggerEdge The trigger edge on which an interrupt is generated + * (see @ref _uart_dtr_trigger_edge enumeration above). */ static inline void UART_SetDtrIntTriggerEdge(UART_Type* base, uint32_t triggerEdge) { assert((triggerEdge == uartDtrTriggerEdgeRising) || \ (triggerEdge == uartDtrTriggerEdgeFalling) || \ (triggerEdge == uartDtrTriggerEdgeBoth)); + UART_UCR3_REG(base) = (UART_UCR3_REG(base) & ~UART_UCR3_DPEC_MASK) | triggerEdge; } @@ -572,8 +563,9 @@ static inline void UART_SetDtrIntTriggerEdge(UART_Type* base, uint32_t triggerEd * or DTR pin(for DTE mode) for the modem interface. * * @param base UART base pointer. - * @param active Set true: DSR/DTR pin is logic one. - * Set false: DSR/DTR pin is logic zero. + * @param active The state of DSR pin. + * - true: DSR/DTR pin is logic one. + * - false: DSR/DTR pin is logic zero. */ void UART_SetDtrPinLevel(UART_Type* base, bool active); @@ -582,8 +574,9 @@ void UART_SetDtrPinLevel(UART_Type* base, bool active); * DCD pin. THIS FUNCTION IS FOR DCE MODE ONLY. * * @param base UART base pointer. - * @param active Set true: DCD_B pin is logic one (DCE mode) - * Set false: DCD_B pin is logic zero (DCE mode) + * @param active The state of DCD pin. + * - true: DCD_B pin is logic one (DCE mode) + * - false: DCD_B pin is logic zero (DCE mode) */ void UART_SetDcdPinLevel(UART_Type* base, bool active); @@ -592,15 +585,16 @@ void UART_SetDcdPinLevel(UART_Type* base, bool active); * RI pin. THIS FUNCTION IS FOR DCE MODE ONLY. * * @param base UART base pointer. - * @param active Set true: RI_B pin is logic one (DCE mode) - * Set false: RI_B pin is logic zero (DCE mode) + * @param active The state of RI pin. + * - true: RI_B pin is logic one (DCE mode) + * - false: RI_B pin is logic zero (DCE mode) */ void UART_SetRiPinLevel(UART_Type* base, bool active); /*@}*/ /*! - * @name Multi-processor and RS-485 functions. + * @name Multiprocessor and RS-485 functions. * @{ */ @@ -609,7 +603,7 @@ void UART_SetRiPinLevel(UART_Type* base, bool active); * RS-485 Multidrop mode. * * @param base UART base pointer. - * @param data Data(9 bits) to be set through uart module. + * @param data Data(9 bits) to be set through UART module. */ void UAER_Putchar9(UART_Type* base, uint16_t data); @@ -627,7 +621,9 @@ uint16_t UAER_Getchar9(UART_Type* base); * 9-Bits data or Multidrop mode. * * @param base UART base pointer. - * @param enable Set true to enable Multidrop mode. + * @param enable Enable/Disable Multidrop mode. + * - true: Enable Multidrop mode. + * - false: Disable Multidrop mode. */ void UART_SetMultidropMode(UART_Type* base, bool enable); @@ -636,13 +632,15 @@ void UART_SetMultidropMode(UART_Type* base, bool enable); * Automatic Address Detect Mode. * * @param base UART base pointer. - * @param enable Set true to enable Automatic Address Detect mode. + * @param enable Enable/Disable Automatic Address Detect mode. + * - true: Enable Automatic Address Detect mode. + * - false: Disable Automatic Address Detect mode. */ void UART_SetSlaveAddressDetectCmd(UART_Type* base, bool enable); /*! * @brief This function is used to set the slave address char - * that the receiver will try to detect. + * that the receiver tries to detect. * * @param base UART base pointer. * @param slaveAddress The slave to detect. @@ -665,14 +663,16 @@ static inline void UART_SetSlaveAddress(UART_Type* base, uint8_t slaveAddress) * IrDA Mode. * * @param base UART base pointer. - * @param enable Set true to enable IrDA mode. + * @param enable Enable/Disable IrDA mode. + * - true: Enable IrDA mode. + * - false: Disable IrDA mode. */ void UART_SetIrDACmd(UART_Type* base, bool enable); /*! * @brief This function is used to set the clock for the IR pulsed * vote logic. The available clock can be select from - * _uart_irda_vote_clock enumeration. + * @ref _uart_irda_vote_clock enumeration. * * @param base UART base pointer. * @param voteClock The available IrDA vote clock selection. @@ -691,7 +691,9 @@ void UART_SetIrDAVoteClock(UART_Type* base, uint32_t voteClock); * Automatic Baud Rate Detection feature. * * @param base UART base pointer. - * @param enable Set true to enable Automatic Baud Rate Detection feature. + * @param enable Enable/Disable Automatic Baud Rate Detection feature. + * - true: Enable Automatic Baud Rate Detection feature. + * - false: Disable Automatic Baud Rate Detection feature. */ void UART_SetAutoBaudRateCmd(UART_Type* base, bool enable); @@ -715,16 +717,19 @@ static inline uint16_t UART_ReadBaudRateCount(UART_Type* base) * * @param base UART base pointer. * @param active Asserted high to generate BREAK. + * - true: Generate BREAK character. + * - false: Stop generate BREAK character. */ void UART_SendBreakChar(UART_Type* base, bool active); /*! - * @brief This function is used to send BREAK character.It is - * important that SNDBRK is asserted high for a sufficient - * period of time to generate a valid BREAK. + * @brief This function is used to Enable/Disable the Escape + * Sequence Decection feature. * * @param base UART base pointer. - * @param active Asserted high to generate BREAK. + * @param enable Enable/Disable Escape Sequence Decection. + * - true: Enable Escape Sequence Decection. + * - false: Disable Escape Sequence Decection. */ void UART_SetEscapeDecectCmd(UART_Type* base, bool enable); diff --git a/platform/drivers/inc/wdog_imx.h b/platform/drivers/inc/wdog_imx.h index 42b982e..8b053df 100644 --- a/platform/drivers/inc/wdog_imx.h +++ b/platform/drivers/inc/wdog_imx.h @@ -44,16 +44,22 @@ /******************************************************************************* * Definitions ******************************************************************************/ -/*! - * @brief Structure to configure the running mode. - */ -typedef struct WdogModeConfig +/*! @brief The reset source of latest reset. */ +enum _wdog_reset_source +{ + wdogResetSourcePor = WDOG_WRSR_POR_MASK, /*!< Indicates the reset is the result of a power on reset.*/ + wdogResetSourceTimeout = WDOG_WRSR_TOUT_MASK, /*!< Indicates the reset is the result of a WDOG timeout.*/ + wdogResetSourceSwRst = WDOG_WRSR_SFTW_MASK, /*!< Indicates the reset is the result of a software reset.*/ +}; + +/*! @brief Structure to configure the running mode. */ +typedef struct _wdog_init_config { - bool wdw; /*!< true: suspend in low power wait, false: not suspend */ - bool wdt; /*!< true: assert WDOG_B when timeout, false: not assert WDOG_B */ - bool wdbg; /*!< true: suspend in debug mode, false: not suspend */ - bool wdzst; /*!< true: suspend in doze and stop mode, false: not suspend */ -} wdog_mode_config_t; + bool wdw; /*!< true: suspend in low power wait, false: not suspend */ + bool wdt; /*!< true: assert WDOG_B when timeout, false: not assert WDOG_B */ + bool wdbg; /*!< true: suspend in debug mode, false: not suspend */ + bool wdzst; /*!< true: suspend in doze and stop mode, false: not suspend */ +} wdog_init_config_t; /******************************************************************************* * API @@ -69,17 +75,17 @@ extern "C" { */ /*! - * @brief Configure WDOG funtions, call once only + * @brief Configure WDOG functions, call once only * * @param base WDOG base pointer. - * @param config WDOG mode configuration + * @param initConfig WDOG mode configuration */ -static inline void WDOG_Init(WDOG_Type *base, wdog_mode_config_t *config) +static inline void WDOG_Init(WDOG_Type *base, const wdog_init_config_t *initConfig) { - base->WCR |= config->wdw ? WDOG_WCR_WDW_MASK : 0 | - config->wdt ? WDOG_WCR_WDT_MASK : 0 | - config->wdbg ? WDOG_WCR_WDBG_MASK : 0 | - config->wdzst ? WDOG_WCR_WDZST_MASK : 0; + base->WCR |= (initConfig->wdw ? WDOG_WCR_WDW_MASK : 0) | + (initConfig->wdt ? WDOG_WCR_WDT_MASK : 0) | + (initConfig->wdbg ? WDOG_WCR_WDBG_MASK : 0) | + (initConfig->wdzst ? WDOG_WCR_WDZST_MASK : 0); } /*! @@ -94,12 +100,28 @@ void WDOG_Enable(WDOG_Type *base, uint8_t timeout); * @brief Assert WDOG software reset signal * * @param base WDOG base pointer. - * @param wda WDOG reset (true: assert WDOG_B, false: no impact on WDOG_B) - * @param srs System reset (true: assert system reset WDOG_RESET_B_DEB, false: no impact on system reset) + * @param wda WDOG reset. + * - true: Assert WDOG_B. + * - false: No impact on WDOG_B. + * @param srs System reset. + * - true: Assert system reset WDOG_RESET_B_DEB. + * - false: No impact on system reset. */ void WDOG_Reset(WDOG_Type *base, bool wda, bool srs); /*! + * @brief Get the latest reset source generated due to + * WatchDog Timer. + * + * @param base WDOG base pointer. + * @return The latest reset source (see @ref _wdog_reset_source enumeration). + */ +static inline uint32_t WDOG_GetResetSource(WDOG_Type *base) +{ + return base->WRSR; +} + +/*! * @brief Refresh the WDOG to prevent timeout * * @param base WDOG base pointer. @@ -138,7 +160,9 @@ static inline void WDOG_EnableInt(WDOG_Type *base, uint8_t time) * @brief Check whether WDOG interrupt is pending * * @param base WDOG base pointer. - * @return WDOG interrupt status (true: pending, false: not pending) + * @return WDOG interrupt status. + * - true: Pending. + * - false: Not pending. */ static inline bool WDOG_IsIntPending(WDOG_Type *base) { diff --git a/platform/drivers/src/adc_imx7d.c b/platform/drivers/src/adc_imx7d.c index 37d98d3..e69ac0b 100644 --- a/platform/drivers/src/adc_imx7d.c +++ b/platform/drivers/src/adc_imx7d.c @@ -44,7 +44,7 @@ * structure. * *END**************************************************************************/ -void ADC_Init(ADC_Type* base, adc_init_config_t* initConfig) +void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig) { assert(initConfig); @@ -81,20 +81,20 @@ void ADC_Deinit(ADC_Type* base) /* Reset ADC Module Register content to default value */ ADC_CH_A_CFG1_REG(base) = 0x0; - ADC_CH_A_CFG2_REG(base) = 0x8000; + ADC_CH_A_CFG2_REG(base) = ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; ADC_CH_B_CFG1_REG(base) = 0x0; - ADC_CH_B_CFG2_REG(base) = 0x8000; + ADC_CH_B_CFG2_REG(base) = ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; ADC_CH_C_CFG1_REG(base) = 0x0; - ADC_CH_C_CFG2_REG(base) = 0x8000; + ADC_CH_C_CFG2_REG(base) = ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; ADC_CH_D_CFG1_REG(base) = 0x0; - ADC_CH_D_CFG2_REG(base) = 0x8000; + ADC_CH_D_CFG2_REG(base) = ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; ADC_CH_SW_CFG_REG(base) = 0x0; ADC_TIMER_UNIT_REG(base) = 0x0; - ADC_DMA_FIFO_REG(base) = 0xF; + ADC_DMA_FIFO_REG(base) = ADC_DMA_FIFO_DMA_WM_LVL(0xF); ADC_INT_SIG_EN_REG(base) = 0x0; ADC_INT_EN_REG(base) = 0x0; ADC_INT_STATUS_REG(base) = 0x0; - ADC_ADC_CFG_REG(base) = 0x1; + ADC_ADC_CFG_REG(base) = ADC_ADC_CFG_ADC_EN_MASK; } /*FUNCTION********************************************************************** @@ -177,10 +177,10 @@ void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown) /*FUNCTION********************************************************************** * * Function Name : ADC_LogicChInit - * Description : Initialize ADC Logic channel with initialize structure. + * Description : Initialize ADC Logic channel with initialization structure. * *END**************************************************************************/ -void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, adc_logic_ch_init_config_t* chInitConfig) +void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfig) { assert(chInitConfig); @@ -427,16 +427,20 @@ void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable) switch (logicCh) { case adcLogicChA: - ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_EN_MASK; + ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SINGLE_MASK) | + ADC_CH_A_CFG1_CHA_EN_MASK; break; case adcLogicChB: - ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_EN_MASK; + ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SINGLE_MASK) | + ADC_CH_B_CFG1_CHB_EN_MASK; break; case adcLogicChC: - ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_EN_MASK; + ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SINGLE_MASK) | + ADC_CH_C_CFG1_CHC_EN_MASK; break; case adcLogicChD: - ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_EN_MASK; + ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SINGLE_MASK) | + ADC_CH_D_CFG1_CHD_EN_MASK; break; default: break; @@ -467,7 +471,7 @@ void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable) /*FUNCTION********************************************************************** * * Function Name : ADC_TriggerSingleConvert - * Description : Trigger single time convert on target logic channel. + * Description : Trigger single time convert on the target logic channel. * *END**************************************************************************/ void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh) @@ -477,16 +481,16 @@ void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh) switch (logicCh) { case adcLogicChA: - ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_SINGLE_MASK; + ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_SINGLE_MASK | ADC_CH_A_CFG1_CHA_EN_MASK; break; case adcLogicChB: - ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_SINGLE_MASK; + ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_SINGLE_MASK | ADC_CH_B_CFG1_CHB_EN_MASK; break; case adcLogicChC: - ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_SINGLE_MASK; + ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_SINGLE_MASK | ADC_CH_C_CFG1_CHC_EN_MASK; break; case adcLogicChD: - ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_SINGLE_MASK; + ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_SINGLE_MASK | ADC_CH_D_CFG1_CHD_EN_MASK; break; case adcLogicChSW: ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_START_CONV_MASK; @@ -498,6 +502,39 @@ void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh) /*FUNCTION********************************************************************** * + * Function Name : ADC_StopConvert + * Description : Stop current convert on the target logic channel. + * + *END**************************************************************************/ +void ADC_StopConvert(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK; + break; + case adcLogicChSW: + /* Wait until ADC conversion finish. */ + while (ADC_CH_SW_CFG_REG(base) & ADC_CH_SW_CFG_START_CONV_MASK); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * * Function Name : ADC_GetConvertResult * Description : Get 12-bit length right aligned convert result. * diff --git a/platform/drivers/src/ccm_analog_imx7d.c b/platform/drivers/src/ccm_analog_imx7d.c index 3493690..0264202 100644 --- a/platform/drivers/src/ccm_analog_imx7d.c +++ b/platform/drivers/src/ccm_analog_imx7d.c @@ -36,6 +36,20 @@ /*FUNCTION********************************************************************** * + * Function Name : CCM_ANALOG_GetArmPllFreq + * Description : Get ARM PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetArmPllFreq(CCM_ANALOG_Type * base) +{ + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllArmControl)) + return 24000000ul; + + return 12000000ul * (CCM_ANALOG_PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK); +} + +/*FUNCTION********************************************************************** + * * Function Name : CCM_ANALOG_GetSysPllFreq * Description : Get system PLL frequency * @@ -43,12 +57,193 @@ uint32_t CCM_ANALOG_GetSysPllFreq(CCM_ANALOG_Type * base) { if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPll480Control)) - return 24000000; + return 24000000ul; if (CCM_ANALOG_PLL_480 & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) - return 528000000; + return 528000000ul; + else + return 480000000ul; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetDdrPllFreq + * Description : Get DDR PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetDdrPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllDdrControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG) & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK; + divTestSelect = (CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG) & CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT; + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_DDR_SS_REG(base) & CCM_ANALOG_PLL_DDR_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_DDR_SS_REG(base) & CCM_ANALOG_PLL_DDR_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_DDR_DENOM_REG(base) & CCM_ANALOG_PLL_DDR_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_DDR_NUM_REG(base) & CCM_ANALOG_PLL_DDR_NUM_A_MASK)); + return (uint32_t)((24000000ul >> divTestSelect) * (divSelect + factor)); + } + else + { + return (24000000ul >> divTestSelect) * divSelect; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetEnetPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetEnetPllFreq(CCM_ANALOG_Type * base) +{ + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllEnetControl)) + return 24000000ul; + + return 1000000000ul; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetAudioPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetAudioPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divPostSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllAudioControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK; + divPostSelect = (CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) >> + CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT; + divTestSelect = (CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT; + + switch (divPostSelect) + { + case 0x0: + case 0x2: + divPostSelect = 0; + break; + case 0x1: + divPostSelect = 1; + break; + case 0x3: + divPostSelect = 2; + break; + } + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_AUDIO_SS_REG(base) & CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_AUDIO_SS_REG(base) & CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_AUDIO_NUM_REG(base) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)); + return (uint32_t)(((24000000ul >> divTestSelect) >> divPostSelect) * (divSelect + factor)); + } + else + { + return ((24000000ul >> divTestSelect) >> divPostSelect) * divSelect; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetVideoPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetVideoPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divPostSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllVideoControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK; + divPostSelect = (CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) >> + CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT; + divTestSelect = (CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT; + + switch (divPostSelect) + { + case 0x0: + case 0x2: + divPostSelect = 0; + break; + case 0x1: + divPostSelect = 1; + break; + case 0x3: + divPostSelect = 2; + break; + } + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_VIDEO_SS_REG(base) & CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_VIDEO_SS_REG(base) & CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_VIDEO_NUM_REG(base) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)); + return (uint32_t)(((24000000ul >> divTestSelect) >> divPostSelect) * (divSelect + factor)); + } else - return 480000000; + { + return ((24000000ul >> divTestSelect) >> divPostSelect) * divSelect; + } } /*FUNCTION********************************************************************** diff --git a/platform/drivers/src/ccm_imx7d.c b/platform/drivers/src/ccm_imx7d.c index 55015d3..11f2889 100644 --- a/platform/drivers/src/ccm_imx7d.c +++ b/platform/drivers/src/ccm_imx7d.c @@ -46,8 +46,8 @@ void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t pre, uint32_ assert (post < 64); CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & - (~(CCM_TARGET_ROOT0_PRE_PODF_MASK | CCM_TARGET_ROOT0_POST_PODF_MASK))) | - CCM_TARGET_ROOT0_PRE_PODF(pre) | CCM_TARGET_ROOT0_POST_PODF(post); + (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) | + CCM_TARGET_ROOT_PRE_PODF(pre) | CCM_TARGET_ROOT_POST_PODF(post); } /*FUNCTION********************************************************************** @@ -60,8 +60,8 @@ void CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t *pre, uint32 { assert (pre && post); - *pre = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT0_PRE_PODF_MASK) >> CCM_TARGET_ROOT0_PRE_PODF_SHIFT; - *post = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT0_POST_PODF_MASK) >> CCM_TARGET_ROOT0_POST_PODF_SHIFT; + *pre = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT; + *post = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT; } /*FUNCTION********************************************************************** @@ -76,8 +76,8 @@ void CCM_UpdateRoot(CCM_Type * base, uint32_t ccmRoot, uint32_t mux, uint32_t pr assert (post < 64); CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & - (~(CCM_TARGET_ROOT0_MUX_MASK | CCM_TARGET_ROOT0_PRE_PODF_MASK | CCM_TARGET_ROOT0_POST_PODF_MASK))) | - CCM_TARGET_ROOT0_MUX(mux) | CCM_TARGET_ROOT0_PRE_PODF(pre) | CCM_TARGET_ROOT0_POST_PODF(post); + (~(CCM_TARGET_ROOT_MUX_MASK | CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) | + CCM_TARGET_ROOT_MUX(mux) | CCM_TARGET_ROOT_PRE_PODF(pre) | CCM_TARGET_ROOT_POST_PODF(post); } /******************************************************************************* diff --git a/platform/drivers/src/ecspi.c b/platform/drivers/src/ecspi.c index bdf4aa8..cfba518 100644 --- a/platform/drivers/src/ecspi.c +++ b/platform/drivers/src/ecspi.c @@ -35,41 +35,41 @@ ******************************************************************************/ /******************************************************************************* - * ECSPI Initialization and Configuration functions + * eCSPI Initialization and Configuration functions ******************************************************************************/ /*FUNCTION********************************************************************** * * Function Name : ECSPI_Init - * Description : Initializes the ECSPI module according to the specified - * parameters in the initStruct. + * Description : Initializes the eCSPI module according to the specified + * parameters in the initConfig. * *END**************************************************************************/ -void ECSPI_Init(ECSPI_Type* base, ecspi_init_t* initStruct) +void ECSPI_Init(ECSPI_Type* base, const ecspi_init_config_t* initConfig) { - /* Disable ECSPI module */ + /* Disable eCSPI module */ ECSPI_CONREG_REG(base) = 0; - /* Enable the ECSPI module before write to other registers */ + /* Enable the eCSPI module before write to other registers */ ECSPI_Enable(base); - /* ECSPI CONREG Configuration */ - ECSPI_CONREG_REG(base) |= ECSPI_CONREG_BURST_LENGTH(initStruct->burstLength) | - ECSPI_CONREG_CHANNEL_SELECT(initStruct->channelSelect); - ECSPI_CONREG_REG(base) |= initStruct->ecspiAutoStart ? ECSPI_CONREG_SMC_MASK : 0; + /* eCSPI CONREG Configuration */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_BURST_LENGTH(initConfig->burstLength) | + ECSPI_CONREG_CHANNEL_SELECT(initConfig->channelSelect); + ECSPI_CONREG_REG(base) |= initConfig->ecspiAutoStart ? ECSPI_CONREG_SMC_MASK : 0; - /* ECSPI CONFIGREG Configuration */ - ECSPI_CONFIGREG_REG(base) = ECSPI_CONFIGREG_SCLK_PHA(((initStruct->clockPhase) & 1) << (initStruct->channelSelect)) | - ECSPI_CONFIGREG_SCLK_POL(((initStruct->clockPolarity) & 1) << (initStruct->channelSelect)); + /* eCSPI CONFIGREG Configuration */ + ECSPI_CONFIGREG_REG(base) = ECSPI_CONFIGREG_SCLK_PHA(((initConfig->clockPhase) & 1) << (initConfig->channelSelect)) | + ECSPI_CONFIGREG_SCLK_POL(((initConfig->clockPolarity) & 1) << (initConfig->channelSelect)); /* Master or Slave mode Configuration */ - if(initStruct->mode == ecspiMasterMode) + if(initConfig->mode == ecspiMasterMode) { /* Set baud rate in bits per second */ - ECSPI_CONREG_REG(base) |= ECSPI_CONREG_CHANNEL_MODE(1 << (initStruct->channelSelect)); - ECSPI_SetBaudRate(base, initStruct->clockRate, initStruct->baudRate); + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_CHANNEL_MODE(1 << (initConfig->channelSelect)); + ECSPI_SetBaudRate(base, initConfig->clockRate, initConfig->baudRate); } else - ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_CHANNEL_MODE(1 << (initStruct->channelSelect)); + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_CHANNEL_MODE(1 << (initConfig->channelSelect)); } /*FUNCTION********************************************************************** @@ -90,7 +90,7 @@ void ECSPI_SetSampClockSource(ECSPI_Type* base, uint32_t source) /*FUNCTION********************************************************************** * * Function Name : ECSPI_SetBaudRate - * Description : Calculated the ECSPI baud rate in bits per second. + * Description : Calculated the eCSPI baud rate in bits per second. * *END**************************************************************************/ uint32_t ECSPI_SetBaudRate(ECSPI_Type* base, uint32_t sourceClockInHz, uint32_t bitsPerSec) @@ -188,7 +188,7 @@ void ECSPI_SetFIFOThreshold(ECSPI_Type* base, uint32_t fifo, uint32_t threshold) /*FUNCTION********************************************************************** * * Function Name : ECSPI_SetIntCmd - * Description : Enable or disable ECSPI interrupts. + * Description : Enable or disable eCSPI interrupts. * *END**************************************************************************/ void ECSPI_SetIntCmd(ECSPI_Type* base, uint32_t flags, bool enable) diff --git a/platform/drivers/src/flexcan.c b/platform/drivers/src/flexcan.c index 25177ad..2fb1d16 100644 --- a/platform/drivers/src/flexcan.c +++ b/platform/drivers/src/flexcan.c @@ -89,7 +89,7 @@ static void FLEXCAN_ExitFreezeMode(CAN_Type* base) /* De-assert Freeze Mode */ CAN_MCR_REG(base) &= ~CAN_MCR_HALT_MASK; CAN_MCR_REG(base) &= ~CAN_MCR_FRZ_MASK; - /* Wait for entering the freeze mode */ + /* Wait for exit the freeze mode */ while (CAN_MCR_REG(base) & CAN_MCR_FRZ_ACK_MASK); } @@ -102,7 +102,7 @@ static void FLEXCAN_ExitFreezeMode(CAN_Type* base) * Description : Initialize Flexcan module with given initialize structure. * *END**************************************************************************/ -void FLEXCAN_Init(CAN_Type* base, flexcan_init_config_t* initConfig) +void FLEXCAN_Init(CAN_Type* base, const flexcan_init_config_t* initConfig) { assert(initConfig); @@ -136,6 +136,8 @@ void FLEXCAN_Init(CAN_Type* base, flexcan_init_config_t* initConfig) *END**************************************************************************/ void FLEXCAN_Deinit(CAN_Type* base) { + uint32_t i; + /* Reset the FLEXCAN module */ CAN_MCR_REG(base) |= CAN_MCR_SOFT_RST_MASK; /* Wait for reset cycle to complete */ @@ -150,8 +152,17 @@ void FLEXCAN_Deinit(CAN_Type* base) /* Reset CTRL2 Register */ CAN_CTRL2_REG(base) = 0x0; + /* Reset All Message Buffer Content */ + for (i = 0; i < CAN_CS_COUNT; i++) + { + base->MB[i].CS = 0x0; + base->MB[i].ID = 0x0; + base->MB[i].WORD0 = 0x0; + base->MB[i].WORD1 = 0x0; + } + /* Reset Rx Individual Mask */ - for (uint8_t i=0; i < CAN_RXIMR_COUNT; i++) + for (i = 0; i < CAN_RXIMR_COUNT; i++) CAN_RXIMR_REG(base, i) = 0x0; /* Reset Rx Mailboxes Global Mask */ @@ -167,8 +178,8 @@ void FLEXCAN_Deinit(CAN_Type* base) CAN_RXFGMASK_REG(base) = 0xFFFFFFFF; /* Disable all MB interrupts */ - CAN_IMASK1_REG(base) = 0X0; - CAN_IMASK2_REG(base) = 0X0; + CAN_IMASK1_REG(base) = 0x0; + CAN_IMASK2_REG(base) = 0x0; // Clear all MB interrupt flags CAN_IFLAG1_REG(base) = 0xFFFFFFFF; @@ -215,7 +226,7 @@ void FLEXCAN_Disable(CAN_Type* base) * Description : Sets the FlexCAN time segments for setting up bit rate. * *END**************************************************************************/ -void FLEXCAN_SetTiming(CAN_Type* base, flexcan_timing_t* timing) +void FLEXCAN_SetTiming(CAN_Type* base, const flexcan_timing_t* timing) { assert(timing); @@ -288,15 +299,6 @@ void FLEXCAN_SetMaxMsgBufNum(CAN_Type* base, uint32_t bufNum) /* Set the maximum number of MBs*/ CAN_MCR_REG(base) = (CAN_MCR_REG(base) & (~CAN_MCR_MAXMB_MASK)) | CAN_MCR_MAXMB(bufNum-1); - /* Clean MBs content to default value */ - for (uint8_t i = 0; i < bufNum; i++) - { - base->MB[i].CS = 0x0; - base->MB[i].ID = 0x0; - base->MB[i].WORD0 = 0x0; - base->MB[i].WORD1 = 0x0; - } - /* De-assert Freeze Mode*/ FLEXCAN_ExitFreezeMode(base); } @@ -491,14 +493,17 @@ void FLEXCAN_ClearMsgBufStatusFlag(CAN_Type* base, uint32_t msgBufIdx) assert(msgBufIdx < CAN_CS_COUNT); if (msgBufIdx > 0x31) + { index = msgBufIdx - 32; + /* write 1 to clear. */ + base->IFLAG2 = 0x1 << index; + } else + { index = msgBufIdx; - - /* The Interrupt flag must be cleared by writing it to '1'. - * Writing '0' has no effect. - */ - base->IFLAG1 = 0x1 << index; + /* write 1 to clear. */ + base->IFLAG1 = 0x1 << index; + } } /*FUNCTION********************************************************************** @@ -693,7 +698,7 @@ void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table switch (idFormat) { - case flexcanFxFifoIdElementFormatA: + case flexcanRxFifoIdElementFormatA: /* One full ID (standard and extended) per ID Filter Table element.*/ if (idFilterTable->isRemoteFrame) { @@ -718,7 +723,7 @@ void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table } } break; - case flexcanFxFifoIdElementFormatB: + case flexcanRxFifoIdElementFormatB: /* Two full standard IDs or two partial 14-bit (standard and extended) IDs*/ /* per ID Filter Table element.*/ if (idFilterTable->isRemoteFrame) @@ -754,7 +759,7 @@ void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table j = j + 2; } break; - case flexcanFxFifoIdElementFormatC: + case flexcanRxFifoIdElementFormatC: /* Four partial 8-bit Standard IDs per ID Filter Table element.*/ j = 0; for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++) @@ -774,7 +779,7 @@ void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table j = j + 4; } break; - case flexcanFxFifoIdElementFormatD: + case flexcanRxFifoIdElementFormatD: /* All frames rejected.*/ break; } @@ -835,7 +840,7 @@ void FLEXCAN_SetRxMaskMode(CAN_Type* base, uint32_t mode) * Description : Set the remote trasmit request mask enablement. * *END**************************************************************************/ -void FLEXCAN_SetRxMaskRtrCmd(CAN_Type* base, uint32_t enable) +void FLEXCAN_SetRxMaskRtrCmd(CAN_Type* base, bool enable) { /* Assert Freeze mode */ FLEXCAN_EnterFreezeMode(base); diff --git a/platform/drivers/src/gpio_imx.c b/platform/drivers/src/gpio_imx.c index 9029876..ffefaf2 100644 --- a/platform/drivers/src/gpio_imx.c +++ b/platform/drivers/src/gpio_imx.c @@ -41,10 +41,10 @@ * * Function Name : GPIO_Init * Description : Initializes the GPIO module according to the specified - * parameters in the initStruct. + * parameters in the initConfig. * *END**************************************************************************/ -void GPIO_Init(GPIO_Type* base, gpio_init_t* initStruct) +void GPIO_Init(GPIO_Type* base, const gpio_init_config_t* initConfig) { uint32_t pin; volatile uint32_t *icr; @@ -54,10 +54,10 @@ void GPIO_Init(GPIO_Type* base, gpio_init_t* initStruct) GPIO_EDGE_SEL_REG(base) = 0; /* Get pin number */ - pin = initStruct->pin; + pin = initConfig->pin; /* Configure GPIO pin direction */ - if (initStruct->direction == gpioDigitalOutput) + if (initConfig->direction == gpioDigitalOutput) GPIO_GDIR_REG(base) |= (1U << pin); else GPIO_GDIR_REG(base) &= ~(1U << pin); @@ -70,7 +70,7 @@ void GPIO_Init(GPIO_Type* base, gpio_init_t* initStruct) icr = &GPIO_ICR2_REG(base); pin -= 16; } - switch(initStruct->interruptMode) + switch(initConfig->interruptMode) { case(gpioIntLowLevel): { @@ -127,12 +127,13 @@ void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal /*FUNCTION********************************************************************** * * Function Name : GPIO_SetPinIntMode - * Description : Disable or enable the specific pin interrupt. + * Description : Enable or Disable the specific pin interrupt. * *END**************************************************************************/ void GPIO_SetPinIntMode(GPIO_Type* base, uint32_t pin, bool enable) { assert(pin < 32); + if(enable) GPIO_IMR_REG(base) |= (1U << pin); else @@ -142,13 +143,14 @@ void GPIO_SetPinIntMode(GPIO_Type* base, uint32_t pin, bool enable) /*FUNCTION********************************************************************** * * Function Name : GPIO_SetIntEdgeSelect - * Description : Disable or enable the specific pin interrupt. + * Description : Enable or Disable the specific pin interrupt. * *END**************************************************************************/ void GPIO_SetIntEdgeSelect(GPIO_Type* base, uint32_t pin, bool enable) { assert(pin < 32); + if(enable) GPIO_EDGE_SEL_REG(base) |= (1U << pin); else diff --git a/platform/drivers/src/gpt.c b/platform/drivers/src/gpt.c index a9c8a21..6c6d12c 100644 --- a/platform/drivers/src/gpt.c +++ b/platform/drivers/src/gpt.c @@ -40,20 +40,20 @@ * Description : Initialize GPT to reset state and initialize running mode * *END**************************************************************************/ -void GPT_Init(GPT_Type * base, gpt_mode_config_t *config) +void GPT_Init(GPT_Type* base, const gpt_init_config_t* initConfig) { - assert(config); + assert(initConfig); base->CR = 0; GPT_SoftReset(base); - base->CR = (config->freeRun ? GPT_CR_FRR_MASK : 0) | - (config->waitEnable ? GPT_CR_WAITEN_MASK : 0) | - (config->stopEnable ? GPT_CR_STOPEN_MASK : 0) | - (config->dozeEnable ? GPT_CR_DOZEEN_MASK : 0) | - (config->dbgEnable ? GPT_CR_DBGEN_MASK : 0) | - (config->enableMode ? GPT_CR_ENMOD_MASK : 0); + base->CR = (initConfig->freeRun ? GPT_CR_FRR_MASK : 0) | + (initConfig->waitEnable ? GPT_CR_WAITEN_MASK : 0) | + (initConfig->stopEnable ? GPT_CR_STOPEN_MASK : 0) | + (initConfig->dozeEnable ? GPT_CR_DOZEEN_MASK : 0) | + (initConfig->dbgEnable ? GPT_CR_DBGEN_MASK : 0) | + (initConfig->enableMode ? GPT_CR_ENMOD_MASK : 0); } /*FUNCTION********************************************************************** @@ -62,14 +62,14 @@ void GPT_Init(GPT_Type * base, gpt_mode_config_t *config) * Description : Set clock source of GPT * *END**************************************************************************/ -void GPT_SetClockSource(GPT_Type * base, uint32_t source) +void GPT_SetClockSource(GPT_Type* base, uint32_t source) { assert(source <= gptClockSourceOsc); if (source == gptClockSourceOsc) - base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_ENABLE_24MHZ_MASK | GPT_CR_CLKSRC(source); + base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(source); else - base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_ENABLE_24MHZ_MASK)) | GPT_CR_CLKSRC(source); + base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(source); } /*FUNCTION********************************************************************** @@ -78,7 +78,7 @@ void GPT_SetClockSource(GPT_Type * base, uint32_t source) * Description : Enable or disable GPT interrupts * *END**************************************************************************/ -void GPT_SetIntCmd(GPT_Type * base, uint32_t flags, bool enable) +void GPT_SetIntCmd(GPT_Type* base, uint32_t flags, bool enable) { if (enable) base->IR |= flags; diff --git a/platform/drivers/src/i2c_imx.c b/platform/drivers/src/i2c_imx.c index 9475c15..e6f5664 100644 --- a/platform/drivers/src/i2c_imx.c +++ b/platform/drivers/src/i2c_imx.c @@ -57,7 +57,7 @@ static const uint32_t i2cClkDivTab[][2] = * Description : Initialize I2C module with given initialize structure. * *END**************************************************************************/ -void I2C_Init(I2C_Type* base, i2c_init_config_t* initConfig) +void I2C_Init(I2C_Type* base, const i2c_init_config_t* initConfig) { assert(initConfig); diff --git a/platform/drivers/src/lmem.c b/platform/drivers/src/lmem.c new file mode 100644 index 0000000..d3ed88a --- /dev/null +++ b/platform/drivers/src/lmem.c @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "lmem.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define LMEM_CACHE_LINE_SIZE 32 + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * System Cache control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_EnableSystemCache + * Description : This function enable the System Cache. + * + *END**************************************************************************/ +void LMEM_EnableSystemCache(LMEM_Type *base) +{ + /* set command to invalidate all ways */ + /* and write GO bit to initiate command */ + LMEM_PSCCR_REG(base) = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); + + /* Enable cache, enable write buffer */ + LMEM_PSCCR_REG(base) = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_DisableSystemCache + * Description : This function disable the System Cache. + * + *END**************************************************************************/ +void LMEM_DisableSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) = 0x0; + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCache + * Description : This function flush the System Cache. + * + *END**************************************************************************/ +void LMEM_FlushSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK ; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCacheLine + * Description : This function is called to push a line out of the System Cache. + * + *END**************************************************************************/ +static void LMEM_FlushSystemCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address >= 0x20000000); + + /* Invalidate by physical address */ + LMEM_PSCLCR_REG(base) = LMEM_PSCLCR_LADSEL_MASK | LMEM_PSCLCR_LCMD(2); + /* Set physical address and activate command */ + LMEM_PSCSAR_REG(base) = ((uint32_t)address & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCSAR_REG(base) & LMEM_PSCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCacheLines + * Description : This function is called to flush the System Cache by + * performing cache copy-backs. It must determine how + * many cache lines need to be copied back and then + * perform the copy-backs. + * + *END**************************************************************************/ +void LMEM_FlushSystemCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + + address = (void *) ((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + do + { + LMEM_FlushSystemCacheLine(base, address); + address = (void *) ((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCache + * Description : This function invalidate the System Cache. + * + *END**************************************************************************/ +void LMEM_InvalidateSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCacheLine + * Description : This function is called to invalidate a line out of + * the System Cache. + * + *END**************************************************************************/ +static void LMEM_InvalidateSystemCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address >= 0x20000000); + + /* Invalidate by physical address */ + LMEM_PSCLCR_REG(base) = LMEM_PSCLCR_LADSEL_MASK | LMEM_PSCLCR_LCMD(1); + /* Set physical address and activate command */ + LMEM_PSCSAR_REG(base) = ((uint32_t)address & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCSAR_REG(base) & LMEM_PSCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCacheLines + * Description : This function is responsible for performing an data + * cache invalidate. It must determine how many cache + * lines need to be invalidated and then perform the + * invalidation. + * + *END**************************************************************************/ +void LMEM_InvalidateSystemCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + address = (void *)((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + + do + { + LMEM_InvalidateSystemCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_EnableCodeCache + * Description : This function enable the Code Cache. + * + *END**************************************************************************/ +void LMEM_EnableCodeCache(LMEM_Type *base) +{ + /* set command to invalidate all ways, enable write buffer */ + /* and write GO bit to initiate command */ + LMEM_PCCCR_REG(base) = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); + + /* Enable cache, enable write buffer */ + LMEM_PCCCR_REG(base) = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_DisableCodeCache + * Description : This function disable the Code Cache. + * + *END**************************************************************************/ +void LMEM_DisableCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) = 0x0; + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCache + * Description : This function flush the Code Cache. + * + *END**************************************************************************/ +void LMEM_FlushCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCacheLine + * Description : This function is called to push a line out of the + * Code Cache. + * + *END**************************************************************************/ +static void LMEM_FlushCodeCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address < 0x20000000); + + /* Invalidate by physical address */ + LMEM_PCCLCR_REG(base) = LMEM_PCCLCR_LADSEL_MASK | LMEM_PCCLCR_LCMD(2); + /* Set physical address and activate command */ + LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCSAR_REG(base) & LMEM_PCCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCacheLines + * Description : This function is called to flush the instruction + * cache by performing cache copy-backs. It must + * determine how many cache lines need to be copied + * back and then perform the copy-backs. + * + *END**************************************************************************/ +void LMEM_FlushCodeCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + + address = (void *) ((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + do + { + LMEM_FlushCodeCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCache + * Description : This function invalidate the Code Cache. + * + *END**************************************************************************/ +void LMEM_InvalidateCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCacheLine + * Description : This function is called to invalidate a line out + * of the Code Cache. + * + *END**************************************************************************/ +static void LMEM_InvalidateCodeCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address < 0x20000000); + + /* Invalidate by physical address */ + LMEM_PCCLCR_REG(base) = LMEM_PCCLCR_LADSEL_MASK | LMEM_PCCLCR_LCMD(1); + /* Set physical address and activate command */ + LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCSAR_REG(base) & LMEM_PCCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCacheLines + * Description : This function is responsible for performing an + * Code Cache invalidate. It must determine + * how many cache lines need to be invalidated and then + * perform the invalidation. + * + *END**************************************************************************/ +void LMEM_InvalidateCodeCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + address = (void *)((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + + do + { + LMEM_InvalidateCodeCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); + __ISB(); + __DSB(); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/platform/drivers/src/uart_imx.c b/platform/drivers/src/uart_imx.c index f86d559..0f78265 100644 --- a/platform/drivers/src/uart_imx.c +++ b/platform/drivers/src/uart_imx.c @@ -44,7 +44,7 @@ * initialize structure. * *END**************************************************************************/ -void UART_Init(UART_Type* base, uart_init_config_t* initConfig) +void UART_Init(UART_Type* base, const uart_init_config_t* initConfig) { assert(initConfig); @@ -85,16 +85,18 @@ void UART_Deinit(UART_Type* base) UART_UCR1_REG(base) &= ~UART_UCR1_UARTEN_MASK; /* Reset UART Module Register content to default value */ - UART_UCR1_REG(base) = 0x00000000; - UART_UCR2_REG(base) = 0x00000001; - UART_UCR3_REG(base) = 0x00000700; - UART_UCR4_REG(base) = 0x00008000; - UART_UFCR_REG(base) = 0x00000801; - UART_UESC_REG(base) = 0x0000002B; - UART_UTIM_REG(base) = 0x00000000; - UART_ONEMS_REG(base) = 0x00000000; - UART_UTS_REG(base) = 0x00000060; - UART_UMCR_REG(base) = 0x00000000; + UART_UCR1_REG(base) = 0x0; + UART_UCR2_REG(base) = UART_UCR2_SRST_MASK; + UART_UCR3_REG(base) = UART_UCR3_DSR_MASK | + UART_UCR3_DCD_MASK | + UART_UCR3_RI_MASK; + UART_UCR4_REG(base) = UART_UCR4_CTSTL(32); + UART_UFCR_REG(base) = UART_UFCR_TXTL(2) | UART_UFCR_RXTL(1); + UART_UESC_REG(base) = UART_UESC_ESC_CHAR(0x2B); + UART_UTIM_REG(base) = 0x0; + UART_ONEMS_REG(base) = 0x0; + UART_UTS_REG(base) = UART_UTS_TXEMPTY_MASK | UART_UTS_RXEMPTY_MASK; + UART_UMCR_REG(base) = 0x0; /* Reset the transmit and receive state machines, all FIFOs and register * USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD and UTS[6-3]. */ @@ -179,7 +181,7 @@ void UART_SetBaudRate(UART_Type* base, uint32_t clockRate, uint32_t baudRate) UART_UFCR_REG(base) |= UART_UFCR_RFDIV(refFreqDiv); UART_UBIR_REG(base) = UART_UBIR_INC(denominator - 1); UART_UBMR_REG(base) = UART_UBMR_MOD(numerator / divider - 1); - UART_ONEMS_REG(base) = UART_ONEMS_ONEMS(clockRate/(1000 * refFreqDiv)); + UART_ONEMS_REG(base) = UART_ONEMS_ONEMS(clockRate/(1000 * divider)); } /*FUNCTION********************************************************************** @@ -301,7 +303,7 @@ void UART_ClearStatusFlag(UART_Type* base, uint32_t flag) uart_mask = (1 << (flag & 0x0000FFFF)); /* write 1 to clear. */ - *uart_reg |= uart_mask; + *uart_reg = uart_mask; } /******************************************************************************* @@ -443,7 +445,7 @@ void UART_SetRiPinLevel(UART_Type* base, bool active) } /******************************************************************************* - * Multi-processor and RS-485 functions + * Multiprocessor and RS-485 functions ******************************************************************************/ /*FUNCTION********************************************************************** * @@ -472,11 +474,17 @@ void UAER_Putchar9(UART_Type* base, uint16_t data) *END**************************************************************************/ uint16_t UAER_Getchar9(UART_Type* base) { - uint16_t rxData = 0; + uint16_t rxData = UART_URXD_REG(base); + + if (rxData & UART_URXD_PRERR_MASK) + { + rxData = (rxData & 0x00FF) | 0x0100; + } + else + { + rxData &= 0x00FF; + } - if (UART_URXD_REG(base) & UART_URXD_PRERR_MASK) - rxData |= 0x0100; - rxData |= (UART_URXD_REG(base) & UART_URXD_RX_DATA_MASK); return rxData; } diff --git a/platform/utilities/inc/debug_console_imx.h b/platform/utilities/inc/debug_console_imx.h index 21069b8..6779e67 100644 --- a/platform/utilities/inc/debug_console_imx.h +++ b/platform/utilities/inc/debug_console_imx.h @@ -76,11 +76,11 @@ extern "C" { */ /*! - * @brief Init the UART_IMX used for debug messages. + * @brief Initialize the UART_IMX used for debug messages. * * Call this function to enable debug log messages to be output via the specified UART_IMX * base address and at the specified baud rate. Just initializes the UART_IMX to the given baud - * rate and 8N1. After this function has returned, stdout and stdin will be connected to the + * rate and 8N1. After this function has returned, stdout and stdin are connected to the * selected UART_IMX. The debug_printf() function also uses this UART_IMX. * * @param base Which UART_IMX instance is used to send debug messages. @@ -95,7 +95,7 @@ debug_console_status_t DbgConsole_Init(UART_Type* base, uint32_t mode); /*! - * @brief Deinit the UART/LPUART used for debug messages. + * @brief Deinitialize the UART/LPUART used for debug messages. * * Call this function to disable debug log messages to be output via the specified UART/LPUART * base address and at the specified baud rate. diff --git a/platform/utilities/src/debug_console_imx.c b/platform/utilities/src/debug_console_imx.c index 93c9a3c..a03e441 100644 --- a/platform/utilities/src/debug_console_imx.c +++ b/platform/utilities/src/debug_console_imx.c @@ -366,6 +366,7 @@ void UART_SendDataPolling(void *base, const uint8_t *txBuff, uint32_t txSize) while (txSize--) { UART_Putchar((UART_Type*)base, *txBuff++); + while (!UART_GetStatusFlag((UART_Type*)base, uartStatusTxEmpty)); while (!UART_GetStatusFlag((UART_Type*)base, uartStatusTxComplete)); } } diff --git a/platform/utilities/src/print_scan.c b/platform/utilities/src/print_scan.c index 01667af..6c09099 100644 --- a/platform/utilities/src/print_scan.c +++ b/platform/utilities/src/print_scan.c @@ -756,7 +756,7 @@ static int32_t mkfloatnumstr (char *numstr, void *nump, int32_t radix, uint32_t for (i = 0; i < precision_width; i++) { fb = fa / (int32_t)radix; - c = (int32_t)(fa - (uint64_t)fb * (int32_t)radix); + c = (int32_t)(fa - (int64_t)fb * (int32_t)radix); if (c < 0) { c = ~c + 1 + '0'; @@ -771,20 +771,28 @@ static int32_t mkfloatnumstr (char *numstr, void *nump, int32_t radix, uint32_t *nstrp++ = (char)'.'; ++nlen; a = (int32_t)intpart; - while (a != 0) + if(a == 0) { - b = (int32_t)a / (int32_t)radix; - c = (int32_t)a - ((int32_t)b * (int32_t)radix); - if (c < 0) - { - c = ~c + 1 + '0'; - }else + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) { - c = c + '0'; + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + c = ~c + 1 + '0'; + }else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; } - a = b; - *nstrp++ = (char)c; - ++nlen; } done: return nlen; |